diff options
Diffstat (limited to 'arch/ppc')
32 files changed, 3243 insertions, 249 deletions
diff --git a/arch/ppc/Kconfig b/arch/ppc/Kconfig index 11899f06bf0..54a0a9bb12d 100644 --- a/arch/ppc/Kconfig +++ b/arch/ppc/Kconfig @@ -481,6 +481,53 @@ config WINCEPT endchoice +menu "Freescale Ethernet driver platform-specific options" + depends on FS_ENET + + config MPC8xx_SECOND_ETH + bool "Second Ethernet channel" + depends on (MPC885ADS || MPC86XADS) + default y + help + This enables support for second Ethernet on MPC885ADS and MPC86xADS boards. + The latter will use SCC1, for 885ADS you can select it below. + + choice + prompt "Second Ethernet channel" + depends on MPC8xx_SECOND_ETH + default MPC8xx_SECOND_ETH_FEC2 + + config MPC8xx_SECOND_ETH_FEC2 + bool "FEC2" + depends on MPC885ADS + help + Enable FEC2 to serve as 2-nd Ethernet channel. Note that SMC2 + (often 2-nd UART) will not work if this is enabled. + + config MPC8xx_SECOND_ETH_SCC1 + bool "SCC1" + depends on MPC86XADS + select MPC8xx_SCC_ENET_FIXED + help + Enable SCC1 to serve as 2-nd Ethernet channel. Note that SMC1 + (often 1-nd UART) will not work if this is enabled. + + config MPC8xx_SECOND_ETH_SCC3 + bool "SCC3" + depends on MPC885ADS + help + Enable SCC3 to serve as 2-nd Ethernet channel. Note that SMC1 + (often 1-nd UART) will not work if this is enabled. + + endchoice + + config MPC8xx_SCC_ENET_FIXED + depends on MPC8xx_SECOND_ETH_SCC + default n + bool "Use fixed MII-less mode for SCC Ethernet" + +endmenu + choice prompt "Machine Type" depends on 6xx || POWER3 diff --git a/arch/ppc/Kconfig.debug b/arch/ppc/Kconfig.debug index 61653cb60c4..8cc75abf3d8 100644 --- a/arch/ppc/Kconfig.debug +++ b/arch/ppc/Kconfig.debug @@ -67,7 +67,7 @@ config SERIAL_TEXT_DEBUG config PPC_OCP bool - depends on IBM_OCP || XILINX_OCP + depends on IBM_OCP default y endmenu diff --git a/arch/ppc/boot/common/ns16550.c b/arch/ppc/boot/common/ns16550.c index 26818bbb6cf..4f00c93ac87 100644 --- a/arch/ppc/boot/common/ns16550.c +++ b/arch/ppc/boot/common/ns16550.c @@ -8,6 +8,9 @@ #include <linux/serial_reg.h> #include <asm/serial.h> +#if defined(CONFIG_XILINX_VIRTEX) +#include <platforms/4xx/xparameters/xparameters.h> +#endif #include "nonstdio.h" #include "serial.h" diff --git a/arch/ppc/boot/simple/Makefile b/arch/ppc/boot/simple/Makefile index 9533f8de238..28be01b99c4 100644 --- a/arch/ppc/boot/simple/Makefile +++ b/arch/ppc/boot/simple/Makefile @@ -192,6 +192,7 @@ boot-$(CONFIG_8xx) += embed_config.o boot-$(CONFIG_8260) += embed_config.o boot-$(CONFIG_EP405) += embed_config.o boot-$(CONFIG_XILINX_ML300) += embed_config.o +boot-$(CONFIG_XILINX_ML403) += embed_config.o boot-$(CONFIG_BSEIP) += iic.o boot-$(CONFIG_MBX) += iic.o pci.o qspan_pci.o boot-$(CONFIG_MV64X60) += misc-mv64x60.o diff --git a/arch/ppc/boot/simple/embed_config.c b/arch/ppc/boot/simple/embed_config.c index 491a691d10c..3a51b106294 100644 --- a/arch/ppc/boot/simple/embed_config.c +++ b/arch/ppc/boot/simple/embed_config.c @@ -21,6 +21,9 @@ #ifdef CONFIG_40x #include <asm/io.h> #endif +#ifdef CONFIG_XILINX_VIRTEX +#include <platforms/4xx/xparameters/xparameters.h> +#endif extern unsigned long timebase_period_ns; /* For those boards that don't provide one. @@ -742,7 +745,7 @@ embed_config(bd_t **bdp) } #endif /* WILLOW */ -#ifdef CONFIG_XILINX_ML300 +#if defined(CONFIG_XILINX_ML300) || defined(CONFIG_XILINX_ML403) void embed_config(bd_t ** bdp) { @@ -779,7 +782,7 @@ embed_config(bd_t ** bdp) timebase_period_ns = 1000000000 / bd->bi_tbfreq; /* see bi_tbfreq definition in arch/ppc/platforms/4xx/xilinx_ml300.h */ } -#endif /* CONFIG_XILINX_ML300 */ +#endif /* CONFIG_XILINX_ML300 || CONFIG_XILINX_ML403 */ #ifdef CONFIG_IBM_OPENBIOS /* This could possibly work for all treeboot roms. diff --git a/arch/ppc/boot/simple/head.S b/arch/ppc/boot/simple/head.S index 5e4adc298bf..119b9dc8958 100644 --- a/arch/ppc/boot/simple/head.S +++ b/arch/ppc/boot/simple/head.S @@ -65,6 +65,13 @@ start_: */ #endif +#if defined(CONFIG_XILINX_VIRTEX_4_FX) + /* PPC errata 213: only for Virtex-4 FX */ + mfccr0 0 + oris 0,0,0x50000000@h + mtccr0 0 +#endif + mflr r3 /* Save our actual starting address. */ /* The following functions we call must not modify r3 or r4..... diff --git a/arch/ppc/configs/ml300_defconfig b/arch/ppc/configs/ml300_defconfig new file mode 100644 index 00000000000..4a33aca948c --- /dev/null +++ b/arch/ppc/configs/ml300_defconfig @@ -0,0 +1,739 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.16-rc1 +# Wed Jan 18 00:49:20 2006 +# +CONFIG_MMU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_PPC=y +CONFIG_PPC32=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_CLEAN_COMPILE=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +# CONFIG_POSIX_MQUEUE is not set +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_SYSCTL=y +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +# CONFIG_EMBEDDED is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SHMEM=y +CONFIG_CC_ALIGN_FUNCTIONS=0 +CONFIG_CC_ALIGN_LABELS=0 +CONFIG_CC_ALIGN_LOOPS=0 +CONFIG_CC_ALIGN_JUMPS=0 +CONFIG_SLAB=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +# CONFIG_SLOB is not set + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_KMOD=y + +# +# Block layer +# +CONFIG_LBD=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# Processor +# +# CONFIG_6xx is not set +CONFIG_40x=y +# CONFIG_44x is not set +# CONFIG_POWER3 is not set +# CONFIG_8xx is not set +# CONFIG_E200 is not set +# CONFIG_E500 is not set +# CONFIG_MATH_EMULATION is not set +# CONFIG_KEXEC is not set +# CONFIG_CPU_FREQ is not set +CONFIG_4xx=y +# CONFIG_WANT_EARLY_SERIAL is not set + +# +# IBM 4xx options +# +# CONFIG_BUBINGA is not set +# CONFIG_CPCI405 is not set +# CONFIG_EP405 is not set +# CONFIG_REDWOOD_5 is not set +# CONFIG_REDWOOD_6 is not set +# CONFIG_SYCAMORE is not set +# CONFIG_WALNUT is not set +CONFIG_XILINX_ML300=y +CONFIG_IBM405_ERR77=y +CONFIG_IBM405_ERR51=y +CONFIG_XILINX_VIRTEX=y +CONFIG_EMBEDDEDBOOT=y +# CONFIG_PPC4xx_DMA is not set +CONFIG_PPC_GEN550=y +CONFIG_UART0_TTYS0=y +# CONFIG_UART0_TTYS1 is not set +CONFIG_NOT_COHERENT_CACHE=y + +# +# Platform options +# +# CONFIG_PC_KEYBOARD is not set +# CONFIG_HIGHMEM is not set +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="console=ttyS0,9600" +# CONFIG_PM is not set +# CONFIG_SOFTWARE_SUSPEND is not set +CONFIG_SECCOMP=y +CONFIG_ISA_DMA_API=y + +# +# Bus options +# +# CONFIG_PPC_I8259 is not set +# CONFIG_PCI is not set +# CONFIG_PCI_DOMAINS is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Advanced setup +# +# CONFIG_ADVANCED_OPTIONS is not set + +# +# Default settings for advanced configuration options are used +# +CONFIG_HIGHMEM_START=0xfe000000 +CONFIG_LOWMEM_SIZE=0x30000000 +CONFIG_KERNEL_START=0xc0000000 +CONFIG_TASK_SIZE=0x80000000 +CONFIG_CONSISTENT_START=0xff100000 +CONFIG_CONSISTENT_SIZE=0x00200000 +CONFIG_BOOT_LOAD=0x00400000 + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set + +# +# TIPC Configuration (EXPERIMENTAL) +# +# CONFIG_TIPC is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_IEEE80211 is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_BLK_DEV_INITRD=y +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# I2O device support +# + +# +# Macintosh device drivers +# +# CONFIG_WINDFARM is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=y + +# +# PHY device support +# + +# +# Ethernet (10 or 100Mbit) +# +# CONFIG_NET_ETHERNET is not set +# CONFIG_IBM_EMAC is not set + +# +# Ethernet (1000 Mbit) +# + +# +# Ethernet (10000 Mbit) +# + +# +# Token Ring devices +# + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_AGP is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +# CONFIG_TELCLOCK is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set + +# +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# +# Misc devices +# + +# +# Multimedia Capabilities Port drivers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# Graphics support +# +# CONFIG_FB is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB_ARCH_HAS_HCD is not set +# CONFIG_USB_ARCH_HAS_OHCI is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set + +# +# MMC/SD Card support +# +# CONFIG_MMC is not set + +# +# InfiniBand support +# + +# +# SN Devices +# + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_RELAYFS_FS is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +# CONFIG_NFS_FS is not set +# CONFIG_NFSD is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y + +# +# IBM 40x options +# + +# +# Library routines +# +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_DEBUG_SLAB is not set +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_FS is not set +# CONFIG_DEBUG_VM is not set +CONFIG_FORCED_INLINING=y +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_KGDB is not set +CONFIG_XMON=y +# CONFIG_BDI_SWITCH is not set +# CONFIG_SERIAL_TEXT_DEBUG is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Hardware crypto devices +# diff --git a/arch/ppc/configs/ml403_defconfig b/arch/ppc/configs/ml403_defconfig new file mode 100644 index 00000000000..fafd2516fa5 --- /dev/null +++ b/arch/ppc/configs/ml403_defconfig @@ -0,0 +1,740 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.16-rc1 +# Wed Jan 18 01:11:41 2006 +# +CONFIG_MMU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_PPC=y +CONFIG_PPC32=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_CLEAN_COMPILE=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +# CONFIG_POSIX_MQUEUE is not set +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_SYSCTL=y +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +# CONFIG_EMBEDDED is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SHMEM=y +CONFIG_CC_ALIGN_FUNCTIONS=0 +CONFIG_CC_ALIGN_LABELS=0 +CONFIG_CC_ALIGN_LOOPS=0 +CONFIG_CC_ALIGN_JUMPS=0 +CONFIG_SLAB=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +# CONFIG_SLOB is not set + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_KMOD=y + +# +# Block layer +# +CONFIG_LBD=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# Processor +# +# CONFIG_6xx is not set +CONFIG_40x=y +# CONFIG_44x is not set +# CONFIG_POWER3 is not set +# CONFIG_8xx is not set +# CONFIG_E200 is not set +# CONFIG_E500 is not set +# CONFIG_MATH_EMULATION is not set +# CONFIG_KEXEC is not set +# CONFIG_CPU_FREQ is not set +CONFIG_4xx=y +# CONFIG_WANT_EARLY_SERIAL is not set + +# +# IBM 4xx options +# +# CONFIG_BUBINGA is not set +# CONFIG_CPCI405 is not set +# CONFIG_EP405 is not set +# CONFIG_REDWOOD_5 is not set +# CONFIG_REDWOOD_6 is not set +# CONFIG_SYCAMORE is not set +# CONFIG_WALNUT is not set +# CONFIG_XILINX_ML300 is not set +CONFIG_XILINX_ML403=y +CONFIG_IBM405_ERR77=y +CONFIG_IBM405_ERR51=y +CONFIG_XILINX_VIRTEX=y +CONFIG_EMBEDDEDBOOT=y +# CONFIG_PPC4xx_DMA is not set +CONFIG_PPC_GEN550=y +CONFIG_UART0_TTYS0=y +# CONFIG_UART0_TTYS1 is not set +CONFIG_NOT_COHERENT_CACHE=y + +# +# Platform options +# +# CONFIG_PC_KEYBOARD is not set +# CONFIG_HIGHMEM is not set +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="console=ttyS0,9600" +# CONFIG_PM is not set +# CONFIG_SOFTWARE_SUSPEND is not set +CONFIG_SECCOMP=y +CONFIG_ISA_DMA_API=y + +# +# Bus options +# +# CONFIG_PPC_I8259 is not set +# CONFIG_PCI is not set +# CONFIG_PCI_DOMAINS is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Advanced setup +# +# CONFIG_ADVANCED_OPTIONS is not set + +# +# Default settings for advanced configuration options are used +# +CONFIG_HIGHMEM_START=0xfe000000 +CONFIG_LOWMEM_SIZE=0x30000000 +CONFIG_KERNEL_START=0xc0000000 +CONFIG_TASK_SIZE=0x80000000 +CONFIG_CONSISTENT_START=0xff100000 +CONFIG_CONSISTENT_SIZE=0x00200000 +CONFIG_BOOT_LOAD=0x00400000 + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set + +# +# TIPC Configuration (EXPERIMENTAL) +# +# CONFIG_TIPC is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_IEEE80211 is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_BLK_DEV_INITRD=y +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# I2O device support +# + +# +# Macintosh device drivers +# +# CONFIG_WINDFARM is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=y + +# +# PHY device support +# + +# +# Ethernet (10 or 100Mbit) +# +# CONFIG_NET_ETHERNET is not set +# CONFIG_IBM_EMAC is not set + +# +# Ethernet (1000 Mbit) +# + +# +# Ethernet (10000 Mbit) +# + +# +# Token Ring devices +# + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_AGP is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +# CONFIG_TELCLOCK is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set + +# +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# +# Misc devices +# + +# +# Multimedia Capabilities Port drivers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# Graphics support +# +# CONFIG_FB is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB_ARCH_HAS_HCD is not set +# CONFIG_USB_ARCH_HAS_OHCI is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set + +# +# MMC/SD Card support +# +# CONFIG_MMC is not set + +# +# InfiniBand support +# + +# +# SN Devices +# + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_RELAYFS_FS is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +# CONFIG_NFS_FS is not set +# CONFIG_NFSD is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y + +# +# IBM 40x options +# + +# +# Library routines +# +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_DEBUG_SLAB is not set +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_FS is not set +# CONFIG_DEBUG_VM is not set +CONFIG_FORCED_INLINING=y +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_KGDB is not set +CONFIG_XMON=y +# CONFIG_BDI_SWITCH is not set +# CONFIG_SERIAL_TEXT_DEBUG is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Hardware crypto devices +# diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index 3e6ca7f5843..c1e89ad0684 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -810,13 +810,16 @@ initial_mmu: mtspr SPRN_MD_TWC, r9 li r11, MI_BOOTINIT /* Create RPN for address 0 */ addis r11, r11, 0x0080 /* Add 8M */ - mtspr SPRN_MD_RPN, r8 + mtspr SPRN_MD_RPN, r11 + + addi r10, r10, 0x0100 + mtspr SPRN_MD_CTR, r10 addis r8, r8, 0x0080 /* Add 8M */ mtspr SPRN_MD_EPN, r8 mtspr SPRN_MD_TWC, r9 addis r11, r11, 0x0080 /* Add 8M */ - mtspr SPRN_MD_RPN, r8 + mtspr SPRN_MD_RPN, r11 #endif /* Since the cache is enabled according to the information we diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig index d8837911bbc..174ddbc9758 100644 --- a/arch/ppc/platforms/4xx/Kconfig +++ b/arch/ppc/platforms/4xx/Kconfig @@ -57,6 +57,10 @@ config XILINX_ML300 help This option enables support for the Xilinx ML300 evaluation board. +config XILINX_ML403 + bool "Xilinx-ML403" + help + This option enables support for the Xilinx ML403 evaluation board. endchoice choice @@ -172,11 +176,6 @@ config IBM_OCP depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT default y -config XILINX_OCP - bool - depends on XILINX_ML300 - default y - config IBM_EMAC4 bool depends on 440GX || 440SP || 440SPE @@ -208,11 +207,21 @@ config 405GPR depends on SYCAMORE default y -config VIRTEX_II_PRO +config XILINX_VIRTEX_II_PRO bool depends on XILINX_ML300 default y +config XILINX_VIRTEX_4_FX + bool + depends on XILINX_ML403 + default y + +config XILINX_VIRTEX + bool + depends on XILINX_VIRTEX_II_PRO || XILINX_VIRTEX_4_FX + default y + config STB03xxx bool depends on REDWOOD_5 || REDWOOD_6 @@ -220,7 +229,7 @@ config STB03xxx config EMBEDDEDBOOT bool - depends on EP405 || XILINX_ML300 + depends on EP405 || XILINX_ML300 || XILINX_ML403 default y config IBM_OPENBIOS diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile index c9bb6117095..a04a0d0a0f5 100644 --- a/arch/ppc/platforms/4xx/Makefile +++ b/arch/ppc/platforms/4xx/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_REDWOOD_6) += redwood6.o obj-$(CONFIG_SYCAMORE) += sycamore.o obj-$(CONFIG_WALNUT) += walnut.o obj-$(CONFIG_XILINX_ML300) += xilinx_ml300.o +obj-$(CONFIG_XILINX_ML403) += xilinx_ml403.o obj-$(CONFIG_405GP) += ibm405gp.o obj-$(CONFIG_REDWOOD_5) += ibmstb4.o @@ -26,4 +27,5 @@ obj-$(CONFIG_440SP) += ibm440sp.o obj-$(CONFIG_440SPE) += ppc440spe.o obj-$(CONFIG_405EP) += ibm405ep.o obj-$(CONFIG_405GPR) += ibm405gpr.o -obj-$(CONFIG_VIRTEX_II_PRO) += virtex-ii_pro.o +obj-$(CONFIG_XILINX_VIRTEX) += virtex.o + diff --git a/arch/ppc/platforms/4xx/virtex-ii_pro.c b/arch/ppc/platforms/4xx/virtex-ii_pro.c deleted file mode 100644 index 097cc9d5aca..00000000000 --- a/arch/ppc/platforms/4xx/virtex-ii_pro.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * arch/ppc/platforms/4xx/virtex-ii_pro.c - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * 2002-2004 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is licensed - * "as is" without any warranty of any kind, whether express or implied. - */ - -#include <linux/config.h> -#include <linux/init.h> -#include <asm/ocp.h> -#include "virtex-ii_pro.h" - -/* Have OCP take care of the serial ports. */ -struct ocp_def core_ocp[] = { -#ifdef XPAR_UARTNS550_0_BASEADDR - { .vendor = OCP_VENDOR_XILINX, - .function = OCP_FUNC_16550, - .index = 0, - .paddr = XPAR_UARTNS550_0_BASEADDR, - .irq = XPAR_INTC_0_UARTNS550_0_VEC_ID, - .pm = OCP_CPM_NA - }, -#ifdef XPAR_UARTNS550_1_BASEADDR - { .vendor = OCP_VENDOR_XILINX, - .function = OCP_FUNC_16550, - .index = 1, - .paddr = XPAR_UARTNS550_1_BASEADDR, - .irq = XPAR_INTC_0_UARTNS550_1_VEC_ID, - .pm = OCP_CPM_NA - }, -#ifdef XPAR_UARTNS550_2_BASEADDR - { .vendor = OCP_VENDOR_XILINX, - .function = OCP_FUNC_16550, - .index = 2, - .paddr = XPAR_UARTNS550_2_BASEADDR, - .irq = XPAR_INTC_0_UARTNS550_2_VEC_ID, - .pm = OCP_CPM_NA - }, -#ifdef XPAR_UARTNS550_3_BASEADDR - { .vendor = OCP_VENDOR_XILINX, - .function = OCP_FUNC_16550, - .index = 3, - .paddr = XPAR_UARTNS550_3_BASEADDR, - .irq = XPAR_INTC_0_UARTNS550_3_VEC_ID, - .pm = OCP_CPM_NA - }, -#ifdef XPAR_UARTNS550_4_BASEADDR -#error Edit this file to add more devices. -#endif /* 4 */ -#endif /* 3 */ -#endif /* 2 */ -#endif /* 1 */ -#endif /* 0 */ - { .vendor = OCP_VENDOR_INVALID - } -}; diff --git a/arch/ppc/platforms/4xx/virtex-ii_pro.h b/arch/ppc/platforms/4xx/virtex-ii_pro.h deleted file mode 100644 index 9014c488733..00000000000 --- a/arch/ppc/platforms/4xx/virtex-ii_pro.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * arch/ppc/platforms/4xx/virtex-ii_pro.h - * - * Include file that defines the Xilinx Virtex-II Pro processor - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * 2002-2004 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is licensed - * "as is" without any warranty of any kind, whether express or implied. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_VIRTEXIIPRO_H__ -#define __ASM_VIRTEXIIPRO_H__ - -#include <linux/config.h> -#include <asm/xparameters.h> - -/* serial defines */ - -#define RS_TABLE_SIZE 4 /* change this and add more devices below - if you have more then 4 16x50 UARTs */ - -#define BASE_BAUD (XPAR_UARTNS550_0_CLOCK_FREQ_HZ/16) - -/* The serial ports in the Virtex-II Pro have each I/O byte in the - * LSByte of a word. This means that iomem_reg_shift needs to be 2 to - * change the byte offsets into word offsets. In addition the base - * addresses need to have 3 added to them to get to the LSByte. - */ -#define STD_UART_OP(num) \ - { 0, BASE_BAUD, 0, XPAR_INTC_0_UARTNS550_##num##_VEC_ID, \ - ASYNC_BOOT_AUTOCONF, \ - .iomem_base = (u8 *)XPAR_UARTNS550_##num##_BASEADDR + 3, \ - .iomem_reg_shift = 2, \ - .io_type = SERIAL_IO_MEM}, - -#if defined(XPAR_INTC_0_UARTNS550_0_VEC_ID) -#define ML300_UART0 STD_UART_OP(0) -#else -#define ML300_UART0 -#endif - -#if defined(XPAR_INTC_0_UARTNS550_1_VEC_ID) -#define ML300_UART1 STD_UART_OP(1) -#else -#define ML300_UART1 -#endif - -#if defined(XPAR_INTC_0_UARTNS550_2_VEC_ID) -#define ML300_UART2 STD_UART_OP(2) -#else -#define ML300_UART2 -#endif - -#if defined(XPAR_INTC_0_UARTNS550_3_VEC_ID) -#define ML300_UART3 STD_UART_OP(3) -#else -#define ML300_UART3 -#endif - -#if defined(XPAR_INTC_0_UARTNS550_4_VEC_ID) -#error Edit this file to add more devices. -#elif defined(XPAR_INTC_0_UARTNS550_3_VEC_ID) -#define NR_SER_PORTS 4 -#elif defined(XPAR_INTC_0_UARTNS550_2_VEC_ID) -#define NR_SER_PORTS 3 -#elif defined(XPAR_INTC_0_UARTNS550_1_VEC_ID) -#define NR_SER_PORTS 2 -#elif defined(XPAR_INTC_0_UARTNS550_0_VEC_ID) -#define NR_SER_PORTS 1 -#else -#define NR_SER_PORTS 0 -#endif - -#if defined(CONFIG_UART0_TTYS0) -#define SERIAL_PORT_DFNS \ - ML300_UART0 \ - ML300_UART1 \ - ML300_UART2 \ - ML300_UART3 -#endif - -#if defined(CONFIG_UART0_TTYS1) -#define SERIAL_PORT_DFNS \ - ML300_UART1 \ - ML300_UART0 \ - ML300_UART2 \ - ML300_UART3 -#endif - -#define DCRN_CPMFR_BASE 0 - -#include <asm/ibm405.h> - -#endif /* __ASM_VIRTEXIIPRO_H__ */ -#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/virtex.c b/arch/ppc/platforms/4xx/virtex.c new file mode 100644 index 00000000000..133a8314719 --- /dev/null +++ b/arch/ppc/platforms/4xx/virtex.c @@ -0,0 +1,56 @@ +/* + * Virtex-II Pro & Virtex-4 FX common infrastructure + * + * Maintainer: Grant Likely <grant.likely@secretlab.ca> + * + * Copyright 2005 Secret Lab Technologies Ltd. + * Copyright 2005 General Dynamics Canada Ltd. + * Copyright 2005 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/device.h> +#include <linux/serial_8250.h> +#include <asm/ppc_sys.h> +#include <platforms/4xx/virtex.h> +#include <platforms/4xx/xparameters/xparameters.h> + +#define XPAR_UART(num) { \ + .mapbase = XPAR_UARTNS550_##num##_BASEADDR + 3, \ + .irq = XPAR_INTC_0_UARTNS550_##num##_VEC_ID, \ + .iotype = UPIO_MEM, \ + .uartclk = XPAR_UARTNS550_##num##_CLOCK_FREQ_HZ, \ + .flags = UPF_BOOT_AUTOCONF, \ + .regshift = 2, \ + } + +struct plat_serial8250_port serial_platform_data[] = { +#ifdef XPAR_UARTNS550_0_BASEADDR + XPAR_UART(0), +#endif +#ifdef XPAR_UARTNS550_1_BASEADDR + XPAR_UART(1), +#endif +#ifdef XPAR_UARTNS550_2_BASEADDR + XPAR_UART(2), +#endif +#ifdef XPAR_UARTNS550_3_BASEADDR + XPAR_UART(3), +#endif + { }, /* terminated by empty record */ +}; + +struct platform_device ppc_sys_platform_devices[] = { + [VIRTEX_UART] = { + .name = "serial8250", + .id = 0, + .dev.platform_data = serial_platform_data, + }, +}; + diff --git a/arch/ppc/platforms/4xx/virtex.h b/arch/ppc/platforms/4xx/virtex.h new file mode 100644 index 00000000000..1a01b81cff1 --- /dev/null +++ b/arch/ppc/platforms/4xx/virtex.h @@ -0,0 +1,35 @@ +/* + * arch/ppc/platforms/4xx/virtex.h + * + * Include file that defines the Xilinx Virtex-II Pro processor + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * 2002-2004 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is licensed + * "as is" without any warranty of any kind, whether express or implied. + */ + +#ifdef __KERNEL__ +#ifndef __ASM_VIRTEX_H__ +#define __ASM_VIRTEX_H__ + +/* serial defines */ + +#include <asm/ibm405.h> + +/* Ugly, ugly, ugly! BASE_BAUD defined here to keep 8250.c happy. */ +#if !defined(BASE_BAUD) + #define BASE_BAUD (0) /* dummy value; not used */ +#endif + +/* Device type enumeration for platform bus definitions */ +#ifndef __ASSEMBLY__ +enum ppc_sys_devices { + VIRTEX_UART, +}; +#endif + +#endif /* __ASM_VIRTEX_H__ */ +#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/xilinx_ml300.c b/arch/ppc/platforms/4xx/xilinx_ml300.c index 0b1b77d986b..267afb50607 100644 --- a/arch/ppc/platforms/4xx/xilinx_ml300.c +++ b/arch/ppc/platforms/4xx/xilinx_ml300.c @@ -17,12 +17,14 @@ #include <linux/tty.h> #include <linux/serial.h> #include <linux/serial_core.h> +#include <linux/serial_8250.h> #include <linux/serialP.h> #include <asm/io.h> #include <asm/machdep.h> -#include <asm/ocp.h> +#include <asm/ppc_sys.h> -#include <platforms/4xx/virtex-ii_pro.h> /* for NR_SER_PORTS */ +#include <syslib/gen550.h> +#include <platforms/4xx/xparameters/xparameters.h> /* * As an overview of how the following functions (platform_init, @@ -54,6 +56,22 @@ * ppc4xx_pic_init arch/ppc/syslib/xilinx_pic.c */ +/* Board specifications structures */ +struct ppc_sys_spec *cur_ppc_sys_spec; +struct ppc_sys_spec ppc_sys_specs[] = { + { + /* Only one entry, always assume the same design */ + .ppc_sys_name = "Xilinx ML300 Reference Design", + .mask = 0x00000000, + .value = 0x00000000, + .num_devices = 1, + .device_list = (enum ppc_sys_devices[]) + { + VIRTEX_UART, + }, + }, +}; + #if defined(XPAR_POWER_0_POWERDOWN_BASEADDR) static volatile unsigned *powerdown_base = @@ -80,28 +98,39 @@ ml300_map_io(void) #endif } +/* Early serial support functions */ static void __init +ml300_early_serial_init(int num, struct plat_serial8250_port *pdata) +{ +#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) + struct uart_port serial_req; + + memset(&serial_req, 0, sizeof(serial_req)); + serial_req.mapbase = pdata->mapbase; + serial_req.membase = pdata->membase; + serial_req.irq = pdata->irq; + serial_req.uartclk = pdata->uartclk; + serial_req.regshift = pdata->regshift; + serial_req.iotype = pdata->iotype; + serial_req.flags = pdata->flags; + gen550_init(num, &serial_req); +#endif +} + +void __init ml300_early_serial_map(void) { #ifdef CONFIG_SERIAL_8250 - struct serial_state old_ports[] = { SERIAL_PORT_DFNS }; - struct uart_port port; - int i; - - /* Setup ioremapped serial port access */ - for (i = 0; i < ARRAY_SIZE(old_ports); i++ ) { - memset(&port, 0, sizeof(port)); - port.membase = ioremap((phys_addr_t)(old_ports[i].iomem_base), 16); - port.irq = old_ports[i].irq; - port.uartclk = old_ports[i].baud_base * 16; - port.regshift = old_ports[i].iomem_reg_shift; - port.iotype = SERIAL_IO_MEM; - port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; - port.line = i; - - if (early_serial_setup(&port) != 0) { - printk("Early serial init of port %d failed\n", i); - } + struct plat_serial8250_port *pdata; + int i = 0; + + pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(VIRTEX_UART); + while(pdata && pdata->flags) + { + pdata->membase = ioremap(pdata->mapbase, 0x100); + ml300_early_serial_init(i, pdata); + pdata++; + i++; } #endif /* CONFIG_SERIAL_8250 */ } @@ -109,9 +138,8 @@ ml300_early_serial_map(void) void __init ml300_setup_arch(void) { - ppc4xx_setup_arch(); /* calls ppc4xx_find_bridges() */ - ml300_early_serial_map(); + ppc4xx_setup_arch(); /* calls ppc4xx_find_bridges() */ /* Identify the system */ printk(KERN_INFO "Xilinx Virtex-II Pro port\n"); @@ -131,6 +159,8 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5, { ppc4xx_init(r3, r4, r5, r6, r7); + identify_ppc_sys_by_id(mfspr(SPRN_PVR)); + ppc_md.setup_arch = ml300_setup_arch; ppc_md.setup_io_mappings = ml300_map_io; ppc_md.init_IRQ = ml300_init_irq; diff --git a/arch/ppc/platforms/4xx/xilinx_ml300.h b/arch/ppc/platforms/4xx/xilinx_ml300.h index f8c58841233..ae8bf1353b0 100644 --- a/arch/ppc/platforms/4xx/xilinx_ml300.h +++ b/arch/ppc/platforms/4xx/xilinx_ml300.h @@ -16,7 +16,7 @@ #define __ASM_XILINX_ML300_H__ /* ML300 has a Xilinx Virtex-II Pro processor */ -#include <platforms/4xx/virtex-ii_pro.h> +#include <platforms/4xx/virtex.h> #ifndef __ASSEMBLY__ @@ -41,7 +41,7 @@ typedef struct board_info { #define PPC4xx_ONB_IO_VADDR 0u #define PPC4xx_ONB_IO_SIZE 0u -#define PPC4xx_MACHINE_NAME "Xilinx ML300" +#define PPC4xx_MACHINE_NAME "Xilinx ML300 Reference System" #endif /* __ASM_XILINX_ML300_H__ */ #endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/xilinx_ml403.c b/arch/ppc/platforms/4xx/xilinx_ml403.c new file mode 100644 index 00000000000..4c0c7e4c111 --- /dev/null +++ b/arch/ppc/platforms/4xx/xilinx_ml403.c @@ -0,0 +1,177 @@ +/* + * arch/ppc/platforms/4xx/xilinx_ml403.c + * + * Xilinx ML403 evaluation board initialization + * + * Author: Grant Likely <grant.likely@secretlab.ca> + * + * 2005 (c) Secret Lab Technologies Ltd. + * 2002-2004 (c) MontaVista Software, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <linux/config.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/tty.h> +#include <linux/serial.h> +#include <linux/serial_core.h> +#include <linux/serial_8250.h> +#include <linux/serialP.h> +#include <asm/io.h> +#include <asm/machdep.h> +#include <asm/ppc_sys.h> + +#include <syslib/gen550.h> +#include <platforms/4xx/xparameters/xparameters.h> + +/* + * As an overview of how the following functions (platform_init, + * ml403_map_io, ml403_setup_arch and ml403_init_IRQ) fit into the + * kernel startup procedure, here's a call tree: + * + * start_here arch/ppc/kernel/head_4xx.S + * early_init arch/ppc/kernel/setup.c + * machine_init arch/ppc/kernel/setup.c + * platform_init this file + * ppc4xx_init arch/ppc/syslib/ppc4xx_setup.c + * parse_bootinfo + * find_bootinfo + * "setup some default ppc_md pointers" + * MMU_init arch/ppc/mm/init.c + * *ppc_md.setup_io_mappings == ml403_map_io this file + * ppc4xx_map_io arch/ppc/syslib/ppc4xx_setup.c + * start_kernel init/main.c + * setup_arch arch/ppc/kernel/setup.c + * #if defined(CONFIG_KGDB) + * *ppc_md.kgdb_map_scc() == gen550_kgdb_map_scc + * #endif + * *ppc_md.setup_arch == ml403_setup_arch this file + * ppc4xx_setup_arch arch/ppc/syslib/ppc4xx_setup.c + * ppc4xx_find_bridges arch/ppc/syslib/ppc405_pci.c + * init_IRQ arch/ppc/kernel/irq.c + * *ppc_md.init_IRQ == ml403_init_IRQ this file + * ppc4xx_init_IRQ arch/ppc/syslib/ppc4xx_setup.c + * ppc4xx_pic_init arch/ppc/syslib/xilinx_pic.c + */ + +/* Board specifications structures */ +struct ppc_sys_spec *cur_ppc_sys_spec; +struct ppc_sys_spec ppc_sys_specs[] = { + { + /* Only one entry, always assume the same design */ + .ppc_sys_name = "Xilinx ML403 Reference Design", + .mask = 0x00000000, + .value = 0x00000000, + .num_devices = 1, + .device_list = (enum ppc_sys_devices[]) + { + VIRTEX_UART, + }, + }, +}; + +#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR) + +static volatile unsigned *powerdown_base = + (volatile unsigned *) XPAR_POWER_0_POWERDOWN_BASEADDR; + +static void +xilinx_power_off(void) +{ + local_irq_disable(); + out_be32(powerdown_base, XPAR_POWER_0_POWERDOWN_VALUE); + while (1) ; +} +#endif + +void __init +ml403_map_io(void) +{ + ppc4xx_map_io(); + +#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR) + powerdown_base = ioremap((unsigned long) powerdown_base, + XPAR_POWER_0_POWERDOWN_HIGHADDR - + XPAR_POWER_0_POWERDOWN_BASEADDR + 1); +#endif +} + +/* Early serial support functions */ +static void __init +ml403_early_serial_init(int num, struct plat_serial8250_port *pdata) +{ +#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) + struct uart_port serial_req; + + memset(&serial_req, 0, sizeof(serial_req)); + serial_req.mapbase = pdata->mapbase; + serial_req.membase = pdata->membase; + serial_req.irq = pdata->irq; + serial_req.uartclk = pdata->uartclk; + serial_req.regshift = pdata->regshift; + serial_req.iotype = pdata->iotype; + serial_req.flags = pdata->flags; + gen550_init(num, &serial_req); +#endif +} + +void __init +ml403_early_serial_map(void) +{ +#ifdef CONFIG_SERIAL_8250 + struct plat_serial8250_port *pdata; + int i = 0; + + pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(VIRTEX_UART); + while(pdata && pdata->flags) + { + pdata->membase = ioremap(pdata->mapbase, 0x100); + ml403_early_serial_init(i, pdata); + pdata++; + i++; + } +#endif /* CONFIG_SERIAL_8250 */ +} + +void __init +ml403_setup_arch(void) +{ + ml403_early_serial_map(); + ppc4xx_setup_arch(); /* calls ppc4xx_find_bridges() */ + + /* Identify the system */ + printk(KERN_INFO "Xilinx ML403 Reference System (Virtex-4 FX)\n"); +} + +/* Called after board_setup_irq from ppc4xx_init_IRQ(). */ +void __init +ml403_init_irq(void) +{ + ppc4xx_init_IRQ(); +} + +void __init +platform_init(unsigned long r3, unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7) +{ + ppc4xx_init(r3, r4, r5, r6, r7); + + identify_ppc_sys_by_id(mfspr(SPRN_PVR)); + + ppc_md.setup_arch = ml403_setup_arch; + ppc_md.setup_io_mappings = ml403_map_io; + ppc_md.init_IRQ = ml403_init_irq; + +#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR) + ppc_md.power_off = xilinx_power_off; +#endif + +#ifdef CONFIG_KGDB + ppc_md.early_serial_map = ml403_early_serial_map; +#endif +} + diff --git a/arch/ppc/platforms/4xx/xilinx_ml403.h b/arch/ppc/platforms/4xx/xilinx_ml403.h new file mode 100644 index 00000000000..47359695990 --- /dev/null +++ b/arch/ppc/platforms/4xx/xilinx_ml403.h @@ -0,0 +1,49 @@ +/* + * arch/ppc/platforms/4xx/xilinx_ml403.h + * + * Include file that defines the Xilinx ML403 reference design + * + * Author: Grant Likely <grant.likely@secretlab.ca> + * + * 2005 (c) Secret Lab Technologies Ltd. + * 2002-2004 (c) MontaVista Software, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#ifdef __KERNEL__ +#ifndef __ASM_XILINX_ML403_H__ +#define __ASM_XILINX_ML403_H__ + +/* ML403 has a Xilinx Virtex-4 FPGA with a PPC405 hard core */ +#include <platforms/4xx/virtex.h> + +#ifndef __ASSEMBLY__ + +#include <linux/types.h> + +typedef struct board_info { + unsigned int bi_memsize; /* DRAM installed, in bytes */ + unsigned char bi_enetaddr[6]; /* Local Ethernet MAC address */ + unsigned int bi_intfreq; /* Processor speed, in Hz */ + unsigned int bi_busfreq; /* PLB Bus speed, in Hz */ + unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ +} bd_t; + +/* Some 4xx parts use a different timebase frequency from the internal clock. +*/ +#define bi_tbfreq bi_intfreq + +#endif /* !__ASSEMBLY__ */ + +/* We don't need anything mapped. Size of zero will accomplish that. */ +#define PPC4xx_ONB_IO_PADDR 0u +#define PPC4xx_ONB_IO_VADDR 0u +#define PPC4xx_ONB_IO_SIZE 0u + +#define PPC4xx_MACHINE_NAME "Xilinx ML403 Reference Design" + +#endif /* __ASM_XILINX_ML403_H__ */ +#endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters.h b/arch/ppc/platforms/4xx/xparameters/xparameters.h new file mode 100644 index 00000000000..4cf21f25635 --- /dev/null +++ b/arch/ppc/platforms/4xx/xparameters/xparameters.h @@ -0,0 +1,37 @@ +/* + * include/asm-ppc/xparameters.h + * + * This file includes the correct xparameters.h for the CONFIG'ed board plus + * fixups to translate board specific XPAR values to a common set of names + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * 2004 (c) MontaVista Software, Inc. This file is licensed under the terms + * of the GNU General Public License version 2. This program is licensed + * "as is" without any warranty of any kind, whether express or implied. + */ + +#include <linux/config.h> + +#if defined(CONFIG_XILINX_ML300) + #include "xparameters_ml300.h" +#elif defined(CONFIG_XILINX_ML403) + #include "xparameters_ml403.h" +#else + /* Add other board xparameter includes here before the #else */ + #error No xparameters_*.h file included +#endif + +#ifndef SERIAL_PORT_DFNS + /* zImage serial port definitions */ + #define RS_TABLE_SIZE 1 + #define SERIAL_PORT_DFNS { \ + .baud_base = XPAR_UARTNS550_0_CLOCK_FREQ_HZ/16, \ + .irq = XPAR_INTC_0_UARTNS550_0_VEC_ID, \ + .flags = ASYNC_BOOT_AUTOCONF, \ + .iomem_base = (u8 *)XPAR_UARTNS550_0_BASEADDR + 3, \ + .iomem_reg_shift = 2, \ + .io_type = SERIAL_IO_MEM, \ + }, +#endif diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h b/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h new file mode 100644 index 00000000000..5cacdcb3964 --- /dev/null +++ b/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h @@ -0,0 +1,243 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by libgen. +* Version: Xilinx EDK 7.1.2 EDK_H.12.5.1 +* DO NOT EDIT. +* +* Copyright (c) 2005 Xilinx, Inc. All rights reserved. +* +* Description: Driver parameters +* +*******************************************************************/ + +#define XPAR_PLB_BRAM_IF_CNTLR_0_BASEADDR 0xFFFF0000 +#define XPAR_PLB_BRAM_IF_CNTLR_0_HIGHADDR 0xFFFFFFFF + +/******************************************************************/ + +#define XPAR_OPB_EMC_0_MEM0_BASEADDR 0x20000000 +#define XPAR_OPB_EMC_0_MEM0_HIGHADDR 0x200FFFFF +#define XPAR_OPB_EMC_0_MEM1_BASEADDR 0x28000000 +#define XPAR_OPB_EMC_0_MEM1_HIGHADDR 0x287FFFFF +#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000 +#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF +#define XPAR_OPB_EMC_USB_0_MEM0_BASEADDR 0xA5000000 +#define XPAR_OPB_EMC_USB_0_MEM0_HIGHADDR 0xA50000FF +#define XPAR_PLB_DDR_0_MEM0_BASEADDR 0x00000000 +#define XPAR_PLB_DDR_0_MEM0_HIGHADDR 0x0FFFFFFF + +/******************************************************************/ + +#define XPAR_XEMAC_NUM_INSTANCES 1 +#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000 +#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF +#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0 +#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1 +#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1 +#define XPAR_OPB_ETHERNET_0_MII_EXIST 1 + +/******************************************************************/ + +#define XPAR_XUARTNS550_NUM_INSTANCES 1 +#define XPAR_XUARTNS550_CLOCK_HZ 100000000 +#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000 +#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF +#define XPAR_OPB_UART16550_0_DEVICE_ID 0 + +/******************************************************************/ + +#define XPAR_XGPIO_NUM_INSTANCES 3 +#define XPAR_OPB_GPIO_0_BASEADDR 0x90000000 +#define XPAR_OPB_GPIO_0_HIGHADDR 0x900001FF +#define XPAR_OPB_GPIO_0_DEVICE_ID 0 +#define XPAR_OPB_GPIO_0_INTERRUPT_PRESENT 0 +#define XPAR_OPB_GPIO_0_IS_DUAL 1 +#define XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR 0x90001000 +#define XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR 0x900011FF +#define XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID 1 +#define XPAR_OPB_GPIO_EXP_HDR_0_INTERRUPT_PRESENT 0 +#define XPAR_OPB_GPIO_EXP_HDR_0_IS_DUAL 1 +#define XPAR_OPB_GPIO_CHAR_LCD_0_BASEADDR 0x90002000 +#define XPAR_OPB_GPIO_CHAR_LCD_0_HIGHADDR 0x900021FF +#define XPAR_OPB_GPIO_CHAR_LCD_0_DEVICE_ID 2 +#define XPAR_OPB_GPIO_CHAR_LCD_0_INTERRUPT_PRESENT 0 +#define XPAR_OPB_GPIO_CHAR_LCD_0_IS_DUAL 0 + +/******************************************************************/ + +#define XPAR_XPS2_NUM_INSTANCES 2 +#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0 +#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000 +#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F) +#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1 +#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000) +#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F) + +/******************************************************************/ + +#define XPAR_XIIC_NUM_INSTANCES 1 +#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000 +#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF +#define XPAR_OPB_IIC_0_DEVICE_ID 0 +#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0 +#define XPAR_OPB_IIC_0_GPO_WIDTH 1 + +/******************************************************************/ + +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 10 +#define XPAR_XINTC_HAS_IPR 1 +#define XPAR_XINTC_USE_DCR 0 +#define XPAR_XINTC_NUM_INSTANCES 1 +#define XPAR_OPB_INTC_0_BASEADDR 0xD1000FC0 +#define XPAR_OPB_INTC_0_HIGHADDR 0xD1000FDF +#define XPAR_OPB_INTC_0_DEVICE_ID 0 +#define XPAR_OPB_INTC_0_KIND_OF_INTR 0x00000000 + +/******************************************************************/ + +#define XPAR_INTC_SINGLE_BASEADDR 0xD1000FC0 +#define XPAR_INTC_SINGLE_HIGHADDR 0xD1000FDF +#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID +#define XPAR_OPB_ETHERNET_0_IP2INTC_IRPT_MASK 0X000001 +#define XPAR_OPB_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 0 +#define XPAR_SYSTEM_USB_HPI_INT_MASK 0X000002 +#define XPAR_OPB_INTC_0_SYSTEM_USB_HPI_INT_INTR 1 +#define XPAR_MISC_LOGIC_0_PHY_MII_INT_MASK 0X000004 +#define XPAR_OPB_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 2 +#define XPAR_OPB_SYSACE_0_SYSACE_IRQ_MASK 0X000008 +#define XPAR_OPB_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 3 +#define XPAR_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_MASK 0X000010 +#define XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 4 +#define XPAR_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_MASK 0X000020 +#define XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 5 +#define XPAR_OPB_IIC_0_IP2INTC_IRPT_MASK 0X000040 +#define XPAR_OPB_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 6 +#define XPAR_OPB_PS2_DUAL_REF_0_SYS_INTR2_MASK 0X000080 +#define XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 7 +#define XPAR_OPB_PS2_DUAL_REF_0_SYS_INTR1_MASK 0X000100 +#define XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8 +#define XPAR_OPB_UART16550_0_IP2INTC_IRPT_MASK 0X000200 +#define XPAR_OPB_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 9 + +/******************************************************************/ + +#define XPAR_XTFT_NUM_INSTANCES 1 +#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200 +#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207 +#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0 + +/******************************************************************/ + +#define XPAR_XSYSACE_MEM_WIDTH 16 +#define XPAR_XSYSACE_NUM_INSTANCES 1 +#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000 +#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF +#define XPAR_OPB_SYSACE_0_DEVICE_ID 0 +#define XPAR_OPB_SYSACE_0_MEM_WIDTH 16 + +/******************************************************************/ + +#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000 + +/******************************************************************/ + + +/******************************************************************/ + +/* Linux Redefines */ + +/******************************************************************/ + +#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000) +#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR +#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ +#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID + +/******************************************************************/ + +#define XPAR_INTC_0_BASEADDR XPAR_OPB_INTC_0_BASEADDR +#define XPAR_INTC_0_HIGHADDR XPAR_OPB_INTC_0_HIGHADDR +#define XPAR_INTC_0_KIND_OF_INTR XPAR_OPB_INTC_0_KIND_OF_INTR +#define XPAR_INTC_0_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID + +/******************************************************************/ + +#define XPAR_INTC_0_EMAC_0_VEC_ID XPAR_OPB_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR +#define XPAR_INTC_0_SYSACE_0_VEC_ID XPAR_OPB_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR +#define XPAR_INTC_0_IIC_0_VEC_ID XPAR_OPB_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR +#define XPAR_INTC_0_PS2_1_VEC_ID XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR +#define XPAR_INTC_0_PS2_0_VEC_ID XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR +#define XPAR_INTC_0_UARTNS550_0_VEC_ID XPAR_OPB_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR + +/******************************************************************/ + +#define XPAR_TFT_0_BASEADDR XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR + +/******************************************************************/ + +#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR +#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR +#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT +#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST +#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST +#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID + +/******************************************************************/ + +#define XPAR_GPIO_0_BASEADDR XPAR_OPB_GPIO_0_BASEADDR_0 +#define XPAR_GPIO_0_HIGHADDR XPAR_OPB_GPIO_0_HIGHADDR_0 +#define XPAR_GPIO_0_DEVICE_ID XPAR_OPB_GPIO_0_DEVICE_ID_0 +#define XPAR_GPIO_1_BASEADDR XPAR_OPB_GPIO_0_BASEADDR_1 +#define XPAR_GPIO_1_HIGHADDR XPAR_OPB_GPIO_0_HIGHADDR_1 +#define XPAR_GPIO_1_DEVICE_ID XPAR_OPB_GPIO_0_DEVICE_ID_1 +#define XPAR_GPIO_2_BASEADDR XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR_0 +#define XPAR_GPIO_2_HIGHADDR XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR_0 +#define XPAR_GPIO_2_DEVICE_ID XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID_0 +#define XPAR_GPIO_3_BASEADDR XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR_1 +#define XPAR_GPIO_3_HIGHADDR XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR_1 +#define XPAR_GPIO_3_DEVICE_ID XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID_1 +#define XPAR_GPIO_4_BASEADDR XPAR_OPB_GPIO_CHAR_LCD_0_BASEADDR +#define XPAR_GPIO_4_HIGHADDR XPAR_OPB_GPIO_CHAR_LCD_0_HIGHADDR +#define XPAR_GPIO_4_DEVICE_ID XPAR_OPB_GPIO_CHAR_LCD_0_DEVICE_ID + +/******************************************************************/ + +#define XPAR_PS2_0_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 +#define XPAR_PS2_0_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 +#define XPAR_PS2_0_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 +#define XPAR_PS2_1_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 +#define XPAR_PS2_1_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 +#define XPAR_PS2_1_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 + +/******************************************************************/ + +#define XPAR_SYSACE_0_BASEADDR XPAR_OPB_SYSACE_0_BASEADDR +#define XPAR_SYSACE_0_HIGHADDR XPAR_OPB_SYSACE_0_HIGHADDR +#define XPAR_SYSACE_0_DEVICE_ID XPAR_OPB_SYSACE_0_DEVICE_ID + +/******************************************************************/ + +#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR +#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR +#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR +#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID + +/******************************************************************/ + +#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 +#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ +#define XPAR_DDR_0_SIZE 0x4000000 + +/******************************************************************/ + +#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400 +#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF +#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0 + +/******************************************************************/ + +#define XPAR_PCI_0_CLOCK_FREQ_HZ 0 + +/******************************************************************/ + diff --git a/arch/ppc/platforms/Makefile b/arch/ppc/platforms/Makefile index 51430e294b3..e8b91a33ce9 100644 --- a/arch/ppc/platforms/Makefile +++ b/arch/ppc/platforms/Makefile @@ -37,6 +37,9 @@ obj-$(CONFIG_SBC82xx) += sbc82xx.o obj-$(CONFIG_SPRUCE) += spruce.o obj-$(CONFIG_LITE5200) += lite5200.o obj-$(CONFIG_EV64360) += ev64360.o +obj-$(CONFIG_MPC86XADS) += mpc866ads_setup.o +obj-$(CONFIG_MPC885ADS) += mpc885ads_setup.o +obj-$(CONFIG_ADS8272) += mpc8272ads_setup.o ifeq ($(CONFIG_SMP),y) obj-$(CONFIG_PPC_CHRP) += chrp_smp.o diff --git a/arch/ppc/platforms/fads.h b/arch/ppc/platforms/fads.h index a48fb8d723e..e1c0b1b6dcb 100644 --- a/arch/ppc/platforms/fads.h +++ b/arch/ppc/platforms/fads.h @@ -112,7 +112,7 @@ /* CPM Ethernet through SCC1 or SCC2 */ -#ifdef CONFIG_SCC1_ENET /* Probably 860 variant */ +#if defined(CONFIG_SCC1_ENET) || defined(CONFIG_MPC8xx_SECOND_ETH_SCC1) /* Probably 860 variant */ /* Bits in parallel I/O port registers that have to be set/cleared * to configure the pins for SCC1 use. * TCLK - CLK1, RCLK - CLK2. diff --git a/arch/ppc/platforms/mpc8272ads_setup.c b/arch/ppc/platforms/mpc8272ads_setup.c new file mode 100644 index 00000000000..bc9b94f77e3 --- /dev/null +++ b/arch/ppc/platforms/mpc8272ads_setup.c @@ -0,0 +1,236 @@ +/* + * arch/ppc/platforms/82xx/pq2ads_pd.c + * + * MPC82xx Board-specific PlatformDevice descriptions + * + * 2005 (c) MontaVista Software, Inc. + * Vitaly Bordug <vbordug@ru.mvista.com> + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/device.h> +#include <linux/ioport.h> +#include <linux/fs_enet_pd.h> +#include <linux/platform_device.h> + +#include <asm/io.h> +#include <asm/mpc8260.h> +#include <asm/cpm2.h> +#include <asm/immap_cpm2.h> +#include <asm/irq.h> +#include <asm/ppc_sys.h> +#include <asm/ppcboot.h> + +#include "pq2ads_pd.h" + +static void init_fcc1_ioports(void); +static void init_fcc2_ioports(void); + +static struct fs_mii_bus_info mii_bus_info = { + .method = fsmii_bitbang, + .id = 0, + .i.bitbang = { + .mdio_port = fsiop_portc, + .mdio_bit = 18, + .mdc_port = fsiop_portc, + .mdc_bit = 19, + .delay = 1, + }, +}; + +static struct fs_platform_info mpc82xx_fcc1_pdata = { + .fs_no = fsid_fcc1, + .cp_page = CPM_CR_FCC1_PAGE, + .cp_block = CPM_CR_FCC1_SBLOCK, + .clk_trx = (PC_F1RXCLK | PC_F1TXCLK), + .clk_route = CMX1_CLK_ROUTE, + .clk_mask = CMX1_CLK_MASK, + .init_ioports = init_fcc1_ioports, + + .phy_addr = 0, +#ifdef PHY_INTERRUPT + .phy_irq = PHY_INTERRUPT, +#else + .phy_irq = -1; +#endif + .mem_offset = FCC1_MEM_OFFSET, + .bus_info = &mii_bus_info, + .rx_ring = 32, + .tx_ring = 32, + .rx_copybreak = 240, + .use_napi = 0, + .napi_weight = 17, +}; + +static struct fs_platform_info mpc82xx_fcc2_pdata = { + .fs_no = fsid_fcc2, + .cp_page = CPM_CR_FCC2_PAGE, + .cp_block = CPM_CR_FCC2_SBLOCK, + .clk_trx = (PC_F2RXCLK | PC_F2TXCLK), + .clk_route = CMX2_CLK_ROUTE, + .clk_mask = CMX2_CLK_MASK, + .init_ioports = init_fcc2_ioports, + + .phy_addr = 3, +#ifdef PHY_INTERRUPT + .phy_irq = PHY_INTERRUPT, +#else + .phy_irq = -1; +#endif + .mem_offset = FCC2_MEM_OFFSET, + .bus_info = &mii_bus_info, + .rx_ring = 32, + .tx_ring = 32, + .rx_copybreak = 240, + .use_napi = 0, + .napi_weight = 17, +}; + +static void init_fcc1_ioports(void) +{ + struct io_port *io; + u32 tempval; + cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t)); + u32 *bcsr = ioremap(BCSR_ADDR+4, sizeof(u32)); + + io = &immap->im_ioport; + + /* Enable the PHY */ + clrbits32(bcsr, BCSR1_FETHIEN); + setbits32(bcsr, BCSR1_FETH_RST); + + /* FCC1 pins are on port A/C. */ + /* Configure port A and C pins for FCC1 Ethernet. */ + + tempval = in_be32(&io->iop_pdira); + tempval &= ~PA1_DIRA0; + tempval |= PA1_DIRA1; + out_be32(&io->iop_pdira, tempval); + + tempval = in_be32(&io->iop_psora); + tempval &= ~PA1_PSORA0; + tempval |= PA1_PSORA1; + out_be32(&io->iop_psora, tempval); + + setbits32(&io->iop_ppara,PA1_DIRA0 | PA1_DIRA1); + + /* Alter clocks */ + tempval = PC_F1TXCLK|PC_F1RXCLK; + + clrbits32(&io->iop_psorc, tempval); + clrbits32(&io->iop_pdirc, tempval); + setbits32(&io->iop_pparc, tempval); + + clrbits32(&immap->im_cpmux.cmx_fcr, CMX1_CLK_MASK); + setbits32(&immap->im_cpmux.cmx_fcr, CMX1_CLK_ROUTE); + iounmap(bcsr); + iounmap(immap); +} + +static void init_fcc2_ioports(void) +{ + cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t)); + u32 *bcsr = ioremap(BCSR_ADDR+12, sizeof(u32)); + + struct io_port *io; + u32 tempval; + + immap = cpm2_immr; + + io = &immap->im_ioport; + + /* Enable the PHY */ + clrbits32(bcsr, BCSR3_FETHIEN2); + setbits32(bcsr, BCSR3_FETH2_RST); + + /* FCC2 are port B/C. */ + /* Configure port A and C pins for FCC2 Ethernet. */ + + tempval = in_be32(&io->iop_pdirb); + tempval &= ~PB2_DIRB0; + tempval |= PB2_DIRB1; + out_be32(&io->iop_pdirb, tempval); + + tempval = in_be32(&io->iop_psorb); + tempval &= ~PB2_PSORB0; + tempval |= PB2_PSORB1; + out_be32(&io->iop_psorb, tempval); + + setbits32(&io->iop_pparb,PB2_DIRB0 | PB2_DIRB1); + + tempval = PC_F2RXCLK|PC_F2TXCLK; + + /* Alter clocks */ + clrbits32(&io->iop_psorc,tempval); + clrbits32(&io->iop_pdirc,tempval); + setbits32(&io->iop_pparc,tempval); + + clrbits32(&immap->im_cpmux.cmx_fcr, CMX2_CLK_MASK); + setbits32(&immap->im_cpmux.cmx_fcr, CMX2_CLK_ROUTE); + + iounmap(bcsr); + iounmap(immap); +} + + +static void __init mpc8272ads_fixup_enet_pdata(struct platform_device *pdev, + int idx) +{ + bd_t* bi = (void*)__res; + int fs_no = fsid_fcc1+pdev->id-1; + + mpc82xx_fcc1_pdata.dpram_offset = mpc82xx_fcc2_pdata.dpram_offset = (u32)cpm2_immr->im_dprambase; + mpc82xx_fcc1_pdata.fcc_regs_c = mpc82xx_fcc2_pdata.fcc_regs_c = (u32)cpm2_immr->im_fcc_c; + + switch(fs_no) { + case fsid_fcc1: + memcpy(&mpc82xx_fcc1_pdata.macaddr,bi->bi_enetaddr,6); + pdev->dev.platform_data = &mpc82xx_fcc1_pdata; + break; + case fsid_fcc2: + memcpy(&mpc82xx_fcc2_pdata.macaddr,bi->bi_enetaddr,6); + mpc82xx_fcc2_pdata.macaddr[5] ^= 1; + pdev->dev.platform_data = &mpc82xx_fcc2_pdata; + break; + } +} + +static int mpc8272ads_platform_notify(struct device *dev) +{ + static const struct platform_notify_dev_map dev_map[] = { + { + .bus_id = "fsl-cpm-fcc", + .rtn = mpc8272ads_fixup_enet_pdata + }, + { + .bus_id = NULL + } + }; + platform_notify_map(dev_map,dev); + + return 0; + +} + +int __init mpc8272ads_init(void) +{ + printk(KERN_NOTICE "mpc8272ads: Init\n"); + + platform_notify = mpc8272ads_platform_notify; + + ppc_sys_device_initfunc(); + + ppc_sys_device_disable_all(); + ppc_sys_device_enable(MPC82xx_CPM_FCC1); + ppc_sys_device_enable(MPC82xx_CPM_FCC2); + + return 0; +} + +arch_initcall(mpc8272ads_init); diff --git a/arch/ppc/platforms/mpc866ads_setup.c b/arch/ppc/platforms/mpc866ads_setup.c new file mode 100644 index 00000000000..ac8fcc68afe --- /dev/null +++ b/arch/ppc/platforms/mpc866ads_setup.c @@ -0,0 +1,273 @@ +/*arch/ppc/platforms/mpc885ads-setup.c + * + * Platform setup for the Freescale mpc885ads board + * + * Vitaly Bordug <vbordug@ru.mvista.com> + * + * Copyright 2005 MontaVista Software Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <linux/config.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/param.h> +#include <linux/string.h> +#include <linux/ioport.h> +#include <linux/device.h> + +#include <linux/fs_enet_pd.h> +#include <linux/mii.h> + +#include <asm/delay.h> +#include <asm/io.h> +#include <asm/machdep.h> +#include <asm/page.h> +#include <asm/processor.h> +#include <asm/system.h> +#include <asm/time.h> +#include <asm/ppcboot.h> +#include <asm/8xx_immap.h> +#include <asm/commproc.h> +#include <asm/ppc_sys.h> +#include <asm/mpc8xx.h> + +extern unsigned char __res[]; + +static struct fs_mii_bus_info fec_mii_bus_info = { + .method = fsmii_fec, + .id = 0, +}; + +static struct fs_mii_bus_info scc_mii_bus_info = { + .method = fsmii_fixed, + .id = 0, + .i.fixed.speed = 10, + .i.fixed.duplex = 0, +}; + +static struct fs_platform_info mpc8xx_fec_pdata[] = { + { + .rx_ring = 128, + .tx_ring = 16, + .rx_copybreak = 240, + + .use_napi = 1, + .napi_weight = 17, + + .phy_addr = 15, + .phy_irq = -1, + + .use_rmii = 0, + + .bus_info = &fec_mii_bus_info, + } +}; + +static struct fs_platform_info mpc8xx_scc_pdata = { + .rx_ring = 64, + .tx_ring = 8, + .rx_copybreak = 240, + + .use_napi = 1, + .napi_weight = 17, + + .phy_addr = -1, + .phy_irq = -1, + + .bus_info = &scc_mii_bus_info, +}; + +void __init board_init(void) +{ + volatile cpm8xx_t *cp = cpmp; + unsigned *bcsr_io; + + bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); + + if (bcsr_io == NULL) { + printk(KERN_CRIT "Could not remap BCSR1\n"); + return; + } +#ifdef CONFIG_SERIAL_CPM_SMC1 + cp->cp_simode &= ~(0xe0000000 >> 17); /* brg1 */ + clrbits32(bcsr_io,(0x80000000 >> 7)); +#else + setbits32(bcsr_io,(0x80000000 >> 7)); + + cp->cp_pbpar &= ~(0x000000c0); + cp->cp_pbdir |= 0x000000c0; + cp->cp_smc[0].smc_smcmr = 0; + cp->cp_smc[0].smc_smce = 0; +#endif + +#ifdef CONFIG_SERIAL_CPM_SMC2 + cp->cp_simode &= ~(0xe0000000 >> 1); + cp->cp_simode |= (0x20000000 >> 1); /* brg2 */ + clrbits32(bcsr_io,(0x80000000 >> 13)); +#else + clrbits32(bcsr_io,(0x80000000 >> 13)); + cp->cp_pbpar &= ~(0x00000c00); + cp->cp_pbdir |= 0x00000c00; + cp->cp_smc[1].smc_smcmr = 0; + cp->cp_smc[1].smc_smce = 0; +#endif + iounmap(bcsr_io); +} + +static void setup_fec1_ioports(void) +{ + immap_t *immap = (immap_t *) IMAP_ADDR; + + setbits16(&immap->im_ioport.iop_pdpar, 0x1fff); + setbits16(&immap->im_ioport.iop_pddir, 0x1fff); +} + +static void setup_scc1_ioports(void) +{ + immap_t *immap = (immap_t *) IMAP_ADDR; + unsigned *bcsr_io; + + bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); + + if (bcsr_io == NULL) { + printk(KERN_CRIT "Could not remap BCSR1\n"); + return; + } + + /* Enable the PHY. + */ + clrbits32(bcsr_io,BCSR1_ETHEN); + + /* Configure port A pins for Txd and Rxd. + */ + /* Disable receive and transmit in case EPPC-Bug started it. + */ + setbits16(&immap->im_ioport.iop_papar, PA_ENET_RXD | PA_ENET_TXD); + clrbits16(&immap->im_ioport.iop_padir, PA_ENET_RXD | PA_ENET_TXD); + clrbits16(&immap->im_ioport.iop_paodr, PA_ENET_TXD); + + /* Configure port C pins to enable CLSN and RENA. + */ + clrbits16(&immap->im_ioport.iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA); + clrbits16(&immap->im_ioport.iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA); + setbits16(&immap->im_ioport.iop_pcso, PC_ENET_CLSN | PC_ENET_RENA); + /* Configure port A for TCLK and RCLK. + */ + setbits16(&immap->im_ioport.iop_papar, PA_ENET_TCLK | PA_ENET_RCLK); + clrbits16(&immap->im_ioport.iop_padir, PA_ENET_TCLK | PA_ENET_RCLK); + clrbits32(&immap->im_cpm.cp_pbpar, PB_ENET_TENA); + clrbits32(&immap->im_cpm.cp_pbdir, PB_ENET_TENA); + + /* Configure Serial Interface clock routing. + * First, clear all SCC bits to zero, then set the ones we want. + */ + clrbits32(&immap->im_cpm.cp_sicr, SICR_ENET_MASK); + setbits32(&immap->im_cpm.cp_sicr, SICR_ENET_CLKRT); + + /* In the original SCC enet driver the following code is placed at + the end of the initialization */ + setbits32(&immap->im_cpm.cp_pbpar, PB_ENET_TENA); + setbits32(&immap->im_cpm.cp_pbdir, PB_ENET_TENA); + +} + +static void mpc866ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no) +{ + struct fs_platform_info *fpi = pdev->dev.platform_data; + + volatile cpm8xx_t *cp; + bd_t *bd = (bd_t *) __res; + char *e; + int i; + + /* Get pointer to Communication Processor */ + cp = cpmp; + switch (fs_no) { + case fsid_fec1: + fpi = &mpc8xx_fec_pdata[0]; + fpi->init_ioports = &setup_fec1_ioports; + + break; + case fsid_scc1: + fpi = &mpc8xx_scc_pdata; + fpi->init_ioports = &setup_scc1_ioports; + + break; + default: + printk(KERN_WARNING"Device %s is not supported!\n", pdev->name); + return; + } + + pdev->dev.platform_data = fpi; + fpi->fs_no = fs_no; + + e = (unsigned char *)&bd->bi_enetaddr; + for (i = 0; i < 6; i++) + fpi->macaddr[i] = *e++; + + fpi->macaddr[5 - pdev->id]++; + +} + +static void mpc866ads_fixup_fec_enet_pdata(struct platform_device *pdev, + int idx) +{ + /* This is for FEC devices only */ + if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec"))) + return; + mpc866ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1); +} + +static void mpc866ads_fixup_scc_enet_pdata(struct platform_device *pdev, + int idx) +{ + /* This is for SCC devices only */ + if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc"))) + return; + + mpc866ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1); +} + +static int mpc866ads_platform_notify(struct device *dev) +{ + static const struct platform_notify_dev_map dev_map[] = { + { + .bus_id = "fsl-cpm-fec", + .rtn = mpc866ads_fixup_fec_enet_pdata, + }, + { + .bus_id = "fsl-cpm-scc", + .rtn = mpc866ads_fixup_scc_enet_pdata, + }, + { + .bus_id = NULL + } + }; + + platform_notify_map(dev_map,dev); + + return 0; +} + +int __init mpc866ads_init(void) +{ + printk(KERN_NOTICE "mpc866ads: Init\n"); + + platform_notify = mpc866ads_platform_notify; + + ppc_sys_device_initfunc(); + ppc_sys_device_disable_all(); + +#ifdef MPC8xx_SECOND_ETH_SCC1 + ppc_sys_device_enable(MPC8xx_CPM_SCC1); +#endif + ppc_sys_device_enable(MPC8xx_CPM_FEC1); + + return 0; +} + +arch_initcall(mpc866ads_init); diff --git a/arch/ppc/platforms/mpc885ads_setup.c b/arch/ppc/platforms/mpc885ads_setup.c new file mode 100644 index 00000000000..50a99e5f7c6 --- /dev/null +++ b/arch/ppc/platforms/mpc885ads_setup.c @@ -0,0 +1,389 @@ +/*arch/ppc/platforms/mpc885ads-setup.c + * + * Platform setup for the Freescale mpc885ads board + * + * Vitaly Bordug <vbordug@ru.mvista.com> + * + * Copyright 2005 MontaVista Software Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <linux/config.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/param.h> +#include <linux/string.h> +#include <linux/ioport.h> +#include <linux/device.h> + +#include <linux/fs_enet_pd.h> +#include <linux/mii.h> + +#include <asm/delay.h> +#include <asm/io.h> +#include <asm/machdep.h> +#include <asm/page.h> +#include <asm/processor.h> +#include <asm/system.h> +#include <asm/time.h> +#include <asm/ppcboot.h> +#include <asm/8xx_immap.h> +#include <asm/commproc.h> +#include <asm/ppc_sys.h> + +extern unsigned char __res[]; + +static void __init mpc885ads_scc_phy_init(char); + +static struct fs_mii_bus_info fec_mii_bus_info = { + .method = fsmii_fec, + .id = 0, +}; + +static struct fs_mii_bus_info scc_mii_bus_info = { +#ifdef CONFIG_SCC_ENET_8xx_FIXED + .method = fsmii_fixed, +#else + .method = fsmii_fec, +#endif + + .id = 0, +}; + +static struct fs_platform_info mpc8xx_fec_pdata[] = { + { + .rx_ring = 128, + .tx_ring = 16, + .rx_copybreak = 240, + + .use_napi = 1, + .napi_weight = 17, + + .phy_addr = 0, + .phy_irq = SIU_IRQ7, + + .bus_info = &fec_mii_bus_info, + }, { + .rx_ring = 128, + .tx_ring = 16, + .rx_copybreak = 240, + + .use_napi = 1, + .napi_weight = 17, + + .phy_addr = 1, + .phy_irq = SIU_IRQ7, + + .bus_info = &fec_mii_bus_info, + } +}; + +static struct fs_platform_info mpc8xx_scc_pdata = { + .rx_ring = 64, + .tx_ring = 8, + .rx_copybreak = 240, + + .use_napi = 1, + .napi_weight = 17, + + .phy_addr = 2, +#ifdef CONFIG_MPC8xx_SCC_ENET_FIXED + .phy_irq = -1, +#else + .phy_irq = SIU_IRQ7, +#endif + + .bus_info = &scc_mii_bus_info, +}; + +void __init board_init(void) +{ + volatile cpm8xx_t *cp = cpmp; + unsigned int *bcsr_io; + +#ifdef CONFIG_FS_ENET + immap_t *immap = (immap_t *) IMAP_ADDR; +#endif + bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); + + if (bcsr_io == NULL) { + printk(KERN_CRIT "Could not remap BCSR\n"); + return; + } +#ifdef CONFIG_SERIAL_CPM_SMC1 + cp->cp_simode &= ~(0xe0000000 >> 17); /* brg1 */ + clrbits32(bcsr_io, BCSR1_RS232EN_1); +#else + setbits32(bcsr_io,BCSR1_RS232EN_1); + cp->cp_smc[0].smc_smcmr = 0; + cp->cp_smc[0].smc_smce = 0; +#endif + +#ifdef CONFIG_SERIAL_CPM_SMC2 + cp->cp_simode &= ~(0xe0000000 >> 1); + cp->cp_simode |= (0x20000000 >> 1); /* brg2 */ + clrbits32(bcsr_io,BCSR1_RS232EN_2); +#else + setbits32(bcsr_io,BCSR1_RS232EN_2); + cp->cp_smc[1].smc_smcmr = 0; + cp->cp_smc[1].smc_smce = 0; +#endif + iounmap(bcsr_io); + +#ifdef CONFIG_FS_ENET + /* use MDC for MII (common) */ + setbits16(&immap->im_ioport.iop_pdpar, 0x0080); + clrbits16(&immap->im_ioport.iop_pddir, 0x0080); +#endif +} + +static void setup_fec1_ioports(void) +{ + immap_t *immap = (immap_t *) IMAP_ADDR; + + /* configure FEC1 pins */ + setbits16(&immap->im_ioport.iop_papar, 0xf830); + setbits16(&immap->im_ioport.iop_padir, 0x0830); + clrbits16(&immap->im_ioport.iop_padir, 0xf000); + setbits32(&immap->im_cpm.cp_pbpar, 0x00001001); + + clrbits32(&immap->im_cpm.cp_pbdir, 0x00001001); + setbits16(&immap->im_ioport.iop_pcpar, 0x000c); + clrbits16(&immap->im_ioport.iop_pcdir, 0x000c); + setbits32(&immap->im_cpm.cp_pepar, 0x00000003); + + setbits32(&immap->im_cpm.cp_pedir, 0x00000003); + clrbits32(&immap->im_cpm.cp_peso, 0x00000003); + clrbits32(&immap->im_cpm.cp_cptr, 0x00000100); +} + +static void setup_fec2_ioports(void) +{ + immap_t *immap = (immap_t *) IMAP_ADDR; + + /* configure FEC2 pins */ + setbits32(&immap->im_cpm.cp_pepar, 0x0003fffc); + setbits32(&immap->im_cpm.cp_pedir, 0x0003fffc); + setbits32(&immap->im_cpm.cp_peso, 0x00037800); + clrbits32(&immap->im_cpm.cp_peso, 0x000087fc); + clrbits32(&immap->im_cpm.cp_cptr, 0x00000080); +} + +static void setup_scc3_ioports(void) +{ + immap_t *immap = (immap_t *) IMAP_ADDR; + unsigned *bcsr_io; + + bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE); + + if (bcsr_io == NULL) { + printk(KERN_CRIT "Could not remap BCSR\n"); + return; + } + + /* Enable the PHY. + */ + setbits32(bcsr_io+4, BCSR4_ETH10_RST); + /* Configure port A pins for Txd and Rxd. + */ + setbits16(&immap->im_ioport.iop_papar, PA_ENET_RXD | PA_ENET_TXD); + clrbits16(&immap->im_ioport.iop_padir, PA_ENET_RXD | PA_ENET_TXD); + + /* Configure port C pins to enable CLSN and RENA. + */ + clrbits16(&immap->im_ioport.iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA); + clrbits16(&immap->im_ioport.iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA); + setbits16(&immap->im_ioport.iop_pcso, PC_ENET_CLSN | PC_ENET_RENA); + + /* Configure port E for TCLK and RCLK. + */ + setbits32(&immap->im_cpm.cp_pepar, PE_ENET_TCLK | PE_ENET_RCLK); + clrbits32(&immap->im_cpm.cp_pepar, PE_ENET_TENA); + clrbits32(&immap->im_cpm.cp_pedir, + PE_ENET_TCLK | PE_ENET_RCLK | PE_ENET_TENA); + clrbits32(&immap->im_cpm.cp_peso, PE_ENET_TCLK | PE_ENET_RCLK); + setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA); + + /* Configure Serial Interface clock routing. + * First, clear all SCC bits to zero, then set the ones we want. + */ + clrbits32(&immap->im_cpm.cp_sicr, SICR_ENET_MASK); + setbits32(&immap->im_cpm.cp_sicr, SICR_ENET_CLKRT); + + /* Disable Rx and Tx. SMC1 sshould be stopped if SCC3 eternet are used. + */ + immap->im_cpm.cp_smc[0].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); + /* On the MPC885ADS SCC ethernet PHY is initialized in the full duplex mode + * by H/W setting after reset. SCC ethernet controller support only half duplex. + * This discrepancy of modes causes a lot of carrier lost errors. + */ + + /* In the original SCC enet driver the following code is placed at + the end of the initialization */ + setbits32(&immap->im_cpm.cp_pepar, PE_ENET_TENA); + clrbits32(&immap->im_cpm.cp_pedir, PE_ENET_TENA); + setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA); + + setbits32(bcsr_io+1, BCSR1_ETHEN); + iounmap(bcsr_io); +} + +static void mpc885ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no) +{ + struct fs_platform_info *fpi = pdev->dev.platform_data; + + volatile cpm8xx_t *cp; + bd_t *bd = (bd_t *) __res; + char *e; + int i; + + /* Get pointer to Communication Processor */ + cp = cpmp; + switch (fs_no) { + case fsid_fec1: + fpi = &mpc8xx_fec_pdata[0]; + fpi->init_ioports = &setup_fec1_ioports; + break; + case fsid_fec2: + fpi = &mpc8xx_fec_pdata[1]; + fpi->init_ioports = &setup_fec2_ioports; + break; + case fsid_scc3: + fpi = &mpc8xx_scc_pdata; + fpi->init_ioports = &setup_scc3_ioports; + mpc885ads_scc_phy_init(fpi->phy_addr); + break; + default: + printk(KERN_WARNING"Device %s is not supported!\n", pdev->name); + return; + } + + pdev->dev.platform_data = fpi; + fpi->fs_no = fs_no; + + e = (unsigned char *)&bd->bi_enetaddr; + for (i = 0; i < 6; i++) + fpi->macaddr[i] = *e++; + + fpi->macaddr[5 - pdev->id]++; + +} + +static void mpc885ads_fixup_fec_enet_pdata(struct platform_device *pdev, + int idx) +{ + /* This is for FEC devices only */ + if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec"))) + return; + mpc885ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1); +} + +static void __init mpc885ads_fixup_scc_enet_pdata(struct platform_device *pdev, + int idx) +{ + /* This is for SCC devices only */ + if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc"))) + return; + + mpc885ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1); +} + +/* SCC ethernet controller does not have MII management channel. FEC1 MII + * channel is used to communicate with the 10Mbit PHY. + */ + +#define MII_ECNTRL_PINMUX 0x4 +#define FEC_ECNTRL_PINMUX 0x00000004 +#define FEC_RCNTRL_MII_MODE 0x00000004 + +/* Make MII read/write commands. + */ +#define mk_mii_write(REG, VAL, PHY_ADDR) (0x50020000 | (((REG) & 0x1f) << 18) | \ + ((VAL) & 0xffff) | ((PHY_ADDR) << 23)) + +static void mpc885ads_scc_phy_init(char phy_addr) +{ + volatile immap_t *immap; + volatile fec_t *fecp; + bd_t *bd; + + bd = (bd_t *) __res; + immap = (immap_t *) IMAP_ADDR; /* pointer to internal registers */ + fecp = &(immap->im_cpm.cp_fec); + + /* Enable MII pins of the FEC1 + */ + setbits16(&immap->im_ioport.iop_pdpar, 0x0080); + clrbits16(&immap->im_ioport.iop_pddir, 0x0080); + /* Set MII speed to 2.5 MHz + */ + out_be32(&fecp->fec_mii_speed, + ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1); + + /* Enable FEC pin MUX + */ + setbits32(&fecp->fec_ecntrl, MII_ECNTRL_PINMUX); + setbits32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE); + + out_be32(&fecp->fec_mii_data, + mk_mii_write(MII_BMCR, BMCR_ISOLATE, phy_addr)); + udelay(100); + out_be32(&fecp->fec_mii_data, + mk_mii_write(MII_ADVERTISE, + ADVERTISE_10HALF | ADVERTISE_CSMA, phy_addr)); + udelay(100); + + /* Disable FEC MII settings + */ + clrbits32(&fecp->fec_ecntrl, MII_ECNTRL_PINMUX); + clrbits32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE); + out_be32(&fecp->fec_mii_speed, 0); +} + +static int mpc885ads_platform_notify(struct device *dev) +{ + + static const struct platform_notify_dev_map dev_map[] = { + { + .bus_id = "fsl-cpm-fec", + .rtn = mpc885ads_fixup_fec_enet_pdata, + }, + { + .bus_id = "fsl-cpm-scc", + .rtn = mpc885ads_fixup_scc_enet_pdata, + }, + { + .bus_id = NULL + } + }; + + platform_notify_map(dev_map,dev); + +} + +int __init mpc885ads_init(void) +{ + printk(KERN_NOTICE "mpc885ads: Init\n"); + + platform_notify = mpc885ads_platform_notify; + + ppc_sys_device_initfunc(); + ppc_sys_device_disable_all(); + + ppc_sys_device_enable(MPC8xx_CPM_FEC1); + +#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3 + ppc_sys_device_enable(MPC8xx_CPM_SCC1); + +#endif +#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2 + ppc_sys_device_enable(MPC8xx_CPM_FEC2); +#endif + + return 0; +} + +arch_initcall(mpc885ads_init); diff --git a/arch/ppc/platforms/pq2ads.h b/arch/ppc/platforms/pq2ads.h index 067d9a5aebc..6b26dd36c64 100644 --- a/arch/ppc/platforms/pq2ads.h +++ b/arch/ppc/platforms/pq2ads.h @@ -13,6 +13,10 @@ #include <asm/ppcboot.h> +#if defined(CONFIG_ADS8272) +#define BOARD_CHIP_NAME "8272" +#endif + /* Memory map is configured by the PROM startup. * We just map a few things we need. The CSR is actually 4 byte-wide * registers that can be accessed as 8-, 16-, or 32-bit values. diff --git a/arch/ppc/platforms/pq2ads_pd.h b/arch/ppc/platforms/pq2ads_pd.h new file mode 100644 index 00000000000..8f14a43eafe --- /dev/null +++ b/arch/ppc/platforms/pq2ads_pd.h @@ -0,0 +1,114 @@ +#ifndef __PQ2ADS_PD_H +#define __PQ2ADS_PD_H +/* + * arch/ppc/platforms/82xx/pq2ads_pd.h + * + * Some defines for MPC82xx board-specific PlatformDevice descriptions + * + * 2005 (c) MontaVista Software, Inc. + * Vitaly Bordug <vbordug@ru.mvista.com> + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/* FCC1 Clock Source Configuration. These can be redefined in the board specific file. + Can only choose from CLK9-12 */ + +#define F1_RXCLK 11 +#define F1_TXCLK 10 + +/* FCC2 Clock Source Configuration. These can be redefined in the board specific file. + Can only choose from CLK13-16 */ +#define F2_RXCLK 15 +#define F2_TXCLK 16 + +/* FCC3 Clock Source Configuration. These can be redefined in the board specific file. + Can only choose from CLK13-16 */ +#define F3_RXCLK 13 +#define F3_TXCLK 14 + +/* Automatically generates register configurations */ +#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */ + +#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */ +#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */ +#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */ +#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */ +#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */ +#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */ + +#define PC_F1RXCLK PC_CLK(F1_RXCLK) +#define PC_F1TXCLK PC_CLK(F1_TXCLK) +#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK)) +#define CMX1_CLK_MASK ((uint)0xff000000) + +#define PC_F2RXCLK PC_CLK(F2_RXCLK) +#define PC_F2TXCLK PC_CLK(F2_TXCLK) +#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK)) +#define CMX2_CLK_MASK ((uint)0x00ff0000) + +#define PC_F3RXCLK PC_CLK(F3_RXCLK) +#define PC_F3TXCLK PC_CLK(F3_TXCLK) +#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK)) +#define CMX3_CLK_MASK ((uint)0x0000ff00) + +/* I/O Pin assignment for FCC1. I don't yet know the best way to do this, + * but there is little variation among the choices. + */ +#define PA1_COL 0x00000001U +#define PA1_CRS 0x00000002U +#define PA1_TXER 0x00000004U +#define PA1_TXEN 0x00000008U +#define PA1_RXDV 0x00000010U +#define PA1_RXER 0x00000020U +#define PA1_TXDAT 0x00003c00U +#define PA1_RXDAT 0x0003c000U +#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT) +#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \ + PA1_RXDV | PA1_RXER) +#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV) +#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER) + + +/* I/O Pin assignment for FCC2. I don't yet know the best way to do this, + * but there is little variation among the choices. + */ +#define PB2_TXER 0x00000001U +#define PB2_RXDV 0x00000002U +#define PB2_TXEN 0x00000004U +#define PB2_RXER 0x00000008U +#define PB2_COL 0x00000010U +#define PB2_CRS 0x00000020U +#define PB2_TXDAT 0x000003c0U +#define PB2_RXDAT 0x00003c00U +#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \ + PB2_RXER | PB2_RXDV | PB2_TXER) +#define PB2_PSORB1 (PB2_TXEN) +#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV) +#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER) + + +/* I/O Pin assignment for FCC3. I don't yet know the best way to do this, + * but there is little variation among the choices. + */ +#define PB3_RXDV 0x00004000U +#define PB3_RXER 0x00008000U +#define PB3_TXER 0x00010000U +#define PB3_TXEN 0x00020000U +#define PB3_COL 0x00040000U +#define PB3_CRS 0x00080000U +#define PB3_TXDAT 0x0f000000U +#define PB3_RXDAT 0x00f00000U +#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \ + PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN) +#define PB3_PSORB1 0 +#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV) +#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER) + +#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128)) +#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0) +#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1) + +#endif diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile index 159dcd92a6d..5cb62c6a51c 100644 --- a/arch/ppc/syslib/Makefile +++ b/arch/ppc/syslib/Makefile @@ -17,8 +17,8 @@ obj-$(CONFIG_440GX) += ibm440gx_common.o obj-$(CONFIG_440SP) += ibm440gx_common.o ibm440sp_common.o obj-$(CONFIG_440SPE) += ibm440gx_common.o ibm440sp_common.o ppc440spe_pcie.o ifeq ($(CONFIG_4xx),y) -ifeq ($(CONFIG_VIRTEX_II_PRO),y) -obj-$(CONFIG_40x) += xilinx_pic.o +ifeq ($(CONFIG_XILINX_VIRTEX),y) +obj-$(CONFIG_40x) += xilinx_pic.o ppc_sys.o else ifeq ($(CONFIG_403),y) obj-$(CONFIG_40x) += ppc403_pic.o diff --git a/arch/ppc/syslib/mv64x60.c b/arch/ppc/syslib/mv64x60.c index 94ea346b7b4..1f01b7e2376 100644 --- a/arch/ppc/syslib/mv64x60.c +++ b/arch/ppc/syslib/mv64x60.c @@ -313,7 +313,7 @@ static struct platform_device mpsc1_device = { }; #endif -#ifdef CONFIG_MV643XX_ETH +#if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE) static struct resource mv64x60_eth_shared_resources[] = { [0] = { .name = "ethernet shared base", @@ -456,7 +456,7 @@ static struct platform_device *mv64x60_pd_devs[] __initdata = { &mpsc0_device, &mpsc1_device, #endif -#ifdef CONFIG_MV643XX_ETH +#if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE) &mv64x60_eth_shared_device, #endif #ifdef CONFIG_MV643XX_ETH_0 diff --git a/arch/ppc/syslib/ppc4xx_pm.c b/arch/ppc/syslib/ppc4xx_pm.c deleted file mode 100644 index 60a47920488..00000000000 --- a/arch/ppc/syslib/ppc4xx_pm.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Author: Armin Kuster <akuster@mvista.com> - * - * 2002 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * This an attempt to get Power Management going for the IBM 4xx processor. - * This was derived from the ppc4xx._setup.c file - */ - -#include <linux/config.h> -#include <linux/init.h> - -#include <asm/ibm4xx.h> - -void __init -ppc4xx_pm_init(void) -{ - - unsigned int value = 0; - - /* turn off unused hardware to save power */ -#ifdef CONFIG_405GP - value |= CPM_DCP; /* CodePack */ -#endif - -#if !defined(CONFIG_IBM_OCP_GPIO) - value |= CPM_GPIO0; -#endif - -#if !defined(CONFIG_PPC405_I2C_ADAP) - value |= CPM_IIC0; -#ifdef CONFIG_STB03xxx - value |= CPM_IIC1; -#endif -#endif - - -#if !defined(CONFIG_405_DMA) - value |= CPM_DMA; -#endif - - mtdcr(DCRN_CPMFR, value); - -} diff --git a/arch/ppc/syslib/xilinx_pic.c b/arch/ppc/syslib/xilinx_pic.c index 47f04c71fe9..848fb512f3f 100644 --- a/arch/ppc/syslib/xilinx_pic.c +++ b/arch/ppc/syslib/xilinx_pic.c @@ -15,7 +15,7 @@ #include <linux/init.h> #include <linux/irq.h> #include <asm/io.h> -#include <asm/xparameters.h> +#include <platforms/4xx/xparameters/xparameters.h> #include <asm/ibm4xx.h> #include <asm/machdep.h> |