diff options
Diffstat (limited to 'arch/sh/include/cpu-sh4')
| -rw-r--r-- | arch/sh/include/cpu-sh4/cpu/addrspace.h | 35 | ||||
| -rw-r--r-- | arch/sh/include/cpu-sh4/cpu/cache.h | 42 | ||||
| -rw-r--r-- | arch/sh/include/cpu-sh4/cpu/cacheflush.h | 43 | ||||
| -rw-r--r-- | arch/sh/include/cpu-sh4/cpu/dma-sh7780.h | 39 | ||||
| -rw-r--r-- | arch/sh/include/cpu-sh4/cpu/dma.h | 65 | ||||
| -rw-r--r-- | arch/sh/include/cpu-sh4/cpu/fpu.h | 32 | ||||
| -rw-r--r-- | arch/sh/include/cpu-sh4/cpu/freq.h | 44 | ||||
| -rw-r--r-- | arch/sh/include/cpu-sh4/cpu/mmu_context.h | 63 | ||||
| -rw-r--r-- | arch/sh/include/cpu-sh4/cpu/rtc.h | 13 | ||||
| -rw-r--r-- | arch/sh/include/cpu-sh4/cpu/sigcontext.h | 24 | ||||
| -rw-r--r-- | arch/sh/include/cpu-sh4/cpu/sq.h | 35 | ||||
| -rw-r--r-- | arch/sh/include/cpu-sh4/cpu/timer.h | 60 | ||||
| -rw-r--r-- | arch/sh/include/cpu-sh4/cpu/ubc.h | 64 | ||||
| -rw-r--r-- | arch/sh/include/cpu-sh4/cpu/watchdog.h | 25 |
14 files changed, 584 insertions, 0 deletions
diff --git a/arch/sh/include/cpu-sh4/cpu/addrspace.h b/arch/sh/include/cpu-sh4/cpu/addrspace.h new file mode 100644 index 00000000000..a3fa733c1c7 --- /dev/null +++ b/arch/sh/include/cpu-sh4/cpu/addrspace.h @@ -0,0 +1,35 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1999 by Kaz Kojima + * + * Defitions for the address spaces of the SH-4 CPUs. + */ +#ifndef __ASM_CPU_SH4_ADDRSPACE_H +#define __ASM_CPU_SH4_ADDRSPACE_H + +#define P0SEG 0x00000000 +#define P1SEG 0x80000000 +#define P2SEG 0xa0000000 +#define P3SEG 0xc0000000 +#define P4SEG 0xe0000000 + +/* Detailed P4SEG */ +#define P4SEG_STORE_QUE (P4SEG) +#define P4SEG_IC_ADDR 0xf0000000 +#define P4SEG_IC_DATA 0xf1000000 +#define P4SEG_ITLB_ADDR 0xf2000000 +#define P4SEG_ITLB_DATA 0xf3000000 +#define P4SEG_OC_ADDR 0xf4000000 +#define P4SEG_OC_DATA 0xf5000000 +#define P4SEG_TLB_ADDR 0xf6000000 +#define P4SEG_TLB_DATA 0xf7000000 +#define P4SEG_REG_BASE 0xff000000 + +#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */ +#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */ + +#endif /* __ASM_CPU_SH4_ADDRSPACE_H */ + diff --git a/arch/sh/include/cpu-sh4/cpu/cache.h b/arch/sh/include/cpu-sh4/cpu/cache.h new file mode 100644 index 00000000000..1c61ebf5c8e --- /dev/null +++ b/arch/sh/include/cpu-sh4/cpu/cache.h @@ -0,0 +1,42 @@ +/* + * include/asm-sh/cpu-sh4/cache.h + * + * Copyright (C) 1999 Niibe Yutaka + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH4_CACHE_H +#define __ASM_CPU_SH4_CACHE_H + +#define L1_CACHE_SHIFT 5 + +#define SH_CACHE_VALID 1 +#define SH_CACHE_UPDATED 2 +#define SH_CACHE_COMBINED 4 +#define SH_CACHE_ASSOC 8 + +#define CCR 0xff00001c /* Address of Cache Control Register */ +#define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */ +#define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/ +#define CCR_CACHE_CB 0x0004 /* Copy-Back (for P1) (else writethrough) */ +#define CCR_CACHE_OCI 0x0008 /* OC Invalidate */ +#define CCR_CACHE_ORA 0x0020 /* OC RAM Mode */ +#define CCR_CACHE_OIX 0x0080 /* OC Index Enable */ +#define CCR_CACHE_ICE 0x0100 /* Instruction Cache Enable */ +#define CCR_CACHE_ICI 0x0800 /* IC Invalidate */ +#define CCR_CACHE_IIX 0x8000 /* IC Index Enable */ +#ifndef CONFIG_CPU_SH4A +#define CCR_CACHE_EMODE 0x80000000 /* EMODE Enable */ +#endif + +/* Default CCR setup: 8k+16k-byte cache,P1-wb,enable */ +#define CCR_CACHE_ENABLE (CCR_CACHE_OCE|CCR_CACHE_ICE) +#define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI|CCR_CACHE_ICI) + +#define CACHE_IC_ADDRESS_ARRAY 0xf0000000 +#define CACHE_OC_ADDRESS_ARRAY 0xf4000000 + +#endif /* __ASM_CPU_SH4_CACHE_H */ + diff --git a/arch/sh/include/cpu-sh4/cpu/cacheflush.h b/arch/sh/include/cpu-sh4/cpu/cacheflush.h new file mode 100644 index 00000000000..065306d376e --- /dev/null +++ b/arch/sh/include/cpu-sh4/cpu/cacheflush.h @@ -0,0 +1,43 @@ +/* + * include/asm-sh/cpu-sh4/cacheflush.h + * + * Copyright (C) 1999 Niibe Yutaka + * Copyright (C) 2003 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH4_CACHEFLUSH_H +#define __ASM_CPU_SH4_CACHEFLUSH_H + +/* + * Caches are broken on SH-4 (unless we use write-through + * caching; in which case they're only semi-broken), + * so we need them. + */ +void flush_cache_all(void); +void flush_dcache_all(void); +void flush_cache_mm(struct mm_struct *mm); +#define flush_cache_dup_mm(mm) flush_cache_mm(mm) +void flush_cache_range(struct vm_area_struct *vma, unsigned long start, + unsigned long end); +void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, + unsigned long pfn); +void flush_dcache_page(struct page *pg); + +#define flush_dcache_mmap_lock(mapping) do { } while (0) +#define flush_dcache_mmap_unlock(mapping) do { } while (0) + +void flush_icache_range(unsigned long start, unsigned long end); +void flush_icache_user_range(struct vm_area_struct *vma, struct page *page, + unsigned long addr, int len); + +#define flush_icache_page(vma,pg) do { } while (0) + +/* Initialization of P3 area for copy_user_page */ +void p3_cache_init(void); + +#define PG_mapped PG_arch_1 + +#endif /* __ASM_CPU_SH4_CACHEFLUSH_H */ diff --git a/arch/sh/include/cpu-sh4/cpu/dma-sh7780.h b/arch/sh/include/cpu-sh4/cpu/dma-sh7780.h new file mode 100644 index 00000000000..71b426a6e48 --- /dev/null +++ b/arch/sh/include/cpu-sh4/cpu/dma-sh7780.h @@ -0,0 +1,39 @@ +#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H +#define __ASM_SH_CPU_SH4_DMA_SH7780_H + +#define REQ_HE 0x000000C0 +#define REQ_H 0x00000080 +#define REQ_LE 0x00000040 +#define TM_BURST 0x0000020 +#define TS_8 0x00000000 +#define TS_16 0x00000008 +#define TS_32 0x00000010 +#define TS_16BLK 0x00000018 +#define TS_32BLK 0x00100000 + +/* + * The SuperH DMAC supports a number of transmit sizes, we list them here, + * with their respective values as they appear in the CHCR registers. + * + * Defaults to a 64-bit transfer size. + */ +enum { + XMIT_SZ_8BIT, + XMIT_SZ_16BIT, + XMIT_SZ_32BIT, + XMIT_SZ_128BIT, + XMIT_SZ_256BIT, +}; + +/* + * The DMA count is defined as the number of bytes to transfer. + */ +static unsigned int ts_shift[] __maybe_unused = { + [XMIT_SZ_8BIT] = 0, + [XMIT_SZ_16BIT] = 1, + [XMIT_SZ_32BIT] = 2, + [XMIT_SZ_128BIT] = 4, + [XMIT_SZ_256BIT] = 5, +}; + +#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */ diff --git a/arch/sh/include/cpu-sh4/cpu/dma.h b/arch/sh/include/cpu-sh4/cpu/dma.h new file mode 100644 index 00000000000..235b7cd1fc9 --- /dev/null +++ b/arch/sh/include/cpu-sh4/cpu/dma.h @@ -0,0 +1,65 @@ +#ifndef __ASM_CPU_SH4_DMA_H +#define __ASM_CPU_SH4_DMA_H + +#define DMAOR_INIT ( 0x8000 | DMAOR_DME ) + +/* SH7751/7760/7780 DMA IRQ sources */ +#define DMTE0_IRQ 34 +#define DMTE1_IRQ 35 +#define DMTE2_IRQ 36 +#define DMTE3_IRQ 37 +#define DMTE4_IRQ 44 +#define DMTE5_IRQ 45 +#define DMTE6_IRQ 46 +#define DMTE7_IRQ 47 +#define DMAE_IRQ 38 + +#ifdef CONFIG_CPU_SH4A +#define SH_DMAC_BASE 0xfc808020 + +#define CHCR_TS_MASK 0x18 +#define CHCR_TS_SHIFT 3 + +#include <cpu/dma-sh7780.h> +#else +#define SH_DMAC_BASE 0xffa00000 + +/* Definitions for the SuperH DMAC */ +#define TM_BURST 0x0000080 +#define TS_8 0x00000010 +#define TS_16 0x00000020 +#define TS_32 0x00000030 +#define TS_64 0x00000000 + +#define CHCR_TS_MASK 0x70 +#define CHCR_TS_SHIFT 4 + +#define DMAOR_COD 0x00000008 + +/* + * The SuperH DMAC supports a number of transmit sizes, we list them here, + * with their respective values as they appear in the CHCR registers. + * + * Defaults to a 64-bit transfer size. + */ +enum { + XMIT_SZ_64BIT, + XMIT_SZ_8BIT, + XMIT_SZ_16BIT, + XMIT_SZ_32BIT, + XMIT_SZ_256BIT, +}; + +/* + * The DMA count is defined as the number of bytes to transfer. + */ +static unsigned int ts_shift[] __maybe_unused = { + [XMIT_SZ_64BIT] = 3, + [XMIT_SZ_8BIT] = 0, + [XMIT_SZ_16BIT] = 1, + [XMIT_SZ_32BIT] = 2, + [XMIT_SZ_256BIT] = 5, +}; +#endif + +#endif /* __ASM_CPU_SH4_DMA_H */ diff --git a/arch/sh/include/cpu-sh4/cpu/fpu.h b/arch/sh/include/cpu-sh4/cpu/fpu.h new file mode 100644 index 00000000000..febef734252 --- /dev/null +++ b/arch/sh/include/cpu-sh4/cpu/fpu.h @@ -0,0 +1,32 @@ +/* + * linux/arch/sh/kernel/cpu/sh4/sh4_fpu.h + * + * Copyright (C) 2006 STMicroelectronics Limited + * Author: Carl Shaw <carl.shaw@st.com> + * + * May be copied or modified under the terms of the GNU General Public + * License Version 2. See linux/COPYING for more information. + * + * Definitions for SH4 FPU operations + */ + +#ifndef __CPU_SH4_FPU_H +#define __CPU_SH4_FPU_H + +#define FPSCR_ENABLE_MASK 0x00000f80UL + +#define FPSCR_FMOV_DOUBLE (1<<1) + +#define FPSCR_CAUSE_INEXACT (1<<12) +#define FPSCR_CAUSE_UNDERFLOW (1<<13) +#define FPSCR_CAUSE_OVERFLOW (1<<14) +#define FPSCR_CAUSE_DIVZERO (1<<15) +#define FPSCR_CAUSE_INVALID (1<<16) +#define FPSCR_CAUSE_ERROR (1<<17) + +#define FPSCR_DBL_PRECISION (1<<19) +#define FPSCR_ROUNDING_MODE(x) ((x >> 20) & 3) +#define FPSCR_RM_NEAREST (0) +#define FPSCR_RM_ZERO (1) + +#endif diff --git a/arch/sh/include/cpu-sh4/cpu/freq.h b/arch/sh/include/cpu-sh4/cpu/freq.h new file mode 100644 index 00000000000..c23af81c2e7 --- /dev/null +++ b/arch/sh/include/cpu-sh4/cpu/freq.h @@ -0,0 +1,44 @@ +/* + * include/asm-sh/cpu-sh4/freq.h + * + * Copyright (C) 2002, 2003 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH4_FREQ_H +#define __ASM_CPU_SH4_FREQ_H + +#if defined(CONFIG_CPU_SUBTYPE_SH7722) || \ + defined(CONFIG_CPU_SUBTYPE_SH7723) || \ + defined(CONFIG_CPU_SUBTYPE_SH7343) || \ + defined(CONFIG_CPU_SUBTYPE_SH7366) +#define FRQCR 0xa4150000 +#define VCLKCR 0xa4150004 +#define SCLKACR 0xa4150008 +#define SCLKBCR 0xa415000c +#define IrDACLKCR 0xa4150010 +#define MSTPCR0 0xa4150030 +#define MSTPCR1 0xa4150034 +#define MSTPCR2 0xa4150038 +#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ + defined(CONFIG_CPU_SUBTYPE_SH7780) +#define FRQCR 0xffc80000 +#elif defined(CONFIG_CPU_SUBTYPE_SH7785) +#define FRQCR0 0xffc80000 +#define FRQCR1 0xffc80004 +#define FRQMR1 0xffc80014 +#elif defined(CONFIG_CPU_SUBTYPE_SHX3) +#define FRQCR 0xffc00014 +#else +#define FRQCR 0xffc00000 +#define FRQCR_PSTBY 0x0200 +#define FRQCR_PLLEN 0x0400 +#define FRQCR_CKOEN 0x0800 +#endif +#define MIN_DIVISOR_NR 0 +#define MAX_DIVISOR_NR 3 + +#endif /* __ASM_CPU_SH4_FREQ_H */ + diff --git a/arch/sh/include/cpu-sh4/cpu/mmu_context.h b/arch/sh/include/cpu-sh4/cpu/mmu_context.h new file mode 100644 index 00000000000..9ea8eb27b18 --- /dev/null +++ b/arch/sh/include/cpu-sh4/cpu/mmu_context.h @@ -0,0 +1,63 @@ +/* + * include/asm-sh/cpu-sh4/mmu_context.h + * + * Copyright (C) 1999 Niibe Yutaka + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH4_MMU_CONTEXT_H +#define __ASM_CPU_SH4_MMU_CONTEXT_H + +#define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */ +#define MMU_PTEL 0xFF000004 /* Page table entry register LOW */ +#define MMU_TTB 0xFF000008 /* Translation table base register */ +#define MMU_TEA 0xFF00000C /* TLB Exception Address */ +#define MMU_PTEA 0xFF000034 /* Page table entry assistance register */ + +#define MMUCR 0xFF000010 /* MMU Control Register */ + +#define MMU_ITLB_ADDRESS_ARRAY 0xF2000000 +#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000 +#define MMU_PAGE_ASSOC_BIT 0x80 + +#define MMUCR_TI (1<<2) + +#ifdef CONFIG_X2TLB +#define MMUCR_ME (1 << 7) +#else +#define MMUCR_ME (0) +#endif + +#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40) +#define MMUCR_SE (1 << 4) +#else +#define MMUCR_SE (0) +#endif + +#ifdef CONFIG_SH_STORE_QUEUES +#define MMUCR_SQMD (1 << 9) +#else +#define MMUCR_SQMD (0) +#endif + +#define MMU_NTLB_ENTRIES 64 +#define MMU_CONTROL_INIT (0x05|MMUCR_SQMD|MMUCR_ME|MMUCR_SE) + +#define MMU_ITLB_DATA_ARRAY 0xF3000000 +#define MMU_UTLB_DATA_ARRAY 0xF7000000 + +#define MMU_UTLB_ENTRIES 64 +#define MMU_U_ENTRY_SHIFT 8 +#define MMU_UTLB_VALID 0x100 +#define MMU_ITLB_ENTRIES 4 +#define MMU_I_ENTRY_SHIFT 8 +#define MMU_ITLB_VALID 0x100 + +#define TRA 0xff000020 +#define EXPEVT 0xff000024 +#define INTEVT 0xff000028 + +#endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */ + diff --git a/arch/sh/include/cpu-sh4/cpu/rtc.h b/arch/sh/include/cpu-sh4/cpu/rtc.h new file mode 100644 index 00000000000..25b1e6adfe8 --- /dev/null +++ b/arch/sh/include/cpu-sh4/cpu/rtc.h @@ -0,0 +1,13 @@ +#ifndef __ASM_SH_CPU_SH4_RTC_H +#define __ASM_SH_CPU_SH4_RTC_H + +#ifdef CONFIG_CPU_SUBTYPE_SH7723 +#define rtc_reg_size sizeof(u16) +#else +#define rtc_reg_size sizeof(u32) +#endif + +#define RTC_BIT_INVERTED 0x40 /* bug on SH7750, SH7750S */ +#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR + +#endif /* __ASM_SH_CPU_SH4_RTC_H */ diff --git a/arch/sh/include/cpu-sh4/cpu/sigcontext.h b/arch/sh/include/cpu-sh4/cpu/sigcontext.h new file mode 100644 index 00000000000..ab392f120e0 --- /dev/null +++ b/arch/sh/include/cpu-sh4/cpu/sigcontext.h @@ -0,0 +1,24 @@ +#ifndef __ASM_CPU_SH4_SIGCONTEXT_H +#define __ASM_CPU_SH4_SIGCONTEXT_H + +struct sigcontext { + unsigned long oldmask; + + /* CPU registers */ + unsigned long sc_regs[16]; + unsigned long sc_pc; + unsigned long sc_pr; + unsigned long sc_sr; + unsigned long sc_gbr; + unsigned long sc_mach; + unsigned long sc_macl; + + /* FPU registers */ + unsigned long sc_fpregs[16]; + unsigned long sc_xfpregs[16]; + unsigned int sc_fpscr; + unsigned int sc_fpul; + unsigned int sc_ownedfp; +}; + +#endif /* __ASM_CPU_SH4_SIGCONTEXT_H */ diff --git a/arch/sh/include/cpu-sh4/cpu/sq.h b/arch/sh/include/cpu-sh4/cpu/sq.h new file mode 100644 index 00000000000..586d6491816 --- /dev/null +++ b/arch/sh/include/cpu-sh4/cpu/sq.h @@ -0,0 +1,35 @@ +/* + * include/asm-sh/cpu-sh4/sq.h + * + * Copyright (C) 2001, 2002, 2003 Paul Mundt + * Copyright (C) 2001, 2002 M. R. Brown + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH4_SQ_H +#define __ASM_CPU_SH4_SQ_H + +#include <asm/addrspace.h> + +/* + * Store queues range from e0000000-e3fffffc, allowing approx. 64MB to be + * mapped to any physical address space. Since data is written (and aligned) + * to 32-byte boundaries, we need to be sure that all allocations are aligned. + */ +#define SQ_SIZE 32 +#define SQ_ALIGN_MASK (~(SQ_SIZE - 1)) +#define SQ_ALIGN(addr) (((addr)+SQ_SIZE-1) & SQ_ALIGN_MASK) + +#define SQ_QACR0 (P4SEG_REG_BASE + 0x38) +#define SQ_QACR1 (P4SEG_REG_BASE + 0x3c) +#define SQ_ADDRMAX (P4SEG_STORE_QUE + 0x04000000) + +/* arch/sh/kernel/cpu/sh4/sq.c */ +unsigned long sq_remap(unsigned long phys, unsigned int size, + const char *name, unsigned long flags); +void sq_unmap(unsigned long vaddr); +void sq_flush_range(unsigned long start, unsigned int len); + +#endif /* __ASM_CPU_SH4_SQ_H */ diff --git a/arch/sh/include/cpu-sh4/cpu/timer.h b/arch/sh/include/cpu-sh4/cpu/timer.h new file mode 100644 index 00000000000..d1e796b9688 --- /dev/null +++ b/arch/sh/include/cpu-sh4/cpu/timer.h @@ -0,0 +1,60 @@ +/* + * include/asm-sh/cpu-sh4/timer.h + * + * Copyright (C) 2004 Lineo Solutions, Inc. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH4_TIMER_H +#define __ASM_CPU_SH4_TIMER_H + +/* + * --------------------------------------------------------------------------- + * TMU Common definitions for SH4 processors + * SH7750S/SH7750R + * SH7751/SH7751R + * SH7760 + * SH-X3 + * --------------------------------------------------------------------------- + */ +#ifdef CONFIG_CPU_SUBTYPE_SHX3 +#define TMU_012_BASE 0xffc10000 +#define TMU_345_BASE 0xffc20000 +#else +#define TMU_012_BASE 0xffd80000 +#define TMU_345_BASE 0xfe100000 +#endif + +#define TMU_TOCR TMU_012_BASE /* Not supported on all CPUs */ + +#define TMU_012_TSTR (TMU_012_BASE + 0x04) +#define TMU_345_TSTR (TMU_345_BASE + 0x04) + +#define TMU0_TCOR (TMU_012_BASE + 0x08) +#define TMU0_TCNT (TMU_012_BASE + 0x0c) +#define TMU0_TCR (TMU_012_BASE + 0x10) + +#define TMU1_TCOR (TMU_012_BASE + 0x14) +#define TMU1_TCNT (TMU_012_BASE + 0x18) +#define TMU1_TCR (TMU_012_BASE + 0x1c) + +#define TMU2_TCOR (TMU_012_BASE + 0x20) +#define TMU2_TCNT (TMU_012_BASE + 0x24) +#define TMU2_TCR (TMU_012_BASE + 0x28) +#define TMU2_TCPR (TMU_012_BASE + 0x2c) + +#define TMU3_TCOR (TMU_345_BASE + 0x08) +#define TMU3_TCNT (TMU_345_BASE + 0x0c) +#define TMU3_TCR (TMU_345_BASE + 0x10) + +#define TMU4_TCOR (TMU_345_BASE + 0x14) +#define TMU4_TCNT (TMU_345_BASE + 0x18) +#define TMU4_TCR (TMU_345_BASE + 0x1c) + +#define TMU5_TCOR (TMU_345_BASE + 0x20) +#define TMU5_TCNT (TMU_345_BASE + 0x24) +#define TMU5_TCR (TMU_345_BASE + 0x28) + +#endif /* __ASM_CPU_SH4_TIMER_H */ diff --git a/arch/sh/include/cpu-sh4/cpu/ubc.h b/arch/sh/include/cpu-sh4/cpu/ubc.h new file mode 100644 index 00000000000..c86e1705093 --- /dev/null +++ b/arch/sh/include/cpu-sh4/cpu/ubc.h @@ -0,0 +1,64 @@ +/* + * include/asm-sh/cpu-sh4/ubc.h + * + * Copyright (C) 1999 Niibe Yutaka + * Copyright (C) 2003 Paul Mundt + * Copyright (C) 2006 Lineo Solutions Inc. support SH4A UBC + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH4_UBC_H +#define __ASM_CPU_SH4_UBC_H + +#if defined(CONFIG_CPU_SH4A) +#define UBC_CBR0 0xff200000 +#define UBC_CRR0 0xff200004 +#define UBC_CAR0 0xff200008 +#define UBC_CAMR0 0xff20000c +#define UBC_CBR1 0xff200020 +#define UBC_CRR1 0xff200024 +#define UBC_CAR1 0xff200028 +#define UBC_CAMR1 0xff20002c +#define UBC_CDR1 0xff200030 +#define UBC_CDMR1 0xff200034 +#define UBC_CETR1 0xff200038 +#define UBC_CCMFR 0xff200600 +#define UBC_CBCR 0xff200620 + +/* CBR */ +#define UBC_CBR_AIE (0x01<<30) +#define UBC_CBR_ID_INST (0x01<<4) +#define UBC_CBR_RW_READ (0x01<<1) +#define UBC_CBR_CE (0x01) + +#define UBC_CBR_AIV_MASK (0x00FF0000) +#define UBC_CBR_AIV_SHIFT (16) +#define UBC_CBR_AIV_SET(asid) (((asid)<<UBC_CBR_AIV_SHIFT) & UBC_CBR_AIV_MASK) + +#define UBC_CBR_INIT 0x20000000 + +/* CRR */ +#define UBC_CRR_RES (0x01<<13) +#define UBC_CRR_PCB (0x01<<1) +#define UBC_CRR_BIE (0x01) + +#define UBC_CRR_INIT 0x00002000 + +#else /* CONFIG_CPU_SH4 */ +#define UBC_BARA 0xff200000 +#define UBC_BAMRA 0xff200004 +#define UBC_BBRA 0xff200008 +#define UBC_BASRA 0xff000014 +#define UBC_BARB 0xff20000c +#define UBC_BAMRB 0xff200010 +#define UBC_BBRB 0xff200014 +#define UBC_BASRB 0xff000018 +#define UBC_BDRB 0xff200018 +#define UBC_BDMRB 0xff20001c +#define UBC_BRCR 0xff200020 +#endif /* CONFIG_CPU_SH4 */ + +#endif /* __ASM_CPU_SH4_UBC_H */ + diff --git a/arch/sh/include/cpu-sh4/cpu/watchdog.h b/arch/sh/include/cpu-sh4/cpu/watchdog.h new file mode 100644 index 00000000000..259f6a0ce23 --- /dev/null +++ b/arch/sh/include/cpu-sh4/cpu/watchdog.h @@ -0,0 +1,25 @@ +/* + * include/asm-sh/cpu-sh4/watchdog.h + * + * Copyright (C) 2002, 2003 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH4_WATCHDOG_H +#define __ASM_CPU_SH4_WATCHDOG_H + +/* Register definitions */ +#define WTCNT 0xffc00008 +#define WTCSR 0xffc0000c + +/* Bit definitions */ +#define WTCSR_TME 0x80 +#define WTCSR_WT 0x40 +#define WTCSR_RSTS 0x20 +#define WTCSR_WOVF 0x10 +#define WTCSR_IOVF 0x08 + +#endif /* __ASM_CPU_SH4_WATCHDOG_H */ + |