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Diffstat (limited to 'arch/sh/kernel/cpu/sh3/probe.c')
-rw-r--r--arch/sh/kernel/cpu/sh3/probe.c42
1 files changed, 21 insertions, 21 deletions
diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c
index e6709883629..821b0ab7b52 100644
--- a/arch/sh/kernel/cpu/sh3/probe.c
+++ b/arch/sh/kernel/cpu/sh3/probe.c
@@ -50,41 +50,41 @@ int __init detect_cpu_and_cache_system(void)
back_to_P1();
- cpu_data->dcache.ways = 4;
- cpu_data->dcache.entry_shift = 4;
- cpu_data->dcache.linesz = L1_CACHE_BYTES;
- cpu_data->dcache.flags = 0;
+ current_cpu_data.dcache.ways = 4;
+ current_cpu_data.dcache.entry_shift = 4;
+ current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
+ current_cpu_data.dcache.flags = 0;
/*
* 7709A/7729 has 16K cache (256-entry), while 7702 has only
* 2K(direct) 7702 is not supported (yet)
*/
if (data0 == data1 && data2 == data3) { /* Shadow */
- cpu_data->dcache.way_incr = (1 << 11);
- cpu_data->dcache.entry_mask = 0x7f0;
- cpu_data->dcache.sets = 128;
- cpu_data->type = CPU_SH7708;
+ current_cpu_data.dcache.way_incr = (1 << 11);
+ current_cpu_data.dcache.entry_mask = 0x7f0;
+ current_cpu_data.dcache.sets = 128;
+ current_cpu_data.type = CPU_SH7708;
- cpu_data->flags |= CPU_HAS_MMU_PAGE_ASSOC;
+ current_cpu_data.flags |= CPU_HAS_MMU_PAGE_ASSOC;
} else { /* 7709A or 7729 */
- cpu_data->dcache.way_incr = (1 << 12);
- cpu_data->dcache.entry_mask = 0xff0;
- cpu_data->dcache.sets = 256;
- cpu_data->type = CPU_SH7729;
+ current_cpu_data.dcache.way_incr = (1 << 12);
+ current_cpu_data.dcache.entry_mask = 0xff0;
+ current_cpu_data.dcache.sets = 256;
+ current_cpu_data.type = CPU_SH7729;
#if defined(CONFIG_CPU_SUBTYPE_SH7706)
- cpu_data->type = CPU_SH7706;
+ current_cpu_data.type = CPU_SH7706;
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7710)
- cpu_data->type = CPU_SH7710;
+ current_cpu_data.type = CPU_SH7710;
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7705)
- cpu_data->type = CPU_SH7705;
+ current_cpu_data.type = CPU_SH7705;
#if defined(CONFIG_SH7705_CACHE_32KB)
- cpu_data->dcache.way_incr = (1 << 13);
- cpu_data->dcache.entry_mask = 0x1ff0;
- cpu_data->dcache.sets = 512;
+ current_cpu_data.dcache.way_incr = (1 << 13);
+ current_cpu_data.dcache.entry_mask = 0x1ff0;
+ current_cpu_data.dcache.sets = 512;
ctrl_outl(CCR_CACHE_32KB, CCR3);
#else
ctrl_outl(CCR_CACHE_16KB, CCR3);
@@ -95,8 +95,8 @@ int __init detect_cpu_and_cache_system(void)
/*
* SH-3 doesn't have separate caches
*/
- cpu_data->dcache.flags |= SH_CACHE_COMBINED;
- cpu_data->icache = cpu_data->dcache;
+ current_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
+ current_cpu_data.icache = current_cpu_data.dcache;
return 0;
}