diff options
Diffstat (limited to 'arch/sh')
| -rw-r--r-- | arch/sh/cchips/Kconfig | 33 | ||||
| -rw-r--r-- | arch/sh/cchips/hd6446x/Makefile | 1 | ||||
| -rw-r--r-- | arch/sh/cchips/hd6446x/hd64465/Makefile | 6 | ||||
| -rw-r--r-- | arch/sh/cchips/hd6446x/hd64465/gpio.c | 196 | ||||
| -rw-r--r-- | arch/sh/cchips/hd6446x/hd64465/io.c | 211 | ||||
| -rw-r--r-- | arch/sh/cchips/hd6446x/hd64465/setup.c | 181 | ||||
| -rw-r--r-- | arch/sh/include/asm/hd64465/gpio.h | 46 | ||||
| -rw-r--r-- | arch/sh/include/asm/hd64465/hd64465.h | 256 | ||||
| -rw-r--r-- | arch/sh/include/asm/hd64465/io.h | 44 | ||||
| -rw-r--r-- | arch/sh/include/asm/serial.h | 17 | ||||
| -rw-r--r-- | arch/sh/tools/mach-types | 1 |
11 files changed, 0 insertions, 992 deletions
diff --git a/arch/sh/cchips/Kconfig b/arch/sh/cchips/Kconfig index 7892361eedc..f43d18373f2 100644 --- a/arch/sh/cchips/Kconfig +++ b/arch/sh/cchips/Kconfig @@ -22,20 +22,6 @@ config HD64461 Say Y if you want support for the HD64461. Otherwise, say N. -config HD64465 - bool "Hitachi HD64465 companion chip support" - ---help--- - The Hitachi HD64465 provides an interface for - the SH7750 CPU, supporting a LCD controller, - CRT color controller, IrDA, USB, PCMCIA, - keyboard controller, and a printer interface. - - More information is available at - <http://global.hitachi.com/New/cnews/E/1998/981019B.html>. - - Say Y if you want support for the HD64465. - Otherwise, say N. - endchoice # These will also be split into the Kconfig's below @@ -61,23 +47,4 @@ config HD64461_ENABLER via the HD64461 companion chip. Otherwise, say N. -config HD64465_IOBASE - hex "HD64465 start address" - depends on HD64465 - default "0xb0000000" - help - The default setting of the HD64465 IO base address is 0xb0000000. - - Do not change this unless you know what you are doing. - -config HD64465_IRQ - int "HD64465 IRQ" - depends on HD64465 - default "5" - help - The default setting of the HD64465 IRQ is 5. - - Do not change this unless you know what you are doing. - endmenu - diff --git a/arch/sh/cchips/hd6446x/Makefile b/arch/sh/cchips/hd6446x/Makefile index f7de4076e24..9682e3ab668 100644 --- a/arch/sh/cchips/hd6446x/Makefile +++ b/arch/sh/cchips/hd6446x/Makefile @@ -1,4 +1,3 @@ obj-$(CONFIG_HD64461) += hd64461.o -obj-$(CONFIG_HD64465) += hd64465/ EXTRA_CFLAGS += -Werror diff --git a/arch/sh/cchips/hd6446x/hd64465/Makefile b/arch/sh/cchips/hd6446x/hd64465/Makefile deleted file mode 100644 index f66edcb52c5..00000000000 --- a/arch/sh/cchips/hd6446x/hd64465/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# Makefile for the HD64465 -# - -obj-y := setup.o io.o gpio.o - diff --git a/arch/sh/cchips/hd6446x/hd64465/gpio.c b/arch/sh/cchips/hd6446x/hd64465/gpio.c deleted file mode 100644 index 43431855ec8..00000000000 --- a/arch/sh/cchips/hd6446x/hd64465/gpio.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * $Id: gpio.c,v 1.4 2003/05/19 22:24:18 lethal Exp $ - * by Greg Banks <gbanks@pocketpenguins.com> - * (c) 2000 PocketPenguins Inc - * - * GPIO pin support for HD64465 companion chip. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/module.h> -#include <linux/sched.h> -#include <linux/ioport.h> -#include <asm/io.h> -#include <asm/hd64465/gpio.h> - -#define _PORTOF(portpin) (((portpin)>>3)&0x7) -#define _PINOF(portpin) ((portpin)&0x7) - -/* Register addresses parametrised on port */ -#define GPIO_CR(port) (HD64465_REG_GPACR+((port)<<1)) -#define GPIO_DR(port) (HD64465_REG_GPADR+((port)<<1)) -#define GPIO_ICR(port) (HD64465_REG_GPAICR+((port)<<1)) -#define GPIO_ISR(port) (HD64465_REG_GPAISR+((port)<<1)) - -#define GPIO_NPORTS 5 - -#define MODNAME "hd64465_gpio" - -EXPORT_SYMBOL(hd64465_gpio_configure); -EXPORT_SYMBOL(hd64465_gpio_get_pin); -EXPORT_SYMBOL(hd64465_gpio_get_port); -EXPORT_SYMBOL(hd64465_gpio_register_irq); -EXPORT_SYMBOL(hd64465_gpio_set_pin); -EXPORT_SYMBOL(hd64465_gpio_set_port); -EXPORT_SYMBOL(hd64465_gpio_unregister_irq); - -/* TODO: each port should be protected with a spinlock */ - - -void hd64465_gpio_configure(int portpin, int direction) -{ - unsigned short cr; - unsigned int shift = (_PINOF(portpin)<<1); - - cr = inw(GPIO_CR(_PORTOF(portpin))); - cr &= ~(3<<shift); - cr |= direction<<shift; - outw(cr, GPIO_CR(_PORTOF(portpin))); -} - -void hd64465_gpio_set_pin(int portpin, unsigned int value) -{ - unsigned short d; - unsigned short mask = 1<<(_PINOF(portpin)); - - d = inw(GPIO_DR(_PORTOF(portpin))); - if (value) - d |= mask; - else - d &= ~mask; - outw(d, GPIO_DR(_PORTOF(portpin))); -} - -unsigned int hd64465_gpio_get_pin(int portpin) -{ - return inw(GPIO_DR(_PORTOF(portpin))) & (1<<(_PINOF(portpin))); -} - -/* TODO: for cleaner atomicity semantics, add a mask to this routine */ - -void hd64465_gpio_set_port(int port, unsigned int value) -{ - outw(value, GPIO_DR(port)); -} - -unsigned int hd64465_gpio_get_port(int port) -{ - return inw(GPIO_DR(port)); -} - - -static struct { - void (*func)(int portpin, void *dev); - void *dev; -} handlers[GPIO_NPORTS * 8]; - -static irqreturn_t hd64465_gpio_interrupt(int irq, void *dev) -{ - unsigned short port, pin, isr, mask, portpin; - - for (port=0 ; port<GPIO_NPORTS ; port++) { - isr = inw(GPIO_ISR(port)); - - for (pin=0 ; pin<8 ; pin++) { - mask = 1<<pin; - if (isr & mask) { - portpin = (port<<3)|pin; - if (handlers[portpin].func != 0) - handlers[portpin].func(portpin, handlers[portpin].dev); - else - printk(KERN_NOTICE "unexpected GPIO interrupt, pin %c%d\n", - port+'A', (int)pin); - } - } - - /* Write 1s back to ISR to clear it? That's what the manual says.. */ - outw(isr, GPIO_ISR(port)); - } - - return IRQ_HANDLED; -} - -void hd64465_gpio_register_irq(int portpin, int mode, - void (*handler)(int portpin, void *dev), void *dev) -{ - unsigned long flags; - unsigned short icr, mask; - - if (handler == 0) - return; - - local_irq_save(flags); - - handlers[portpin].func = handler; - handlers[portpin].dev = dev; - - /* - * Configure Interrupt Control Register - */ - icr = inw(GPIO_ICR(_PORTOF(portpin))); - mask = (1<<_PINOF(portpin)); - - /* unmask interrupt */ - icr &= ~mask; - - /* set TS bit */ - mask <<= 8; - icr &= ~mask; - if (mode == HD64465_GPIO_RISING) - icr |= mask; - - outw(icr, GPIO_ICR(_PORTOF(portpin))); - - local_irq_restore(flags); -} - -void hd64465_gpio_unregister_irq(int portpin) -{ - unsigned long flags; - unsigned short icr; - - local_irq_save(flags); - - /* - * Configure Interrupt Control Register - */ - icr = inw(GPIO_ICR(_PORTOF(portpin))); - icr |= (1<<_PINOF(portpin)); /* mask interrupt */ - outw(icr, GPIO_ICR(_PORTOF(portpin))); - - handlers[portpin].func = 0; - handlers[portpin].dev = 0; - - local_irq_restore(flags); -} - -static int __init hd64465_gpio_init(void) -{ - if (!request_region(HD64465_REG_GPACR, 0x1000, MODNAME)) - return -EBUSY; - if (request_irq(HD64465_IRQ_GPIO, hd64465_gpio_interrupt, - IRQF_DISABLED, MODNAME, 0)) - goto out_irqfailed; - - printk("HD64465 GPIO layer on irq %d\n", HD64465_IRQ_GPIO); - - return 0; - -out_irqfailed: - release_region(HD64465_REG_GPACR, 0x1000); - - return -EINVAL; -} - -static void __exit hd64465_gpio_exit(void) -{ - release_region(HD64465_REG_GPACR, 0x1000); - free_irq(HD64465_IRQ_GPIO, 0); -} - -module_init(hd64465_gpio_init); -module_exit(hd64465_gpio_exit); - -MODULE_LICENSE("GPL"); - diff --git a/arch/sh/cchips/hd6446x/hd64465/io.c b/arch/sh/cchips/hd6446x/hd64465/io.c deleted file mode 100644 index 58704d066ae..00000000000 --- a/arch/sh/cchips/hd6446x/hd64465/io.c +++ /dev/null @@ -1,211 +0,0 @@ -/* - * $Id: io.c,v 1.4 2003/08/03 03:05:10 lethal Exp $ - * by Greg Banks <gbanks@pocketpenguins.com> - * (c) 2000 PocketPenguins Inc - * - * Derived from io_hd64461.c, which bore the message: - * Copyright (C) 2000 YAEGASHI Takeshi - * - * Typical I/O routines for HD64465 system. - */ - -#include <linux/kernel.h> -#include <linux/module.h> -#include <asm/io.h> -#include <asm/hd64465/hd64465.h> - - -#define HD64465_DEBUG 0 - -#if HD64465_DEBUG -#define DPRINTK(args...) printk(args) -#define DIPRINTK(n, args...) if (hd64465_io_debug>(n)) printk(args) -#else -#define DPRINTK(args...) -#define DIPRINTK(n, args...) -#endif - - - -/* This is a hack suitable only for debugging IO port problems */ -int hd64465_io_debug; -EXPORT_SYMBOL(hd64465_io_debug); - -/* Low iomap maps port 0-1K to addresses in 8byte chunks */ -#define HD64465_IOMAP_LO_THRESH 0x400 -#define HD64465_IOMAP_LO_SHIFT 3 -#define HD64465_IOMAP_LO_MASK ((1<<HD64465_IOMAP_LO_SHIFT)-1) -#define HD64465_IOMAP_LO_NMAP (HD64465_IOMAP_LO_THRESH>>HD64465_IOMAP_LO_SHIFT) -static unsigned long hd64465_iomap_lo[HD64465_IOMAP_LO_NMAP]; -static unsigned char hd64465_iomap_lo_shift[HD64465_IOMAP_LO_NMAP]; - -/* High iomap maps port 1K-64K to addresses in 1K chunks */ -#define HD64465_IOMAP_HI_THRESH 0x10000 -#define HD64465_IOMAP_HI_SHIFT 10 -#define HD64465_IOMAP_HI_MASK ((1<<HD64465_IOMAP_HI_SHIFT)-1) -#define HD64465_IOMAP_HI_NMAP (HD64465_IOMAP_HI_THRESH>>HD64465_IOMAP_HI_SHIFT) -static unsigned long hd64465_iomap_hi[HD64465_IOMAP_HI_NMAP]; -static unsigned char hd64465_iomap_hi_shift[HD64465_IOMAP_HI_NMAP]; - -#define PORT2ADDR(x) (sh_mv.mv_isa_port2addr(x)) - -void hd64465_port_map(unsigned short baseport, unsigned int nports, - unsigned long addr, unsigned char shift) -{ - unsigned int port, endport = baseport + nports; - - DPRINTK("hd64465_port_map(base=0x%04hx, n=0x%04hx, addr=0x%08lx,endport=0x%04x)\n", - baseport, nports, addr,endport); - - for (port = baseport ; - port < endport && port < HD64465_IOMAP_LO_THRESH ; - port += (1<<HD64465_IOMAP_LO_SHIFT)) { - DPRINTK(" maplo[0x%x] = 0x%08lx\n", port, addr); - hd64465_iomap_lo[port>>HD64465_IOMAP_LO_SHIFT] = addr; - hd64465_iomap_lo_shift[port>>HD64465_IOMAP_LO_SHIFT] = shift; - addr += (1<<(HD64465_IOMAP_LO_SHIFT)); - } - - for (port = max_t(unsigned int, baseport, HD64465_IOMAP_LO_THRESH); - port < endport && port < HD64465_IOMAP_HI_THRESH ; - port += (1<<HD64465_IOMAP_HI_SHIFT)) { - DPRINTK(" maphi[0x%x] = 0x%08lx\n", port, addr); - hd64465_iomap_hi[port>>HD64465_IOMAP_HI_SHIFT] = addr; - hd64465_iomap_hi_shift[port>>HD64465_IOMAP_HI_SHIFT] = shift; - addr += (1<<(HD64465_IOMAP_HI_SHIFT)); - } -} -EXPORT_SYMBOL(hd64465_port_map); - -void hd64465_port_unmap(unsigned short baseport, unsigned int nports) -{ - unsigned int port, endport = baseport + nports; - - DPRINTK("hd64465_port_unmap(base=0x%04hx, n=0x%04hx)\n", - baseport, nports); - - for (port = baseport ; - port < endport && port < HD64465_IOMAP_LO_THRESH ; - port += (1<<HD64465_IOMAP_LO_SHIFT)) { - hd64465_iomap_lo[port>>HD64465_IOMAP_LO_SHIFT] = 0; - } - - for (port = max_t(unsigned int, baseport, HD64465_IOMAP_LO_THRESH); - port < endport && port < HD64465_IOMAP_HI_THRESH ; - port += (1<<HD64465_IOMAP_HI_SHIFT)) { - hd64465_iomap_hi[port>>HD64465_IOMAP_HI_SHIFT] = 0; - } -} -EXPORT_SYMBOL(hd64465_port_unmap); - -unsigned long hd64465_isa_port2addr(unsigned long port) -{ - unsigned long addr = 0; - unsigned char shift; - - /* handle remapping of low IO ports */ - if (port < HD64465_IOMAP_LO_THRESH) { - addr = hd64465_iomap_lo[port >> HD64465_IOMAP_LO_SHIFT]; - shift = hd64465_iomap_lo_shift[port >> HD64465_IOMAP_LO_SHIFT]; - if (addr != 0) - addr += (port & HD64465_IOMAP_LO_MASK) << shift; - else - printk(KERN_NOTICE "io_hd64465: access to un-mapped port %lx\n", port); - } else if (port < HD64465_IOMAP_HI_THRESH) { - addr = hd64465_iomap_hi[port >> HD64465_IOMAP_HI_SHIFT]; - shift = hd64465_iomap_hi_shift[port >> HD64465_IOMAP_HI_SHIFT]; - if (addr != 0) - addr += (port & HD64465_IOMAP_HI_MASK) << shift; - else - printk(KERN_NOTICE "io_hd64465: access to un-mapped port %lx\n", port); - } - - /* HD64465 internal devices (0xb0000000) */ - else if (port < 0x20000) - addr = CONFIG_HD64465_IOBASE + port - 0x10000; - - /* Whole physical address space (0xa0000000) */ - else - addr = P2SEGADDR(port); - - DIPRINTK(2, "PORT2ADDR(0x%08lx) = 0x%08lx\n", port, addr); - - return addr; -} - -static inline void delay(void) -{ - ctrl_inw(0xa0000000); -} - -unsigned char hd64465_inb(unsigned long port) -{ - unsigned long addr = PORT2ADDR(port); - unsigned long b = (addr == 0 ? 0 : *(volatile unsigned char*)addr); - - DIPRINTK(0, "inb(%08lx) = %02x\n", addr, (unsigned)b); - return b; -} - -unsigned char hd64465_inb_p(unsigned long port) -{ - unsigned long v; - unsigned long addr = PORT2ADDR(port); - - v = (addr == 0 ? 0 : *(volatile unsigned char*)addr); - delay(); - DIPRINTK(0, "inb_p(%08lx) = %02x\n", addr, (unsigned)v); - return v; -} - -unsigned short hd64465_inw(unsigned long port) -{ - unsigned long addr = PORT2ADDR(port); - unsigned long b = (addr == 0 ? 0 : *(volatile unsigned short*)addr); - DIPRINTK(0, "inw(%08lx) = %04lx\n", addr, b); - return b; -} - -unsigned int hd64465_inl(unsigned long port) -{ - unsigned long addr = PORT2ADDR(port); - unsigned int b = (addr == 0 ? 0 : *(volatile unsigned long*)addr); - DIPRINTK(0, "inl(%08lx) = %08x\n", addr, b); - return b; -} - -void hd64465_outb(unsigned char b, unsigned long port) -{ - unsigned long addr = PORT2ADDR(port); - - DIPRINTK(0, "outb(%02x, %08lx)\n", (unsigned)b, addr); - if (addr != 0) - *(volatile unsigned char*)addr = b; -} - -void hd64465_outb_p(unsigned char b, unsigned long port) -{ - unsigned long addr = PORT2ADDR(port); - - DIPRINTK(0, "outb_p(%02x, %08lx)\n", (unsigned)b, addr); - if (addr != 0) - *(volatile unsigned char*)addr = b; - delay(); -} - -void hd64465_outw(unsigned short b, unsigned long port) -{ - unsigned long addr = PORT2ADDR(port); - DIPRINTK(0, "outw(%04x, %08lx)\n", (unsigned)b, addr); - if (addr != 0) - *(volatile unsigned short*)addr = b; -} - -void hd64465_outl(unsigned int b, unsigned long port) -{ - unsigned long addr = PORT2ADDR(port); - DIPRINTK(0, "outl(%08x, %08lx)\n", b, addr); - if (addr != 0) - *(volatile unsigned long*)addr = b; -} - diff --git a/arch/sh/cchips/hd6446x/hd64465/setup.c b/arch/sh/cchips/hd6446x/hd64465/setup.c deleted file mode 100644 index 9b8820c3670..00000000000 --- a/arch/sh/cchips/hd6446x/hd64465/setup.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * $Id: setup.c,v 1.4 2003/08/03 03:05:10 lethal Exp $ - * - * Setup and IRQ handling code for the HD64465 companion chip. - * by Greg Banks <gbanks@pocketpenguins.com> - * Copyright (c) 2000 PocketPenguins Inc - * - * Derived from setup_hd64461.c which bore the message: - * Copyright (C) 2000 YAEGASHI Takeshi - */ - -#include <linux/sched.h> -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/param.h> -#include <linux/ioport.h> -#include <linux/interrupt.h> -#include <linux/init.h> -#include <linux/irq.h> -#include <asm/io.h> -#include <asm/irq.h> -#include <asm/hd64465/hd64465.h> - -static void disable_hd64465_irq(unsigned int irq) -{ - unsigned short nimr; - unsigned short mask = 1 << (irq - HD64465_IRQ_BASE); - - pr_debug("disable_hd64465_irq(%d): mask=%x\n", irq, mask); - nimr = inw(HD64465_REG_NIMR); - nimr |= mask; - outw(nimr, HD64465_REG_NIMR); -} - -static void enable_hd64465_irq(unsigned int irq) -{ - unsigned short nimr; - unsigned short mask = 1 << (irq - HD64465_IRQ_BASE); - - pr_debug("enable_hd64465_irq(%d): mask=%x\n", irq, mask); - nimr = inw(HD64465_REG_NIMR); - nimr &= ~mask; - outw(nimr, HD64465_REG_NIMR); -} - -static void mask_and_ack_hd64465(unsigned int irq) -{ - disable_hd64465_irq(irq); -} - -static void end_hd64465_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_hd64465_irq(irq); -} - -static unsigned int startup_hd64465_irq(unsigned int irq) -{ - enable_hd64465_irq(irq); - return 0; -} - -static void shutdown_hd64465_irq(unsigned int irq) -{ - disable_hd64465_irq(irq); -} - -static struct hw_interrupt_type hd64465_irq_type = { - .typename = "HD64465-IRQ", - .startup = startup_hd64465_irq, - .shutdown = shutdown_hd64465_irq, - .enable = enable_hd64465_irq, - .disable = disable_hd64465_irq, - .ack = mask_and_ack_hd64465, - .end = end_hd64465_irq, -}; - -static irqreturn_t hd64465_interrupt(int irq, void *dev_id) -{ - printk(KERN_INFO - "HD64465: spurious interrupt, nirr: 0x%x nimr: 0x%x\n", - inw(HD64465_REG_NIRR), inw(HD64465_REG_NIMR)); - - return IRQ_NONE; -} - -/* - * Support for a secondary IRQ demux step. This is necessary - * because the HD64465 presents a very thin interface to the - * PCMCIA bus; a lot of features (such as remapping interrupts) - * normally done in hardware by other PCMCIA host bridges is - * instead done in software. - */ -static struct { - int (*func)(int, void *); - void *dev; -} hd64465_demux[HD64465_IRQ_NUM]; - -void hd64465_register_irq_demux(int irq, - int (*demux)(int irq, void *dev), void *dev) -{ - hd64465_demux[irq - HD64465_IRQ_BASE].func = demux; - hd64465_demux[irq - HD64465_IRQ_BASE].dev = dev; -} -EXPORT_SYMBOL(hd64465_register_irq_demux); - -void hd64465_unregister_irq_demux(int irq) -{ - hd64465_demux[irq - HD64465_IRQ_BASE].func = 0; -} -EXPORT_SYMBOL(hd64465_unregister_irq_demux); - -int hd64465_irq_demux(int irq) -{ - if (irq == CONFIG_HD64465_IRQ) { - unsigned short i, bit; - unsigned short nirr = inw(HD64465_REG_NIRR); - unsigned short nimr = inw(HD64465_REG_NIMR); - - pr_debug("hd64465_irq_demux, nirr=%04x, nimr=%04x\n", nirr, nimr); - nirr &= ~nimr; - for (bit = 1, i = 0 ; i < HD64465_IRQ_NUM ; bit <<= 1, i++) - if (nirr & bit) - break; - - if (i < HD64465_IRQ_NUM) { - irq = HD64465_IRQ_BASE + i; - if (hd64465_demux[i].func != 0) - irq = hd64465_demux[i].func(irq, hd64465_demux[i].dev); - } - } - return irq; -} - -static struct irqaction irq0 = { - .handler = hd64465_interrupt, - .flags = IRQF_DISABLED, - .mask = CPU_MASK_NONE, - .name = "HD64465", -}; - -static int __init setup_hd64465(void) -{ - int i; - unsigned short rev; - unsigned short smscr; - - if (!MACH_HD64465) - return 0; - - printk(KERN_INFO "HD64465 configured at 0x%x on irq %d(mapped into %d to %d)\n", - CONFIG_HD64465_IOBASE, - CONFIG_HD64465_IRQ, - HD64465_IRQ_BASE, - HD64465_IRQ_BASE+HD64465_IRQ_NUM-1); - - if (inw(HD64465_REG_SDID) != HD64465_SDID) { - printk(KERN_ERR "HD64465 device ID not found, check base address\n"); - } - - rev = inw(HD64465_REG_SRR); - printk(KERN_INFO "HD64465 hardware revision %d.%d\n", (rev >> 8) & 0xff, rev & 0xff); - - outw(0xffff, HD64465_REG_NIMR); /* mask all interrupts */ - - for (i = 0; i < HD64465_IRQ_NUM ; i++) { - irq_desc[HD64465_IRQ_BASE + i].chip = &hd64465_irq_type; - } - - setup_irq(CONFIG_HD64465_IRQ, &irq0); - - /* wake up the UART from STANDBY at this point */ - smscr = inw(HD64465_REG_SMSCR); - outw(smscr & (~HD64465_SMSCR_UARTST), HD64465_REG_SMSCR); - - /* remap IO ports for first ISA serial port to HD64465 UART */ - hd64465_port_map(0x3f8, 8, CONFIG_HD64465_IOBASE + 0x8000, 1); - - return 0; -} -module_init(setup_hd64465); diff --git a/arch/sh/include/asm/hd64465/gpio.h b/arch/sh/include/asm/hd64465/gpio.h deleted file mode 100644 index a3cdca2713d..00000000000 --- a/arch/sh/include/asm/hd64465/gpio.h +++ /dev/null @@ -1,46 +0,0 @@ -#ifndef _ASM_SH_HD64465_GPIO_ -#define _ASM_SH_HD64465_GPIO_ 1 -/* - * $Id: gpio.h,v 1.3 2003/05/04 19:30:14 lethal Exp $ - * - * Hitachi HD64465 companion chip: General Purpose IO pins support. - * This layer enables other device drivers to configure GPIO - * pins, get and set their values, and register an interrupt - * routine for when input pins change in hardware. - * - * by Greg Banks <gbanks@pocketpenguins.com> - * (c) 2000 PocketPenguins Inc. - */ -#include <asm/hd64465.h> - -/* Macro to construct a portpin number (used in all - * subsequent functions) from a port letter and a pin - * number, e.g. HD64465_GPIO_PORTPIN('A', 5). - */ -#define HD64465_GPIO_PORTPIN(port,pin) (((port)-'A')<<3|(pin)) - -/* Pin configuration constants for _configure() */ -#define HD64465_GPIO_FUNCTION2 0 /* use the pin's *other* function */ -#define HD64465_GPIO_OUT 1 /* output */ -#define HD64465_GPIO_IN_PULLUP 2 /* input, pull-up MOS on */ -#define HD64465_GPIO_IN 3 /* input */ - -/* Configure a pin's direction */ -extern void hd64465_gpio_configure(int portpin, int direction); - -/* Get, set value */ -extern void hd64465_gpio_set_pin(int portpin, unsigned int value); -extern unsigned int hd64465_gpio_get_pin(int portpin); -extern void hd64465_gpio_set_port(int port, unsigned int value); -extern unsigned int hd64465_gpio_get_port(int port); - -/* mode constants for _register_irq() */ -#define HD64465_GPIO_FALLING 0 -#define HD64465_GPIO_RISING 1 - -/* Interrupt on external value change */ -extern void hd64465_gpio_register_irq(int portpin, int mode, - void (*handler)(int portpin, void *dev), void *dev); -extern void hd64465_gpio_unregister_irq(int portpin); - -#endif /* _ASM_SH_HD64465_GPIO_ */ diff --git a/arch/sh/include/asm/hd64465/hd64465.h b/arch/sh/include/asm/hd64465/hd64465.h deleted file mode 100644 index cfd0e803d2a..00000000000 --- a/arch/sh/include/asm/hd64465/hd64465.h +++ /dev/null @@ -1,256 +0,0 @@ -#ifndef _ASM_SH_HD64465_ -#define _ASM_SH_HD64465_ 1 -/* - * $Id: hd64465.h,v 1.3 2003/05/04 19:30:15 lethal Exp $ - * - * Hitachi HD64465 companion chip support - * - * by Greg Banks <gbanks@pocketpenguins.com> - * (c) 2000 PocketPenguins Inc. - * - * Derived from <asm/hd64461.h> which bore the message: - * Copyright (C) 2000 YAEGASHI Takeshi - */ -#include <asm/io.h> -#include <asm/irq.h> - -/* - * Note that registers are defined here as virtual port numbers, - * which have no meaning except to get translated by hd64465_isa_port2addr() - * to an address in the range 0xb0000000-0xb3ffffff. Note that - * this translation happens to consist of adding the lower 16 bits - * of the virtual port number to 0xb0000000. Note also that the manual - * shows addresses as absolute physical addresses starting at 0x10000000, - * so e.g. the NIRR register is listed as 0x15000 here, 0x10005000 in the - * manual, and accessed using address 0xb0005000 - Greg. - */ - -/* System registers */ -#define HD64465_REG_SRR 0x1000c /* System Revision Register */ -#define HD64465_REG_SDID 0x10010 /* System Device ID Reg */ -#define HD64465_SDID 0x8122 /* 64465 device ID */ - -/* Power Management registers */ -#define HD64465_REG_SMSCR 0x10000 /* System Module Standby Control Reg */ -#define HD64465_SMSCR_PS2ST 0x4000 /* PS/2 Standby */ -#define HD64465_SMSCR_ADCST 0x1000 /* ADC Standby */ -#define HD64465_SMSCR_UARTST 0x0800 /* UART Standby */ -#define HD64465_SMSCR_SCDIST 0x0200 /* Serial Codec Standby */ -#define HD64465_SMSCR_PPST 0x0100 /* Parallel Port Standby */ -#define HD64465_SMSCR_PC0ST 0x0040 /* PCMCIA0 Standby */ -#define HD64465_SMSCR_PC1ST 0x0020 /* PCMCIA1 Standby */ -#define HD64465_SMSCR_AFEST 0x0010 /* AFE Standby */ -#define HD64465_SMSCR_TM0ST 0x0008 /* Timer0 Standby */ -#define HD64465_SMSCR_TM1ST 0x0004 /* Timer1 Standby */ -#define HD64465_SMSCR_IRDAST 0x0002 /* IRDA Standby */ -#define HD64465_SMSCR_KBCST 0x0001 /* Keyboard Controller Standby */ - -/* Interrupt Controller registers */ -#define HD64465_REG_NIRR 0x15000 /* Interrupt Request Register */ -#define HD64465_REG_NIMR 0x15002 /* Interrupt Mask Register */ -#define HD64465_REG_NITR 0x15004 /* Interrupt Trigger Mode Register */ - -/* Timer registers */ -#define HD64465_REG_TCVR1 0x16000 /* Timer 1 constant value register */ -#define HD64465_REG_TCVR0 0x16002 /* Timer 0 constant value register */ -#define HD64465_REG_TRVR1 0x16004 /* Timer 1 read value register */ -#define HD64465_REG_TRVR0 0x16006 /* Timer 0 read value register */ -#define HD64465_REG_TCR1 0x16008 /* Timer 1 control register */ -#define HD64465_REG_TCR0 0x1600A /* Timer 0 control register */ -#define HD64465_TCR_EADT 0x10 /* Enable ADTRIG# signal */ -#define HD64465_TCR_ETMO 0x08 /* Enable TMO signal */ -#define HD64465_TCR_PST_MASK 0x06 /* Clock Prescale */ -#define HD64465_TCR_PST_1 0x06 /* 1:1 */ -#define HD64465_TCR_PST_4 0x04 /* 1:4 */ -#define HD64465_TCR_PST_8 0x02 /* 1:8 */ -#define HD64465_TCR_PST_16 0x00 /* 1:16 */ -#define HD64465_TCR_TSTP 0x01 /* Start/Stop timer */ -#define HD64465_REG_TIRR 0x1600C /* Timer interrupt request register */ -#define HD64465_REG_TIDR 0x1600E /* Timer interrupt disable register */ -#define HD64465_REG_PWM1CS 0x16010 /* PWM 1 clock scale register */ -#define HD64465_REG_PWM1LPC 0x16012 /* PWM 1 low pulse width counter register */ -#define HD64465_REG_PWM1HPC 0x16014 /* PWM 1 high pulse width counter register */ -#define HD64465_REG_PWM0CS 0x16018 /* PWM 0 clock scale register */ -#define HD64465_REG_PWM0LPC 0x1601A /* PWM 0 low pulse width counter register */ -#define HD64465_REG_PWM0HPC 0x1601C /* PWM 0 high pulse width counter register */ - -/* Analog/Digital Converter registers */ -#define HD64465_REG_ADDRA 0x1E000 /* A/D data register A */ -#define HD64465_REG_ADDRB 0x1E002 /* A/D data register B */ -#define HD64465_REG_ADDRC 0x1E004 /* A/D data register C */ -#define HD64465_REG_ADDRD 0x1E006 /* A/D data register D */ -#define HD64465_REG_ADCSR 0x1E008 /* A/D control/status register */ -#define HD64465_ADCSR_ADF 0x80 /* A/D End Flag */ -#define HD64465_ADCSR_ADST 0x40 /* A/D Start Flag */ -#define HD64465_ADCSR_ADIS 0x20 /* A/D Interrupt Status */ -#define HD64465_ADCSR_TRGE 0x10 /* A/D Trigger Enable */ -#define HD64465_ADCSR_ADIE 0x08 /* A/D Interrupt Enable */ -#define HD64465_ADCSR_SCAN 0x04 /* A/D Scan Mode */ -#define HD64465_ADCSR_CH_MASK 0x03 /* A/D Channel */ -#define HD64465_REG_ADCALCR 0x1E00A /* A/D calibration sample control */ -#define HD64465_REG_ADCAL 0x1E00C /* A/D calibration data register */ - - -/* General Purpose I/O ports registers */ -#define HD64465_REG_GPACR 0x14000 /* Port A Control Register */ -#define HD64465_REG_GPBCR 0x14002 /* Port B Control Register */ -#define HD64465_REG_GPCCR 0x14004 /* Port C Control Register */ -#define HD64465_REG_GPDCR 0x14006 /* Port D Control Register */ -#define HD64465_REG_GPECR 0x14008 /* Port E Control Register */ -#define HD64465_REG_GPADR 0x14010 /* Port A Data Register */ -#define HD64465_REG_GPBDR 0x14012 /* Port B Data Register */ -#define HD64465_REG_GPCDR 0x14014 /* Port C Data Register */ -#define HD64465_REG_GPDDR 0x14016 /* Port D Data Register */ -#define HD64465_REG_GPEDR 0x14018 /* Port E Data Register */ -#define HD64465_REG_GPAICR 0x14020 /* Port A Interrupt Control Register */ -#define HD64465_REG_GPBICR 0x14022 /* Port B Interrupt Control Register */ -#define HD64465_REG_GPCICR 0x14024 /* Port C Interrupt Control Register */ -#define HD64465_REG_GPDICR 0x14026 /* Port D Interrupt Control Register */ -#define HD64465_REG_GPEICR 0x14028 /* Port E Interrupt Control Register */ -#define HD64465_REG_GPAISR 0x14040 /* Port A Interrupt Status Register */ -#define HD64465_REG_GPBISR 0x14042 /* Port B Interrupt Status Register */ -#define HD64465_REG_GPCISR 0x14044 /* Port C Interrupt Status Register */ -#define HD64465_REG_GPDISR 0x14046 /* Port D Interrupt Status Register */ -#define HD64465_REG_GPEISR 0x14048 /* Port E Interrupt Status Register */ - -/* PCMCIA bridge interface */ -#define HD64465_REG_PCC0ISR 0x12000 /* socket 0 interface status */ -#define HD64465_PCCISR_PREADY 0x80 /* mem card ready / io card IREQ */ -#define HD64465_PCCISR_PIREQ 0x80 -#define HD64465_PCCISR_PMWP 0x40 /* mem card write-protected */ -#define HD64465_PCCISR_PVS2 0x20 /* voltage select pin 2 */ -#define HD64465_PCCISR_PVS1 0x10 /* voltage select pin 1 */ -#define HD64465_PCCISR_PCD_MASK 0x0c /* card detect */ -#define HD64465_PCCISR_PBVD_MASK 0x03 /* battery voltage */ -#define HD64465_PCCISR_PBVD_BATGOOD 0x03 /* battery good */ -#define HD64465_PCCISR_PBVD_BATWARN 0x01 /* battery low warning */ -#define HD64465_PCCISR_PBVD_BATDEAD1 0x02 /* battery dead */ -#define HD64465_PCCISR_PBVD_BATDEAD2 0x00 /* battery dead */ -#define HD64465_REG_PCC0GCR 0x12002 /* socket 0 general control */ -#define HD64465_PCCGCR_PDRV 0x80 /* output drive */ -#define HD64465_PCCGCR_PCCR 0x40 /* PC card reset */ -#define HD64465_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */ -#define HD64465_PCCGCR_PVCC0 0x10 /* voltage control pin VCC0SEL0 */ -#define HD64465_PCCGCR_PMMOD 0x08 /* memory mode */ -#define HD64465_PCCGCR_PPA25 0x04 /* pin A25 */ -#define HD64465_PCCGCR_PPA24 0x02 /* pin A24 */ -#define HD64465_PCCGCR_PREG 0x01 /* ping PCC0REG# */ -#define HD64465_REG_PCC0CSCR 0x12004 /* socket 0 card status change */ -#define HD64465_PCCCSCR_PSCDI 0x80 /* sw card detect intr */ -#define HD64465_PCCCSCR_PSWSEL 0x40 /* power select */ -#define HD64465_PCCCSCR_PIREQ 0x20 /* IREQ intr req */ -#define HD64465_PCCCSCR_PSC 0x10 /* STSCHG (status change) pin */ -#define HD64465_PCCCSCR_PCDC 0x08 /* CD (card detect) change */ -#define HD64465_PCCCSCR_PRC 0x04 /* ready change */ -#define HD64465_PCCCSCR_PBW 0x02 /* battery warning change */ -#define HD64465_PCCCSCR_PBD 0x01 /* battery dead change */ -#define HD64465_REG_PCC0CSCIER 0x12006 /* socket 0 card status change interrupt enable */ -#define HD64465_PCCCSCIER_PCRE 0x80 /* change reset enable */ -#define HD64465_PCCCSCIER_PIREQE_MASK 0x60 /* IREQ enable */ -#define HD64465_PCCCSCIER_PIREQE_DISABLED 0x00 /* IREQ disabled */ -#define HD64465_PCCCSCIER_PIREQE_LEVEL 0x20 /* IREQ level-triggered */ -#define HD64465_PCCCSCIER_PIREQE_FALLING 0x40 /* IREQ falling-edge-trig */ -#define HD64465_PCCCSCIER_PIREQE_RISING 0x60 /* IREQ rising-edge-trig */ -#define HD64465_PCCCSCIER_PSCE 0x10 /* status change enable */ -#define HD64465_PCCCSCIER_PCDE 0x08 /* card detect change enable */ -#define HD64465_PCCCSCIER_PRE 0x04 /* ready change enable */ -#define HD64465_PCCCSCIER_PBWE 0x02 /* battery warn change enable */ -#define HD64465_PCCCSCIER_PBDE 0x01 /* battery dead change enable*/ -#define HD64465_REG_PCC0SCR 0x12008 /* socket 0 software control */ -#define HD64465_PCCSCR_SHDN 0x10 /* TPS2206 SHutDowN pin */ -#define HD64465_PCCSCR_SWP 0x01 /* write protect */ -#define HD64465_REG_PCCPSR 0x1200A /* serial power switch control */ -#define HD64465_REG_PCC1ISR 0x12010 /* socket 1 interface status */ -#define HD64465_REG_PCC1GCR 0x12012 /* socket 1 general control */ -#define HD64465_REG_PCC1CSCR 0x12014 /* socket 1 card status change */ -#define HD64465_REG_PCC1CSCIER 0x12016 /* socket 1 card status change interrupt enable */ -#define HD64465_REG_PCC1SCR 0x12018 /* socket 1 software control */ - - -/* PS/2 Keyboard and mouse controller -- *not* register compatible */ -#define HD64465_REG_KBCSR 0x1dc00 /* Keyboard Control/Status reg */ -#define HD64465_KBCSR_KBCIE 0x8000 /* KBCK Input Enable */ -#define HD64465_KBCSR_KBCOE 0x4000 /* KBCK Output Enable */ -#define HD64465_KBCSR_KBDOE 0x2000 /* KB DATA Output Enable */ -#define HD64465_KBCSR_KBCD 0x1000 /* KBCK Driven */ -#define HD64465_KBCSR_KBDD 0x0800 /* KB DATA Driven */ -#define HD64465_KBCSR_KBCS 0x0400 /* KBCK pin Status */ -#define HD64465_KBCSR_KBDS 0x0200 /* KB DATA pin Status */ -#define HD64465_KBCSR_KBDP 0x0100 /* KB DATA Parity bit */ -#define HD64465_KBCSR_KBD_MASK 0x00ff /* KD DATA shift reg */ -#define HD64465_REG_KBISR 0x1dc04 /* Keyboard Interrupt Status reg */ -#define HD64465_KBISR_KBRDF 0x0001 /* KB Received Data Full */ -#define HD64465_REG_MSCSR 0x1dc10 /* Mouse Control/Status reg */ -#define HD64465_REG_MSISR 0x1dc14 /* Mouse Interrupt Status reg */ - - -/* - * Logical address at which the HD64465 is mapped. Note that this - * should always be in the P2 segment (uncached and untranslated). - */ -#ifndef CONFIG_HD64465_IOBASE -#define CONFIG_HD64465_IOBASE 0xb0000000 -#endif -/* - * The HD64465 multiplexes all its modules' interrupts onto - * this single interrupt. - */ -#ifndef CONFIG_HD64465_IRQ -#define CONFIG_HD64465_IRQ 5 -#endif - - -#define _HD64465_IO_MASK 0xf8000000 -#define is_hd64465_addr(addr) \ - ((addr & _HD64465_IO_MASK) == (CONFIG_HD64465_IOBASE & _HD64465_IO_MASK)) - -/* - * A range of 16 virtual interrupts generated by - * demuxing the HD64465 muxed interrupt. - */ -#define HD64465_IRQ_BASE OFFCHIP_IRQ_BASE -#define HD64465_IRQ_NUM 16 -#define HD64465_IRQ_ADC (HD64465_IRQ_BASE+0) -#define HD64465_IRQ_USB (HD64465_IRQ_BASE+1) -#define HD64465_IRQ_SCDI (HD64465_IRQ_BASE+2) -#define HD64465_IRQ_PARALLEL (HD64465_IRQ_BASE+3) -/* bit 4 is reserved */ -#define HD64465_IRQ_UART (HD64465_IRQ_BASE+5) -#define HD64465_IRQ_IRDA (HD64465_IRQ_BASE+6) -#define HD64465_IRQ_PS2MOUSE (HD64465_IRQ_BASE+7) -#define HD64465_IRQ_KBC (HD64465_IRQ_BASE+8) -#define HD64465_IRQ_TIMER1 (HD64465_IRQ_BASE+9) -#define HD64465_IRQ_TIMER0 (HD64465_IRQ_BASE+10) -#define HD64465_IRQ_GPIO (HD64465_IRQ_BASE+11) -#define HD64465_IRQ_AFE (HD64465_IRQ_BASE+12) -#define HD64465_IRQ_PCMCIA1 (HD64465_IRQ_BASE+13) -#define HD64465_IRQ_PCMCIA0 (HD64465_IRQ_BASE+14) -#define HD64465_IRQ_PS2KBD (HD64465_IRQ_BASE+15) - -/* Constants for PCMCIA mappings */ -#define HD64465_PCC_WINDOW 0x01000000 - -#define HD64465_PCC0_BASE 0xb8000000 /* area 6 */ -#define HD64465_PCC0_ATTR (HD64465_PCC0_BASE) -#define HD64465_PCC0_COMM (HD64465_PCC0_BASE+HD64465_PCC_WINDOW) -#define HD64465_PCC0_IO (HD64465_PCC0_BASE+2*HD64465_PCC_WINDOW) - -#define HD64465_PCC1_BASE 0xb4000000 /* area 5 */ -#define HD64465_PCC1_ATTR (HD64465_PCC1_BASE) -#define HD64465_PCC1_COMM (HD64465_PCC1_BASE+HD64465_PCC_WINDOW) -#define HD64465_PCC1_IO (HD64465_PCC1_BASE+2*HD64465_PCC_WINDOW) - -/* - * Base of USB controller interface (as memory) - */ -#define HD64465_USB_BASE (CONFIG_HD64465_IOBASE+0xb000) -#define HD64465_USB_LEN 0x1000 -/* - * Base of embedded SRAM, used for USB controller. - */ -#define HD64465_SRAM_BASE (CONFIG_HD64465_IOBASE+0x9000) -#define HD64465_SRAM_LEN 0x1000 - - - -#endif /* _ASM_SH_HD64465_ */ diff --git a/arch/sh/include/asm/hd64465/io.h b/arch/sh/include/asm/hd64465/io.h deleted file mode 100644 index 139f1472e5b..00000000000 --- a/arch/sh/include/asm/hd64465/io.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * include/asm-sh/hd64465/io.h - * - * By Greg Banks <gbanks@pocketpenguins.com> - * (c) 2000 PocketPenguins Inc. - * - * Derived from io_hd64461.h, which bore the message: - * Copyright 2000 Stuart Menefy (stuart.menefy@st.com) - * - * May be copied or modified under the terms of the GNU General Public - * License. See linux/COPYING for more information. - * - * IO functions for an HD64465 "Windows CE Intelligent Peripheral Controller". - */ - -#ifndef _ASM_SH_IO_HD64465_H -#define _ASM_SH_IO_HD64465_H - -extern unsigned char hd64465_inb(unsigned long port); -extern unsigned short hd64465_inw(unsigned long port); -extern unsigned int hd64465_inl(unsigned long port); - -extern void hd64465_outb(unsigned char value, unsigned long port); -extern void hd64465_outw(unsigned short value, unsigned long port); -extern void hd64465_outl(unsigned int value, unsigned long port); - -extern unsigned char hd64465_inb_p(unsigned long port); -extern void hd64465_outb_p(unsigned char value, unsigned long port); - -extern unsigned long hd64465_isa_port2addr(unsigned long offset); -extern int hd64465_irq_demux(int irq); -/* Provision for generic secondary demux step -- used by PCMCIA code */ -extern void hd64465_register_irq_demux(int irq, - int (*demux)(int irq, void *dev), void *dev); -extern void hd64465_unregister_irq_demux(int irq); -/* Set this variable to 1 to see port traffic */ -extern int hd64465_io_debug; -/* Map a range of ports to a range of kernel virtual memory. - */ -extern void hd64465_port_map(unsigned short baseport, unsigned int nports, - unsigned long addr, unsigned char shift); -extern void hd64465_port_unmap(unsigned short baseport, unsigned int nports); - -#endif /* _ASM_SH_IO_HD64465_H */ diff --git a/arch/sh/include/asm/serial.h b/arch/sh/include/asm/serial.h index e13cc948ee6..11f854dd136 100644 --- a/arch/sh/include/asm/serial.h +++ b/arch/sh/include/asm/serial.h @@ -7,8 +7,6 @@ #ifndef _ASM_SERIAL_H #define _ASM_SERIAL_H -#include <linux/kernel.h> - /* * This assumes you have a 1.8432 MHz clock for your UART. * @@ -18,19 +16,4 @@ */ #define BASE_BAUD ( 1843200 / 16 ) -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) - -#ifdef CONFIG_HD64465 -#include <asm/hd64465/hd64465.h> - -#define SERIAL_PORT_DFNS \ - /* UART CLK PORT IRQ FLAGS */ \ - { 0, BASE_BAUD, 0x3F8, HD64465_IRQ_UART, STD_COM_FLAGS } /* ttyS0 */ - -#else - -#define SERIAL_PORT_DFNS - -#endif - #endif /* _ASM_SERIAL_H */ diff --git a/arch/sh/tools/mach-types b/arch/sh/tools/mach-types index d4fb11f7e2e..d0c2928d106 100644 --- a/arch/sh/tools/mach-types +++ b/arch/sh/tools/mach-types @@ -13,7 +13,6 @@ RTS7751R2D SH_RTS7751R2D # List of companion chips / MFDs. # HD64461 HD64461 -HD64465 HD64465 # # List of boards. |