diff options
Diffstat (limited to 'arch/sh')
| -rw-r--r-- | arch/sh/include/asm/cacheflush.h | 3 | ||||
| -rw-r--r-- | arch/sh/include/cpu-common/cpu/cacheflush.h | 2 | ||||
| -rw-r--r-- | arch/sh/include/cpu-sh2a/cpu/cacheflush.h | 1 | ||||
| -rw-r--r-- | arch/sh/include/cpu-sh3/cpu/cacheflush.h | 2 | ||||
| -rw-r--r-- | arch/sh/include/cpu-sh4/cpu/cacheflush.h | 3 | ||||
| -rw-r--r-- | arch/sh/include/cpu-sh5/cpu/cacheflush.h | 1 | ||||
| -rw-r--r-- | arch/sh/mm/cache-sh4.c | 2 | ||||
| -rw-r--r-- | arch/sh/mm/cache-sh5.c | 2 | ||||
| -rw-r--r-- | arch/sh/mm/cache.c | 11 | ||||
| -rw-r--r-- | arch/sh/mm/init.c | 2 |
10 files changed, 16 insertions, 13 deletions
diff --git a/arch/sh/include/asm/cacheflush.h b/arch/sh/include/asm/cacheflush.h index 9ec13fb909d..e37654f7f54 100644 --- a/arch/sh/include/asm/cacheflush.h +++ b/arch/sh/include/asm/cacheflush.h @@ -12,7 +12,6 @@ * * See arch/sh/kernel/cpu/init.c:cache_init(). */ -#define p3_cache_init() do { } while (0) #define flush_cache_all() do { } while (0) #define flush_cache_mm(mm) do { } while (0) #define flush_cache_dup_mm(mm) do { } while (0) @@ -78,5 +77,7 @@ void kunmap_coherent(void); #define PG_dcache_dirty PG_arch_1 +void cpu_cache_init(void); + #endif /* __KERNEL__ */ #endif /* __ASM_SH_CACHEFLUSH_H */ diff --git a/arch/sh/include/cpu-common/cpu/cacheflush.h b/arch/sh/include/cpu-common/cpu/cacheflush.h index c3db00b7360..0c38278509c 100644 --- a/arch/sh/include/cpu-common/cpu/cacheflush.h +++ b/arch/sh/include/cpu-common/cpu/cacheflush.h @@ -39,6 +39,4 @@ #define flush_icache_user_range(vma,pg,adr,len) do { } while (0) #define flush_cache_sigtramp(vaddr) do { } while (0) -#define p3_cache_init() do { } while (0) - #endif /* __ASM_CPU_SH2_CACHEFLUSH_H */ diff --git a/arch/sh/include/cpu-sh2a/cpu/cacheflush.h b/arch/sh/include/cpu-sh2a/cpu/cacheflush.h index 3d3b9205d2a..b9eaa19325e 100644 --- a/arch/sh/include/cpu-sh2a/cpu/cacheflush.h +++ b/arch/sh/include/cpu-sh2a/cpu/cacheflush.h @@ -30,5 +30,4 @@ void flush_icache_range(unsigned long start, unsigned long end); #define flush_icache_user_range(vma,pg,adr,len) do { } while (0) #define flush_cache_sigtramp(vaddr) do { } while (0) -#define p3_cache_init() do { } while (0) #endif /* __ASM_CPU_SH2A_CACHEFLUSH_H */ diff --git a/arch/sh/include/cpu-sh3/cpu/cacheflush.h b/arch/sh/include/cpu-sh3/cpu/cacheflush.h index 3b5f3df4e1c..cf656a09377 100644 --- a/arch/sh/include/cpu-sh3/cpu/cacheflush.h +++ b/arch/sh/include/cpu-sh3/cpu/cacheflush.h @@ -32,8 +32,6 @@ void flush_icache_page(struct vm_area_struct *vma, struct page *page); #define flush_cache_sigtramp(vaddr) do { } while (0) #define flush_icache_user_range(vma,pg,adr,len) do { } while (0) -#define p3_cache_init() do { } while (0) - #else #include <cpu-common/cpu/cacheflush.h> #endif diff --git a/arch/sh/include/cpu-sh4/cpu/cacheflush.h b/arch/sh/include/cpu-sh4/cpu/cacheflush.h index 76764f0fb88..a28c542f517 100644 --- a/arch/sh/include/cpu-sh4/cpu/cacheflush.h +++ b/arch/sh/include/cpu-sh4/cpu/cacheflush.h @@ -35,7 +35,4 @@ void flush_icache_user_range(struct vm_area_struct *vma, struct page *page, #define flush_icache_page(vma,pg) do { } while (0) -/* Initialization of P3 area for copy_user_page */ -void p3_cache_init(void); - #endif /* __ASM_CPU_SH4_CACHEFLUSH_H */ diff --git a/arch/sh/include/cpu-sh5/cpu/cacheflush.h b/arch/sh/include/cpu-sh5/cpu/cacheflush.h index 5a11f0b7e66..8350cc7ed1c 100644 --- a/arch/sh/include/cpu-sh5/cpu/cacheflush.h +++ b/arch/sh/include/cpu-sh5/cpu/cacheflush.h @@ -25,7 +25,6 @@ extern void flush_icache_user_range(struct vm_area_struct *vma, #define flush_dcache_mmap_unlock(mapping) do { } while (0) #define flush_icache_page(vma, page) do { } while (0) -void p3_cache_init(void); #endif /* __ASSEMBLY__ */ diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c index 92f87a460a8..df2eb87f152 100644 --- a/arch/sh/mm/cache-sh4.c +++ b/arch/sh/mm/cache-sh4.c @@ -94,7 +94,7 @@ static void __init emit_cache_params(void) /* * SH-4 has virtually indexed and physically tagged cache. */ -void __init p3_cache_init(void) +void __init sh4_cache_init(void) { compute_alias(&boot_cpu_data.icache); compute_alias(&boot_cpu_data.dcache); diff --git a/arch/sh/mm/cache-sh5.c b/arch/sh/mm/cache-sh5.c index 28f3c8fb1b9..576cad04b11 100644 --- a/arch/sh/mm/cache-sh5.c +++ b/arch/sh/mm/cache-sh5.c @@ -23,7 +23,7 @@ /* Wired TLB entry for the D-cache */ static unsigned long long dtlb_cache_slot; -void __init p3_cache_init(void) +void __init cpu_cache_init(void) { /* Reserve a slot for dcache colouring in the DTLB */ dtlb_cache_slot = sh64_get_wired_dtlb_entry(); diff --git a/arch/sh/mm/cache.c b/arch/sh/mm/cache.c index f51d0a4eb3b..659981ffae2 100644 --- a/arch/sh/mm/cache.c +++ b/arch/sh/mm/cache.c @@ -127,3 +127,14 @@ void __flush_anon_page(struct page *page, unsigned long vmaddr) __flush_wback_region((void *)addr, PAGE_SIZE); } } + +void __init cpu_cache_init(void) +{ + if ((boot_cpu_data.family == CPU_FAMILY_SH4) || + (boot_cpu_data.family == CPU_FAMILY_SH4A) || + (boot_cpu_data.family == CPU_FAMILY_SH4AL_DSP)) { + extern void __weak sh4_cache_init(void); + + sh4_cache_init(); + } +} diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c index fe532aeaa16..cf0e9c5146b 100644 --- a/arch/sh/mm/init.c +++ b/arch/sh/mm/init.c @@ -230,7 +230,7 @@ void __init mem_init(void) datasize >> 10, initsize >> 10); - p3_cache_init(); + cpu_cache_init(); /* Initialize the vDSO */ vsyscall_init(); |