aboutsummaryrefslogtreecommitdiff
path: root/drivers/net/igb/e1000_82575.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/igb/e1000_82575.c')
-rw-r--r--drivers/net/igb/e1000_82575.c240
1 files changed, 151 insertions, 89 deletions
diff --git a/drivers/net/igb/e1000_82575.c b/drivers/net/igb/e1000_82575.c
index cda3ec87909..2c8b91060d9 100644
--- a/drivers/net/igb/e1000_82575.c
+++ b/drivers/net/igb/e1000_82575.c
@@ -1,7 +1,7 @@
/*******************************************************************************
Intel(R) Gigabit Ethernet Linux driver
- Copyright(c) 2007 Intel Corporation.
+ Copyright(c) 2007 - 2008 Intel Corporation.
This program is free software; you can redistribute it and/or modify it
under the terms and conditions of the GNU General Public License,
@@ -171,6 +171,10 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
* for setting word_size.
*/
size += NVM_WORD_SIZE_BASE_SHIFT;
+
+ /* EEPROM access above 16k is unsupported */
+ if (size > 14)
+ size = 14;
nvm->word_size = 1 << size;
/* setup PHY parameters */
@@ -222,7 +226,7 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
}
/**
- * e1000_acquire_phy_82575 - Acquire rights to access PHY
+ * igb_acquire_phy_82575 - Acquire rights to access PHY
* @hw: pointer to the HW structure
*
* Acquire access rights to the correct PHY. This is a
@@ -238,7 +242,7 @@ static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
}
/**
- * e1000_release_phy_82575 - Release rights to access PHY
+ * igb_release_phy_82575 - Release rights to access PHY
* @hw: pointer to the HW structure
*
* A wrapper to release access rights to the correct PHY. This is a
@@ -253,7 +257,7 @@ static void igb_release_phy_82575(struct e1000_hw *hw)
}
/**
- * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
+ * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
* @hw: pointer to the HW structure
* @offset: register offset to be read
* @data: pointer to the read data
@@ -268,7 +272,7 @@ static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
u32 i, i2ccmd = 0;
if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
- hw_dbg(hw, "PHY Address %u is out of range\n", offset);
+ hw_dbg("PHY Address %u is out of range\n", offset);
return -E1000_ERR_PARAM;
}
@@ -291,11 +295,11 @@ static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
break;
}
if (!(i2ccmd & E1000_I2CCMD_READY)) {
- hw_dbg(hw, "I2CCMD Read did not complete\n");
+ hw_dbg("I2CCMD Read did not complete\n");
return -E1000_ERR_PHY;
}
if (i2ccmd & E1000_I2CCMD_ERROR) {
- hw_dbg(hw, "I2CCMD Error bit set\n");
+ hw_dbg("I2CCMD Error bit set\n");
return -E1000_ERR_PHY;
}
@@ -306,7 +310,7 @@ static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
}
/**
- * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
+ * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
* @hw: pointer to the HW structure
* @offset: register offset to write to
* @data: data to write at register offset
@@ -322,7 +326,7 @@ static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
u16 phy_data_swapped;
if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
- hw_dbg(hw, "PHY Address %d is out of range\n", offset);
+ hw_dbg("PHY Address %d is out of range\n", offset);
return -E1000_ERR_PARAM;
}
@@ -349,11 +353,11 @@ static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
break;
}
if (!(i2ccmd & E1000_I2CCMD_READY)) {
- hw_dbg(hw, "I2CCMD Write did not complete\n");
+ hw_dbg("I2CCMD Write did not complete\n");
return -E1000_ERR_PHY;
}
if (i2ccmd & E1000_I2CCMD_ERROR) {
- hw_dbg(hw, "I2CCMD Error bit set\n");
+ hw_dbg("I2CCMD Error bit set\n");
return -E1000_ERR_PHY;
}
@@ -361,10 +365,10 @@ static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
}
/**
- * e1000_get_phy_id_82575 - Retreive PHY addr and id
+ * igb_get_phy_id_82575 - Retrieve PHY addr and id
* @hw: pointer to the HW structure
*
- * Retreives the PHY address and ID for both PHY's which do and do not use
+ * Retrieves the PHY address and ID for both PHY's which do and do not use
* sgmi interface.
**/
static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
@@ -393,9 +397,8 @@ static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
for (phy->addr = 1; phy->addr < 8; phy->addr++) {
ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
if (ret_val == 0) {
- hw_dbg(hw, "Vendor ID 0x%08X read at address %u\n",
- phy_id,
- phy->addr);
+ hw_dbg("Vendor ID 0x%08X read at address %u\n",
+ phy_id, phy->addr);
/*
* At the time of this writing, The M88 part is
* the only supported SGMII PHY product.
@@ -403,8 +406,7 @@ static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
if (phy_id == M88_VENDOR)
break;
} else {
- hw_dbg(hw, "PHY address %u was unreadable\n",
- phy->addr);
+ hw_dbg("PHY address %u was unreadable\n", phy->addr);
}
}
@@ -422,7 +424,7 @@ out:
}
/**
- * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
+ * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
* @hw: pointer to the HW structure
*
* Resets the PHY using the serial gigabit media independent interface.
@@ -436,7 +438,7 @@ static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
* available to us at this time.
*/
- hw_dbg(hw, "Soft resetting SGMII attached PHY...\n");
+ hw_dbg("Soft resetting SGMII attached PHY...\n");
/*
* SFP documentation requires the following to configure the SPF module
@@ -453,7 +455,7 @@ out:
}
/**
- * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
+ * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
* @hw: pointer to the HW structure
* @active: true to enable LPLU, false to disable
*
@@ -471,34 +473,29 @@ static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
s32 ret_val;
u16 data;
- ret_val = hw->phy.ops.read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
- &data);
+ ret_val = phy->ops.read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
if (ret_val)
goto out;
if (active) {
data |= IGP02E1000_PM_D0_LPLU;
- ret_val = hw->phy.ops.write_phy_reg(hw,
- IGP02E1000_PHY_POWER_MGMT,
- data);
+ ret_val = phy->ops.write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
+ data);
if (ret_val)
goto out;
/* When LPLU is enabled, we should disable SmartSpeed */
- ret_val = hw->phy.ops.read_phy_reg(hw,
- IGP01E1000_PHY_PORT_CONFIG,
- &data);
+ ret_val = phy->ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+ &data);
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
- ret_val = hw->phy.ops.write_phy_reg(hw,
- IGP01E1000_PHY_PORT_CONFIG,
- data);
+ ret_val = phy->ops.write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+ data);
if (ret_val)
goto out;
} else {
data &= ~IGP02E1000_PM_D0_LPLU;
- ret_val = hw->phy.ops.write_phy_reg(hw,
- IGP02E1000_PHY_POWER_MGMT,
- data);
+ ret_val = phy->ops.write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
+ data);
/*
* LPLU and SmartSpeed are mutually exclusive. LPLU is used
* during Dx states where the power conservation is most
@@ -506,29 +503,25 @@ static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
* SmartSpeed, so performance is maintained.
*/
if (phy->smart_speed == e1000_smart_speed_on) {
- ret_val = hw->phy.ops.read_phy_reg(hw,
- IGP01E1000_PHY_PORT_CONFIG,
- &data);
+ ret_val = phy->ops.read_phy_reg(hw,
+ IGP01E1000_PHY_PORT_CONFIG, &data);
if (ret_val)
goto out;
data |= IGP01E1000_PSCFR_SMART_SPEED;
- ret_val = hw->phy.ops.write_phy_reg(hw,
- IGP01E1000_PHY_PORT_CONFIG,
- data);
+ ret_val = phy->ops.write_phy_reg(hw,
+ IGP01E1000_PHY_PORT_CONFIG, data);
if (ret_val)
goto out;
} else if (phy->smart_speed == e1000_smart_speed_off) {
- ret_val = hw->phy.ops.read_phy_reg(hw,
- IGP01E1000_PHY_PORT_CONFIG,
- &data);
+ ret_val = phy->ops.read_phy_reg(hw,
+ IGP01E1000_PHY_PORT_CONFIG, &data);
if (ret_val)
goto out;
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
- ret_val = hw->phy.ops.write_phy_reg(hw,
- IGP01E1000_PHY_PORT_CONFIG,
- data);
+ ret_val = phy->ops.write_phy_reg(hw,
+ IGP01E1000_PHY_PORT_CONFIG, data);
if (ret_val)
goto out;
}
@@ -539,10 +532,10 @@ out:
}
/**
- * e1000_acquire_nvm_82575 - Request for access to EEPROM
+ * igb_acquire_nvm_82575 - Request for access to EEPROM
* @hw: pointer to the HW structure
*
- * Acquire the necessary semaphores for exclussive access to the EEPROM.
+ * Acquire the necessary semaphores for exclusive access to the EEPROM.
* Set the EEPROM access request bit and wait for EEPROM access grant bit.
* Return successful if access grant bit set, else clear the request for
* EEPROM access and return -E1000_ERR_NVM (-1).
@@ -565,7 +558,7 @@ out:
}
/**
- * e1000_release_nvm_82575 - Release exclusive access to EEPROM
+ * igb_release_nvm_82575 - Release exclusive access to EEPROM
* @hw: pointer to the HW structure
*
* Stop any current commands to the EEPROM and clear the EEPROM request bit,
@@ -578,7 +571,7 @@ static void igb_release_nvm_82575(struct e1000_hw *hw)
}
/**
- * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
+ * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
* @hw: pointer to the HW structure
* @mask: specifies which semaphore to acquire
*
@@ -613,7 +606,7 @@ static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
}
if (i == timeout) {
- hw_dbg(hw, "Can't access resource, SW_FW_SYNC timeout.\n");
+ hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
ret_val = -E1000_ERR_SWFW_SYNC;
goto out;
}
@@ -628,7 +621,7 @@ out:
}
/**
- * e1000_release_swfw_sync_82575 - Release SW/FW semaphore
+ * igb_release_swfw_sync_82575 - Release SW/FW semaphore
* @hw: pointer to the HW structure
* @mask: specifies which semaphore to acquire
*
@@ -650,7 +643,7 @@ static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
}
/**
- * e1000_get_cfg_done_82575 - Read config done bit
+ * igb_get_cfg_done_82575 - Read config done bit
* @hw: pointer to the HW structure
*
* Read the management control register for the config done bit for
@@ -675,7 +668,7 @@ static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
timeout--;
}
if (!timeout)
- hw_dbg(hw, "MNG configuration cycle has not completed.\n");
+ hw_dbg("MNG configuration cycle has not completed.\n");
/* If EEPROM is not marked present, init the PHY manually */
if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
@@ -686,7 +679,7 @@ static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
}
/**
- * e1000_check_for_link_82575 - Check for link
+ * igb_check_for_link_82575 - Check for link
* @hw: pointer to the HW structure
*
* If sgmii is enabled, then use the pcs register to determine link, otherwise
@@ -709,12 +702,12 @@ static s32 igb_check_for_link_82575(struct e1000_hw *hw)
}
/**
- * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
+ * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
* @hw: pointer to the HW structure
* @speed: stores the current speed
* @duplex: stores the current duplex
*
- * Using the physical coding sub-layer (PCS), retreive the current speed and
+ * Using the physical coding sub-layer (PCS), retrieve the current speed and
* duplex, then store the values in the pointers provided.
**/
static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
@@ -764,7 +757,7 @@ static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
}
/**
- * e1000_rar_set_82575 - Set receive address register
+ * igb_rar_set_82575 - Set receive address register
* @hw: pointer to the HW structure
* @addr: pointer to the receive address
* @index: receive address array register
@@ -781,7 +774,7 @@ static void igb_rar_set_82575(struct e1000_hw *hw, u8 *addr, u32 index)
}
/**
- * e1000_reset_hw_82575 - Reset hardware
+ * igb_reset_hw_82575 - Reset hardware
* @hw: pointer to the HW structure
*
* This resets the hardware into a known state. This is a
@@ -798,9 +791,9 @@ static s32 igb_reset_hw_82575(struct e1000_hw *hw)
*/
ret_val = igb_disable_pcie_master(hw);
if (ret_val)
- hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
+ hw_dbg("PCI-E Master disable polling has failed.\n");
- hw_dbg(hw, "Masking off all interrupts\n");
+ hw_dbg("Masking off all interrupts\n");
wr32(E1000_IMC, 0xffffffff);
wr32(E1000_RCTL, 0);
@@ -811,7 +804,7 @@ static s32 igb_reset_hw_82575(struct e1000_hw *hw)
ctrl = rd32(E1000_CTRL);
- hw_dbg(hw, "Issuing a global reset to MAC\n");
+ hw_dbg("Issuing a global reset to MAC\n");
wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
ret_val = igb_get_auto_rd_done(hw);
@@ -821,7 +814,7 @@ static s32 igb_reset_hw_82575(struct e1000_hw *hw)
* return with an error. This can happen in situations
* where there is no eeprom and prevents getting link.
*/
- hw_dbg(hw, "Auto Read Done did not complete\n");
+ hw_dbg("Auto Read Done did not complete\n");
}
/* If EEPROM is not present, run manual init scripts */
@@ -838,7 +831,7 @@ static s32 igb_reset_hw_82575(struct e1000_hw *hw)
}
/**
- * e1000_init_hw_82575 - Initialize hardware
+ * igb_init_hw_82575 - Initialize hardware
* @hw: pointer to the HW structure
*
* This inits the hardware readying it for operation.
@@ -852,18 +845,18 @@ static s32 igb_init_hw_82575(struct e1000_hw *hw)
/* Initialize identification LED */
ret_val = igb_id_led_init(hw);
if (ret_val) {
- hw_dbg(hw, "Error initializing identification LED\n");
+ hw_dbg("Error initializing identification LED\n");
/* This is not fatal and we should not stop init due to this */
}
/* Disabling VLAN filtering */
- hw_dbg(hw, "Initializing the IEEE VLAN\n");
+ hw_dbg("Initializing the IEEE VLAN\n");
igb_clear_vfta(hw);
/* Setup the receive address */
igb_init_rx_addrs(hw, rar_count);
/* Zero out the Multicast HASH table */
- hw_dbg(hw, "Zeroing the MTA\n");
+ hw_dbg("Zeroing the MTA\n");
for (i = 0; i < mac->mta_reg_count; i++)
array_wr32(E1000_MTA, i, 0);
@@ -882,7 +875,7 @@ static s32 igb_init_hw_82575(struct e1000_hw *hw)
}
/**
- * e1000_setup_copper_link_82575 - Configure copper link settings
+ * igb_setup_copper_link_82575 - Configure copper link settings
* @hw: pointer to the HW structure
*
* Configures the link for auto-neg or forced speed and duplex. Then we check
@@ -933,10 +926,10 @@ static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
* PHY will be set to 10H, 10F, 100H or 100F
* depending on user settings.
*/
- hw_dbg(hw, "Forcing Speed and Duplex\n");
+ hw_dbg("Forcing Speed and Duplex\n");
ret_val = igb_phy_force_speed_duplex(hw);
if (ret_val) {
- hw_dbg(hw, "Error Forcing Speed and Duplex\n");
+ hw_dbg("Error Forcing Speed and Duplex\n");
goto out;
}
}
@@ -949,20 +942,17 @@ static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
* Check link status. Wait up to 100 microseconds for link to become
* valid.
*/
- ret_val = igb_phy_has_link(hw,
- COPPER_LINK_UP_LIMIT,
- 10,
- &link);
+ ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
if (ret_val)
goto out;
if (link) {
- hw_dbg(hw, "Valid link established!!!\n");
+ hw_dbg("Valid link established!!!\n");
/* Config the MAC and PHY after link is up */
igb_config_collision_dist(hw);
ret_val = igb_config_fc_after_link_up(hw);
} else {
- hw_dbg(hw, "Unable to establish link!!!\n");
+ hw_dbg("Unable to establish link!!!\n");
}
out:
@@ -970,7 +960,7 @@ out:
}
/**
- * e1000_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes
+ * igb_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes
* @hw: pointer to the HW structure
*
* Configures speed and duplex for fiber and serdes links.
@@ -1018,7 +1008,7 @@ static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *hw)
E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
- hw_dbg(hw, "Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
+ hw_dbg("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
} else {
/* Set PCS register for forced speed */
reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
@@ -1026,7 +1016,7 @@ static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *hw)
E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
E1000_PCS_LCTL_FSD | /* Force Speed */
E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
- hw_dbg(hw, "Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg);
+ hw_dbg("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg);
}
wr32(E1000_PCS_LCTL, reg);
@@ -1034,7 +1024,7 @@ static s32 igb_setup_fiber_serdes_link_82575(struct e1000_hw *hw)
}
/**
- * e1000_configure_pcs_link_82575 - Configure PCS link
+ * igb_configure_pcs_link_82575 - Configure PCS link
* @hw: pointer to the HW structure
*
* Configure the physical coding sub-layer (PCS) link. The PCS link is
@@ -1067,7 +1057,7 @@ static s32 igb_configure_pcs_link_82575(struct e1000_hw *hw)
*/
reg |= E1000_PCS_LCTL_AN_RESTART | E1000_PCS_LCTL_AN_ENABLE;
} else {
- /* Set PCS regiseter for forced speed */
+ /* Set PCS register for forced speed */
/* Turn off bits for full duplex, speed, and autoneg */
reg &= ~(E1000_PCS_LCTL_FSV_1000 |
@@ -1088,8 +1078,7 @@ static s32 igb_configure_pcs_link_82575(struct e1000_hw *hw)
E1000_PCS_LCTL_FORCE_LINK |
E1000_PCS_LCTL_FLV_LINK_UP;
- hw_dbg(hw,
- "Wrote 0x%08X to PCS_LCTL to configure forced link\n",
+ hw_dbg("Wrote 0x%08X to PCS_LCTL to configure forced link\n",
reg);
}
wr32(E1000_PCS_LCTL, reg);
@@ -1099,7 +1088,7 @@ out:
}
/**
- * e1000_sgmii_active_82575 - Return sgmii state
+ * igb_sgmii_active_82575 - Return sgmii state
* @hw: pointer to the HW structure
*
* 82575 silicon has a serialized gigabit media independent interface (sgmii)
@@ -1125,7 +1114,7 @@ out:
}
/**
- * e1000_reset_init_script_82575 - Inits HW defaults after reset
+ * igb_reset_init_script_82575 - Inits HW defaults after reset
* @hw: pointer to the HW structure
*
* Inits recommended HW defaults after a reset when there is no EEPROM
@@ -1134,7 +1123,7 @@ out:
static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
{
if (hw->mac.type == e1000_82575) {
- hw_dbg(hw, "Running reset init script for 82575\n");
+ hw_dbg("Running reset init script for 82575\n");
/* SerDes configuration via SERDESCTRL */
igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
@@ -1161,7 +1150,7 @@ static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
}
/**
- * e1000_read_mac_addr_82575 - Read device MAC address
+ * igb_read_mac_addr_82575 - Read device MAC address
* @hw: pointer to the HW structure
**/
static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
@@ -1175,7 +1164,7 @@ static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
}
/**
- * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
+ * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
* @hw: pointer to the HW structure
*
* Clears the hardware counters by reading the counter registers.
@@ -1238,6 +1227,79 @@ static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
temp = rd32(E1000_SCVPC);
}
+/**
+ * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
+ * @hw: pointer to the HW structure
+ *
+ * After rx enable if managability is enabled then there is likely some
+ * bad data at the start of the fifo and possibly in the DMA fifo. This
+ * function clears the fifos and flushes any packets that came in as rx was
+ * being enabled.
+ **/
+void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
+{
+ u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
+ int i, ms_wait;
+
+ if (hw->mac.type != e1000_82575 ||
+ !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
+ return;
+
+ /* Disable all RX queues */
+ for (i = 0; i < 4; i++) {
+ rxdctl[i] = rd32(E1000_RXDCTL(i));
+ wr32(E1000_RXDCTL(i),
+ rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
+ }
+ /* Poll all queues to verify they have shut down */
+ for (ms_wait = 0; ms_wait < 10; ms_wait++) {
+ msleep(1);
+ rx_enabled = 0;
+ for (i = 0; i < 4; i++)
+ rx_enabled |= rd32(E1000_RXDCTL(i));
+ if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
+ break;
+ }
+
+ if (ms_wait == 10)
+ hw_dbg("Queue disable timed out after 10ms\n");
+
+ /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
+ * incoming packets are rejected. Set enable and wait 2ms so that
+ * any packet that was coming in as RCTL.EN was set is flushed
+ */
+ rfctl = rd32(E1000_RFCTL);
+ wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
+
+ rlpml = rd32(E1000_RLPML);
+ wr32(E1000_RLPML, 0);
+
+ rctl = rd32(E1000_RCTL);
+ temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
+ temp_rctl |= E1000_RCTL_LPE;
+
+ wr32(E1000_RCTL, temp_rctl);
+ wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
+ wrfl();
+ msleep(2);
+
+ /* Enable RX queues that were previously enabled and restore our
+ * previous state
+ */
+ for (i = 0; i < 4; i++)
+ wr32(E1000_RXDCTL(i), rxdctl[i]);
+ wr32(E1000_RCTL, rctl);
+ wrfl();
+
+ wr32(E1000_RLPML, rlpml);
+ wr32(E1000_RFCTL, rfctl);
+
+ /* Flush receive errors generated by workaround */
+ rd32(E1000_ROC);
+ rd32(E1000_RNBC);
+ rd32(E1000_MPC);
+}
+
static struct e1000_mac_operations e1000_mac_ops_82575 = {
.reset_hw = igb_reset_hw_82575,
.init_hw = igb_init_hw_82575,
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-22 08:18:30 +0000