diff options
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/Kconfig | 26 | ||||
| -rw-r--r-- | drivers/spi/Makefile | 3 | ||||
| -rw-r--r-- | drivers/spi/pxa2xx_spi.c | 93 | ||||
| -rw-r--r-- | drivers/spi/spi.c | 6 | ||||
| -rw-r--r-- | drivers/spi/spi_butterfly.c | 1 | ||||
| -rw-r--r-- | drivers/spi/spi_mpc83xx.c | 483 | ||||
| -rw-r--r-- | drivers/spi/spi_s3c24xx.c | 453 | ||||
| -rw-r--r-- | drivers/spi/spi_s3c24xx_gpio.c | 188 |
8 files changed, 1213 insertions, 40 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 9ce1d01469b..23334c8bc4c 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -75,6 +75,18 @@ config SPI_BUTTERFLY inexpensive battery powered microcontroller evaluation board. This same cable can be used to flash new firmware. +config SPI_MPC83xx + tristate "Freescale MPC83xx SPI controller" + depends on SPI_MASTER && PPC_83xx && EXPERIMENTAL + select SPI_BITBANG + help + This enables using the Freescale MPC83xx SPI controller in master + mode. + + Note, this driver uniquely supports the SPI controller on the MPC83xx + family of PowerPC processors. The MPC83xx uses a simple set of shift + registers for data (opposed to the CPM based descriptor model). + config SPI_PXA2XX tristate "PXA2xx SSP SPI master" depends on SPI_MASTER && ARCH_PXA && EXPERIMENTAL @@ -83,11 +95,25 @@ config SPI_PXA2XX The driver can be configured to use any SSP port and additional documentation can be found a Documentation/spi/pxa2xx. +config SPI_S3C24XX_GPIO + tristate "Samsung S3C24XX series SPI by GPIO" + depends on SPI_MASTER && ARCH_S3C2410 && SPI_BITBANG && EXPERIMENTAL + help + SPI driver for Samsung S3C24XX series ARM SoCs using + GPIO lines to provide the SPI bus. This can be used where + the inbuilt hardware cannot provide the transfer mode, or + where the board is using non hardware connected pins. # # Add new SPI master controllers in alphabetical order above this line # +config SPI_S3C24XX + tristate "Samsung S3C24XX series SPI" + depends on SPI_MASTER && ARCH_S3C2410 && EXPERIMENTAL + help + SPI driver for Samsung S3C24XX series ARM SoCs + # # There are lots of SPI device types, with sensors and memory # being probably the most widely used ones. diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 1bca5f95de2..8f4cb67997b 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -14,6 +14,9 @@ obj-$(CONFIG_SPI_MASTER) += spi.o obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o +obj-$(CONFIG_SPI_MPC83xx) += spi_mpc83xx.o +obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o +obj-$(CONFIG_SPI_S3C24XX) += spi_s3c24xx.o # ... add above this line ... # SPI protocol drivers (device/link on bus) diff --git a/drivers/spi/pxa2xx_spi.c b/drivers/spi/pxa2xx_spi.c index 596bf820b70..29aec77f98b 100644 --- a/drivers/spi/pxa2xx_spi.c +++ b/drivers/spi/pxa2xx_spi.c @@ -363,25 +363,30 @@ static void unmap_dma_buffers(struct driver_data *drv_data) } /* caller already set message->status; dma and pio irqs are blocked */ -static void giveback(struct spi_message *message, struct driver_data *drv_data) +static void giveback(struct driver_data *drv_data) { struct spi_transfer* last_transfer; + unsigned long flags; + struct spi_message *msg; - last_transfer = list_entry(message->transfers.prev, + spin_lock_irqsave(&drv_data->lock, flags); + msg = drv_data->cur_msg; + drv_data->cur_msg = NULL; + drv_data->cur_transfer = NULL; + drv_data->cur_chip = NULL; + queue_work(drv_data->workqueue, &drv_data->pump_messages); + spin_unlock_irqrestore(&drv_data->lock, flags); + + last_transfer = list_entry(msg->transfers.prev, struct spi_transfer, transfer_list); if (!last_transfer->cs_change) drv_data->cs_control(PXA2XX_CS_DEASSERT); - message->state = NULL; - if (message->complete) - message->complete(message->context); - - drv_data->cur_msg = NULL; - drv_data->cur_transfer = NULL; - drv_data->cur_chip = NULL; - queue_work(drv_data->workqueue, &drv_data->pump_messages); + msg->state = NULL; + if (msg->complete) + msg->complete(msg->context); } static int wait_ssp_rx_stall(void *ioaddr) @@ -415,10 +420,11 @@ static void dma_handler(int channel, void *data, struct pt_regs *regs) if (irq_status & DCSR_BUSERR) { /* Disable interrupts, clear status and reset DMA */ + write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); + write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); if (drv_data->ssp_type != PXA25x_SSP) write_SSTO(0, reg); write_SSSR(drv_data->clear_sr, reg); - write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; @@ -454,8 +460,8 @@ static void dma_handler(int channel, void *data, struct pt_regs *regs) "dma_handler: ssp rx stall failed\n"); /* Clear and disable interrupts on SSP and DMA channels*/ - write_SSSR(drv_data->clear_sr, reg); write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); + write_SSSR(drv_data->clear_sr, reg); DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; if (wait_dma_channel_stop(drv_data->rx_channel) == 0) @@ -497,10 +503,11 @@ static irqreturn_t dma_transfer(struct driver_data *drv_data) irq_status = read_SSSR(reg) & drv_data->mask_sr; if (irq_status & SSSR_ROR) { /* Clear and disable interrupts on SSP and DMA channels*/ + write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); + write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); if (drv_data->ssp_type != PXA25x_SSP) write_SSTO(0, reg); write_SSSR(drv_data->clear_sr, reg); - write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; unmap_dma_buffers(drv_data); @@ -526,10 +533,10 @@ static irqreturn_t dma_transfer(struct driver_data *drv_data) if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) { /* Clear and disable interrupts on SSP and DMA channels*/ + write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); if (drv_data->ssp_type != PXA25x_SSP) write_SSTO(0, reg); write_SSSR(drv_data->clear_sr, reg); - write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; @@ -572,26 +579,30 @@ static irqreturn_t dma_transfer(struct driver_data *drv_data) static irqreturn_t interrupt_transfer(struct driver_data *drv_data) { - u32 irq_status; struct spi_message *msg = drv_data->cur_msg; void *reg = drv_data->ioaddr; - irqreturn_t handled = IRQ_NONE; unsigned long limit = loops_per_jiffy << 1; + u32 irq_status; + u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ? + drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; - while ((irq_status = (read_SSSR(reg) & drv_data->mask_sr))) { + while ((irq_status = read_SSSR(reg) & irq_mask)) { if (irq_status & SSSR_ROR) { /* Clear and disable interrupts */ + write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); + write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); if (drv_data->ssp_type != PXA25x_SSP) write_SSTO(0, reg); write_SSSR(drv_data->clear_sr, reg); - write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); if (flush(drv_data) == 0) dev_err(&drv_data->pdev->dev, "interrupt_transfer: flush fail\n"); + /* Stop the SSP */ + dev_warn(&drv_data->pdev->dev, "interrupt_transfer: fifo overun\n"); @@ -613,6 +624,7 @@ static irqreturn_t interrupt_transfer(struct driver_data *drv_data) if (drv_data->tx == drv_data->tx_end) { /* Disable tx interrupt */ write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg); + irq_mask = drv_data->mask_sr & ~SSSR_TFS; /* PXA25x_SSP has no timeout, read trailing bytes */ if (drv_data->ssp_type == PXA25x_SSP) { @@ -630,10 +642,10 @@ static irqreturn_t interrupt_transfer(struct driver_data *drv_data) || (drv_data->rx == drv_data->rx_end)) { /* Clear timeout */ + write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); if (drv_data->ssp_type != PXA25x_SSP) write_SSTO(0, reg); write_SSSR(drv_data->clear_sr, reg); - write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); /* Update total byte transfered */ msg->actual_length += drv_data->len; @@ -648,24 +660,29 @@ static irqreturn_t interrupt_transfer(struct driver_data *drv_data) /* Schedule transfer tasklet */ tasklet_schedule(&drv_data->pump_transfers); - - return IRQ_HANDLED; } - - /* We did something */ - handled = IRQ_HANDLED; } - return handled; + /* We did something */ + return IRQ_HANDLED; } static irqreturn_t ssp_int(int irq, void *dev_id, struct pt_regs *regs) { struct driver_data *drv_data = (struct driver_data *)dev_id; + void *reg = drv_data->ioaddr; if (!drv_data->cur_msg) { + + write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); + write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg); + if (drv_data->ssp_type != PXA25x_SSP) + write_SSTO(0, reg); + write_SSSR(drv_data->clear_sr, reg); + dev_err(&drv_data->pdev->dev, "bad message state " - "in interrupt handler\n"); + "in interrupt handler"); + /* Never fail */ return IRQ_HANDLED; } @@ -694,14 +711,14 @@ static void pump_transfers(unsigned long data) /* Handle for abort */ if (message->state == ERROR_STATE) { message->status = -EIO; - giveback(message, drv_data); + giveback(drv_data); return; } /* Handle end of message */ if (message->state == DONE_STATE) { message->status = 0; - giveback(message, drv_data); + giveback(drv_data); return; } @@ -718,7 +735,7 @@ static void pump_transfers(unsigned long data) if (flush(drv_data) == 0) { dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); message->status = -EIO; - giveback(message, drv_data); + giveback(drv_data); return; } drv_data->n_bytes = chip->n_bytes; @@ -782,7 +799,7 @@ static void pump_transfers(unsigned long data) cr0 = clk_div | SSCR0_Motorola - | SSCR0_DataSize(bits & 0x0f) + | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) | SSCR0_SSE | (bits > 16 ? SSCR0_EDSS : 0); @@ -890,8 +907,6 @@ static void pump_messages(void *data) drv_data->cur_msg = list_entry(drv_data->queue.next, struct spi_message, queue); list_del_init(&drv_data->cur_msg->queue); - drv_data->busy = 1; - spin_unlock_irqrestore(&drv_data->lock, flags); /* Initial message state*/ drv_data->cur_msg->state = START_STATE; @@ -905,6 +920,9 @@ static void pump_messages(void *data) /* Mark as busy and launch transfers */ tasklet_schedule(&drv_data->pump_transfers); + + drv_data->busy = 1; + spin_unlock_irqrestore(&drv_data->lock, flags); } static int transfer(struct spi_device *spi, struct spi_message *msg) @@ -958,7 +976,7 @@ static int setup(struct spi_device *spi) chip->cs_control = null_cs_control; chip->enable_dma = 0; - chip->timeout = 5; + chip->timeout = SSP_TIMEOUT(1000); chip->threshold = SSCR1_RxTresh(1) | SSCR1_TxTresh(1); chip->dma_burst_size = drv_data->master_info->enable_dma ? DCMD_BURST8 : 0; @@ -971,7 +989,7 @@ static int setup(struct spi_device *spi) if (chip_info->cs_control) chip->cs_control = chip_info->cs_control; - chip->timeout = (chip_info->timeout_microsecs * 10000) / 2712; + chip->timeout = SSP_TIMEOUT(chip_info->timeout_microsecs); chip->threshold = SSCR1_RxTresh(chip_info->rx_threshold) | SSCR1_TxTresh(chip_info->tx_threshold); @@ -1013,7 +1031,8 @@ static int setup(struct spi_device *spi) chip->cr0 = clk_div | SSCR0_Motorola - | SSCR0_DataSize(spi->bits_per_word & 0x0f) + | SSCR0_DataSize(spi->bits_per_word > 16 ? + spi->bits_per_word - 16 : spi->bits_per_word) | SSCR0_SSE | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0); chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) << 4) @@ -1196,7 +1215,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev) goto out_error_master_alloc; } - drv_data->ioaddr = (void *)io_p2v(memory_resource->start); + drv_data->ioaddr = (void *)io_p2v((unsigned long)(memory_resource->start)); drv_data->ssdr_physical = memory_resource->start + 0x00000010; if (platform_info->ssp_type == PXA25x_SSP) { drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; @@ -1218,7 +1237,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev) goto out_error_master_alloc; } - status = request_irq(irq, ssp_int, SA_INTERRUPT, dev->bus_id, drv_data); + status = request_irq(irq, ssp_int, 0, dev->bus_id, drv_data); if (status < 0) { dev_err(&pdev->dev, "can not get IRQ\n"); goto out_error_master_alloc; diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 7a3f733051e..1cea4a6799f 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -338,18 +338,18 @@ static struct class spi_master_class = { * spi_alloc_master - allocate SPI master controller * @dev: the controller, possibly using the platform_bus * @size: how much driver-private data to preallocate; the pointer to this - * memory is in the class_data field of the returned class_device, + * memory is in the class_data field of the returned class_device, * accessible with spi_master_get_devdata(). * * This call is used only by SPI master controller drivers, which are the * only ones directly touching chip registers. It's how they allocate - * an spi_master structure, prior to calling spi_add_master(). + * an spi_master structure, prior to calling spi_register_master(). * * This must be called from context that can sleep. It returns the SPI * master structure on success, else NULL. * * The caller is responsible for assigning the bus number and initializing - * the master's methods before calling spi_add_master(); and (after errors + * the master's methods before calling spi_register_master(); and (after errors * adding the device) calling spi_master_put() to prevent a memory leak. */ struct spi_master * __init_or_module diff --git a/drivers/spi/spi_butterfly.c b/drivers/spi/spi_butterfly.c index ff9e5faa4dc..a006a1ee27a 100644 --- a/drivers/spi/spi_butterfly.c +++ b/drivers/spi/spi_butterfly.c @@ -321,6 +321,7 @@ static void butterfly_attach(struct parport *p) * (firmware resets at45, acts as spi slave) or neither (we ignore * both, AVR uses AT45). Here we expect firmware for the first option. */ + pp->info[0].max_speed_hz = 15 * 1000 * 1000; strcpy(pp->info[0].modalias, "mtd_dataflash"); pp->info[0].platform_data = &flash; diff --git a/drivers/spi/spi_mpc83xx.c b/drivers/spi/spi_mpc83xx.c new file mode 100644 index 00000000000..5d92a7e5cb4 --- /dev/null +++ b/drivers/spi/spi_mpc83xx.c @@ -0,0 +1,483 @@ +/* + * MPC83xx SPI controller driver. + * + * Maintainer: Kumar Gala + * + * Copyright (C) 2006 Polycom, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include <linux/module.h> +#include <linux/init.h> +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/completion.h> +#include <linux/interrupt.h> +#include <linux/delay.h> +#include <linux/irq.h> +#include <linux/device.h> +#include <linux/spi/spi.h> +#include <linux/spi/spi_bitbang.h> +#include <linux/platform_device.h> +#include <linux/fsl_devices.h> + +#include <asm/irq.h> +#include <asm/io.h> + +/* SPI Controller registers */ +struct mpc83xx_spi_reg { + u8 res1[0x20]; + __be32 mode; + __be32 event; + __be32 mask; + __be32 command; + __be32 transmit; + __be32 receive; +}; + +/* SPI Controller mode register definitions */ +#define SPMODE_CI_INACTIVEHIGH (1 << 29) +#define SPMODE_CP_BEGIN_EDGECLK (1 << 28) +#define SPMODE_DIV16 (1 << 27) +#define SPMODE_REV (1 << 26) +#define SPMODE_MS (1 << 25) +#define SPMODE_ENABLE (1 << 24) +#define SPMODE_LEN(x) ((x) << 20) +#define SPMODE_PM(x) ((x) << 16) + +/* + * Default for SPI Mode: + * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk + */ +#define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \ + SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf)) + +/* SPIE register values */ +#define SPIE_NE 0x00000200 /* Not empty */ +#define SPIE_NF 0x00000100 /* Not full */ + +/* SPIM register values */ +#define SPIM_NE 0x00000200 /* Not empty */ +#define SPIM_NF 0x00000100 /* Not full */ + +/* SPI Controller driver's private data. */ +struct mpc83xx_spi { + /* bitbang has to be first */ + struct spi_bitbang bitbang; + struct completion done; + + struct mpc83xx_spi_reg __iomem *base; + + /* rx & tx bufs from the spi_transfer */ + const void *tx; + void *rx; + + /* functions to deal with different sized buffers */ + void (*get_rx) (u32 rx_data, struct mpc83xx_spi *); + u32(*get_tx) (struct mpc83xx_spi *); + + unsigned int count; + u32 irq; + + unsigned nsecs; /* (clock cycle time)/2 */ + + u32 sysclk; + void (*activate_cs) (u8 cs, u8 polarity); + void (*deactivate_cs) (u8 cs, u8 polarity); +}; + +static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val) +{ + out_be32(reg, val); +} + +static inline u32 mpc83xx_spi_read_reg(__be32 __iomem * reg) +{ + return in_be32(reg); +} + +#define MPC83XX_SPI_RX_BUF(type) \ +void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \ +{ \ + type * rx = mpc83xx_spi->rx; \ + *rx++ = (type)data; \ + mpc83xx_spi->rx = rx; \ +} + +#define MPC83XX_SPI_TX_BUF(type) \ +u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi) \ +{ \ + u32 data; \ + const type * tx = mpc83xx_spi->tx; \ + data = *tx++; \ + mpc83xx_spi->tx = tx; \ + return data; \ +} + +MPC83XX_SPI_RX_BUF(u8) +MPC83XX_SPI_RX_BUF(u16) +MPC83XX_SPI_RX_BUF(u32) +MPC83XX_SPI_TX_BUF(u8) +MPC83XX_SPI_TX_BUF(u16) +MPC83XX_SPI_TX_BUF(u32) + +static void mpc83xx_spi_chipselect(struct spi_device *spi, int value) +{ + struct mpc83xx_spi *mpc83xx_spi; + u8 pol = spi->mode & SPI_CS_HIGH ? 1 : 0; + + mpc83xx_spi = spi_master_get_devdata(spi->master); + + if (value == BITBANG_CS_INACTIVE) { + if (mpc83xx_spi->deactivate_cs) + mpc83xx_spi->deactivate_cs(spi->chip_select, pol); + } + + if (value == BITBANG_CS_ACTIVE) { + u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode); + u32 len = spi->bits_per_word; + if (len == 32) + len = 0; + else + len = len - 1; + + /* mask out bits we are going to set */ + regval &= ~0x38ff0000; + + if (spi->mode & SPI_CPHA) + regval |= SPMODE_CP_BEGIN_EDGECLK; + if (spi->mode & SPI_CPOL) + regval |= SPMODE_CI_INACTIVEHIGH; + + regval |= SPMODE_LEN(len); + + if ((mpc83xx_spi->sysclk / spi->max_speed_hz) >= 64) { + u8 pm = mpc83xx_spi->sysclk / (spi->max_speed_hz * 64); + regval |= SPMODE_PM(pm) | SPMODE_DIV16; + } else { + u8 pm = mpc83xx_spi->sysclk / (spi->max_speed_hz * 4); + regval |= SPMODE_PM(pm); + } + + mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval); + if (mpc83xx_spi->activate_cs) + mpc83xx_spi->activate_cs(spi->chip_select, pol); + } +} + +static +int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) +{ + struct mpc83xx_spi *mpc83xx_spi; + u32 regval; + u8 bits_per_word; + u32 hz; + + mpc83xx_spi = spi_master_get_devdata(spi->master); + + if (t) { + bits_per_word = t->bits_per_word; + hz = t->speed_hz; + } else { + bits_per_word = 0; + hz = 0; + } + + /* spi_transfer level calls that work per-word */ + if (!bits_per_word) + bits_per_word = spi->bits_per_word; + + /* Make sure its a bit width we support [4..16, 32] */ + if ((bits_per_word < 4) + || ((bits_per_word > 16) && (bits_per_word != 32))) + return -EINVAL; + + if (bits_per_word <= 8) { + mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8; + mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8; + } else if (bits_per_word <= 16) { + mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u16; + mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u16; + } else if (bits_per_word <= 32) { + mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u32; + mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u32; + } else + return -EINVAL; + + /* nsecs = (clock period)/2 */ + if (!hz) + hz = spi->max_speed_hz; + mpc83xx_spi->nsecs = (1000000000 / 2) / hz; + if (mpc83xx_spi->nsecs > MAX_UDELAY_MS * 1000) + return -EINVAL; + + if (bits_per_word == 32) + bits_per_word = 0; + else + bits_per_word = bits_per_word - 1; + + regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode); + + /* Mask out bits_per_wordgth */ + regval &= 0xff0fffff; + regval |= SPMODE_LEN(bits_per_word); + + mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval); + + return 0; +} + +static int mpc83xx_spi_setup(struct spi_device *spi) +{ + struct spi_bitbang *bitbang; + struct mpc83xx_spi *mpc83xx_spi; + int retval; + + if (!spi->max_speed_hz) + return -EINVAL; + + bitbang = spi_master_get_devdata(spi->master); + mpc83xx_spi = spi_master_get_devdata(spi->master); + + if (!spi->bits_per_word) + spi->bits_per_word = 8; + + retval = mpc83xx_spi_setup_transfer(spi, NULL); + if (retval < 0) + return retval; + + dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec\n", + __FUNCTION__, spi->mode & (SPI_CPOL | SPI_CPHA), + spi->bits_per_word, 2 * mpc83xx_spi->nsecs); + + /* NOTE we _need_ to call chipselect() early, ideally with adapter + * setup, unless the hardware defaults cooperate to avoid confusion + * between normal (active low) and inverted chipselects. + */ + + /* deselect chip (low or high) */ + spin_lock(&bitbang->lock); + if (!bitbang->busy) { + bitbang->chipselect(spi, BITBANG_CS_INACTIVE); + ndelay(mpc83xx_spi->nsecs); + } + spin_unlock(&bitbang->lock); + + return 0; +} + +static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t) +{ + struct mpc83xx_spi *mpc83xx_spi; + u32 word; + + mpc83xx_spi = spi_master_get_devdata(spi->master); + + mpc83xx_spi->tx = t->tx_buf; + mpc83xx_spi->rx = t->rx_buf; + mpc83xx_spi->count = t->len; + INIT_COMPLETION(mpc83xx_spi->done); + + /* enable rx ints */ + mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE); + + /* transmit word */ + word = mpc83xx_spi->get_tx(mpc83xx_spi); + mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word); + + wait_for_completion(&mpc83xx_spi->done); + + /* disable rx ints */ + mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0); + + return t->len - mpc83xx_spi->count; +} + +irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data, + struct pt_regs * ptregs) +{ + struct mpc83xx_spi *mpc83xx_spi = context_data; + u32 event; + irqreturn_t ret = IRQ_NONE; + + /* Get interrupt events(tx/rx) */ + event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event); + + /* We need handle RX first */ + if (event & SPIE_NE) { + u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive); + + if (mpc83xx_spi->rx) + mpc83xx_spi->get_rx(rx_data, mpc83xx_spi); + + ret = IRQ_HANDLED; + } + + if ((event & SPIE_NF) == 0) + /* spin until TX is done */ + while (((event = + mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) & + SPIE_NF) == 0) + cpu_relax(); + + mpc83xx_spi->count -= 1; + if (mpc83xx_spi->count) { + if (mpc83xx_spi->tx) { + u32 word = mpc83xx_spi->get_tx(mpc83xx_spi); + mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, + word); + } + } else { + complete(&mpc83xx_spi->done); + } + + /* Clear the events */ + mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event); + + return ret; +} + +static int __init mpc83xx_spi_probe(struct platform_device *dev) +{ + struct spi_master *master; + struct mpc83xx_spi *mpc83xx_spi; + struct fsl_spi_platform_data *pdata; + struct resource *r; + u32 regval; + int ret = 0; + + /* Get resources(memory, IRQ) associated with the device */ + master = spi_alloc_master(&dev->dev, sizeof(struct mpc83xx_spi)); + + if (master == NULL) { + ret = -ENOMEM; + goto err; + } + + platform_set_drvdata(dev, master); + pdata = dev->dev.platform_data; + + if (pdata == NULL) { + ret = -ENODEV; + goto free_master; + } + + r = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (r == NULL) { + ret = -ENODEV; + goto free_master; + } + + mpc83xx_spi = spi_master_get_devdata(master); + mpc83xx_spi->bitbang.master = spi_master_get(master); + mpc83xx_spi->bitbang.chipselect = mpc83xx_spi_chipselect; + mpc83xx_spi->bitbang.setup_transfer = mpc83xx_spi_setup_transfer; + mpc83xx_spi->bitbang.txrx_bufs = mpc83xx_spi_bufs; + mpc83xx_spi->sysclk = pdata->sysclk; + mpc83xx_spi->activate_cs = pdata->activate_cs; + mpc83xx_spi->deactivate_cs = pdata->deactivate_cs; + mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8; + mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8; + + mpc83xx_spi->bitbang.master->setup = mpc83xx_spi_setup; + init_completion(&mpc83xx_spi->done); + + mpc83xx_spi->base = ioremap(r->start, r->end - r->start + 1); + if (mpc83xx_spi->base == NULL) { + ret = -ENOMEM; + goto put_master; + } + + mpc83xx_spi->irq = platform_get_irq(dev, 0); + + if (mpc83xx_spi->irq < 0) { + ret = -ENXIO; + goto unmap_io; + } + + /* Register for SPI Interrupt */ + ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq, + 0, "mpc83xx_spi", mpc83xx_spi); + + if (ret != 0) + goto unmap_io; + + master->bus_num = pdata->bus_num; + master->num_chipselect = pdata->max_chipselect; + + /* SPI controller initializations */ + mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0); + mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0); + mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0); + mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff); + + /* Enable SPI interface */ + regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; + mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval); + + ret = spi_bitbang_start(&mpc83xx_spi->bitbang); + + if (ret != 0) + goto free_irq; + + printk(KERN_INFO + "%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n", + dev->dev.bus_id, mpc83xx_spi->base, mpc83xx_spi->irq); + + return ret; + +free_irq: + free_irq(mpc83xx_spi->irq, mpc83xx_spi); +unmap_io: + iounmap(mpc83xx_spi->base); +put_master: + spi_master_put(master); +free_master: + kfree(master); +err: + return ret; +} + +static int __devexit mpc83xx_spi_remove(struct platform_device *dev) +{ + struct mpc83xx_spi *mpc83xx_spi; + struct spi_master *master; + + master = platform_get_drvdata(dev); + mpc83xx_spi = spi_master_get_devdata(master); + + spi_bitbang_stop(&mpc83xx_spi->bitbang); + free_irq(mpc83xx_spi->irq, mpc83xx_spi); + iounmap(mpc83xx_spi->base); + spi_master_put(mpc83xx_spi->bitbang.master); + + return 0; +} + +static struct platform_driver mpc83xx_spi_driver = { + .probe = mpc83xx_spi_probe, + .remove = __devexit_p(mpc83xx_spi_remove), + .driver = { + .name = "mpc83xx_spi", + }, +}; + +static int __init mpc83xx_spi_init(void) +{ + return platform_driver_register(&mpc83xx_spi_driver); +} + +static void __exit mpc83xx_spi_exit(void) +{ + platform_driver_unregister(&mpc83xx_spi_driver); +} + +module_init(mpc83xx_spi_init); +module_exit(mpc83xx_spi_exit); + +MODULE_AUTHOR("Kumar Gala"); +MODULE_DESCRIPTION("Simple MPC83xx SPI Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/spi/spi_s3c24xx.c b/drivers/spi/spi_s3c24xx.c new file mode 100644 index 00000000000..5fc14563ee3 --- /dev/null +++ b/drivers/spi/spi_s3c24xx.c @@ -0,0 +1,453 @@ +/* linux/drivers/spi/spi_s3c24xx.c + * + * Copyright (c) 2006 Ben Dooks + * Copyright (c) 2006 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + + +//#define DEBUG + +#include <linux/config.h> +#include <linux/init.h> +#include <linux/spinlock.h> +#include <linux/workqueue.h> +#include <linux/interrupt.h> +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/platform_device.h> + +#include <linux/spi/spi.h> +#include <linux/spi/spi_bitbang.h> + +#include <asm/io.h> +#include <asm/dma.h> +#include <asm/hardware.h> + +#include <asm/arch/regs-gpio.h> +#include <asm/arch/regs-spi.h> +#include <asm/arch/spi.h> + +struct s3c24xx_spi { + /* bitbang has to be first */ + struct spi_bitbang bitbang; + struct completion done; + + void __iomem *regs; + int irq; + int len; + int count; + + /* data buffers */ + const unsigned char *tx; + unsigned char *rx; + + struct clk *clk; + struct resource *ioarea; + struct spi_master *master; + struct spi_device *curdev; + struct device *dev; + struct s3c2410_spi_info *pdata; +}; + +#define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT) +#define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP) + +static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev) +{ + return spi_master_get_devdata(sdev->master); +} + +static void s3c24xx_spi_chipsel(struct spi_device *spi, int value) +{ + struct s3c24xx_spi *hw = to_hw(spi); + unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0; + unsigned int spcon; + + switch (value) { + case BITBANG_CS_INACTIVE: + if (hw->pdata->set_cs) + hw->pdata->set_cs(hw->pdata, value, cspol); + else + s3c2410_gpio_setpin(hw->pdata->pin_cs, cspol ^ 1); + break; + + case BITBANG_CS_ACTIVE: + spcon = readb(hw->regs + S3C2410_SPCON); + + if (spi->mode & SPI_CPHA) + spcon |= S3C2410_SPCON_CPHA_FMTB; + else + spcon &= ~S3C2410_SPCON_CPHA_FMTB; + + if (spi->mode & SPI_CPOL) + spcon |= S3C2410_SPCON_CPOL_HIGH; + else + spcon &= ~S3C2410_SPCON_CPOL_HIGH; + + spcon |= S3C2410_SPCON_ENSCK; + + /* write new configration */ + + writeb(spcon, hw->regs + S3C2410_SPCON); + + if (hw->pdata->set_cs) + hw->pdata->set_cs(hw->pdata, value, cspol); + else + s3c2410_gpio_setpin(hw->pdata->pin_cs, cspol); + + break; + + } +} + +static int s3c24xx_spi_setupxfer(struct spi_device *spi, + struct spi_transfer *t) +{ + struct s3c24xx_spi *hw = to_hw(spi); + unsigned int bpw; + unsigned int hz; + unsigned int div; + + bpw = t ? t->bits_per_word : spi->bits_per_word; + hz = t ? t->speed_hz : spi->max_speed_hz; + + if (bpw != 8) { + dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw); + return -EINVAL; + } + + div = clk_get_rate(hw->clk) / hz; + + /* is clk = pclk / (2 * (pre+1)), or is it + * clk = (pclk * 2) / ( pre + 1) */ + + div = (div / 2) - 1; + + if (div < 0) + div = 1; + + if (div > 255) + div = 255; + + dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", div, hz); + writeb(div, hw->regs + S3C2410_SPPRE); + + spin_lock(&hw->bitbang.lock); + if (!hw->bitbang.busy) { + hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE); + /* need to ndelay for 0.5 clocktick ? */ + } + spin_unlock(&hw->bitbang.lock); + + return 0; +} + +static int s3c24xx_spi_setup(struct spi_device *spi) +{ + int ret; + + if (!spi->bits_per_word) + spi->bits_per_word = 8; + + if ((spi->mode & SPI_LSB_FIRST) != 0) + return -EINVAL; + + ret = s3c24xx_spi_setupxfer(spi, NULL); + if (ret < 0) { + dev_err(&spi->dev, "setupxfer returned %d\n", ret); + return ret; + } + + dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", + __FUNCTION__, spi->mode, spi->bits_per_word, + spi->max_speed_hz); + + return 0; +} + +static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count) +{ + return hw->tx ? hw->tx[count] : 0xff; +} + +static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t) +{ + struct s3c24xx_spi *hw = to_hw(spi); + + dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", + t->tx_buf, t->rx_buf, t->len); + + hw->tx = t->tx_buf; + hw->rx = t->rx_buf; + hw->len = t->len; + hw->count = 0; + + /* send the first byte */ + writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT); + wait_for_completion(&hw->done); + + return hw->count; +} + +static irqreturn_t s3c24xx_spi_irq(int irq, void *dev, struct pt_regs *regs) +{ + struct s3c24xx_spi *hw = dev; + unsigned int spsta = readb(hw->regs + S3C2410_SPSTA); + unsigned int count = hw->count; + + if (spsta & S3C2410_SPSTA_DCOL) { + dev_dbg(hw->dev, "data-collision\n"); + complete(&hw->done); + goto irq_done; + } + + if (!(spsta & S3C2410_SPSTA_READY)) { + dev_dbg(hw->dev, "spi not ready for tx?\n"); + complete(&hw->done); + goto irq_done; + } + + hw->count++; + + if (hw->rx) + hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT); + + count++; + + if (count < hw->len) + writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT); + else + complete(&hw->done); + + irq_done: + return IRQ_HANDLED; +} + +static int s3c24xx_spi_probe(struct platform_device *pdev) +{ + struct s3c24xx_spi *hw; + struct spi_master *master; + struct spi_board_info *bi; + struct resource *res; + int err = 0; + int i; + + master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi)); + if (master == NULL) { + dev_err(&pdev->dev, "No memory for spi_master\n"); + err = -ENOMEM; + goto err_nomem; + } + + hw = spi_master_get_devdata(master); + memset(hw, 0, sizeof(struct s3c24xx_spi)); + + hw->master = spi_master_get(master); + hw->pdata = pdev->dev.platform_data; + hw->dev = &pdev->dev; + + if (hw->pdata == NULL) { + dev_err(&pdev->dev, "No platform data supplied\n"); + err = -ENOENT; + goto err_no_pdata; + } + + platform_set_drvdata(pdev, hw); + init_completion(&hw->done); + + /* setup the state for the bitbang driver */ + + hw->bitbang.master = hw->master; + hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer; + hw->bitbang.chipselect = s3c24xx_spi_chipsel; + hw->bitbang.txrx_bufs = s3c24xx_spi_txrx; + hw->bitbang.master->setup = s3c24xx_spi_setup; + + dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang); + + /* find and map our resources */ + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n"); + err = -ENOENT; + goto err_no_iores; + } + + hw->ioarea = request_mem_region(res->start, (res->end - res->start)+1, + pdev->name); + + if (hw->ioarea == NULL) { + dev_err(&pdev->dev, "Cannot reserve region\n"); + err = -ENXIO; + goto err_no_iores; + } + + hw->regs = ioremap(res->start, (res->end - res->start)+1); + if (hw->regs == NULL) { + dev_err(&pdev->dev, "Cannot map IO\n"); + err = -ENXIO; + goto err_no_iomap; + } + + hw->irq = platform_get_irq(pdev, 0); + if (hw->irq < 0) { + dev_err(&pdev->dev, "No IRQ specified\n"); + err = -ENOENT; + goto err_no_irq; + } + + err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw); + if (err) { + dev_err(&pdev->dev, "Cannot claim IRQ\n"); + goto err_no_irq; + } + + hw->clk = clk_get(&pdev->dev, "spi"); + if (IS_ERR(hw->clk)) { + dev_err(&pdev->dev, "No clock for device\n"); + err = PTR_ERR(hw->clk); + goto err_no_clk; + } + + /* for the moment, permanently enable the clock */ + + clk_enable(hw->clk); + + /* program defaults into the registers */ + + writeb(0xff, hw->regs + S3C2410_SPPRE); + writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN); + writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON); + + /* setup any gpio we can */ + + if (!hw->pdata->set_cs) { + s3c2410_gpio_setpin(hw->pdata->pin_cs, 1); + s3c2410_gpio_cfgpin(hw->pdata->pin_cs, S3C2410_GPIO_OUTPUT); + } + + /* register our spi controller */ + + err = spi_bitbang_start(&hw->bitbang); + if (err) { + dev_err(&pdev->dev, "Failed to register SPI master\n"); + goto err_register; + } + + dev_dbg(hw->dev, "shutdown=%d\n", hw->bitbang.shutdown); + + /* register all the devices associated */ + + bi = &hw->pdata->board_info[0]; + for (i = 0; i < hw->pdata->board_size; i++, bi++) { + dev_info(hw->dev, "registering %s\n", bi->modalias); + + bi->controller_data = hw; + spi_new_device(master, bi); + } + + return 0; + + err_register: + clk_disable(hw->clk); + clk_put(hw->clk); + + err_no_clk: + free_irq(hw->irq, hw); + + err_no_irq: + iounmap(hw->regs); + + err_no_iomap: + release_resource(hw->ioarea); + kfree(hw->ioarea); + + err_no_iores: + err_no_pdata: + spi_master_put(hw->master);; + + err_nomem: + return err; +} + +static int s3c24xx_spi_remove(struct platform_device *dev) +{ + struct s3c24xx_spi *hw = platform_get_drvdata(dev); + + platform_set_drvdata(dev, NULL); + + spi_unregister_master(hw->master); + + clk_disable(hw->clk); + clk_put(hw->clk); + + free_irq(hw->irq, hw); + iounmap(hw->regs); + + release_resource(hw->ioarea); + kfree(hw->ioarea); + + spi_master_put(hw->master); + return 0; +} + + +#ifdef CONFIG_PM + +static int s3c24xx_spi_suspend(struct platform_device *pdev, pm_message_t msg) +{ + struct s3c24xx_spi *hw = platform_get_drvdata(pdev); + + clk_disable(hw->clk); + return 0; +} + +static int s3c24xx_spi_resume(struct platform_device *pdev) +{ + struct s3c24xx_spi *hw = platform_get_drvdata(pdev); + + clk_enable(hw->clk); + return 0; +} + +#else +#define s3c24xx_spi_suspend NULL +#define s3c24xx_spi_resume NULL +#endif + +static struct platform_driver s3c24xx_spidrv = { + .probe = s3c24xx_spi_probe, + .remove = s3c24xx_spi_remove, + .suspend = s3c24xx_spi_suspend, + .resume = s3c24xx_spi_resume, + .driver = { + .name = "s3c2410-spi", + .owner = THIS_MODULE, + }, +}; + +static int __init s3c24xx_spi_init(void) +{ + return platform_driver_register(&s3c24xx_spidrv); +} + +static void __exit s3c24xx_spi_exit(void) +{ + platform_driver_unregister(&s3c24xx_spidrv); +} + +module_init(s3c24xx_spi_init); +module_exit(s3c24xx_spi_exit); + +MODULE_DESCRIPTION("S3C24XX SPI Driver"); +MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/spi/spi_s3c24xx_gpio.c b/drivers/spi/spi_s3c24xx_gpio.c new file mode 100644 index 00000000000..aacdceb8f44 --- /dev/null +++ b/drivers/spi/spi_s3c24xx_gpio.c @@ -0,0 +1,188 @@ +/* linux/drivers/spi/spi_s3c24xx_gpio.c + * + * Copyright (c) 2006 Ben Dooks + * Copyright (c) 2006 Simtec Electronics + * + * S3C24XX GPIO based SPI driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + +#include <linux/config.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/spinlock.h> +#include <linux/platform_device.h> + +#include <linux/spi/spi.h> +#include <linux/spi/spi_bitbang.h> + +#include <asm/arch/regs-gpio.h> +#include <asm/arch/spi-gpio.h> +#include <asm/arch/hardware.h> + +struct s3c2410_spigpio { + struct spi_bitbang bitbang; + + struct s3c2410_spigpio_info *info; + struct platform_device *dev; +}; + +static inline struct s3c2410_spigpio *spidev_to_sg(struct spi_device *spi) +{ + return spi->controller_data; +} + +static inline void setsck(struct spi_device *dev, int on) +{ + struct s3c2410_spigpio *sg = spidev_to_sg(dev); + s3c2410_gpio_setpin(sg->info->pin_clk, on ? 1 : 0); +} + +static inline void setmosi(struct spi_device *dev, int on) +{ + struct s3c2410_spigpio *sg = spidev_to_sg(dev); + s3c2410_gpio_setpin(sg->info->pin_mosi, on ? 1 : 0); +} + +static inline u32 getmiso(struct spi_device *dev) +{ + struct s3c2410_spigpio *sg = spidev_to_sg(dev); + return s3c2410_gpio_getpin(sg->info->pin_miso) ? 1 : 0; +} + +#define spidelay(x) ndelay(x) + +#define EXPAND_BITBANG_TXRX +#include <linux/spi/spi_bitbang.h> + + +static u32 s3c2410_spigpio_txrx_mode0(struct spi_device *spi, + unsigned nsecs, u32 word, u8 bits) +{ + return bitbang_txrx_be_cpha0(spi, nsecs, 0, word, bits); +} + +static u32 s3c2410_spigpio_txrx_mode1(struct spi_device *spi, + unsigned nsecs, u32 word, u8 bits) +{ + return bitbang_txrx_be_cpha1(spi, nsecs, 0, word, bits); +} + +static void s3c2410_spigpio_chipselect(struct spi_device *dev, int value) +{ + struct s3c2410_spigpio *sg = spidev_to_sg(dev); + + if (sg->info && sg->info->chip_select) + (sg->info->chip_select)(sg->info, value); +} + +static int s3c2410_spigpio_probe(struct platform_device *dev) +{ + struct spi_master *master; + struct s3c2410_spigpio *sp; + int ret; + int i; + + master = spi_alloc_master(&dev->dev, sizeof(struct s3c2410_spigpio)); + if (master == NULL) { + dev_err(&dev->dev, "failed to allocate spi master\n"); + ret = -ENOMEM; + goto err; + } + + sp = spi_master_get_devdata(master); + + platform_set_drvdata(dev, sp); + + /* copy in the plkatform data */ + sp->info = dev->dev.platform_data; + + /* setup spi bitbang adaptor */ + sp->bitbang.master = spi_master_get(master); + sp->bitbang.chipselect = s3c2410_spigpio_chipselect; + + sp->bitbang.txrx_word[SPI_MODE_0] = s3c2410_spigpio_txrx_mode0; + sp->bitbang.txrx_word[SPI_MODE_1] = s3c2410_spigpio_txrx_mode1; + + /* set state of spi pins */ + s3c2410_gpio_setpin(sp->info->pin_clk, 0); + s3c2410_gpio_setpin(sp->info->pin_mosi, 0); + + s3c2410_gpio_cfgpin(sp->info->pin_clk, S3C2410_GPIO_OUTPUT); + s3c2410_gpio_cfgpin(sp->info->pin_mosi, S3C2410_GPIO_OUTPUT); + s3c2410_gpio_cfgpin(sp->info->pin_miso, S3C2410_GPIO_INPUT); + + ret = spi_bitbang_start(&sp->bitbang); + if (ret) + goto err_no_bitbang; + + /* register the chips to go with the board */ + + for (i = 0; i < sp->info->board_size; i++) { + dev_info(&dev->dev, "registering %p: %s\n", + &sp->info->board_info[i], + sp->info->board_info[i].modalias); + + sp->info->board_info[i].controller_data = sp; + spi_new_device(master, sp->info->board_info + i); + } + + return 0; + + err_no_bitbang: + spi_master_put(sp->bitbang.master); + err: + return ret; + +} + +static int s3c2410_spigpio_remove(struct platform_device *dev) +{ + struct s3c2410_spigpio *sp = platform_get_drvdata(dev); + + spi_bitbang_stop(&sp->bitbang); + spi_master_put(sp->bitbang.master); + + return 0; +} + +/* all gpio should be held over suspend/resume, so we should + * not need to deal with this +*/ + +#define s3c2410_spigpio_suspend NULL +#define s3c2410_spigpio_resume NULL + + +static struct platform_driver s3c2410_spigpio_drv = { + .probe = s3c2410_spigpio_probe, + .remove = s3c2410_spigpio_remove, + .suspend = s3c2410_spigpio_suspend, + .resume = s3c2410_spigpio_resume, + .driver = { + .name = "s3c24xx-spi-gpio", + .owner = THIS_MODULE, + }, +}; + +static int __init s3c2410_spigpio_init(void) +{ + return platform_driver_register(&s3c2410_spigpio_drv); +} + +static void __exit s3c2410_spigpio_exit(void) +{ + platform_driver_unregister(&s3c2410_spigpio_drv); +} + +module_init(s3c2410_spigpio_init); +module_exit(s3c2410_spigpio_exit); + +MODULE_DESCRIPTION("S3C24XX SPI Driver"); +MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); +MODULE_LICENSE("GPL"); |