diff options
Diffstat (limited to 'drivers/staging/agnx')
-rw-r--r-- | drivers/staging/agnx/agnx.h | 14 | ||||
-rw-r--r-- | drivers/staging/agnx/debug.h | 21 | ||||
-rw-r--r-- | drivers/staging/agnx/pci.c | 75 | ||||
-rw-r--r-- | drivers/staging/agnx/phy.c | 32 | ||||
-rw-r--r-- | drivers/staging/agnx/rf.c | 23 | ||||
-rw-r--r-- | drivers/staging/agnx/sta.c | 21 | ||||
-rw-r--r-- | drivers/staging/agnx/sta.h | 2 | ||||
-rw-r--r-- | drivers/staging/agnx/table.c | 12 | ||||
-rw-r--r-- | drivers/staging/agnx/xmit.c | 216 |
9 files changed, 214 insertions, 202 deletions
diff --git a/drivers/staging/agnx/agnx.h b/drivers/staging/agnx/agnx.h index 20f36da6247..3963d2597a1 100644 --- a/drivers/staging/agnx/agnx.h +++ b/drivers/staging/agnx/agnx.h @@ -41,16 +41,16 @@ static const struct ieee80211_rate agnx_rates_80211g[] = { /* { .bitrate = 20, .hw_value = 2, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, */ /* { .bitrate = 55, .hw_value = 3, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, */ /* { .bitrate = 110, .hw_value = 4, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, */ - { .bitrate = 10, .hw_value = 1, }, - { .bitrate = 20, .hw_value = 2, }, - { .bitrate = 55, .hw_value = 3, }, - { .bitrate = 110, .hw_value = 4,}, + { .bitrate = 10, .hw_value = 1, }, + { .bitrate = 20, .hw_value = 2, }, + { .bitrate = 55, .hw_value = 3, }, + { .bitrate = 110, .hw_value = 4,}, { .bitrate = 60, .hw_value = 0xB, }, { .bitrate = 90, .hw_value = 0xF, }, { .bitrate = 120, .hw_value = 0xA }, { .bitrate = 180, .hw_value = 0xE, }, -// { .bitrate = 240, .hw_value = 0xd, }, +/* { .bitrate = 240, .hw_value = 0xd, }, */ { .bitrate = 360, .hw_value = 0xD, }, { .bitrate = 480, .hw_value = 0x8, }, { .bitrate = 540, .hw_value = 0xC, }, @@ -110,10 +110,10 @@ struct agnx_priv { /* Need volatile? */ u32 irq_status; - struct delayed_work periodic_work; /* Periodic tasks like recalibrate*/ + struct delayed_work periodic_work; /* Periodic tasks like recalibrate */ struct ieee80211_low_level_stats stats; -// unsigned int phymode; + /* unsigned int phymode; */ int mode; int channel; u8 bssid[ETH_ALEN]; diff --git a/drivers/staging/agnx/debug.h b/drivers/staging/agnx/debug.h index e3e25dda0ba..761d99c2d3f 100644 --- a/drivers/staging/agnx/debug.h +++ b/drivers/staging/agnx/debug.h @@ -23,7 +23,7 @@ static inline void agnx_bug(char *reason) static inline void agnx_print_desc(struct agnx_desc *desc) { - u32 reg = be32_to_cpu(desc->frag); + u32 reg = be32_to_cpu(desc->frag); PRINTK_BITS(DESC, PACKET_LEN); @@ -291,7 +291,7 @@ static inline void agnx_print_sta(struct agnx_priv *priv, unsigned int sta_idx) PRINTK_LE32(STA, sta->phy_stats_high); PRINTK_LE32(STA, sta->phy_stats_low); -// for (i = 0; i < 8; i++) + /* for (i = 0; i < 8; i++) */ agnx_print_sta_traffic(sta->traffic + 0); PRINTK_LE16(STA, sta->traffic_class0_frag_success); @@ -311,10 +311,10 @@ static inline void agnx_print_sta(struct agnx_priv *priv, unsigned int sta_idx) static inline void dump_ieee80211_hdr(struct ieee80211_hdr *hdr, char *tag) { u16 fctl; - int hdrlen; + int hdrlen; DECLARE_MAC_BUF(mac); - fctl = le16_to_cpu(hdr->frame_control); + fctl = le16_to_cpu(hdr->frame_control); switch (fctl & IEEE80211_FCTL_FTYPE) { case IEEE80211_FTYPE_DATA: printk(PFX "%s DATA ", tag); @@ -324,7 +324,7 @@ static inline void dump_ieee80211_hdr(struct ieee80211_hdr *hdr, char *tag) break; case IEEE80211_FTYPE_MGMT: printk(PFX "%s MGMT ", tag); - switch(fctl & IEEE80211_FCTL_STYPE) { + switch (fctl & IEEE80211_FCTL_STYPE) { case IEEE80211_STYPE_ASSOC_REQ: printk("SubType: ASSOC_REQ "); break; @@ -369,7 +369,7 @@ static inline void dump_ieee80211_hdr(struct ieee80211_hdr *hdr, char *tag) printk(PFX "%s Packet type: Unknow\n", tag); } - hdrlen = ieee80211_hdrlen(fctl); + hdrlen = ieee80211_hdrlen(fctl); if (hdrlen >= 4) printk("FC=0x%04x DUR=0x%04x", @@ -389,29 +389,28 @@ static inline void dump_txm_registers(struct agnx_priv *priv) { void __iomem *ctl = priv->ctl; int i; - for (i = 0; i <=0x1e8; i += 4) { + for (i = 0; i <= 0x1e8; i += 4) printk(KERN_DEBUG PFX "TXM: %x---> 0x%.8x\n", i, ioread32(ctl + i)); - } } static inline void dump_rxm_registers(struct agnx_priv *priv) { void __iomem *ctl = priv->ctl; int i; - for (i = 0; i <=0x108; i += 4) + for (i = 0; i <= 0x108; i += 4) printk(KERN_DEBUG PFX "RXM: %x---> 0x%.8x\n", i, ioread32(ctl + 0x2000 + i)); } static inline void dump_bm_registers(struct agnx_priv *priv) { void __iomem *ctl = priv->ctl; int i; - for (i = 0; i <=0x90; i += 4) + for (i = 0; i <= 0x90; i += 4) printk(KERN_DEBUG PFX "BM: %x---> 0x%.8x\n", i, ioread32(ctl + 0x2c00 + i)); } static inline void dump_cir_registers(struct agnx_priv *priv) { void __iomem *ctl = priv->ctl; int i; - for (i = 0; i <=0xb8; i += 4) + for (i = 0; i <= 0xb8; i += 4) printk(KERN_DEBUG PFX "CIR: %x---> 0x%.8x\n", i, ioread32(ctl + 0x3000 + i)); } diff --git a/drivers/staging/agnx/pci.c b/drivers/staging/agnx/pci.c index 854630cb527..4ff4c160142 100644 --- a/drivers/staging/agnx/pci.c +++ b/drivers/staging/agnx/pci.c @@ -39,34 +39,34 @@ static inline void agnx_interrupt_ack(struct agnx_priv *priv, u32 *reason) void __iomem *ctl = priv->ctl; u32 reg; - if ( *reason & AGNX_STAT_RX ) { + if (*reason & AGNX_STAT_RX) { /* Mark complete RX */ reg = ioread32(ctl + AGNX_CIR_RXCTL); reg |= 0x4; iowrite32(reg, ctl + AGNX_CIR_RXCTL); /* disable Rx interrupt */ } - if ( *reason & AGNX_STAT_TX ) { + if (*reason & AGNX_STAT_TX) { reg = ioread32(ctl + AGNX_CIR_TXDCTL); if (reg & 0x4) { iowrite32(reg, ctl + AGNX_CIR_TXDCTL); *reason |= AGNX_STAT_TXD; } - reg = ioread32(ctl + AGNX_CIR_TXMCTL); + reg = ioread32(ctl + AGNX_CIR_TXMCTL); if (reg & 0x4) { iowrite32(reg, ctl + AGNX_CIR_TXMCTL); *reason |= AGNX_STAT_TXM; } } - if ( *reason & AGNX_STAT_X ) { -/* reg = ioread32(ctl + AGNX_INT_STAT); */ -/* iowrite32(reg, ctl + AGNX_INT_STAT); */ -/* /\* FIXME reinit interrupt mask *\/ */ -/* reg = 0xc390bf9 & ~IRQ_TX_BEACON; */ -/* reg &= ~IRQ_TX_DISABLE; */ -/* iowrite32(reg, ctl + AGNX_INT_MASK); */ -/* iowrite32(0x800, ctl + AGNX_CIR_BLKCTL); */ - } +/* if (*reason & AGNX_STAT_X) { + reg = ioread32(ctl + AGNX_INT_STAT); + iowrite32(reg, ctl + AGNX_INT_STAT); + /* FIXME reinit interrupt mask *\/ + reg = 0xc390bf9 & ~IRQ_TX_BEACON; + reg &= ~IRQ_TX_DISABLE; + iowrite32(reg, ctl + AGNX_INT_MASK); + iowrite32(0x800, ctl + AGNX_CIR_BLKCTL); + } */ } /* agnx_interrupt_ack */ static irqreturn_t agnx_interrupt_handler(int irq, void *dev_id) @@ -79,7 +79,7 @@ static irqreturn_t agnx_interrupt_handler(int irq, void *dev_id) spin_lock(&priv->lock); -// printk(KERN_ERR PFX "Get a interrupt %s\n", __func__); +/* printk(KERN_ERR PFX "Get a interrupt %s\n", __func__); */ if (priv->init_status != AGNX_START) goto out; @@ -92,7 +92,7 @@ static irqreturn_t agnx_interrupt_handler(int irq, void *dev_id) ret = IRQ_HANDLED; priv->irq_status = ioread32(ctl + AGNX_INT_STAT); -// printk(PFX "Interrupt reason is 0x%x\n", irq_reason); +/* printk(PFX "Interrupt reason is 0x%x\n", irq_reason); */ /* Make sure the txm and txd flags don't conflict with other unknown interrupt flag, maybe is not necessary */ irq_reason &= 0xF; @@ -101,13 +101,13 @@ static irqreturn_t agnx_interrupt_handler(int irq, void *dev_id) /* TODO Make sure the card finished initialized */ agnx_interrupt_ack(priv, &irq_reason); - if ( irq_reason & AGNX_STAT_RX ) + if (irq_reason & AGNX_STAT_RX) handle_rx_irq(priv); - if ( irq_reason & AGNX_STAT_TXD ) + if (irq_reason & AGNX_STAT_TXD) handle_txd_irq(priv); - if ( irq_reason & AGNX_STAT_TXM ) + if (irq_reason & AGNX_STAT_TXM) handle_txm_irq(priv); - if ( irq_reason & AGNX_STAT_X ) + if (irq_reason & AGNX_STAT_X) handle_other_irq(priv); enable_rx_interrupt(priv); @@ -171,7 +171,7 @@ static int agnx_alloc_rings(struct agnx_priv *priv) len = priv->rx.size + priv->txm.size + priv->txd.size; -// priv->rx.info = kzalloc(sizeof(struct agnx_info) * len, GFP_KERNEL); +/* priv->rx.info = kzalloc(sizeof(struct agnx_info) * len, GFP_KERNEL); */ priv->rx.info = kzalloc(sizeof(struct agnx_info) * len, GFP_ATOMIC); if (!priv->rx.info) return -ENOMEM; @@ -210,28 +210,27 @@ static void rings_free(struct agnx_priv *priv) #if 0 static void agnx_periodic_work_handler(struct work_struct *work) { - struct agnx_priv *priv = container_of(work, struct agnx_priv, - periodic_work.work); -// unsigned long flags; + struct agnx_priv *priv = container_of(work, struct agnx_priv, periodic_work.work); +/* unsigned long flags; */ unsigned long delay; /* fixme: using mutex?? */ -// spin_lock_irqsave(&priv->lock, flags); +/* spin_lock_irqsave(&priv->lock, flags); */ /* TODO Recalibrate*/ -// calibrate_oscillator(priv); -// antenna_calibrate(priv); -// agnx_send_packet(priv, 997); +/* calibrate_oscillator(priv); */ +/* antenna_calibrate(priv); */ +/* agnx_send_packet(priv, 997); / /* FIXME */ /* if (debug == 3) */ /* delay = msecs_to_jiffies(AGNX_PERIODIC_DELAY); */ /* else */ delay = msecs_to_jiffies(AGNX_PERIODIC_DELAY); -// delay = round_jiffies(HZ * 15); +/* delay = round_jiffies(HZ * 15); */ queue_delayed_work(priv->hw->workqueue, &priv->periodic_work, delay); -// spin_unlock_irqrestore(&priv->lock, flags); +/* spin_unlock_irqrestore(&priv->lock, flags); */ } #endif @@ -255,12 +254,12 @@ static int agnx_start(struct ieee80211_hw *dev) goto out; } -// mdelay(500); +/* mdelay(500); */ might_sleep(); agnx_hw_init(priv); -// mdelay(500); +/* mdelay(500); */ might_sleep(); priv->init_status = AGNX_START; @@ -280,16 +279,16 @@ static void agnx_stop(struct ieee80211_hw *dev) /* make sure hardware will not generate irq */ agnx_hw_reset(priv); free_irq(priv->pdev->irq, dev); - flush_workqueue(priv->hw->workqueue); -// cancel_delayed_work_sync(&priv->periodic_work); + flush_workqueue(priv->hw->workqueue); +/* cancel_delayed_work_sync(&priv->periodic_work); */ unfill_rings(priv); rings_free(priv); } -static int agnx_config(struct ieee80211_hw *dev, - struct ieee80211_conf *conf) +static int agnx_config(struct ieee80211_hw *dev, u32 changed) { struct agnx_priv *priv = dev->priv; + struct ieee80211_conf *conf = &dev->conf; int channel = ieee80211_frequency_to_channel(conf->channel->center_freq); AGNX_TRACE; @@ -315,7 +314,6 @@ static int agnx_config_interface(struct ieee80211_hw *dev, spin_lock(&priv->lock); if (memcmp(conf->bssid, priv->bssid, ETH_ALEN)) { -// u32 reghi, reglo; agnx_set_bssid(priv, conf->bssid); memcpy(priv->bssid, conf->bssid, ETH_ALEN); hash_write(priv, conf->bssid, BSSID_STAID); @@ -425,7 +423,7 @@ static struct ieee80211_ops agnx_ops = { .remove_interface = agnx_remove_interface, .config = agnx_config, .config_interface = agnx_config_interface, - .configure_filter = agnx_configure_filter, + .configure_filter = agnx_configure_filter, .get_stats = agnx_get_stats, .get_tx_stats = agnx_get_tx_stats, .get_tsf = agnx_get_tsft @@ -434,11 +432,12 @@ static struct ieee80211_ops agnx_ops = { static void __devexit agnx_pci_remove(struct pci_dev *pdev) { struct ieee80211_hw *dev = pci_get_drvdata(pdev); - struct agnx_priv *priv = dev->priv; + struct agnx_priv *priv; AGNX_TRACE; if (!dev) return; + priv = dev->priv; ieee80211_unregister_hw(dev); pci_iounmap(pdev, priv->ctl); pci_iounmap(pdev, priv->data); @@ -504,7 +503,7 @@ static int __devinit agnx_pci_probe(struct pci_dev *pdev, /* Map mem #1 and #2 */ priv->ctl = pci_iomap(pdev, 0, mem_len0); -// printk(KERN_DEBUG PFX"MEM1 mapped address is 0x%p\n", priv->ctl); +/* printk(KERN_DEBUG PFX"MEM1 mapped address is 0x%p\n", priv->ctl); */ if (!priv->ctl) { printk(KERN_ERR PFX "Can't map device memory\n"); goto err_free_dev; diff --git a/drivers/staging/agnx/phy.c b/drivers/staging/agnx/phy.c index da8f10c0838..2be63312b72 100644 --- a/drivers/staging/agnx/phy.c +++ b/drivers/staging/agnx/phy.c @@ -114,7 +114,7 @@ static void mac_address_set(struct agnx_priv *priv) /* FIXME */ reg = (mac_addr[0] << 24) | (mac_addr[1] << 16) | mac_addr[2] << 8 | mac_addr[3]; iowrite32(reg, ctl + AGNX_RXM_MACHI); - reg = (mac_addr[4] << 8) | mac_addr[5]; + reg = (mac_addr[4] << 8) | mac_addr[5]; iowrite32(reg, ctl + AGNX_RXM_MACLO); } @@ -127,7 +127,7 @@ static void receiver_bssid_set(struct agnx_priv *priv, u8 *bssid) /* FIXME */ reg = bssid[0] << 24 | (bssid[1] << 16) | (bssid[2] << 8) | bssid[3]; iowrite32(reg, ctl + AGNX_RXM_BSSIDHI); - reg = (bssid[4] << 8) | bssid[5]; + reg = (bssid[4] << 8) | bssid[5]; iowrite32(reg, ctl + AGNX_RXM_BSSIDLO); /* Enable the receiver */ @@ -401,9 +401,9 @@ static void rx_management_init(struct agnx_priv *priv) agnx_write32(ctl, 0x2074, 0x1f171710); agnx_write32(ctl, 0x2078, 0x10100d0d); agnx_write32(ctl, 0x207c, 0x11111010); - } - else + } else { agnx_write32(ctl, AGNX_RXM_DELAY11, 0x0); + } agnx_write32(ctl, AGNX_RXM_REQRATE, 0x8195e00); } @@ -476,7 +476,7 @@ static void gain_ctlcnt_init(struct agnx_priv *priv) /* It seemed if we set other bit to 1 the bit 0 will be auto change to 0 */ agnx_write32(ctl, AGNX_BM_TXTOPEER, 0x2 | 0x1); -// agnx_write32(ctl, AGNX_BM_TXTOPEER, 0x1); +/* agnx_write32(ctl, AGNX_BM_TXTOPEER, 0x1); */ } /* gain_ctlcnt_init */ @@ -490,7 +490,7 @@ static void phy_init(struct agnx_priv *priv) /* Load InitialGainTable */ gain_table_init(priv); - agnx_write32(ctl, AGNX_CIR_ADDRWIN, 0x2000000); + agnx_write32(ctl, AGNX_CIR_ADDRWIN, 0x2000000); /* Clear the following offsets in Memory Range #2: */ memset_io(data + 0x5040, 0, 0xa * 4); @@ -586,7 +586,7 @@ static void phy_init(struct agnx_priv *priv) agnx_write32(ctl, AGNX_GCR_SIFST11B, 0x28); agnx_write32(ctl, AGNX_GCR_CWDETEC, 0x0); agnx_write32(ctl, AGNX_GCR_0X38, 0x1e); -// agnx_write32(ctl, AGNX_GCR_BOACT, 0x26); +/* agnx_write32(ctl, AGNX_GCR_BOACT, 0x26);*/ agnx_write32(ctl, AGNX_GCR_DISCOVMOD, 0x3); agnx_write32(ctl, AGNX_GCR_THCAP11A, 0x32); @@ -810,10 +810,10 @@ static void card_interface_init(struct agnx_priv *priv) } print_hex_dump_bytes(PFX "EEPROM: ", DUMP_PREFIX_NONE, eeprom, ARRAY_SIZE(eeprom)); - } while(0); + } while (0); spi_rc_write(ctl, RF_CHIP0, 0x26); - reg = agnx_read32(ctl, AGNX_SPI_RLSW); + reg = agnx_read32(ctl, AGNX_SPI_RLSW); /* Initialize the system interface */ system_itf_init(priv); @@ -874,19 +874,19 @@ static void card_interface_init(struct agnx_priv *priv) /* FIXME Enable the request */ /* Check packet length */ /* Set maximum packet length */ -/* agnx_write32(ctl, AGNX_RXM_REQRATE, 0x88195e00); */ -/* enable_receiver(priv); */ +/* agnx_write32(ctl, AGNX_RXM_REQRATE, 0x88195e00); */ +/* enable_receiver(priv); */ /* Set the Receiver BSSID */ receiver_bssid_set(priv, bssid); /* FIXME Set to managed mode */ set_managed_mode(priv); -// set_promiscuous_mode(priv); -/* set_scan_mode(priv); */ -/* set_learn_mode(priv); */ -// set_promis_and_managed(priv); -// set_adhoc_mode(priv); +/* set_promiscuous_mode(priv); */ +/* set_scan_mode(priv); */ +/* set_learn_mode(priv); */ +/* set_promis_and_managed(priv); */ +/* set_adhoc_mode(priv); */ /* Set the recieve request rate */ /* Check packet length */ diff --git a/drivers/staging/agnx/rf.c b/drivers/staging/agnx/rf.c index 8294b6e2eb9..42e457a1844 100644 --- a/drivers/staging/agnx/rf.c +++ b/drivers/staging/agnx/rf.c @@ -109,12 +109,12 @@ void rf_chips_init(struct agnx_priv *priv) } /* Set SPI clock speed to 200NS */ - reg = agnx_read32(ctl, AGNX_SPI_CFG); - reg &= ~0xF; - reg |= 0x3; - agnx_write32(ctl, AGNX_SPI_CFG, reg); + reg = agnx_read32(ctl, AGNX_SPI_CFG); + reg &= ~0xF; + reg |= 0x3; + agnx_write32(ctl, AGNX_SPI_CFG, reg); - /* Set SPI clock speed to 50NS */ + /* Set SPI clock speed to 50NS */ reg = agnx_read32(ctl, AGNX_SPI_CFG); reg &= ~0xF; reg |= 0x1; @@ -256,7 +256,7 @@ static void antenna_init(struct agnx_priv *priv, int num_antenna) agnx_write32(ctl, AGNX_GCR_THD0BTFEST, 70); agnx_write32(ctl, AGNX_GCR_SIGHTH, 100); agnx_write32(ctl, AGNX_GCR_SIGLTH, 48); -// agnx_write32(ctl, AGNX_GCR_SIGLTH, 16); +/* agnx_write32(ctl, AGNX_GCR_SIGLTH, 16); */ break; default: printk(KERN_WARNING PFX "Unknow antenna number\n"); @@ -275,8 +275,8 @@ static void chain_update(struct agnx_priv *priv, u32 chain) if (reg == 0x4) spi_rf_write(ctl, RF_CHIP0|RF_CHIP1, reg|0x1000); else if (reg != 0x0) - spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, reg|0x1000); - else { + spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, reg|0x1000); + else { if (chain == 3 || chain == 6) { spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, reg|0x1000); agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0x0); @@ -634,8 +634,7 @@ static void chain_calibrate(struct agnx_priv *priv, struct chains *chains, } } /* chain_calibrate */ - -static void inline get_calibrete_value(struct agnx_priv *priv, struct chains *chains, +static inline void get_calibrete_value(struct agnx_priv *priv, struct chains *chains, unsigned int num) { void __iomem *ctl = priv->ctl; @@ -652,7 +651,7 @@ static void inline get_calibrete_value(struct agnx_priv *priv, struct chains *ch } if (num == 0 || num == 1 || num == 2) { - if ( 0 == chains[num].cali) + if (0 == chains[num].cali) chains[num].cali = 0xff; else chains[num].cali--; @@ -669,7 +668,7 @@ static inline void calibra_delay(struct agnx_priv *priv) unsigned int i = 100; wmb(); - while (i--) { + while (--i) { reg = (ioread32(ctl + AGNX_ACI_STATUS)); if (reg == 0x4000) break; diff --git a/drivers/staging/agnx/sta.c b/drivers/staging/agnx/sta.c index d3ac675e45b..5b2d54a587c 100644 --- a/drivers/staging/agnx/sta.c +++ b/drivers/staging/agnx/sta.c @@ -18,7 +18,7 @@ void hash_read(struct agnx_priv *priv, u32 reghi, u32 reglo, u8 sta_id) iowrite32(reglo, ctl + AGNX_RXM_HASH_CMD_LOW); reghi = ioread32(ctl + AGNX_RXM_HASH_CMD_HIGH); - reglo = ioread32(ctl + AGNX_RXM_HASH_CMD_LOW); + reglo = ioread32(ctl + AGNX_RXM_HASH_CMD_LOW); printk(PFX "RX hash cmd are : %.8x%.8x\n", reghi, reglo); } @@ -40,7 +40,7 @@ void hash_write(struct agnx_priv *priv, u8 *mac_addr, u8 sta_id) iowrite32(reghi, ctl + AGNX_RXM_HASH_CMD_HIGH); iowrite32(reglo, ctl + AGNX_RXM_HASH_CMD_LOW); - reglo = ioread32(ctl + AGNX_RXM_HASH_CMD_LOW); + reglo = ioread32(ctl + AGNX_RXM_HASH_CMD_LOW); if (!(reglo & 0x80000000)) printk(KERN_WARNING PFX "Update hash table failed\n"); } @@ -59,7 +59,7 @@ void hash_delete(struct agnx_priv *priv, u32 reghi, u32 reglo, u8 sta_id) iowrite32(reglo, ctl + AGNX_RXM_HASH_CMD_LOW); reghi = ioread32(ctl + AGNX_RXM_HASH_CMD_HIGH); - reglo = ioread32(ctl + AGNX_RXM_HASH_CMD_LOW); + reglo = ioread32(ctl + AGNX_RXM_HASH_CMD_LOW); printk(PFX "RX hash cmd are : %.8x%.8x\n", reghi, reglo); } @@ -69,15 +69,14 @@ void hash_dump(struct agnx_priv *priv, u8 sta_id) void __iomem *ctl = priv->ctl; u32 reghi, reglo; - reglo = 0x0; /* dump command */ - reglo|= 0x40000000; /* status bit */ + reglo = 0x40000000; /* status bit */ iowrite32(reglo, ctl + AGNX_RXM_HASH_CMD_LOW); iowrite32(sta_id << 16, ctl + AGNX_RXM_HASH_DUMP_DATA); udelay(80); reghi = ioread32(ctl + AGNX_RXM_HASH_CMD_HIGH); - reglo = ioread32(ctl + AGNX_RXM_HASH_CMD_LOW); + reglo = ioread32(ctl + AGNX_RXM_HASH_CMD_LOW); printk(PFX "hash cmd are : %.8x%.8x\n", reghi, reglo); reghi = ioread32(ctl + AGNX_RXM_HASH_CMD_FLAG); printk(PFX "hash flag is : %.8x\n", reghi); @@ -91,7 +90,7 @@ void hash_dump(struct agnx_priv *priv, u8 sta_id) void get_sta_power(struct agnx_priv *priv, struct agnx_sta_power *power, unsigned int sta_idx) { void __iomem *ctl = priv->ctl; - memcpy_fromio(power, ctl + AGNX_TXM_STAPOWTEMP + sizeof(*power) * sta_idx, + memcpy_fromio(power, ctl + AGNX_TXM_STAPOWTEMP + sizeof(*power) * sta_idx, sizeof(*power)); } @@ -100,7 +99,7 @@ set_sta_power(struct agnx_priv *priv, struct agnx_sta_power *power, unsigned int { void __iomem *ctl = priv->ctl; /* FIXME 2. Write Template to offset + station number */ - memcpy_toio(ctl + AGNX_TXM_STAPOWTEMP + sizeof(*power) * sta_idx, + memcpy_toio(ctl + AGNX_TXM_STAPOWTEMP + sizeof(*power) * sta_idx, power, sizeof(*power)); } @@ -135,7 +134,7 @@ inline void set_sta(struct agnx_priv *priv, struct agnx_sta *sta, unsigned int s { void __iomem *data = priv->data; - memcpy_toio(data + AGNX_PDUPOOL + sizeof(*sta) * sta_idx, + memcpy_toio(data + AGNX_PDUPOOL + sizeof(*sta) * sta_idx, sta, sizeof(*sta)); } @@ -165,7 +164,7 @@ static void sta_tx_workqueue_init(struct agnx_priv *priv, unsigned int sta_idx) reg = agnx_set_bits(WORK_QUEUE_VALID, WORK_QUEUE_VALID_SHIFT, 1); reg |= agnx_set_bits(WORK_QUEUE_ACK_TYPE, WORK_QUEUE_ACK_TYPE_SHIFT, 1); -// reg |= agnx_set_bits(WORK_QUEUE_ACK_TYPE, WORK_QUEUE_ACK_TYPE_SHIFT, 0); +/* reg |= agnx_set_bits(WORK_QUEUE_ACK_TYPE, WORK_QUEUE_ACK_TYPE_SHIFT, 0); */ tx_wq.reg2 |= cpu_to_le32(reg); /* Suppose all 8 traffic class are used */ @@ -181,7 +180,7 @@ static void sta_traffic_init(struct agnx_sta_traffic *traffic) reg = agnx_set_bits(NEW_PACKET, NEW_PACKET_SHIFT, 1); reg |= agnx_set_bits(TRAFFIC_VALID, TRAFFIC_VALID_SHIFT, 1); -// reg |= agnx_set_bits(TRAFFIC_ACK_TYPE, TRAFFIC_ACK_TYPE_SHIFT, 1); +/* reg |= agnx_set_bits(TRAFFIC_ACK_TYPE, TRAFFIC_ACK_TYPE_SHIFT, 1); */ traffic->reg0 = cpu_to_le32(reg); /* 3. setting RX Sequence Number to 4095 */ diff --git a/drivers/staging/agnx/sta.h b/drivers/staging/agnx/sta.h index 58d0b12900d..94e2cf1f973 100644 --- a/drivers/staging/agnx/sta.h +++ b/drivers/staging/agnx/sta.h @@ -16,7 +16,7 @@ struct agnx_hash_cmd { #define PASS 0x00000001 #define PASS_SHIFT 1 __be32 cmdlo; -}__attribute__((__packed__)); +} __attribute__((__packed__)); /* diff --git a/drivers/staging/agnx/table.c b/drivers/staging/agnx/table.c index c60048487b5..b52fef9db0e 100644 --- a/drivers/staging/agnx/table.c +++ b/drivers/staging/agnx/table.c @@ -80,7 +80,7 @@ void routing_table_init(struct agnx_priv *priv) disable_receiver(priv); - for ( type = 0; type < 0x3; type++ ) { + for (type = 0; type < 0x3; type++) { for (subtype = 0; subtype < 0x10; subtype++) { /* 1. Set Routing table to R/W and to Return status on Read */ reg = (type << ROUTAB_TYPE_SHIFT) | @@ -89,7 +89,7 @@ void routing_table_init(struct agnx_priv *priv) if (type == ROUTAB_TYPE_DATA) { /* NULL goes to RFP */ if (subtype == ROUTAB_SUBTYPE_NULL) -// reg |= ROUTAB_ROUTE_RFP; +/* reg |= ROUTAB_ROUTE_RFP; */ reg |= ROUTAB_ROUTE_CPU; /* QOS NULL goes to CPU */ else if (subtype == ROUTAB_SUBTYPE_QOSNULL) @@ -104,7 +104,7 @@ void routing_table_init(struct agnx_priv *priv) (subtype == ROUTAB_SUBTYPE_QOSDATAPOLL) || (subtype == ROUTAB_SUBTYPE_QOSDATAACKPOLL)) reg |= ROUTAB_ROUTE_ENCRY; -// reg |= ROUTAB_ROUTE_CPU; +/* reg |= ROUTAB_ROUTE_CPU; */ /*Drop NULL and QOS NULL ack, poll and poll ack*/ else if ((subtype == ROUTAB_SUBTYPE_NULLACK) || (subtype == ROUTAB_SUBTYPE_QOSNULLACK) || @@ -112,11 +112,11 @@ void routing_table_init(struct agnx_priv *priv) (subtype == ROUTAB_SUBTYPE_QOSNULLPOLL) || (subtype == ROUTAB_SUBTYPE_NULLPOLLACK) || (subtype == ROUTAB_SUBTYPE_QOSNULLPOLLACK)) -// reg |= ROUTAB_ROUTE_DROP; +/* reg |= ROUTAB_ROUTE_DROP; */ reg |= ROUTAB_ROUTE_CPU; - } - else + } else { reg |= (ROUTAB_ROUTE_CPU); + } iowrite32(reg, ctl + AGNX_RXM_ROUTAB); /* Check to verify that the status bit cleared */ routing_table_delay(); diff --git a/drivers/staging/agnx/xmit.c b/drivers/staging/agnx/xmit.c index 7f01528b8a4..0e034081f3a 100644 --- a/drivers/staging/agnx/xmit.c +++ b/drivers/staging/agnx/xmit.c @@ -17,8 +17,8 @@ #include "debug.h" #include "phy.h" -unsigned int rx_frame_cnt = 0; -//unsigned int local_tx_sent_cnt = 0; +unsigned int rx_frame_cnt; +/* unsigned int local_tx_sent_cnt = 0; */ static inline void disable_rx_engine(struct agnx_priv *priv) { @@ -242,15 +242,15 @@ static void get_rx_stats(struct agnx_priv *priv, struct agnx_hdr *hdr, memset(stat, 0, sizeof(*stat)); /* RSSI */ rssi = (u8 *)&hdr->phy_stats_lo; -// stat->ssi = (rssi[0] + rssi[1] + rssi[2]) / 3; +/* stat->ssi = (rssi[0] + rssi[1] + rssi[2]) / 3; */ /* Noise */ noise = ioread32(ctl + AGNX_GCR_NOISE0); noise += ioread32(ctl + AGNX_GCR_NOISE1); noise += ioread32(ctl + AGNX_GCR_NOISE2); stat->noise = noise / 3; /* Signal quality */ - //snr = stat->ssi - stat->noise; - if (snr >=0 && snr < 40) +/* snr = stat->ssi - stat->noise; */ + if (snr >= 0 && snr < 40) stat->signal = 5 * snr / 2; else if (snr >= 40) stat->signal = 100; @@ -269,10 +269,9 @@ static void get_rx_stats(struct agnx_priv *priv, struct agnx_hdr *hdr, stat->band = IEEE80211_BAND_2GHZ; stat->freq = agnx_channels[priv->channel - 1].center_freq; -// stat->antenna = 3; -// stat->mactime = be32_to_cpu(hdr->time_stamp); -// stat->channel = priv->channel; - +/* stat->antenna = 3; + stat->mactime = be32_to_cpu(hdr->time_stamp); + stat->channel = priv->channel; */ } static inline void combine_hdr_frag(struct ieee80211_hdr *ieeehdr, @@ -296,7 +295,7 @@ static inline void combine_hdr_frag(struct ieee80211_hdr *ieeehdr, static inline int agnx_packet_check(struct agnx_priv *priv, struct agnx_hdr *agnxhdr, unsigned packet_len) { - if (agnx_get_bits(CRC_FAIL, CRC_FAIL_SHIFT, be32_to_cpu(agnxhdr->reg1)) == 1){ + if (agnx_get_bits(CRC_FAIL, CRC_FAIL_SHIFT, be32_to_cpu(agnxhdr->reg1)) == 1) { printk(PFX "RX: CRC check fail\n"); goto drop; } @@ -320,7 +319,7 @@ void handle_rx_irq(struct agnx_priv *priv) { struct ieee80211_rx_status status; unsigned int len; -// AGNX_TRACE; +/* AGNX_TRACE; */ do { struct agnx_desc *desc; @@ -341,54 +340,54 @@ void handle_rx_irq(struct agnx_priv *priv) len = (frag & PACKET_LEN) >> PACKET_LEN_SHIFT; if (agnx_packet_check(priv, hdr, len) == -1) { - rx_desc_reusing(priv, i); + rx_desc_reusing(priv, i); continue; } skb_put(skb, len); do { - u16 fctl; + u16 fctl; fctl = le16_to_cpu(((struct ieee80211_hdr *)hdr->mac_hdr)->frame_control); - if ((fctl & IEEE80211_FCTL_STYPE) != IEEE80211_STYPE_BEACON)// && !(fctl & IEEE80211_STYPE_BEACON)) + if ((fctl & IEEE80211_FCTL_STYPE) != IEEE80211_STYPE_BEACON)/* && !(fctl & IEEE80211_STYPE_BEACON)) */ dump_ieee80211_hdr((struct ieee80211_hdr *)hdr->mac_hdr, "RX"); } while (0); if (hdr->_11b0 && !hdr->_11g0) { -/* int j; */ -/* u16 fctl = le16_to_cpu(((struct ieee80211_hdr *)hdr->mac_hdr) */ -/* ->frame_control); */ -/* if ( (fctl & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA) { */ -/* agnx_print_rx_hdr(hdr); */ -// agnx_print_sta(priv, BSSID_STAID); -/* for (j = 0; j < 8; j++) */ -/* agnx_print_sta_tx_wq(priv, BSSID_STAID, j); */ -/* } */ +/* int j; + u16 fctl = le16_to_cpu(((struct ieee80211_hdr *)hdr->mac_hdr) + ->frame_control); + if ( (fctl & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA) { + agnx_print_rx_hdr(hdr); + agnx_print_sta(priv, BSSID_STAID); + for (j = 0; j < 8; j++) + agnx_print_sta_tx_wq(priv, BSSID_STAID, j); + } */ get_rx_stats(priv, hdr, &status); skb_pull(skb, sizeof(*hdr)); combine_hdr_frag((struct ieee80211_hdr *)hdr->mac_hdr, skb); } else if (!hdr->_11b0 && hdr->_11g0) { -// int j; +/* int j; */ agnx_print_rx_hdr(hdr); agnx_print_sta(priv, BSSID_STAID); -// for (j = 0; j < 8; j++) +/* for (j = 0; j < 8; j++) */ agnx_print_sta_tx_wq(priv, BSSID_STAID, 0); print_hex_dump_bytes("agnx: RX_PACKET: ", DUMP_PREFIX_NONE, skb->data, skb->len + 8); -// if (agnx_plcp_get_bitrate_ofdm(&hdr->_11g0) == 0) +/* if (agnx_plcp_get_bitrate_ofdm(&hdr->_11g0) == 0) */ get_rx_stats(priv, hdr, &status); skb_pull(skb, sizeof(*hdr)); combine_hdr_frag((struct ieee80211_hdr *) ((void *)&hdr->mac_hdr), skb); -// dump_ieee80211_hdr((struct ieee80211_hdr *)skb->data, "RX G"); +/* dump_ieee80211_hdr((struct ieee80211_hdr *)skb->data, "RX G"); */ } else agnx_bug("Unknown packets type"); ieee80211_rx_irqsafe(priv->hw, skb, &status); rx_desc_reinit(priv, i); - } while ( priv->rx.idx++ ); + } while (priv->rx.idx++); } /* handle_rx_irq */ static inline void handle_tx_irq(struct agnx_priv *priv, struct agnx_ring *ring) @@ -415,40 +414,40 @@ static inline void handle_tx_irq(struct agnx_priv *priv, struct agnx_ring *ring) pci_unmap_single(priv->pdev, info->mapping, info->dma_len, PCI_DMA_TODEVICE); do { -// int j; +/* int j; */ size_t len; len = info->skb->len - sizeof(struct agnx_hdr) + info->hdr_len; - // if (len == 614) { -// agnx_print_desc(desc); +/* if (len == 614) { */ +/* agnx_print_desc(desc); */ if (info->type == PACKET) { -// agnx_print_tx_hdr((struct agnx_hdr *)info->skb->data); -/* agnx_print_sta_power(priv, LOCAL_STAID); */ -/* agnx_print_sta(priv, LOCAL_STAID); */ -/* // for (j = 0; j < 8; j++) */ -/* agnx_print_sta_tx_wq(priv, LOCAL_STAID, 0); */ -// agnx_print_sta_power(priv, BSSID_STAID); -// agnx_print_sta(priv, BSSID_STAID); -// for (j = 0; j < 8; j++) -// agnx_print_sta_tx_wq(priv, BSSID_STAID, 0); +/* agnx_print_tx_hdr((struct agnx_hdr *)info->skb->data); */ +/* agnx_print_sta_power(priv, LOCAL_STAID); */ +/* agnx_print_sta(priv, LOCAL_STAID); */ +/* for (j = 0; j < 8; j++) */ +/* agnx_print_sta_tx_wq(priv, LOCAL_STAID, 0); */ +/* agnx_print_sta_power(priv, BSSID_STAID); */ +/* agnx_print_sta(priv, BSSID_STAID); */ +/* for (j = 0; j < 8; j++) */ +/* agnx_print_sta_tx_wq(priv, BSSID_STAID, 0); */ } -// } +/* } */ } while (0); if (info->type == PACKET) { -// dump_txm_registers(priv); -// dump_rxm_registers(priv); -// dump_bm_registers(priv); -// dump_cir_registers(priv); +/* dump_txm_registers(priv); + dump_rxm_registers(priv); + dump_bm_registers(priv); + dump_cir_registers(priv); */ } if (info->type == PACKET) { -// struct ieee80211_hdr *hdr; +/* struct ieee80211_hdr *hdr; */ struct ieee80211_tx_info *txi = IEEE80211_SKB_CB(info->skb); skb_pull(info->skb, sizeof(struct agnx_hdr)); memcpy(skb_push(info->skb, info->hdr_len), &info->hdr, info->hdr_len); -// dump_ieee80211_hdr((struct ieee80211_hdr *)info->skb->data, "TX_HANDLE"); +/* dump_ieee80211_hdr((struct ieee80211_hdr *)info->skb->data, "TX_HANDLE"); */ /* print_hex_dump_bytes("agnx: TX_HANDLE: ", DUMP_PREFIX_NONE, */ /* info->skb->data, info->skb->len); */ @@ -462,7 +461,7 @@ static inline void handle_tx_irq(struct agnx_priv *priv, struct agnx_ring *ring) /* ieee80211_tx_status_irqsafe(priv->hw, info->skb, &(info->tx_status)); */ /* } else */ /* dev_kfree_skb_irq(info->skb); */ - } + } memset(desc, 0, sizeof(*desc)); memset(info, 0, sizeof(*info)); } @@ -485,7 +484,7 @@ void handle_txd_irq(struct agnx_priv *priv) void handle_other_irq(struct agnx_priv *priv) { -// void __iomem *ctl = priv->ctl; +/* void __iomem *ctl = priv->ctl; */ u32 status = priv->irq_status; void __iomem *ctl = priv->ctl; u32 reg; @@ -526,11 +525,11 @@ void handle_other_irq(struct agnx_priv *priv) iowrite32(reg, ctl + AGNX_INT_MASK); iowrite32(IRQ_RX_FRAME, ctl + AGNX_INT_STAT); printk(PFX "IRQ: RX Frame\n"); - rx_frame_cnt++; + rx_frame_cnt++; } if (status & IRQ_ERR_INT) { iowrite32(IRQ_ERR_INT, ctl + AGNX_INT_STAT); -// agnx_hw_reset(priv); +/* agnx_hw_reset(priv); */ printk(PFX "IRQ: Error Interrupt\n"); } if (status & IRQ_TX_QUE_FULL) @@ -558,14 +557,14 @@ void handle_other_irq(struct agnx_priv *priv) static inline void route_flag_set(struct agnx_hdr *txhdr) { -// u32 reg = 0; +/* u32 reg = 0; */ /* FIXME */ -/* reg = (0x7 << ROUTE_COMPRESSION_SHIFT) & ROUTE_COMPRESSION; */ -/* txhdr->reg5 = cpu_to_be32(reg); */ - txhdr->reg5 = (0xa << 0x0) | (0x7 << 0x18); -// txhdr->reg5 = cpu_to_be32((0xa << 0x0) | (0x7 << 0x18)); -// txhdr->reg5 = cpu_to_be32(0x7 << 0x0); +/* reg = (0x7 << ROUTE_COMPRESSION_SHIFT) & ROUTE_COMPRESSION; */ +/* txhdr->reg5 = cpu_to_be32(reg); */ + txhdr->reg5 = (0xa << 0x0) | (0x7 << 0x18); +/* txhdr->reg5 = cpu_to_be32((0xa << 0x0) | (0x7 << 0x18)); */ +/* txhdr->reg5 = cpu_to_be32(0x7 << 0x0); */ } /* Return 0 if no match */ @@ -579,12 +578,29 @@ static inline unsigned int get_power_level(unsigned int rate, unsigned int anten case 55: case 60: case 90: - case 120: power_level = 22; break; - case 180: power_level = 19; break; - case 240: power_level = 18; break; - case 360: power_level = 16; break; - case 480: power_level = 15; break; - case 540: power_level = 14; break; + case 120: + power_level = 22; + break; + + case 180: + power_level = 19; + break; + + case 240: + power_level = 18; + break; + + case 360: + power_level = 16; + break; + + case 480: + power_level = 15; + break; + + case 540: + power_level = 14; + break; default: agnx_bug("Error rate setting\n"); } @@ -604,30 +620,30 @@ static inline void fill_agnx_hdr(struct agnx_priv *priv, struct agnx_info *tx_in memset(txhdr, 0, sizeof(*txhdr)); -// reg = agnx_set_bits(STATION_ID, STATION_ID_SHIFT, LOCAL_STAID); +/* reg = agnx_set_bits(STATION_ID, STATION_ID_SHIFT, LOCAL_STAID); */ reg = agnx_set_bits(STATION_ID, STATION_ID_SHIFT, BSSID_STAID); reg |= agnx_set_bits(WORKQUEUE_ID, WORKQUEUE_ID_SHIFT, 0); txhdr->reg4 = cpu_to_be32(reg); /* Set the Hardware Sequence Number to 1? */ reg = agnx_set_bits(SEQUENCE_NUMBER, SEQUENCE_NUMBER_SHIFT, 0); -// reg = agnx_set_bits(SEQUENCE_NUMBER, SEQUENCE_NUMBER_SHIFT, 1); +/* reg = agnx_set_bits(SEQUENCE_NUMBER, SEQUENCE_NUMBER_SHIFT, 1); */ reg |= agnx_set_bits(MAC_HDR_LEN, MAC_HDR_LEN_SHIFT, tx_info->hdr_len); txhdr->reg1 = cpu_to_be32(reg); /* Set the agnx_hdr's MAC header */ memcpy(txhdr->mac_hdr, &tx_info->hdr, tx_info->hdr_len); reg = agnx_set_bits(ACK, ACK_SHIFT, 1); -// reg = agnx_set_bits(ACK, ACK_SHIFT, 0); +/* reg = agnx_set_bits(ACK, ACK_SHIFT, 0); */ reg |= agnx_set_bits(MULTICAST, MULTICAST_SHIFT, 0); -// reg |= agnx_set_bits(MULTICAST, MULTICAST_SHIFT, 1); +/* reg |= agnx_set_bits(MULTICAST, MULTICAST_SHIFT, 1); */ reg |= agnx_set_bits(RELAY, RELAY_SHIFT, 0); reg |= agnx_set_bits(TM, TM_SHIFT, 0); txhdr->reg0 = cpu_to_be32(reg); /* Set the long and short retry limits */ - txhdr->tx.short_retry_limit = tx_info->txi->control.rates[0].count; - txhdr->tx.long_retry_limit = tx_info->txi->control.rates[0].count; + txhdr->tx.short_retry_limit = tx_info->txi->control.rates[0].count; + txhdr->tx.long_retry_limit = tx_info->txi->control.rates[0].count; /* FIXME */ len = tx_info->skb->len - sizeof(*txhdr) + tx_info->hdr_len + FCS_LEN; @@ -652,23 +668,23 @@ static void txm_power_set(struct agnx_priv *priv, if (txi->control.rates[0].idx < 0) { /* For B mode Short Preamble */ reg = agnx_set_bits(PHY_MODE, PHY_MODE_SHIFT, AGNX_MODE_80211B_SHORT); -// control->tx_rate = -control->tx_rate; +/* control->tx_rate = -control->tx_rate; */ } else reg = agnx_set_bits(PHY_MODE, PHY_MODE_SHIFT, AGNX_MODE_80211G); -// reg = agnx_set_bits(PHY_MODE, PHY_MODE_SHIFT, AGNX_MODE_80211B_LONG); +/* reg = agnx_set_bits(PHY_MODE, PHY_MODE_SHIFT, AGNX_MODE_80211B_LONG); */ reg |= agnx_set_bits(SIGNAL, SIGNAL_SHIFT, 0xB); reg |= agnx_set_bits(RATE, RATE_SHIFT, 0xB); -// reg |= agnx_set_bits(POWER_LEVEL, POWER_LEVEL_SHIFT, 15); +/* reg |= agnx_set_bits(POWER_LEVEL, POWER_LEVEL_SHIFT, 15); */ reg |= agnx_set_bits(POWER_LEVEL, POWER_LEVEL_SHIFT, 20); /* if rate < 11M set it to 0 */ reg |= agnx_set_bits(NUM_TRANSMITTERS, NUM_TRANSMITTERS_SHIFT, 1); -// reg |= agnx_set_bits(EDCF, EDCF_SHIFT, 1); -// reg |= agnx_set_bits(TIFS, TIFS_SHIFT, 1); +/* reg |= agnx_set_bits(EDCF, EDCF_SHIFT, 1); */ +/* reg |= agnx_set_bits(TIFS, TIFS_SHIFT, 1); */ power.reg = reg; -// power.reg = cpu_to_le32(reg); +/* power.reg = cpu_to_le32(reg); */ -// set_sta_power(priv, &power, LOCAL_STAID); +/* set_sta_power(priv, &power, LOCAL_STAID); */ set_sta_power(priv, &power, BSSID_STAID); } @@ -759,24 +775,24 @@ static int __agnx_tx(struct agnx_priv *priv, struct sk_buff *skb, txm_power_set(priv, txi); -/* do { */ -/* int j; */ -/* size_t len; */ -/* len = skb->len - hdr_info->dma_len + hdr_info->hdr_len; */ -/* // if (len == 614) { */ -/* agnx_print_desc(hdr_desc); */ -/* agnx_print_desc(frag_desc); */ -/* agnx_print_tx_hdr((struct agnx_hdr *)skb->data); */ -/* agnx_print_sta_power(priv, LOCAL_STAID); */ -/* agnx_print_sta(priv, LOCAL_STAID); */ -/* for (j = 0; j < 8; j++) */ -/* agnx_print_sta_tx_wq(priv, LOCAL_STAID, j); */ -/* agnx_print_sta_power(priv, BSSID_STAID); */ -/* agnx_print_sta(priv, BSSID_STAID); */ -/* for (j = 0; j < 8; j++) */ -/* agnx_print_sta_tx_wq(priv, BSSID_STAID, j); */ -/* // } */ -/* } while (0); */ +/* do { */ +/* int j; */ +/* size_t len; */ +/* len = skb->len - hdr_info->dma_len + hdr_info->hdr_len; */ +/* if (len == 614) { */ +/* agnx_print_desc(hdr_desc); */ +/* agnx_print_desc(frag_desc); */ +/* agnx_print_tx_hdr((struct agnx_hdr *)skb->data); */ +/* agnx_print_sta_power(priv, LOCAL_STAID); */ +/* agnx_print_sta(priv, LOCAL_STAID); */ +/* for (j = 0; j < 8; j++) */ +/* agnx_print_sta_tx_wq(priv, LOCAL_STAID, j); */ +/* agnx_print_sta_power(priv, BSSID_STAID); */ +/* agnx_print_sta(priv, BSSID_STAID); */ +/* for (j = 0; j < 8; j++) */ +/* agnx_print_sta_tx_wq(priv, BSSID_STAID, j); */ +/* } */ +/* } while (0); */ spin_unlock_irqrestore(&priv->lock, flags); @@ -787,7 +803,7 @@ static int __agnx_tx(struct agnx_priv *priv, struct sk_buff *skb, reg = (ioread32(priv->ctl + AGNX_CIR_TXMCTL)); reg |= 0x8; iowrite32((reg), priv->ctl + AGNX_CIR_TXMCTL); - }while (0); + } while (0); /* Trigger TXD */ do { @@ -795,7 +811,7 @@ static int __agnx_tx(struct agnx_priv *priv, struct sk_buff *skb, reg = (ioread32(priv->ctl + AGNX_CIR_TXDCTL)); reg |= 0x8; iowrite32((reg), priv->ctl + AGNX_CIR_TXDCTL); - }while (0); + } while (0); return 0; } @@ -807,12 +823,12 @@ int _agnx_tx(struct agnx_priv *priv, struct sk_buff *skb) if (tx_packet_check(skb)) return 0; -/* print_hex_dump_bytes("agnx: TX_PACKET: ", DUMP_PREFIX_NONE, */ -/* skb->data, skb->len); */ +/* print_hex_dump_bytes("agnx: TX_PACKET: ", DUMP_PREFIX_NONE, */ +/* skb->data, skb->len); */ - fctl = le16_to_cpu(*((__le16 *)skb->data)); + fctl = le16_to_cpu(*((__le16 *)skb->data)); - if ( (fctl & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA ) + if ((fctl & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA) return __agnx_tx(priv, skb, &priv->txd); else return __agnx_tx(priv, skb, &priv->txm); |