diff options
Diffstat (limited to 'drivers/staging/epl/Edrv8139.c')
| -rw-r--r-- | drivers/staging/epl/Edrv8139.c | 1395 |
1 files changed, 665 insertions, 730 deletions
diff --git a/drivers/staging/epl/Edrv8139.c b/drivers/staging/epl/Edrv8139.c index 3fa0564d229..88ab4a4f102 100644 --- a/drivers/staging/epl/Edrv8139.c +++ b/drivers/staging/epl/Edrv8139.c @@ -89,7 +89,6 @@ #include <linux/sched.h> #include <linux/delay.h> - /***************************************************************************/ /* */ /* */ @@ -108,7 +107,6 @@ // NMT requests / commands. The less the size of the buffer the less the // number of the buffer. - //--------------------------------------------------------------------------- // const defines //--------------------------------------------------------------------------- @@ -119,26 +117,25 @@ #define EDRV_MAX_FRAME_SIZE 0x600 -#define EDRV_RX_BUFFER_SIZE 0x8610 // 32 kB + 16 Byte + 1,5 kB (WRAP is enabled) -#define EDRV_RX_BUFFER_LENGTH (EDRV_RX_BUFFER_SIZE & 0xF800) // buffer size cut down to 2 kB alignment +#define EDRV_RX_BUFFER_SIZE 0x8610 // 32 kB + 16 Byte + 1,5 kB (WRAP is enabled) +#define EDRV_RX_BUFFER_LENGTH (EDRV_RX_BUFFER_SIZE & 0xF800) // buffer size cut down to 2 kB alignment -#define EDRV_TX_BUFFER_SIZE (EDRV_MAX_TX_BUFFERS * EDRV_MAX_FRAME_SIZE) // n * (MTU + 14 + 4) +#define EDRV_TX_BUFFER_SIZE (EDRV_MAX_TX_BUFFERS * EDRV_MAX_FRAME_SIZE) // n * (MTU + 14 + 4) #define DRV_NAME "epl" - -#define EDRV_REGW_INT_MASK 0x3C // interrupt mask register -#define EDRV_REGW_INT_STATUS 0x3E // interrupt status register -#define EDRV_REGW_INT_ROK 0x0001 // Receive OK interrupt -#define EDRV_REGW_INT_RER 0x0002 // Receive error interrupt -#define EDRV_REGW_INT_TOK 0x0004 // Transmit OK interrupt -#define EDRV_REGW_INT_TER 0x0008 // Transmit error interrupt -#define EDRV_REGW_INT_RXOVW 0x0010 // Rx buffer overflow interrupt -#define EDRV_REGW_INT_PUN 0x0020 // Packet underrun/ link change interrupt -#define EDRV_REGW_INT_FOVW 0x0040 // Rx FIFO overflow interrupt -#define EDRV_REGW_INT_LENCHG 0x2000 // Cable length change interrupt -#define EDRV_REGW_INT_TIMEOUT 0x4000 // Time out interrupt -#define EDRV_REGW_INT_SERR 0x8000 // System error interrupt +#define EDRV_REGW_INT_MASK 0x3C // interrupt mask register +#define EDRV_REGW_INT_STATUS 0x3E // interrupt status register +#define EDRV_REGW_INT_ROK 0x0001 // Receive OK interrupt +#define EDRV_REGW_INT_RER 0x0002 // Receive error interrupt +#define EDRV_REGW_INT_TOK 0x0004 // Transmit OK interrupt +#define EDRV_REGW_INT_TER 0x0008 // Transmit error interrupt +#define EDRV_REGW_INT_RXOVW 0x0010 // Rx buffer overflow interrupt +#define EDRV_REGW_INT_PUN 0x0020 // Packet underrun/ link change interrupt +#define EDRV_REGW_INT_FOVW 0x0040 // Rx FIFO overflow interrupt +#define EDRV_REGW_INT_LENCHG 0x2000 // Cable length change interrupt +#define EDRV_REGW_INT_TIMEOUT 0x4000 // Time out interrupt +#define EDRV_REGW_INT_SERR 0x8000 // System error interrupt #define EDRV_REGW_INT_MASK_DEF (EDRV_REGW_INT_ROK \ | EDRV_REGW_INT_RER \ | EDRV_REGW_INT_TOK \ @@ -147,88 +144,86 @@ | EDRV_REGW_INT_FOVW \ | EDRV_REGW_INT_PUN \ | EDRV_REGW_INT_TIMEOUT \ - | EDRV_REGW_INT_SERR) // default interrupt mask + | EDRV_REGW_INT_SERR) // default interrupt mask -#define EDRV_REGB_COMMAND 0x37 // command register +#define EDRV_REGB_COMMAND 0x37 // command register #define EDRV_REGB_COMMAND_RST 0x10 #define EDRV_REGB_COMMAND_RE 0x08 #define EDRV_REGB_COMMAND_TE 0x04 #define EDRV_REGB_COMMAND_BUFE 0x01 -#define EDRV_REGB_CMD9346 0x50 // 93C46 command register -#define EDRV_REGB_CMD9346_LOCK 0x00 // lock configuration registers -#define EDRV_REGB_CMD9346_UNLOCK 0xC0 // unlock configuration registers - -#define EDRV_REGDW_RCR 0x44 // Rx configuration register -#define EDRV_REGDW_RCR_NO_FTH 0x0000E000 // no receive FIFO threshold -#define EDRV_REGDW_RCR_RBLEN32K 0x00001000 // 32 kB receive buffer -#define EDRV_REGDW_RCR_MXDMAUNL 0x00000700 // unlimited maximum DMA burst size -#define EDRV_REGDW_RCR_NOWRAP 0x00000080 // do not wrap frame at end of buffer -#define EDRV_REGDW_RCR_AER 0x00000020 // accept error frames (CRC, alignment, collided) -#define EDRV_REGDW_RCR_AR 0x00000010 // accept runt -#define EDRV_REGDW_RCR_AB 0x00000008 // accept broadcast frames -#define EDRV_REGDW_RCR_AM 0x00000004 // accept multicast frames -#define EDRV_REGDW_RCR_APM 0x00000002 // accept physical match frames -#define EDRV_REGDW_RCR_AAP 0x00000001 // accept all frames +#define EDRV_REGB_CMD9346 0x50 // 93C46 command register +#define EDRV_REGB_CMD9346_LOCK 0x00 // lock configuration registers +#define EDRV_REGB_CMD9346_UNLOCK 0xC0 // unlock configuration registers + +#define EDRV_REGDW_RCR 0x44 // Rx configuration register +#define EDRV_REGDW_RCR_NO_FTH 0x0000E000 // no receive FIFO threshold +#define EDRV_REGDW_RCR_RBLEN32K 0x00001000 // 32 kB receive buffer +#define EDRV_REGDW_RCR_MXDMAUNL 0x00000700 // unlimited maximum DMA burst size +#define EDRV_REGDW_RCR_NOWRAP 0x00000080 // do not wrap frame at end of buffer +#define EDRV_REGDW_RCR_AER 0x00000020 // accept error frames (CRC, alignment, collided) +#define EDRV_REGDW_RCR_AR 0x00000010 // accept runt +#define EDRV_REGDW_RCR_AB 0x00000008 // accept broadcast frames +#define EDRV_REGDW_RCR_AM 0x00000004 // accept multicast frames +#define EDRV_REGDW_RCR_APM 0x00000002 // accept physical match frames +#define EDRV_REGDW_RCR_AAP 0x00000001 // accept all frames #define EDRV_REGDW_RCR_DEF (EDRV_REGDW_RCR_NO_FTH \ | EDRV_REGDW_RCR_RBLEN32K \ | EDRV_REGDW_RCR_MXDMAUNL \ | EDRV_REGDW_RCR_NOWRAP \ | EDRV_REGDW_RCR_AB \ | EDRV_REGDW_RCR_AM \ - | EDRV_REGDW_RCR_APM) // default value - -#define EDRV_REGDW_TCR 0x40 // Tx configuration register -#define EDRV_REGDW_TCR_VER_MASK 0x7CC00000 // mask for hardware version -#define EDRV_REGDW_TCR_VER_C 0x74000000 // RTL8139C -#define EDRV_REGDW_TCR_VER_D 0x74400000 // RTL8139D -#define EDRV_REGDW_TCR_IFG96 0x03000000 // default interframe gap (960 ns) -#define EDRV_REGDW_TCR_CRC 0x00010000 // disable appending of CRC by the controller -#define EDRV_REGDW_TCR_MXDMAUNL 0x00000700 // maximum DMA burst size of 2048 b -#define EDRV_REGDW_TCR_TXRETRY 0x00000000 // 16 retries + | EDRV_REGDW_RCR_APM) // default value + +#define EDRV_REGDW_TCR 0x40 // Tx configuration register +#define EDRV_REGDW_TCR_VER_MASK 0x7CC00000 // mask for hardware version +#define EDRV_REGDW_TCR_VER_C 0x74000000 // RTL8139C +#define EDRV_REGDW_TCR_VER_D 0x74400000 // RTL8139D +#define EDRV_REGDW_TCR_IFG96 0x03000000 // default interframe gap (960 ns) +#define EDRV_REGDW_TCR_CRC 0x00010000 // disable appending of CRC by the controller +#define EDRV_REGDW_TCR_MXDMAUNL 0x00000700 // maximum DMA burst size of 2048 b +#define EDRV_REGDW_TCR_TXRETRY 0x00000000 // 16 retries #define EDRV_REGDW_TCR_DEF (EDRV_REGDW_TCR_IFG96 \ | EDRV_REGDW_TCR_MXDMAUNL \ | EDRV_REGDW_TCR_TXRETRY) -#define EDRV_REGW_MULINT 0x5C // multiple interrupt select register - -#define EDRV_REGDW_MPC 0x4C // missed packet counter register +#define EDRV_REGW_MULINT 0x5C // multiple interrupt select register -#define EDRV_REGDW_TSAD0 0x20 // Transmit start address of descriptor 0 -#define EDRV_REGDW_TSAD1 0x24 // Transmit start address of descriptor 1 -#define EDRV_REGDW_TSAD2 0x28 // Transmit start address of descriptor 2 -#define EDRV_REGDW_TSAD3 0x2C // Transmit start address of descriptor 3 -#define EDRV_REGDW_TSD0 0x10 // Transmit status of descriptor 0 -#define EDRV_REGDW_TSD_CRS 0x80000000 // Carrier sense lost -#define EDRV_REGDW_TSD_TABT 0x40000000 // Transmit Abort -#define EDRV_REGDW_TSD_OWC 0x20000000 // Out of window collision -#define EDRV_REGDW_TSD_TXTH_DEF 0x00020000 // Transmit FIFO threshold of 64 bytes -#define EDRV_REGDW_TSD_TOK 0x00008000 // Transmit OK -#define EDRV_REGDW_TSD_TUN 0x00004000 // Transmit FIFO underrun -#define EDRV_REGDW_TSD_OWN 0x00002000 // Owner +#define EDRV_REGDW_MPC 0x4C // missed packet counter register -#define EDRV_REGDW_RBSTART 0x30 // Receive buffer start address +#define EDRV_REGDW_TSAD0 0x20 // Transmit start address of descriptor 0 +#define EDRV_REGDW_TSAD1 0x24 // Transmit start address of descriptor 1 +#define EDRV_REGDW_TSAD2 0x28 // Transmit start address of descriptor 2 +#define EDRV_REGDW_TSAD3 0x2C // Transmit start address of descriptor 3 +#define EDRV_REGDW_TSD0 0x10 // Transmit status of descriptor 0 +#define EDRV_REGDW_TSD_CRS 0x80000000 // Carrier sense lost +#define EDRV_REGDW_TSD_TABT 0x40000000 // Transmit Abort +#define EDRV_REGDW_TSD_OWC 0x20000000 // Out of window collision +#define EDRV_REGDW_TSD_TXTH_DEF 0x00020000 // Transmit FIFO threshold of 64 bytes +#define EDRV_REGDW_TSD_TOK 0x00008000 // Transmit OK +#define EDRV_REGDW_TSD_TUN 0x00004000 // Transmit FIFO underrun +#define EDRV_REGDW_TSD_OWN 0x00002000 // Owner -#define EDRV_REGW_CAPR 0x38 // Current address of packet read +#define EDRV_REGDW_RBSTART 0x30 // Receive buffer start address -#define EDRV_REGDW_IDR0 0x00 // ID register 0 -#define EDRV_REGDW_IDR4 0x04 // ID register 4 +#define EDRV_REGW_CAPR 0x38 // Current address of packet read -#define EDRV_REGDW_MAR0 0x08 // Multicast address register 0 -#define EDRV_REGDW_MAR4 0x0C // Multicast address register 4 +#define EDRV_REGDW_IDR0 0x00 // ID register 0 +#define EDRV_REGDW_IDR4 0x04 // ID register 4 +#define EDRV_REGDW_MAR0 0x08 // Multicast address register 0 +#define EDRV_REGDW_MAR4 0x0C // Multicast address register 4 // defines for the status word in the receive buffer -#define EDRV_RXSTAT_MAR 0x8000 // Multicast address received -#define EDRV_RXSTAT_PAM 0x4000 // Physical address matched -#define EDRV_RXSTAT_BAR 0x2000 // Broadcast address received -#define EDRV_RXSTAT_ISE 0x0020 // Invalid symbol error -#define EDRV_RXSTAT_RUNT 0x0010 // Runt packet received -#define EDRV_RXSTAT_LONG 0x0008 // Long packet -#define EDRV_RXSTAT_CRC 0x0004 // CRC error -#define EDRV_RXSTAT_FAE 0x0002 // Frame alignment error -#define EDRV_RXSTAT_ROK 0x0001 // Receive OK - +#define EDRV_RXSTAT_MAR 0x8000 // Multicast address received +#define EDRV_RXSTAT_PAM 0x4000 // Physical address matched +#define EDRV_RXSTAT_BAR 0x2000 // Broadcast address received +#define EDRV_RXSTAT_ISE 0x0020 // Invalid symbol error +#define EDRV_RXSTAT_RUNT 0x0010 // Runt packet received +#define EDRV_RXSTAT_LONG 0x0008 // Long packet +#define EDRV_RXSTAT_CRC 0x0004 // CRC error +#define EDRV_RXSTAT_FAE 0x0002 // Frame alignment error +#define EDRV_RXSTAT_ROK 0x0001 // Receive OK #define EDRV_REGDW_WRITE(dwReg, dwVal) writel(dwVal, EdrvInstance_l.m_pIoAddr + dwReg) #define EDRV_REGW_WRITE(dwReg, wVal) writew(wVal, EdrvInstance_l.m_pIoAddr + dwReg) @@ -237,16 +232,15 @@ #define EDRV_REGW_READ(dwReg) readw(EdrvInstance_l.m_pIoAddr + dwReg) #define EDRV_REGB_READ(dwReg) readb(EdrvInstance_l.m_pIoAddr + dwReg) - // TracePoint support for realtime-debugging #ifdef _DBG_TRACE_POINTS_ - void PUBLIC TgtDbgSignalTracePoint (BYTE bTracePointNumber_p); - void PUBLIC TgtDbgPostTraceValue (DWORD dwTraceValue_p); - #define TGT_DBG_SIGNAL_TRACE_POINT(p) TgtDbgSignalTracePoint(p) - #define TGT_DBG_POST_TRACE_VALUE(v) TgtDbgPostTraceValue(v) +void PUBLIC TgtDbgSignalTracePoint(BYTE bTracePointNumber_p); +void PUBLIC TgtDbgPostTraceValue(DWORD dwTraceValue_p); +#define TGT_DBG_SIGNAL_TRACE_POINT(p) TgtDbgSignalTracePoint(p) +#define TGT_DBG_POST_TRACE_VALUE(v) TgtDbgPostTraceValue(v) #else - #define TGT_DBG_SIGNAL_TRACE_POINT(p) - #define TGT_DBG_POST_TRACE_VALUE(v) +#define TGT_DBG_SIGNAL_TRACE_POINT(p) +#define TGT_DBG_POST_TRACE_VALUE(v) #endif #define EDRV_COUNT_SEND TGT_DBG_SIGNAL_TRACE_POINT(2) @@ -271,7 +265,6 @@ #define EDRV_TRACE_RX_PUN(x) TGT_DBG_POST_TRACE_VALUE(((x) & 0xFFFF) | 0x11000000) #define EDRV_TRACE(x) TGT_DBG_POST_TRACE_VALUE(((x) & 0xFFFF0000) | 0x0000FEC0) - //--------------------------------------------------------------------------- // local types //--------------------------------------------------------------------------- @@ -286,59 +279,51 @@ typedef struct */ // Private structure -typedef struct -{ - struct pci_dev* m_pPciDev; // pointer to PCI device structure - void* m_pIoAddr; // pointer to register space of Ethernet controller - BYTE* m_pbRxBuf; // pointer to Rx buffer - dma_addr_t m_pRxBufDma; - BYTE* m_pbTxBuf; // pointer to Tx buffer - dma_addr_t m_pTxBufDma; - BOOL m_afTxBufUsed[EDRV_MAX_TX_BUFFERS]; - unsigned int m_uiCurTxDesc; - - tEdrvInitParam m_InitParam; - tEdrvTxBuffer* m_pLastTransmittedTxBuffer; +typedef struct { + struct pci_dev *m_pPciDev; // pointer to PCI device structure + void *m_pIoAddr; // pointer to register space of Ethernet controller + BYTE *m_pbRxBuf; // pointer to Rx buffer + dma_addr_t m_pRxBufDma; + BYTE *m_pbTxBuf; // pointer to Tx buffer + dma_addr_t m_pTxBufDma; + BOOL m_afTxBufUsed[EDRV_MAX_TX_BUFFERS]; + unsigned int m_uiCurTxDesc; + + tEdrvInitParam m_InitParam; + tEdrvTxBuffer *m_pLastTransmittedTxBuffer; } tEdrvInstance; - - //--------------------------------------------------------------------------- // local function prototypes //--------------------------------------------------------------------------- static int EdrvInitOne(struct pci_dev *pPciDev, - const struct pci_device_id *pId); + const struct pci_device_id *pId); static void EdrvRemoveOne(struct pci_dev *pPciDev); - //--------------------------------------------------------------------------- // modul globale vars //--------------------------------------------------------------------------- // buffers and buffer descriptors and pointers static struct pci_device_id aEdrvPciTbl[] = { - {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, - {0,} + {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, + {0,} }; -MODULE_DEVICE_TABLE (pci, aEdrvPciTbl); +MODULE_DEVICE_TABLE(pci, aEdrvPciTbl); static tEdrvInstance EdrvInstance_l; - static struct pci_driver EdrvDriver = { - .name = DRV_NAME, - .id_table = aEdrvPciTbl, - .probe = EdrvInitOne, - .remove = EdrvRemoveOne, + .name = DRV_NAME, + .id_table = aEdrvPciTbl, + .probe = EdrvInitOne, + .remove = EdrvRemoveOne, }; - - - /***************************************************************************/ /* */ /* */ @@ -352,7 +337,6 @@ static struct pci_driver EdrvDriver = { // /***************************************************************************/ - //=========================================================================// // // // P R I V A T E D E F I N I T I O N S // @@ -375,9 +359,7 @@ static struct pci_driver EdrvDriver = { // local function prototypes //--------------------------------------------------------------------------- -static BYTE EdrvCalcHash (BYTE * pbMAC_p); - - +static BYTE EdrvCalcHash(BYTE * pbMAC_p); //--------------------------------------------------------------------------- // @@ -395,49 +377,46 @@ static BYTE EdrvCalcHash (BYTE * pbMAC_p); //--------------------------------------------------------------------------- tEplKernel EdrvInit(tEdrvInitParam * pEdrvInitParam_p) { -tEplKernel Ret; -int iResult; - - Ret = kEplSuccessful; - - // clear instance structure - EPL_MEMSET(&EdrvInstance_l, 0, sizeof (EdrvInstance_l)); - - // save the init data - EdrvInstance_l.m_InitParam = *pEdrvInitParam_p; - - - // register PCI driver - iResult = pci_register_driver (&EdrvDriver); - if (iResult != 0) - { - printk("%s pci_register_driver failed with %d\n", __FUNCTION__, iResult); - Ret = kEplNoResource; - goto Exit; - } - - if (EdrvInstance_l.m_pPciDev == NULL) - { - printk("%s m_pPciDev=NULL\n", __FUNCTION__); - Ret = kEplNoResource; - goto Exit; - } - - // read MAC address from controller - printk("%s local MAC = ", __FUNCTION__); - for (iResult = 0; iResult < 6; iResult++) - { - pEdrvInitParam_p->m_abMyMacAddr[iResult] = EDRV_REGB_READ((EDRV_REGDW_IDR0 + iResult)); - printk("%02X ", (unsigned int)pEdrvInitParam_p->m_abMyMacAddr[iResult]); - } - printk("\n"); - -Exit: - return Ret; + tEplKernel Ret; + int iResult; + + Ret = kEplSuccessful; + + // clear instance structure + EPL_MEMSET(&EdrvInstance_l, 0, sizeof(EdrvInstance_l)); + + // save the init data + EdrvInstance_l.m_InitParam = *pEdrvInitParam_p; + + // register PCI driver + iResult = pci_register_driver(&EdrvDriver); + if (iResult != 0) { + printk("%s pci_register_driver failed with %d\n", __FUNCTION__, + iResult); + Ret = kEplNoResource; + goto Exit; + } + + if (EdrvInstance_l.m_pPciDev == NULL) { + printk("%s m_pPciDev=NULL\n", __FUNCTION__); + Ret = kEplNoResource; + goto Exit; + } + // read MAC address from controller + printk("%s local MAC = ", __FUNCTION__); + for (iResult = 0; iResult < 6; iResult++) { + pEdrvInitParam_p->m_abMyMacAddr[iResult] = + EDRV_REGB_READ((EDRV_REGDW_IDR0 + iResult)); + printk("%02X ", + (unsigned int)pEdrvInitParam_p->m_abMyMacAddr[iResult]); + } + printk("\n"); + + Exit: + return Ret; } - //--------------------------------------------------------------------------- // // Function: EdrvShutdown @@ -454,14 +433,13 @@ Exit: tEplKernel EdrvShutdown(void) { - // unregister PCI driver - printk("%s calling pci_unregister_driver()\n", __FUNCTION__); - pci_unregister_driver (&EdrvDriver); + // unregister PCI driver + printk("%s calling pci_unregister_driver()\n", __FUNCTION__); + pci_unregister_driver(&EdrvDriver); - return kEplSuccessful; + return kEplSuccessful; } - //--------------------------------------------------------------------------- // // Function: EdrvDefineRxMacAddrEntry @@ -475,13 +453,13 @@ tEplKernel EdrvShutdown(void) // State: // //--------------------------------------------------------------------------- -tEplKernel EdrvDefineRxMacAddrEntry (BYTE * pbMacAddr_p) +tEplKernel EdrvDefineRxMacAddrEntry(BYTE * pbMacAddr_p) { -tEplKernel Ret = kEplSuccessful; -DWORD dwData; -BYTE bHash; + tEplKernel Ret = kEplSuccessful; + DWORD dwData; + BYTE bHash; - bHash = EdrvCalcHash (pbMacAddr_p); + bHash = EdrvCalcHash(pbMacAddr_p); /* dwData = ether_crc(6, pbMacAddr_p); @@ -490,23 +468,19 @@ BYTE bHash; (WORD) pbMacAddr_p[3], (WORD) pbMacAddr_p[4], (WORD) pbMacAddr_p[5], (WORD) bHash, (WORD) (dwData >> 26), dwData); */ - if (bHash > 31) - { - dwData = EDRV_REGDW_READ(EDRV_REGDW_MAR4); - dwData |= 1 << (bHash - 32); - EDRV_REGDW_WRITE(EDRV_REGDW_MAR4, dwData); - } - else - { - dwData = EDRV_REGDW_READ(EDRV_REGDW_MAR0); - dwData |= 1 << bHash; - EDRV_REGDW_WRITE(EDRV_REGDW_MAR0, dwData); - } - - return Ret; + if (bHash > 31) { + dwData = EDRV_REGDW_READ(EDRV_REGDW_MAR4); + dwData |= 1 << (bHash - 32); + EDRV_REGDW_WRITE(EDRV_REGDW_MAR4, dwData); + } else { + dwData = EDRV_REGDW_READ(EDRV_REGDW_MAR0); + dwData |= 1 << bHash; + EDRV_REGDW_WRITE(EDRV_REGDW_MAR0, dwData); + } + + return Ret; } - //--------------------------------------------------------------------------- // // Function: EdrvUndefineRxMacAddrEntry @@ -520,28 +494,25 @@ BYTE bHash; // State: // //--------------------------------------------------------------------------- -tEplKernel EdrvUndefineRxMacAddrEntry (BYTE * pbMacAddr_p) +tEplKernel EdrvUndefineRxMacAddrEntry(BYTE * pbMacAddr_p) { -tEplKernel Ret = kEplSuccessful; -DWORD dwData; -BYTE bHash; - - bHash = EdrvCalcHash (pbMacAddr_p); - - if (bHash > 31) - { - dwData = EDRV_REGDW_READ(EDRV_REGDW_MAR4); - dwData &= ~(1 << (bHash - 32)); - EDRV_REGDW_WRITE(EDRV_REGDW_MAR4, dwData); - } - else - { - dwData = EDRV_REGDW_READ(EDRV_REGDW_MAR0); - dwData &= ~(1 << bHash); - EDRV_REGDW_WRITE(EDRV_REGDW_MAR0, dwData); - } - - return Ret; + tEplKernel Ret = kEplSuccessful; + DWORD dwData; + BYTE bHash; + + bHash = EdrvCalcHash(pbMacAddr_p); + + if (bHash > 31) { + dwData = EDRV_REGDW_READ(EDRV_REGDW_MAR4); + dwData &= ~(1 << (bHash - 32)); + EDRV_REGDW_WRITE(EDRV_REGDW_MAR4, dwData); + } else { + dwData = EDRV_REGDW_READ(EDRV_REGDW_MAR0); + dwData &= ~(1 << bHash); + EDRV_REGDW_WRITE(EDRV_REGDW_MAR0, dwData); + } + + return Ret; } //--------------------------------------------------------------------------- @@ -558,42 +529,38 @@ BYTE bHash; // State: // //--------------------------------------------------------------------------- -tEplKernel EdrvAllocTxMsgBuffer (tEdrvTxBuffer * pBuffer_p) +tEplKernel EdrvAllocTxMsgBuffer(tEdrvTxBuffer * pBuffer_p) { -tEplKernel Ret = kEplSuccessful; -DWORD i; - - if (pBuffer_p->m_uiMaxBufferLen > EDRV_MAX_FRAME_SIZE) - { - Ret = kEplEdrvNoFreeBufEntry; - goto Exit; - } - - // search a free Tx buffer with appropriate size - for (i = 0; i < EDRV_MAX_TX_BUFFERS; i++) - { - if (EdrvInstance_l.m_afTxBufUsed[i] == FALSE) - { - // free channel found - EdrvInstance_l.m_afTxBufUsed[i] = TRUE; - pBuffer_p->m_uiBufferNumber = i; - pBuffer_p->m_pbBuffer = EdrvInstance_l.m_pbTxBuf + (i * EDRV_MAX_FRAME_SIZE); - pBuffer_p->m_uiMaxBufferLen = EDRV_MAX_FRAME_SIZE; - break; - } - } - if (i >= EDRV_MAX_TX_BUFFERS) - { - Ret = kEplEdrvNoFreeBufEntry; - goto Exit; - } - -Exit: - return Ret; + tEplKernel Ret = kEplSuccessful; + DWORD i; + + if (pBuffer_p->m_uiMaxBufferLen > EDRV_MAX_FRAME_SIZE) { + Ret = kEplEdrvNoFreeBufEntry; + goto Exit; + } + // search a free Tx buffer with appropriate size + for (i = 0; i < EDRV_MAX_TX_BUFFERS; i++) { + if (EdrvInstance_l.m_afTxBufUsed[i] == FALSE) { + // free channel found + EdrvInstance_l.m_afTxBufUsed[i] = TRUE; + pBuffer_p->m_uiBufferNumber = i; + pBuffer_p->m_pbBuffer = + EdrvInstance_l.m_pbTxBuf + + (i * EDRV_MAX_FRAME_SIZE); + pBuffer_p->m_uiMaxBufferLen = EDRV_MAX_FRAME_SIZE; + break; + } + } + if (i >= EDRV_MAX_TX_BUFFERS) { + Ret = kEplEdrvNoFreeBufEntry; + goto Exit; + } + + Exit: + return Ret; } - //--------------------------------------------------------------------------- // // Function: EdrvReleaseTxMsgBuffer @@ -607,22 +574,20 @@ Exit: // State: // //--------------------------------------------------------------------------- -tEplKernel EdrvReleaseTxMsgBuffer (tEdrvTxBuffer * pBuffer_p) +tEplKernel EdrvReleaseTxMsgBuffer(tEdrvTxBuffer * pBuffer_p) { -unsigned int uiBufferNumber; + unsigned int uiBufferNumber; - uiBufferNumber = pBuffer_p->m_uiBufferNumber; + uiBufferNumber = pBuffer_p->m_uiBufferNumber; - if (uiBufferNumber < EDRV_MAX_TX_BUFFERS) - { - EdrvInstance_l.m_afTxBufUsed[uiBufferNumber] = FALSE; - } + if (uiBufferNumber < EDRV_MAX_TX_BUFFERS) { + EdrvInstance_l.m_afTxBufUsed[uiBufferNumber] = FALSE; + } - return kEplSuccessful; + return kEplSuccessful; } - //--------------------------------------------------------------------------- // // Function: EdrvSendTxMsg @@ -636,54 +601,64 @@ unsigned int uiBufferNumber; // State: // //--------------------------------------------------------------------------- -tEplKernel EdrvSendTxMsg (tEdrvTxBuffer * pBuffer_p) +tEplKernel EdrvSendTxMsg(tEdrvTxBuffer * pBuffer_p) { -tEplKernel Ret = kEplSuccessful; -unsigned int uiBufferNumber; -DWORD dwTemp; - - uiBufferNumber = pBuffer_p->m_uiBufferNumber; - - if ((uiBufferNumber >= EDRV_MAX_TX_BUFFERS) - || (EdrvInstance_l.m_afTxBufUsed[uiBufferNumber] == FALSE)) - { - Ret = kEplEdrvBufNotExisting; - goto Exit; - } - - if (EdrvInstance_l.m_pLastTransmittedTxBuffer != NULL) - { // transmission is already active - Ret = kEplInvalidOperation; - dwTemp = EDRV_REGDW_READ((EDRV_REGDW_TSD0 + (EdrvInstance_l.m_uiCurTxDesc * sizeof (DWORD)))); - printk("%s InvOp TSD%u = 0x%08lX", __FUNCTION__, EdrvInstance_l.m_uiCurTxDesc, dwTemp); - printk(" Cmd = 0x%02X\n", (WORD) EDRV_REGB_READ(EDRV_REGB_COMMAND)); - goto Exit; - } - - // save pointer to buffer structure for TxHandler - EdrvInstance_l.m_pLastTransmittedTxBuffer = pBuffer_p; - - EDRV_COUNT_SEND; - - // pad with zeros if necessary, because controller does not do it - if (pBuffer_p->m_uiTxMsgLen < MIN_ETH_SIZE) - { - EPL_MEMSET(pBuffer_p->m_pbBuffer + pBuffer_p->m_uiTxMsgLen, 0, MIN_ETH_SIZE - pBuffer_p->m_uiTxMsgLen); - pBuffer_p->m_uiTxMsgLen = MIN_ETH_SIZE; - } - - // set DMA address of buffer - EDRV_REGDW_WRITE((EDRV_REGDW_TSAD0 + (EdrvInstance_l.m_uiCurTxDesc * sizeof (DWORD))), (EdrvInstance_l.m_pTxBufDma + (uiBufferNumber * EDRV_MAX_FRAME_SIZE))); - dwTemp = EDRV_REGDW_READ((EDRV_REGDW_TSAD0 + (EdrvInstance_l.m_uiCurTxDesc * sizeof (DWORD)))); + tEplKernel Ret = kEplSuccessful; + unsigned int uiBufferNumber; + DWORD dwTemp; + + uiBufferNumber = pBuffer_p->m_uiBufferNumber; + + if ((uiBufferNumber >= EDRV_MAX_TX_BUFFERS) + || (EdrvInstance_l.m_afTxBufUsed[uiBufferNumber] == FALSE)) { + Ret = kEplEdrvBufNotExisting; + goto Exit; + } + + if (EdrvInstance_l.m_pLastTransmittedTxBuffer != NULL) { // transmission is already active + Ret = kEplInvalidOperation; + dwTemp = + EDRV_REGDW_READ((EDRV_REGDW_TSD0 + + (EdrvInstance_l.m_uiCurTxDesc * + sizeof(DWORD)))); + printk("%s InvOp TSD%u = 0x%08lX", __FUNCTION__, + EdrvInstance_l.m_uiCurTxDesc, dwTemp); + printk(" Cmd = 0x%02X\n", + (WORD) EDRV_REGB_READ(EDRV_REGB_COMMAND)); + goto Exit; + } + // save pointer to buffer structure for TxHandler + EdrvInstance_l.m_pLastTransmittedTxBuffer = pBuffer_p; + + EDRV_COUNT_SEND; + + // pad with zeros if necessary, because controller does not do it + if (pBuffer_p->m_uiTxMsgLen < MIN_ETH_SIZE) { + EPL_MEMSET(pBuffer_p->m_pbBuffer + pBuffer_p->m_uiTxMsgLen, 0, + MIN_ETH_SIZE - pBuffer_p->m_uiTxMsgLen); + pBuffer_p->m_uiTxMsgLen = MIN_ETH_SIZE; + } + // set DMA address of buffer + EDRV_REGDW_WRITE((EDRV_REGDW_TSAD0 + + (EdrvInstance_l.m_uiCurTxDesc * sizeof(DWORD))), + (EdrvInstance_l.m_pTxBufDma + + (uiBufferNumber * EDRV_MAX_FRAME_SIZE))); + dwTemp = + EDRV_REGDW_READ((EDRV_REGDW_TSAD0 + + (EdrvInstance_l.m_uiCurTxDesc * sizeof(DWORD)))); // printk("%s TSAD%u = 0x%08lX", __FUNCTION__, EdrvInstance_l.m_uiCurTxDesc, dwTemp); - // start transmission - EDRV_REGDW_WRITE((EDRV_REGDW_TSD0 + (EdrvInstance_l.m_uiCurTxDesc * sizeof (DWORD))), (EDRV_REGDW_TSD_TXTH_DEF | pBuffer_p->m_uiTxMsgLen)); - dwTemp = EDRV_REGDW_READ((EDRV_REGDW_TSD0 + (EdrvInstance_l.m_uiCurTxDesc * sizeof (DWORD)))); + // start transmission + EDRV_REGDW_WRITE((EDRV_REGDW_TSD0 + + (EdrvInstance_l.m_uiCurTxDesc * sizeof(DWORD))), + (EDRV_REGDW_TSD_TXTH_DEF | pBuffer_p->m_uiTxMsgLen)); + dwTemp = + EDRV_REGDW_READ((EDRV_REGDW_TSD0 + + (EdrvInstance_l.m_uiCurTxDesc * sizeof(DWORD)))); // printk(" TSD%u = 0x%08lX / 0x%08lX\n", EdrvInstance_l.m_uiCurTxDesc, dwTemp, (DWORD)(EDRV_REGDW_TSD_TXTH_DEF | pBuffer_p->m_uiTxMsgLen)); -Exit: - return Ret; + Exit: + return Ret; } #if 0 @@ -700,17 +675,15 @@ Exit: // State: // //--------------------------------------------------------------------------- -tEplKernel EdrvTxMsgReady (tEdrvTxBuffer * pBuffer_p) +tEplKernel EdrvTxMsgReady(tEdrvTxBuffer * pBuffer_p) { -tEplKernel Ret = kEplSuccessful; -unsigned int uiBufferNumber; + tEplKernel Ret = kEplSuccessful; + unsigned int uiBufferNumber; - -Exit: - return Ret; + Exit: + return Ret; } - //--------------------------------------------------------------------------- // // Function: EdrvTxMsgStart @@ -724,18 +697,14 @@ Exit: // State: // //--------------------------------------------------------------------------- -tEplKernel EdrvTxMsgStart (tEdrvTxBuffer * pBuffer_p) +tEplKernel EdrvTxMsgStart(tEdrvTxBuffer * pBuffer_p) { -tEplKernel Ret = kEplSuccessful; - - + tEplKernel Ret = kEplSuccessful; - return Ret; + return Ret; } #endif - - //--------------------------------------------------------------------------- // // Function: EdrvReinitRx @@ -751,19 +720,18 @@ tEplKernel Ret = kEplSuccessful; //--------------------------------------------------------------------------- static void EdrvReinitRx(void) { -BYTE bCmd; + BYTE bCmd; - // simply switch off and on the receiver - // this will reset the CAPR register - bCmd = EDRV_REGB_READ(EDRV_REGB_COMMAND); - EDRV_REGB_WRITE(EDRV_REGB_COMMAND, (bCmd & ~EDRV_REGB_COMMAND_RE)); - EDRV_REGB_WRITE(EDRV_REGB_COMMAND, bCmd); + // simply switch off and on the receiver + // this will reset the CAPR register + bCmd = EDRV_REGB_READ(EDRV_REGB_COMMAND); + EDRV_REGB_WRITE(EDRV_REGB_COMMAND, (bCmd & ~EDRV_REGB_COMMAND_RE)); + EDRV_REGB_WRITE(EDRV_REGB_COMMAND, bCmd); - // set receive configuration register - EDRV_REGDW_WRITE(EDRV_REGDW_RCR, EDRV_REGDW_RCR_DEF); + // set receive configuration register + EDRV_REGDW_WRITE(EDRV_REGDW_RCR, EDRV_REGDW_RCR_DEF); } - //--------------------------------------------------------------------------- // // Function: EdrvInterruptHandler @@ -778,203 +746,183 @@ BYTE bCmd; // //--------------------------------------------------------------------------- #if 0 -void EdrvInterruptHandler (void) +void EdrvInterruptHandler(void) { } #endif #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -static int TgtEthIsr (int nIrqNum_p, void* ppDevInstData_p) +static int TgtEthIsr(int nIrqNum_p, void *ppDevInstData_p) #else -static int TgtEthIsr (int nIrqNum_p, void* ppDevInstData_p, struct pt_regs* ptRegs_p) +static int TgtEthIsr(int nIrqNum_p, void *ppDevInstData_p, + struct pt_regs *ptRegs_p) #endif { // EdrvInterruptHandler(); -tEdrvRxBuffer RxBuffer; -tEdrvTxBuffer* pTxBuffer; -WORD wStatus; -DWORD dwTxStatus; -DWORD dwRxStatus; -WORD wCurRx; -BYTE* pbRxBuf; -unsigned int uiLength; -int iHandled = IRQ_HANDLED; + tEdrvRxBuffer RxBuffer; + tEdrvTxBuffer *pTxBuffer; + WORD wStatus; + DWORD dwTxStatus; + DWORD dwRxStatus; + WORD wCurRx; + BYTE *pbRxBuf; + unsigned int uiLength; + int iHandled = IRQ_HANDLED; // printk("¤"); - // read the interrupt status - wStatus = EDRV_REGW_READ(EDRV_REGW_INT_STATUS); - - // acknowledge the interrupts - EDRV_REGW_WRITE(EDRV_REGW_INT_STATUS, wStatus); - - if (wStatus == 0) - { - iHandled = IRQ_NONE; - goto Exit; - } - - // process tasks - if ((wStatus & (EDRV_REGW_INT_TER | EDRV_REGW_INT_TOK)) != 0) - { // transmit interrupt - - if (EdrvInstance_l.m_pbTxBuf == NULL) - { - printk("%s Tx buffers currently not allocated\n", __FUNCTION__); - goto Exit; - } - - // read transmit status - dwTxStatus = EDRV_REGDW_READ((EDRV_REGDW_TSD0 + (EdrvInstance_l.m_uiCurTxDesc * sizeof (DWORD)))); - if ((dwTxStatus & (EDRV_REGDW_TSD_TOK | EDRV_REGDW_TSD_TABT | EDRV_REGDW_TSD_TUN)) != 0) - { // transmit finished - EdrvInstance_l.m_uiCurTxDesc = (EdrvInstance_l.m_uiCurTxDesc + 1) & 0x03; - pTxBuffer = EdrvInstance_l.m_pLastTransmittedTxBuffer; - EdrvInstance_l.m_pLastTransmittedTxBuffer = NULL; - - if ((dwTxStatus & EDRV_REGDW_TSD_TOK) != 0) - { - EDRV_COUNT_TX; - } - else if ((dwTxStatus & EDRV_REGDW_TSD_TUN) != 0) - { - EDRV_COUNT_TX_FUN; - } - else - { // assume EDRV_REGDW_TSD_TABT - EDRV_COUNT_TX_COL_RL; - } + // read the interrupt status + wStatus = EDRV_REGW_READ(EDRV_REGW_INT_STATUS); + + // acknowledge the interrupts + EDRV_REGW_WRITE(EDRV_REGW_INT_STATUS, wStatus); + + if (wStatus == 0) { + iHandled = IRQ_NONE; + goto Exit; + } + // process tasks + if ((wStatus & (EDRV_REGW_INT_TER | EDRV_REGW_INT_TOK)) != 0) { // transmit interrupt + + if (EdrvInstance_l.m_pbTxBuf == NULL) { + printk("%s Tx buffers currently not allocated\n", + __FUNCTION__); + goto Exit; + } + // read transmit status + dwTxStatus = + EDRV_REGDW_READ((EDRV_REGDW_TSD0 + + (EdrvInstance_l.m_uiCurTxDesc * + sizeof(DWORD)))); + if ((dwTxStatus & (EDRV_REGDW_TSD_TOK | EDRV_REGDW_TSD_TABT | EDRV_REGDW_TSD_TUN)) != 0) { // transmit finished + EdrvInstance_l.m_uiCurTxDesc = + (EdrvInstance_l.m_uiCurTxDesc + 1) & 0x03; + pTxBuffer = EdrvInstance_l.m_pLastTransmittedTxBuffer; + EdrvInstance_l.m_pLastTransmittedTxBuffer = NULL; + + if ((dwTxStatus & EDRV_REGDW_TSD_TOK) != 0) { + EDRV_COUNT_TX; + } else if ((dwTxStatus & EDRV_REGDW_TSD_TUN) != 0) { + EDRV_COUNT_TX_FUN; + } else { // assume EDRV_REGDW_TSD_TABT + EDRV_COUNT_TX_COL_RL; + } // printk("T"); - if (pTxBuffer != NULL) - { - // call Tx handler of Data link layer - EdrvInstance_l.m_InitParam.m_pfnTxHandler(pTxBuffer); - } - } - else - { - EDRV_COUNT_TX_ERR; - } - } - - if ((wStatus & (EDRV_REGW_INT_RER | EDRV_REGW_INT_FOVW | EDRV_REGW_INT_RXOVW | EDRV_REGW_INT_PUN)) != 0) - { // receive error interrupt - - if ((wStatus & EDRV_REGW_INT_FOVW) != 0) - { - EDRV_COUNT_RX_FOVW; - } - else if ((wStatus & EDRV_REGW_INT_RXOVW) != 0) - { - EDRV_COUNT_RX_OVW; - } - else if ((wStatus & EDRV_REGW_INT_PUN) != 0) - { // Packet underrun - EDRV_TRACE_RX_PUN(wStatus); - EDRV_COUNT_RX_PUN; - } - else /*if ((wStatus & EDRV_REGW_INT_RER) != 0)*/ - { - EDRV_TRACE_RX_ERR(wStatus); - EDRV_COUNT_RX_ERR; - } - - // reinitialize Rx process - EdrvReinitRx(); - } - - if ((wStatus & EDRV_REGW_INT_ROK) != 0) - { // receive interrupt - - if (EdrvInstance_l.m_pbRxBuf == NULL) - { - printk("%s Rx buffers currently not allocated\n", __FUNCTION__); - goto Exit; - } - - // read current offset in receive buffer - wCurRx = (EDRV_REGW_READ(EDRV_REGW_CAPR) + 0x10) % EDRV_RX_BUFFER_LENGTH; - - while ((EDRV_REGB_READ(EDRV_REGB_COMMAND) & EDRV_REGB_COMMAND_BUFE) == 0) - { // frame available - - // calculate pointer to current frame in receive buffer - pbRxBuf = EdrvInstance_l.m_pbRxBuf + wCurRx; - - // read receive status DWORD - dwRxStatus = le32_to_cpu(*((DWORD*)pbRxBuf)); - - // calculate length of received frame - uiLength = dwRxStatus >> 16; - - if (uiLength == 0xFFF0) - { // frame is unfinished (maybe early Rx interrupt is active) - break; - } - - if ((dwRxStatus & EDRV_RXSTAT_ROK) == 0) - { // error occured while receiving this frame - // ignore it - if ((dwRxStatus & EDRV_RXSTAT_FAE) != 0) - { - EDRV_COUNT_RX_FAE; - } - else if ((dwRxStatus & EDRV_RXSTAT_CRC) != 0) - { - EDRV_TRACE_RX_CRC(dwRxStatus); - EDRV_COUNT_RX_CRC; - } - else - { - EDRV_TRACE_RX_ERR(dwRxStatus); - EDRV_COUNT_RX_ERR; - } - - // reinitialize Rx process - EdrvReinitRx(); - - break; - } - else - { // frame is OK - RxBuffer.m_BufferInFrame = kEdrvBufferLastInFrame; - RxBuffer.m_uiRxMsgLen = uiLength - ETH_CRC_SIZE; - RxBuffer.m_pbBuffer = pbRxBuf + sizeof (dwRxStatus); + if (pTxBuffer != NULL) { + // call Tx handler of Data link layer + EdrvInstance_l.m_InitParam. + m_pfnTxHandler(pTxBuffer); + } + } else { + EDRV_COUNT_TX_ERR; + } + } + + if ((wStatus & (EDRV_REGW_INT_RER | EDRV_REGW_INT_FOVW | EDRV_REGW_INT_RXOVW | EDRV_REGW_INT_PUN)) != 0) { // receive error interrupt + + if ((wStatus & EDRV_REGW_INT_FOVW) != 0) { + EDRV_COUNT_RX_FOVW; + } else if ((wStatus & EDRV_REGW_INT_RXOVW) != 0) { + EDRV_COUNT_RX_OVW; + } else if ((wStatus & EDRV_REGW_INT_PUN) != 0) { // Packet underrun + EDRV_TRACE_RX_PUN(wStatus); + EDRV_COUNT_RX_PUN; + } else { /*if ((wStatus & EDRV_REGW_INT_RER) != 0) */ + + EDRV_TRACE_RX_ERR(wStatus); + EDRV_COUNT_RX_ERR; + } + + // reinitialize Rx process + EdrvReinitRx(); + } + + if ((wStatus & EDRV_REGW_INT_ROK) != 0) { // receive interrupt + + if (EdrvInstance_l.m_pbRxBuf == NULL) { + printk("%s Rx buffers currently not allocated\n", + __FUNCTION__); + goto Exit; + } + // read current offset in receive buffer + wCurRx = + (EDRV_REGW_READ(EDRV_REGW_CAPR) + + 0x10) % EDRV_RX_BUFFER_LENGTH; + + while ((EDRV_REGB_READ(EDRV_REGB_COMMAND) & EDRV_REGB_COMMAND_BUFE) == 0) { // frame available + + // calculate pointer to current frame in receive buffer + pbRxBuf = EdrvInstance_l.m_pbRxBuf + wCurRx; + + // read receive status DWORD + dwRxStatus = le32_to_cpu(*((DWORD *) pbRxBuf)); + + // calculate length of received frame + uiLength = dwRxStatus >> 16; + + if (uiLength == 0xFFF0) { // frame is unfinished (maybe early Rx interrupt is active) + break; + } + + if ((dwRxStatus & EDRV_RXSTAT_ROK) == 0) { // error occured while receiving this frame + // ignore it + if ((dwRxStatus & EDRV_RXSTAT_FAE) != 0) { + EDRV_COUNT_RX_FAE; + } else if ((dwRxStatus & EDRV_RXSTAT_CRC) != 0) { + EDRV_TRACE_RX_CRC(dwRxStatus); + EDRV_COUNT_RX_CRC; + } else { + EDRV_TRACE_RX_ERR(dwRxStatus); + EDRV_COUNT_RX_ERR; + } + + // reinitialize Rx process + EdrvReinitRx(); + + break; + } else { // frame is OK + RxBuffer.m_BufferInFrame = + kEdrvBufferLastInFrame; + RxBuffer.m_uiRxMsgLen = uiLength - ETH_CRC_SIZE; + RxBuffer.m_pbBuffer = + pbRxBuf + sizeof(dwRxStatus); // printk("R"); - EDRV_COUNT_RX; - - // call Rx handler of Data link layer - EdrvInstance_l.m_InitParam.m_pfnRxHandler(&RxBuffer); - } - - // calulate new offset (DWORD aligned) - wCurRx = (WORD) ((wCurRx + uiLength + sizeof (dwRxStatus) + 3) & ~0x3); - EDRV_TRACE_CAPR(wCurRx - 0x10); - EDRV_REGW_WRITE(EDRV_REGW_CAPR, wCurRx - 0x10); - - // reread current offset in receive buffer - wCurRx = (EDRV_REGW_READ(EDRV_REGW_CAPR) + 0x10) % EDRV_RX_BUFFER_LENGTH; - - } - } - - if ((wStatus & EDRV_REGW_INT_SERR) != 0) - { // PCI error - EDRV_COUNT_PCI_ERR; - } - - if ((wStatus & EDRV_REGW_INT_TIMEOUT) != 0) - { // Timeout - EDRV_COUNT_TIMEOUT; - } - -Exit: - return iHandled; + EDRV_COUNT_RX; + + // call Rx handler of Data link layer + EdrvInstance_l.m_InitParam. + m_pfnRxHandler(&RxBuffer); + } + + // calulate new offset (DWORD aligned) + wCurRx = + (WORD) ((wCurRx + uiLength + sizeof(dwRxStatus) + + 3) & ~0x3); + EDRV_TRACE_CAPR(wCurRx - 0x10); + EDRV_REGW_WRITE(EDRV_REGW_CAPR, wCurRx - 0x10); + + // reread current offset in receive buffer + wCurRx = + (EDRV_REGW_READ(EDRV_REGW_CAPR) + + 0x10) % EDRV_RX_BUFFER_LENGTH; + + } + } + + if ((wStatus & EDRV_REGW_INT_SERR) != 0) { // PCI error + EDRV_COUNT_PCI_ERR; + } + + if ((wStatus & EDRV_REGW_INT_TIMEOUT) != 0) { // Timeout + EDRV_COUNT_TIMEOUT; + } + + Exit: + return iHandled; } - //--------------------------------------------------------------------------- // // Function: EdrvInitOne @@ -990,99 +938,96 @@ Exit: // //--------------------------------------------------------------------------- -static int EdrvInitOne(struct pci_dev *pPciDev, - const struct pci_device_id *pId) +static int EdrvInitOne(struct pci_dev *pPciDev, const struct pci_device_id *pId) { -int iResult = 0; -DWORD dwTemp; - - if (EdrvInstance_l.m_pPciDev != NULL) - { // Edrv is already connected to a PCI device - printk("%s device %s discarded\n", __FUNCTION__, pci_name(pPciDev)); - iResult = -ENODEV; - goto Exit; - } - - if (pPciDev->revision >= 0x20) - { - printk("%s device %s is an enhanced 8139C+ version, which is not supported\n", __FUNCTION__, pci_name(pPciDev)); - iResult = -ENODEV; - goto Exit; - } - - EdrvInstance_l.m_pPciDev = pPciDev; - - // enable device - printk("%s enable device\n", __FUNCTION__); - iResult = pci_enable_device(pPciDev); - if (iResult != 0) - { - goto Exit; - } - - if ((pci_resource_flags(pPciDev, 1) & IORESOURCE_MEM) == 0) - { - iResult = -ENODEV; - goto Exit; - } - - printk("%s request regions\n", __FUNCTION__); - iResult = pci_request_regions(pPciDev, DRV_NAME); - if (iResult != 0) - { - goto Exit; - } - - printk("%s ioremap\n", __FUNCTION__); - EdrvInstance_l.m_pIoAddr = ioremap (pci_resource_start(pPciDev, 1), pci_resource_len(pPciDev, 1)); - if (EdrvInstance_l.m_pIoAddr == NULL) - { // remap of controller's register space failed - iResult = -EIO; - goto Exit; - } - - // enable PCI busmaster - printk("%s enable busmaster\n", __FUNCTION__); - pci_set_master (pPciDev); - - // reset controller - printk("%s reset controller\n", __FUNCTION__); - EDRV_REGB_WRITE(EDRV_REGB_COMMAND, EDRV_REGB_COMMAND_RST); - - // wait until reset has finished - for (iResult = 500; iResult > 0; iResult--) - { - if ((EDRV_REGB_READ(EDRV_REGB_COMMAND) & EDRV_REGB_COMMAND_RST) == 0) - { - break; - } - - schedule_timeout(10); - } - - // check hardware version, i.e. chip ID - dwTemp = EDRV_REGDW_READ(EDRV_REGDW_TCR); - if (((dwTemp & EDRV_REGDW_TCR_VER_MASK) != EDRV_REGDW_TCR_VER_C) - && ((dwTemp & EDRV_REGDW_TCR_VER_MASK) != EDRV_REGDW_TCR_VER_D)) - { // unsupported chip - printk("%s Unsupported chip! TCR = 0x%08lX\n", __FUNCTION__, dwTemp); - iResult = -ENODEV; - goto Exit; - } - - // disable interrupts - printk("%s disable interrupts\n", __FUNCTION__); - EDRV_REGW_WRITE(EDRV_REGW_INT_MASK, 0); - // acknowledge all pending interrupts - EDRV_REGW_WRITE(EDRV_REGW_INT_STATUS, EDRV_REGW_READ(EDRV_REGW_INT_STATUS)); - - // install interrupt handler - printk("%s install interrupt handler\n", __FUNCTION__); - iResult = request_irq(pPciDev->irq, TgtEthIsr, IRQF_SHARED, DRV_NAME /*pPciDev->dev.name*/, pPciDev); - if (iResult != 0) - { - goto Exit; - } + int iResult = 0; + DWORD dwTemp; + + if (EdrvInstance_l.m_pPciDev != NULL) { // Edrv is already connected to a PCI device + printk("%s device %s discarded\n", __FUNCTION__, + pci_name(pPciDev)); + iResult = -ENODEV; + goto Exit; + } + + if (pPciDev->revision >= 0x20) { + printk + ("%s device %s is an enhanced 8139C+ version, which is not supported\n", + __FUNCTION__, pci_name(pPciDev)); + iResult = -ENODEV; + goto Exit; + } + + EdrvInstance_l.m_pPciDev = pPciDev; + + // enable device + printk("%s enable device\n", __FUNCTION__); + iResult = pci_enable_device(pPciDev); + if (iResult != 0) { + goto Exit; + } + + if ((pci_resource_flags(pPciDev, 1) & IORESOURCE_MEM) == 0) { + iResult = -ENODEV; + goto Exit; + } + + printk("%s request regions\n", __FUNCTION__); + iResult = pci_request_regions(pPciDev, DRV_NAME); + if (iResult != 0) { + goto Exit; + } + + printk("%s ioremap\n", __FUNCTION__); + EdrvInstance_l.m_pIoAddr = + ioremap(pci_resource_start(pPciDev, 1), + pci_resource_len(pPciDev, 1)); + if (EdrvInstance_l.m_pIoAddr == NULL) { // remap of controller's register space failed + iResult = -EIO; + goto Exit; + } + // enable PCI busmaster + printk("%s enable busmaster\n", __FUNCTION__); + pci_set_master(pPciDev); + + // reset controller + printk("%s reset controller\n", __FUNCTION__); + EDRV_REGB_WRITE(EDRV_REGB_COMMAND, EDRV_REGB_COMMAND_RST); + + // wait until reset has finished + for (iResult = 500; iResult > 0; iResult--) { + if ((EDRV_REGB_READ(EDRV_REGB_COMMAND) & EDRV_REGB_COMMAND_RST) + == 0) { + break; + } + + schedule_timeout(10); + } + + // check hardware version, i.e. chip ID + dwTemp = EDRV_REGDW_READ(EDRV_REGDW_TCR); + if (((dwTemp & EDRV_REGDW_TCR_VER_MASK) != EDRV_REGDW_TCR_VER_C) + && ((dwTemp & EDRV_REGDW_TCR_VER_MASK) != EDRV_REGDW_TCR_VER_D)) { // unsupported chip + printk("%s Unsupported chip! TCR = 0x%08lX\n", __FUNCTION__, + dwTemp); + iResult = -ENODEV; + goto Exit; + } + // disable interrupts + printk("%s disable interrupts\n", __FUNCTION__); + EDRV_REGW_WRITE(EDRV_REGW_INT_MASK, 0); + // acknowledge all pending interrupts + EDRV_REGW_WRITE(EDRV_REGW_INT_STATUS, + EDRV_REGW_READ(EDRV_REGW_INT_STATUS)); + + // install interrupt handler + printk("%s install interrupt handler\n", __FUNCTION__); + iResult = + request_irq(pPciDev->irq, TgtEthIsr, IRQF_SHARED, + DRV_NAME /*pPciDev->dev.name */ , pPciDev); + if (iResult != 0) { + goto Exit; + } /* // unlock configuration registers @@ -1113,64 +1058,66 @@ DWORD dwTemp; EDRV_REGB_WRITE(EDRV_REGB_CMD9346, EDRV_REGB_CMD9346_LOCK); */ - // allocate buffers - printk("%s allocate buffers\n", __FUNCTION__); - EdrvInstance_l.m_pbTxBuf = pci_alloc_consistent(pPciDev, EDRV_TX_BUFFER_SIZE, - &EdrvInstance_l.m_pTxBufDma); - if (EdrvInstance_l.m_pbTxBuf == NULL) - { - iResult = -ENOMEM; - goto Exit; - } - - EdrvInstance_l.m_pbRxBuf = pci_alloc_consistent(pPciDev, EDRV_RX_BUFFER_SIZE, - &EdrvInstance_l.m_pRxBufDma); - if (EdrvInstance_l.m_pbRxBuf == NULL) - { - iResult = -ENOMEM; - goto Exit; - } - - // reset pointers for Tx buffers - printk("%s reset pointers fo Tx buffers\n", __FUNCTION__); - EDRV_REGDW_WRITE(EDRV_REGDW_TSAD0, 0); - dwTemp = EDRV_REGDW_READ(EDRV_REGDW_TSAD0); - EDRV_REGDW_WRITE(EDRV_REGDW_TSAD1, 0); - dwTemp = EDRV_REGDW_READ(EDRV_REGDW_TSAD1); - EDRV_REGDW_WRITE(EDRV_REGDW_TSAD2, 0); - dwTemp = EDRV_REGDW_READ(EDRV_REGDW_TSAD2); - EDRV_REGDW_WRITE(EDRV_REGDW_TSAD3, 0); - dwTemp = EDRV_REGDW_READ(EDRV_REGDW_TSAD3); - - printk(" Command = 0x%02X\n", (WORD) EDRV_REGB_READ(EDRV_REGB_COMMAND)); - - // set pointer for receive buffer in controller - printk("%s set pointer to Rx buffer\n", __FUNCTION__); - EDRV_REGDW_WRITE(EDRV_REGDW_RBSTART, EdrvInstance_l.m_pRxBufDma); - - // enable transmitter and receiver - printk("%s enable Tx and Rx", __FUNCTION__); - EDRV_REGB_WRITE(EDRV_REGB_COMMAND, (EDRV_REGB_COMMAND_RE | EDRV_REGB_COMMAND_TE)); - printk(" Command = 0x%02X\n", (WORD) EDRV_REGB_READ(EDRV_REGB_COMMAND)); - - // clear missed packet counter to enable Rx/Tx process - EDRV_REGDW_WRITE(EDRV_REGDW_MPC, 0); - - // set transmit configuration register - printk("%s set Tx conf register", __FUNCTION__); - EDRV_REGDW_WRITE(EDRV_REGDW_TCR, EDRV_REGDW_TCR_DEF); - printk(" = 0x%08X\n", EDRV_REGDW_READ(EDRV_REGDW_TCR)); - - // set receive configuration register - printk("%s set Rx conf register", __FUNCTION__); - EDRV_REGDW_WRITE(EDRV_REGDW_RCR, EDRV_REGDW_RCR_DEF); - printk(" = 0x%08X\n", EDRV_REGDW_READ(EDRV_REGDW_RCR)); - - // reset multicast MAC address filter - EDRV_REGDW_WRITE(EDRV_REGDW_MAR0, 0); - dwTemp = EDRV_REGDW_READ(EDRV_REGDW_MAR0); - EDRV_REGDW_WRITE(EDRV_REGDW_MAR4, 0); - dwTemp = EDRV_REGDW_READ(EDRV_REGDW_MAR4); + // allocate buffers + printk("%s allocate buffers\n", __FUNCTION__); + EdrvInstance_l.m_pbTxBuf = + pci_alloc_consistent(pPciDev, EDRV_TX_BUFFER_SIZE, + &EdrvInstance_l.m_pTxBufDma); + if (EdrvInstance_l.m_pbTxBuf == NULL) { + iResult = -ENOMEM; + goto Exit; + } + + EdrvInstance_l.m_pbRxBuf = + pci_alloc_consistent(pPciDev, EDRV_RX_BUFFER_SIZE, + &EdrvInstance_l.m_pRxBufDma); + if (EdrvInstance_l.m_pbRxBuf == NULL) { + iResult = -ENOMEM; + goto Exit; + } + // reset pointers for Tx buffers + printk("%s reset pointers fo Tx buffers\n", __FUNCTION__); + EDRV_REGDW_WRITE(EDRV_REGDW_TSAD0, 0); + dwTemp = EDRV_REGDW_READ(EDRV_REGDW_TSAD0); + EDRV_REGDW_WRITE(EDRV_REGDW_TSAD1, 0); + dwTemp = EDRV_REGDW_READ(EDRV_REGDW_TSAD1); + EDRV_REGDW_WRITE(EDRV_REGDW_TSAD2, 0); + dwTemp = EDRV_REGDW_READ(EDRV_REGDW_TSAD2); + EDRV_REGDW_WRITE(EDRV_REGDW_TSAD3, 0); + dwTemp = EDRV_REGDW_READ(EDRV_REGDW_TSAD3); + + printk(" Command = 0x%02X\n", + (WORD) EDRV_REGB_READ(EDRV_REGB_COMMAND)); + + // set pointer for receive buffer in controller + printk("%s set pointer to Rx buffer\n", __FUNCTION__); + EDRV_REGDW_WRITE(EDRV_REGDW_RBSTART, EdrvInstance_l.m_pRxBufDma); + + // enable transmitter and receiver + printk("%s enable Tx and Rx", __FUNCTION__); + EDRV_REGB_WRITE(EDRV_REGB_COMMAND, + (EDRV_REGB_COMMAND_RE | EDRV_REGB_COMMAND_TE)); + printk(" Command = 0x%02X\n", + (WORD) EDRV_REGB_READ(EDRV_REGB_COMMAND)); + + // clear missed packet counter to enable Rx/Tx process + EDRV_REGDW_WRITE(EDRV_REGDW_MPC, 0); + + // set transmit configuration register + printk("%s set Tx conf register", __FUNCTION__); + EDRV_REGDW_WRITE(EDRV_REGDW_TCR, EDRV_REGDW_TCR_DEF); + printk(" = 0x%08X\n", EDRV_REGDW_READ(EDRV_REGDW_TCR)); + + // set receive configuration register + printk("%s set Rx conf register", __FUNCTION__); + EDRV_REGDW_WRITE(EDRV_REGDW_RCR, EDRV_REGDW_RCR_DEF); + printk(" = 0x%08X\n", EDRV_REGDW_READ(EDRV_REGDW_RCR)); + + // reset multicast MAC address filter + EDRV_REGDW_WRITE(EDRV_REGDW_MAR0, 0); + dwTemp = EDRV_REGDW_READ(EDRV_REGDW_MAR0); + EDRV_REGDW_WRITE(EDRV_REGDW_MAR4, 0); + dwTemp = EDRV_REGDW_READ(EDRV_REGDW_MAR4); /* // enable transmitter and receiver @@ -1178,20 +1125,18 @@ DWORD dwTemp; EDRV_REGB_WRITE(EDRV_REGB_COMMAND, (EDRV_REGB_COMMAND_RE | EDRV_REGB_COMMAND_TE)); printk(" Command = 0x%02X\n", (WORD) EDRV_REGB_READ(EDRV_REGB_COMMAND)); */ - // disable early interrupts - EDRV_REGW_WRITE(EDRV_REGW_MULINT, 0); - - // enable interrupts - printk("%s enable interrupts\n", __FUNCTION__); - EDRV_REGW_WRITE(EDRV_REGW_INT_MASK, EDRV_REGW_INT_MASK_DEF); + // disable early interrupts + EDRV_REGW_WRITE(EDRV_REGW_MULINT, 0); + // enable interrupts + printk("%s enable interrupts\n", __FUNCTION__); + EDRV_REGW_WRITE(EDRV_REGW_INT_MASK, EDRV_REGW_INT_MASK_DEF); -Exit: - printk("%s finished with %d\n", __FUNCTION__, iResult); - return iResult; + Exit: + printk("%s finished with %d\n", __FUNCTION__, iResult); + return iResult; } - //--------------------------------------------------------------------------- // // Function: EdrvRemoveOne @@ -1209,55 +1154,48 @@ Exit: static void EdrvRemoveOne(struct pci_dev *pPciDev) { - if (EdrvInstance_l.m_pPciDev != pPciDev) - { // trying to remove unknown device - BUG_ON(EdrvInstance_l.m_pPciDev != pPciDev); - goto Exit; - } - - // disable transmitter and receiver - EDRV_REGB_WRITE(EDRV_REGB_COMMAND, 0); - - // disable interrupts - EDRV_REGW_WRITE(EDRV_REGW_INT_MASK, 0); - - // remove interrupt handler - free_irq(pPciDev->irq, pPciDev); - - - // free buffers - if (EdrvInstance_l.m_pbTxBuf != NULL) - { - pci_free_consistent(pPciDev, EDRV_TX_BUFFER_SIZE, - EdrvInstance_l.m_pbTxBuf, EdrvInstance_l.m_pTxBufDma); - EdrvInstance_l.m_pbTxBuf = NULL; - } - - if (EdrvInstance_l.m_pbRxBuf != NULL) - { - pci_free_consistent(pPciDev, EDRV_RX_BUFFER_SIZE, - EdrvInstance_l.m_pbRxBuf, EdrvInstance_l.m_pRxBufDma); - EdrvInstance_l.m_pbRxBuf = NULL; - } - - // unmap controller's register space - if (EdrvInstance_l.m_pIoAddr != NULL) - { - iounmap(EdrvInstance_l.m_pIoAddr); - } - - // disable the PCI device - pci_disable_device(pPciDev); - - // release memory regions - pci_release_regions(pPciDev); - - EdrvInstance_l.m_pPciDev = NULL; - -Exit:; + if (EdrvInstance_l.m_pPciDev != pPciDev) { // trying to remove unknown device + BUG_ON(EdrvInstance_l.m_pPciDev != pPciDev); + goto Exit; + } + // disable transmitter and receiver + EDRV_REGB_WRITE(EDRV_REGB_COMMAND, 0); + + // disable interrupts + EDRV_REGW_WRITE(EDRV_REGW_INT_MASK, 0); + + // remove interrupt handler + free_irq(pPciDev->irq, pPciDev); + + // free buffers + if (EdrvInstance_l.m_pbTxBuf != NULL) { + pci_free_consistent(pPciDev, EDRV_TX_BUFFER_SIZE, + EdrvInstance_l.m_pbTxBuf, + EdrvInstance_l.m_pTxBufDma); + EdrvInstance_l.m_pbTxBuf = NULL; + } + + if (EdrvInstance_l.m_pbRxBuf != NULL) { + pci_free_consistent(pPciDev, EDRV_RX_BUFFER_SIZE, + EdrvInstance_l.m_pbRxBuf, + EdrvInstance_l.m_pRxBufDma); + EdrvInstance_l.m_pbRxBuf = NULL; + } + // unmap controller's register space + if (EdrvInstance_l.m_pIoAddr != NULL) { + iounmap(EdrvInstance_l.m_pIoAddr); + } + // disable the PCI device + pci_disable_device(pPciDev); + + // release memory regions + pci_release_regions(pPciDev); + + EdrvInstance_l.m_pPciDev = NULL; + + Exit:; } - //--------------------------------------------------------------------------- // // Function: EdrvCalcHash @@ -1272,46 +1210,43 @@ Exit:; // State: // //--------------------------------------------------------------------------- -#define HASH_BITS 6 // used bits in hash -#define CRC32_POLY 0x04C11DB6 // +#define HASH_BITS 6 // used bits in hash +#define CRC32_POLY 0x04C11DB6 // //#define CRC32_POLY 0xEDB88320 // // G(x) = x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 -static BYTE EdrvCalcHash (BYTE * pbMAC_p) +static BYTE EdrvCalcHash(BYTE * pbMAC_p) { -DWORD dwByteCounter; -DWORD dwBitCounter; -DWORD dwData; -DWORD dwCrc; -DWORD dwCarry; -BYTE * pbData; -BYTE bHash; - - pbData = pbMAC_p; - - // calculate crc32 value of mac address - dwCrc = 0xFFFFFFFF; - - for (dwByteCounter = 0; dwByteCounter < 6; dwByteCounter++) - { - dwData = *pbData; - pbData++; - for (dwBitCounter = 0; dwBitCounter < 8; dwBitCounter++, dwData >>= 1) - { - dwCarry = (((dwCrc >> 31) ^ dwData) & 1); - dwCrc = dwCrc << 1; - if (dwCarry != 0) - { - dwCrc = (dwCrc ^ CRC32_POLY) | dwCarry; - } - } - } + DWORD dwByteCounter; + DWORD dwBitCounter; + DWORD dwData; + DWORD dwCrc; + DWORD dwCarry; + BYTE *pbData; + BYTE bHash; + + pbData = pbMAC_p; + + // calculate crc32 value of mac address + dwCrc = 0xFFFFFFFF; + + for (dwByteCounter = 0; dwByteCounter < 6; dwByteCounter++) { + dwData = *pbData; + pbData++; + for (dwBitCounter = 0; dwBitCounter < 8; + dwBitCounter++, dwData >>= 1) { + dwCarry = (((dwCrc >> 31) ^ dwData) & 1); + dwCrc = dwCrc << 1; + if (dwCarry != 0) { + dwCrc = (dwCrc ^ CRC32_POLY) | dwCarry; + } + } + } // printk("MyCRC = 0x%08lX\n", dwCrc); - // only upper 6 bits (HASH_BITS) are used - // which point to specific bit in the hash registers - bHash = (BYTE)((dwCrc >> (32 - HASH_BITS)) & 0x3f); + // only upper 6 bits (HASH_BITS) are used + // which point to specific bit in the hash registers + bHash = (BYTE) ((dwCrc >> (32 - HASH_BITS)) & 0x3f); - return bHash; + return bHash; } - |