diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mmc/at91_mci.c | 141 | ||||
| -rw-r--r-- | drivers/mmc/imxmmc.c | 2 | ||||
| -rw-r--r-- | drivers/mmc/omap.c | 6 | ||||
| -rw-r--r-- | drivers/mmc/sdhci.c | 8 | ||||
| -rw-r--r-- | drivers/serial/Kconfig | 19 | ||||
| -rw-r--r-- | drivers/serial/Makefile | 1 | ||||
| -rw-r--r-- | drivers/serial/amba-pl010.c | 2 | ||||
| -rw-r--r-- | drivers/serial/netx-serial.c | 749 | ||||
| -rw-r--r-- | drivers/serial/pxa.c | 1 |
9 files changed, 844 insertions, 85 deletions
diff --git a/drivers/mmc/at91_mci.c b/drivers/mmc/at91_mci.c index 88f0eef9cf3..3228516b7d1 100644 --- a/drivers/mmc/at91_mci.c +++ b/drivers/mmc/at91_mci.c @@ -81,13 +81,6 @@ #undef SUPPORT_4WIRE -#ifdef CONFIG_MMC_DEBUG -#define DBG(fmt...) \ - printk(fmt) -#else -#define DBG(fmt...) do { } while (0) -#endif - static struct clk *mci_clk; #define FL_SENT_COMMAND (1 << 0) @@ -202,50 +195,50 @@ static void at91mci_pre_dma_read(struct at91mci_host *host) struct mmc_command *cmd; struct mmc_data *data; - DBG("pre dma read\n"); + pr_debug("pre dma read\n"); cmd = host->cmd; if (!cmd) { - DBG("no command\n"); + pr_debug("no command\n"); return; } data = cmd->data; if (!data) { - DBG("no data\n"); + pr_debug("no data\n"); return; } for (i = 0; i < 2; i++) { /* nothing left to transfer */ if (host->transfer_index >= data->sg_len) { - DBG("Nothing left to transfer (index = %d)\n", host->transfer_index); + pr_debug("Nothing left to transfer (index = %d)\n", host->transfer_index); break; } /* Check to see if this needs filling */ if (i == 0) { if (at91_mci_read(AT91_PDC_RCR) != 0) { - DBG("Transfer active in current\n"); + pr_debug("Transfer active in current\n"); continue; } } else { if (at91_mci_read(AT91_PDC_RNCR) != 0) { - DBG("Transfer active in next\n"); + pr_debug("Transfer active in next\n"); continue; } } /* Setup the next transfer */ - DBG("Using transfer index %d\n", host->transfer_index); + pr_debug("Using transfer index %d\n", host->transfer_index); sg = &data->sg[host->transfer_index++]; - DBG("sg = %p\n", sg); + pr_debug("sg = %p\n", sg); sg->dma_address = dma_map_page(NULL, sg->page, sg->offset, sg->length, DMA_FROM_DEVICE); - DBG("dma address = %08X, length = %d\n", sg->dma_address, sg->length); + pr_debug("dma address = %08X, length = %d\n", sg->dma_address, sg->length); if (i == 0) { at91_mci_write(AT91_PDC_RPR, sg->dma_address); @@ -257,7 +250,7 @@ static void at91mci_pre_dma_read(struct at91mci_host *host) } } - DBG("pre dma read done\n"); + pr_debug("pre dma read done\n"); } /* @@ -268,17 +261,17 @@ static void at91mci_post_dma_read(struct at91mci_host *host) struct mmc_command *cmd; struct mmc_data *data; - DBG("post dma read\n"); + pr_debug("post dma read\n"); cmd = host->cmd; if (!cmd) { - DBG("no command\n"); + pr_debug("no command\n"); return; } data = cmd->data; if (!data) { - DBG("no data\n"); + pr_debug("no data\n"); return; } @@ -289,17 +282,17 @@ static void at91mci_post_dma_read(struct at91mci_host *host) struct scatterlist *sg; - DBG("finishing index %d\n", host->in_use_index); + pr_debug("finishing index %d\n", host->in_use_index); sg = &data->sg[host->in_use_index++]; - DBG("Unmapping page %08X\n", sg->dma_address); + pr_debug("Unmapping page %08X\n", sg->dma_address); dma_unmap_page(NULL, sg->dma_address, sg->length, DMA_FROM_DEVICE); /* Swap the contents of the buffer */ buffer = kmap_atomic(sg->page, KM_BIO_SRC_IRQ) + sg->offset; - DBG("buffer = %p, length = %d\n", buffer, sg->length); + pr_debug("buffer = %p, length = %d\n", buffer, sg->length); data->bytes_xfered += sg->length; @@ -320,7 +313,7 @@ static void at91mci_post_dma_read(struct at91mci_host *host) at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); } - DBG("post dma read done\n"); + pr_debug("post dma read done\n"); } /* @@ -331,7 +324,7 @@ static void at91_mci_handle_transmitted(struct at91mci_host *host) struct mmc_command *cmd; struct mmc_data *data; - DBG("Handling the transmit\n"); + pr_debug("Handling the transmit\n"); /* Disable the transfer */ at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); @@ -387,12 +380,12 @@ static unsigned int at91_mci_send_command(struct at91mci_host *host, struct mmc_ /* Not sure if this is needed */ #if 0 if ((at91_mci_read(AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) { - DBG("Clearing timeout\n"); + pr_debug("Clearing timeout\n"); at91_mci_write(AT91_MCI_ARGR, 0); at91_mci_write(AT91_MCI_CMDR, AT91_MCI_OPDCMD); while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY)) { /* spin */ - DBG("Clearing: SR = %08X\n", at91_mci_read(AT91_MCI_SR)); + pr_debug("Clearing: SR = %08X\n", at91_mci_read(AT91_MCI_SR)); } } #endif @@ -411,7 +404,7 @@ static unsigned int at91_mci_send_command(struct at91mci_host *host, struct mmc_ } if (data) { - block_length = 1 << data->blksz_bits; + block_length = data->blksz; blocks = data->blocks; /* always set data start - also set direction flag for read */ @@ -439,7 +432,7 @@ static unsigned int at91_mci_send_command(struct at91mci_host *host, struct mmc_ /* * Set the arguments and send the command */ - DBG("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08lX)\n", + pr_debug("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08lX)\n", cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91_MCI_MR)); if (!data) { @@ -491,7 +484,7 @@ static unsigned int at91_mci_send_command(struct at91mci_host *host, struct mmc_ at91mci_sg_to_dma(host, data); - DBG("Transmitting %d bytes\n", host->total_length); + pr_debug("Transmitting %d bytes\n", host->total_length); at91_mci_write(AT91_PDC_TPR, host->physical_address); at91_mci_write(AT91_PDC_TCR, host->total_length / 4); @@ -525,7 +518,7 @@ static void at91mci_process_command(struct at91mci_host *host, struct mmc_comman ier = at91_mci_send_command(host, cmd); - DBG("setting ier to %08X\n", ier); + pr_debug("setting ier to %08X\n", ier); /* Stop on errors or the required value */ at91_mci_write(AT91_MCI_IER, 0xffff0000 | ier); @@ -570,7 +563,7 @@ static void at91mci_completed_command(struct at91mci_host *host) status = at91_mci_read(AT91_MCI_SR); - DBG("Status = %08X [%08X %08X %08X %08X]\n", + pr_debug("Status = %08X [%08X %08X %08X %08X]\n", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); if (status & (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE | @@ -590,7 +583,7 @@ static void at91mci_completed_command(struct at91mci_host *host) else cmd->error = MMC_ERR_FAILED; - DBG("Error detected and set to %d (cmd = %d, retries = %d)\n", + pr_debug("Error detected and set to %d (cmd = %d, retries = %d)\n", cmd->error, cmd->opcode, cmd->retries); } } @@ -621,10 +614,7 @@ static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) struct at91mci_host *host = mmc_priv(mmc); unsigned long at91_master_clock = clk_get_rate(mci_clk); - if (host) - host->bus_mode = ios->bus_mode; - else - printk("MMC: No host for bus_mode\n"); + host->bus_mode = ios->bus_mode; if (ios->clock == 0) { /* Disable the MCI controller */ @@ -640,15 +630,15 @@ static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) else clkdiv = (at91_master_clock / ios->clock) / 2; - DBG("clkdiv = %d. mcck = %ld\n", clkdiv, + pr_debug("clkdiv = %d. mcck = %ld\n", clkdiv, at91_master_clock / (2 * (clkdiv + 1))); } if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) { - DBG("MMC: Setting controller bus width to 4\n"); + pr_debug("MMC: Setting controller bus width to 4\n"); at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) | AT91_MCI_SDCBUS); } else { - DBG("MMC: Setting controller bus width to 1\n"); + pr_debug("MMC: Setting controller bus width to 1\n"); at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); } @@ -656,7 +646,7 @@ static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) at91_mci_write(AT91_MCI_MR, (at91_mci_read(AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv); /* maybe switch power to the card */ - if (host && host->board->vcc_pin) { + if (host->board->vcc_pin) { switch (ios->power_mode) { case MMC_POWER_OFF: at91_set_gpio_output(host->board->vcc_pin, 0); @@ -679,11 +669,8 @@ static irqreturn_t at91_mci_irq(int irq, void *devid, struct pt_regs *regs) unsigned int int_status; - if (host == NULL) - return IRQ_HANDLED; - int_status = at91_mci_read(AT91_MCI_SR); - DBG("MCI irq: status = %08X, %08lX, %08lX\n", int_status, at91_mci_read(AT91_MCI_IMR), + pr_debug("MCI irq: status = %08X, %08lX, %08lX\n", int_status, at91_mci_read(AT91_MCI_IMR), int_status & at91_mci_read(AT91_MCI_IMR)); if ((int_status & at91_mci_read(AT91_MCI_IMR)) & 0xffff0000) @@ -692,75 +679,75 @@ static irqreturn_t at91_mci_irq(int irq, void *devid, struct pt_regs *regs) int_status &= at91_mci_read(AT91_MCI_IMR); if (int_status & AT91_MCI_UNRE) - DBG("MMC: Underrun error\n"); + pr_debug("MMC: Underrun error\n"); if (int_status & AT91_MCI_OVRE) - DBG("MMC: Overrun error\n"); + pr_debug("MMC: Overrun error\n"); if (int_status & AT91_MCI_DTOE) - DBG("MMC: Data timeout\n"); + pr_debug("MMC: Data timeout\n"); if (int_status & AT91_MCI_DCRCE) - DBG("MMC: CRC error in data\n"); + pr_debug("MMC: CRC error in data\n"); if (int_status & AT91_MCI_RTOE) - DBG("MMC: Response timeout\n"); + pr_debug("MMC: Response timeout\n"); if (int_status & AT91_MCI_RENDE) - DBG("MMC: Response end bit error\n"); + pr_debug("MMC: Response end bit error\n"); if (int_status & AT91_MCI_RCRCE) - DBG("MMC: Response CRC error\n"); + pr_debug("MMC: Response CRC error\n"); if (int_status & AT91_MCI_RDIRE) - DBG("MMC: Response direction error\n"); + pr_debug("MMC: Response direction error\n"); if (int_status & AT91_MCI_RINDE) - DBG("MMC: Response index error\n"); + pr_debug("MMC: Response index error\n"); /* Only continue processing if no errors */ if (!completed) { if (int_status & AT91_MCI_TXBUFE) { - DBG("TX buffer empty\n"); + pr_debug("TX buffer empty\n"); at91_mci_handle_transmitted(host); } if (int_status & AT91_MCI_RXBUFF) { - DBG("RX buffer full\n"); + pr_debug("RX buffer full\n"); at91_mci_write(AT91_MCI_IER, AT91_MCI_CMDRDY); } if (int_status & AT91_MCI_ENDTX) { - DBG("Transmit has ended\n"); + pr_debug("Transmit has ended\n"); } if (int_status & AT91_MCI_ENDRX) { - DBG("Receive has ended\n"); + pr_debug("Receive has ended\n"); at91mci_post_dma_read(host); } if (int_status & AT91_MCI_NOTBUSY) { - DBG("Card is ready\n"); + pr_debug("Card is ready\n"); at91_mci_write(AT91_MCI_IER, AT91_MCI_CMDRDY); } if (int_status & AT91_MCI_DTIP) { - DBG("Data transfer in progress\n"); + pr_debug("Data transfer in progress\n"); } if (int_status & AT91_MCI_BLKE) { - DBG("Block transfer has ended\n"); + pr_debug("Block transfer has ended\n"); } if (int_status & AT91_MCI_TXRDY) { - DBG("Ready to transmit\n"); + pr_debug("Ready to transmit\n"); } if (int_status & AT91_MCI_RXRDY) { - DBG("Ready to receive\n"); + pr_debug("Ready to receive\n"); } if (int_status & AT91_MCI_CMDRDY) { - DBG("Command ready\n"); + pr_debug("Command ready\n"); completed = 1; } } at91_mci_write(AT91_MCI_IDR, int_status); if (completed) { - DBG("Completed command\n"); + pr_debug("Completed command\n"); at91_mci_write(AT91_MCI_IDR, 0xffffffff); at91mci_completed_command(host); } @@ -779,10 +766,10 @@ static irqreturn_t at91_mmc_det_irq(int irq, void *_host, struct pt_regs *regs) */ if (present != host->present) { host->present = present; - DBG("%s: card %s\n", mmc_hostname(host->mmc), + pr_debug("%s: card %s\n", mmc_hostname(host->mmc), present ? "insert" : "remove"); if (!present) { - DBG("****** Resetting SD-card bus width ******\n"); + pr_debug("****** Resetting SD-card bus width ******\n"); at91_mci_write(AT91_MCI_SDCR, 0); } mmc_detect_change(host->mmc, msecs_to_jiffies(100)); @@ -822,13 +809,13 @@ static int at91_mci_probe(struct platform_device *pdev) struct at91mci_host *host; int ret; - DBG("Probe MCI devices\n"); + pr_debug("Probe MCI devices\n"); at91_mci_disable(); at91_mci_enable(); mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev); if (!mmc) { - DBG("Failed to allocate mmc host\n"); + pr_debug("Failed to allocate mmc host\n"); return -ENOMEM; } @@ -854,8 +841,9 @@ static int at91_mci_probe(struct platform_device *pdev) * Get Clock */ mci_clk = clk_get(&pdev->dev, "mci_clk"); - if (!mci_clk) { + if (IS_ERR(mci_clk)) { printk(KERN_ERR "AT91 MMC: no clock defined.\n"); + mmc_free_host(mmc); return -ENODEV; } clk_enable(mci_clk); /* Enable the peripheral clock */ @@ -865,7 +853,10 @@ static int at91_mci_probe(struct platform_device *pdev) */ ret = request_irq(AT91_ID_MCI, at91_mci_irq, SA_SHIRQ, DRIVER_NAME, host); if (ret) { - DBG("Failed to request MCI interrupt\n"); + printk(KERN_ERR "Failed to request MCI interrupt\n"); + clk_disable(mci_clk); + clk_put(mci_clk); + mmc_free_host(mmc); return ret; } @@ -886,12 +877,12 @@ static int at91_mci_probe(struct platform_device *pdev) */ if (host->board->det_pin) { ret = request_irq(host->board->det_pin, at91_mmc_det_irq, - SA_SAMPLE_RANDOM, DRIVER_NAME, host); + 0, DRIVER_NAME, host); if (ret) - DBG("couldn't allocate MMC detect irq\n"); + printk(KERN_ERR "couldn't allocate MMC detect irq\n"); } - DBG(KERN_INFO "Added MCI driver\n"); + pr_debug(KERN_INFO "Added MCI driver\n"); return 0; } @@ -924,7 +915,7 @@ static int at91_mci_remove(struct platform_device *pdev) platform_set_drvdata(pdev, NULL); - DBG("Removed\n"); + pr_debug("MCI Removed\n"); return 0; } diff --git a/drivers/mmc/imxmmc.c b/drivers/mmc/imxmmc.c index a4eb1d0e7a7..5c62f4e6ad0 100644 --- a/drivers/mmc/imxmmc.c +++ b/drivers/mmc/imxmmc.c @@ -228,7 +228,7 @@ static int imxmci_busy_wait_for_status(struct imxmci_host *host, static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data) { unsigned int nob = data->blocks; - unsigned int blksz = 1 << data->blksz_bits; + unsigned int blksz = data->blksz; unsigned int datasz = nob * blksz; int i; diff --git a/drivers/mmc/omap.c b/drivers/mmc/omap.c index becb3c68c34..c25244b3657 100644 --- a/drivers/mmc/omap.c +++ b/drivers/mmc/omap.c @@ -584,10 +584,10 @@ mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data) int sync_dev = 0; data_addr = io_v2p((u32) host->base) + OMAP_MMC_REG_DATA; - frame = 1 << data->blksz_bits; + frame = data->blksz; count = sg_dma_len(sg); - if ((data->blocks == 1) && (count > (1 << data->blksz_bits))) + if ((data->blocks == 1) && (count > data->blksz)) count = frame; host->dma_len = count; @@ -776,7 +776,7 @@ mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req) } - block_size = 1 << data->blksz_bits; + block_size = data->blksz; OMAP_MMC_WRITE(host->base, NBLK, data->blocks - 1); OMAP_MMC_WRITE(host->base, BLEN, block_size - 1); diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 6bfcdbc7491..8e9100bd57e 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -268,7 +268,7 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data) } DBG("blksz %04x blks %04x flags %08x\n", - 1 << data->blksz_bits, data->blocks, data->flags); + data->blksz, data->blocks, data->flags); DBG("tsac %d ms nsac %d clk\n", data->timeout_ns / 1000000, data->timeout_clks); @@ -282,7 +282,7 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data) writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE); - writew(1 << data->blksz_bits, host->ioaddr + SDHCI_BLOCK_SIZE); + writew(data->blksz, host->ioaddr + SDHCI_BLOCK_SIZE); writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT); if (host->flags & SDHCI_USE_DMA) { @@ -294,7 +294,7 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data) writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS); } else { - host->size = (1 << data->blksz_bits) * data->blocks; + host->size = data->blksz * data->blocks; host->cur_sg = data->sg; host->num_sg = data->sg_len; @@ -335,7 +335,7 @@ static void sdhci_finish_data(struct sdhci_host *host) blocks = 0; else blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT); - data->bytes_xfered = (1 << data->blksz_bits) * (data->blocks - blocks); + data->bytes_xfered = data->blksz * (data->blocks - blocks); if ((data->error == MMC_ERR_NONE) && blocks) { printk(KERN_ERR "%s: Controller signalled completion even " diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 5ea778fc1ca..bef4a9622ed 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -937,4 +937,23 @@ config SERIAL_SGI_IOC3 If you have an SGI Altix with an IOC3 serial card, say Y or M. Otherwise, say N. +config SERIAL_NETX + bool "NetX serial port support" + depends on ARM && ARCH_NETX + select SERIAL_CORE + help + If you have a machine based on a Hilscher NetX SoC you + can enable its onboard serial port by enabling this option. + + To compile this driver as a module, choose M here: the + module will be called netx-serial. + +config SERIAL_NETX_CONSOLE + bool "Console on NetX serial port" + depends on SERIAL_NETX + select SERIAL_CORE_CONSOLE + help + If you have enabled the serial port on the Motorola IMX + CPU you can make it the console by answering Y to this option. + endmenu diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 0a71bf68a03..927faee0362 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -55,3 +55,4 @@ obj-$(CONFIG_SERIAL_VR41XX) += vr41xx_siu.o obj-$(CONFIG_SERIAL_SGI_IOC4) += ioc4_serial.o obj-$(CONFIG_SERIAL_SGI_IOC3) += ioc3_serial.o obj-$(CONFIG_SERIAL_AT91) += at91_serial.o +obj-$(CONFIG_SERIAL_NETX) += netx-serial.o diff --git a/drivers/serial/amba-pl010.c b/drivers/serial/amba-pl010.c index 1631414000a..e920d196d0b 100644 --- a/drivers/serial/amba-pl010.c +++ b/drivers/serial/amba-pl010.c @@ -52,7 +52,7 @@ #include <asm/io.h> -#define UART_NR 2 +#define UART_NR 8 #define SERIAL_AMBA_MAJOR 204 #define SERIAL_AMBA_MINOR 16 diff --git a/drivers/serial/netx-serial.c b/drivers/serial/netx-serial.c new file mode 100644 index 00000000000..c1adc9e4b23 --- /dev/null +++ b/drivers/serial/netx-serial.c @@ -0,0 +1,749 @@ +/* + * drivers/serial/netx-serial.c + * + * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/config.h> + +#if defined(CONFIG_SERIAL_NETX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) +#define SUPPORT_SYSRQ +#endif + +#include <linux/device.h> +#include <linux/module.h> +#include <linux/ioport.h> +#include <linux/init.h> +#include <linux/console.h> +#include <linux/sysrq.h> +#include <linux/platform_device.h> +#include <linux/tty.h> +#include <linux/tty_flip.h> +#include <linux/serial_core.h> +#include <linux/serial.h> + +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/hardware.h> +#include <asm/arch/netx-regs.h> + +/* We've been assigned a range on the "Low-density serial ports" major */ +#define SERIAL_NX_MAJOR 204 +#define MINOR_START 170 + +#ifdef CONFIG_SERIAL_NETX_CONSOLE + +enum uart_regs { + UART_DR = 0x00, + UART_SR = 0x04, + UART_LINE_CR = 0x08, + UART_BAUDDIV_MSB = 0x0c, + UART_BAUDDIV_LSB = 0x10, + UART_CR = 0x14, + UART_FR = 0x18, + UART_IIR = 0x1c, + UART_ILPR = 0x20, + UART_RTS_CR = 0x24, + UART_RTS_LEAD = 0x28, + UART_RTS_TRAIL = 0x2c, + UART_DRV_ENABLE = 0x30, + UART_BRM_CR = 0x34, + UART_RXFIFO_IRQLEVEL = 0x38, + UART_TXFIFO_IRQLEVEL = 0x3c, +}; + +#define SR_FE (1<<0) +#define SR_PE (1<<1) +#define SR_BE (1<<2) +#define SR_OE (1<<3) + +#define LINE_CR_BRK (1<<0) +#define LINE_CR_PEN (1<<1) +#define LINE_CR_EPS (1<<2) +#define LINE_CR_STP2 (1<<3) +#define LINE_CR_FEN (1<<4) +#define LINE_CR_5BIT (0<<5) +#define LINE_CR_6BIT (1<<5) +#define LINE_CR_7BIT (2<<5) +#define LINE_CR_8BIT (3<<5) +#define LINE_CR_BITS_MASK (3<<5) + +#define CR_UART_EN (1<<0) +#define CR_SIREN (1<<1) +#define CR_SIRLP (1<<2) +#define CR_MSIE (1<<3) +#define CR_RIE (1<<4) +#define CR_TIE (1<<5) +#define CR_RTIE (1<<6) +#define CR_LBE (1<<7) + +#define FR_CTS (1<<0) +#define FR_DSR (1<<1) +#define FR_DCD (1<<2) +#define FR_BUSY (1<<3) +#define FR_RXFE (1<<4) +#define FR_TXFF (1<<5) +#define FR_RXFF (1<<6) +#define FR_TXFE (1<<7) + +#define IIR_MIS (1<<0) +#define IIR_RIS (1<<1) +#define IIR_TIS (1<<2) +#define IIR_RTIS (1<<3) +#define IIR_MASK 0xf + +#define RTS_CR_AUTO (1<<0) +#define RTS_CR_RTS (1<<1) +#define RTS_CR_COUNT (1<<2) +#define RTS_CR_MOD2 (1<<3) +#define RTS_CR_RTS_POL (1<<4) +#define RTS_CR_CTS_CTR (1<<5) +#define RTS_CR_CTS_POL (1<<6) +#define RTS_CR_STICK (1<<7) + +#define UART_PORT_SIZE 0x40 +#define DRIVER_NAME "netx-uart" + +struct netx_port { + struct uart_port port; +}; + +static void netx_stop_tx(struct uart_port *port) +{ + unsigned int val; + val = readl(port->membase + UART_CR); + writel(val & ~CR_TIE, port->membase + UART_CR); +} + +static void netx_stop_rx(struct uart_port *port) +{ + unsigned int val; + val = readl(port->membase + UART_CR); + writel(val & ~CR_RIE, port->membase + UART_CR); +} + +static void netx_enable_ms(struct uart_port *port) +{ + unsigned int val; + val = readl(port->membase + UART_CR); + writel(val | CR_MSIE, port->membase + UART_CR); +} + +static inline void netx_transmit_buffer(struct uart_port *port) +{ + struct circ_buf *xmit = &port->info->xmit; + + if (port->x_char) { + writel(port->x_char, port->membase + UART_DR); + port->icount.tx++; + port->x_char = 0; + return; + } + + if (uart_tx_stopped(port) || uart_circ_empty(xmit)) { + netx_stop_tx(port); + return; + } + + do { + /* send xmit->buf[xmit->tail] + * out the port here */ + writel(xmit->buf[xmit->tail], port->membase + UART_DR); + xmit->tail = (xmit->tail + 1) & + (UART_XMIT_SIZE - 1); + port->icount.tx++; + if (uart_circ_empty(xmit)) + break; + } while (!(readl(port->membase + UART_FR) & FR_TXFF)); + + if (uart_circ_empty(xmit)) + netx_stop_tx(port); +} + +static void netx_start_tx(struct uart_port *port) +{ + writel( + readl(port->membase + UART_CR) | CR_TIE, port->membase + UART_CR); + + if (!(readl(port->membase + UART_FR) & FR_TXFF)) + netx_transmit_buffer(port); +} + +static unsigned int netx_tx_empty(struct uart_port *port) +{ + return readl(port->membase + UART_FR) & FR_BUSY ? 0 : TIOCSER_TEMT; +} + +static void netx_txint(struct uart_port *port) +{ + struct circ_buf *xmit = &port->info->xmit; + + if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { + netx_stop_tx(port); + return; + } + + netx_transmit_buffer(port); + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(port); +} + +static void netx_rxint(struct uart_port *port, struct pt_regs *regs) +{ + unsigned char rx, flg, status; + struct tty_struct *tty = port->info->tty; + + while (!(readl(port->membase + UART_FR) & FR_RXFE)) { + rx = readl(port->membase + UART_DR); + flg = TTY_NORMAL; + port->icount.rx++; + status = readl(port->membase + UART_SR); + if (status & SR_BE) { + writel(0, port->membase + UART_SR); + if (uart_handle_break(port)) + continue; + } + + if (unlikely(status & (SR_FE | SR_PE | SR_OE))) { + + if (status & SR_PE) + port->icount.parity++; + else if (status & SR_FE) + port->icount.frame++; + if (status & SR_OE) + port->icount.overrun++; + + status &= port->read_status_mask; + + if (status & SR_BE) + flg = TTY_BREAK; + else if (status & SR_PE) + flg = TTY_PARITY; + else if (status & SR_FE) + flg = TTY_FRAME; + } + + if (uart_handle_sysrq_char(port, rx, regs)) + continue; + + uart_insert_char(port, status, SR_OE, rx, flg); + } + + tty_flip_buffer_push(tty); + return; +} + +static irqreturn_t netx_int(int irq, void *dev_id, struct pt_regs *regs) +{ + struct uart_port *port = (struct uart_port *)dev_id; + unsigned long flags; + unsigned char status; + + spin_lock_irqsave(&port->lock,flags); + + status = readl(port->membase + UART_IIR) & IIR_MASK; + while (status) { + if (status & IIR_RIS) + netx_rxint(port, regs); + if (status & IIR_TIS) + netx_txint(port); + if (status & IIR_MIS) { + if (readl(port->membase + UART_FR) & FR_CTS) + uart_handle_cts_change(port, 1); + else + uart_handle_cts_change(port, 0); + } + writel(0, port->membase + UART_IIR); + status = readl(port->membase + UART_IIR) & IIR_MASK; + } + + spin_unlock_irqrestore(&port->lock,flags); + return IRQ_HANDLED; +} + +static unsigned int netx_get_mctrl(struct uart_port *port) +{ + unsigned int ret = TIOCM_DSR | TIOCM_CAR; + + if (readl(port->membase + UART_FR) & FR_CTS) + ret |= TIOCM_CTS; + + return ret; +} + +static void netx_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + unsigned int val; + + if (mctrl & TIOCM_RTS) { + val = readl(port->membase + UART_RTS_CR); + writel(val | RTS_CR_RTS, port->membase + UART_RTS_CR); + } +} + +static void netx_break_ctl(struct uart_port *port, int break_state) +{ + unsigned int line_cr; + spin_lock_irq(&port->lock); + + line_cr = readl(port->membase + UART_LINE_CR); + if (break_state != 0) + line_cr |= LINE_CR_BRK; + else + line_cr &= ~LINE_CR_BRK; + writel(line_cr, port->membase + UART_LINE_CR); + + spin_unlock_irq(&port->lock); +} + +static int netx_startup(struct uart_port *port) +{ + int ret; + + ret = request_irq(port->irq, netx_int, 0, + DRIVER_NAME, port); + if (ret) { + dev_err(port->dev, "unable to grab irq%d\n",port->irq); + goto exit; + } + + writel(readl(port->membase + UART_LINE_CR) | LINE_CR_FEN, + port->membase + UART_LINE_CR); + + writel(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE | CR_UART_EN, + port->membase + UART_CR); + +exit: + return ret; +} + +static void netx_shutdown(struct uart_port *port) +{ + writel(0, port->membase + UART_CR) ; + + free_irq(port->irq, port); +} + +static void +netx_set_termios(struct uart_port *port, struct termios *termios, + struct termios *old) +{ + unsigned int baud, quot; + unsigned char old_cr; + unsigned char line_cr = LINE_CR_FEN; + unsigned char rts_cr = 0; + + switch (termios->c_cflag & CSIZE) { + case CS5: + line_cr |= LINE_CR_5BIT; + break; + case CS6: + line_cr |= LINE_CR_6BIT; + break; + case CS7: + line_cr |= LINE_CR_7BIT; + break; + case CS8: + line_cr |= LINE_CR_8BIT; + break; + } + + if (termios->c_cflag & CSTOPB) + line_cr |= LINE_CR_STP2; + + if (termios->c_cflag & PARENB) { + line_cr |= LINE_CR_PEN; + if (!(termios->c_cflag & PARODD)) + line_cr |= LINE_CR_EPS; + } + + if (termios->c_cflag & CRTSCTS) + rts_cr = RTS_CR_AUTO | RTS_CR_CTS_CTR | RTS_CR_RTS_POL; + + baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); + quot = baud * 4096; + quot /= 1000; + quot *= 256; + quot /= 100000; + + spin_lock_irq(&port->lock); + + uart_update_timeout(port, termios->c_cflag, baud); + + old_cr = readl(port->membase + UART_CR); + + /* disable interrupts */ + writel(old_cr & ~(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE), + port->membase + UART_CR); + + /* drain transmitter */ + while (readl(port->membase + UART_FR) & FR_BUSY); + + /* disable UART */ + writel(old_cr & ~CR_UART_EN, port->membase + UART_CR); + + /* modem status interrupts */ + old_cr &= ~CR_MSIE; + if (UART_ENABLE_MS(port, termios->c_cflag)) + old_cr |= CR_MSIE; + + writel((quot>>8) & 0xff, port->membase + UART_BAUDDIV_MSB); + writel(quot & 0xff, port->membase + UART_BAUDDIV_LSB); + writel(line_cr, port->membase + UART_LINE_CR); + + writel(rts_cr, port->membase + UART_RTS_CR); + + /* + * Characters to ignore + */ + port->ignore_status_mask = 0; + if (termios->c_iflag & IGNPAR) + port->ignore_status_mask |= SR_PE; + if (termios->c_iflag & IGNBRK) { + port->ignore_status_mask |= SR_BE; + /* + * If we're ignoring parity and break indicators, + * ignore overruns too (for real raw support). + */ + if (termios->c_iflag & IGNPAR) + port->ignore_status_mask |= SR_PE; + } + + port->read_status_mask = 0; + if (termios->c_iflag & (BRKINT | PARMRK)) + port->read_status_mask |= SR_BE; + if (termios->c_iflag & INPCK) + port->read_status_mask |= SR_PE | SR_FE; + + writel(old_cr, port->membase + UART_CR); + + spin_unlock_irq(&port->lock); +} + +static const char *netx_type(struct uart_port *port) +{ + return port->type == PORT_NETX ? "NETX" : NULL; +} + +static void netx_release_port(struct uart_port *port) +{ + release_mem_region(port->mapbase, UART_PORT_SIZE); +} + +static int netx_request_port(struct uart_port *port) +{ + return request_mem_region(port->mapbase, UART_PORT_SIZE, + DRIVER_NAME) != NULL ? 0 : -EBUSY; +} + +static void netx_config_port(struct uart_port *port, int flags) +{ + if (flags & UART_CONFIG_TYPE && netx_request_port(port) == 0) + port->type = PORT_NETX; +} + +static int +netx_verify_port(struct uart_port *port, struct serial_struct *ser) +{ + int ret = 0; + + if (ser->type != PORT_UNKNOWN && ser->type != PORT_NETX) + ret = -EINVAL; + + return ret; +} + +static struct uart_ops netx_pops = { + .tx_empty = netx_tx_empty, + .set_mctrl = netx_set_mctrl, + .get_mctrl = netx_get_mctrl, + .stop_tx = netx_stop_tx, + .start_tx = netx_start_tx, + .stop_rx = netx_stop_rx, + .enable_ms = netx_enable_ms, + .break_ctl = netx_break_ctl, + .startup = netx_startup, + .shutdown = netx_shutdown, + .set_termios = netx_set_termios, + .type = netx_type, + .release_port = netx_release_port, + .request_port = netx_request_port, + .config_port = netx_config_port, + .verify_port = netx_verify_port, +}; + +static struct netx_port netx_ports[] = { + { + .port = { + .type = PORT_NETX, + .iotype = UPIO_MEM, + .membase = (char __iomem *)io_p2v(NETX_PA_UART0), + .mapbase = NETX_PA_UART0, + .irq = NETX_IRQ_UART0, + .uartclk = 100000000, + .fifosize = 16, + .flags = UPF_BOOT_AUTOCONF, + .ops = &netx_pops, + .line = 0, + }, + }, { + .port = { + .type = PORT_NETX, + .iotype = UPIO_MEM, + .membase = (char __iomem *)io_p2v(NETX_PA_UART1), + .mapbase = NETX_PA_UART1, + .irq = NETX_IRQ_UART1, + .uartclk = 100000000, + .fifosize = 16, + .flags = UPF_BOOT_AUTOCONF, + .ops = &netx_pops, + .line = 1, + }, + }, { + .port = { + .type = PORT_NETX, + .iotype = UPIO_MEM, + .membase = (char __iomem *)io_p2v(NETX_PA_UART2), + .mapbase = NETX_PA_UART2, + .irq = NETX_IRQ_UART2, + .uartclk = 100000000, + .fifosize = 16, + .flags = UPF_BOOT_AUTOCONF, + .ops = &netx_pops, + .line = 2, + }, + } +}; + +static void netx_console_putchar(struct uart_port *port, int ch) +{ + while (readl(port->membase + UART_FR) & FR_BUSY); + writel(ch, port->membase + UART_DR); +} + +static void +netx_console_write(struct console *co, const char *s, unsigned int count) +{ + struct uart_port *port = &netx_ports[co->index].port; + unsigned char cr_save; + + cr_save = readl(port->membase + UART_CR); + writel(cr_save | CR_UART_EN, port->membase + UART_CR); + + uart_console_write(port, s, count, netx_console_putchar); + + while (readl(port->membase + UART_FR) & FR_BUSY); + writel(cr_save, port->membase + UART_CR); +} + +static void __init +netx_console_get_options(struct uart_port *port, int *baud, + int *parity, int *bits, int *flow) +{ + unsigned char line_cr; + + *baud = (readl(port->membase + UART_BAUDDIV_MSB) << 8) | + readl(port->membase + UART_BAUDDIV_LSB); + *baud *= 1000; + *baud /= 4096; + *baud *= 1000; + *baud /= 256; + *baud *= 100; + + line_cr = readl(port->membase + UART_LINE_CR); + *parity = 'n'; + if (line_cr & LINE_CR_PEN) { + if (line_cr & LINE_CR_EPS) + *parity = 'e'; + else + *parity = 'o'; + } + + switch (line_cr & LINE_CR_BITS_MASK) { + case LINE_CR_8BIT: + *bits = 8; + break; + case LINE_CR_7BIT: + *bits = 7; + break; + case LINE_CR_6BIT: + *bits = 6; + break; + case LINE_CR_5BIT: + *bits = 5; + break; + } + + if (readl(port->membase + UART_RTS_CR) & RTS_CR_AUTO) + *flow = 'r'; +} + +static int __init +netx_console_setup(struct console *co, char *options) +{ + struct netx_port *sport; + int baud = 9600; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + + /* + * Check whether an invalid uart number has been specified, and + * if so, search for the first available port that does have + * console support. + */ + if (co->index == -1 || co->index >= ARRAY_SIZE(netx_ports)) + co->index = 0; + sport = &netx_ports[co->index]; + + if (options) { + uart_parse_options(options, &baud, &parity, &bits, &flow); + } else { + /* if the UART is enabled, assume it has been correctly setup + * by the bootloader and get the options + */ + if (readl(sport->port.membase + UART_CR) & CR_UART_EN) { + netx_console_get_options(&sport->port, &baud, + &parity, &bits, &flow); + } + + } + + return uart_set_options(&sport->port, co, baud, parity, bits, flow); +} + +static struct uart_driver netx_reg; +static struct console netx_console = { + .name = "ttyNX", + .write = netx_console_write, + .device = uart_console_device, + .setup = netx_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &netx_reg, +}; + +static int __init netx_console_init(void) +{ + register_console(&netx_console); + return 0; +} +console_initcall(netx_console_init); + +#define NETX_CONSOLE &netx_console +#else +#define NETX_CONSOLE NULL +#endif + +static struct uart_driver netx_reg = { + .owner = THIS_MODULE, + .driver_name = DRIVER_NAME, + .dev_name = "ttyNX", + .major = SERIAL_NX_MAJOR, + .minor = MINOR_START, + .nr = ARRAY_SIZE(netx_ports), + .cons = NETX_CONSOLE, +}; + +static int serial_netx_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct netx_port *sport = platform_get_drvdata(pdev); + + if (sport) + uart_suspend_port(&netx_reg, &sport->port); + + return 0; +} + +static int serial_netx_resume(struct platform_device *pdev) +{ + struct netx_port *sport = platform_get_drvdata(pdev); + + if (sport) + uart_resume_port(&netx_reg, &sport->port); + + return 0; +} + +static int serial_netx_probe(struct platform_device *pdev) +{ + struct uart_port *port = &netx_ports[pdev->id].port; + + dev_info(&pdev->dev, "initialising\n"); + + port->dev = &pdev->dev; + + writel(1, port->membase + UART_RXFIFO_IRQLEVEL); + uart_add_one_port(&netx_reg, &netx_ports[pdev->id].port); + platform_set_drvdata(pdev, &netx_ports[pdev->id]); + + return 0; +} + +static int serial_netx_remove(struct platform_device *pdev) +{ + struct netx_port *sport = platform_get_drvdata(pdev); + + platform_set_drvdata(pdev, NULL); + + if (sport) + uart_remove_one_port(&netx_reg, &sport->port); + + return 0; +} + +static struct platform_driver serial_netx_driver = { + .probe = serial_netx_probe, + .remove = serial_netx_remove, + + .suspend = serial_netx_suspend, + .resume = serial_netx_resume, + + .driver = { + .name = DRIVER_NAME, + }, +}; + +static int __init netx_serial_init(void) +{ + int ret; + + printk(KERN_INFO "Serial: NetX driver\n"); + + ret = uart_register_driver(&netx_reg); + if (ret) + return ret; + + ret = platform_driver_register(&serial_netx_driver); + if (ret != 0) + uart_unregister_driver(&netx_reg); + + return 0; +} + +static void __exit netx_serial_exit(void) +{ + platform_driver_unregister(&serial_netx_driver); + uart_unregister_driver(&netx_reg); +} + +module_init(netx_serial_init); +module_exit(netx_serial_exit); + +MODULE_AUTHOR("Sascha Hauer"); +MODULE_DESCRIPTION("NetX serial port driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/serial/pxa.c b/drivers/serial/pxa.c index 77d4568ccc3..ae364956854 100644 --- a/drivers/serial/pxa.c +++ b/drivers/serial/pxa.c @@ -269,7 +269,6 @@ static unsigned int serial_pxa_get_mctrl(struct uart_port *port) unsigned char status; unsigned int ret; -return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; status = serial_in(up, UART_MSR); ret = 0; |