diff options
Diffstat (limited to 'include/asm-arm/arch-iop13xx')
| -rw-r--r-- | include/asm-arm/arch-iop13xx/adma.h | 537 | ||||
| -rw-r--r-- | include/asm-arm/arch-iop13xx/debug-macro.S | 26 | ||||
| -rw-r--r-- | include/asm-arm/arch-iop13xx/dma.h | 3 | ||||
| -rw-r--r-- | include/asm-arm/arch-iop13xx/entry-macro.S | 45 | ||||
| -rw-r--r-- | include/asm-arm/arch-iop13xx/hardware.h | 28 | ||||
| -rw-r--r-- | include/asm-arm/arch-iop13xx/io.h | 41 | ||||
| -rw-r--r-- | include/asm-arm/arch-iop13xx/iop13xx.h | 526 | ||||
| -rw-r--r-- | include/asm-arm/arch-iop13xx/iq81340.h | 28 | ||||
| -rw-r--r-- | include/asm-arm/arch-iop13xx/irqs.h | 196 | ||||
| -rw-r--r-- | include/asm-arm/arch-iop13xx/memory.h | 64 | ||||
| -rw-r--r-- | include/asm-arm/arch-iop13xx/msi.h | 11 | ||||
| -rw-r--r-- | include/asm-arm/arch-iop13xx/pci.h | 57 | ||||
| -rw-r--r-- | include/asm-arm/arch-iop13xx/system.h | 27 | ||||
| -rw-r--r-- | include/asm-arm/arch-iop13xx/time.h | 107 | ||||
| -rw-r--r-- | include/asm-arm/arch-iop13xx/timex.h | 3 | ||||
| -rw-r--r-- | include/asm-arm/arch-iop13xx/uncompress.h | 23 | ||||
| -rw-r--r-- | include/asm-arm/arch-iop13xx/vmalloc.h | 4 |
17 files changed, 0 insertions, 1726 deletions
diff --git a/include/asm-arm/arch-iop13xx/adma.h b/include/asm-arm/arch-iop13xx/adma.h deleted file mode 100644 index ef4f5da2029..00000000000 --- a/include/asm-arm/arch-iop13xx/adma.h +++ /dev/null @@ -1,537 +0,0 @@ -/* - * Copyright(c) 2006, Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. - * - */ -#ifndef _ADMA_H -#define _ADMA_H -#include <linux/types.h> -#include <linux/io.h> -#include <asm/hardware.h> -#include <asm/hardware/iop_adma.h> - -#define ADMA_ACCR(chan) (chan->mmr_base + 0x0) -#define ADMA_ACSR(chan) (chan->mmr_base + 0x4) -#define ADMA_ADAR(chan) (chan->mmr_base + 0x8) -#define ADMA_IIPCR(chan) (chan->mmr_base + 0x18) -#define ADMA_IIPAR(chan) (chan->mmr_base + 0x1c) -#define ADMA_IIPUAR(chan) (chan->mmr_base + 0x20) -#define ADMA_ANDAR(chan) (chan->mmr_base + 0x24) -#define ADMA_ADCR(chan) (chan->mmr_base + 0x28) -#define ADMA_CARMD(chan) (chan->mmr_base + 0x2c) -#define ADMA_ABCR(chan) (chan->mmr_base + 0x30) -#define ADMA_DLADR(chan) (chan->mmr_base + 0x34) -#define ADMA_DUADR(chan) (chan->mmr_base + 0x38) -#define ADMA_SLAR(src, chan) (chan->mmr_base + (0x3c + (src << 3))) -#define ADMA_SUAR(src, chan) (chan->mmr_base + (0x40 + (src << 3))) - -struct iop13xx_adma_src { - u32 src_addr; - union { - u32 upper_src_addr; - struct { - unsigned int pq_upper_src_addr:24; - unsigned int pq_dmlt:8; - }; - }; -}; - -struct iop13xx_adma_desc_ctrl { - unsigned int int_en:1; - unsigned int xfer_dir:2; - unsigned int src_select:4; - unsigned int zero_result:1; - unsigned int block_fill_en:1; - unsigned int crc_gen_en:1; - unsigned int crc_xfer_dis:1; - unsigned int crc_seed_fetch_dis:1; - unsigned int status_write_back_en:1; - unsigned int endian_swap_en:1; - unsigned int reserved0:2; - unsigned int pq_update_xfer_en:1; - unsigned int dual_xor_en:1; - unsigned int pq_xfer_en:1; - unsigned int p_xfer_dis:1; - unsigned int reserved1:10; - unsigned int relax_order_en:1; - unsigned int no_snoop_en:1; -}; - -struct iop13xx_adma_byte_count { - unsigned int byte_count:24; - unsigned int host_if:3; - unsigned int reserved:2; - unsigned int zero_result_err_q:1; - unsigned int zero_result_err:1; - unsigned int tx_complete:1; -}; - -struct iop13xx_adma_desc_hw { - u32 next_desc; - union { - u32 desc_ctrl; - struct iop13xx_adma_desc_ctrl desc_ctrl_field; - }; - union { - u32 crc_addr; - u32 block_fill_data; - u32 q_dest_addr; - }; - union { - u32 byte_count; - struct iop13xx_adma_byte_count byte_count_field; - }; - union { - u32 dest_addr; - u32 p_dest_addr; - }; - union { - u32 upper_dest_addr; - u32 pq_upper_dest_addr; - }; - struct iop13xx_adma_src src[1]; -}; - -struct iop13xx_adma_desc_dual_xor { - u32 next_desc; - u32 desc_ctrl; - u32 reserved; - u32 byte_count; - u32 h_dest_addr; - u32 h_upper_dest_addr; - u32 src0_addr; - u32 upper_src0_addr; - u32 src1_addr; - u32 upper_src1_addr; - u32 h_src_addr; - u32 h_upper_src_addr; - u32 d_src_addr; - u32 d_upper_src_addr; - u32 d_dest_addr; - u32 d_upper_dest_addr; -}; - -struct iop13xx_adma_desc_pq_update { - u32 next_desc; - u32 desc_ctrl; - u32 reserved; - u32 byte_count; - u32 p_dest_addr; - u32 p_upper_dest_addr; - u32 src0_addr; - u32 upper_src0_addr; - u32 src1_addr; - u32 upper_src1_addr; - u32 p_src_addr; - u32 p_upper_src_addr; - u32 q_src_addr; - struct { - unsigned int q_upper_src_addr:24; - unsigned int q_dmlt:8; - }; - u32 q_dest_addr; - u32 q_upper_dest_addr; -}; - -static inline int iop_adma_get_max_xor(void) -{ - return 16; -} - -static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan) -{ - return __raw_readl(ADMA_ADAR(chan)); -} - -static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan, - u32 next_desc_addr) -{ - __raw_writel(next_desc_addr, ADMA_ANDAR(chan)); -} - -#define ADMA_STATUS_BUSY (1 << 13) - -static inline char iop_chan_is_busy(struct iop_adma_chan *chan) -{ - if (__raw_readl(ADMA_ACSR(chan)) & - ADMA_STATUS_BUSY) - return 1; - else - return 0; -} - -static inline int -iop_chan_get_desc_align(struct iop_adma_chan *chan, int num_slots) -{ - return 1; -} -#define iop_desc_is_aligned(x, y) 1 - -static inline int -iop_chan_memcpy_slot_count(size_t len, int *slots_per_op) -{ - *slots_per_op = 1; - return 1; -} - -#define iop_chan_interrupt_slot_count(s, c) iop_chan_memcpy_slot_count(0, s) - -static inline int -iop_chan_memset_slot_count(size_t len, int *slots_per_op) -{ - *slots_per_op = 1; - return 1; -} - -static inline int -iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op) -{ - static const char slot_count_table[] = { 1, 2, 2, 2, - 2, 3, 3, 3, - 3, 4, 4, 4, - 4, 5, 5, 5, - }; - *slots_per_op = slot_count_table[src_cnt - 1]; - return *slots_per_op; -} - -#define ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024) -#define IOP_ADMA_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT -#define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT -#define IOP_ADMA_XOR_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT -#define iop_chan_zero_sum_slot_count(l, s, o) iop_chan_xor_slot_count(l, s, o) - -static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc, - struct iop_adma_chan *chan) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - return hw_desc->dest_addr; -} - -static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc, - struct iop_adma_chan *chan) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - return hw_desc->byte_count_field.byte_count; -} - -static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc, - struct iop_adma_chan *chan, - int src_idx) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - return hw_desc->src[src_idx].src_addr; -} - -static inline u32 iop_desc_get_src_count(struct iop_adma_desc_slot *desc, - struct iop_adma_chan *chan) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - return hw_desc->desc_ctrl_field.src_select + 1; -} - -static inline void -iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - union { - u32 value; - struct iop13xx_adma_desc_ctrl field; - } u_desc_ctrl; - - u_desc_ctrl.value = 0; - u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ - u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; - hw_desc->desc_ctrl = u_desc_ctrl.value; - hw_desc->crc_addr = 0; -} - -static inline void -iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - union { - u32 value; - struct iop13xx_adma_desc_ctrl field; - } u_desc_ctrl; - - u_desc_ctrl.value = 0; - u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ - u_desc_ctrl.field.block_fill_en = 1; - u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; - hw_desc->desc_ctrl = u_desc_ctrl.value; - hw_desc->crc_addr = 0; -} - -/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */ -static inline void -iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, - unsigned long flags) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - union { - u32 value; - struct iop13xx_adma_desc_ctrl field; - } u_desc_ctrl; - - u_desc_ctrl.value = 0; - u_desc_ctrl.field.src_select = src_cnt - 1; - u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ - u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; - hw_desc->desc_ctrl = u_desc_ctrl.value; - hw_desc->crc_addr = 0; - -} -#define iop_desc_init_null_xor(d, s, i) iop_desc_init_xor(d, s, i) - -/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */ -static inline int -iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, - unsigned long flags) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - union { - u32 value; - struct iop13xx_adma_desc_ctrl field; - } u_desc_ctrl; - - u_desc_ctrl.value = 0; - u_desc_ctrl.field.src_select = src_cnt - 1; - u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ - u_desc_ctrl.field.zero_result = 1; - u_desc_ctrl.field.status_write_back_en = 1; - u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; - hw_desc->desc_ctrl = u_desc_ctrl.value; - hw_desc->crc_addr = 0; - - return 1; -} - -static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc, - struct iop_adma_chan *chan, - u32 byte_count) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - hw_desc->byte_count = byte_count; -} - -static inline void -iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len) -{ - int slots_per_op = desc->slots_per_op; - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter; - int i = 0; - - if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) { - hw_desc->byte_count = len; - } else { - do { - iter = iop_hw_desc_slot_idx(hw_desc, i); - iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; - len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; - i += slots_per_op; - } while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT); - - if (len) { - iter = iop_hw_desc_slot_idx(hw_desc, i); - iter->byte_count = len; - } - } -} - - -static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc, - struct iop_adma_chan *chan, - dma_addr_t addr) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - hw_desc->dest_addr = addr; - hw_desc->upper_dest_addr = 0; -} - -static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc, - dma_addr_t addr) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - hw_desc->src[0].src_addr = addr; - hw_desc->src[0].upper_src_addr = 0; -} - -static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc, - int src_idx, dma_addr_t addr) -{ - int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter; - int i = 0; - - do { - iter = iop_hw_desc_slot_idx(hw_desc, i); - iter->src[src_idx].src_addr = addr; - iter->src[src_idx].upper_src_addr = 0; - slot_cnt -= slots_per_op; - if (slot_cnt) { - i += slots_per_op; - addr += IOP_ADMA_XOR_MAX_BYTE_COUNT; - } - } while (slot_cnt); -} - -static inline void -iop_desc_init_interrupt(struct iop_adma_desc_slot *desc, - struct iop_adma_chan *chan) -{ - iop_desc_init_memcpy(desc, 1); - iop_desc_set_byte_count(desc, chan, 0); - iop_desc_set_dest_addr(desc, chan, 0); - iop_desc_set_memcpy_src_addr(desc, 0); -} - -#define iop_desc_set_zero_sum_src_addr iop_desc_set_xor_src_addr - -static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc, - u32 next_desc_addr) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - BUG_ON(hw_desc->next_desc); - hw_desc->next_desc = next_desc_addr; -} - -static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - return hw_desc->next_desc; -} - -static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - hw_desc->next_desc = 0; -} - -static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc, - u32 val) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - hw_desc->block_fill_data = val; -} - -static inline int iop_desc_get_zero_result(struct iop_adma_desc_slot *desc) -{ - struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; - struct iop13xx_adma_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field; - struct iop13xx_adma_byte_count byte_count = hw_desc->byte_count_field; - - BUG_ON(!(byte_count.tx_complete && desc_ctrl.zero_result)); - - if (desc_ctrl.pq_xfer_en) - return byte_count.zero_result_err_q; - else - return byte_count.zero_result_err; -} - -static inline void iop_chan_append(struct iop_adma_chan *chan) -{ - u32 adma_accr; - - adma_accr = __raw_readl(ADMA_ACCR(chan)); - adma_accr |= 0x2; - __raw_writel(adma_accr, ADMA_ACCR(chan)); -} - -static inline u32 iop_chan_get_status(struct iop_adma_chan *chan) -{ - return __raw_readl(ADMA_ACSR(chan)); -} - -static inline void iop_chan_disable(struct iop_adma_chan *chan) -{ - u32 adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan)); - adma_chan_ctrl &= ~0x1; - __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan)); -} - -static inline void iop_chan_enable(struct iop_adma_chan *chan) -{ - u32 adma_chan_ctrl; - - adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan)); - adma_chan_ctrl |= 0x1; - __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan)); -} - -static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan) -{ - u32 status = __raw_readl(ADMA_ACSR(chan)); - status &= (1 << 12); - __raw_writel(status, ADMA_ACSR(chan)); -} - -static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan) -{ - u32 status = __raw_readl(ADMA_ACSR(chan)); - status &= (1 << 11); - __raw_writel(status, ADMA_ACSR(chan)); -} - -static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan) -{ - u32 status = __raw_readl(ADMA_ACSR(chan)); - status &= (1 << 9) | (1 << 5) | (1 << 4) | (1 << 3); - __raw_writel(status, ADMA_ACSR(chan)); -} - -static inline int -iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan) -{ - return test_bit(9, &status); -} - -static inline int -iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan) -{ - return test_bit(5, &status); -} - -static inline int -iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan) -{ - return test_bit(4, &status); -} - -static inline int -iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan) -{ - return test_bit(3, &status); -} - -static inline int -iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan) -{ - return 0; -} - -static inline int -iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan) -{ - return 0; -} - -static inline int -iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan) -{ - return 0; -} - -#endif /* _ADMA_H */ diff --git a/include/asm-arm/arch-iop13xx/debug-macro.S b/include/asm-arm/arch-iop13xx/debug-macro.S deleted file mode 100644 index 788b4e386c1..00000000000 --- a/include/asm-arm/arch-iop13xx/debug-macro.S +++ /dev/null @@ -1,26 +0,0 @@ -/* - * include/asm-arm/arch-iop13xx/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - - .macro addruart, rx - mrc p15, 0, \rx, c1, c0 - tst \rx, #1 @ mmu enabled? - moveq \rx, #0xff000000 @ physical - orreq \rx, \rx, #0x00d80000 - movne \rx, #0xfe000000 @ virtual - orrne \rx, \rx, #0x00e80000 - orr \rx, \rx, #0x00002300 - orr \rx, \rx, #0x00000040 - .endm - -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> diff --git a/include/asm-arm/arch-iop13xx/dma.h b/include/asm-arm/arch-iop13xx/dma.h deleted file mode 100644 index d79846fbb39..00000000000 --- a/include/asm-arm/arch-iop13xx/dma.h +++ /dev/null @@ -1,3 +0,0 @@ -#ifndef _IOP13XX_DMA_H -#define _IOP13XX_DMA_H -#endif diff --git a/include/asm-arm/arch-iop13xx/entry-macro.S b/include/asm-arm/arch-iop13xx/entry-macro.S deleted file mode 100644 index a624a7870c6..00000000000 --- a/include/asm-arm/arch-iop13xx/entry-macro.S +++ /dev/null @@ -1,45 +0,0 @@ -/* - * iop13xx low level irq macros - * Copyright (c) 2005-2006, Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 59 Temple - * Place - Suite 330, Boston, MA 02111-1307 USA. - * - */ - .macro disable_fiq - .endm - - .macro get_irqnr_preamble, base, tmp - mrc p15, 0, \tmp, c15, c1, 0 - orr \tmp, \tmp, #(1 << 6) - mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access - .endm - - /* - * Note: a 1-cycle window exists where iintvec will return the value - * of iintbase, so we explicitly check for "bad zeros" - */ - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - mrc p6, 0, \irqnr, c3, c2, 0 @ Read IINTVEC - cmp \irqnr, #0 - mrceq p6, 0, \irqnr, c3, c2, 0 @ Re-read on potentially bad zero - adds \irqstat, \irqnr, #1 @ Check for 0xffffffff - movne \irqnr, \irqnr, lsr #2 @ Convert to irqnr - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - mrc p15, 0, \tmp1, c15, c1, 0 - ands \tmp2, \tmp1, #(1 << 6) - bicne \tmp1, \tmp1, #(1 << 6) - mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access - .endm diff --git a/include/asm-arm/arch-iop13xx/hardware.h b/include/asm-arm/arch-iop13xx/hardware.h deleted file mode 100644 index 8e1d5628984..00000000000 --- a/include/asm-arm/arch-iop13xx/hardware.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H -#include <asm/types.h> - -#define pcibios_assign_all_busses() 1 - -#ifndef __ASSEMBLY__ -extern unsigned long iop13xx_pcibios_min_io; -extern unsigned long iop13xx_pcibios_min_mem; -extern u16 iop13xx_dev_id(void); -extern void iop13xx_set_atu_mmr_bases(void); -#endif - -#define PCIBIOS_MIN_IO (iop13xx_pcibios_min_io) -#define PCIBIOS_MIN_MEM (iop13xx_pcibios_min_mem) - -/* - * Generic chipset bits - * - */ -#include "iop13xx.h" - -/* - * Board specific bits - */ -#include "iq81340.h" - -#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-iop13xx/io.h b/include/asm-arm/arch-iop13xx/io.h deleted file mode 100644 index a6e0f9e6ddc..00000000000 --- a/include/asm-arm/arch-iop13xx/io.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * iop13xx custom ioremap implementation - * Copyright (c) 2005-2006, Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 59 Temple - * Place - Suite 330, Boston, MA 02111-1307 USA. - * - */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xffffffff - -#define __io(a) __iop13xx_io(a) -#define __mem_pci(a) (a) -#define __mem_isa(a) (a) - -extern void __iomem * __iop13xx_io(unsigned long io_addr); -extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size, - unsigned int mtype); -extern void __iop13xx_iounmap(void __iomem *addr); - -extern u32 iop13xx_atue_mem_base; -extern u32 iop13xx_atux_mem_base; -extern size_t iop13xx_atue_mem_size; -extern size_t iop13xx_atux_mem_size; - -#define __arch_ioremap(a, s, f) __iop13xx_ioremap(a, s, f) -#define __arch_iounmap(a) __iop13xx_iounmap(a) - -#endif diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h deleted file mode 100644 index 52b7fab7ef6..00000000000 --- a/include/asm-arm/arch-iop13xx/iop13xx.h +++ /dev/null @@ -1,526 +0,0 @@ -#ifndef _IOP13XX_HW_H_ -#define _IOP13XX_HW_H_ - -#ifndef __ASSEMBLY__ -/* The ATU offsets can change based on the strapping */ -extern u32 iop13xx_atux_pmmr_offset; -extern u32 iop13xx_atue_pmmr_offset; -void iop13xx_init_irq(void); -void iop13xx_map_io(void); -void iop13xx_platform_init(void); -void iop13xx_add_tpmi_devices(void); -void iop13xx_init_irq(void); - -/* CPUID CP6 R0 Page 0 */ -static inline int iop13xx_cpu_id(void) -{ - int id; - asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id)); - return id; -} - -/* WDTCR CP6 R7 Page 9 */ -static inline u32 read_wdtcr(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val)); - return val; -} -static inline void write_wdtcr(u32 val) -{ - asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val)); -} - -/* WDTSR CP6 R8 Page 9 */ -static inline u32 read_wdtsr(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val)); - return val; -} -static inline void write_wdtsr(u32 val) -{ - asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val)); -} - -/* RCSR - Reset Cause Status Register */ -static inline u32 read_rcsr(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c0, c1, 0":"=r" (val)); - return val; -} - -extern unsigned long get_iop_tick_rate(void); -#endif - -/* - * IOP13XX I/O and Mem space regions for PCI autoconfiguration - */ -#define IOP13XX_MAX_RAM_SIZE 0x80000000UL /* 2GB */ -#define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE - -/* PCI MAP - * bus range cpu phys cpu virt note - * 0x0000.0000 + 2GB (n/a) (n/a) inbound, 1:1 mapping with Physical RAM - * 0x8000.0000 + 928M 0x1.8000.0000 (ioremap) PCIX outbound memory window - * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window - * - * IO MAP - * 0x1000 + 64K 0x0.fffb.1000 0xfec6.1000 PCIX outbound i/o window - * 0x1000 + 64K 0x0.fffd.1000 0xfed7.1000 PCIE outbound i/o window - */ -#define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL -#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL -#define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL -#define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */ -#define IOP13XX_PCIX_IO_BUS_OFFSET 0x1000UL -#define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\ - IOP13XX_PCIX_IO_WINDOW_SIZE - 1) -#define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\ - IOP13XX_PCIX_IO_WINDOW_SIZE - 1) -#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ - (IOP13XX_PCIX_LOWER_IO_PA\ - - IOP13XX_PCIX_LOWER_IO_VA)) - -#define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL -#define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL -#define IOP13XX_PCIX_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET) -#define IOP13XX_PCIX_LOWER_MEM_PA (IOP13XX_PCIX_MEM_PHYS_OFFSET +\ - IOP13XX_PCIX_LOWER_MEM_BA) -#define IOP13XX_PCIX_UPPER_MEM_PA (IOP13XX_PCIX_LOWER_MEM_PA +\ - IOP13XX_PCIX_MEM_WINDOW_SIZE - 1) -#define IOP13XX_PCIX_UPPER_MEM_BA (IOP13XX_PCIX_LOWER_MEM_BA +\ - IOP13XX_PCIX_MEM_WINDOW_SIZE - 1) - -#define IOP13XX_PCIX_MEM_COOKIE 0x80000000UL -#define IOP13XX_PCIX_LOWER_MEM_RA IOP13XX_PCIX_MEM_COOKIE -#define IOP13XX_PCIX_UPPER_MEM_RA (IOP13XX_PCIX_LOWER_MEM_RA +\ - IOP13XX_PCIX_MEM_WINDOW_SIZE - 1) -#define IOP13XX_PCIX_MEM_OFFSET (IOP13XX_PCIX_MEM_COOKIE -\ - IOP13XX_PCIX_LOWER_MEM_BA) - -/* PCI-E ranges */ -#define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL -#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL -#define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL -#define IOP13XX_PCIE_LOWER_IO_BA 0x0UL /* OIOTVR */ -#define IOP13XX_PCIE_IO_BUS_OFFSET 0x1000UL -#define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\ - IOP13XX_PCIE_IO_WINDOW_SIZE - 1) -#define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\ - IOP13XX_PCIE_IO_WINDOW_SIZE - 1) -#define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\ - IOP13XX_PCIE_IO_WINDOW_SIZE - 1) -#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ - (IOP13XX_PCIE_LOWER_IO_PA\ - - IOP13XX_PCIE_LOWER_IO_VA)) - -#define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL -#define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL -#define IOP13XX_PCIE_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET) -#define IOP13XX_PCIE_LOWER_MEM_PA (IOP13XX_PCIE_MEM_PHYS_OFFSET +\ - IOP13XX_PCIE_LOWER_MEM_BA) -#define IOP13XX_PCIE_UPPER_MEM_PA (IOP13XX_PCIE_LOWER_MEM_PA +\ - IOP13XX_PCIE_MEM_WINDOW_SIZE - 1) -#define IOP13XX_PCIE_UPPER_MEM_BA (IOP13XX_PCIE_LOWER_MEM_BA +\ - IOP13XX_PCIE_MEM_WINDOW_SIZE - 1) - -/* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */ -#define IOP13XX_PCIE_MEM_COOKIE 0xc0000000UL -#define IOP13XX_PCIE_LOWER_MEM_RA IOP13XX_PCIE_MEM_COOKIE -#define IOP13XX_PCIE_UPPER_MEM_RA (IOP13XX_PCIE_LOWER_MEM_RA +\ - IOP13XX_PCIE_MEM_WINDOW_SIZE - 1) -#define IOP13XX_PCIE_MEM_OFFSET (IOP13XX_PCIE_MEM_COOKIE -\ - IOP13XX_PCIE_LOWER_MEM_BA) - -/* PBI Ranges */ -#define IOP13XX_PBI_LOWER_MEM_PA 0xf0000000UL -#define IOP13XX_PBI_MEM_WINDOW_SIZE 0x04000000UL -#define IOP13XX_PBI_MEM_COOKIE 0xfa000000UL -#define IOP13XX_PBI_LOWER_MEM_RA IOP13XX_PBI_MEM_COOKIE -#define IOP13XX_PBI_UPPER_MEM_RA (IOP13XX_PBI_LOWER_MEM_RA +\ - IOP13XX_PBI_MEM_WINDOW_SIZE - 1) - -/* - * IOP13XX chipset registers - */ -#define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */ -#define IOP13XX_PMMR_VIRT_MEM_BASE 0xfee80000UL /* PMMR phys. address */ -#define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000 -#define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\ - IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) -#define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\ - IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) -#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (u32) ((u32) addr +\ - (IOP13XX_PMMR_PHYS_MEM_BASE\ - - IOP13XX_PMMR_VIRT_MEM_BASE)) -#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ - (IOP13XX_PMMR_PHYS_MEM_BASE\ - - IOP13XX_PMMR_VIRT_MEM_BASE)) -#define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) -#define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) -#define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) -#define IOP13XX_REG_ADDR32_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg)) -#define IOP13XX_REG_ADDR16_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg)) -#define IOP13XX_REG_ADDR8_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg)) -#define IOP13XX_PMMR_SIZE 0x00080000 - -/*=================== Defines for Platform Devices =====================*/ -#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300) -#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340) -#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300) -#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340) - -#define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500) -#define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520) -#define IOP13XX_I2C2_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540) -#define IOP13XX_I2C0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500) -#define IOP13XX_I2C1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520) -#define IOP13XX_I2C2_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540) - -/* ATU selection flags */ -/* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */ -#define IOP13XX_INIT_ATU_DEFAULT (0) -#define IOP13XX_INIT_ATU_ATUX (1 << 0) -#define IOP13XX_INIT_ATU_ATUE (1 << 1) -#define IOP13XX_INIT_ATU_NONE (1 << 2) - -/* UART selection flags */ -/* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */ -#define IOP13XX_INIT_UART_DEFAULT (0) -#define IOP13XX_INIT_UART_0 (1 << 0) -#define IOP13XX_INIT_UART_1 (1 << 1) - -/* I2C selection flags */ -/* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */ -#define IOP13XX_INIT_I2C_DEFAULT (0) -#define IOP13XX_INIT_I2C_0 (1 << 0) -#define IOP13XX_INIT_I2C_1 (1 << 1) -#define IOP13XX_INIT_I2C_2 (1 << 2) - -/* ADMA selection flags */ -/* INIT_ADMA_DEFAULT = Rely on CONFIG_IOP13XX_ADMA* */ -#define IOP13XX_INIT_ADMA_DEFAULT (0) -#define IOP13XX_INIT_ADMA_0 (1 << 0) -#define IOP13XX_INIT_ADMA_1 (1 << 1) -#define IOP13XX_INIT_ADMA_2 (1 << 2) - -/* Platform devices */ -#define IQ81340_NUM_UART 2 -#define IQ81340_NUM_I2C 3 -#define IQ81340_NUM_PHYS_MAP_FLASH 1 -#define IQ81340_NUM_ADMA 3 -#define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART + \ - IQ81340_NUM_I2C + \ - IQ81340_NUM_PHYS_MAP_FLASH + \ - IQ81340_NUM_ADMA) - -/*========================== PMMR offsets for key registers ============*/ -#define IOP13XX_ATU0_PMMR_OFFSET 0x00048000 -#define IOP13XX_ATU1_PMMR_OFFSET 0x0004c000 -#define IOP13XX_ATU2_PMMR_OFFSET 0x0004d000 -#define IOP13XX_ADMA0_PMMR_OFFSET 0x00000000 -#define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200 -#define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400 -#define IOP13XX_PBI_PMMR_OFFSET 0x00001580 -#define IOP13XX_MU_PMMR_OFFSET 0x00004000 -#define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188 -#define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188) - -#define IOP13XX_ESSR0_IFACE_MASK 0x00004000 /* Interface PCI-X / PCI-E */ -#define IOP13XX_CONTROLLER_ONLY (1 << 14) -#define IOP13XX_INTERFACE_SEL_PCIX (1 << 15) - -#define IOP13XX_PMON_PMMR_OFFSET 0x0001A000 -#define IOP13XX_PMON_BASE (IOP13XX_PMMR_VIRT_MEM_BASE +\ - IOP13XX_PMON_PMMR_OFFSET) -#define IOP13XX_PMON_PHYSBASE (IOP13XX_PMMR_PHYS_MEM_BASE +\ - IOP13XX_PMON_PMMR_OFFSET) - -#define IOP13XX_PMON_CMD0 (IOP13XX_PMON_BASE + 0x0) -#define IOP13XX_PMON_EVR0 (IOP13XX_PMON_BASE + 0x4) -#define IOP13XX_PMON_STS0 (IOP13XX_PMON_BASE + 0x8) -#define IOP13XX_PMON_DATA0 (IOP13XX_PMON_BASE + 0xC) - -#define IOP13XX_PMON_CMD3 (IOP13XX_PMON_BASE + 0x30) -#define IOP13XX_PMON_EVR3 (IOP13XX_PMON_BASE + 0x34) -#define IOP13XX_PMON_STS3 (IOP13XX_PMON_BASE + 0x38) -#define IOP13XX_PMON_DATA3 (IOP13XX_PMON_BASE + 0x3C) - -#define IOP13XX_PMON_CMD7 (IOP13XX_PMON_BASE + 0x70) -#define IOP13XX_PMON_EVR7 (IOP13XX_PMON_BASE + 0x74) -#define IOP13XX_PMON_STS7 (IOP13XX_PMON_BASE + 0x78) -#define IOP13XX_PMON_DATA7 (IOP13XX_PMON_BASE + 0x7C) - -#define IOP13XX_PMONEN (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040) -#define IOP13XX_PMONSTAT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044) - -/*================================ATU===================================*/ -#define IOP13XX_ATUX_OFFSET(ofs) IOP13XX_REG_ADDR32(\ - iop13xx_atux_pmmr_offset + (ofs)) - -#define IOP13XX_ATUX_DID IOP13XX_REG_ADDR16(\ - iop13xx_atux_pmmr_offset + 0x2) - -#define IOP13XX_ATUX_ATUCMD IOP13XX_REG_ADDR16(\ - iop13xx_atux_pmmr_offset + 0x4) -#define IOP13XX_ATUX_ATUSR IOP13XX_REG_ADDR16(\ - iop13xx_atux_pmmr_offset + 0x6) - -#define IOP13XX_ATUX_IABAR0 IOP13XX_ATUX_OFFSET(0x10) -#define IOP13XX_ATUX_IAUBAR0 IOP13XX_ATUX_OFFSET(0x14) -#define IOP13XX_ATUX_IABAR1 IOP13XX_ATUX_OFFSET(0x18) -#define IOP13XX_ATUX_IAUBAR1 IOP13XX_ATUX_OFFSET(0x1c) -#define IOP13XX_ATUX_IABAR2 IOP13XX_ATUX_OFFSET(0x20) -#define IOP13XX_ATUX_IAUBAR2 IOP13XX_ATUX_OFFSET(0x24) -#define IOP13XX_ATUX_IALR0 IOP13XX_ATUX_OFFSET(0x40) -#define IOP13XX_ATUX_IATVR0 IOP13XX_ATUX_OFFSET(0x44) -#define IOP13XX_ATUX_IAUTVR0 IOP13XX_ATUX_OFFSET(0x48) -#define IOP13XX_ATUX_IALR1 IOP13XX_ATUX_OFFSET(0x4c) -#define IOP13XX_ATUX_IATVR1 IOP13XX_ATUX_OFFSET(0x50) -#define IOP13XX_ATUX_IAUTVR1 IOP13XX_ATUX_OFFSET(0x54) -#define IOP13XX_ATUX_IALR2 IOP13XX_ATUX_OFFSET(0x58) -#define IOP13XX_ATUX_IATVR2 IOP13XX_ATUX_OFFSET(0x5c) -#define IOP13XX_ATUX_IAUTVR2 IOP13XX_ATUX_OFFSET(0x60) -#define IOP13XX_ATUX_ATUCR IOP13XX_ATUX_OFFSET(0x70) -#define IOP13XX_ATUX_PCSR IOP13XX_ATUX_OFFSET(0x74) -#define IOP13XX_ATUX_ATUISR IOP13XX_ATUX_OFFSET(0x78) -#define IOP13XX_ATUX_PCIXSR IOP13XX_ATUX_OFFSET(0xD4) -#define IOP13XX_ATUX_IABAR3 IOP13XX_ATUX_OFFSET(0x200) -#define IOP13XX_ATUX_IAUBAR3 IOP13XX_ATUX_OFFSET(0x204) -#define IOP13XX_ATUX_IALR3 IOP13XX_ATUX_OFFSET(0x208) -#define IOP13XX_ATUX_IATVR3 IOP13XX_ATUX_OFFSET(0x20c) -#define IOP13XX_ATUX_IAUTVR3 IOP13XX_ATUX_OFFSET(0x210) - -#define IOP13XX_ATUX_OIOBAR IOP13XX_ATUX_OFFSET(0x300) -#define IOP13XX_ATUX_OIOWTVR IOP13XX_ATUX_OFFSET(0x304) -#define IOP13XX_ATUX_OUMBAR0 IOP13XX_ATUX_OFFSET(0x308) -#define IOP13XX_ATUX_OUMWTVR0 IOP13XX_ATUX_OFFSET(0x30c) -#define IOP13XX_ATUX_OUMBAR1 IOP13XX_ATUX_OFFSET(0x310) -#define IOP13XX_ATUX_OUMWTVR1 IOP13XX_ATUX_OFFSET(0x314) -#define IOP13XX_ATUX_OUMBAR2 IOP13XX_ATUX_OFFSET(0x318) -#define IOP13XX_ATUX_OUMWTVR2 IOP13XX_ATUX_OFFSET(0x31c) -#define IOP13XX_ATUX_OUMBAR3 IOP13XX_ATUX_OFFSET(0x320) -#define IOP13XX_ATUX_OUMWTVR3 IOP13XX_ATUX_OFFSET(0x324) -#define IOP13XX_ATUX_OUDMABAR IOP13XX_ATUX_OFFSET(0x328) -#define IOP13XX_ATUX_OUMSIBAR IOP13XX_ATUX_OFFSET(0x32c) -#define IOP13XX_ATUX_OCCAR IOP13XX_ATUX_OFFSET(0x330) -#define IOP13XX_ATUX_OCCDR IOP13XX_ATUX_OFFSET(0x334) - -#define IOP13XX_ATUX_ATUCR_OUT_EN (1 << 1) -#define IOP13XX_ATUX_PCSR_CENTRAL_RES (1 << 25) -#define IOP13XX_ATUX_PCSR_P_RSTOUT (1 << 21) -#define IOP13XX_ATUX_PCSR_OUT_Q_BUSY (1 << 15) -#define IOP13XX_ATUX_PCSR_IN_Q_BUSY (1 << 14) -#define IOP13XX_ATUX_PCSR_FREQ_OFFSET (16) - -#define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18) -#define IOP13XX_ATUX_STAT_VPD_ADDR (1 << 17) -#define IOP13XX_ATUX_STAT_INT_PAR_ERR (1 << 16) -#define IOP13XX_ATUX_STAT_CFG_WRITE (1 << 15) -#define IOP13XX_ATUX_STAT_ERR_COR (1 << 14) -#define IOP13XX_ATUX_STAT_TX_SCEM (1 << 13) -#define IOP13XX_ATUX_STAT_REC_SCEM (1 << 12) -#define IOP13XX_ATUX_STAT_POWER_TRAN (1 << 11) -#define IOP13XX_ATUX_STAT_TX_SERR (1 << 10) -#define IOP13XX_ATUX_STAT_DET_PAR_ERR (1 << 9 ) -#define IOP13XX_ATUX_STAT_BIST (1 << 8 ) -#define IOP13XX_ATUX_STAT_INT_REC_MABORT (1 << 7 ) -#define IOP13XX_ATUX_STAT_REC_SERR (1 << 4 ) -#define IOP13XX_ATUX_STAT_EXT_REC_MABORT (1 << 3 ) -#define IOP13XX_ATUX_STAT_EXT_REC_TABORT (1 << 2 ) -#define IOP13XX_ATUX_STAT_EXT_SIG_TABORT (1 << 1 ) -#define IOP13XX_ATUX_STAT_MASTER_DATA_PAR (1 << 0 ) - -#define IOP13XX_ATUX_PCIXSR_BUS_NUM (8) -#define IOP13XX_ATUX_PCIXSR_DEV_NUM (3) -#define IOP13XX_ATUX_PCIXSR_FUNC_NUM (0) - -#define IOP13XX_ATUX_IALR_DISABLE 0x00000001 -#define IOP13XX_ATUX_OUMBAR_ENABLE 0x80000000 - -#define IOP13XX_ATUE_OFFSET(ofs) IOP13XX_REG_ADDR32(\ - iop13xx_atue_pmmr_offset + (ofs)) - -#define IOP13XX_ATUE_DID IOP13XX_REG_ADDR16(\ - iop13xx_atue_pmmr_offset + 0x2) -#define IOP13XX_ATUE_ATUCMD IOP13XX_REG_ADDR16(\ - iop13xx_atue_pmmr_offset + 0x4) -#define IOP13XX_ATUE_ATUSR IOP13XX_REG_ADDR16(\ - iop13xx_atue_pmmr_offset + 0x6) - -#define IOP13XX_ATUE_IABAR0 IOP13XX_ATUE_OFFSET(0x10) -#define IOP13XX_ATUE_IAUBAR0 IOP13XX_ATUE_OFFSET(0x14) -#define IOP13XX_ATUE_IABAR1 IOP13XX_ATUE_OFFSET(0x18) -#define IOP13XX_ATUE_IAUBAR1 IOP13XX_ATUE_OFFSET(0x1c) -#define IOP13XX_ATUE_IABAR2 IOP13XX_ATUE_OFFSET(0x20) -#define IOP13XX_ATUE_IAUBAR2 IOP13XX_ATUE_OFFSET(0x24) -#define IOP13XX_ATUE_IALR0 IOP13XX_ATUE_OFFSET(0x40) -#define IOP13XX_ATUE_IATVR0 IOP13XX_ATUE_OFFSET(0x44) -#define IOP13XX_ATUE_IAUTVR0 IOP13XX_ATUE_OFFSET(0x48) -#define IOP13XX_ATUE_IALR1 IOP13XX_ATUE_OFFSET(0x4c) -#define IOP13XX_ATUE_IATVR1 IOP13XX_ATUE_OFFSET(0x50) -#define IOP13XX_ATUE_IAUTVR1 IOP13XX_ATUE_OFFSET(0x54) -#define IOP13XX_ATUE_IALR2 IOP13XX_ATUE_OFFSET(0x58) -#define IOP13XX_ATUE_IATVR2 IOP13XX_ATUE_OFFSET(0x5c) -#define IOP13XX_ATUE_IAUTVR2 IOP13XX_ATUE_OFFSET(0x60) -#define IOP13XX_ATUE_PE_LSTS IOP13XX_REG_ADDR16(\ - iop13xx_atue_pmmr_offset + 0xe2) -#define IOP13XX_ATUE_OIOWTVR IOP13XX_ATUE_OFFSET(0x304) -#define IOP13XX_ATUE_OUMBAR0 IOP13XX_ATUE_OFFSET(0x308) -#define IOP13XX_ATUE_OUMWTVR0 IOP13XX_ATUE_OFFSET(0x30c) -#define IOP13XX_ATUE_OUMBAR1 IOP13XX_ATUE_OFFSET(0x310) -#define IOP13XX_ATUE_OUMWTVR1 IOP13XX_ATUE_OFFSET(0x314) -#define IOP13XX_ATUE_OUMBAR2 IOP13XX_ATUE_OFFSET(0x318) -#define IOP13XX_ATUE_OUMWTVR2 IOP13XX_ATUE_OFFSET(0x31c) -#define IOP13XX_ATUE_OUMBAR3 IOP13XX_ATUE_OFFSET(0x320) -#define IOP13XX_ATUE_OUMWTVR3 IOP13XX_ATUE_OFFSET(0x324) - -#define IOP13XX_ATUE_ATUCR IOP13XX_ATUE_OFFSET(0x70) -#define IOP13XX_ATUE_PCSR IOP13XX_ATUE_OFFSET(0x74) -#define IOP13XX_ATUE_ATUISR IOP13XX_ATUE_OFFSET(0x78) -#define IOP13XX_ATUE_OIOBAR IOP13XX_ATUE_OFFSET(0x300) -#define IOP13XX_ATUE_OCCAR IOP13XX_ATUE_OFFSET(0x32c) -#define IOP13XX_ATUE_OCCDR IOP13XX_ATUE_OFFSET(0x330) - -#define IOP13XX_ATUE_PIE_STS IOP13XX_ATUE_OFFSET(0x384) -#define IOP13XX_ATUE_PIE_MSK IOP13XX_ATUE_OFFSET(0x388) - -#define IOP13XX_ATUE_ATUCR_IVM (1 << 6) -#define IOP13XX_ATUE_ATUCR_OUT_EN (1 << 1) -#define IOP13XX_ATUE_OCCAR_BUS_NUM (24) -#define IOP13XX_ATUE_OCCAR_DEV_NUM (19) -#define IOP13XX_ATUE_OCCAR_FUNC_NUM (16) -#define IOP13XX_ATUE_OCCAR_EXT_REG (8) -#define IOP13XX_ATUE_OCCAR_REG (2) - -#define IOP13XX_ATUE_PCSR_BUS_NUM (24) -#define IOP13XX_ATUE_PCSR_DEV_NUM (19) -#define IOP13XX_ATUE_PCSR_FUNC_NUM (16) -#define IOP13XX_ATUE_PCSR_OUT_Q_BUSY (1 << 15) -#define IOP13XX_ATUE_PCSR_IN_Q_BUSY (1 << 14) -#define IOP13XX_ATUE_PCSR_END_POINT (1 << 13) -#define IOP13XX_ATUE_PCSR_LLRB_BUSY (1 << 12) - -#define IOP13XX_ATUE_PCSR_BUS_NUM_MASK (0xff) -#define IOP13XX_ATUE_PCSR_DEV_NUM_MASK (0x1f) -#define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7) - -#define IOP13XX_ATUE_PCSR_CORE_RESET (8) -#define IOP13XX_ATUE_PCSR_FUNC_NUM (16) - -#define IOP13XX_ATUE_LSTS_TRAINING (1 << 11) -#define IOP13XX_ATUE_STAT_SLOT_PWR_MSG (1 << 28) -#define IOP13XX_ATUE_STAT_PME (1 << 27) -#define IOP13XX_ATUE_STAT_HOT_PLUG_MSG (1 << 26) -#define IOP13XX_ATUE_STAT_IVM (1 << 25) -#define IOP13XX_ATUE_STAT_BIST (1 << 24) -#define IOP13XX_ATUE_STAT_CFG_WRITE (1 << 18) -#define IOP13XX_ATUE_STAT_VPD_ADDR (1 << 17) -#define IOP13XX_ATUE_STAT_POWER_TRAN (1 << 16) -#define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13) -#define IOP13XX_ATUE_STAT_ROOT_SYS_ERR (1 << 12) -#define IOP13XX_ATUE_STAT_ROOT_ERR_MSG (1 << 11) -#define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10) -#define IOP13XX_ATUE_STAT_ERR_COR (1 << 9 ) -#define IOP13XX_ATUE_STAT_ERR_UNCOR (1 << 8 ) -#define IOP13XX_ATUE_STAT_CRS (1 << 7 ) -#define IOP13XX_ATUE_STAT_LNK_DWN (1 << 6 ) -#define IOP13XX_ATUE_STAT_INT_REC_MABORT (1 << 5 ) -#define IOP13XX_ATUE_STAT_DET_PAR_ERR (1 << 4 ) -#define IOP13XX_ATUE_STAT_EXT_REC_MABORT (1 << 3 ) -#define IOP13XX_ATUE_STAT_SIG_TABORT (1 << 2 ) -#define IOP13XX_ATUE_STAT_EXT_REC_TABORT (1 << 1 ) -#define IOP13XX_ATUE_STAT_MASTER_DATA_PAR (1 << 0 ) - -#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ (1 << 31) -#define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT (1 << 30) -#define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP (1 << 29) -#define IOP13XX_ATUE_ESTAT_TX_PAR_ERR (1 << 28) -#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ (1 << 20) -#define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR (1 << 19) -#define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP (1 << 18) -#define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17) -#define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP (1 << 16) -#define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT (1 << 15) -#define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT (1 << 14) -#define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR (1 << 13) -#define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP (1 << 12) -#define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR (1 << 4 ) -#define IOP13XX_ATUE_ESTAT_TRAINING_ERR (1 << 0 ) - -#define IOP13XX_ATUE_IALR_DISABLE (0x00000001) -#define IOP13XX_ATUE_OUMBAR_ENABLE (0x80000000) -#define IOP13XX_ATU_OUMBAR_FUNC_NUM (28) -#define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7) -/*=======================================================================*/ - -/*============================MESSAGING UNIT=============================*/ -#define IOP13XX_MU_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_MU_PMMR_OFFSET +\ - (ofs)) - -#define IOP13XX_MU_IMR0 IOP13XX_MU_OFFSET(0x10) -#define IOP13XX_MU_IMR1 IOP13XX_MU_OFFSET(0x14) -#define IOP13XX_MU_OMR0 IOP13XX_MU_OFFSET(0x18) -#define IOP13XX_MU_OMR1 IOP13XX_MU_OFFSET(0x1C) -#define IOP13XX_MU_IDR IOP13XX_MU_OFFSET(0x20) -#define IOP13XX_MU_IISR IOP13XX_MU_OFFSET(0x24) -#define IOP13XX_MU_IIMR IOP13XX_MU_OFFSET(0x28) -#define IOP13XX_MU_ODR IOP13XX_MU_OFFSET(0x2C) -#define IOP13XX_MU_OISR IOP13XX_MU_OFFSET(0x30) -#define IOP13XX_MU_OIMR IOP13XX_MU_OFFSET(0x34) -#define IOP13XX_MU_IRCSR IOP13XX_MU_OFFSET(0x38) -#define IOP13XX_MU_ORCSR IOP13XX_MU_OFFSET(0x3C) -#define IOP13XX_MU_MIMR IOP13XX_MU_OFFSET(0x48) -#define IOP13XX_MU_MUCR IOP13XX_MU_OFFSET(0x50) -#define IOP13XX_MU_QBAR IOP13XX_MU_OFFSET(0x54) -#define IOP13XX_MU_MUBAR IOP13XX_MU_OFFSET(0x84) - -#define IOP13XX_MU_WINDOW_SIZE (8 * 1024) -#define IOP13XX_MU_BASE_PHYS (0xff000000) -#define IOP13XX_MU_BASE_PCI (0xff000000) -#define IOP13XX_MU_MIMR_PCI (IOP13XX_MU_BASE_PCI + 0x48) -#define IOP13XX_MU_MIMR_CORE_SELECT (15) -/*=======================================================================*/ - -/*==============================ADMA UNITS===============================*/ -#define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9)) -#define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0) - -/*==============================XSI BRIDGE===============================*/ -#define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c) -#define IOP13XX_XBG_BERAR IOP13XX_REG_ADDR32(0x1790) -#define IOP13XX_XBG_BERUAR IOP13XX_REG_ADDR32(0x1794) -#define is_atue_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \ - IOP13XX_PMMR_VIRT_TO_PHYS(\ - IOP13XX_ATUE_OCCDR))\ - && (__raw_readl(IOP13XX_XBG_BECSR) & 1)) -#define is_atux_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \ - IOP13XX_PMMR_VIRT_TO_PHYS(\ - IOP13XX_ATUX_OCCDR))\ - && (__raw_readl(IOP13XX_XBG_BECSR) & 1)) -/*=======================================================================*/ - -#define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\ - (ofs)) - -#define IOP13XX_PBI_CR IOP13XX_PBI_OFFSET(0x0) -#define IOP13XX_PBI_SR IOP13XX_PBI_OFFSET(0x4) -#define IOP13XX_PBI_BAR0 IOP13XX_PBI_OFFSET(0x8) -#define IOP13XX_PBI_LR0 IOP13XX_PBI_OFFSET(0xc) -#define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10) -#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14) - -#define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180) - -/* Watchdog timer definitions */ -#define IOP_WDTCR_EN_ARM 0x1e1e1e1e -#define IOP_WDTCR_EN 0xe1e1e1e1 -#define IOP_WDTCR_DIS_ARM 0x1f1f1f1f -#define IOP_WDTCR_DIS 0xf1f1f1f1 -#define IOP_RCSR_WDT (1 << 5) /* reset caused by watchdog timer */ -#define IOP13XX_WDTSR_WRITE_EN (1 << 31) /* used to speed up reset requests */ -#define IOP13XX_WDTCR_IB_RESET (1 << 0) - -#endif /* _IOP13XX_HW_H_ */ diff --git a/include/asm-arm/arch-iop13xx/iq81340.h b/include/asm-arm/arch-iop13xx/iq81340.h deleted file mode 100644 index ba2cf931e9c..00000000000 --- a/include/asm-arm/arch-iop13xx/iq81340.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef _IQ81340_H_ -#define _IQ81340_H_ - -#define IQ81340_PCE_BAR0 IOP13XX_PBI_LOWER_MEM_RA -#define IQ81340_PCE_BAR1 (IQ81340_PCE_BAR0 + 0x02000000) - -#define IQ81340_FLASHBASE IQ81340_PCE_BAR0 /* Flash */ - -#define IQ81340_PCE_BAR1_OFFSET(a) (IQ81340_PCE_BAR1 + (a)) - -#define IQ81340_PRD_CODE IQ81340_PCE_BAR1_OFFSET(0) -#define IQ81340_BRD_STEP IQ81340_PCE_BAR1_OFFSET(0x10000) -#define IQ81340_CPLD_REV IQ81340_PCE_BAR1_OFFSET(0x20000) -#define IQ81340_LED IQ81340_PCE_BAR1_OFFSET(0x30000) -#define IQ81340_LHEX IQ81340_PCE_BAR1_OFFSET(0x40000) -#define IQ81340_RHEX IQ81340_PCE_BAR1_OFFSET(0x50000) -#define IQ81340_BUZZER IQ81340_PCE_BAR1_OFFSET(0x60000) -#define IQ81340_32K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x70000) -#define IQ81340_256K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x80000) -#define IQ81340_ROTARY_SW IQ81340_PCE_BAR1_OFFSET(0xd0000) -#define IQ81340_BATT_STAT IQ81340_PCE_BAR1_OFFSET(0xf0000) -#define IQ81340_CMP_FLSH IQ81340_PCE_BAR1_OFFSET(0x1000000) /* 16MB */ - -#define PBI_CF_IDE_BASE (IQ81340_CMP_FLSH) -#define PBI_CF_BAR_ADDR (IOP13XX_PBI_BAR1) - - -#endif /* _IQ81340_H_ */ diff --git a/include/asm-arm/arch-iop13xx/irqs.h b/include/asm-arm/arch-iop13xx/irqs.h deleted file mode 100644 index 054e7acb5bf..00000000000 --- a/include/asm-arm/arch-iop13xx/irqs.h +++ /dev/null @@ -1,196 +0,0 @@ -#ifndef _IOP13XX_IRQS_H_ -#define _IOP13XX_IRQS_H_ - -#ifndef __ASSEMBLER__ -#include <linux/types.h> - -/* INTPND0 CP6 R0 Page 3 - */ -static inline u32 read_intpnd_0(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c0, c3, 0":"=r" (val)); - return val; -} - -/* INTPND1 CP6 R1 Page 3 - */ -static inline u32 read_intpnd_1(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c1, c3, 0":"=r" (val)); - return val; -} - -/* INTPND2 CP6 R2 Page 3 - */ -static inline u32 read_intpnd_2(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c2, c3, 0":"=r" (val)); - return val; -} - -/* INTPND3 CP6 R3 Page 3 - */ -static inline u32 read_intpnd_3(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val)); - return val; -} -#endif - -#define INTBASE 0 -#define INTSIZE_4 1 - -/* - * iop34x chipset interrupts - */ -#define IOP13XX_IRQ(x) (IOP13XX_IRQ_OFS + (x)) - -/* - * On IRQ or FIQ register - */ -#define IRQ_IOP13XX_ADMA0_EOT (0) -#define IRQ_IOP13XX_ADMA0_EOC (1) -#define IRQ_IOP13XX_ADMA1_EOT (2) -#define IRQ_IOP13XX_ADMA1_EOC (3) -#define IRQ_IOP13XX_ADMA2_EOT (4) -#define IRQ_IOP13XX_ADMA2_EOC (5) -#define IRQ_IOP134_WATCHDOG (6) -#define IRQ_IOP13XX_RSVD_7 (7) -#define IRQ_IOP13XX_TIMER0 (8) -#define IRQ_IOP13XX_TIMER1 (9) -#define IRQ_IOP13XX_I2C_0 (10) -#define IRQ_IOP13XX_I2C_1 (11) -#define IRQ_IOP13XX_MSG (12) -#define IRQ_IOP13XX_MSGIBQ (13) -#define IRQ_IOP13XX_ATU_IM (14) -#define IRQ_IOP13XX_ATU_BIST (15) -#define IRQ_IOP13XX_PPMU (16) -#define IRQ_IOP13XX_COREPMU (17) -#define IRQ_IOP13XX_CORECACHE (18) -#define IRQ_IOP13XX_RSVD_19 (19) -#define IRQ_IOP13XX_RSVD_20 (20) -#define IRQ_IOP13XX_RSVD_21 (21) -#define IRQ_IOP13XX_RSVD_22 (22) -#define IRQ_IOP13XX_RSVD_23 (23) -#define IRQ_IOP13XX_XINT0 (24) -#define IRQ_IOP13XX_XINT1 (25) -#define IRQ_IOP13XX_XINT2 (26) -#define IRQ_IOP13XX_XINT3 (27) -#define IRQ_IOP13XX_XINT4 (28) -#define IRQ_IOP13XX_XINT5 (29) -#define IRQ_IOP13XX_XINT6 (30) -#define IRQ_IOP13XX_XINT7 (31) - /* IINTSRC1 bit */ -#define IRQ_IOP13XX_XINT8 (32) /* 0 */ -#define IRQ_IOP13XX_XINT9 (33) /* 1 */ -#define IRQ_IOP13XX_XINT10 (34) /* 2 */ -#define IRQ_IOP13XX_XINT11 (35) /* 3 */ -#define IRQ_IOP13XX_XINT12 (36) /* 4 */ -#define IRQ_IOP13XX_XINT13 (37) /* 5 */ -#define IRQ_IOP13XX_XINT14 (38) /* 6 */ -#define IRQ_IOP13XX_XINT15 (39) /* 7 */ -#define IRQ_IOP13XX_RSVD_40 (40) /* 8 */ -#define IRQ_IOP13XX_RSVD_41 (41) /* 9 */ -#define IRQ_IOP13XX_RSVD_42 (42) /* 10 */ -#define IRQ_IOP13XX_RSVD_43 (43) /* 11 */ -#define IRQ_IOP13XX_RSVD_44 (44) /* 12 */ -#define IRQ_IOP13XX_RSVD_45 (45) /* 13 */ -#define IRQ_IOP13XX_RSVD_46 (46) /* 14 */ -#define IRQ_IOP13XX_RSVD_47 (47) /* 15 */ -#define IRQ_IOP13XX_RSVD_48 (48) /* 16 */ -#define IRQ_IOP13XX_RSVD_49 (49) /* 17 */ -#define IRQ_IOP13XX_RSVD_50 (50) /* 18 */ -#define IRQ_IOP13XX_UART0 (51) /* 19 */ -#define IRQ_IOP13XX_UART1 (52) /* 20 */ -#define IRQ_IOP13XX_PBIE (53) /* 21 */ -#define IRQ_IOP13XX_ATU_CRW (54) /* 22 */ -#define IRQ_IOP13XX_ATU_ERR (55) /* 23 */ -#define IRQ_IOP13XX_MCU_ERR (56) /* 24 */ -#define IRQ_IOP13XX_ADMA0_ERR (57) /* 25 */ -#define IRQ_IOP13XX_ADMA1_ERR (58) /* 26 */ -#define IRQ_IOP13XX_ADMA2_ERR (59) /* 27 */ -#define IRQ_IOP13XX_RSVD_60 (60) /* 28 */ -#define IRQ_IOP13XX_RSVD_61 (61) /* 29 */ -#define IRQ_IOP13XX_MSG_ERR (62) /* 30 */ -#define IRQ_IOP13XX_RSVD_63 (63) /* 31 */ - /* IINTSRC2 bit */ -#define IRQ_IOP13XX_INTERPROC (64) /* 0 */ -#define IRQ_IOP13XX_RSVD_65 (65) /* 1 */ -#define IRQ_IOP13XX_RSVD_66 (66) /* 2 */ -#define IRQ_IOP13XX_RSVD_67 (67) /* 3 */ -#define IRQ_IOP13XX_RSVD_68 (68) /* 4 */ -#define IRQ_IOP13XX_RSVD_69 (69) /* 5 */ -#define IRQ_IOP13XX_RSVD_70 (70) /* 6 */ -#define IRQ_IOP13XX_RSVD_71 (71) /* 7 */ -#define IRQ_IOP13XX_RSVD_72 (72) /* 8 */ -#define IRQ_IOP13XX_RSVD_73 (73) /* 9 */ -#define IRQ_IOP13XX_RSVD_74 (74) /* 10 */ -#define IRQ_IOP13XX_RSVD_75 (75) /* 11 */ -#define IRQ_IOP13XX_RSVD_76 (76) /* 12 */ -#define IRQ_IOP13XX_RSVD_77 (77) /* 13 */ -#define IRQ_IOP13XX_RSVD_78 (78) /* 14 */ -#define IRQ_IOP13XX_RSVD_79 (79) /* 15 */ -#define IRQ_IOP13XX_RSVD_80 (80) /* 16 */ -#define IRQ_IOP13XX_RSVD_81 (81) /* 17 */ -#define IRQ_IOP13XX_RSVD_82 (82) /* 18 */ -#define IRQ_IOP13XX_RSVD_83 (83) /* 19 */ -#define IRQ_IOP13XX_RSVD_84 (84) /* 20 */ -#define IRQ_IOP13XX_RSVD_85 (85) /* 21 */ -#define IRQ_IOP13XX_RSVD_86 (86) /* 22 */ -#define IRQ_IOP13XX_RSVD_87 (87) /* 23 */ -#define IRQ_IOP13XX_RSVD_88 (88) /* 24 */ -#define IRQ_IOP13XX_RSVD_89 (89) /* 25 */ -#define IRQ_IOP13XX_RSVD_90 (90) /* 26 */ -#define IRQ_IOP13XX_RSVD_91 (91) /* 27 */ -#define IRQ_IOP13XX_RSVD_92 (92) /* 28 */ -#define IRQ_IOP13XX_RSVD_93 (93) /* 29 */ -#define IRQ_IOP13XX_SIB_ERR (94) /* 30 */ -#define IRQ_IOP13XX_SRAM_ERR (95) /* 31 */ - /* IINTSRC3 bit */ -#define IRQ_IOP13XX_I2C_2 (96) /* 0 */ -#define IRQ_IOP13XX_ATUE_BIST (97) /* 1 */ -#define IRQ_IOP13XX_ATUE_CRW (98) /* 2 */ -#define IRQ_IOP13XX_ATUE_ERR (99) /* 3 */ -#define IRQ_IOP13XX_IMU (100) /* 4 */ -#define IRQ_IOP13XX_RSVD_101 (101) /* 5 */ -#define IRQ_IOP13XX_RSVD_102 (102) /* 6 */ -#define IRQ_IOP13XX_TPMI0_OUT (103) /* 7 */ -#define IRQ_IOP13XX_TPMI1_OUT (104) /* 8 */ -#define IRQ_IOP13XX_TPMI2_OUT (105) /* 9 */ -#define IRQ_IOP13XX_TPMI3_OUT (106) /* 10 */ -#define IRQ_IOP13XX_ATUE_IMA (107) /* 11 */ -#define IRQ_IOP13XX_ATUE_IMB (108) /* 12 */ -#define IRQ_IOP13XX_ATUE_IMC (109) /* 13 */ -#define IRQ_IOP13XX_ATUE_IMD (110) /* 14 */ -#define IRQ_IOP13XX_MU_MSI_TB (111) /* 15 */ -#define IRQ_IOP13XX_RSVD_112 (112) /* 16 */ -#define IRQ_IOP13XX_INBD_MSI (113) /* 17 */ -#define IRQ_IOP13XX_RSVD_114 (114) /* 18 */ -#define IRQ_IOP13XX_RSVD_115 (115) /* 19 */ -#define IRQ_IOP13XX_RSVD_116 (116) /* 20 */ -#define IRQ_IOP13XX_RSVD_117 (117) /* 21 */ -#define IRQ_IOP13XX_RSVD_118 (118) /* 22 */ -#define IRQ_IOP13XX_RSVD_119 (119) /* 23 */ -#define IRQ_IOP13XX_RSVD_120 (120) /* 24 */ -#define IRQ_IOP13XX_RSVD_121 (121) /* 25 */ -#define IRQ_IOP13XX_RSVD_122 (122) /* 26 */ -#define IRQ_IOP13XX_RSVD_123 (123) /* 27 */ -#define IRQ_IOP13XX_RSVD_124 (124) /* 28 */ -#define IRQ_IOP13XX_RSVD_125 (125) /* 29 */ -#define IRQ_IOP13XX_RSVD_126 (126) /* 30 */ -#define IRQ_IOP13XX_HPI (127) /* 31 */ - -#ifdef CONFIG_PCI_MSI -#define IRQ_IOP13XX_MSI_0 (IRQ_IOP13XX_HPI + 1) -#define NR_IOP13XX_IRQS (IRQ_IOP13XX_MSI_0 + 128) -#else -#define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1) -#endif - -#define NR_IRQS NR_IOP13XX_IRQS - -#endif /* _IOP13XX_IRQ_H_ */ diff --git a/include/asm-arm/arch-iop13xx/memory.h b/include/asm-arm/arch-iop13xx/memory.h deleted file mode 100644 index 031a0fa78ef..00000000000 --- a/include/asm-arm/arch-iop13xx/memory.h +++ /dev/null @@ -1,64 +0,0 @@ -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -#include <asm/arch/hardware.h> - -/* - * Physical DRAM offset. - */ -#define PHYS_OFFSET UL(0x00000000) -#define TASK_SIZE UL(0x3f000000) -#define PAGE_OFFSET UL(0x40000000) -#define TASK_UNMAPPED_BASE ((TASK_SIZE + 0x01000000) / 3) - -#ifndef __ASSEMBLY__ - -#if defined(CONFIG_ARCH_IOP13XX) -#define IOP13XX_PMMR_V_START (IOP13XX_PMMR_VIRT_MEM_BASE) -#define IOP13XX_PMMR_V_END (IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_SIZE) -#define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE) -#define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE) - -/* - * Virtual view <-> PCI DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - */ - -/* RAM has 1:1 mapping on the PCIe/x Busses */ -#define __virt_to_bus(x) (__virt_to_phys(x)) -#define __bus_to_virt(x) (__phys_to_virt(x)) - -#define virt_to_lbus(x) \ -(( ((void*)(x) >= (void*)IOP13XX_PMMR_V_START) && \ -((void*)(x) < (void*)IOP13XX_PMMR_V_END) ) ? \ -((x) - IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_PHYS_MEM_BASE) : \ -((x) - PAGE_OFFSET + PHYS_OFFSET)) - -#define lbus_to_virt(x) \ -(( ((x) >= IOP13XX_PMMR_P_START) && ((x) < IOP13XX_PMMR_P_END) ) ? \ -((x) - IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_VIRT_MEM_BASE ) : \ -((x) - PHYS_OFFSET + PAGE_OFFSET)) - -/* Device is an lbus device if it is on the platform bus of the IOP13XX */ -#define is_lbus_device(dev) (dev &&\ - (strncmp(dev->bus->name, "platform", 8) == 0)) - -#define __arch_page_to_dma(dev, page) \ -({is_lbus_device(dev) ? (dma_addr_t)virt_to_lbus(page_address(page)) : \ -(dma_addr_t)__virt_to_bus(page_address(page));}) - -#define __arch_dma_to_virt(dev, addr) \ -({is_lbus_device(dev) ? lbus_to_virt(addr) : __bus_to_virt(addr);}) - -#define __arch_virt_to_dma(dev, addr) \ -({is_lbus_device(dev) ? virt_to_lbus(addr) : __virt_to_bus(addr);}) - -#endif /* CONFIG_ARCH_IOP13XX */ -#endif /* !ASSEMBLY */ - -#define PFN_TO_NID(addr) (0) - -#endif diff --git a/include/asm-arm/arch-iop13xx/msi.h b/include/asm-arm/arch-iop13xx/msi.h deleted file mode 100644 index b80c5ae17e9..00000000000 --- a/include/asm-arm/arch-iop13xx/msi.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef _IOP13XX_MSI_H_ -#define _IOP13XX_MSI_H_ -#ifdef CONFIG_PCI_MSI -void iop13xx_msi_init(void); -#else -static inline void iop13xx_msi_init(void) -{ - return; -} -#endif -#endif diff --git a/include/asm-arm/arch-iop13xx/pci.h b/include/asm-arm/arch-iop13xx/pci.h deleted file mode 100644 index 4041f30d4cd..00000000000 --- a/include/asm-arm/arch-iop13xx/pci.h +++ /dev/null @@ -1,57 +0,0 @@ -#ifndef _IOP13XX_PCI_H_ -#define _IOP13XX_PCI_H_ -#include <asm/arch/irqs.h> -#include <asm/io.h> - -struct pci_sys_data; -struct hw_pci; -int iop13xx_pci_setup(int nr, struct pci_sys_data *sys); -struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *); -void iop13xx_atu_select(struct hw_pci *plat_pci); -void iop13xx_pci_init(void); -void iop13xx_map_pci_memory(void); - -#define IOP_PCI_STATUS_ERROR (PCI_STATUS_PARITY | \ - PCI_STATUS_SIG_TARGET_ABORT | \ - PCI_STATUS_REC_TARGET_ABORT | \ - PCI_STATUS_REC_TARGET_ABORT | \ - PCI_STATUS_REC_MASTER_ABORT | \ - PCI_STATUS_SIG_SYSTEM_ERROR | \ - PCI_STATUS_DETECTED_PARITY) - -#define IOP13XX_ATUE_ATUISR_ERROR (IOP13XX_ATUE_STAT_HALT_ON_ERROR | \ - IOP13XX_ATUE_STAT_ROOT_SYS_ERR | \ - IOP13XX_ATUE_STAT_PCI_IFACE_ERR | \ - IOP13XX_ATUE_STAT_ERR_COR | \ - IOP13XX_ATUE_STAT_ERR_UNCOR | \ - IOP13XX_ATUE_STAT_CRS | \ - IOP13XX_ATUE_STAT_DET_PAR_ERR | \ - IOP13XX_ATUE_STAT_EXT_REC_MABORT | \ - IOP13XX_ATUE_STAT_SIG_TABORT | \ - IOP13XX_ATUE_STAT_EXT_REC_TABORT | \ - IOP13XX_ATUE_STAT_MASTER_DATA_PAR) - -#define IOP13XX_ATUX_ATUISR_ERROR (IOP13XX_ATUX_STAT_TX_SCEM | \ - IOP13XX_ATUX_STAT_REC_SCEM | \ - IOP13XX_ATUX_STAT_TX_SERR | \ - IOP13XX_ATUX_STAT_DET_PAR_ERR | \ - IOP13XX_ATUX_STAT_INT_REC_MABORT | \ - IOP13XX_ATUX_STAT_REC_SERR | \ - IOP13XX_ATUX_STAT_EXT_REC_MABORT | \ - IOP13XX_ATUX_STAT_EXT_REC_TABORT | \ - IOP13XX_ATUX_STAT_EXT_SIG_TABORT | \ - IOP13XX_ATUX_STAT_MASTER_DATA_PAR) - -/* PCI interrupts - */ -#define ATUX_INTA IRQ_IOP13XX_XINT0 -#define ATUX_INTB IRQ_IOP13XX_XINT1 -#define ATUX_INTC IRQ_IOP13XX_XINT2 -#define ATUX_INTD IRQ_IOP13XX_XINT3 - -#define ATUE_INTA IRQ_IOP13XX_ATUE_IMA -#define ATUE_INTB IRQ_IOP13XX_ATUE_IMB -#define ATUE_INTC IRQ_IOP13XX_ATUE_IMC -#define ATUE_INTD IRQ_IOP13XX_ATUE_IMD - -#endif /* _IOP13XX_PCI_H_ */ diff --git a/include/asm-arm/arch-iop13xx/system.h b/include/asm-arm/arch-iop13xx/system.h deleted file mode 100644 index 8575af8db78..00000000000 --- a/include/asm-arm/arch-iop13xx/system.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * linux/include/asm-arm/arch-iop13xx/system.h - * - * Copyright (C) 2004 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <asm/arch/iop13xx.h> -static inline void arch_idle(void) -{ - cpu_do_idle(); -} - -static inline void arch_reset(char mode) -{ - /* - * Reset the internal bus (warning both cores are reset) - */ - write_wdtcr(IOP_WDTCR_EN_ARM); - write_wdtcr(IOP_WDTCR_EN); - write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET); - write_wdtcr(0x1000); - - for(;;); -} diff --git a/include/asm-arm/arch-iop13xx/time.h b/include/asm-arm/arch-iop13xx/time.h deleted file mode 100644 index 49213d9d7ca..00000000000 --- a/include/asm-arm/arch-iop13xx/time.h +++ /dev/null @@ -1,107 +0,0 @@ -#ifndef _IOP13XX_TIME_H_ -#define _IOP13XX_TIME_H_ -#define IRQ_IOP_TIMER0 IRQ_IOP13XX_TIMER0 - -#define IOP_TMR_EN 0x02 -#define IOP_TMR_RELOAD 0x04 -#define IOP_TMR_PRIVILEGED 0x08 -#define IOP_TMR_RATIO_1_1 0x00 - -#define IOP13XX_XSI_FREQ_RATIO_MASK (3 << 19) -#define IOP13XX_XSI_FREQ_RATIO_2 (0 << 19) -#define IOP13XX_XSI_FREQ_RATIO_3 (1 << 19) -#define IOP13XX_XSI_FREQ_RATIO_4 (2 << 19) -#define IOP13XX_CORE_FREQ_MASK (7 << 16) -#define IOP13XX_CORE_FREQ_600 (0 << 16) -#define IOP13XX_CORE_FREQ_667 (1 << 16) -#define IOP13XX_CORE_FREQ_800 (2 << 16) -#define IOP13XX_CORE_FREQ_933 (3 << 16) -#define IOP13XX_CORE_FREQ_1000 (4 << 16) -#define IOP13XX_CORE_FREQ_1200 (5 << 16) - -void iop_init_time(unsigned long tickrate); -unsigned long iop_gettimeoffset(void); - -static inline unsigned long iop13xx_core_freq(void) -{ - unsigned long freq = __raw_readl(IOP13XX_PROCESSOR_FREQ); - freq &= IOP13XX_CORE_FREQ_MASK; - switch (freq) { - case IOP13XX_CORE_FREQ_600: - return 600000000; - case IOP13XX_CORE_FREQ_667: - return 667000000; - case IOP13XX_CORE_FREQ_800: - return 800000000; - case IOP13XX_CORE_FREQ_933: - return 933000000; - case IOP13XX_CORE_FREQ_1000: - return 1000000000; - case IOP13XX_CORE_FREQ_1200: - return 1200000000; - default: - printk("%s: warning unknown frequency, defaulting to 800Mhz\n", - __FUNCTION__); - } - - return 800000000; -} - -static inline unsigned long iop13xx_xsi_bus_ratio(void) -{ - unsigned long ratio = __raw_readl(IOP13XX_PROCESSOR_FREQ); - ratio &= IOP13XX_XSI_FREQ_RATIO_MASK; - switch (ratio) { - case IOP13XX_XSI_FREQ_RATIO_2: - return 2; - case IOP13XX_XSI_FREQ_RATIO_3: - return 3; - case IOP13XX_XSI_FREQ_RATIO_4: - return 4; - default: - printk("%s: warning unknown ratio, defaulting to 2\n", - __FUNCTION__); - } - - return 2; -} - -static inline void write_tmr0(u32 val) -{ - asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val)); -} - -static inline void write_tmr1(u32 val) -{ - asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (val)); -} - -static inline u32 read_tcr0(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c2, c9, 0" : "=r" (val)); - return val; -} - -static inline u32 read_tcr1(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val)); - return val; -} - -static inline void write_trr0(u32 val) -{ - asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val)); -} - -static inline void write_trr1(u32 val) -{ - asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (val)); -} - -static inline void write_tisr(u32 val) -{ - asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (val)); -} -#endif diff --git a/include/asm-arm/arch-iop13xx/timex.h b/include/asm-arm/arch-iop13xx/timex.h deleted file mode 100644 index f0c51dd97ed..00000000000 --- a/include/asm-arm/arch-iop13xx/timex.h +++ /dev/null @@ -1,3 +0,0 @@ -#include <asm/hardware.h> - -#define CLOCK_TICK_RATE (100 * HZ) diff --git a/include/asm-arm/arch-iop13xx/uncompress.h b/include/asm-arm/arch-iop13xx/uncompress.h deleted file mode 100644 index dd9c2934190..00000000000 --- a/include/asm-arm/arch-iop13xx/uncompress.h +++ /dev/null @@ -1,23 +0,0 @@ -#include <asm/types.h> -#include <linux/serial_reg.h> -#include <asm/hardware.h> - -#define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS) -#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) - -static inline void putc(char c) -{ - while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE) - barrier(); - UART_BASE[UART_TX] = c; -} - -static inline void flush(void) -{ -} - -/* - * nothing to do - */ -#define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/include/asm-arm/arch-iop13xx/vmalloc.h b/include/asm-arm/arch-iop13xx/vmalloc.h deleted file mode 100644 index c5345674034..00000000000 --- a/include/asm-arm/arch-iop13xx/vmalloc.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef _VMALLOC_H_ -#define _VMALLOC_H_ -#define VMALLOC_END 0xfa000000UL -#endif |