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-rw-r--r--include/asm-arm/arch-s3c2410/debug-macro.S10
-rw-r--r--include/asm-arm/arch-s3c2410/entry-macro.S30
-rw-r--r--include/asm-arm/arch-s3c2410/map.h16
-rw-r--r--include/asm-arm/arch-s3c2410/regs-clock.h63
-rw-r--r--include/asm-arm/arch-s3c2410/regs-dsc.h3
-rw-r--r--include/asm-arm/arch-s3c2410/regs-gpio.h63
-rw-r--r--include/asm-arm/arch-s3c2410/regs-gpioj.h5
-rw-r--r--include/asm-arm/arch-s3c2410/regs-irq.h6
-rw-r--r--include/asm-arm/arch-s3c2410/regs-serial.h15
9 files changed, 182 insertions, 29 deletions
diff --git a/include/asm-arm/arch-s3c2410/debug-macro.S b/include/asm-arm/arch-s3c2410/debug-macro.S
index 5f8223e700d..b7d15d12545 100644
--- a/include/asm-arm/arch-s3c2410/debug-macro.S
+++ b/include/asm-arm/arch-s3c2410/debug-macro.S
@@ -33,7 +33,7 @@
.endm
.macro senduart,rd,rx
- str \rd, [\rx, # S3C2410_UTXH ]
+ strb \rd, [\rx, # S3C2410_UTXH ]
.endm
.macro busyuart, rd, rx
@@ -42,6 +42,12 @@
beq 1001f @
@ FIFO enabled...
1003:
+ @ check for arm920 vs arm926. currently assume all arm926
+ @ devices have an 64 byte FIFO identical to the s3c2440
+ mrc p15, 0, \rd, c0, c0
+ and \rd, \rd, #0xff0
+ teq \rd, #0x260
+ beq 1004f
mrc p15, 0, \rd, c1, c0
tst \rd, #1
addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
@@ -50,7 +56,7 @@
ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
and \rd, \rd, #0x00ff0000
teq \rd, #0x00440000 @ is it 2440?
-
+1004:
ldr \rd, [ \rx, # S3C2410_UFSTAT ]
moveq \rd, \rd, lsr #SHIFT_2440TXF
tst \rd, #S3C2410_UFSTAT_TXFULL
diff --git a/include/asm-arm/arch-s3c2410/entry-macro.S b/include/asm-arm/arch-s3c2410/entry-macro.S
index 894c35cf3b1..e09a6b8ec15 100644
--- a/include/asm-arm/arch-s3c2410/entry-macro.S
+++ b/include/asm-arm/arch-s3c2410/entry-macro.S
@@ -18,8 +18,6 @@
#define INTPND (0x10)
#define INTOFFSET (0x14)
-#define EXTINTPEND (0xa8)
-#define EXTINTMASK (0xa4)
#include <asm/hardware.h>
#include <asm/arch/irqs.h>
@@ -28,37 +26,23 @@
mov \base, #S3C24XX_VA_IRQ
- ldr \irqstat, [ \base, #INTPND]
- bics \irqnr, \irqstat, #3<<4 @@ only an GPIO IRQ
- beq 2000f
-
@@ try the interrupt offset register, since it is there
+ ldr \irqstat, [ \base, #INTPND ]
+ teq \irqstat, #0
+ beq 1002f
ldr \irqnr, [ \base, #INTOFFSET ]
mov \tmp, #1
tst \irqstat, \tmp, lsl \irqnr
- addne \irqnr, \irqnr, #IRQ_EINT0
bne 1001f
@@ the number specified is not a valid irq, so try
@@ and work it out for ourselves
- mov \irqnr, #IRQ_EINT0 @@ start here
- b 3000f
-
-2000:
- @@ load the GPIO interrupt register, and check it
-
- add \tmp, \base, #S3C24XX_VA_GPIO - S3C24XX_VA_IRQ
- ldr \irqstat, [ \tmp, # EXTINTPEND ]
- ldr \irqnr, [ \tmp, # EXTINTMASK ]
- bics \irqstat, \irqstat, \irqnr
- beq 1001f
-
- mov \irqnr, #(IRQ_EINT4 - 4)
+ mov \irqnr, #0 @@ start here
@@ work out which irq (if any) we got
-3000:
+
movs \tmp, \irqstat, lsl#16
addeq \irqnr, \irqnr, #16
moveq \irqstat, \irqstat, lsr#16
@@ -75,9 +59,9 @@
addeq \irqnr, \irqnr, #1
@@ we have the value
- movs \irqnr, \irqnr
-
1001:
+ adds \irqnr, \irqnr, #IRQ_EINT0
+1002:
@@ exit here, Z flag unset if IRQ
.endm
diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h
index 5e4c8c37bc6..fae2766ff32 100644
--- a/include/asm-arm/arch-s3c2410/map.h
+++ b/include/asm-arm/arch-s3c2410/map.h
@@ -236,4 +236,20 @@
#define S3C24XX_PA_SPI S3C2410_PA_SPI
#endif
+/* deal with the registers that move under the 2412/2413 */
+
+#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
+#ifndef __ASSEMBLY__
+extern void __iomem *s3c24xx_va_gpio2;
+#endif
+#ifdef CONFIG_CPU_S3C2412_ONLY
+#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
+#else
+#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
+#endif
+#else
+#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
+#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
+#endif
+
#endif /* __ASM_ARCH_MAP_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
index 6c92faffe98..a7c61feb843 100644
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -1,6 +1,6 @@
/* linux/include/asm/arch-s3c2410/regs-clock.h
*
- * Copyright (c) 2003,2004,2005 Simtec Electronics <linux@simtec.co.uk>
+ * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
@@ -140,5 +140,66 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
#endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */
+#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
+
+#define S3C2412_OSCSET S3C2410_CLKREG(0x18)
+#define S3C2412_CLKSRC S3C2410_CLKREG(0x1C)
+
+#define S3C2412_PLLCON_OFF (1<<20)
+
+#define S3C2412_CLKDIVN_PDIVN (1<<2)
+#define S3C2412_CLKDIVN_HDIVN_MASK (3<<0)
+#define S3C2421_CLKDIVN_ARMDIVN (1<<3)
+#define S3C2412_CLKDIVN_USB48DIV (1<<6)
+#define S3C2412_CLKDIVN_UARTDIV_MASK (15<<8)
+#define S3C2412_CLKDIVN_UARTDIV_SHIFT (8)
+#define S3C2412_CLKDIVN_I2SDIV_MASK (15<<12)
+#define S3C2412_CLKDIVN_I2SDIV_SHIFT (12)
+#define S3C2412_CLKDIVN_CAMDIV_MASK (15<<16)
+#define S3C2412_CLKDIVN_CAMDIV_SHIFT (16)
+
+#define S3C2412_CLKCON_WDT (1<<28)
+#define S3C2412_CLKCON_SPI (1<<27)
+#define S3C2412_CLKCON_IIS (1<<26)
+#define S3C2412_CLKCON_IIC (1<<25)
+#define S3C2412_CLKCON_ADC (1<<24)
+#define S3C2412_CLKCON_RTC (1<<23)
+#define S3C2412_CLKCON_GPIO (1<<22)
+#define S3C2412_CLKCON_UART2 (1<<21)
+#define S3C2412_CLKCON_UART1 (1<<20)
+#define S3C2412_CLKCON_UART0 (1<<19)
+#define S3C2412_CLKCON_SDI (1<<18)
+#define S3C2412_CLKCON_PWMT (1<<17)
+#define S3C2412_CLKCON_USBD (1<<16)
+#define S3C2412_CLKCON_CAMCLK (1<<15)
+#define S3C2412_CLKCON_UARTCLK (1<<14)
+/* missing 13 */
+#define S3C2412_CLKCON_USB_HOST48 (1<<12)
+#define S3C2412_CLKCON_USB_DEV48 (1<<11)
+#define S3C2412_CLKCON_HCLKdiv2 (1<<10)
+#define S3C2412_CLKCON_HCLKx2 (1<<9)
+#define S3C2412_CLKCON_SDRAM (1<<8)
+/* missing 7 */
+#define S3C2412_CLKCON_USBH S3C2410_CLKCON_USBH
+#define S3C2412_CLKCON_LCDC S3C2410_CLKCON_LCDC
+#define S3C2412_CLKCON_NAND S3C2410_CLKCON_NAND
+#define S3C2412_CLKCON_DMA3 (1<<3)
+#define S3C2412_CLKCON_DMA2 (1<<2)
+#define S3C2412_CLKCON_DMA1 (1<<1)
+#define S3C2412_CLKCON_DMA0 (1<<0)
+
+/* clock sourec controls */
+
+#define S3C2412_CLKSRC_EXTCLKDIV_MASK (7 << 0)
+#define S3C2412_CLKSRC_EXTCLKDIV_SHIFT (0)
+#define S3C2412_CLKSRC_MDIVCLK_EXTCLKDIV (1<<3)
+#define S3C2412_CLKSRC_MSYSCLK_MPLL (1<<4)
+#define S3C2412_CLKSRC_USYSCLK_UPLL (1<<5)
+#define S3C2412_CLKSRC_UARTCLK_MPLL (1<<8)
+#define S3C2412_CLKSRC_I2SCLK_MPLL (1<<9)
+#define S3C2412_CLKSRC_USBCLK_HCLK (1<<10)
+#define S3C2412_CLKSRC_CAMCLK_HCLK (1<<11)
+
+#endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */
#endif /* __ASM_ARM_REGS_CLOCK */
diff --git a/include/asm-arm/arch-s3c2410/regs-dsc.h b/include/asm-arm/arch-s3c2410/regs-dsc.h
index ba13a2c9e54..84aca61cbaa 100644
--- a/include/asm-arm/arch-s3c2410/regs-dsc.h
+++ b/include/asm-arm/arch-s3c2410/regs-dsc.h
@@ -23,6 +23,9 @@
#define S3C2440_DSC0 S3C2410_GPIOREG(0xc4)
#define S3C2440_DSC1 S3C2410_GPIOREG(0xc8)
+#define S3C2412_DSC0 S3C2410_GPIOREG(0xdc)
+#define S3C2412_DSC1 S3C2410_GPIOREG(0xe0)
+
#define S3C2440_SELECT_DSC0 (0)
#define S3C2440_SELECT_DSC1 (1<<31)
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
index 5f10334f06b..6dd17f0f84e 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -45,7 +45,7 @@
#define S3C24XX_MISCCR S3C2400_MISCCR
#else
#define S3C24XX_GPIO_BASE(x) S3C2410_GPIO_BASE(x)
-#define S3C24XX_MISCCR S3C2410_MISCCR
+#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)
#endif /* CONFIG_CPU_S3C2400 */
@@ -73,9 +73,15 @@
#define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* not available on A */
#define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */
-/* configure GPIO ports A..G */
+/* register address for the GPIO registers.
+ * S3C24XX_GPIOREG2 is for the second set of registers in the
+ * GPIO which move between s3c2410 and s3c2412 type systems */
#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
+#define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2)
+
+
+/* configure GPIO ports A..G */
/* port A - S3C2410: 22bits, zero in bit X makes pin X output
* S3C2400: 18bits, zero in bit X makes pin X output
@@ -953,11 +959,18 @@
#define S3C2410_GPH10_OUTP (0x01 << 20)
#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
+/* The S3C2412 and S3C2413 move the GPJ register set to after
+ * GPH, which means all registers after 0x80 are now offset by 0x10
+ * for the 2412/2413 from the 2410/2440/2442
+*/
+
/* miscellaneous control */
#define S3C2400_MISCCR S3C2410_GPIOREG(0x54)
#define S3C2410_MISCCR S3C2410_GPIOREG(0x80)
#define S3C2410_DCLKCON S3C2410_GPIOREG(0x84)
+#define S3C24XX_DCLKCON S3C24XX_GPIOREG2(0x84)
+
/* see clock.h for dclk definitions */
/* pullup control on databus */
@@ -985,6 +998,8 @@
#define S3C2410_MISCCR_CLK0_DCLK0 (5<<4)
#define S3C2410_MISCCR_CLK0_MASK (7<<4)
+#define S3C2412_MISCCR_CLK0_RTC (2<<4)
+
#define S3C2410_MISCCR_CLK1_MPLL (0<<8)
#define S3C2410_MISCCR_CLK1_UPLL (1<<8)
#define S3C2410_MISCCR_CLK1_FCLK (2<<8)
@@ -993,6 +1008,8 @@
#define S3C2410_MISCCR_CLK1_DCLK1 (5<<8)
#define S3C2410_MISCCR_CLK1_MASK (7<<8)
+#define S3C2412_MISCCR_CLK1_CLKsrc (0<<8)
+
#define S3C2410_MISCCR_USBSUSPND0 (1<<12)
#define S3C2410_MISCCR_USBSUSPND1 (1<<13)
@@ -1000,7 +1017,7 @@
#define S3C2410_MISCCR_nEN_SCLK0 (1<<17)
#define S3C2410_MISCCR_nEN_SCLK1 (1<<18)
-#define S3C2410_MISCCR_nEN_SCLKE (1<<19)
+#define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */
#define S3C2410_MISCCR_SDSLEEP (7<<17)
/* external interrupt control... */
@@ -1017,6 +1034,10 @@
#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C)
#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90)
+#define S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88)
+#define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C)
+#define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90)
+
/* values for S3C2410_EXTINT0/1/2 */
#define S3C2410_EXTINT_LOWLEV (0x00)
#define S3C2410_EXTINT_HILEV (0x01)
@@ -1030,6 +1051,11 @@
#define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C)
#define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0)
+#define S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94)
+#define S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98)
+#define S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C)
+#define S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0)
+
/* values for interrupt filtering */
#define S3C2410_EINTFLT_PCLK (0x00)
#define S3C2410_EINTFLT_EXTCLK (1<<7)
@@ -1039,6 +1065,7 @@
/* GSTATUS have miscellaneous information in them
*
+ * These move between s3c2410 and s3c2412 style systems.
*/
#define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC)
@@ -1047,6 +1074,18 @@
#define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8)
#define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC)
+#define S3C2412_GSTATUS0 S3C2410_GPIOREG(0x0BC)
+#define S3C2412_GSTATUS1 S3C2410_GPIOREG(0x0C0)
+#define S3C2412_GSTATUS2 S3C2410_GPIOREG(0x0C4)
+#define S3C2412_GSTATUS3 S3C2410_GPIOREG(0x0C8)
+#define S3C2412_GSTATUS4 S3C2410_GPIOREG(0x0CC)
+
+#define S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC)
+#define S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0)
+#define S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4)
+#define S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8)
+#define S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC)
+
#define S3C2410_GSTATUS0_nWAIT (1<<3)
#define S3C2410_GSTATUS0_NCON (1<<2)
#define S3C2410_GSTATUS0_RnB (1<<1)
@@ -1054,6 +1093,7 @@
#define S3C2410_GSTATUS1_IDMASK (0xffff0000)
#define S3C2410_GSTATUS1_2410 (0x32410000)
+#define S3C2410_GSTATUS1_2412 (0x32412001)
#define S3C2410_GSTATUS1_2440 (0x32440000)
#define S3C2410_GSTATUS1_2442 (0x32440aaa)
@@ -1077,5 +1117,22 @@
#define S3C2400_OPENCR_OPC_MOSIDIS (0<<5)
#define S3C2400_OPENCR_OPC_MOSIEN (1<<5)
+/* 2412/2413 sleep configuration registers */
+
+#define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C)
+#define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C)
+#define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C)
+#define S3C2412_GPESLPCON S3C2410_GPIOREG(0x4C)
+#define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C)
+#define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C)
+#define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C)
+
+/* definitions for each pin bit */
+#define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2))
+#define S3C2412_SLPCON_HI(x) ( 0x01 << ((x) * 2))
+#define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2))
+#define S3C2412_SLPCON_PDWN(x) ( 0x03 << ((x) * 2))
+#define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2))
+
#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-gpioj.h b/include/asm-arm/arch-s3c2410/regs-gpioj.h
index 3ad2324acc3..18edae50d0b 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpioj.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpioj.h
@@ -32,6 +32,11 @@
#define S3C2440_GPJDAT S3C2410_GPIOREG(0xd4)
#define S3C2440_GPJUP S3C2410_GPIOREG(0xd8)
+#define S3C2413_GPJCON S3C2410_GPIOREG(0x80)
+#define S3C2413_GPJDAT S3C2410_GPIOREG(0x84)
+#define S3C2413_GPJUP S3C2410_GPIOREG(0x88)
+#define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C)
+
#define S3C2440_GPJ0 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 0)
#define S3C2440_GPJ0_INP (0x00 << 0)
#define S3C2440_GPJ0_OUTP (0x01 << 0)
diff --git a/include/asm-arm/arch-s3c2410/regs-irq.h b/include/asm-arm/arch-s3c2410/regs-irq.h
index 24b7292df79..572fca5d9ac 100644
--- a/include/asm-arm/arch-s3c2410/regs-irq.h
+++ b/include/asm-arm/arch-s3c2410/regs-irq.h
@@ -23,6 +23,7 @@
#define S3C2410_IRQREG(x) ((x) + S3C24XX_VA_IRQ)
#define S3C2410_EINTREG(x) ((x) + S3C24XX_VA_GPIO)
+#define S3C24XX_EINTREG(x) ((x) + S3C24XX_VA_GPIO2)
#define S3C2410_SRCPND S3C2410_IRQREG(0x000)
#define S3C2410_INTMOD S3C2410_IRQREG(0x004)
@@ -40,5 +41,10 @@
#define S3C2410_EINTMASK S3C2410_EINTREG(0x0A4)
#define S3C2410_EINTPEND S3C2410_EINTREG(0X0A8)
+#define S3C2412_EINTMASK S3C2410_EINTREG(0x0B4)
+#define S3C2412_EINTPEND S3C2410_EINTREG(0X0B8)
+
+#define S3C24XX_EINTMASK S3C24XX_EINTREG(0x0A4)
+#define S3C24XX_EINTPEND S3C24XX_EINTREG(0X0A8)
#endif /* ___ASM_ARCH_REGS_IRQ_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-serial.h b/include/asm-arm/arch-s3c2410/regs-serial.h
index 83b01254c4a..93f651ae296 100644
--- a/include/asm-arm/arch-s3c2410/regs-serial.h
+++ b/include/asm-arm/arch-s3c2410/regs-serial.h
@@ -82,6 +82,12 @@
#define S3C2440_UCON2_DIVMASK (7 << 12)
#define S3C2440_UCON_DIVSHIFT (12)
+#define S3C2412_UCON_CLKMASK (3<<10)
+#define S3C2412_UCON_UCLK (1<<10)
+#define S3C2412_UCON_USYSCLK (3<<10)
+#define S3C2412_UCON_PCLK (0<<10)
+#define S3C2412_UCON_PCLK2 (2<<10)
+
#define S3C2410_UCON_UCLK (1<<10)
#define S3C2410_UCON_SBREAK (1<<4)
@@ -124,6 +130,15 @@
#define S3C2410_UMCOM_AFC (1<<4)
#define S3C2410_UMCOM_RTS_LOW (1<<0)
+#define S3C2412_UMCON_AFC_63 (0<<5)
+#define S3C2412_UMCON_AFC_56 (1<<5)
+#define S3C2412_UMCON_AFC_48 (2<<5)
+#define S3C2412_UMCON_AFC_40 (3<<5)
+#define S3C2412_UMCON_AFC_32 (4<<5)
+#define S3C2412_UMCON_AFC_24 (5<<5)
+#define S3C2412_UMCON_AFC_16 (6<<5)
+#define S3C2412_UMCON_AFC_8 (7<<5)
+
#define S3C2410_UFSTAT_TXFULL (1<<9)
#define S3C2410_UFSTAT_RXFULL (1<<8)
#define S3C2410_UFSTAT_TXMASK (15<<4)