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-rw-r--r--include/asm-arm/arch-ixp2000/platform.h1
-rw-r--r--include/asm-arm/arch-ixp4xx/io.h176
-rw-r--r--include/asm-arm/arch-omap/board-h2.h5
-rw-r--r--include/asm-arm/arch-omap/board-h3.h5
-rw-r--r--include/asm-arm/arch-omap/board-osk.h5
-rw-r--r--include/asm-arm/arch-omap/board.h12
-rw-r--r--include/asm-arm/arch-omap/common.h36
-rw-r--r--include/asm-arm/arch-omap/dma.h1
-rw-r--r--include/asm-arm/arch-omap/hardware.h24
-rw-r--r--include/asm-arm/arch-omap/irqs.h3
-rw-r--r--include/asm-arm/arch-omap/mux.h28
-rw-r--r--include/asm-arm/arch-omap/omap16xx.h32
-rw-r--r--include/asm-arm/arch-omap/system.h21
13 files changed, 311 insertions, 38 deletions
diff --git a/include/asm-arm/arch-ixp2000/platform.h b/include/asm-arm/arch-ixp2000/platform.h
index 52ded516ea5..c0caf3e3e6f 100644
--- a/include/asm-arm/arch-ixp2000/platform.h
+++ b/include/asm-arm/arch-ixp2000/platform.h
@@ -115,6 +115,7 @@ static inline unsigned int ixp2000_is_pcimaster(void)
}
void ixp2000_map_io(void);
+void ixp2000_uart_init(void);
void ixp2000_init_irq(void);
void ixp2000_init_time(unsigned long);
unsigned long ixp2000_gettimeoffset(void);
diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h
index c27b9d3079a..7495026e2c1 100644
--- a/include/asm-arm/arch-ixp4xx/io.h
+++ b/include/asm-arm/arch-ixp4xx/io.h
@@ -3,7 +3,7 @@
*
* Author: Deepak Saxena <dsaxena@plexity.net>
*
- * Copyright (C) 2002-2004 MontaVista Software, Inc.
+ * Copyright (C) 2002-2005 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -383,6 +383,180 @@ __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
*vaddr++ = inl(io_addr);
}
+#define __is_io_address(p) (((unsigned long)p >= 0x0) && \
+ ((unsigned long)p <= 0x0000ffff))
+static inline unsigned int
+__ixp4xx_ioread8(void __iomem *port)
+{
+ if (__is_io_address(port))
+ return (unsigned int)__ixp4xx_inb((unsigned int)port);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ return (unsigned int)__raw_readb((u32)port);
+#else
+ return (unsigned int)__ixp4xx_readb((u32)port);
+#endif
+}
+
+static inline void
+__ixp4xx_ioread8_rep(u32 port, u8 *vaddr, u32 count)
+{
+ if (__is_io_address(port))
+ __ixp4xx_insb(port, vaddr, count);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_readsb((void __iomem *)port, vaddr, count);
+#else
+ __ixp4xx_readsb(port, vaddr, count);
+#endif
+}
+
+static inline unsigned int
+__ixp4xx_ioread16(void __iomem *port)
+{
+ if (__is_io_address(port))
+ return (unsigned int)__ixp4xx_inw((unsigned int)port);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ return le16_to_cpu(__raw_readw((u32)port));
+#else
+ return (unsigned int)__ixp4xx_readw((u32)port);
+#endif
+}
+
+static inline void
+__ixp4xx_ioread16_rep(u32 port, u16 *vaddr, u32 count)
+{
+ if (__is_io_address(port))
+ __ixp4xx_insw(port, vaddr, count);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_readsw((void __iomem *)port, vaddr, count);
+#else
+ __ixp4xx_readsw(port, vaddr, count);
+#endif
+}
+
+static inline unsigned int
+__ixp4xx_ioread32(void __iomem *port)
+{
+ if (__is_io_address(port))
+ return (unsigned int)__ixp4xx_inl((unsigned int)port);
+ else {
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ return le32_to_cpu(__raw_readl((u32)port));
+#else
+ return (unsigned int)__ixp4xx_readl((u32)port);
+#endif
+ }
+}
+
+static inline void
+__ixp4xx_ioread32_rep(u32 port, u32 *vaddr, u32 count)
+{
+ if (__is_io_address(port))
+ __ixp4xx_insl(port, vaddr, count);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_readsl((void __iomem *)port, vaddr, count);
+#else
+ __ixp4xx_readsl(port, vaddr, count);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite8(u8 value, void __iomem *port)
+{
+ if (__is_io_address(port))
+ __ixp4xx_outb(value, (unsigned int)port);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_writeb(value, (u32)port);
+#else
+ __ixp4xx_writeb(value, (u32)port);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite8_rep(u32 port, u8 *vaddr, u32 count)
+{
+ if (__is_io_address(port))
+ __ixp4xx_outsb(port, vaddr, count);
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_writesb((void __iomem *)port, vaddr, count);
+#else
+ __ixp4xx_writesb(port, vaddr, count);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite16(u16 value, void __iomem *port)
+{
+ if (__is_io_address(port))
+ __ixp4xx_outw(value, (unsigned int)port);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_writew(cpu_to_le16(value), (u32)port);
+#else
+ __ixp4xx_writew(value, (u32)port);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite16_rep(u32 port, u16 *vaddr, u32 count)
+{
+ if (__is_io_address(port))
+ __ixp4xx_outsw(port, vaddr, count);
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_readsw((void __iomem *)port, vaddr, count);
+#else
+ __ixp4xx_writesw(port, vaddr, count);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite32(u32 value, void __iomem *port)
+{
+ if (__is_io_address(port))
+ __ixp4xx_outl(value, (unsigned int)port);
+ else
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_writel(cpu_to_le32(value), (u32)port);
+#else
+ __ixp4xx_writel(value, (u32)port);
+#endif
+}
+
+static inline void
+__ixp4xx_iowrite32_rep(u32 port, u32 *vaddr, u32 count)
+{
+ if (__is_io_address(port))
+ __ixp4xx_outsl(port, vaddr, count);
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+ __raw_readsl((void __iomem *)port, vaddr, count);
+#else
+ __ixp4xx_outsl(port, vaddr, count);
+#endif
+}
+
+#define ioread8(p) __ixp4xx_ioread8(p)
+#define ioread16(p) __ixp4xx_ioread16(p)
+#define ioread32(p) __ixp4xx_ioread32(p)
+
+#define ioread8_rep(p, v, c) __ixp4xx_ioread8_rep(p, v, c)
+#define ioread16_rep(p, v, c) __ixp4xx_ioread16_rep(p, v, c)
+#define ioread32_rep(p, v, c) __ixp4xx_ioread32_rep(p, v, c)
+
+#define iowrite8(v,p) __ixp4xx_iowrite8(v,p)
+#define iowrite16(v,p) __ixp4xx_iowrite16(v,p)
+#define iowrite32(v,p) __ixp4xx_iowrite32(v,p)
+
+#define iowrite8_rep(p, v, c) __ixp4xx_iowrite8_rep(p, v, c)
+#define iowrite16_rep(p, v, c) __ixp4xx_iowrite16_rep(p, v, c)
+#define iowrite32_rep(p, v, c) __ixp4xx_iowrite32_rep(p, v, c)
+
+#define ioport_map(port, nr) ((void __iomem*)port)
+#define ioport_unmap(addr)
#endif // __ASM_ARM_ARCH_IO_H
diff --git a/include/asm-arm/arch-omap/board-h2.h b/include/asm-arm/arch-omap/board-h2.h
index 60f002b7298..39ca5a31aee 100644
--- a/include/asm-arm/arch-omap/board-h2.h
+++ b/include/asm-arm/arch-omap/board-h2.h
@@ -34,11 +34,6 @@
/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
#define OMAP1610_ETHR_START 0x04000300
-/* Intel STRATA NOR flash at CS3 or CS2B(NAND Boot) */
-#define OMAP_NOR_FLASH_SIZE SZ_32M
-#define OMAP_NOR_FLASH_START1 0x0C000000 /* CS3 */
-#define OMAP_NOR_FLASH_START2 0x0A000000 /* CS2B */
-
/* Samsung NAND flash at CS2B or CS3(NAND Boot) */
#define OMAP_NAND_FLASH_START1 0x0A000000 /* CS2B */
#define OMAP_NAND_FLASH_START2 0x0C000000 /* CS3 */
diff --git a/include/asm-arm/arch-omap/board-h3.h b/include/asm-arm/arch-omap/board-h3.h
index e4d1cd23173..1b12c1dcc2f 100644
--- a/include/asm-arm/arch-omap/board-h3.h
+++ b/include/asm-arm/arch-omap/board-h3.h
@@ -30,11 +30,6 @@
/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
#define OMAP1710_ETHR_START 0x04000300
-/* Intel STRATA NOR flash at CS3 or CS2B(NAND Boot) */
-#define OMAP_NOR_FLASH_SIZE SZ_32M
-#define OMAP_NOR_FLASH_START1 0x0C000000 /* CS3 */
-#define OMAP_NOR_FLASH_START2 0x0A000000 /* CS2B */
-
/* Samsung NAND flash at CS2B or CS3(NAND Boot) */
#define OMAP_NAND_FLASH_START1 0x0A000000 /* CS2B */
#define OMAP_NAND_FLASH_START2 0x0C000000 /* CS3 */
diff --git a/include/asm-arm/arch-omap/board-osk.h b/include/asm-arm/arch-omap/board-osk.h
index aaa49a0fbd2..2b1a8a4fe44 100644
--- a/include/asm-arm/arch-omap/board-osk.h
+++ b/include/asm-arm/arch-omap/board-osk.h
@@ -32,10 +32,5 @@
/* At OMAP5912 OSK the Ethernet is directly connected to CS1 */
#define OMAP_OSK_ETHR_START 0x04800300
-/* Micron NOR flash at CS3 mapped to address 0x0 if BM bit is 1 */
-#define OMAP_OSK_NOR_FLASH_BASE 0xD8000000
-#define OMAP_OSK_NOR_FLASH_SIZE SZ_32M
-#define OMAP_OSK_NOR_FLASH_START 0x00000000
-
#endif /* __ASM_ARCH_OMAP_OSK_H */
diff --git a/include/asm-arm/arch-omap/board.h b/include/asm-arm/arch-omap/board.h
index 1cefd60b6f2..95bd625480c 100644
--- a/include/asm-arm/arch-omap/board.h
+++ b/include/asm-arm/arch-omap/board.h
@@ -16,10 +16,11 @@
/* Different peripheral ids */
#define OMAP_TAG_CLOCK 0x4f01
#define OMAP_TAG_MMC 0x4f02
-#define OMAP_TAG_UART 0x4f03
+#define OMAP_TAG_SERIAL_CONSOLE 0x4f03
#define OMAP_TAG_USB 0x4f04
#define OMAP_TAG_LCD 0x4f05
#define OMAP_TAG_GPIO_SWITCH 0x4f06
+#define OMAP_TAG_UART 0x4f07
#define OMAP_TAG_BOOT_REASON 0x4f80
#define OMAP_TAG_FLASH_PART 0x4f81
@@ -35,7 +36,7 @@ struct omap_mmc_config {
s16 mmc1_switch_pin, mmc2_switch_pin;
};
-struct omap_uart_config {
+struct omap_serial_console_config {
u8 console_uart;
u32 console_speed;
};
@@ -82,7 +83,8 @@ struct omap_lcd_config {
*/
#define OMAP_GPIO_SWITCH_TYPE_COVER 0x0000
#define OMAP_GPIO_SWITCH_TYPE_CONNECTION 0x0001
-#define OMAP_GPIO_SWITCH_FLAG_INVERTED 0x0001
+#define OMAP_GPIO_SWITCH_FLAG_INVERTED 0x0001
+#define OMAP_GPIO_SWITCH_FLAG_OUTPUT 0x0002
struct omap_gpio_switch_config {
char name[12];
u16 gpio;
@@ -99,6 +101,10 @@ struct omap_boot_reason_config {
char reason_str[12];
};
+struct omap_uart_config {
+ /* Bit field of UARTs present; bit 0 --> UART1 */
+ unsigned int enabled_uarts;
+};
struct omap_board_config_entry {
u16 tag;
diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h
new file mode 100644
index 00000000000..2a676b4f13b
--- /dev/null
+++ b/include/asm-arm/arch-omap/common.h
@@ -0,0 +1,36 @@
+/*
+ * linux/include/asm-arm/arch-omap/common.h
+ *
+ * Header for code common to all OMAP machines.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
+#define __ARCH_ARM_MACH_OMAP_COMMON_H
+
+struct sys_timer;
+
+extern void omap_map_common_io(void);
+extern struct sys_timer omap_timer;
+extern void omap_serial_init(int ports[]);
+
+#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
index d785248377d..ce114ce5af5 100644
--- a/include/asm-arm/arch-omap/dma.h
+++ b/include/asm-arm/arch-omap/dma.h
@@ -241,6 +241,7 @@ extern void omap_dma_unlink_lch (int lch_head, int lch_queue);
extern dma_addr_t omap_get_dma_src_pos(int lch);
extern dma_addr_t omap_get_dma_dst_pos(int lch);
extern void omap_clear_dma(int lch);
+extern int omap_dma_running(void);
/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
extern int omap_dma_in_1510_mode(void);
diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h
index 37e06c782bd..48258c7f654 100644
--- a/include/asm-arm/arch-omap/hardware.h
+++ b/include/asm-arm/arch-omap/hardware.h
@@ -54,6 +54,19 @@
/*
* ----------------------------------------------------------------------------
+ * Timers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP_MPU_TIMER1_BASE (0xfffec500)
+#define OMAP_MPU_TIMER2_BASE (0xfffec600)
+#define OMAP_MPU_TIMER3_BASE (0xfffec700)
+#define MPU_TIMER_FREE (1 << 6)
+#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
+#define MPU_TIMER_AR (1 << 1)
+#define MPU_TIMER_ST (1 << 0)
+
+/*
+ * ----------------------------------------------------------------------------
* Clocks
* ----------------------------------------------------------------------------
*/
@@ -78,6 +91,7 @@
/* DSP clock control */
#define DSP_CONFIG_REG_BASE (0xe1008000)
+#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
@@ -88,6 +102,7 @@
*/
#define ULPD_REG_BASE (0xfffe0800)
#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
+#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
@@ -268,17 +283,10 @@
* Processor specific defines
* ---------------------------------------------------------------------------
*/
-#ifdef CONFIG_ARCH_OMAP730
-#include "omap730.h"
-#endif
-#ifdef CONFIG_ARCH_OMAP1510
+#include "omap730.h"
#include "omap1510.h"
-#endif
-
-#ifdef CONFIG_ARCH_OMAP16XX
#include "omap16xx.h"
-#endif
/*
* ---------------------------------------------------------------------------
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
index 6701fd9e5f9..0d05a7c957d 100644
--- a/include/asm-arm/arch-omap/irqs.h
+++ b/include/asm-arm/arch-omap/irqs.h
@@ -159,6 +159,7 @@
#define INT_1610_GPIO_BANK3 (41 + IH2_BASE)
#define INT_1610_MMC2 (42 + IH2_BASE)
#define INT_1610_CF (43 + IH2_BASE)
+#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE)
#define INT_1610_GPIO_BANK4 (48 + IH2_BASE)
#define INT_1610_SPI (49 + IH2_BASE)
#define INT_1610_DMA_CH6 (53 + IH2_BASE)
@@ -238,6 +239,8 @@
#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
#define IH_BOARD_BASE (16 + IH_MPUIO_BASE)
+#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
+
#ifndef __ASSEMBLY__
extern void omap_init_irq(void);
#endif
diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h
index 39f99decbb7..5bd3f0097fc 100644
--- a/include/asm-arm/arch-omap/mux.h
+++ b/include/asm-arm/arch-omap/mux.h
@@ -231,7 +231,7 @@ typedef enum {
J19_1610_ETM_D6,
J18_1610_ETM_D7,
- /* OMAP-1610 GPIO */
+ /* OMAP16XX GPIO */
P20_1610_GPIO4,
V9_1610_GPIO7,
W8_1610_GPIO9,
@@ -241,6 +241,9 @@ typedef enum {
AA20_1610_GPIO_41,
W19_1610_GPIO48,
M7_1610_GPIO62,
+ V14_16XX_GPIO37,
+ R9_16XX_GPIO18,
+ L14_16XX_GPIO49,
/* OMAP-1610 uWire */
V19_1610_UWIRE_SCLK,
@@ -285,12 +288,13 @@ typedef enum {
V6_USB2_TXD,
W5_USB2_SE0,
- /* UART1 1610 */
-
+ /* 16XX UART */
R13_1610_UART1_TX,
- V14_1610_UART1_RX,
+ V14_16XX_UART1_RX,
R14_1610_UART1_CTS,
AA15_1610_UART1_RTS,
+ R9_16XX_UART2_RX,
+ L14_16XX_UART3_RX,
/* I2C OMAP-1610 */
I2C_SCL,
@@ -332,7 +336,7 @@ typedef enum {
* Table of various FUNC_MUX and PULL_DWN combinations for each device.
* See also reg_cfg_t above for the lookup table.
*/
-static reg_cfg_set __initdata_or_module
+static const reg_cfg_set __initdata_or_module
reg_cfg_table[] = {
/*
* description mux mode mux pull pull pull pu_pd pu dbg
@@ -455,7 +459,7 @@ MUX_CFG("L19_1610_ETM_D0", 5, 18, 1, 0, 26, 0, 0, 0, 1)
MUX_CFG("J19_1610_ETM_D6", 5, 0, 1, 0, 20, 0, 0, 0, 1)
MUX_CFG("J18_1610_ETM_D7", 5, 27, 1, 0, 19, 0, 0, 0, 1)
-/* OMAP-1610 GPIO */
+/* OMAP16XX GPIO */
MUX_CFG("P20_1610_GPIO4", 6, 27, 0, 1, 7, 0, 1, 1, 1)
MUX_CFG("V9_1610_GPIO7", B, 12, 1, 2, 20, 0, 2, 1, 1)
MUX_CFG("W8_1610_GPIO9", B, 21, 0, 2, 23, 0, 2, 1, 1)
@@ -465,6 +469,9 @@ MUX_CFG("V5_1610_GPIO24", B, 15, 7, 2, 21, 0, 2, 1, 1)
MUX_CFG("AA20_1610_GPIO_41", 9, 9, 7, 1, 31, 0, 1, 1, 1)
MUX_CFG("W19_1610_GPIO48", 8, 15, 7, 1, 23, 1, 1, 0, 1)
MUX_CFG("M7_1610_GPIO62", 10, 0, 0, 4, 24, 0, 4, 0, 1)
+MUX_CFG("V14_16XX_GPIO37", 9, 18, 7, 2, 2, 0, 2, 2, 0)
+MUX_CFG("R9_16XX_GPIO18", C, 18, 7, 3, 0, 0, 3, 0, 0)
+MUX_CFG("L14_16XX_GPIO49", 6, 3, 7, 0, 31, 0, 0, 31, 0)
/* OMAP-1610 uWire */
MUX_CFG("V19_1610_UWIRE_SCLK", 8, 6, 0, 1, 20, 0, 1, 1, 1)
@@ -503,16 +510,17 @@ MUX_CFG("Y10_USB0_SUSP", B, 3, 5, 2, 17, 0, 2, 0, 1)
MUX_CFG("W9_USB2_TXEN", B, 9, 1, NA, 0, 0, NA, 0, 1)
MUX_CFG("AA9_USB2_VP", B, 6, 1, NA, 0, 0, NA, 0, 1)
MUX_CFG("Y5_USB2_RCV", C, 21, 1, NA, 0, 0, NA, 0, 1)
-MUX_CFG("R8_USB2_VM", C, 18, 1, NA, 0, 0, NA, 0, 1)
+MUX_CFG("R9_USB2_VM", C, 18, 1, NA, 0, 0, NA, 0, 1)
MUX_CFG("V6_USB2_TXD", C, 27, 2, NA, 0, 0, NA, 0, 1)
MUX_CFG("W5_USB2_SE0", C, 24, 2, NA, 0, 0, NA, 0, 1)
-
-/* UART1 */
+/* 16XX UART */
MUX_CFG("R13_1610_UART1_TX", A, 12, 6, 2, 10, 0, 2, 10, 1)
-MUX_CFG("V14_1610_UART1_RX", 9, 18, 0, 2, 2, 0, 2, 2, 1)
+MUX_CFG("V14_16XX_UART1_RX", 9, 18, 0, 2, 2, 0, 2, 2, 1)
MUX_CFG("R14_1610_UART1_CTS", 9, 15, 0, 2, 1, 0, 2, 1, 1)
MUX_CFG("AA15_1610_UART1_RTS", 9, 12, 1, 2, 0, 0, 2, 0, 1)
+MUX_CFG("R9_16XX_UART2_RX", C, 18, 0, 3, 0, 0, 3, 0, 1)
+MUX_CFG("L14_16XX_UART3_RX", 6, 3, 0, 0, 31, 0, 0, 31, 1)
/* I2C interface */
MUX_CFG("I2C_SCL", 7, 24, 0, NA, 0, 0, NA, 0, 0)
diff --git a/include/asm-arm/arch-omap/omap16xx.h b/include/asm-arm/arch-omap/omap16xx.h
index 88b1fe43ae9..38a9b95e6a3 100644
--- a/include/asm-arm/arch-omap/omap16xx.h
+++ b/include/asm-arm/arch-omap/omap16xx.h
@@ -183,5 +183,37 @@
#define OMAP16XX_PWL_ENABLE (OMAP16XX_PWL_BASE + 0x00)
#define OMAP16XX_PWL_CLK_ENABLE (OMAP16XX_PWL_BASE + 0x04)
+/*
+ * ---------------------------------------------------------------------------
+ * Watchdog timer
+ * ---------------------------------------------------------------------------
+ */
+
+/* 32-bit Watchdog timer in OMAP 16XX */
+#define OMAP_16XX_WATCHDOG_BASE (0xfffeb000)
+#define OMAP_16XX_WIDR (OMAP_16XX_WATCHDOG_BASE + 0x00)
+#define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10)
+#define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14)
+#define OMAP_16XX_WCLR (OMAP_16XX_WATCHDOG_BASE + 0x24)
+#define OMAP_16XX_WCRR (OMAP_16XX_WATCHDOG_BASE + 0x28)
+#define OMAP_16XX_WLDR (OMAP_16XX_WATCHDOG_BASE + 0x2c)
+#define OMAP_16XX_WTGR (OMAP_16XX_WATCHDOG_BASE + 0x30)
+#define OMAP_16XX_WWPS (OMAP_16XX_WATCHDOG_BASE + 0x34)
+#define OMAP_16XX_WSPR (OMAP_16XX_WATCHDOG_BASE + 0x48)
+
+#define WCLR_PRE_SHIFT 5
+#define WCLR_PTV_SHIFT 2
+
+#define WWPS_W_PEND_WSPR (1 << 4)
+#define WWPS_W_PEND_WTGR (1 << 3)
+#define WWPS_W_PEND_WLDR (1 << 2)
+#define WWPS_W_PEND_WCRR (1 << 1)
+#define WWPS_W_PEND_WCLR (1 << 0)
+
+#define WSPR_ENABLE_0 (0x0000bbbb)
+#define WSPR_ENABLE_1 (0x00004444)
+#define WSPR_DISABLE_0 (0x0000aaaa)
+#define WSPR_DISABLE_1 (0x00005555)
+
#endif /* __ASM_ARCH_OMAP16XX_H */
diff --git a/include/asm-arm/arch-omap/system.h b/include/asm-arm/arch-omap/system.h
index 17a2c4825f0..ff37bc27e60 100644
--- a/include/asm-arm/arch-omap/system.h
+++ b/include/asm-arm/arch-omap/system.h
@@ -5,7 +5,9 @@
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <linux/config.h>
+#include <asm/mach-types.h>
#include <asm/arch/hardware.h>
+#include <asm/mach-types.h>
static inline void arch_idle(void)
{
@@ -14,7 +16,24 @@ static inline void arch_idle(void)
static inline void arch_reset(char mode)
{
- omap_writew(1, ARM_RSTCT1);
+
+#ifdef CONFIG_ARCH_OMAP16XX
+ /*
+ * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
+ * "Global Software Reset Affects Traffic Controller Frequency".
+ */
+ if (cpu_is_omap5912()) {
+ omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4),
+ DPLL_CTL);
+ omap_writew(0x8, ARM_RSTCT1);
+ }
+#endif
+#ifdef CONFIG_MACH_VOICEBLUE
+ if (machine_is_voiceblue())
+ voiceblue_reset();
+ else
+#endif
+ omap_writew(1, ARM_RSTCT1);
}
#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-13 15:43:26 +0000