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-rw-r--r--include/asm-avr32/arch-at32ap/at32ap700x.h (renamed from include/asm-avr32/arch-at32ap/at32ap7000.h)8
-rw-r--r--include/asm-avr32/arch-at32ap/cpu.h3
-rw-r--r--include/asm-avr32/arch-at32ap/gpio.h34
-rw-r--r--include/asm-avr32/arch-at32ap/io.h4
-rw-r--r--include/asm-avr32/arch-at32ap/irq.h4
-rw-r--r--include/asm-avr32/cacheflush.h19
-rw-r--r--include/asm-avr32/delay.h2
-rw-r--r--include/asm-avr32/irq.h5
-rw-r--r--include/asm-avr32/kdebug.h1
-rw-r--r--include/asm-avr32/ocd.h597
-rw-r--r--include/asm-avr32/pgalloc.h6
-rw-r--r--include/asm-avr32/processor.h17
-rw-r--r--include/asm-avr32/ptrace.h19
-rw-r--r--include/asm-avr32/setup.h2
-rw-r--r--include/asm-avr32/socket.h2
-rw-r--r--include/asm-avr32/sysreg.h2
-rw-r--r--include/asm-avr32/system.h4
-rw-r--r--include/asm-avr32/thread_info.h26
-rw-r--r--include/asm-avr32/timex.h3
-rw-r--r--include/asm-avr32/unistd.h2
20 files changed, 641 insertions, 119 deletions
diff --git a/include/asm-avr32/arch-at32ap/at32ap7000.h b/include/asm-avr32/arch-at32ap/at32ap700x.h
index 3914d7b94ff..31e48b0e732 100644
--- a/include/asm-avr32/arch-at32ap/at32ap7000.h
+++ b/include/asm-avr32/arch-at32ap/at32ap700x.h
@@ -7,14 +7,12 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
-#ifndef __ASM_ARCH_AT32AP7000_H__
-#define __ASM_ARCH_AT32AP7000_H__
+#ifndef __ASM_ARCH_AT32AP700X_H__
+#define __ASM_ARCH_AT32AP700X_H__
#define GPIO_PERIPH_A 0
#define GPIO_PERIPH_B 1
-#define NR_GPIO_CONTROLLERS 4
-
/*
* Pin numbers identifying specific GPIO pins on the chip. They can
* also be converted to IRQ numbers by passing them through
@@ -32,4 +30,4 @@
#define GPIO_PIN_PD(N) (GPIO_PIOD_BASE + (N))
#define GPIO_PIN_PE(N) (GPIO_PIOE_BASE + (N))
-#endif /* __ASM_ARCH_AT32AP7000_H__ */
+#endif /* __ASM_ARCH_AT32AP700X_H__ */
diff --git a/include/asm-avr32/arch-at32ap/cpu.h b/include/asm-avr32/arch-at32ap/cpu.h
index a762f42cbb7..44d0bfa1f40 100644
--- a/include/asm-avr32/arch-at32ap/cpu.h
+++ b/include/asm-avr32/arch-at32ap/cpu.h
@@ -14,7 +14,7 @@
* Only AT32AP7000 is defined for now. We can identify the specific
* chip at runtime, but I'm not sure if it's really worth it.
*/
-#ifdef CONFIG_CPU_AT32AP7000
+#ifdef CONFIG_CPU_AT32AP700X
# define cpu_is_at32ap7000() (1)
#else
# define cpu_is_at32ap7000() (0)
@@ -30,5 +30,6 @@
#define cpu_is_at91sam9261() (0)
#define cpu_is_at91sam9263() (0)
#define cpu_is_at91sam9rl() (0)
+#define cpu_is_at91cap9() (0)
#endif /* __ASM_ARCH_CPU_H */
diff --git a/include/asm-avr32/arch-at32ap/gpio.h b/include/asm-avr32/arch-at32ap/gpio.h
index af7f9535bab..0180f584ef0 100644
--- a/include/asm-avr32/arch-at32ap/gpio.h
+++ b/include/asm-avr32/arch-at32ap/gpio.h
@@ -5,20 +5,36 @@
#include <asm/irq.h>
-/* Arch-neutral GPIO API */
-int __must_check gpio_request(unsigned int gpio, const char *label);
-void gpio_free(unsigned int gpio);
+/* Some GPIO chips can manage IRQs; some can't. The exact numbers can
+ * be changed if needed, but for the moment they're not configurable.
+ */
+#define ARCH_NR_GPIOS (NR_GPIO_IRQS + 2 * 32)
-int gpio_direction_input(unsigned int gpio);
-int gpio_direction_output(unsigned int gpio, int value);
-int gpio_get_value(unsigned int gpio);
-void gpio_set_value(unsigned int gpio, int value);
-#include <asm-generic/gpio.h> /* cansleep wrappers */
+/* Arch-neutral GPIO API, supporting both "native" and external GPIOs. */
+#include <asm-generic/gpio.h>
+
+static inline int gpio_get_value(unsigned int gpio)
+{
+ return __gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned int gpio, int value)
+{
+ __gpio_set_value(gpio, value);
+}
+
+static inline int gpio_cansleep(unsigned int gpio)
+{
+ return __gpio_cansleep(gpio);
+}
+
static inline int gpio_to_irq(unsigned int gpio)
{
- return gpio + GPIO_IRQ_BASE;
+ if (gpio < NR_GPIO_IRQS)
+ return gpio + GPIO_IRQ_BASE;
+ return -EINVAL;
}
static inline int irq_to_gpio(unsigned int irq)
diff --git a/include/asm-avr32/arch-at32ap/io.h b/include/asm-avr32/arch-at32ap/io.h
index ee59e401f04..4ec6abc68ea 100644
--- a/include/asm-avr32/arch-at32ap/io.h
+++ b/include/asm-avr32/arch-at32ap/io.h
@@ -4,7 +4,7 @@
/* For "bizarre" halfword swapping */
#include <linux/byteorder/swabb.h>
-#if defined(CONFIG_AP7000_32_BIT_SMC)
+#if defined(CONFIG_AP700X_32_BIT_SMC)
# define __swizzle_addr_b(addr) (addr ^ 3UL)
# define __swizzle_addr_w(addr) (addr ^ 2UL)
# define __swizzle_addr_l(addr) (addr)
@@ -14,7 +14,7 @@
# define __mem_ioswabb(a, x) (x)
# define __mem_ioswabw(a, x) swab16(x)
# define __mem_ioswabl(a, x) swab32(x)
-#elif defined(CONFIG_AP7000_16_BIT_SMC)
+#elif defined(CONFIG_AP700X_16_BIT_SMC)
# define __swizzle_addr_b(addr) (addr ^ 1UL)
# define __swizzle_addr_w(addr) (addr)
# define __swizzle_addr_l(addr) (addr)
diff --git a/include/asm-avr32/arch-at32ap/irq.h b/include/asm-avr32/arch-at32ap/irq.h
index 5adffab9a57..608e350368c 100644
--- a/include/asm-avr32/arch-at32ap/irq.h
+++ b/include/asm-avr32/arch-at32ap/irq.h
@@ -3,11 +3,11 @@
#define EIM_IRQ_BASE NR_INTERNAL_IRQS
#define NR_EIM_IRQS 32
-
#define AT32_EXTINT(n) (EIM_IRQ_BASE + (n))
#define GPIO_IRQ_BASE (EIM_IRQ_BASE + NR_EIM_IRQS)
-#define NR_GPIO_IRQS (5 * 32)
+#define NR_GPIO_CTLR (5 /*internal*/ + 1 /*external*/)
+#define NR_GPIO_IRQS (NR_GPIO_CTLR * 32)
#define NR_IRQS (GPIO_IRQ_BASE + NR_GPIO_IRQS)
diff --git a/include/asm-avr32/cacheflush.h b/include/asm-avr32/cacheflush.h
index dfaaa88cd41..670674749b2 100644
--- a/include/asm-avr32/cacheflush.h
+++ b/include/asm-avr32/cacheflush.h
@@ -116,15 +116,16 @@ extern void flush_icache_page(struct vm_area_struct *vma, struct page *page);
* flush with all configurations.
*/
extern void flush_icache_range(unsigned long start, unsigned long end);
-extern void flush_icache_user_range(struct vm_area_struct *vma,
- struct page *page,
- unsigned long addr, int len);
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) do { \
- memcpy(dst, src, len); \
- flush_icache_user_range(vma, page, vaddr, len); \
-} while(0)
-#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
- memcpy(dst, src, len)
+extern void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
+ unsigned long vaddr, void *dst, const void *src,
+ unsigned long len);
+
+static inline void copy_from_user_page(struct vm_area_struct *vma,
+ struct page *page, unsigned long vaddr, void *dst,
+ const void *src, unsigned long len)
+{
+ memcpy(dst, src, len);
+}
#endif /* __ASM_AVR32_CACHEFLUSH_H */
diff --git a/include/asm-avr32/delay.h b/include/asm-avr32/delay.h
index cc3b2e3343b..a0ed9a9839a 100644
--- a/include/asm-avr32/delay.h
+++ b/include/asm-avr32/delay.h
@@ -12,7 +12,7 @@ extern void __bad_ndelay(void);
extern void __udelay(unsigned long usecs);
extern void __ndelay(unsigned long nsecs);
-extern void __const_udelay(unsigned long usecs);
+extern void __const_udelay(unsigned long xloops);
extern void __delay(unsigned long loops);
#define udelay(n) (__builtin_constant_p(n) ? \
diff --git a/include/asm-avr32/irq.h b/include/asm-avr32/irq.h
index 83e6549d778..9315724c059 100644
--- a/include/asm-avr32/irq.h
+++ b/include/asm-avr32/irq.h
@@ -11,4 +11,9 @@
#define irq_canonicalize(i) (i)
+#ifndef __ASSEMBLER__
+int nmi_enable(void);
+void nmi_disable(void);
+#endif
+
#endif /* __ASM_AVR32_IOCTLS_H */
diff --git a/include/asm-avr32/kdebug.h b/include/asm-avr32/kdebug.h
index fd7e99046b2..ca4f9542365 100644
--- a/include/asm-avr32/kdebug.h
+++ b/include/asm-avr32/kdebug.h
@@ -5,6 +5,7 @@
enum die_val {
DIE_BREAKPOINT,
DIE_SSTEP,
+ DIE_NMI,
};
#endif /* __ASM_AVR32_KDEBUG_H */
diff --git a/include/asm-avr32/ocd.h b/include/asm-avr32/ocd.h
index 46f73180a12..6bef0949023 100644
--- a/include/asm-avr32/ocd.h
+++ b/include/asm-avr32/ocd.h
@@ -1,7 +1,7 @@
/*
- * AVR32 OCD Registers
+ * AVR32 OCD Interface and register definitions
*
- * Copyright (C) 2004-2006 Atmel Corporation
+ * Copyright (C) 2004-2007 Atmel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -10,69 +10,534 @@
#ifndef __ASM_AVR32_OCD_H
#define __ASM_AVR32_OCD_H
-/* Debug Registers */
-#define DBGREG_DID 0
-#define DBGREG_DC 8
-#define DBGREG_DS 16
-#define DBGREG_RWCS 28
-#define DBGREG_RWA 36
-#define DBGREG_RWD 40
-#define DBGREG_WT 44
-#define DBGREG_DTC 52
-#define DBGREG_DTSA0 56
-#define DBGREG_DTSA1 60
-#define DBGREG_DTEA0 72
-#define DBGREG_DTEA1 76
-#define DBGREG_BWC0A 88
-#define DBGREG_BWC0B 92
-#define DBGREG_BWC1A 96
-#define DBGREG_BWC1B 100
-#define DBGREG_BWC2A 104
-#define DBGREG_BWC2B 108
-#define DBGREG_BWC3A 112
-#define DBGREG_BWC3B 116
-#define DBGREG_BWA0A 120
-#define DBGREG_BWA0B 124
-#define DBGREG_BWA1A 128
-#define DBGREG_BWA1B 132
-#define DBGREG_BWA2A 136
-#define DBGREG_BWA2B 140
-#define DBGREG_BWA3A 144
-#define DBGREG_BWA3B 148
-#define DBGREG_BWD3A 153
-#define DBGREG_BWD3B 156
-
-#define DBGREG_PID 284
-
-#define SABAH_OCD 0x01
-#define SABAH_ICACHE 0x02
-#define SABAH_MEM_CACHED 0x04
-#define SABAH_MEM_UNCACHED 0x05
-
-/* Fields in the Development Control register */
-#define DC_SS_BIT 8
-
-#define DC_SS (1 << DC_SS_BIT)
-#define DC_DBE (1 << 13)
-#define DC_RID (1 << 27)
-#define DC_ORP (1 << 28)
-#define DC_MM (1 << 29)
-#define DC_RES (1 << 30)
-
-/* Fields in the Development Status register */
-#define DS_SSS (1 << 0)
-#define DS_SWB (1 << 1)
-#define DS_HWB (1 << 2)
-#define DS_BP_SHIFT 8
-#define DS_BP_MASK (0xff << DS_BP_SHIFT)
-
-#define __mfdr(addr) \
-({ \
- register unsigned long value; \
- asm volatile("mfdr %0, %1" : "=r"(value) : "i"(addr)); \
- value; \
-})
-#define __mtdr(addr, value) \
- asm volatile("mtdr %0, %1" : : "i"(addr), "r"(value))
+/* OCD Register offsets. Abbreviations used below:
+ *
+ * BP Breakpoint
+ * Comm Communication
+ * DT Data Trace
+ * PC Program Counter
+ * PID Process ID
+ * R/W Read/Write
+ * WP Watchpoint
+ */
+#define OCD_DID 0x0000 /* Device ID */
+#define OCD_DC 0x0008 /* Development Control */
+#define OCD_DS 0x0010 /* Development Status */
+#define OCD_RWCS 0x001c /* R/W Access Control */
+#define OCD_RWA 0x0024 /* R/W Access Address */
+#define OCD_RWD 0x0028 /* R/W Access Data */
+#define OCD_WT 0x002c /* Watchpoint Trigger */
+#define OCD_DTC 0x0034 /* Data Trace Control */
+#define OCD_DTSA0 0x0038 /* DT Start Addr Channel 0 */
+#define OCD_DTSA1 0x003c /* DT Start Addr Channel 1 */
+#define OCD_DTEA0 0x0048 /* DT End Addr Channel 0 */
+#define OCD_DTEA1 0x004c /* DT End Addr Channel 1 */
+#define OCD_BWC0A 0x0058 /* PC BP/WP Control 0A */
+#define OCD_BWC0B 0x005c /* PC BP/WP Control 0B */
+#define OCD_BWC1A 0x0060 /* PC BP/WP Control 1A */
+#define OCD_BWC1B 0x0064 /* PC BP/WP Control 1B */
+#define OCD_BWC2A 0x0068 /* PC BP/WP Control 2A */
+#define OCD_BWC2B 0x006c /* PC BP/WP Control 2B */
+#define OCD_BWC3A 0x0070 /* Data BP/WP Control 3A */
+#define OCD_BWC3B 0x0074 /* Data BP/WP Control 3B */
+#define OCD_BWA0A 0x0078 /* PC BP/WP Address 0A */
+#define OCD_BWA0B 0x007c /* PC BP/WP Address 0B */
+#define OCD_BWA1A 0x0080 /* PC BP/WP Address 1A */
+#define OCD_BWA1B 0x0084 /* PC BP/WP Address 1B */
+#define OCD_BWA2A 0x0088 /* PC BP/WP Address 2A */
+#define OCD_BWA2B 0x008c /* PC BP/WP Address 2B */
+#define OCD_BWA3A 0x0090 /* Data BP/WP Address 3A */
+#define OCD_BWA3B 0x0094 /* Data BP/WP Address 3B */
+#define OCD_NXCFG 0x0100 /* Nexus Configuration */
+#define OCD_DINST 0x0104 /* Debug Instruction */
+#define OCD_DPC 0x0108 /* Debug Program Counter */
+#define OCD_CPUCM 0x010c /* CPU Control Mask */
+#define OCD_DCCPU 0x0110 /* Debug Comm CPU */
+#define OCD_DCEMU 0x0114 /* Debug Comm Emulator */
+#define OCD_DCSR 0x0118 /* Debug Comm Status */
+#define OCD_PID 0x011c /* Ownership Trace PID */
+#define OCD_EPC0 0x0120 /* Event Pair Control 0 */
+#define OCD_EPC1 0x0124 /* Event Pair Control 1 */
+#define OCD_EPC2 0x0128 /* Event Pair Control 2 */
+#define OCD_EPC3 0x012c /* Event Pair Control 3 */
+#define OCD_AXC 0x0130 /* AUX port Control */
+
+/* Bits in DID */
+#define OCD_DID_MID_START 1
+#define OCD_DID_MID_SIZE 11
+#define OCD_DID_PN_START 12
+#define OCD_DID_PN_SIZE 16
+#define OCD_DID_RN_START 28
+#define OCD_DID_RN_SIZE 4
+
+/* Bits in DC */
+#define OCD_DC_TM_START 0
+#define OCD_DC_TM_SIZE 2
+#define OCD_DC_EIC_START 3
+#define OCD_DC_EIC_SIZE 2
+#define OCD_DC_OVC_START 5
+#define OCD_DC_OVC_SIZE 3
+#define OCD_DC_SS_BIT 8
+#define OCD_DC_DBR_BIT 12
+#define OCD_DC_DBE_BIT 13
+#define OCD_DC_EOS_START 20
+#define OCD_DC_EOS_SIZE 2
+#define OCD_DC_SQA_BIT 22
+#define OCD_DC_IRP_BIT 23
+#define OCD_DC_IFM_BIT 24
+#define OCD_DC_TOZ_BIT 25
+#define OCD_DC_TSR_BIT 26
+#define OCD_DC_RID_BIT 27
+#define OCD_DC_ORP_BIT 28
+#define OCD_DC_MM_BIT 29
+#define OCD_DC_RES_BIT 30
+#define OCD_DC_ABORT_BIT 31
+
+/* Bits in DS */
+#define OCD_DS_SSS_BIT 0
+#define OCD_DS_SWB_BIT 1
+#define OCD_DS_HWB_BIT 2
+#define OCD_DS_HWE_BIT 3
+#define OCD_DS_STP_BIT 4
+#define OCD_DS_DBS_BIT 5
+#define OCD_DS_BP_START 8
+#define OCD_DS_BP_SIZE 8
+#define OCD_DS_INC_BIT 24
+#define OCD_DS_BOZ_BIT 25
+#define OCD_DS_DBA_BIT 26
+#define OCD_DS_EXB_BIT 27
+#define OCD_DS_NTBF_BIT 28
+
+/* Bits in RWCS */
+#define OCD_RWCS_DV_BIT 0
+#define OCD_RWCS_ERR_BIT 1
+#define OCD_RWCS_CNT_START 2
+#define OCD_RWCS_CNT_SIZE 14
+#define OCD_RWCS_CRC_BIT 19
+#define OCD_RWCS_NTBC_START 20
+#define OCD_RWCS_NTBC_SIZE 2
+#define OCD_RWCS_NTE_BIT 22
+#define OCD_RWCS_NTAP_BIT 23
+#define OCD_RWCS_WRAPPED_BIT 24
+#define OCD_RWCS_CCTRL_START 25
+#define OCD_RWCS_CCTRL_SIZE 2
+#define OCD_RWCS_SZ_START 27
+#define OCD_RWCS_SZ_SIZE 3
+#define OCD_RWCS_RW_BIT 30
+#define OCD_RWCS_AC_BIT 31
+
+/* Bits in RWA */
+#define OCD_RWA_RWA_START 0
+#define OCD_RWA_RWA_SIZE 32
+
+/* Bits in RWD */
+#define OCD_RWD_RWD_START 0
+#define OCD_RWD_RWD_SIZE 32
+
+/* Bits in WT */
+#define OCD_WT_DTE_START 20
+#define OCD_WT_DTE_SIZE 3
+#define OCD_WT_DTS_START 23
+#define OCD_WT_DTS_SIZE 3
+#define OCD_WT_PTE_START 26
+#define OCD_WT_PTE_SIZE 3
+#define OCD_WT_PTS_START 29
+#define OCD_WT_PTS_SIZE 3
+
+/* Bits in DTC */
+#define OCD_DTC_T0WP_BIT 0
+#define OCD_DTC_T1WP_BIT 1
+#define OCD_DTC_ASID0EN_BIT 2
+#define OCD_DTC_ASID0_START 3
+#define OCD_DTC_ASID0_SIZE 8
+#define OCD_DTC_ASID1EN_BIT 11
+#define OCD_DTC_ASID1_START 12
+#define OCD_DTC_ASID1_SIZE 8
+#define OCD_DTC_RWT1_START 28
+#define OCD_DTC_RWT1_SIZE 2
+#define OCD_DTC_RWT0_START 30
+#define OCD_DTC_RWT0_SIZE 2
+
+/* Bits in DTSA0 */
+#define OCD_DTSA0_DTSA_START 0
+#define OCD_DTSA0_DTSA_SIZE 32
+
+/* Bits in DTSA1 */
+#define OCD_DTSA1_DTSA_START 0
+#define OCD_DTSA1_DTSA_SIZE 32
+
+/* Bits in DTEA0 */
+#define OCD_DTEA0_DTEA_START 0
+#define OCD_DTEA0_DTEA_SIZE 32
+
+/* Bits in DTEA1 */
+#define OCD_DTEA1_DTEA_START 0
+#define OCD_DTEA1_DTEA_SIZE 32
+
+/* Bits in BWC0A */
+#define OCD_BWC0A_ASIDEN_BIT 0
+#define OCD_BWC0A_ASID_START 1
+#define OCD_BWC0A_ASID_SIZE 8
+#define OCD_BWC0A_EOC_BIT 14
+#define OCD_BWC0A_AME_BIT 25
+#define OCD_BWC0A_BWE_START 30
+#define OCD_BWC0A_BWE_SIZE 2
+
+/* Bits in BWC0B */
+#define OCD_BWC0B_ASIDEN_BIT 0
+#define OCD_BWC0B_ASID_START 1
+#define OCD_BWC0B_ASID_SIZE 8
+#define OCD_BWC0B_EOC_BIT 14
+#define OCD_BWC0B_AME_BIT 25
+#define OCD_BWC0B_BWE_START 30
+#define OCD_BWC0B_BWE_SIZE 2
+
+/* Bits in BWC1A */
+#define OCD_BWC1A_ASIDEN_BIT 0
+#define OCD_BWC1A_ASID_START 1
+#define OCD_BWC1A_ASID_SIZE 8
+#define OCD_BWC1A_EOC_BIT 14
+#define OCD_BWC1A_AME_BIT 25
+#define OCD_BWC1A_BWE_START 30
+#define OCD_BWC1A_BWE_SIZE 2
+
+/* Bits in BWC1B */
+#define OCD_BWC1B_ASIDEN_BIT 0
+#define OCD_BWC1B_ASID_START 1
+#define OCD_BWC1B_ASID_SIZE 8
+#define OCD_BWC1B_EOC_BIT 14
+#define OCD_BWC1B_AME_BIT 25
+#define OCD_BWC1B_BWE_START 30
+#define OCD_BWC1B_BWE_SIZE 2
+
+/* Bits in BWC2A */
+#define OCD_BWC2A_ASIDEN_BIT 0
+#define OCD_BWC2A_ASID_START 1
+#define OCD_BWC2A_ASID_SIZE 8
+#define OCD_BWC2A_EOC_BIT 14
+#define OCD_BWC2A_AMB_START 20
+#define OCD_BWC2A_AMB_SIZE 5
+#define OCD_BWC2A_AME_BIT 25
+#define OCD_BWC2A_BWE_START 30
+#define OCD_BWC2A_BWE_SIZE 2
+
+/* Bits in BWC2B */
+#define OCD_BWC2B_ASIDEN_BIT 0
+#define OCD_BWC2B_ASID_START 1
+#define OCD_BWC2B_ASID_SIZE 8
+#define OCD_BWC2B_EOC_BIT 14
+#define OCD_BWC2B_AME_BIT 25
+#define OCD_BWC2B_BWE_START 30
+#define OCD_BWC2B_BWE_SIZE 2
+
+/* Bits in BWC3A */
+#define OCD_BWC3A_ASIDEN_BIT 0
+#define OCD_BWC3A_ASID_START 1
+#define OCD_BWC3A_ASID_SIZE 8
+#define OCD_BWC3A_SIZE_START 9
+#define OCD_BWC3A_SIZE_SIZE 3
+#define OCD_BWC3A_EOC_BIT 14
+#define OCD_BWC3A_BWO_START 16
+#define OCD_BWC3A_BWO_SIZE 2
+#define OCD_BWC3A_BME_START 20
+#define OCD_BWC3A_BME_SIZE 4
+#define OCD_BWC3A_BRW_START 28
+#define OCD_BWC3A_BRW_SIZE 2
+#define OCD_BWC3A_BWE_START 30
+#define OCD_BWC3A_BWE_SIZE 2
+
+/* Bits in BWC3B */
+#define OCD_BWC3B_ASIDEN_BIT 0
+#define OCD_BWC3B_ASID_START 1
+#define OCD_BWC3B_ASID_SIZE 8
+#define OCD_BWC3B_SIZE_START 9
+#define OCD_BWC3B_SIZE_SIZE 3
+#define OCD_BWC3B_EOC_BIT 14
+#define OCD_BWC3B_BWO_START 16
+#define OCD_BWC3B_BWO_SIZE 2
+#define OCD_BWC3B_BME_START 20
+#define OCD_BWC3B_BME_SIZE 4
+#define OCD_BWC3B_BRW_START 28
+#define OCD_BWC3B_BRW_SIZE 2
+#define OCD_BWC3B_BWE_START 30
+#define OCD_BWC3B_BWE_SIZE 2
+
+/* Bits in BWA0A */
+#define OCD_BWA0A_BWA_START 0
+#define OCD_BWA0A_BWA_SIZE 32
+
+/* Bits in BWA0B */
+#define OCD_BWA0B_BWA_START 0
+#define OCD_BWA0B_BWA_SIZE 32
+
+/* Bits in BWA1A */
+#define OCD_BWA1A_BWA_START 0
+#define OCD_BWA1A_BWA_SIZE 32
+
+/* Bits in BWA1B */
+#define OCD_BWA1B_BWA_START 0
+#define OCD_BWA1B_BWA_SIZE 32
+
+/* Bits in BWA2A */
+#define OCD_BWA2A_BWA_START 0
+#define OCD_BWA2A_BWA_SIZE 32
+
+/* Bits in BWA2B */
+#define OCD_BWA2B_BWA_START 0
+#define OCD_BWA2B_BWA_SIZE 32
+
+/* Bits in BWA3A */
+#define OCD_BWA3A_BWA_START 0
+#define OCD_BWA3A_BWA_SIZE 32
+
+/* Bits in BWA3B */
+#define OCD_BWA3B_BWA_START 0
+#define OCD_BWA3B_BWA_SIZE 32
+
+/* Bits in NXCFG */
+#define OCD_NXCFG_NXARCH_START 0
+#define OCD_NXCFG_NXARCH_SIZE 4
+#define OCD_NXCFG_NXOCD_START 4
+#define OCD_NXCFG_NXOCD_SIZE 4
+#define OCD_NXCFG_NXPCB_START 8
+#define OCD_NXCFG_NXPCB_SIZE 4
+#define OCD_NXCFG_NXDB_START 12
+#define OCD_NXCFG_NXDB_SIZE 4
+#define OCD_NXCFG_MXMSEO_BIT 16
+#define OCD_NXCFG_NXMDO_START 17
+#define OCD_NXCFG_NXMDO_SIZE 4
+#define OCD_NXCFG_NXPT_BIT 21
+#define OCD_NXCFG_NXOT_BIT 22
+#define OCD_NXCFG_NXDWT_BIT 23
+#define OCD_NXCFG_NXDRT_BIT 24
+#define OCD_NXCFG_NXDTC_START 25
+#define OCD_NXCFG_NXDTC_SIZE 3
+#define OCD_NXCFG_NXDMA_BIT 28
+
+/* Bits in DINST */
+#define OCD_DINST_DINST_START 0
+#define OCD_DINST_DINST_SIZE 32
+
+/* Bits in CPUCM */
+#define OCD_CPUCM_BEM_BIT 1
+#define OCD_CPUCM_FEM_BIT 2
+#define OCD_CPUCM_REM_BIT 3
+#define OCD_CPUCM_IBEM_BIT 4
+#define OCD_CPUCM_IEEM_BIT 5
+
+/* Bits in DCCPU */
+#define OCD_DCCPU_DATA_START 0
+#define OCD_DCCPU_DATA_SIZE 32
+
+/* Bits in DCEMU */
+#define OCD_DCEMU_DATA_START 0
+#define OCD_DCEMU_DATA_SIZE 32
+
+/* Bits in DCSR */
+#define OCD_DCSR_CPUD_BIT 0
+#define OCD_DCSR_EMUD_BIT 1
+
+/* Bits in PID */
+#define OCD_PID_PROCESS_START 0
+#define OCD_PID_PROCESS_SIZE 32
+
+/* Bits in EPC0 */
+#define OCD_EPC0_RNG_START 0
+#define OCD_EPC0_RNG_SIZE 2
+#define OCD_EPC0_CE_BIT 4
+#define OCD_EPC0_ECNT_START 16
+#define OCD_EPC0_ECNT_SIZE 16
+
+/* Bits in EPC1 */
+#define OCD_EPC1_RNG_START 0
+#define OCD_EPC1_RNG_SIZE 2
+#define OCD_EPC1_ATB_BIT 5
+#define OCD_EPC1_AM_BIT 6
+
+/* Bits in EPC2 */
+#define OCD_EPC2_RNG_START 0
+#define OCD_EPC2_RNG_SIZE 2
+#define OCD_EPC2_DB_START 2
+#define OCD_EPC2_DB_SIZE 2
+
+/* Bits in EPC3 */
+#define OCD_EPC3_RNG_START 0
+#define OCD_EPC3_RNG_SIZE 2
+#define OCD_EPC3_DWE_BIT 2
+
+/* Bits in AXC */
+#define OCD_AXC_DIV_START 0
+#define OCD_AXC_DIV_SIZE 4
+#define OCD_AXC_AXE_BIT 8
+#define OCD_AXC_AXS_BIT 9
+#define OCD_AXC_DDR_BIT 10
+#define OCD_AXC_LS_BIT 11
+#define OCD_AXC_REX_BIT 12
+#define OCD_AXC_REXTEN_BIT 13
+
+/* Constants for DC:EIC */
+#define OCD_EIC_PROGRAM_AND_DATA_TRACE 0
+#define OCD_EIC_BREAKPOINT 1
+#define OCD_EIC_NOP 2
+
+/* Constants for DC:OVC */
+#define OCD_OVC_OVERRUN 0
+#define OCD_OVC_DELAY_CPU_BTM 1
+#define OCD_OVC_DELAY_CPU_DTM 2
+#define OCD_OVC_DELAY_CPU_BTM_DTM 3
+
+/* Constants for DC:EOS */
+#define OCD_EOS_NOP 0
+#define OCD_EOS_DEBUG_MODE 1
+#define OCD_EOS_BREAKPOINT_WATCHPOINT 2
+#define OCD_EOS_THQ 3
+
+/* Constants for RWCS:NTBC */
+#define OCD_NTBC_OVERWRITE 0
+#define OCD_NTBC_DISABLE 1
+#define OCD_NTBC_BREAKPOINT 2
+
+/* Constants for RWCS:CCTRL */
+#define OCD_CCTRL_AUTO 0
+#define OCD_CCTRL_CACHED 1
+#define OCD_CCTRL_UNCACHED 2
+
+/* Constants for RWCS:SZ */
+#define OCD_SZ_BYTE 0
+#define OCD_SZ_HALFWORD 1
+#define OCD_SZ_WORD 2
+
+/* Constants for WT:PTS */
+#define OCD_PTS_DISABLED 0
+#define OCD_PTS_PROGRAM_0B 1
+#define OCD_PTS_PROGRAM_1A 2
+#define OCD_PTS_PROGRAM_1B 3
+#define OCD_PTS_PROGRAM_2A 4
+#define OCD_PTS_PROGRAM_2B 5
+#define OCD_PTS_DATA_3A 6
+#define OCD_PTS_DATA_3B 7
+
+/* Constants for DTC:RWT1 */
+#define OCD_RWT1_NO_TRACE 0
+#define OCD_RWT1_DATA_READ 1
+#define OCD_RWT1_DATA_WRITE 2
+#define OCD_RWT1_DATA_READ_WRITE 3
+
+/* Constants for DTC:RWT0 */
+#define OCD_RWT0_NO_TRACE 0
+#define OCD_RWT0_DATA_READ 1
+#define OCD_RWT0_DATA_WRITE 2
+#define OCD_RWT0_DATA_READ_WRITE 3
+
+/* Constants for BWC0A:BWE */
+#define OCD_BWE_DISABLED 0
+#define OCD_BWE_BREAKPOINT_ENABLED 1
+#define OCD_BWE_WATCHPOINT_ENABLED 3
+
+/* Constants for BWC0B:BWE */
+#define OCD_BWE_DISABLED 0
+#define OCD_BWE_BREAKPOINT_ENABLED 1
+#define OCD_BWE_WATCHPOINT_ENABLED 3
+
+/* Constants for BWC1A:BWE */
+#define OCD_BWE_DISABLED 0
+#define OCD_BWE_BREAKPOINT_ENABLED 1
+#define OCD_BWE_WATCHPOINT_ENABLED 3
+
+/* Constants for BWC1B:BWE */
+#define OCD_BWE_DISABLED 0
+#define OCD_BWE_BREAKPOINT_ENABLED 1
+#define OCD_BWE_WATCHPOINT_ENABLED 3
+
+/* Constants for BWC2A:BWE */
+#define OCD_BWE_DISABLED 0
+#define OCD_BWE_BREAKPOINT_ENABLED 1
+#define OCD_BWE_WATCHPOINT_ENABLED 3
+
+/* Constants for BWC2B:BWE */
+#define OCD_BWE_DISABLED 0
+#define OCD_BWE_BREAKPOINT_ENABLED 1
+#define OCD_BWE_WATCHPOINT_ENABLED 3
+
+/* Constants for BWC3A:SIZE */
+#define OCD_SIZE_BYTE_ACCESS 4
+#define OCD_SIZE_HALFWORD_ACCESS 5
+#define OCD_SIZE_WORD_ACCESS 6
+#define OCD_SIZE_DOUBLE_WORD_ACCESS 7
+
+/* Constants for BWC3A:BRW */
+#define OCD_BRW_READ_BREAK 0
+#define OCD_BRW_WRITE_BREAK 1
+#define OCD_BRW_ANY_ACCES_BREAK 2
+
+/* Constants for BWC3A:BWE */
+#define OCD_BWE_DISABLED 0
+#define OCD_BWE_BREAKPOINT_ENABLED 1
+#define OCD_BWE_WATCHPOINT_ENABLED 3
+
+/* Constants for BWC3B:SIZE */
+#define OCD_SIZE_BYTE_ACCESS 4
+#define OCD_SIZE_HALFWORD_ACCESS 5
+#define OCD_SIZE_WORD_ACCESS 6
+#define OCD_SIZE_DOUBLE_WORD_ACCESS 7
+
+/* Constants for BWC3B:BRW */
+#define OCD_BRW_READ_BREAK 0
+#define OCD_BRW_WRITE_BREAK 1
+#define OCD_BRW_ANY_ACCES_BREAK 2
+
+/* Constants for BWC3B:BWE */
+#define OCD_BWE_DISABLED 0
+#define OCD_BWE_BREAKPOINT_ENABLED 1
+#define OCD_BWE_WATCHPOINT_ENABLED 3
+
+/* Constants for EPC0:RNG */
+#define OCD_RNG_DISABLED 0
+#define OCD_RNG_EXCLUSIVE 1
+#define OCD_RNG_INCLUSIVE 2
+
+/* Constants for EPC1:RNG */
+#define OCD_RNG_DISABLED 0
+#define OCD_RNG_EXCLUSIVE 1
+#define OCD_RNG_INCLUSIVE 2
+
+/* Constants for EPC2:RNG */
+#define OCD_RNG_DISABLED 0
+#define OCD_RNG_EXCLUSIVE 1
+#define OCD_RNG_INCLUSIVE 2
+
+/* Constants for EPC2:DB */
+#define OCD_DB_DISABLED 0
+#define OCD_DB_CHAINED_B 1
+#define OCD_DB_CHAINED_A 2
+#define OCD_DB_AHAINED_A_AND_B 3
+
+/* Constants for EPC3:RNG */
+#define OCD_RNG_DISABLED 0
+#define OCD_RNG_EXCLUSIVE 1
+#define OCD_RNG_INCLUSIVE 2
+
+#ifndef __ASSEMBLER__
+
+/* Register access macros */
+static inline unsigned long __ocd_read(unsigned int reg)
+{
+ return __builtin_mfdr(reg);
+}
+
+static inline void __ocd_write(unsigned int reg, unsigned long value)
+{
+ __builtin_mtdr(reg, value);
+}
+
+#define ocd_read(reg) __ocd_read(OCD_##reg)
+#define ocd_write(reg, value) __ocd_write(OCD_##reg, value)
+
+struct task_struct;
+
+void ocd_enable(struct task_struct *child);
+void ocd_disable(struct task_struct *child);
+
+#endif /* !__ASSEMBLER__ */
#endif /* __ASM_AVR32_OCD_H */
diff --git a/include/asm-avr32/pgalloc.h b/include/asm-avr32/pgalloc.h
index 0e680f47209..b77e364b4c4 100644
--- a/include/asm-avr32/pgalloc.h
+++ b/include/asm-avr32/pgalloc.h
@@ -30,7 +30,7 @@ static __inline__ pgd_t *pgd_alloc(struct mm_struct *mm)
return kcalloc(USER_PTRS_PER_PGD, sizeof(pgd_t), GFP_KERNEL);
}
-static inline void pgd_free(pgd_t *pgd)
+static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
{
kfree(pgd);
}
@@ -55,12 +55,12 @@ static inline struct page *pte_alloc_one(struct mm_struct *mm,
return pte;
}
-static inline void pte_free_kernel(pte_t *pte)
+static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
{
free_page((unsigned long)pte);
}
-static inline void pte_free(struct page *pte)
+static inline void pte_free(struct mm_struct *mm, struct page *pte)
{
__free_page(pte);
}
diff --git a/include/asm-avr32/processor.h b/include/asm-avr32/processor.h
index 6a64833756a..4212551c1cd 100644
--- a/include/asm-avr32/processor.h
+++ b/include/asm-avr32/processor.h
@@ -57,11 +57,25 @@ struct avr32_cpuinfo {
unsigned short cpu_revision;
enum tlb_config tlb_config;
unsigned long features;
+ u32 device_id;
struct cache_info icache;
struct cache_info dcache;
};
+static inline unsigned int avr32_get_manufacturer_id(struct avr32_cpuinfo *cpu)
+{
+ return (cpu->device_id >> 1) & 0x7f;
+}
+static inline unsigned int avr32_get_product_number(struct avr32_cpuinfo *cpu)
+{
+ return (cpu->device_id >> 12) & 0xffff;
+}
+static inline unsigned int avr32_get_chip_revision(struct avr32_cpuinfo *cpu)
+{
+ return (cpu->device_id >> 28) & 0x0f;
+}
+
extern struct avr32_cpuinfo boot_cpu_data;
#ifdef CONFIG_SMP
@@ -139,6 +153,9 @@ extern void show_regs_log_lvl(struct pt_regs *regs, const char *log_lvl);
extern void show_stack_log_lvl(struct task_struct *tsk, unsigned long sp,
struct pt_regs *regs, const char *log_lvl);
+#define task_pt_regs(p) \
+ ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
+
#define KSTK_EIP(tsk) ((tsk)->thread.cpu_context.pc)
#define KSTK_ESP(tsk) ((tsk)->thread.cpu_context.ksp)
diff --git a/include/asm-avr32/ptrace.h b/include/asm-avr32/ptrace.h
index 60f0f19a81f..9e2d44f4e0f 100644
--- a/include/asm-avr32/ptrace.h
+++ b/include/asm-avr32/ptrace.h
@@ -14,8 +14,7 @@
/*
* Status Register bits
*/
-#define SR_H 0x40000000
-#define SR_R 0x20000000
+#define SR_H 0x20000000
#define SR_J 0x10000000
#define SR_DM 0x08000000
#define SR_D 0x04000000
@@ -35,8 +34,7 @@
#define SR_I0M 0x00020000
#define SR_GM 0x00010000
-#define SR_H_BIT 30
-#define SR_R_BIT 29
+#define SR_H_BIT 29
#define SR_J_BIT 28
#define SR_DM_BIT 27
#define SR_D_BIT 26
@@ -123,7 +121,15 @@ struct pt_regs {
};
#ifdef __KERNEL__
-# define user_mode(regs) (((regs)->sr & MODE_MASK) == MODE_USER)
+
+#include <asm/ocd.h>
+
+#define arch_ptrace_attach(child) ocd_enable(child)
+
+#define user_mode(regs) (((regs)->sr & MODE_MASK) == MODE_USER)
+#define instruction_pointer(regs) ((regs)->pc)
+#define profile_pc(regs) instruction_pointer(regs)
+
extern void show_regs (struct pt_regs *);
static __inline__ int valid_user_regs(struct pt_regs *regs)
@@ -143,9 +149,6 @@ static __inline__ int valid_user_regs(struct pt_regs *regs)
return 0;
}
-#define instruction_pointer(regs) ((regs)->pc)
-
-#define profile_pc(regs) instruction_pointer(regs)
#endif /* __KERNEL__ */
diff --git a/include/asm-avr32/setup.h b/include/asm-avr32/setup.h
index b0828d43e11..ea3070ff13a 100644
--- a/include/asm-avr32/setup.h
+++ b/include/asm-avr32/setup.h
@@ -110,7 +110,7 @@ struct tagtable {
int (*parse)(struct tag *);
};
-#define __tag __attribute_used__ __attribute__((__section__(".taglist.init")))
+#define __tag __used __attribute__((__section__(".taglist.init")))
#define __tagtable(tag, fn) \
static struct tagtable __tagtable_##fn __tag = { tag, fn }
diff --git a/include/asm-avr32/socket.h b/include/asm-avr32/socket.h
index a0d0507a503..35863f26092 100644
--- a/include/asm-avr32/socket.h
+++ b/include/asm-avr32/socket.h
@@ -52,4 +52,6 @@
#define SO_TIMESTAMPNS 35
#define SCM_TIMESTAMPNS SO_TIMESTAMPNS
+#define SO_MARK 36
+
#endif /* __ASM_AVR32_SOCKET_H */
diff --git a/include/asm-avr32/sysreg.h b/include/asm-avr32/sysreg.h
index dd21182b60e..d4e0950170c 100644
--- a/include/asm-avr32/sysreg.h
+++ b/include/asm-avr32/sysreg.h
@@ -93,6 +93,8 @@
#define SYSREG_I3M_SIZE 1
#define SYSREG_EM_OFFSET 21
#define SYSREG_EM_SIZE 1
+#define SYSREG_MODE_OFFSET 22
+#define SYSREG_MODE_SIZE 3
#define SYSREG_M0_OFFSET 22
#define SYSREG_M0_SIZE 1
#define SYSREG_M1_OFFSET 23
diff --git a/include/asm-avr32/system.h b/include/asm-avr32/system.h
index dc2d527cef4..c600cc15cbc 100644
--- a/include/asm-avr32/system.h
+++ b/include/asm-avr32/system.h
@@ -35,8 +35,8 @@
#include <asm/ocd.h>
#define finish_arch_switch(prev) \
do { \
- __mtdr(DBGREG_PID, prev->pid); \
- __mtdr(DBGREG_PID, current->pid); \
+ ocd_write(PID, prev->pid); \
+ ocd_write(PID, current->pid); \
} while(0)
#endif
diff --git a/include/asm-avr32/thread_info.h b/include/asm-avr32/thread_info.h
index 17dacf3f36d..07049f6c0d4 100644
--- a/include/asm-avr32/thread_info.h
+++ b/include/asm-avr32/thread_info.h
@@ -25,6 +25,11 @@ struct thread_info {
unsigned long flags; /* low level flags */
__u32 cpu;
__s32 preempt_count; /* 0 => preemptable, <0 => BUG */
+ __u32 rar_saved; /* return address... */
+ __u32 rsr_saved; /* ...and status register
+ saved by debug handler
+ when setting up
+ trampoline */
struct restart_block restart_block;
__u8 supervisor_stack[0];
};
@@ -78,29 +83,36 @@ static inline struct thread_info *current_thread_info(void)
#define TIF_NEED_RESCHED 2 /* rescheduling necessary */
#define TIF_POLLING_NRFLAG 3 /* true if poll_idle() is polling
TIF_NEED_RESCHED */
-#define TIF_BREAKPOINT 4 /* true if we should break after return */
-#define TIF_SINGLE_STEP 5 /* single step after next break */
+#define TIF_BREAKPOINT 4 /* enter monitor mode on return */
+#define TIF_SINGLE_STEP 5 /* single step in progress */
#define TIF_MEMDIE 6
#define TIF_RESTORE_SIGMASK 7 /* restore signal mask in do_signal */
#define TIF_CPU_GOING_TO_SLEEP 8 /* CPU is entering sleep 0 mode */
+#define TIF_DEBUG 30 /* debugging enabled */
#define TIF_USERSPACE 31 /* true if FS sets userspace */
#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE)
#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
#define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG)
-#define _TIF_BREAKPOINT (1 << TIF_BREAKPOINT)
#define _TIF_SINGLE_STEP (1 << TIF_SINGLE_STEP)
#define _TIF_MEMDIE (1 << TIF_MEMDIE)
#define _TIF_RESTORE_SIGMASK (1 << TIF_RESTORE_SIGMASK)
#define _TIF_CPU_GOING_TO_SLEEP (1 << TIF_CPU_GOING_TO_SLEEP)
-/* XXX: These two masks must never span more than 16 bits! */
+/* Note: The masks below must never span more than 16 bits! */
+
/* work to do on interrupt/exception return */
-#define _TIF_WORK_MASK 0x0000013e
+#define _TIF_WORK_MASK \
+ ((1 << TIF_SIGPENDING) \
+ | (1 << TIF_NEED_RESCHED) \
+ | (1 << TIF_POLLING_NRFLAG) \
+ | (1 << TIF_BREAKPOINT) \
+ | (1 << TIF_RESTORE_SIGMASK))
+
/* work to do on any return to userspace */
-#define _TIF_ALLWORK_MASK 0x0000013f
+#define _TIF_ALLWORK_MASK (_TIF_WORK_MASK | (1 << TIF_SYSCALL_TRACE))
/* work to do on return from debug mode */
-#define _TIF_DBGWORK_MASK 0x0000017e
+#define _TIF_DBGWORK_MASK (_TIF_WORK_MASK & ~(1 << TIF_BREAKPOINT))
#endif /* __ASM_AVR32_THREAD_INFO_H */
diff --git a/include/asm-avr32/timex.h b/include/asm-avr32/timex.h
index 5e44ecb3ce0..187dcf38b21 100644
--- a/include/asm-avr32/timex.h
+++ b/include/asm-avr32/timex.h
@@ -34,7 +34,6 @@ static inline cycles_t get_cycles (void)
return 0;
}
-extern int read_current_timer(unsigned long *timer_value);
-#define ARCH_HAS_READ_CURRENT_TIMER 1
+#define ARCH_HAS_READ_CURRENT_TIMER
#endif /* __ASM_AVR32_TIMEX_H */
diff --git a/include/asm-avr32/unistd.h b/include/asm-avr32/unistd.h
index de09009593f..89861a27543 100644
--- a/include/asm-avr32/unistd.h
+++ b/include/asm-avr32/unistd.h
@@ -297,7 +297,7 @@
#define __NR_utimensat 278
#define __NR_signalfd 279
-#define __NR_timerfd 280
+/* 280 was __NR_timerfd */
#define __NR_eventfd 281
#ifdef __KERNEL__
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-05 19:42:22 +0000