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Diffstat (limited to 'include/asm-blackfin/mach-bf533/defBF532.h')
-rw-r--r--include/asm-blackfin/mach-bf533/defBF532.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h
index 6a3cf93f8b5..37134aaf995 100644
--- a/include/asm-blackfin/mach-bf533/defBF532.h
+++ b/include/asm-blackfin/mach-bf533/defBF532.h
@@ -104,6 +104,7 @@
#define UART_GCTL 0xFFC00424 /* Global Control Register */
/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
+#define SPI0_REGBASE 0xFFC00500
#define SPI_CTL 0xFFC00500 /* SPI Control Register */
#define SPI_FLG 0xFFC00504 /* SPI Flag register */
#define SPI_STAT 0xFFC00508 /* SPI Status register */
@@ -928,7 +929,7 @@
#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */
-#define SPI_LEN 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
+#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */