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-rw-r--r--include/asm-mips/txx9/generic.h62
-rw-r--r--include/asm-mips/txx9/jmr3927.h180
-rw-r--r--include/asm-mips/txx9/pci.h39
-rw-r--r--include/asm-mips/txx9/rbtx4927.h89
-rw-r--r--include/asm-mips/txx9/rbtx4938.h145
-rw-r--r--include/asm-mips/txx9/smsc_fdc37m81x.h67
-rw-r--r--include/asm-mips/txx9/spi.h19
-rw-r--r--include/asm-mips/txx9/tx3927.h339
-rw-r--r--include/asm-mips/txx9/tx4927.h255
-rw-r--r--include/asm-mips/txx9/tx4927pcic.h203
-rw-r--r--include/asm-mips/txx9/tx4938.h293
11 files changed, 0 insertions, 1691 deletions
diff --git a/include/asm-mips/txx9/generic.h b/include/asm-mips/txx9/generic.h
deleted file mode 100644
index 5b1ccf901c6..00000000000
--- a/include/asm-mips/txx9/generic.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * linux/include/asm-mips/txx9/generic.h
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_TXX9_GENERIC_H
-#define __ASM_TXX9_GENERIC_H
-
-#include <linux/init.h>
-#include <linux/ioport.h> /* for struct resource */
-
-extern struct resource txx9_ce_res[];
-#define TXX9_CE(n) (unsigned long)(txx9_ce_res[(n)].start)
-extern unsigned int txx9_pcode;
-extern char txx9_pcode_str[8];
-void txx9_reg_res_init(unsigned int pcode, unsigned long base,
- unsigned long size);
-
-extern unsigned int txx9_master_clock;
-extern unsigned int txx9_cpu_clock;
-extern unsigned int txx9_gbus_clock;
-#define TXX9_IMCLK (txx9_gbus_clock / 2)
-
-extern int txx9_ccfg_toeon;
-struct uart_port;
-int early_serial_txx9_setup(struct uart_port *port);
-
-struct pci_dev;
-struct txx9_board_vec {
- const char *system;
- void (*prom_init)(void);
- void (*mem_setup)(void);
- void (*irq_setup)(void);
- void (*time_init)(void);
- void (*arch_init)(void);
- void (*device_init)(void);
-#ifdef CONFIG_PCI
- int (*pci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
-#endif
-};
-extern struct txx9_board_vec *txx9_board_vec;
-extern int (*txx9_irq_dispatch)(int pending);
-void prom_init_cmdline(void);
-char *prom_getcmdline(void);
-void txx9_wdt_init(unsigned long base);
-void txx9_spi_init(int busid, unsigned long base, int irq);
-void txx9_ethaddr_init(unsigned int id, unsigned char *ethaddr);
-void txx9_sio_init(unsigned long baseaddr, int irq,
- unsigned int line, unsigned int sclk, int nocts);
-void prom_putchar(char c);
-#ifdef CONFIG_EARLY_PRINTK
-extern void (*txx9_prom_putchar)(char c);
-void txx9_sio_putchar_init(unsigned long baseaddr);
-#else
-static inline void txx9_sio_putchar_init(unsigned long baseaddr)
-{
-}
-#endif
-
-#endif /* __ASM_TXX9_GENERIC_H */
diff --git a/include/asm-mips/txx9/jmr3927.h b/include/asm-mips/txx9/jmr3927.h
deleted file mode 100644
index a409c446bf1..00000000000
--- a/include/asm-mips/txx9/jmr3927.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * Defines for the TJSYS JMR-TX3927
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000-2001 Toshiba Corporation
- */
-#ifndef __ASM_TXX9_JMR3927_H
-#define __ASM_TXX9_JMR3927_H
-
-#include <asm/txx9/tx3927.h>
-#include <asm/addrspace.h>
-#include <asm/system.h>
-#include <asm/txx9irq.h>
-
-/* CS */
-#define JMR3927_ROMCE0 0x1fc00000 /* 4M */
-#define JMR3927_ROMCE1 0x1e000000 /* 4M */
-#define JMR3927_ROMCE2 0x14000000 /* 16M */
-#define JMR3927_ROMCE3 0x10000000 /* 64M */
-#define JMR3927_ROMCE5 0x1d000000 /* 4M */
-#define JMR3927_SDCS0 0x00000000 /* 32M */
-#define JMR3927_SDCS1 0x02000000 /* 32M */
-/* PCI Direct Mappings */
-
-#define JMR3927_PCIMEM 0x08000000
-#define JMR3927_PCIMEM_SIZE 0x08000000 /* 128M */
-#define JMR3927_PCIIO 0x15000000
-#define JMR3927_PCIIO_SIZE 0x01000000 /* 16M */
-
-#define JMR3927_SDRAM_SIZE 0x02000000 /* 32M */
-#define JMR3927_PORT_BASE KSEG1
-
-/* Address map (virtual address) */
-#define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0)
-#define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1)
-#define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2)
-#define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM)
-#define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO)
-
-#define JMR3927_IOC_REV_ADDR (JMR3927_IOC_BASE + 0x00000000)
-#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000)
-#define JMR3927_IOC_LED_ADDR (JMR3927_IOC_BASE + 0x00020000)
-#define JMR3927_IOC_DIPSW_ADDR (JMR3927_IOC_BASE + 0x00030000)
-#define JMR3927_IOC_BREV_ADDR (JMR3927_IOC_BASE + 0x00040000)
-#define JMR3927_IOC_DTR_ADDR (JMR3927_IOC_BASE + 0x00050000)
-#define JMR3927_IOC_INTS1_ADDR (JMR3927_IOC_BASE + 0x00080000)
-#define JMR3927_IOC_INTS2_ADDR (JMR3927_IOC_BASE + 0x00090000)
-#define JMR3927_IOC_INTM_ADDR (JMR3927_IOC_BASE + 0x000a0000)
-#define JMR3927_IOC_INTP_ADDR (JMR3927_IOC_BASE + 0x000b0000)
-#define JMR3927_IOC_RESET_ADDR (JMR3927_IOC_BASE + 0x000f0000)
-
-/* Flash ROM */
-#define JMR3927_FLASH_BASE (JMR3927_ROM0_BASE)
-#define JMR3927_FLASH_SIZE 0x00400000
-
-/* bits for IOC_REV/IOC_BREV (high byte) */
-#define JMR3927_IDT_MASK 0xfc
-#define JMR3927_REV_MASK 0x03
-#define JMR3927_IOC_IDT 0xe0
-
-/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */
-#define JMR3927_IOC_INTB_PCIA 0
-#define JMR3927_IOC_INTB_PCIB 1
-#define JMR3927_IOC_INTB_PCIC 2
-#define JMR3927_IOC_INTB_PCID 3
-#define JMR3927_IOC_INTB_MODEM 4
-#define JMR3927_IOC_INTB_INT6 5
-#define JMR3927_IOC_INTB_INT7 6
-#define JMR3927_IOC_INTB_SOFT 7
-#define JMR3927_IOC_INTF_PCIA (1 << JMR3927_IOC_INTF_PCIA)
-#define JMR3927_IOC_INTF_PCIB (1 << JMR3927_IOC_INTB_PCIB)
-#define JMR3927_IOC_INTF_PCIC (1 << JMR3927_IOC_INTB_PCIC)
-#define JMR3927_IOC_INTF_PCID (1 << JMR3927_IOC_INTB_PCID)
-#define JMR3927_IOC_INTF_MODEM (1 << JMR3927_IOC_INTB_MODEM)
-#define JMR3927_IOC_INTF_INT6 (1 << JMR3927_IOC_INTB_INT6)
-#define JMR3927_IOC_INTF_INT7 (1 << JMR3927_IOC_INTB_INT7)
-#define JMR3927_IOC_INTF_SOFT (1 << JMR3927_IOC_INTB_SOFT)
-
-/* bits for IOC_RESET (high byte) */
-#define JMR3927_IOC_RESET_CPU 1
-#define JMR3927_IOC_RESET_PCI 2
-
-#if defined(__BIG_ENDIAN)
-#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d))
-#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)(a))
-#elif defined(__LITTLE_ENDIAN)
-#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)((a)^1)) = (d))
-#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)((a)^1))
-#else
-#error "No Endian"
-#endif
-
-/* LED macro */
-#define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR)
-
-#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR)
-
-/* DIPSW4 macro */
-#define jmr3927_dipsw1() (gpio_get_value(11) == 0)
-#define jmr3927_dipsw2() (gpio_get_value(10) == 0)
-#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0)
-#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0)
-
-/*
- * IRQ mappings
- */
-
-/* These are the virtual IRQ numbers, we divide all IRQ's into
- * 'spaces', the 'space' determines where and how to enable/disable
- * that particular IRQ on an JMR machine. Add new 'spaces' as new
- * IRQ hardware is supported.
- */
-#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */
-#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */
-
-#define JMR3927_IRQ_IRC TXX9_IRQ_BASE
-#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
-#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
-
-#define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0)
-#define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1)
-#define JMR3927_IRQ_IRC_INT2 (JMR3927_IRQ_IRC + TX3927_IR_INT2)
-#define JMR3927_IRQ_IRC_INT3 (JMR3927_IRQ_IRC + TX3927_IR_INT3)
-#define JMR3927_IRQ_IRC_INT4 (JMR3927_IRQ_IRC + TX3927_IR_INT4)
-#define JMR3927_IRQ_IRC_INT5 (JMR3927_IRQ_IRC + TX3927_IR_INT5)
-#define JMR3927_IRQ_IRC_SIO0 (JMR3927_IRQ_IRC + TX3927_IR_SIO0)
-#define JMR3927_IRQ_IRC_SIO1 (JMR3927_IRQ_IRC + TX3927_IR_SIO1)
-#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch))
-#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA)
-#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO)
-#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI)
-#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch))
-#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA)
-#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB)
-#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC)
-#define JMR3927_IRQ_IOC_PCID (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCID)
-#define JMR3927_IRQ_IOC_MODEM (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_MODEM)
-#define JMR3927_IRQ_IOC_INT6 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6)
-#define JMR3927_IRQ_IOC_INT7 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7)
-#define JMR3927_IRQ_IOC_SOFT (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT)
-
-/* IOC (PCI, MODEM) */
-#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1
-/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */
-#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3
-
-/* Clocks */
-#define JMR3927_CORECLK 132710400 /* 132.7MHz */
-
-/*
- * TX3927 Pin Configuration:
- *
- * PCFG bits Avail Dead
- * SELSIO[1:0]:11 RXD[1:0], TXD[1:0] PIO[6:3]
- * SELSIOC[0]:1 CTS[0], RTS[0] INT[5:4]
- * SELSIOC[1]:0,SELDSF:0, GSDAO[0],GPCST[3] CTS[1], RTS[1],DSF,
- * GDBGE* PIO[2:1]
- * SELDMA[2]:1 DMAREQ[2],DMAACK[2] PIO[13:12]
- * SELTMR[2:0]:000 TIMER[1:0]
- * SELCS:0,SELDMA[1]:0 PIO[11;10] SDCS_CE[7:6],
- * DMAREQ[1],DMAACK[1]
- * SELDMA[0]:1 DMAREQ[0],DMAACK[0] PIO[9:8]
- * SELDMA[3]:1 DMAREQ[3],DMAACK[3] PIO[15:14]
- * SELDONE:1 DMADONE PIO[7]
- *
- * Usable pins are:
- * RXD[1;0],TXD[1:0],CTS[0],RTS[0],
- * DMAREQ[0,2,3],DMAACK[0,2,3],DMADONE,PIO[0,10,11]
- * INT[3:0]
- */
-
-void jmr3927_prom_init(void);
-void jmr3927_irq_setup(void);
-struct pci_dev;
-int jmr3927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
-
-#endif /* __ASM_TXX9_JMR3927_H */
diff --git a/include/asm-mips/txx9/pci.h b/include/asm-mips/txx9/pci.h
deleted file mode 100644
index 3d32529060a..00000000000
--- a/include/asm-mips/txx9/pci.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_TXX9_PCI_H
-#define __ASM_TXX9_PCI_H
-
-#include <linux/pci.h>
-
-extern struct pci_controller txx9_primary_pcic;
-struct pci_controller *
-txx9_alloc_pci_controller(struct pci_controller *pcic,
- unsigned long mem_base, unsigned long mem_size,
- unsigned long io_base, unsigned long io_size);
-
-int txx9_pci66_check(struct pci_controller *hose, int top_bus,
- int current_bus);
-extern int txx9_pci_mem_high __initdata;
-
-extern int txx9_pci_option;
-#define TXX9_PCI_OPT_PICMG 0x0002
-#define TXX9_PCI_OPT_CLK_33 0x0008
-#define TXX9_PCI_OPT_CLK_66 0x0010
-#define TXX9_PCI_OPT_CLK_MASK \
- (TXX9_PCI_OPT_CLK_33 | TXX9_PCI_OPT_CLK_66)
-#define TXX9_PCI_OPT_CLK_AUTO TXX9_PCI_OPT_CLK_MASK
-
-enum txx9_pci_err_action {
- TXX9_PCI_ERR_REPORT,
- TXX9_PCI_ERR_IGNORE,
- TXX9_PCI_ERR_PANIC,
-};
-extern enum txx9_pci_err_action txx9_pci_err_action;
-
-extern char * (*txx9_board_pcibios_setup)(char *str);
-char *txx9_pcibios_setup(char *str);
-
-#endif /* __ASM_TXX9_PCI_H */
diff --git a/include/asm-mips/txx9/rbtx4927.h b/include/asm-mips/txx9/rbtx4927.h
deleted file mode 100644
index 6fcec912c14..00000000000
--- a/include/asm-mips/txx9/rbtx4927.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Author: MontaVista Software, Inc.
- * source@mvista.com
- *
- * Copyright 2001-2002 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef __ASM_TXX9_RBTX4927_H
-#define __ASM_TXX9_RBTX4927_H
-
-#include <asm/txx9/tx4927.h>
-
-#define RBTX4927_PCIMEM 0x08000000
-#define RBTX4927_PCIMEM_SIZE 0x08000000
-#define RBTX4927_PCIIO 0x16000000
-#define RBTX4927_PCIIO_SIZE 0x01000000
-
-#define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000)
-#define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006)
-#define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000)
-#define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002)
-#define RBTX4927_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f006)
-#define RBTX4927_BRAMRTC_BASE (IO_BASE + TXX9_CE(2) + 0x00010000)
-#define RBTX4927_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000)
-
-/* Ethernet port address */
-#define RBTX4927_ETHER_ADDR (RBTX4927_ETHER_BASE + 0x280)
-
-#define rbtx4927_imask_addr ((__u8 __iomem *)RBTX4927_IMASK_ADDR)
-#define rbtx4927_imstat_addr ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR)
-#define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR)
-#define rbtx4927_softresetlock_addr \
- ((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR)
-#define rbtx4927_pcireset_addr ((__u8 __iomem *)RBTX4927_PCIRESET_ADDR)
-
-/* bits for ISTAT/IMASK/IMSTAT */
-#define RBTX4927_INTB_PCID 0
-#define RBTX4927_INTB_PCIC 1
-#define RBTX4927_INTB_PCIB 2
-#define RBTX4927_INTB_PCIA 3
-#define RBTX4927_INTF_PCID (1 << RBTX4927_INTB_PCID)
-#define RBTX4927_INTF_PCIC (1 << RBTX4927_INTB_PCIC)
-#define RBTX4927_INTF_PCIB (1 << RBTX4927_INTB_PCIB)
-#define RBTX4927_INTF_PCIA (1 << RBTX4927_INTB_PCIA)
-
-#define RBTX4927_NR_IRQ_IOC 8 /* IOC */
-
-#define RBTX4927_IRQ_IOC (TXX9_IRQ_BASE + TX4927_NUM_IR)
-#define RBTX4927_IRQ_IOC_PCID (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCID)
-#define RBTX4927_IRQ_IOC_PCIC (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIC)
-#define RBTX4927_IRQ_IOC_PCIB (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIB)
-#define RBTX4927_IRQ_IOC_PCIA (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIA)
-
-#define RBTX4927_IRQ_IOCINT (TXX9_IRQ_BASE + TX4927_IR_INT(1))
-
-#ifdef CONFIG_PCI
-#define RBTX4927_ISA_IO_OFFSET RBTX4927_PCIIO
-#else
-#define RBTX4927_ISA_IO_OFFSET 0
-#endif
-
-#define RBTX4927_RTL_8019_BASE (RBTX4927_ETHER_ADDR - mips_io_port_base)
-#define RBTX4927_RTL_8019_IRQ (TXX9_IRQ_BASE + TX4927_IR_INT(3))
-
-void rbtx4927_prom_init(void);
-void rbtx4927_irq_setup(void);
-struct pci_dev;
-int rbtx4927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
-
-#endif /* __ASM_TXX9_RBTX4927_H */
diff --git a/include/asm-mips/txx9/rbtx4938.h b/include/asm-mips/txx9/rbtx4938.h
deleted file mode 100644
index 9f0441a2812..00000000000
--- a/include/asm-mips/txx9/rbtx4938.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Definitions for TX4937/TX4938
- *
- * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
- */
-#ifndef __ASM_TXX9_RBTX4938_H
-#define __ASM_TXX9_RBTX4938_H
-
-#include <asm/addrspace.h>
-#include <asm/txx9irq.h>
-#include <asm/txx9/tx4938.h>
-
-/* Address map */
-#define RBTX4938_FPGA_REG_ADDR (IO_BASE + TXX9_CE(2) + 0x00000000)
-#define RBTX4938_FPGA_REV_ADDR (IO_BASE + TXX9_CE(2) + 0x00000002)
-#define RBTX4938_CONFIG1_ADDR (IO_BASE + TXX9_CE(2) + 0x00000004)
-#define RBTX4938_CONFIG2_ADDR (IO_BASE + TXX9_CE(2) + 0x00000006)
-#define RBTX4938_CONFIG3_ADDR (IO_BASE + TXX9_CE(2) + 0x00000008)
-#define RBTX4938_LED_ADDR (IO_BASE + TXX9_CE(2) + 0x00001000)
-#define RBTX4938_DIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001002)
-#define RBTX4938_BDIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001004)
-#define RBTX4938_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000)
-#define RBTX4938_IMASK2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002002)
-#define RBTX4938_INTPOL_ADDR (IO_BASE + TXX9_CE(2) + 0x00002004)
-#define RBTX4938_ISTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006)
-#define RBTX4938_ISTAT2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002008)
-#define RBTX4938_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x0000200a)
-#define RBTX4938_IMSTAT2_ADDR (IO_BASE + TXX9_CE(2) + 0x0000200c)
-#define RBTX4938_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000)
-#define RBTX4938_PIOSEL_ADDR (IO_BASE + TXX9_CE(2) + 0x00005000)
-#define RBTX4938_SPICS_ADDR (IO_BASE + TXX9_CE(2) + 0x00005002)
-#define RBTX4938_SFPWR_ADDR (IO_BASE + TXX9_CE(2) + 0x00005008)
-#define RBTX4938_SFVOL_ADDR (IO_BASE + TXX9_CE(2) + 0x0000500a)
-#define RBTX4938_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007000)
-#define RBTX4938_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x00007002)
-#define RBTX4938_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007004)
-#define RBTX4938_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000)
-
-/* Ethernet port address (Jumperless Mode (W12:Open)) */
-#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280)
-
-/* bits for ISTAT/IMASK/IMSTAT */
-#define RBTX4938_INTB_PCID 0
-#define RBTX4938_INTB_PCIC 1
-#define RBTX4938_INTB_PCIB 2
-#define RBTX4938_INTB_PCIA 3
-#define RBTX4938_INTB_RTC 4
-#define RBTX4938_INTB_ATA 5
-#define RBTX4938_INTB_MODEM 6
-#define RBTX4938_INTB_SWINT 7
-#define RBTX4938_INTF_PCID (1 << RBTX4938_INTB_PCID)
-#define RBTX4938_INTF_PCIC (1 << RBTX4938_INTB_PCIC)
-#define RBTX4938_INTF_PCIB (1 << RBTX4938_INTB_PCIB)
-#define RBTX4938_INTF_PCIA (1 << RBTX4938_INTB_PCIA)
-#define RBTX4938_INTF_RTC (1 << RBTX4938_INTB_RTC)
-#define RBTX4938_INTF_ATA (1 << RBTX4938_INTB_ATA)
-#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM)
-#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT)
-
-#define rbtx4938_fpga_rev_addr ((__u8 __iomem *)RBTX4938_FPGA_REV_ADDR)
-#define rbtx4938_led_addr ((__u8 __iomem *)RBTX4938_LED_ADDR)
-#define rbtx4938_dipsw_addr ((__u8 __iomem *)RBTX4938_DIPSW_ADDR)
-#define rbtx4938_bdipsw_addr ((__u8 __iomem *)RBTX4938_BDIPSW_ADDR)
-#define rbtx4938_imask_addr ((__u8 __iomem *)RBTX4938_IMASK_ADDR)
-#define rbtx4938_imask2_addr ((__u8 __iomem *)RBTX4938_IMASK2_ADDR)
-#define rbtx4938_intpol_addr ((__u8 __iomem *)RBTX4938_INTPOL_ADDR)
-#define rbtx4938_istat_addr ((__u8 __iomem *)RBTX4938_ISTAT_ADDR)
-#define rbtx4938_istat2_addr ((__u8 __iomem *)RBTX4938_ISTAT2_ADDR)
-#define rbtx4938_imstat_addr ((__u8 __iomem *)RBTX4938_IMSTAT_ADDR)
-#define rbtx4938_imstat2_addr ((__u8 __iomem *)RBTX4938_IMSTAT2_ADDR)
-#define rbtx4938_softint_addr ((__u8 __iomem *)RBTX4938_SOFTINT_ADDR)
-#define rbtx4938_piosel_addr ((__u8 __iomem *)RBTX4938_PIOSEL_ADDR)
-#define rbtx4938_spics_addr ((__u8 __iomem *)RBTX4938_SPICS_ADDR)
-#define rbtx4938_sfpwr_addr ((__u8 __iomem *)RBTX4938_SFPWR_ADDR)
-#define rbtx4938_sfvol_addr ((__u8 __iomem *)RBTX4938_SFVOL_ADDR)
-#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR)
-#define rbtx4938_softresetlock_addr \
- ((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR)
-#define rbtx4938_pcireset_addr ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR)
-
-/*
- * IRQ mappings
- */
-
-#define RBTX4938_SOFT_INT0 0 /* not used */
-#define RBTX4938_SOFT_INT1 1 /* not used */
-#define RBTX4938_IRC_INT 2
-#define RBTX4938_TIMER_INT 7
-
-/* These are the virtual IRQ numbers, we divide all IRQ's into
- * 'spaces', the 'space' determines where and how to enable/disable
- * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new
- * IRQ hardware is supported.
- */
-#define RBTX4938_NR_IRQ_IOC 8
-
-#define RBTX4938_IRQ_IRC TXX9_IRQ_BASE
-#define RBTX4938_IRQ_IOC (TXX9_IRQ_BASE + TX4938_NUM_IR)
-#define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC)
-
-#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
-#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
-#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
-#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n))
-#define RBTX4938_IRQ_IRC_DMA(ch, n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n))
-#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO)
-#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC)
-#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC)
-#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n))
-#define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC)
-#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR)
-#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME)
-#define RBTX4938_IRQ_IRC_ACLC (RBTX4938_IRQ_IRC + TX4938_IR_ACLC)
-#define RBTX4938_IRQ_IRC_ACLCPME (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME)
-#define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1)
-#define RBTX4938_IRQ_IRC_SPI (RBTX4938_IRQ_IRC + TX4938_IR_SPI)
-#define RBTX4938_IRQ_IOC_PCID (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID)
-#define RBTX4938_IRQ_IOC_PCIC (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC)
-#define RBTX4938_IRQ_IOC_PCIB (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB)
-#define RBTX4938_IRQ_IOC_PCIA (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA)
-#define RBTX4938_IRQ_IOC_RTC (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC)
-#define RBTX4938_IRQ_IOC_ATA (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA)
-#define RBTX4938_IRQ_IOC_MODEM (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM)
-#define RBTX4938_IRQ_IOC_SWINT (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT)
-
-
-/* IOC (PCI, etc) */
-#define RBTX4938_IRQ_IOCINT (TXX9_IRQ_BASE + TX4938_IR_INT(0))
-/* Onboard 10M Ether */
-#define RBTX4938_IRQ_ETHER (TXX9_IRQ_BASE + TX4938_IR_INT(1))
-
-#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
-#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER)
-
-void rbtx4938_prom_init(void);
-void rbtx4938_irq_setup(void);
-struct pci_dev;
-int rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
-
-#endif /* __ASM_TXX9_RBTX4938_H */
diff --git a/include/asm-mips/txx9/smsc_fdc37m81x.h b/include/asm-mips/txx9/smsc_fdc37m81x.h
deleted file mode 100644
index 02e161d0755..00000000000
--- a/include/asm-mips/txx9/smsc_fdc37m81x.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Interface for smsc fdc48m81x Super IO chip
- *
- * Author: MontaVista Software, Inc. source@mvista.com
- *
- * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * Copyright (C) 2004 MontaVista Software Inc.
- * Manish Lachwani, mlachwani@mvista.com
- */
-
-#ifndef _SMSC_FDC37M81X_H_
-#define _SMSC_FDC37M81X_H_
-
-/* Common Registers */
-#define SMSC_FDC37M81X_CONFIG_INDEX 0x00
-#define SMSC_FDC37M81X_CONFIG_DATA 0x01
-#define SMSC_FDC37M81X_CONF 0x02
-#define SMSC_FDC37M81X_INDEX 0x03
-#define SMSC_FDC37M81X_DNUM 0x07
-#define SMSC_FDC37M81X_DID 0x20
-#define SMSC_FDC37M81X_DREV 0x21
-#define SMSC_FDC37M81X_PCNT 0x22
-#define SMSC_FDC37M81X_PMGT 0x23
-#define SMSC_FDC37M81X_OSC 0x24
-#define SMSC_FDC37M81X_CONFPA0 0x26
-#define SMSC_FDC37M81X_CONFPA1 0x27
-#define SMSC_FDC37M81X_TEST4 0x2B
-#define SMSC_FDC37M81X_TEST5 0x2C
-#define SMSC_FDC37M81X_TEST1 0x2D
-#define SMSC_FDC37M81X_TEST2 0x2E
-#define SMSC_FDC37M81X_TEST3 0x2F
-
-/* Logical device numbers */
-#define SMSC_FDC37M81X_FDD 0x00
-#define SMSC_FDC37M81X_PARALLEL 0x03
-#define SMSC_FDC37M81X_SERIAL1 0x04
-#define SMSC_FDC37M81X_SERIAL2 0x05
-#define SMSC_FDC37M81X_KBD 0x07
-#define SMSC_FDC37M81X_AUXIO 0x08
-#define SMSC_FDC37M81X_NONE 0xff
-
-/* Logical device Config Registers */
-#define SMSC_FDC37M81X_ACTIVE 0x30
-#define SMSC_FDC37M81X_BASEADDR0 0x60
-#define SMSC_FDC37M81X_BASEADDR1 0x61
-#define SMSC_FDC37M81X_INT 0x70
-#define SMSC_FDC37M81X_INT2 0x72
-#define SMSC_FDC37M81X_LDCR_F0 0xF0
-
-/* Chip Config Values */
-#define SMSC_FDC37M81X_CONFIG_ENTER 0x55
-#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa
-#define SMSC_FDC37M81X_CHIP_ID 0x4d
-
-unsigned long smsc_fdc37m81x_init(unsigned long port);
-
-void smsc_fdc37m81x_config_beg(void);
-
-void smsc_fdc37m81x_config_end(void);
-
-void smsc_fdc37m81x_config_set(u8 reg, u8 val);
-
-#endif
diff --git a/include/asm-mips/txx9/spi.h b/include/asm-mips/txx9/spi.h
deleted file mode 100644
index ddfb2a0dc43..00000000000
--- a/include/asm-mips/txx9/spi.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Definitions for TX4937/TX4938 SPI
- *
- * Copyright (C) 2000-2001 Toshiba Corporation
- *
- * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
- */
-#ifndef __ASM_TXX9_SPI_H
-#define __ASM_TXX9_SPI_H
-
-extern int spi_eeprom_register(int chipid);
-extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len);
-
-#endif /* __ASM_TXX9_SPI_H */
diff --git a/include/asm-mips/txx9/tx3927.h b/include/asm-mips/txx9/tx3927.h
deleted file mode 100644
index 587deb9592d..00000000000
--- a/include/asm-mips/txx9/tx3927.h
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Toshiba Corporation
- */
-#ifndef __ASM_TXX9_TX3927_H
-#define __ASM_TXX9_TX3927_H
-
-#define TX3927_REG_BASE 0xfffe0000UL
-#define TX3927_REG_SIZE 0x00010000
-#define TX3927_SDRAMC_REG (TX3927_REG_BASE + 0x8000)
-#define TX3927_ROMC_REG (TX3927_REG_BASE + 0x9000)
-#define TX3927_DMA_REG (TX3927_REG_BASE + 0xb000)
-#define TX3927_IRC_REG (TX3927_REG_BASE + 0xc000)
-#define TX3927_PCIC_REG (TX3927_REG_BASE + 0xd000)
-#define TX3927_CCFG_REG (TX3927_REG_BASE + 0xe000)
-#define TX3927_NR_TMR 3
-#define TX3927_TMR_REG(ch) (TX3927_REG_BASE + 0xf000 + (ch) * 0x100)
-#define TX3927_NR_SIO 2
-#define TX3927_SIO_REG(ch) (TX3927_REG_BASE + 0xf300 + (ch) * 0x100)
-#define TX3927_PIO_REG (TX3927_REG_BASE + 0xf500)
-
-struct tx3927_sdramc_reg {
- volatile unsigned long cr[8];
- volatile unsigned long tr[3];
- volatile unsigned long cmd;
- volatile unsigned long smrs[2];
-};
-
-struct tx3927_romc_reg {
- volatile unsigned long cr[8];
-};
-
-struct tx3927_dma_reg {
- struct tx3927_dma_ch_reg {
- volatile unsigned long cha;
- volatile unsigned long sar;
- volatile unsigned long dar;
- volatile unsigned long cntr;
- volatile unsigned long sair;
- volatile unsigned long dair;
- volatile unsigned long ccr;
- volatile unsigned long csr;
- } ch[4];
- volatile unsigned long dbr[8];
- volatile unsigned long tdhr;
- volatile unsigned long mcr;
- volatile unsigned long unused0;
-};
-
-#include <asm/byteorder.h>
-
-#ifdef __BIG_ENDIAN
-#define endian_def_s2(e1, e2) \
- volatile unsigned short e1, e2
-#define endian_def_sb2(e1, e2, e3) \
- volatile unsigned short e1;volatile unsigned char e2, e3
-#define endian_def_b2s(e1, e2, e3) \
- volatile unsigned char e1, e2;volatile unsigned short e3
-#define endian_def_b4(e1, e2, e3, e4) \
- volatile unsigned char e1, e2, e3, e4
-#else
-#define endian_def_s2(e1, e2) \
- volatile unsigned short e2, e1
-#define endian_def_sb2(e1, e2, e3) \
- volatile unsigned char e3, e2;volatile unsigned short e1
-#define endian_def_b2s(e1, e2, e3) \
- volatile unsigned short e3;volatile unsigned char e2, e1
-#define endian_def_b4(e1, e2, e3, e4) \
- volatile unsigned char e4, e3, e2, e1
-#endif
-
-struct tx3927_pcic_reg {
- endian_def_s2(did, vid);
- endian_def_s2(pcistat, pcicmd);
- endian_def_b4(cc, scc, rpli, rid);
- endian_def_b4(unused0, ht, mlt, cls);
- volatile unsigned long ioba; /* +10 */
- volatile unsigned long mba;
- volatile unsigned long unused1[5];
- endian_def_s2(svid, ssvid);
- volatile unsigned long unused2; /* +30 */
- endian_def_sb2(unused3, unused4, capptr);
- volatile unsigned long unused5;
- endian_def_b4(ml, mg, ip, il);
- volatile unsigned long unused6; /* +40 */
- volatile unsigned long istat;
- volatile unsigned long iim;
- volatile unsigned long rrt;
- volatile unsigned long unused7[3]; /* +50 */
- volatile unsigned long ipbmma;
- volatile unsigned long ipbioma; /* +60 */
- volatile unsigned long ilbmma;
- volatile unsigned long ilbioma;
- volatile unsigned long unused8[9];
- volatile unsigned long tc; /* +90 */
- volatile unsigned long tstat;
- volatile unsigned long tim;
- volatile unsigned long tccmd;
- volatile unsigned long pcirrt; /* +a0 */
- volatile unsigned long pcirrt_cmd;
- volatile unsigned long pcirrdt;
- volatile unsigned long unused9[3];
- volatile unsigned long tlboap;
- volatile unsigned long tlbiap;
- volatile unsigned long tlbmma; /* +c0 */
- volatile unsigned long tlbioma;
- volatile unsigned long sc_msg;
- volatile unsigned long sc_be;
- volatile unsigned long tbl; /* +d0 */
- volatile unsigned long unused10[3];
- volatile unsigned long pwmng; /* +e0 */
- volatile unsigned long pwmngs;
- volatile unsigned long unused11[6];
- volatile unsigned long req_trace; /* +100 */
- volatile unsigned long pbapmc;
- volatile unsigned long pbapms;
- volatile unsigned long pbapmim;
- volatile unsigned long bm; /* +110 */
- volatile unsigned long cpcibrs;
- volatile unsigned long cpcibgs;
- volatile unsigned long pbacs;
- volatile unsigned long iobas; /* +120 */
- volatile unsigned long mbas;
- volatile unsigned long lbc;
- volatile unsigned long lbstat;
- volatile unsigned long lbim; /* +130 */
- volatile unsigned long pcistatim;
- volatile unsigned long ica;
- volatile unsigned long icd;
- volatile unsigned long iiadp; /* +140 */
- volatile unsigned long iscdp;
- volatile unsigned long mmas;
- volatile unsigned long iomas;
- volatile unsigned long ipciaddr; /* +150 */
- volatile unsigned long ipcidata;
- volatile unsigned long ipcibe;
-};
-
-struct tx3927_ccfg_reg {
- volatile unsigned long ccfg;
- volatile unsigned long crir;
- volatile unsigned long pcfg;
- volatile unsigned long tear;
- volatile unsigned long pdcr;
-};
-
-/*
- * SDRAMC
- */
-
-/*
- * ROMC
- */
-
-/*
- * DMA
- */
-/* bits for MCR */
-#define TX3927_DMA_MCR_EIS(ch) (0x10000000<<(ch))
-#define TX3927_DMA_MCR_DIS(ch) (0x01000000<<(ch))
-#define TX3927_DMA_MCR_RSFIF 0x00000080
-#define TX3927_DMA_MCR_FIFUM(ch) (0x00000008<<(ch))
-#define TX3927_DMA_MCR_LE 0x00000004
-#define TX3927_DMA_MCR_RPRT 0x00000002
-#define TX3927_DMA_MCR_MSTEN 0x00000001
-
-/* bits for CCRn */
-#define TX3927_DMA_CCR_DBINH 0x04000000
-#define TX3927_DMA_CCR_SBINH 0x02000000
-#define TX3927_DMA_CCR_CHRST 0x01000000
-#define TX3927_DMA_CCR_RVBYTE 0x00800000
-#define TX3927_DMA_CCR_ACKPOL 0x00400000
-#define TX3927_DMA_CCR_REQPL 0x00200000
-#define TX3927_DMA_CCR_EGREQ 0x00100000
-#define TX3927_DMA_CCR_CHDN 0x00080000
-#define TX3927_DMA_CCR_DNCTL 0x00060000
-#define TX3927_DMA_CCR_EXTRQ 0x00010000
-#define TX3927_DMA_CCR_INTRQD 0x0000e000
-#define TX3927_DMA_CCR_INTENE 0x00001000
-#define TX3927_DMA_CCR_INTENC 0x00000800
-#define TX3927_DMA_CCR_INTENT 0x00000400
-#define TX3927_DMA_CCR_CHNEN 0x00000200
-#define TX3927_DMA_CCR_XFACT 0x00000100
-#define TX3927_DMA_CCR_SNOP 0x00000080
-#define TX3927_DMA_CCR_DSTINC 0x00000040
-#define TX3927_DMA_CCR_SRCINC 0x00000020
-#define TX3927_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c)
-#define TX3927_DMA_CCR_XFSZ_1W TX3927_DMA_CCR_XFSZ(2)
-#define TX3927_DMA_CCR_XFSZ_4W TX3927_DMA_CCR_XFSZ(4)
-#define TX3927_DMA_CCR_XFSZ_8W TX3927_DMA_CCR_XFSZ(5)
-#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6)
-#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7)
-#define TX3927_DMA_CCR_MEMIO 0x00000002
-#define TX3927_DMA_CCR_ONEAD 0x00000001
-
-/* bits for CSRn */
-#define TX3927_DMA_CSR_CHNACT 0x00000100
-#define TX3927_DMA_CSR_ABCHC 0x00000080
-#define TX3927_DMA_CSR_NCHNC 0x00000040
-#define TX3927_DMA_CSR_NTRNFC 0x00000020
-#define TX3927_DMA_CSR_EXTDN 0x00000010
-#define TX3927_DMA_CSR_CFERR 0x00000008
-#define TX3927_DMA_CSR_CHERR 0x00000004
-#define TX3927_DMA_CSR_DESERR 0x00000002
-#define TX3927_DMA_CSR_SORERR 0x00000001
-
-/*
- * IRC
- */
-#define TX3927_IR_INT0 0
-#define TX3927_IR_INT1 1
-#define TX3927_IR_INT2 2
-#define TX3927_IR_INT3 3
-#define TX3927_IR_INT4 4
-#define TX3927_IR_INT5 5
-#define TX3927_IR_SIO0 6
-#define TX3927_IR_SIO1 7
-#define TX3927_IR_SIO(ch) (6 + (ch))
-#define TX3927_IR_DMA 8
-#define TX3927_IR_PIO 9
-#define TX3927_IR_PCI 10
-#define TX3927_IR_TMR(ch) (13 + (ch))
-#define TX3927_NUM_IR 16
-
-/*
- * PCIC
- */
-/* bits for PCICMD */
-/* see PCI_COMMAND_XXX in linux/pci.h */
-
-/* bits for PCISTAT */
-/* see PCI_STATUS_XXX in linux/pci.h */
-#define PCI_STATUS_NEW_CAP 0x0010
-
-/* bits for ISTAT/IIM */
-#define TX3927_PCIC_IIM_ALL 0x00001600
-
-/* bits for TC */
-#define TX3927_PCIC_TC_OF16E 0x00000020
-#define TX3927_PCIC_TC_IF8E 0x00000010
-#define TX3927_PCIC_TC_OF8E 0x00000008
-
-/* bits for TSTAT/TIM */
-#define TX3927_PCIC_TIM_ALL 0x0003ffff
-
-/* bits for IOBA/MBA */
-/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */
-
-/* bits for PBAPMC */
-#define TX3927_PCIC_PBAPMC_RPBA 0x00000004
-#define TX3927_PCIC_PBAPMC_PBAEN 0x00000002
-#define TX3927_PCIC_PBAPMC_BMCEN 0x00000001
-
-/* bits for LBSTAT/LBIM */
-#define TX3927_PCIC_LBIM_ALL 0x0000003e
-
-/* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */
-#define TX3927_PCIC_PCISTATIM_ALL 0x0000f900
-
-/* bits for LBC */
-#define TX3927_PCIC_LBC_IBSE 0x00004000
-#define TX3927_PCIC_LBC_TIBSE 0x00002000
-#define TX3927_PCIC_LBC_TMFBSE 0x00001000
-#define TX3927_PCIC_LBC_HRST 0x00000800
-#define TX3927_PCIC_LBC_SRST 0x00000400
-#define TX3927_PCIC_LBC_EPCAD 0x00000200
-#define TX3927_PCIC_LBC_MSDSE 0x00000100
-#define TX3927_PCIC_LBC_CRR 0x00000080
-#define TX3927_PCIC_LBC_ILMDE 0x00000040
-#define TX3927_PCIC_LBC_ILIDE 0x00000020
-
-#define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
-#define TX3927_PCIC_MAX_DEVNU TX3927_PCIC_IDSEL_AD_TO_SLOT(32)
-
-/*
- * CCFG
- */
-/* CCFG : Chip Configuration */
-#define TX3927_CCFG_TLBOFF 0x00020000
-#define TX3927_CCFG_BEOW 0x00010000
-#define TX3927_CCFG_WR 0x00008000
-#define TX3927_CCFG_TOE 0x00004000
-#define TX3927_CCFG_PCIXARB 0x00002000
-#define TX3927_CCFG_PCI3 0x00001000
-#define TX3927_CCFG_PSNP 0x00000800
-#define TX3927_CCFG_PPRI 0x00000400
-#define TX3927_CCFG_PLLM 0x00000030
-#define TX3927_CCFG_ENDIAN 0x00000004
-#define TX3927_CCFG_HALT 0x00000002
-#define TX3927_CCFG_ACEHOLD 0x00000001
-
-/* PCFG : Pin Configuration */
-#define TX3927_PCFG_SYSCLKEN 0x08000000
-#define TX3927_PCFG_SDRCLKEN_ALL 0x07c00000
-#define TX3927_PCFG_SDRCLKEN(ch) (0x00400000<<(ch))
-#define TX3927_PCFG_PCICLKEN_ALL 0x003c0000
-#define TX3927_PCFG_PCICLKEN(ch) (0x00040000<<(ch))
-#define TX3927_PCFG_SELALL 0x0003ffff
-#define TX3927_PCFG_SELCS 0x00020000
-#define TX3927_PCFG_SELDSF 0x00010000
-#define TX3927_PCFG_SELSIOC_ALL 0x0000c000
-#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch))
-#define TX3927_PCFG_SELSIO_ALL 0x00003000
-#define TX3927_PCFG_SELSIO(ch) (0x00001000<<(ch))
-#define TX3927_PCFG_SELTMR_ALL 0x00000e00
-#define TX3927_PCFG_SELTMR(ch) (0x00000200<<(ch))
-#define TX3927_PCFG_SELDONE 0x00000100
-#define TX3927_PCFG_INTDMA_ALL 0x000000f0
-#define TX3927_PCFG_INTDMA(ch) (0x00000010<<(ch))
-#define TX3927_PCFG_SELDMA_ALL 0x0000000f
-#define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch))
-
-#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
-#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG)
-#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG)
-#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
-#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
-#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
-#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG)
-
-#define TX3927_REV_PCODE() (tx3927_ccfgptr->crir >> 16)
-#define TX3927_ROMC_BA(ch) (tx3927_romcptr->cr[(ch)] & 0xfff00000)
-#define TX3927_ROMC_SIZE(ch) \
- (0x00100000 << ((tx3927_romcptr->cr[(ch)] >> 8) & 0xf))
-
-void tx3927_wdt_init(void);
-void tx3927_setup(void);
-void tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr);
-void tx3927_sio_init(unsigned int sclk, unsigned int cts_mask);
-struct pci_controller;
-void tx3927_pcic_setup(struct pci_controller *channel,
- unsigned long sdram_size, int extarb);
-void tx3927_setup_pcierr_irq(void);
-void tx3927_irq_init(void);
-
-#endif /* __ASM_TXX9_TX3927_H */
diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h
deleted file mode 100644
index 195f6515db9..00000000000
--- a/include/asm-mips/txx9/tx4927.h
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * Author: MontaVista Software, Inc.
- * source@mvista.com
- *
- * Copyright 2001-2006 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef __ASM_TXX9_TX4927_H
-#define __ASM_TXX9_TX4927_H
-
-#include <linux/types.h>
-#include <linux/io.h>
-#include <asm/txx9irq.h>
-#include <asm/txx9/tx4927pcic.h>
-
-#ifdef CONFIG_64BIT
-#define TX4927_REG_BASE 0xffffffffff1f0000UL
-#else
-#define TX4927_REG_BASE 0xff1f0000UL
-#endif
-#define TX4927_REG_SIZE 0x00010000
-
-#define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000)
-#define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000)
-#define TX4927_PCIC_REG (TX4927_REG_BASE + 0xd000)
-#define TX4927_CCFG_REG (TX4927_REG_BASE + 0xe000)
-#define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600)
-#define TX4927_NR_TMR 3
-#define TX4927_TMR_REG(ch) (TX4927_REG_BASE + 0xf000 + (ch) * 0x100)
-#define TX4927_NR_SIO 2
-#define TX4927_SIO_REG(ch) (TX4927_REG_BASE + 0xf300 + (ch) * 0x100)
-#define TX4927_PIO_REG (TX4927_REG_BASE + 0xf500)
-
-#define TX4927_IR_INT(n) (2 + (n))
-#define TX4927_IR_SIO(n) (8 + (n))
-#define TX4927_IR_PCIC 16
-#define TX4927_NUM_IR_TMR 3
-#define TX4927_IR_TMR(n) (17 + (n))
-#define TX4927_IR_PCIERR 22
-#define TX4927_NUM_IR 32
-
-#define TX4927_IRC_INT 2 /* IP[2] in Status register */
-
-#define TX4927_NUM_PIO 16
-
-struct tx4927_sdramc_reg {
- u64 cr[4];
- u64 unused0[4];
- u64 tr;
- u64 unused1[2];
- u64 cmd;
-};
-
-struct tx4927_ebusc_reg {
- u64 cr[8];
-};
-
-struct tx4927_ccfg_reg {
- u64 ccfg;
- u64 crir;
- u64 pcfg;
- u64 toea;
- u64 clkctr;
- u64 unused0;
- u64 garbc;
- u64 unused1;
- u64 unused2;
- u64 ramp;
-};
-
-/*
- * CCFG
- */
-/* CCFG : Chip Configuration */
-#define TX4927_CCFG_WDRST 0x0000020000000000ULL
-#define TX4927_CCFG_WDREXEN 0x0000010000000000ULL
-#define TX4927_CCFG_BCFG_MASK 0x000000ff00000000ULL
-#define TX4927_CCFG_TINTDIS 0x01000000
-#define TX4927_CCFG_PCI66 0x00800000
-#define TX4927_CCFG_PCIMODE 0x00400000
-#define TX4927_CCFG_DIVMODE_MASK 0x000e0000
-#define TX4927_CCFG_DIVMODE_8 (0x0 << 17)
-#define TX4927_CCFG_DIVMODE_12 (0x1 << 17)
-#define TX4927_CCFG_DIVMODE_16 (0x2 << 17)
-#define TX4927_CCFG_DIVMODE_10 (0x3 << 17)
-#define TX4927_CCFG_DIVMODE_2 (0x4 << 17)
-#define TX4927_CCFG_DIVMODE_3 (0x5 << 17)
-#define TX4927_CCFG_DIVMODE_4 (0x6 << 17)
-#define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17)
-#define TX4927_CCFG_BEOW 0x00010000
-#define TX4927_CCFG_WR 0x00008000
-#define TX4927_CCFG_TOE 0x00004000
-#define TX4927_CCFG_PCIARB 0x00002000
-#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
-#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000
-#define TX4927_CCFG_PCIDIVMODE_3 0x00000800
-#define TX4927_CCFG_PCIDIVMODE_5 0x00001000
-#define TX4927_CCFG_PCIDIVMODE_6 0x00001800
-#define TX4927_CCFG_SYSSP_MASK 0x000000c0
-#define TX4927_CCFG_ENDIAN 0x00000004
-#define TX4927_CCFG_HALT 0x00000002
-#define TX4927_CCFG_ACEHOLD 0x00000001
-#define TX4927_CCFG_W1CBITS (TX4927_CCFG_WDRST | TX4927_CCFG_BEOW)
-
-/* PCFG : Pin Configuration */
-#define TX4927_PCFG_SDCLKDLY_MASK 0x30000000
-#define TX4927_PCFG_SDCLKDLY(d) ((d)<<28)
-#define TX4927_PCFG_SYSCLKEN 0x08000000
-#define TX4927_PCFG_SDCLKEN_ALL 0x07800000
-#define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
-#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
-#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
-#define TX4927_PCFG_SEL2 0x00000200
-#define TX4927_PCFG_SEL1 0x00000100
-#define TX4927_PCFG_DMASEL_ALL 0x000000ff
-#define TX4927_PCFG_DMASEL0_MASK 0x00000003
-#define TX4927_PCFG_DMASEL1_MASK 0x0000000c
-#define TX4927_PCFG_DMASEL2_MASK 0x00000030
-#define TX4927_PCFG_DMASEL3_MASK 0x000000c0
-#define TX4927_PCFG_DMASEL0_DRQ0 0x00000000
-#define TX4927_PCFG_DMASEL0_SIO1 0x00000001
-#define TX4927_PCFG_DMASEL0_ACL0 0x00000002
-#define TX4927_PCFG_DMASEL0_ACL2 0x00000003
-#define TX4927_PCFG_DMASEL1_DRQ1 0x00000000
-#define TX4927_PCFG_DMASEL1_SIO1 0x00000004
-#define TX4927_PCFG_DMASEL1_ACL1 0x00000008
-#define TX4927_PCFG_DMASEL1_ACL3 0x0000000c
-#define TX4927_PCFG_DMASEL2_DRQ2 0x00000000 /* SEL2=0 */
-#define TX4927_PCFG_DMASEL2_SIO0 0x00000010 /* SEL2=0 */
-#define TX4927_PCFG_DMASEL2_ACL1 0x00000000 /* SEL2=1 */
-#define TX4927_PCFG_DMASEL2_ACL2 0x00000020 /* SEL2=1 */
-#define TX4927_PCFG_DMASEL2_ACL0 0x00000030 /* SEL2=1 */
-#define TX4927_PCFG_DMASEL3_DRQ3 0x00000000
-#define TX4927_PCFG_DMASEL3_SIO0 0x00000040
-#define TX4927_PCFG_DMASEL3_ACL3 0x00000080
-#define TX4927_PCFG_DMASEL3_ACL1 0x000000c0
-
-/* CLKCTR : Clock Control */
-#define TX4927_CLKCTR_ACLCKD 0x02000000
-#define TX4927_CLKCTR_PIOCKD 0x01000000
-#define TX4927_CLKCTR_DMACKD 0x00800000
-#define TX4927_CLKCTR_PCICKD 0x00400000
-#define TX4927_CLKCTR_TM0CKD 0x00100000
-#define TX4927_CLKCTR_TM1CKD 0x00080000
-#define TX4927_CLKCTR_TM2CKD 0x00040000
-#define TX4927_CLKCTR_SIO0CKD 0x00020000
-#define TX4927_CLKCTR_SIO1CKD 0x00010000
-#define TX4927_CLKCTR_ACLRST 0x00000200
-#define TX4927_CLKCTR_PIORST 0x00000100
-#define TX4927_CLKCTR_DMARST 0x00000080
-#define TX4927_CLKCTR_PCIRST 0x00000040
-#define TX4927_CLKCTR_TM0RST 0x00000010
-#define TX4927_CLKCTR_TM1RST 0x00000008
-#define TX4927_CLKCTR_TM2RST 0x00000004
-#define TX4927_CLKCTR_SIO0RST 0x00000002
-#define TX4927_CLKCTR_SIO1RST 0x00000001
-
-#define tx4927_sdramcptr \
- ((struct tx4927_sdramc_reg __iomem *)TX4927_SDRAMC_REG)
-#define tx4927_pcicptr \
- ((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG)
-#define tx4927_ccfgptr \
- ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG)
-#define tx4927_ebuscptr \
- ((struct tx4927_ebusc_reg __iomem *)TX4927_EBUSC_REG)
-#define tx4927_pioptr ((struct txx9_pio_reg __iomem *)TX4927_PIO_REG)
-
-#define TX4927_REV_PCODE() \
- ((__u32)__raw_readq(&tx4927_ccfgptr->crir) >> 16)
-
-#define TX4927_SDRAMC_CR(ch) __raw_readq(&tx4927_sdramcptr->cr[(ch)])
-#define TX4927_SDRAMC_BA(ch) ((TX4927_SDRAMC_CR(ch) >> 49) << 21)
-#define TX4927_SDRAMC_SIZE(ch) \
- ((((TX4927_SDRAMC_CR(ch) >> 33) & 0x7fff) + 1) << 21)
-
-#define TX4927_EBUSC_CR(ch) __raw_readq(&tx4927_ebuscptr->cr[(ch)])
-#define TX4927_EBUSC_BA(ch) ((TX4927_EBUSC_CR(ch) >> 48) << 20)
-#define TX4927_EBUSC_SIZE(ch) \
- (0x00100000 << ((unsigned long)(TX4927_EBUSC_CR(ch) >> 8) & 0xf))
-
-/* utilities */
-static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits)
-{
-#ifdef CONFIG_32BIT
- unsigned long flags;
- local_irq_save(flags);
-#endif
- ____raw_writeq(____raw_readq(adr) & ~bits, adr);
-#ifdef CONFIG_32BIT
- local_irq_restore(flags);
-#endif
-}
-static inline void txx9_set64(__u64 __iomem *adr, __u64 bits)
-{
-#ifdef CONFIG_32BIT
- unsigned long flags;
- local_irq_save(flags);
-#endif
- ____raw_writeq(____raw_readq(adr) | bits, adr);
-#ifdef CONFIG_32BIT
- local_irq_restore(flags);
-#endif
-}
-
-/* These functions are not interrupt safe. */
-static inline void tx4927_ccfg_clear(__u64 bits)
-{
- ____raw_writeq(____raw_readq(&tx4927_ccfgptr->ccfg)
- & ~(TX4927_CCFG_W1CBITS | bits),
- &tx4927_ccfgptr->ccfg);
-}
-static inline void tx4927_ccfg_set(__u64 bits)
-{
- ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
- & ~TX4927_CCFG_W1CBITS) | bits,
- &tx4927_ccfgptr->ccfg);
-}
-static inline void tx4927_ccfg_change(__u64 change, __u64 new)
-{
- ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
- & ~(TX4927_CCFG_W1CBITS | change)) |
- new,
- &tx4927_ccfgptr->ccfg);
-}
-
-unsigned int tx4927_get_mem_size(void);
-void tx4927_wdt_init(void);
-void tx4927_setup(void);
-void tx4927_time_init(unsigned int tmrnr);
-void tx4927_sio_init(unsigned int sclk, unsigned int cts_mask);
-int tx4927_report_pciclk(void);
-int tx4927_pciclk66_setup(void);
-void tx4927_setup_pcierr_irq(void);
-void tx4927_irq_init(void);
-
-#endif /* __ASM_TXX9_TX4927_H */
diff --git a/include/asm-mips/txx9/tx4927pcic.h b/include/asm-mips/txx9/tx4927pcic.h
deleted file mode 100644
index c470b8a5fe5..00000000000
--- a/include/asm-mips/txx9/tx4927pcic.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/*
- * include/asm-mips/txx9/tx4927pcic.h
- * TX4927 PCI controller definitions.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_TXX9_TX4927PCIC_H
-#define __ASM_TXX9_TX4927PCIC_H
-
-#include <linux/pci.h>
-#include <linux/irqreturn.h>
-
-struct tx4927_pcic_reg {
- u32 pciid;
- u32 pcistatus;
- u32 pciccrev;
- u32 pcicfg1;
- u32 p2gm0plbase; /* +10 */
- u32 p2gm0pubase;
- u32 p2gm1plbase;
- u32 p2gm1pubase;
- u32 p2gm2pbase; /* +20 */
- u32 p2giopbase;
- u32 unused0;
- u32 pcisid;
- u32 unused1; /* +30 */
- u32 pcicapptr;
- u32 unused2;
- u32 pcicfg2;
- u32 g2ptocnt; /* +40 */
- u32 unused3[15];
- u32 g2pstatus; /* +80 */
- u32 g2pmask;
- u32 pcisstatus;
- u32 pcimask;
- u32 p2gcfg; /* +90 */
- u32 p2gstatus;
- u32 p2gmask;
- u32 p2gccmd;
- u32 unused4[24]; /* +a0 */
- u32 pbareqport; /* +100 */
- u32 pbacfg;
- u32 pbastatus;
- u32 pbamask;
- u32 pbabm; /* +110 */
- u32 pbacreq;
- u32 pbacgnt;
- u32 pbacstate;
- u64 g2pmgbase[3]; /* +120 */
- u64 g2piogbase;
- u32 g2pmmask[3]; /* +140 */
- u32 g2piomask;
- u64 g2pmpbase[3]; /* +150 */
- u64 g2piopbase;
- u32 pciccfg; /* +170 */
- u32 pcicstatus;
- u32 pcicmask;
- u32 unused5;
- u64 p2gmgbase[3]; /* +180 */
- u64 p2giogbase;
- u32 g2pcfgadrs; /* +1a0 */
- u32 g2pcfgdata;
- u32 unused6[8];
- u32 g2pintack;
- u32 g2pspc;
- u32 unused7[12]; /* +1d0 */
- u64 pdmca; /* +200 */
- u64 pdmga;
- u64 pdmpa;
- u64 pdmctr;
- u64 pdmcfg; /* +220 */
- u64 pdmsts;
-};
-
-/* bits for PCICMD */
-/* see PCI_COMMAND_XXX in linux/pci_regs.h */
-
-/* bits for PCISTAT */
-/* see PCI_STATUS_XXX in linux/pci_regs.h */
-
-/* bits for IOBA/MBA */
-/* see PCI_BASE_ADDRESS_XXX in linux/pci_regs.h */
-
-/* bits for G2PSTATUS/G2PMASK */
-#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003
-#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002
-#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001
-
-/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci_regs.h */
-#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900
-
-/* bits for PBACFG */
-#define TX4927_PCIC_PBACFG_FIXPA 0x00000008
-#define TX4927_PCIC_PBACFG_RPBA 0x00000004
-#define TX4927_PCIC_PBACFG_PBAEN 0x00000002
-#define TX4927_PCIC_PBACFG_BMCEN 0x00000001
-
-/* bits for PBASTATUS/PBAMASK */
-#define TX4927_PCIC_PBASTATUS_ALL 0x00000001
-#define TX4927_PCIC_PBASTATUS_BM 0x00000001
-
-/* bits for G2PMnGBASE */
-#define TX4927_PCIC_G2PMnGBASE_BSDIS 0x0000002000000000ULL
-#define TX4927_PCIC_G2PMnGBASE_ECHG 0x0000001000000000ULL
-
-/* bits for G2PIOGBASE */
-#define TX4927_PCIC_G2PIOGBASE_BSDIS 0x0000002000000000ULL
-#define TX4927_PCIC_G2PIOGBASE_ECHG 0x0000001000000000ULL
-
-/* bits for PCICSTATUS/PCICMASK */
-#define TX4927_PCIC_PCICSTATUS_ALL 0x000007b8
-#define TX4927_PCIC_PCICSTATUS_PME 0x00000400
-#define TX4927_PCIC_PCICSTATUS_TLB 0x00000200
-#define TX4927_PCIC_PCICSTATUS_NIB 0x00000100
-#define TX4927_PCIC_PCICSTATUS_ZIB 0x00000080
-#define TX4927_PCIC_PCICSTATUS_PERR 0x00000020
-#define TX4927_PCIC_PCICSTATUS_SERR 0x00000010
-#define TX4927_PCIC_PCICSTATUS_GBE 0x00000008
-#define TX4927_PCIC_PCICSTATUS_IWB 0x00000002
-#define TX4927_PCIC_PCICSTATUS_E2PDONE 0x00000001
-
-/* bits for PCICCFG */
-#define TX4927_PCIC_PCICCFG_GBWC_MASK 0x0fff0000
-#define TX4927_PCIC_PCICCFG_HRST 0x00000800
-#define TX4927_PCIC_PCICCFG_SRST 0x00000400
-#define TX4927_PCIC_PCICCFG_IRBER 0x00000200
-#define TX4927_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch))
-#define TX4927_PCIC_PCICCFG_G2PM0EN 0x00000100
-#define TX4927_PCIC_PCICCFG_G2PM1EN 0x00000080
-#define TX4927_PCIC_PCICCFG_G2PM2EN 0x00000040
-#define TX4927_PCIC_PCICCFG_G2PIOEN 0x00000020
-#define TX4927_PCIC_PCICCFG_TCAR 0x00000010
-#define TX4927_PCIC_PCICCFG_ICAEN 0x00000008
-
-/* bits for P2GMnGBASE */
-#define TX4927_PCIC_P2GMnGBASE_TMEMEN 0x0000004000000000ULL
-#define TX4927_PCIC_P2GMnGBASE_TBSDIS 0x0000002000000000ULL
-#define TX4927_PCIC_P2GMnGBASE_TECHG 0x0000001000000000ULL
-
-/* bits for P2GIOGBASE */
-#define TX4927_PCIC_P2GIOGBASE_TIOEN 0x0000004000000000ULL
-#define TX4927_PCIC_P2GIOGBASE_TBSDIS 0x0000002000000000ULL
-#define TX4927_PCIC_P2GIOGBASE_TECHG 0x0000001000000000ULL
-
-#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
-#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
-
-/* bits for PDMCFG */
-#define TX4927_PCIC_PDMCFG_RSTFIFO 0x00200000
-#define TX4927_PCIC_PDMCFG_EXFER 0x00100000
-#define TX4927_PCIC_PDMCFG_REQDLY_MASK 0x00003800
-#define TX4927_PCIC_PDMCFG_REQDLY_NONE (0 << 11)
-#define TX4927_PCIC_PDMCFG_REQDLY_16 (1 << 11)
-#define TX4927_PCIC_PDMCFG_REQDLY_32 (2 << 11)
-#define TX4927_PCIC_PDMCFG_REQDLY_64 (3 << 11)
-#define TX4927_PCIC_PDMCFG_REQDLY_128 (4 << 11)
-#define TX4927_PCIC_PDMCFG_REQDLY_256 (5 << 11)
-#define TX4927_PCIC_PDMCFG_REQDLY_512 (6 << 11)
-#define TX4927_PCIC_PDMCFG_REQDLY_1024 (7 << 11)
-#define TX4927_PCIC_PDMCFG_ERRIE 0x00000400
-#define TX4927_PCIC_PDMCFG_NCCMPIE 0x00000200
-#define TX4927_PCIC_PDMCFG_NTCMPIE 0x00000100
-#define TX4927_PCIC_PDMCFG_CHNEN 0x00000080
-#define TX4927_PCIC_PDMCFG_XFRACT 0x00000040
-#define TX4927_PCIC_PDMCFG_BSWAP 0x00000020
-#define TX4927_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
-#define TX4927_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000
-#define TX4927_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004
-#define TX4927_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008
-#define TX4927_PCIC_PDMCFG_XFRDIRC 0x00000002
-#define TX4927_PCIC_PDMCFG_CHRST 0x00000001
-
-/* bits for PDMSTS */
-#define TX4927_PCIC_PDMSTS_REQCNT_MASK 0x3f000000
-#define TX4927_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
-#define TX4927_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000
-#define TX4927_PCIC_PDMSTS_FIFORP_MASK 0x00030000
-#define TX4927_PCIC_PDMSTS_ERRINT 0x00000800
-#define TX4927_PCIC_PDMSTS_DONEINT 0x00000400
-#define TX4927_PCIC_PDMSTS_CHNEN 0x00000200
-#define TX4927_PCIC_PDMSTS_XFRACT 0x00000100
-#define TX4927_PCIC_PDMSTS_ACCMP 0x00000080
-#define TX4927_PCIC_PDMSTS_NCCMP 0x00000040
-#define TX4927_PCIC_PDMSTS_NTCMP 0x00000020
-#define TX4927_PCIC_PDMSTS_CFGERR 0x00000008
-#define TX4927_PCIC_PDMSTS_PCIERR 0x00000004
-#define TX4927_PCIC_PDMSTS_CHNERR 0x00000002
-#define TX4927_PCIC_PDMSTS_DATAERR 0x00000001
-#define TX4927_PCIC_PDMSTS_ALL_CMP 0x000000e0
-#define TX4927_PCIC_PDMSTS_ALL_ERR 0x0000000f
-
-struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
- struct pci_controller *channel);
-void tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
- struct pci_controller *channel, int extarb);
-void tx4927_report_pcic_status(void);
-char *tx4927_pcibios_setup(char *str);
-void tx4927_dump_pcic_settings(void);
-irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id);
-
-#endif /* __ASM_TXX9_TX4927PCIC_H */
diff --git a/include/asm-mips/txx9/tx4938.h b/include/asm-mips/txx9/tx4938.h
deleted file mode 100644
index 8175d4ccbc3..00000000000
--- a/include/asm-mips/txx9/tx4938.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/*
- * Definitions for TX4937/TX4938
- * Copyright (C) 2000-2001 Toshiba Corporation
- *
- * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
- */
-#ifndef __ASM_TXX9_TX4938_H
-#define __ASM_TXX9_TX4938_H
-
-/* some controllers are compatible with 4927 */
-#include <asm/txx9/tx4927.h>
-
-#ifdef CONFIG_64BIT
-#define TX4938_REG_BASE 0xffffffffff1f0000UL /* == TX4937_REG_BASE */
-#else
-#define TX4938_REG_BASE 0xff1f0000UL /* == TX4937_REG_BASE */
-#endif
-#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
-
-/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
-#define TX4938_NDFMC_REG (TX4938_REG_BASE + 0x5000)
-#define TX4938_SRAMC_REG (TX4938_REG_BASE + 0x6000)
-#define TX4938_PCIC1_REG (TX4938_REG_BASE + 0x7000)
-#define TX4938_SDRAMC_REG (TX4938_REG_BASE + 0x8000)
-#define TX4938_EBUSC_REG (TX4938_REG_BASE + 0x9000)
-#define TX4938_DMA_REG(ch) (TX4938_REG_BASE + 0xb000 + (ch) * 0x800)
-#define TX4938_PCIC_REG (TX4938_REG_BASE + 0xd000)
-#define TX4938_CCFG_REG (TX4938_REG_BASE + 0xe000)
-#define TX4938_NR_TMR 3
-#define TX4938_TMR_REG(ch) ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100)
-#define TX4938_NR_SIO 2
-#define TX4938_SIO_REG(ch) ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100)
-#define TX4938_PIO_REG (TX4938_REG_BASE + 0xf500)
-#define TX4938_IRC_REG (TX4938_REG_BASE + 0xf600)
-#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700)
-#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800)
-
-struct tx4938_sramc_reg {
- u64 cr;
-};
-
-struct tx4938_ccfg_reg {
- u64 ccfg;
- u64 crir;
- u64 pcfg;
- u64 toea;
- u64 clkctr;
- u64 unused0;
- u64 garbc;
- u64 unused1;
- u64 unused2;
- u64 ramp;
- u64 unused3;
- u64 jmpadr;
-};
-
-/*
- * IRC
- */
-
-#define TX4938_IR_ECCERR 0
-#define TX4938_IR_WTOERR 1
-#define TX4938_NUM_IR_INT 6
-#define TX4938_IR_INT(n) (2 + (n))
-#define TX4938_NUM_IR_SIO 2
-#define TX4938_IR_SIO(n) (8 + (n))
-#define TX4938_NUM_IR_DMA 4
-#define TX4938_IR_DMA(ch, n) ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */
-#define TX4938_IR_PIO 14
-#define TX4938_IR_PDMAC 15
-#define TX4938_IR_PCIC 16
-#define TX4938_NUM_IR_TMR 3
-#define TX4938_IR_TMR(n) (17 + (n))
-#define TX4938_IR_NDFMC 21
-#define TX4938_IR_PCIERR 22
-#define TX4938_IR_PCIPME 23
-#define TX4938_IR_ACLC 24
-#define TX4938_IR_ACLCPME 25
-#define TX4938_IR_PCIC1 26
-#define TX4938_IR_SPI 31
-#define TX4938_NUM_IR 32
-/* multiplex */
-#define TX4938_IR_ETH0 TX4938_IR_INT(4)
-#define TX4938_IR_ETH1 TX4938_IR_INT(3)
-
-#define TX4938_IRC_INT 2 /* IP[2] in Status register */
-
-#define TX4938_NUM_PIO 16
-
-/*
- * CCFG
- */
-/* CCFG : Chip Configuration */
-#define TX4938_CCFG_WDRST 0x0000020000000000ULL
-#define TX4938_CCFG_WDREXEN 0x0000010000000000ULL
-#define TX4938_CCFG_BCFG_MASK 0x000000ff00000000ULL
-#define TX4938_CCFG_TINTDIS 0x01000000
-#define TX4938_CCFG_PCI66 0x00800000
-#define TX4938_CCFG_PCIMODE 0x00400000
-#define TX4938_CCFG_PCI1_66 0x00200000
-#define TX4938_CCFG_DIVMODE_MASK 0x001e0000
-#define TX4938_CCFG_DIVMODE_2 (0x4 << 17)
-#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17)
-#define TX4938_CCFG_DIVMODE_3 (0x5 << 17)
-#define TX4938_CCFG_DIVMODE_4 (0x6 << 17)
-#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17)
-#define TX4938_CCFG_DIVMODE_8 (0x0 << 17)
-#define TX4938_CCFG_DIVMODE_10 (0xb << 17)
-#define TX4938_CCFG_DIVMODE_12 (0x1 << 17)
-#define TX4938_CCFG_DIVMODE_16 (0x2 << 17)
-#define TX4938_CCFG_DIVMODE_18 (0x9 << 17)
-#define TX4938_CCFG_BEOW 0x00010000
-#define TX4938_CCFG_WR 0x00008000
-#define TX4938_CCFG_TOE 0x00004000
-#define TX4938_CCFG_PCIARB 0x00002000
-#define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00
-#define TX4938_CCFG_PCIDIVMODE_4 (0x1 << 10)
-#define TX4938_CCFG_PCIDIVMODE_4_5 (0x3 << 10)
-#define TX4938_CCFG_PCIDIVMODE_5 (0x5 << 10)
-#define TX4938_CCFG_PCIDIVMODE_5_5 (0x7 << 10)
-#define TX4938_CCFG_PCIDIVMODE_8 (0x0 << 10)
-#define TX4938_CCFG_PCIDIVMODE_9 (0x2 << 10)
-#define TX4938_CCFG_PCIDIVMODE_10 (0x4 << 10)
-#define TX4938_CCFG_PCIDIVMODE_11 (0x6 << 10)
-#define TX4938_CCFG_PCI1DMD 0x00000100
-#define TX4938_CCFG_SYSSP_MASK 0x000000c0
-#define TX4938_CCFG_ENDIAN 0x00000004
-#define TX4938_CCFG_HALT 0x00000002
-#define TX4938_CCFG_ACEHOLD 0x00000001
-
-/* PCFG : Pin Configuration */
-#define TX4938_PCFG_ETH0_SEL 0x8000000000000000ULL
-#define TX4938_PCFG_ETH1_SEL 0x4000000000000000ULL
-#define TX4938_PCFG_ATA_SEL 0x2000000000000000ULL
-#define TX4938_PCFG_ISA_SEL 0x1000000000000000ULL
-#define TX4938_PCFG_SPI_SEL 0x0800000000000000ULL
-#define TX4938_PCFG_NDF_SEL 0x0400000000000000ULL
-#define TX4938_PCFG_SDCLKDLY_MASK 0x30000000
-#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
-#define TX4938_PCFG_SYSCLKEN 0x08000000
-#define TX4938_PCFG_SDCLKEN_ALL 0x07800000
-#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
-#define TX4938_PCFG_PCICLKEN_ALL 0x003f0000
-#define TX4938_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
-#define TX4938_PCFG_SEL2 0x00000200
-#define TX4938_PCFG_SEL1 0x00000100
-#define TX4938_PCFG_DMASEL_ALL 0x0000000f
-#define TX4938_PCFG_DMASEL0_DRQ0 0x00000000
-#define TX4938_PCFG_DMASEL0_SIO1 0x00000001
-#define TX4938_PCFG_DMASEL1_DRQ1 0x00000000
-#define TX4938_PCFG_DMASEL1_SIO1 0x00000002
-#define TX4938_PCFG_DMASEL2_DRQ2 0x00000000
-#define TX4938_PCFG_DMASEL2_SIO0 0x00000004
-#define TX4938_PCFG_DMASEL3_DRQ3 0x00000000
-#define TX4938_PCFG_DMASEL3_SIO0 0x00000008
-
-/* CLKCTR : Clock Control */
-#define TX4938_CLKCTR_NDFCKD 0x0001000000000000ULL
-#define TX4938_CLKCTR_NDFRST 0x0000000100000000ULL
-#define TX4938_CLKCTR_ETH1CKD 0x80000000
-#define TX4938_CLKCTR_ETH0CKD 0x40000000
-#define TX4938_CLKCTR_SPICKD 0x20000000
-#define TX4938_CLKCTR_SRAMCKD 0x10000000
-#define TX4938_CLKCTR_PCIC1CKD 0x08000000
-#define TX4938_CLKCTR_DMA1CKD 0x04000000
-#define TX4938_CLKCTR_ACLCKD 0x02000000
-#define TX4938_CLKCTR_PIOCKD 0x01000000
-#define TX4938_CLKCTR_DMACKD 0x00800000
-#define TX4938_CLKCTR_PCICKD 0x00400000
-#define TX4938_CLKCTR_TM0CKD 0x00100000
-#define TX4938_CLKCTR_TM1CKD 0x00080000
-#define TX4938_CLKCTR_TM2CKD 0x00040000
-#define TX4938_CLKCTR_SIO0CKD 0x00020000
-#define TX4938_CLKCTR_SIO1CKD 0x00010000
-#define TX4938_CLKCTR_ETH1RST 0x00008000
-#define TX4938_CLKCTR_ETH0RST 0x00004000
-#define TX4938_CLKCTR_SPIRST 0x00002000
-#define TX4938_CLKCTR_SRAMRST 0x00001000
-#define TX4938_CLKCTR_PCIC1RST 0x00000800
-#define TX4938_CLKCTR_DMA1RST 0x00000400
-#define TX4938_CLKCTR_ACLRST 0x00000200
-#define TX4938_CLKCTR_PIORST 0x00000100
-#define TX4938_CLKCTR_DMARST 0x00000080
-#define TX4938_CLKCTR_PCIRST 0x00000040
-#define TX4938_CLKCTR_TM0RST 0x00000010
-#define TX4938_CLKCTR_TM1RST 0x00000008
-#define TX4938_CLKCTR_TM2RST 0x00000004
-#define TX4938_CLKCTR_SIO0RST 0x00000002
-#define TX4938_CLKCTR_SIO1RST 0x00000001
-
-/*
- * DMA
- */
-/* bits for MCR */
-#define TX4938_DMA_MCR_EIS(ch) (0x10000000<<(ch))
-#define TX4938_DMA_MCR_DIS(ch) (0x01000000<<(ch))
-#define TX4938_DMA_MCR_RSFIF 0x00000080
-#define TX4938_DMA_MCR_FIFUM(ch) (0x00000008<<(ch))
-#define TX4938_DMA_MCR_RPRT 0x00000002
-#define TX4938_DMA_MCR_MSTEN 0x00000001
-
-/* bits for CCRn */
-#define TX4938_DMA_CCR_IMMCHN 0x20000000
-#define TX4938_DMA_CCR_USEXFSZ 0x10000000
-#define TX4938_DMA_CCR_LE 0x08000000
-#define TX4938_DMA_CCR_DBINH 0x04000000
-#define TX4938_DMA_CCR_SBINH 0x02000000
-#define TX4938_DMA_CCR_CHRST 0x01000000
-#define TX4938_DMA_CCR_RVBYTE 0x00800000
-#define TX4938_DMA_CCR_ACKPOL 0x00400000
-#define TX4938_DMA_CCR_REQPL 0x00200000
-#define TX4938_DMA_CCR_EGREQ 0x00100000
-#define TX4938_DMA_CCR_CHDN 0x00080000
-#define TX4938_DMA_CCR_DNCTL 0x00060000
-#define TX4938_DMA_CCR_EXTRQ 0x00010000
-#define TX4938_DMA_CCR_INTRQD 0x0000e000
-#define TX4938_DMA_CCR_INTENE 0x00001000
-#define TX4938_DMA_CCR_INTENC 0x00000800
-#define TX4938_DMA_CCR_INTENT 0x00000400
-#define TX4938_DMA_CCR_CHNEN 0x00000200
-#define TX4938_DMA_CCR_XFACT 0x00000100
-#define TX4938_DMA_CCR_SMPCHN 0x00000020
-#define TX4938_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c)
-#define TX4938_DMA_CCR_XFSZ_1W TX4938_DMA_CCR_XFSZ(2)
-#define TX4938_DMA_CCR_XFSZ_2W TX4938_DMA_CCR_XFSZ(3)
-#define TX4938_DMA_CCR_XFSZ_4W TX4938_DMA_CCR_XFSZ(4)
-#define TX4938_DMA_CCR_XFSZ_8W TX4938_DMA_CCR_XFSZ(5)
-#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6)
-#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7)
-#define TX4938_DMA_CCR_MEMIO 0x00000002
-#define TX4938_DMA_CCR_SNGAD 0x00000001
-
-/* bits for CSRn */
-#define TX4938_DMA_CSR_CHNEN 0x00000400
-#define TX4938_DMA_CSR_STLXFER 0x00000200
-#define TX4938_DMA_CSR_CHNACT 0x00000100
-#define TX4938_DMA_CSR_ABCHC 0x00000080
-#define TX4938_DMA_CSR_NCHNC 0x00000040
-#define TX4938_DMA_CSR_NTRNFC 0x00000020
-#define TX4938_DMA_CSR_EXTDN 0x00000010
-#define TX4938_DMA_CSR_CFERR 0x00000008
-#define TX4938_DMA_CSR_CHERR 0x00000004
-#define TX4938_DMA_CSR_DESERR 0x00000002
-#define TX4938_DMA_CSR_SORERR 0x00000001
-
-#define tx4938_sdramcptr tx4927_sdramcptr
-#define tx4938_ebuscptr tx4927_ebuscptr
-#define tx4938_pcicptr tx4927_pcicptr
-#define tx4938_pcic1ptr \
- ((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG)
-#define tx4938_ccfgptr \
- ((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG)
-#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG)
-#define tx4938_sramcptr \
- ((struct tx4938_sramc_reg __iomem *)TX4938_SRAMC_REG)
-
-
-#define TX4938_REV_PCODE() \
- ((__u32)__raw_readq(&tx4938_ccfgptr->crir) >> 16)
-
-#define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits)
-#define tx4938_ccfg_set(bits) tx4927_ccfg_set(bits)
-#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new)
-
-#define TX4938_SDRAMC_CR(ch) TX4927_SDRAMC_CR(ch)
-#define TX4938_SDRAMC_BA(ch) TX4927_SDRAMC_BA(ch)
-#define TX4938_SDRAMC_SIZE(ch) TX4927_SDRAMC_SIZE(ch)
-
-#define TX4938_EBUSC_CR(ch) TX4927_EBUSC_CR(ch)
-#define TX4938_EBUSC_BA(ch) TX4927_EBUSC_BA(ch)
-#define TX4938_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch)
-
-#define tx4938_get_mem_size() tx4927_get_mem_size()
-void tx4938_wdt_init(void);
-void tx4938_setup(void);
-void tx4938_time_init(unsigned int tmrnr);
-void tx4938_sio_init(unsigned int sclk, unsigned int cts_mask);
-void tx4938_spi_init(int busid);
-void tx4938_ethaddr_init(unsigned char *addr0, unsigned char *addr1);
-int tx4938_report_pciclk(void);
-void tx4938_report_pci1clk(void);
-int tx4938_pciclk66_setup(void);
-struct pci_dev;
-int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
-void tx4938_setup_pcierr_irq(void);
-void tx4938_irq_init(void);
-
-#endif