diff options
Diffstat (limited to 'include/asm-powerpc')
| -rw-r--r-- | include/asm-powerpc/cpm.h | 73 | ||||
| -rw-r--r-- | include/asm-powerpc/cpm1.h (renamed from include/asm-powerpc/commproc.h) | 77 | ||||
| -rw-r--r-- | include/asm-powerpc/cpm2.h | 64 | ||||
| -rw-r--r-- | include/asm-powerpc/irq.h | 212 | ||||
| -rw-r--r-- | include/asm-powerpc/mpc8xx.h | 20 |
5 files changed, 78 insertions, 368 deletions
diff --git a/include/asm-powerpc/cpm.h b/include/asm-powerpc/cpm.h index fae83b13733..77e39dad972 100644 --- a/include/asm-powerpc/cpm.h +++ b/include/asm-powerpc/cpm.h @@ -4,6 +4,79 @@ #include <linux/compiler.h> #include <linux/types.h> +/* Buffer descriptors used by many of the CPM protocols. */ +typedef struct cpm_buf_desc { + ushort cbd_sc; /* Status and Control */ + ushort cbd_datlen; /* Data length in buffer */ + uint cbd_bufaddr; /* Buffer address in host memory */ +} cbd_t; + +/* Buffer descriptor control/status used by serial + */ + +#define BD_SC_EMPTY (0x8000) /* Receive is empty */ +#define BD_SC_READY (0x8000) /* Transmit is ready */ +#define BD_SC_WRAP (0x2000) /* Last buffer descriptor */ +#define BD_SC_INTRPT (0x1000) /* Interrupt on change */ +#define BD_SC_LAST (0x0800) /* Last buffer in frame */ +#define BD_SC_TC (0x0400) /* Transmit CRC */ +#define BD_SC_CM (0x0200) /* Continous mode */ +#define BD_SC_ID (0x0100) /* Rec'd too many idles */ +#define BD_SC_P (0x0100) /* xmt preamble */ +#define BD_SC_BR (0x0020) /* Break received */ +#define BD_SC_FR (0x0010) /* Framing error */ +#define BD_SC_PR (0x0008) /* Parity error */ +#define BD_SC_NAK (0x0004) /* NAK - did not respond */ +#define BD_SC_OV (0x0002) /* Overrun */ +#define BD_SC_UN (0x0002) /* Underrun */ +#define BD_SC_CD (0x0001) /* */ +#define BD_SC_CL (0x0001) /* Collision */ + +/* Buffer descriptor control/status used by Ethernet receive. + * Common to SCC and FCC. + */ +#define BD_ENET_RX_EMPTY (0x8000) +#define BD_ENET_RX_WRAP (0x2000) +#define BD_ENET_RX_INTR (0x1000) +#define BD_ENET_RX_LAST (0x0800) +#define BD_ENET_RX_FIRST (0x0400) +#define BD_ENET_RX_MISS (0x0100) +#define BD_ENET_RX_BC (0x0080) /* FCC Only */ +#define BD_ENET_RX_MC (0x0040) /* FCC Only */ +#define BD_ENET_RX_LG (0x0020) +#define BD_ENET_RX_NO (0x0010) +#define BD_ENET_RX_SH (0x0008) +#define BD_ENET_RX_CR (0x0004) +#define BD_ENET_RX_OV (0x0002) +#define BD_ENET_RX_CL (0x0001) +#define BD_ENET_RX_STATS (0x01ff) /* All status bits */ + +/* Buffer descriptor control/status used by Ethernet transmit. + * Common to SCC and FCC. + */ +#define BD_ENET_TX_READY (0x8000) +#define BD_ENET_TX_PAD (0x4000) +#define BD_ENET_TX_WRAP (0x2000) +#define BD_ENET_TX_INTR (0x1000) +#define BD_ENET_TX_LAST (0x0800) +#define BD_ENET_TX_TC (0x0400) +#define BD_ENET_TX_DEF (0x0200) +#define BD_ENET_TX_HB (0x0100) +#define BD_ENET_TX_LC (0x0080) +#define BD_ENET_TX_RL (0x0040) +#define BD_ENET_TX_RCMASK (0x003c) +#define BD_ENET_TX_UN (0x0002) +#define BD_ENET_TX_CSL (0x0001) +#define BD_ENET_TX_STATS (0x03ff) /* All status bits */ + +/* Buffer descriptor control/status used by Transparent mode SCC. + */ +#define BD_SCC_TX_LAST (0x0800) + +/* Buffer descriptor control/status used by I2C. + */ +#define BD_I2C_START (0x0400) + int cpm_muram_init(void); unsigned long cpm_muram_alloc(unsigned long size, unsigned long align); int cpm_muram_free(unsigned long offset); diff --git a/include/asm-powerpc/commproc.h b/include/asm-powerpc/cpm1.h index 9e3b8648648..b2ebd6ac6da 100644 --- a/include/asm-powerpc/commproc.h +++ b/include/asm-powerpc/cpm1.h @@ -14,8 +14,8 @@ * IDMA1 space. The remaining DP RAM is available for buffer descriptors * or other use. */ -#ifndef __CPM_8XX__ -#define __CPM_8XX__ +#ifndef __CPM1__ +#define __CPM1__ #include <asm/8xx_immap.h> #include <asm/ptrace.h> @@ -82,42 +82,14 @@ extern int cpm_dpfree(unsigned long offset); extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align); extern void cpm_dpdump(void); extern void *cpm_dpram_addr(unsigned long offset); -extern uint cpm_dpram_phys(u8* addr); +extern uint cpm_dpram_phys(u8 *addr); #endif extern void cpm_setbrg(uint brg, uint rate); -extern uint m8xx_cpm_hostalloc(uint size); -extern int m8xx_cpm_hostfree(uint start); -extern void m8xx_cpm_hostdump(void); - extern void cpm_load_patch(cpm8xx_t *cp); -/* Buffer descriptors used by many of the CPM protocols. -*/ -typedef struct cpm_buf_desc { - ushort cbd_sc; /* Status and Control */ - ushort cbd_datlen; /* Data length in buffer */ - uint cbd_bufaddr; /* Buffer address in host memory */ -} cbd_t; - -#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ -#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ -#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ -#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ -#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ -#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ -#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ -#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ -#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ -#define BD_SC_BR ((ushort)0x0020) /* Break received */ -#define BD_SC_FR ((ushort)0x0010) /* Framing error */ -#define BD_SC_PR ((ushort)0x0008) /* Parity error */ -#define BD_SC_NAK ((ushort)0x0004) /* NAK - did not respond */ -#define BD_SC_OV ((ushort)0x0002) /* Overrun */ -#define BD_SC_UN ((ushort)0x0002) /* Underrun */ -#define BD_SC_CD ((ushort)0x0001) /* ?? */ -#define BD_SC_CL ((ushort)0x0001) /* Collision */ +extern void cpm_reset(void); /* Parameter RAM offsets. */ @@ -448,41 +420,6 @@ typedef struct scc_enet { #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ -/* Buffer descriptor control/status used by Ethernet receive. -*/ -#define BD_ENET_RX_EMPTY ((ushort)0x8000) -#define BD_ENET_RX_WRAP ((ushort)0x2000) -#define BD_ENET_RX_INTR ((ushort)0x1000) -#define BD_ENET_RX_LAST ((ushort)0x0800) -#define BD_ENET_RX_FIRST ((ushort)0x0400) -#define BD_ENET_RX_MISS ((ushort)0x0100) -#define BD_ENET_RX_LG ((ushort)0x0020) -#define BD_ENET_RX_NO ((ushort)0x0010) -#define BD_ENET_RX_SH ((ushort)0x0008) -#define BD_ENET_RX_CR ((ushort)0x0004) -#define BD_ENET_RX_OV ((ushort)0x0002) -#define BD_ENET_RX_CL ((ushort)0x0001) -#define BD_ENET_RX_BC ((ushort)0x0080) /* DA is Broadcast */ -#define BD_ENET_RX_MC ((ushort)0x0040) /* DA is Multicast */ -#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ - -/* Buffer descriptor control/status used by Ethernet transmit. -*/ -#define BD_ENET_TX_READY ((ushort)0x8000) -#define BD_ENET_TX_PAD ((ushort)0x4000) -#define BD_ENET_TX_WRAP ((ushort)0x2000) -#define BD_ENET_TX_INTR ((ushort)0x1000) -#define BD_ENET_TX_LAST ((ushort)0x0800) -#define BD_ENET_TX_TC ((ushort)0x0400) -#define BD_ENET_TX_DEF ((ushort)0x0200) -#define BD_ENET_TX_HB ((ushort)0x0100) -#define BD_ENET_TX_LC ((ushort)0x0080) -#define BD_ENET_TX_RL ((ushort)0x0040) -#define BD_ENET_TX_RCMASK ((ushort)0x003c) -#define BD_ENET_TX_UN ((ushort)0x0002) -#define BD_ENET_TX_CSL ((ushort)0x0001) -#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ - /* SCC as UART */ typedef struct scc_uart { @@ -551,8 +488,6 @@ typedef struct scc_trans { uint st_cmask; /* Constant mask for CRC */ } scc_trans_t; -#define BD_SCC_TX_LAST ((ushort)0x0800) - /* IIC parameter RAM. */ typedef struct iic { @@ -576,8 +511,6 @@ typedef struct iic { char res2[2]; /* Reserved */ } iic_t; -#define BD_IIC_START ((ushort)0x0400) - /* SPI parameter RAM. */ typedef struct spi { @@ -749,4 +682,4 @@ enum cpm_clk { int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode); -#endif /* __CPM_8XX__ */ +#endif /* __CPM1__ */ diff --git a/include/asm-powerpc/cpm2.h b/include/asm-powerpc/cpm2.h index f1112c15ef9..b93a53eb55c 100644 --- a/include/asm-powerpc/cpm2.h +++ b/include/asm-powerpc/cpm2.h @@ -132,29 +132,6 @@ extern void cpm_setbrg(uint brg, uint rate); extern void cpm2_fastbrg(uint brg, uint rate, int div16); extern void cpm2_reset(void); - -/* Buffer descriptors used by many of the CPM protocols. -*/ -typedef struct cpm_buf_desc { - ushort cbd_sc; /* Status and Control */ - ushort cbd_datlen; /* Data length in buffer */ - uint cbd_bufaddr; /* Buffer address in host memory */ -} cbd_t; - -#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ -#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ -#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ -#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ -#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ -#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ -#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ -#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ -#define BD_SC_BR ((ushort)0x0020) /* Break received */ -#define BD_SC_FR ((ushort)0x0010) /* Framing error */ -#define BD_SC_PR ((ushort)0x0008) /* Parity error */ -#define BD_SC_OV ((ushort)0x0002) /* Overrun */ -#define BD_SC_CD ((ushort)0x0001) /* ?? */ - /* Function code bits, usually generic to devices. */ #define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */ @@ -456,43 +433,6 @@ typedef struct scc_enet { #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ -/* Buffer descriptor control/status used by Ethernet receive. - * Common to SCC and FCC. - */ -#define BD_ENET_RX_EMPTY ((ushort)0x8000) -#define BD_ENET_RX_WRAP ((ushort)0x2000) -#define BD_ENET_RX_INTR ((ushort)0x1000) -#define BD_ENET_RX_LAST ((ushort)0x0800) -#define BD_ENET_RX_FIRST ((ushort)0x0400) -#define BD_ENET_RX_MISS ((ushort)0x0100) -#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */ -#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */ -#define BD_ENET_RX_LG ((ushort)0x0020) -#define BD_ENET_RX_NO ((ushort)0x0010) -#define BD_ENET_RX_SH ((ushort)0x0008) -#define BD_ENET_RX_CR ((ushort)0x0004) -#define BD_ENET_RX_OV ((ushort)0x0002) -#define BD_ENET_RX_CL ((ushort)0x0001) -#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */ - -/* Buffer descriptor control/status used by Ethernet transmit. - * Common to SCC and FCC. - */ -#define BD_ENET_TX_READY ((ushort)0x8000) -#define BD_ENET_TX_PAD ((ushort)0x4000) -#define BD_ENET_TX_WRAP ((ushort)0x2000) -#define BD_ENET_TX_INTR ((ushort)0x1000) -#define BD_ENET_TX_LAST ((ushort)0x0800) -#define BD_ENET_TX_TC ((ushort)0x0400) -#define BD_ENET_TX_DEF ((ushort)0x0200) -#define BD_ENET_TX_HB ((ushort)0x0100) -#define BD_ENET_TX_LC ((ushort)0x0080) -#define BD_ENET_TX_RL ((ushort)0x0040) -#define BD_ENET_TX_RCMASK ((ushort)0x003c) -#define BD_ENET_TX_UN ((ushort)0x0002) -#define BD_ENET_TX_CSL ((ushort)0x0001) -#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ - /* SCC as UART */ typedef struct scc_uart { @@ -562,8 +502,6 @@ typedef struct scc_trans { uint st_cmask; /* Constant mask for CRC */ } scc_trans_t; -#define BD_SCC_TX_LAST ((ushort)0x0800) - /* How about some FCCs..... */ #define FCC_GFMR_DIAG_NORM ((uint)0x00000000) @@ -769,8 +707,6 @@ typedef struct spi { #define SPI_EB ((u_char)0x10) /* big endian byte order */ -#define BD_IIC_START ((ushort)0x0400) - /* IDMA parameter RAM */ typedef struct idma { diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h index 1392db45652..b5c03127a9b 100644 --- a/include/asm-powerpc/irq.h +++ b/include/asm-powerpc/irq.h @@ -483,218 +483,6 @@ static __inline__ int irq_canonicalize(int irq) */ #define mk_int_int_mask(IL) (1 << (7 - (IL/2))) -#elif defined(CONFIG_83xx) -#include <asm/mpc83xx.h> - -#define NR_IRQS (NR_IPIC_INTS) - -#elif defined(CONFIG_85xx) -/* Now include the board configuration specific associations. -*/ -#include <asm/mpc85xx.h> - -/* The MPC8548 openpic has 48 internal interrupts and 12 external - * interrupts. - * - * We are "flattening" the interrupt vectors of the cascaded CPM - * so that we can uniquely identify any interrupt source with a - * single integer. - */ -#define NR_CPM_INTS 64 -#define NR_EPIC_INTS 60 -#ifndef NR_8259_INTS -#define NR_8259_INTS 0 -#endif -#define NUM_8259_INTERRUPTS NR_8259_INTS - -#ifndef CPM_IRQ_OFFSET -#define CPM_IRQ_OFFSET 0 -#endif - -#define NR_IRQS (NR_EPIC_INTS + NR_CPM_INTS + NR_8259_INTS) - -/* Internal IRQs on MPC85xx OpenPIC */ - -#ifndef MPC85xx_OPENPIC_IRQ_OFFSET -#ifdef CONFIG_CPM2 -#define MPC85xx_OPENPIC_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS) -#else -#define MPC85xx_OPENPIC_IRQ_OFFSET 0 -#endif -#endif - -/* Not all of these exist on all MPC85xx implementations */ -#define MPC85xx_IRQ_L2CACHE ( 0 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_ECM ( 1 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_DDR ( 2 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_LBIU ( 3 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_DMA0 ( 4 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_DMA1 ( 5 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_DMA2 ( 6 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_DMA3 ( 7 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_PCI1 ( 8 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_PCI2 ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_RIO_ERROR ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_RIO_BELL (10 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_RIO_TX (11 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_RIO_RX (12 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC1_TX (13 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC1_RX (14 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC3_TX (15 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC3_RX (16 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC3_ERROR (17 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC2_TX (19 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC2_RX (20 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC4_TX (21 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC4_RX (22 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC4_ERROR (23 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_FEC (25 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_DUART (26 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_IIC1 (27 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_PERFMON (28 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_SEC2 (29 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_CPM (30 + MPC85xx_OPENPIC_IRQ_OFFSET) - -/* The 12 external interrupt lines */ -#define MPC85xx_IRQ_EXT0 (48 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT1 (49 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT2 (50 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT3 (51 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT4 (52 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT5 (53 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT6 (54 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT7 (55 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT8 (56 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT9 (57 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT10 (58 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT11 (59 + MPC85xx_OPENPIC_IRQ_OFFSET) - -/* CPM related interrupts */ -#define SIU_INT_ERROR ((uint)0x00+CPM_IRQ_OFFSET) -#define SIU_INT_I2C ((uint)0x01+CPM_IRQ_OFFSET) -#define SIU_INT_SPI ((uint)0x02+CPM_IRQ_OFFSET) -#define SIU_INT_RISC ((uint)0x03+CPM_IRQ_OFFSET) -#define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET) -#define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET) -#define SIU_INT_USB ((uint)0x0b+CPM_IRQ_OFFSET) -#define SIU_INT_TIMER1 ((uint)0x0c+CPM_IRQ_OFFSET) -#define SIU_INT_TIMER2 ((uint)0x0d+CPM_IRQ_OFFSET) -#define SIU_INT_TIMER3 ((uint)0x0e+CPM_IRQ_OFFSET) -#define SIU_INT_TIMER4 ((uint)0x0f+CPM_IRQ_OFFSET) -#define SIU_INT_FCC1 ((uint)0x20+CPM_IRQ_OFFSET) -#define SIU_INT_FCC2 ((uint)0x21+CPM_IRQ_OFFSET) -#define SIU_INT_FCC3 ((uint)0x22+CPM_IRQ_OFFSET) -#define SIU_INT_MCC1 ((uint)0x24+CPM_IRQ_OFFSET) -#define SIU_INT_MCC2 ((uint)0x25+CPM_IRQ_OFFSET) -#define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET) -#define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET) -#define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET) -#define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET) -#define SIU_INT_PC15 ((uint)0x30+CPM_IRQ_OFFSET) -#define SIU_INT_PC14 ((uint)0x31+CPM_IRQ_OFFSET) -#define SIU_INT_PC13 ((uint)0x32+CPM_IRQ_OFFSET) -#define SIU_INT_PC12 ((uint)0x33+CPM_IRQ_OFFSET) -#define SIU_INT_PC11 ((uint)0x34+CPM_IRQ_OFFSET) -#define SIU_INT_PC10 ((uint)0x35+CPM_IRQ_OFFSET) -#define SIU_INT_PC9 ((uint)0x36+CPM_IRQ_OFFSET) -#define SIU_INT_PC8 ((uint)0x37+CPM_IRQ_OFFSET) -#define SIU_INT_PC7 ((uint)0x38+CPM_IRQ_OFFSET) -#define SIU_INT_PC6 ((uint)0x39+CPM_IRQ_OFFSET) -#define SIU_INT_PC5 ((uint)0x3a+CPM_IRQ_OFFSET) -#define SIU_INT_PC4 ((uint)0x3b+CPM_IRQ_OFFSET) -#define SIU_INT_PC3 ((uint)0x3c+CPM_IRQ_OFFSET) -#define SIU_INT_PC2 ((uint)0x3d+CPM_IRQ_OFFSET) -#define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET) -#define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET) - -#elif defined(CONFIG_PPC_86xx) -#include <asm/mpc86xx.h> - -#define NR_EPIC_INTS 48 -#ifndef NR_8259_INTS -#define NR_8259_INTS 16 /*ULI 1575 can route 12 interrupts */ -#endif -#define NUM_8259_INTERRUPTS NR_8259_INTS - -#ifndef I8259_OFFSET -#define I8259_OFFSET 0 -#endif - -#define NR_IRQS 256 - -/* Internal IRQs on MPC86xx OpenPIC */ - -#ifndef MPC86xx_OPENPIC_IRQ_OFFSET -#define MPC86xx_OPENPIC_IRQ_OFFSET NR_8259_INTS -#endif - -/* The 48 internal sources */ -#define MPC86xx_IRQ_NULL ( 0 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_MCM ( 1 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_DDR ( 2 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_LBC ( 3 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_DMA0 ( 4 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_DMA1 ( 5 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_DMA2 ( 6 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_DMA3 ( 7 + MPC86xx_OPENPIC_IRQ_OFFSET) - -/* no 10,11 */ -#define MPC86xx_IRQ_UART2 (12 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC1_TX (13 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC1_RX (14 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC3_TX (15 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC3_RX (16 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC3_ERROR (17 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC1_ERROR (18 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC2_TX (19 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC2_RX (20 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC4_TX (21 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC4_RX (22 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC4_ERROR (23 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC2_ERROR (24 + MPC86xx_OPENPIC_IRQ_OFFSET) -/* no 25 */ -#define MPC86xx_IRQ_UART1 (26 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_IIC (27 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_PERFMON (28 + MPC86xx_OPENPIC_IRQ_OFFSET) -/* no 29,30,31 */ -#define MPC86xx_IRQ_SRIO_ERROR (32 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_SRIO_OUT_BELL (33 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_SRIO_IN_BELL (34 + MPC86xx_OPENPIC_IRQ_OFFSET) -/* no 35,36 */ -#define MPC86xx_IRQ_SRIO_OUT_MSG1 (37 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_SRIO_IN_MSG1 (38 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_SRIO_OUT_MSG2 (39 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_SRIO_IN_MSG2 (40 + MPC86xx_OPENPIC_IRQ_OFFSET) - -/* The 12 external interrupt lines */ -#define MPC86xx_IRQ_EXT_BASE 48 -#define MPC86xx_IRQ_EXT0 (0 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT1 (1 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT2 (2 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT3 (3 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT4 (4 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT5 (5 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT6 (6 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT7 (7 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT8 (8 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT9 (9 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT10 (10 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT11 (11 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) - #else /* CONFIG_40x + CONFIG_8xx */ /* * this is the # irq's for all ppc arch's (pmac/chrp/prep) diff --git a/include/asm-powerpc/mpc8xx.h b/include/asm-powerpc/mpc8xx.h index 2be014b6f57..98f3c4f1732 100644 --- a/include/asm-powerpc/mpc8xx.h +++ b/include/asm-powerpc/mpc8xx.h @@ -4,29 +4,9 @@ * file that has to include MPC8xx configuration, they all include * this one and the configuration switching is done here. */ -#ifdef __KERNEL__ #ifndef __CONFIG_8xx_DEFS #define __CONFIG_8xx_DEFS - -#ifdef CONFIG_8xx - -#ifdef CONFIG_FADS -#include <platforms/fads.h> -#endif - -#if defined(CONFIG_MPC86XADS) -#include <platforms/8xx/mpc86xads.h> -#endif - -#if defined(CONFIG_MPC885ADS) -#include <platforms/8xx/mpc885ads.h> -#endif - -#ifdef CONFIG_PCMCIA_M8XX extern struct mpc8xx_pcmcia_ops m8xx_pcmcia_ops; -#endif -#endif /* CONFIG_8xx */ #endif /* __CONFIG_8xx_DEFS */ -#endif /* __KERNEL__ */ |