diff options
Diffstat (limited to 'include')
496 files changed, 14412 insertions, 7157 deletions
diff --git a/include/acpi/acpi_numa.h b/include/acpi/acpi_numa.h index b62cd36ff32..e2fcee2b340 100644 --- a/include/acpi/acpi_numa.h +++ b/include/acpi/acpi_numa.h @@ -13,7 +13,7 @@ extern int pxm_to_node(int); extern int node_to_pxm(int); -extern int __cpuinit acpi_map_pxm_to_node(int); +extern int acpi_map_pxm_to_node(int); extern void __cpuinit acpi_unmap_pxm_to_node(int); #endif /* CONFIG_ACPI_NUMA */ diff --git a/include/acpi/acpiosxf.h b/include/acpi/acpiosxf.h index 5e07db0d46e..ca882b8e7d1 100644 --- a/include/acpi/acpiosxf.h +++ b/include/acpi/acpiosxf.h @@ -78,7 +78,7 @@ struct acpi_signal_fatal_info { /* * OSL Initialization and shutdown primitives */ -acpi_status acpi_os_initialize(void); +acpi_status __initdata acpi_os_initialize(void); acpi_status acpi_os_terminate(void); @@ -236,6 +236,7 @@ acpi_os_derive_pci_id(acpi_handle rhandle, * Miscellaneous */ acpi_status acpi_os_validate_interface(char *interface); +acpi_status acpi_osi_invalidate(char* interface); acpi_status acpi_os_validate_address(u8 space_id, diff --git a/include/acpi/acpixf.h b/include/acpi/acpixf.h index e08f7df85a4..b5cca5daa34 100644 --- a/include/acpi/acpixf.h +++ b/include/acpi/acpixf.h @@ -55,7 +55,7 @@ acpi_status acpi_initialize_tables(struct acpi_table_desc *initial_storage, u32 initial_table_count, u8 allow_resize); -acpi_status acpi_initialize_subsystem(void); +acpi_status __init acpi_initialize_subsystem(void); acpi_status acpi_enable_subsystem(u32 flags); diff --git a/include/acpi/acutils.h b/include/acpi/acutils.h index 15a838862cd..a87ef1c8d46 100644 --- a/include/acpi/acutils.h +++ b/include/acpi/acutils.h @@ -390,6 +390,8 @@ void acpi_ut_delete_object_desc(union acpi_operand_object *object); u8 acpi_ut_valid_internal_object(void *object); +union acpi_operand_object *acpi_ut_create_package_object(u32 count); + union acpi_operand_object *acpi_ut_create_buffer_object(acpi_size buffer_size); union acpi_operand_object *acpi_ut_create_string_object(acpi_size string_size); diff --git a/include/asm-alpha/core_t2.h b/include/asm-alpha/core_t2.h index 457c34b6eb0..90e6b5d6c21 100644 --- a/include/asm-alpha/core_t2.h +++ b/include/asm-alpha/core_t2.h @@ -437,9 +437,15 @@ static inline void t2_outl(u32 b, unsigned long addr) static DEFINE_SPINLOCK(t2_hae_lock); +/* + * NOTE: take T2_DENSE_MEM off in each readX/writeX routine, since + * they may be called directly, rather than through the + * ioreadNN/iowriteNN routines. + */ + __EXTERN_INLINE u8 t2_readb(const volatile void __iomem *xaddr) { - unsigned long addr = (unsigned long) xaddr; + unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; unsigned long result, msb; unsigned long flags; spin_lock_irqsave(&t2_hae_lock, flags); @@ -453,7 +459,7 @@ __EXTERN_INLINE u8 t2_readb(const volatile void __iomem *xaddr) __EXTERN_INLINE u16 t2_readw(const volatile void __iomem *xaddr) { - unsigned long addr = (unsigned long) xaddr; + unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; unsigned long result, msb; unsigned long flags; spin_lock_irqsave(&t2_hae_lock, flags); @@ -471,7 +477,7 @@ __EXTERN_INLINE u16 t2_readw(const volatile void __iomem *xaddr) */ __EXTERN_INLINE u32 t2_readl(const volatile void __iomem *xaddr) { - unsigned long addr = (unsigned long) xaddr; + unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; unsigned long result, msb; unsigned long flags; spin_lock_irqsave(&t2_hae_lock, flags); @@ -485,7 +491,7 @@ __EXTERN_INLINE u32 t2_readl(const volatile void __iomem *xaddr) __EXTERN_INLINE u64 t2_readq(const volatile void __iomem *xaddr) { - unsigned long addr = (unsigned long) xaddr; + unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; unsigned long r0, r1, work, msb; unsigned long flags; spin_lock_irqsave(&t2_hae_lock, flags); @@ -501,7 +507,7 @@ __EXTERN_INLINE u64 t2_readq(const volatile void __iomem *xaddr) __EXTERN_INLINE void t2_writeb(u8 b, volatile void __iomem *xaddr) { - unsigned long addr = (unsigned long) xaddr; + unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; unsigned long msb, w; unsigned long flags; spin_lock_irqsave(&t2_hae_lock, flags); @@ -515,7 +521,7 @@ __EXTERN_INLINE void t2_writeb(u8 b, volatile void __iomem *xaddr) __EXTERN_INLINE void t2_writew(u16 b, volatile void __iomem *xaddr) { - unsigned long addr = (unsigned long) xaddr; + unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; unsigned long msb, w; unsigned long flags; spin_lock_irqsave(&t2_hae_lock, flags); @@ -533,7 +539,7 @@ __EXTERN_INLINE void t2_writew(u16 b, volatile void __iomem *xaddr) */ __EXTERN_INLINE void t2_writel(u32 b, volatile void __iomem *xaddr) { - unsigned long addr = (unsigned long) xaddr; + unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; unsigned long msb; unsigned long flags; spin_lock_irqsave(&t2_hae_lock, flags); @@ -546,7 +552,7 @@ __EXTERN_INLINE void t2_writel(u32 b, volatile void __iomem *xaddr) __EXTERN_INLINE void t2_writeq(u64 b, volatile void __iomem *xaddr) { - unsigned long addr = (unsigned long) xaddr; + unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; unsigned long msb, work; unsigned long flags; spin_lock_irqsave(&t2_hae_lock, flags); @@ -587,14 +593,14 @@ __EXTERN_INLINE int t2_is_mmio(const volatile void __iomem *addr) __EXTERN_INLINE unsigned int t2_ioread##NS(void __iomem *xaddr) \ { \ if (t2_is_mmio(xaddr)) \ - return t2_read##OS(xaddr - T2_DENSE_MEM); \ + return t2_read##OS(xaddr); \ else \ return t2_in##OS((unsigned long)xaddr - T2_IO); \ } \ __EXTERN_INLINE void t2_iowrite##NS(u##NS b, void __iomem *xaddr) \ { \ if (t2_is_mmio(xaddr)) \ - t2_write##OS(b, xaddr - T2_DENSE_MEM); \ + t2_write##OS(b, xaddr); \ else \ t2_out##OS(b, (unsigned long)xaddr - T2_IO); \ } diff --git a/include/asm-alpha/core_titan.h b/include/asm-alpha/core_titan.h index a64ccbff7d9..a17f6f33b68 100644 --- a/include/asm-alpha/core_titan.h +++ b/include/asm-alpha/core_titan.h @@ -380,12 +380,7 @@ struct el_PRIVATEER_envdata_mcheck { /* * Memory functions. all accesses are done through linear space. */ - -__EXTERN_INLINE void __iomem *titan_ioportmap(unsigned long addr) -{ - return (void __iomem *)(addr + TITAN_IO_BIAS); -} - +extern void __iomem *titan_ioportmap(unsigned long addr); extern void __iomem *titan_ioremap(unsigned long addr, unsigned long size); extern void titan_iounmap(volatile void __iomem *addr); diff --git a/include/asm-alpha/core_tsunami.h b/include/asm-alpha/core_tsunami.h index 44e635d2c57..58d4fe48742 100644 --- a/include/asm-alpha/core_tsunami.h +++ b/include/asm-alpha/core_tsunami.h @@ -2,6 +2,7 @@ #define __ALPHA_TSUNAMI__H__ #include <linux/types.h> +#include <linux/pci.h> #include <asm/compiler.h> /* @@ -302,18 +303,8 @@ struct el_TSUNAMI_sysdata_mcheck { /* * Memory functions. all accesses are done through linear space. */ - -__EXTERN_INLINE void __iomem *tsunami_ioportmap(unsigned long addr) -{ - return (void __iomem *)(addr + TSUNAMI_IO_BIAS); -} - -__EXTERN_INLINE void __iomem *tsunami_ioremap(unsigned long addr, - unsigned long size) -{ - return (void __iomem *)(addr + TSUNAMI_MEM_BIAS); -} - +extern void __iomem *tsunami_ioportmap(unsigned long addr); +extern void __iomem *tsunami_ioremap(unsigned long addr, unsigned long size); __EXTERN_INLINE int tsunami_is_ioaddr(unsigned long addr) { return addr >= TSUNAMI_BASE; diff --git a/include/asm-alpha/core_wildfire.h b/include/asm-alpha/core_wildfire.h index 12af803d445..cd562f544ba 100644 --- a/include/asm-alpha/core_wildfire.h +++ b/include/asm-alpha/core_wildfire.h @@ -295,7 +295,7 @@ __EXTERN_INLINE int wildfire_is_ioaddr(unsigned long addr) __EXTERN_INLINE int wildfire_is_mmio(const volatile void __iomem *xaddr) { - unsigned long addr = (unsigned long)addr; + unsigned long addr = (unsigned long)xaddr; return (addr & 0x100000000UL) == 0; } diff --git a/include/asm-alpha/pci.h b/include/asm-alpha/pci.h index 85aa1127c90..30ee7669b19 100644 --- a/include/asm-alpha/pci.h +++ b/include/asm-alpha/pci.h @@ -199,30 +199,6 @@ pci_dma_sync_sg_for_device(struct pci_dev *dev, struct scatterlist *sg, extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask); -/* True if the machine supports DAC addressing, and DEV can - make use of it given MASK. */ -extern int pci_dac_dma_supported(struct pci_dev *hwdev, u64 mask); - -/* Convert to/from DAC dma address and struct page. */ -extern dma64_addr_t pci_dac_page_to_dma(struct pci_dev *, struct page *, - unsigned long, int); -extern struct page *pci_dac_dma_to_page(struct pci_dev *, dma64_addr_t); -extern unsigned long pci_dac_dma_to_offset(struct pci_dev *, dma64_addr_t); - -static inline void -pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev, dma64_addr_t dma_addr, - size_t len, int direction) -{ - /* Nothing to do. */ -} - -static inline void -pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, dma64_addr_t dma_addr, - size_t len, int direction) -{ - /* Nothing to do. */ -} - #ifdef CONFIG_PCI static inline void pci_dma_burst_advice(struct pci_dev *pdev, enum pci_dma_burst_strategy *strat, @@ -275,11 +251,6 @@ static inline int pci_proc_domain(struct pci_bus *bus) return hose->need_domain_info; } -static inline void -pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - struct pci_dev *alpha_gendev_to_pci(struct device *dev); #endif /* __KERNEL__ */ diff --git a/include/asm-alpha/vga.h b/include/asm-alpha/vga.h index ed06f59b544..e8df1e7aae6 100644 --- a/include/asm-alpha/vga.h +++ b/include/asm-alpha/vga.h @@ -46,6 +46,37 @@ extern void scr_memcpyw(u16 *d, const u16 *s, unsigned int count); #define vga_readb(a) readb((u8 __iomem *)(a)) #define vga_writeb(v,a) writeb(v, (u8 __iomem *)(a)) +#ifdef CONFIG_VGA_HOSE +#include <linux/ioport.h> +#include <linux/pci.h> + +extern struct pci_controller *pci_vga_hose; + +# define __is_port_vga(a) \ + (((a) >= 0x3b0) && ((a) < 0x3e0) && \ + ((a) != 0x3b3) && ((a) != 0x3d3)) + +# define __is_mem_vga(a) \ + (((a) >= 0xa0000) && ((a) <= 0xc0000)) + +# define FIXUP_IOADDR_VGA(a) do { \ + if (pci_vga_hose && __is_port_vga(a)) \ + (a) += pci_vga_hose->io_space->start; \ + } while(0) + +# define FIXUP_MEMADDR_VGA(a) do { \ + if (pci_vga_hose && __is_mem_vga(a)) \ + (a) += pci_vga_hose->mem_space->start; \ + } while(0) + +#else /* CONFIG_VGA_HOSE */ +# define pci_vga_hose 0 +# define __is_port_vga(a) 0 +# define __is_mem_vga(a) 0 +# define FIXUP_IOADDR_VGA(a) +# define FIXUP_MEMADDR_VGA(a) +#endif /* CONFIG_VGA_HOSE */ + #define VGA_MAP_MEM(x,s) ((unsigned long) ioremap(x, s)) #endif diff --git a/include/asm-arm/Kbuild b/include/asm-arm/Kbuild index c68e1680da0..73237bd130a 100644 --- a/include/asm-arm/Kbuild +++ b/include/asm-arm/Kbuild @@ -1 +1,3 @@ include include/asm-generic/Kbuild.asm + +unifdef-y += hwcap.h diff --git a/include/asm-arm/arch-at91/at91_dbgu.h b/include/asm-arm/arch-at91/at91_dbgu.h index b0369e176f7..8019ffd0ad3 100644 --- a/include/asm-arm/arch-at91/at91_dbgu.h +++ b/include/asm-arm/arch-at91/at91_dbgu.h @@ -16,6 +16,7 @@ #ifndef AT91_DBGU_H #define AT91_DBGU_H +#ifdef AT91_DBGU #define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */ #define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */ #define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */ @@ -30,6 +31,15 @@ #define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */ #define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */ +#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */ +#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ + +#endif /* AT91_DBGU */ + +/* + * Some AT91 parts that don't have full DEBUG units still support the ID + * and extensions register. + */ #define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */ #define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */ #define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */ @@ -53,7 +63,4 @@ #define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */ #define AT91_CIDR_EXT (1 << 31) /* Extension Flag */ -#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */ -#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ - #endif diff --git a/include/asm-arm/arch-at91/at91_shdwc.h b/include/asm-arm/arch-at91/at91_shdwc.h index 795fcc26622..01b433de227 100644 --- a/include/asm-arm/arch-at91/at91_shdwc.h +++ b/include/asm-arm/arch-at91/at91_shdwc.h @@ -14,8 +14,8 @@ #define AT91_SHDWC_H #define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */ -#define AT91_SHDW_SHDW (1 << 0) /* Processor Reset */ -#define AT91_SHDW_KEY (0xff << 24) /* KEY Password */ +#define AT91_SHDW_SHDW (1 << 0) /* Shut Down command */ +#define AT91_SHDW_KEY (0xa5 << 24) /* KEY Password */ #define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */ #define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */ diff --git a/include/asm-arm/arch-at91/at91_wdt.h b/include/asm-arm/arch-at91/at91_wdt.h index 7251a344c74..1014e9bf181 100644 --- a/include/asm-arm/arch-at91/at91_wdt.h +++ b/include/asm-arm/arch-at91/at91_wdt.h @@ -15,7 +15,7 @@ #define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */ #define AT91_WDT_WDRSTT (1 << 0) /* Restart */ -#define AT91_WDT_KEY (0xff << 24) /* KEY Password */ +#define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */ #define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */ #define AT91_WDT_WDV (0xfff << 0) /* Counter Value */ diff --git a/include/asm-arm/arch-at91/at91x40.h b/include/asm-arm/arch-at91/at91x40.h new file mode 100644 index 00000000000..612203e0177 --- /dev/null +++ b/include/asm-arm/arch-at91/at91x40.h @@ -0,0 +1,55 @@ +/* + * include/asm-arm/arch-at91/at91x40.h + * + * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91X40_H +#define AT91X40_H + +/* + * IRQ list. + */ +#define AT91_ID_FIQ 0 /* FIQ */ +#define AT91_ID_SYS 1 /* System Peripheral */ +#define AT91X40_ID_USART0 2 /* USART port 0 */ +#define AT91X40_ID_USART1 3 /* USART port 1 */ +#define AT91X40_ID_TC0 4 /* Timer/Counter 0 */ +#define AT91X40_ID_TC1 5 /* Timer/Counter 1*/ +#define AT91X40_ID_TC2 6 /* Timer/Counter 2*/ +#define AT91X40_ID_WD 7 /* Watchdog? */ +#define AT91X40_ID_PIOA 8 /* Parallel IO Controller A */ + +#define AT91X40_ID_IRQ0 16 /* External IRQ 0 */ +#define AT91X40_ID_IRQ1 17 /* External IRQ 1 */ +#define AT91X40_ID_IRQ2 18 /* External IRQ 2 */ + +/* + * System Peripherals (offset from AT91_BASE_SYS) + */ +#define AT91_BASE_SYS 0xffc00000 + +#define AT91_EBI (0xffe00000 - AT91_BASE_SYS) /* External Bus Interface */ +#define AT91_SF (0xfff00000 - AT91_BASE_SYS) /* Special Function */ +#define AT91_USART1 (0xfffcc000 - AT91_BASE_SYS) /* USART 1 */ +#define AT91_USART0 (0xfffd0000 - AT91_BASE_SYS) /* USART 0 */ +#define AT91_TC (0xfffe0000 - AT91_BASE_SYS) /* Timer Counter */ +#define AT91_PIOA (0xffff0000 - AT91_BASE_SYS) /* PIO Controller A */ +#define AT91_PS (0xffff4000 - AT91_BASE_SYS) /* Power Save */ +#define AT91_WD (0xffff8000 - AT91_BASE_SYS) /* Watchdog Timer */ +#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */ + +/* + * The AT91x40 series doesn't have a debug unit like the other AT91 parts. + * But it does have a chip identify register and extension ID, so define at + * least these here. + */ +#define AT91_DBGU_CIDR (AT91_SF + 0) /* CIDR in PS segment */ +#define AT91_DBGU_EXID (AT91_SF + 4) /* EXID in PS segment */ + +#endif /* AT91X40_H */ diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h index ef93c30a9c5..080cbb401a8 100644 --- a/include/asm-arm/arch-at91/cpu.h +++ b/include/asm-arm/arch-at91/cpu.h @@ -28,6 +28,11 @@ #define ARCH_ID_AT91SAM9RL64 0x019b03a0 +#define ARCH_ID_AT91M40800 0x14080044 +#define ARCH_ID_AT91R40807 0x44080746 +#define ARCH_ID_AT91M40807 0x14080745 +#define ARCH_ID_AT91R40008 0x44000840 + static inline unsigned long at91_cpu_identify(void) { return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h index 46835e945ae..8f1cdd38a96 100644 --- a/include/asm-arm/arch-at91/hardware.h +++ b/include/asm-arm/arch-at91/hardware.h @@ -26,18 +26,29 @@ #include <asm/arch/at91sam9263.h> #elif defined(CONFIG_ARCH_AT91SAM9RL) #include <asm/arch/at91sam9rl.h> +#elif defined(CONFIG_ARCH_AT91X40) +#include <asm/arch/at91x40.h> #else #error "Unsupported AT91 processor" #endif +#ifdef CONFIG_MMU /* * Remap the peripherals from address 0xFFF78000 .. 0xFFFFFFFF * to 0xFEF78000 .. 0xFF000000. (544Kb) */ #define AT91_IO_PHYS_BASE 0xFFF78000 -#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1) #define AT91_IO_VIRT_BASE (0xFF000000 - AT91_IO_SIZE) +#else +/* + * Identity mapping for the non MMU case. + */ +#define AT91_IO_PHYS_BASE AT91_BASE_SYS +#define AT91_IO_VIRT_BASE AT91_IO_PHYS_BASE +#endif + +#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1) /* Convert a physical IO address to virtual IO address */ #define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE) @@ -66,7 +77,11 @@ #define AT91_CHIPSELECT_7 0x80000000 /* SDRAM */ +#ifdef CONFIG_DRAM_BASE +#define AT91_SDRAM_BASE CONFIG_DRAM_BASE +#else #define AT91_SDRAM_BASE AT91_CHIPSELECT_1 +#endif /* Clocks */ #define AT91_SLOW_CLOCK 32768 /* slow clock */ diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h index 2df1ee12dfb..a310698fb4d 100644 --- a/include/asm-arm/arch-at91/timex.h +++ b/include/asm-arm/arch-at91/timex.h @@ -42,6 +42,11 @@ #define AT91SAM9_MASTER_CLOCK 100000000 #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) +#elif defined(CONFIG_ARCH_AT91X40) + +#define AT91X40_MASTER_CLOCK 40000000 +#define CLOCK_TICK_RATE (AT91X40_MASTER_CLOCK) + #endif #endif diff --git a/include/asm-arm/arch-at91/uncompress.h b/include/asm-arm/arch-at91/uncompress.h index 30ac587b3b4..272a7e0dc6c 100644 --- a/include/asm-arm/arch-at91/uncompress.h +++ b/include/asm-arm/arch-at91/uncompress.h @@ -33,20 +33,24 @@ */ static void putc(int c) { +#ifdef AT91_DBGU void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) barrier(); __raw_writel(c, sys + AT91_DBGU_THR); +#endif } static inline void flush(void) { +#ifdef AT91_DBGU void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ /* wait for transmission to complete */ while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY)) barrier(); +#endif } #define arch_decomp_setup() diff --git a/include/asm-arm/arch-davinci/clock.h b/include/asm-arm/arch-davinci/clock.h new file mode 100644 index 00000000000..cc168b7a14f --- /dev/null +++ b/include/asm-arm/arch-davinci/clock.h @@ -0,0 +1,22 @@ +/* + * include/asm-arm/arch-davinci/clock.h + * + * Clock control driver for DaVinci - header file + * + * Authors: Vladimir Barinov <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_DAVINCI_CLOCK_H +#define __ASM_ARCH_DAVINCI_CLOCK_H + +struct clk; + +extern int clk_register(struct clk *clk); +extern void clk_unregister(struct clk *clk); +extern int davinci_clk_init(void); + +#endif diff --git a/include/asm-arm/arch-davinci/gpio.h b/include/asm-arm/arch-davinci/gpio.h new file mode 100644 index 00000000000..ea24a0e0bfd --- /dev/null +++ b/include/asm-arm/arch-davinci/gpio.h @@ -0,0 +1,156 @@ +/* + * TI DaVinci GPIO Support + * + * Copyright (c) 2006 David Brownell + * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __DAVINCI_GPIO_H +#define __DAVINCI_GPIO_H + +/* + * basic gpio routines + * + * board-specific init should be done by arch/.../.../board-XXX.c (maybe + * initializing banks together) rather than boot loaders; kexec() won't + * go through boot loaders. + * + * the gpio clock will be turned on when gpios are used, and you may also + * need to pay attention to PINMUX0 and PINMUX1 to be sure those pins are + * used as gpios, not with other peripherals. + * + * GPIOs are numbered 0..(DAVINCI_N_GPIO-1). For documentation, and maybe + * for later updates, code should write GPIO(N) or: + * - GPIOV18(N) for 1.8V pins, N in 0..53; same as GPIO(0)..GPIO(53) + * - GPIOV33(N) for 3.3V pins, N in 0..17; same as GPIO(54)..GPIO(70) + * + * For GPIO IRQs use gpio_to_irq(GPIO(N)) or gpio_to_irq(GPIOV33(N)) etc + * for now, that's != GPIO(N) + */ +#define GPIO(X) (X) /* 0 <= X <= 70 */ +#define GPIOV18(X) (X) /* 1.8V i/o; 0 <= X <= 53 */ +#define GPIOV33(X) ((X)+54) /* 3.3V i/o; 0 <= X <= 17 */ + +struct gpio_controller { + u32 dir; + u32 out_data; + u32 set_data; + u32 clr_data; + u32 in_data; + u32 set_rising; + u32 clr_rising; + u32 set_falling; + u32 clr_falling; + u32 intstat; +}; + +/* The __gpio_to_controller() and __gpio_mask() functions inline to constants + * with constant parameters; or in outlined code they execute at runtime. + * + * You'd access the controller directly when reading or writing more than + * one gpio value at a time, and to support wired logic where the value + * being driven by the cpu need not match the value read back. + * + * These are NOT part of the cross-platform GPIO interface + */ +static inline struct gpio_controller *__iomem +__gpio_to_controller(unsigned gpio) +{ + void *__iomem ptr; + + if (gpio < 32) + ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10); + else if (gpio < 64) + ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38); + else if (gpio < DAVINCI_N_GPIO) + ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60); + else + ptr = NULL; + return ptr; +} + +static inline u32 __gpio_mask(unsigned gpio) +{ + return 1 << (gpio % 32); +} + +/* The get/set/clear functions will inline when called with constant + * parameters, for low-overhead bitbanging. Illegal constant parameters + * cause link-time errors. + * + * Otherwise, calls with variable parameters use outlined functions. + */ +extern int __error_inval_gpio(void); + +extern void __gpio_set(unsigned gpio, int value); +extern int __gpio_get(unsigned gpio); + +static inline void gpio_set_value(unsigned gpio, int value) +{ + if (__builtin_constant_p(value)) { + struct gpio_controller *__iomem g; + u32 mask; + + if (gpio >= DAVINCI_N_GPIO) + __error_inval_gpio(); + + g = __gpio_to_controller(gpio); + mask = __gpio_mask(gpio); + if (value) + __raw_writel(mask, &g->set_data); + else + __raw_writel(mask, &g->clr_data); + return; + } + + __gpio_set(gpio, value); +} + +/* Returns zero or nonzero; works for gpios configured as inputs OR + * as outputs. + * + * NOTE: changes in reported values are synchronized to the GPIO clock. + * This is most easily seen after calling gpio_set_value() and then immediatly + * gpio_get_value(), where the gpio_get_value() would return the old value + * until the GPIO clock ticks and the new value gets latched. + */ + +static inline int gpio_get_value(unsigned gpio) +{ + struct gpio_controller *__iomem g; + + if (!__builtin_constant_p(gpio)) + return __gpio_get(gpio); + + if (gpio >= DAVINCI_N_GPIO) + return __error_inval_gpio(); + + g = __gpio_to_controller(gpio); + return !!(__gpio_mask(gpio) & __raw_readl(&g->in_data)); +} + +/* powerup default direction is IN */ +extern int gpio_direction_input(unsigned gpio); +extern int gpio_direction_output(unsigned gpio, int value); + +#include <asm-generic/gpio.h> /* cansleep wrappers */ + +extern int gpio_request(unsigned gpio, const char *tag); +extern void gpio_free(unsigned gpio); + +static inline int gpio_to_irq(unsigned gpio) +{ + return DAVINCI_N_AINTC_IRQ + gpio; +} + +static inline int irq_to_gpio(unsigned irq) +{ + return irq - DAVINCI_N_AINTC_IRQ; +} + +#endif /* __DAVINCI_GPIO_H */ diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h index 60362d80229..a2e8969afac 100644 --- a/include/asm-arm/arch-davinci/hardware.h +++ b/include/asm-arm/arch-davinci/hardware.h @@ -11,4 +11,42 @@ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H +/* + * Base register addresses + */ +#define DAVINCI_DMA_3PCC_BASE (0x01C00000) +#define DAVINCI_DMA_3PTC0_BASE (0x01C10000) +#define DAVINCI_DMA_3PTC1_BASE (0x01C10400) +#define DAVINCI_I2C_BASE (0x01C21000) +#define DAVINCI_PWM0_BASE (0x01C22000) +#define DAVINCI_PWM1_BASE (0x01C22400) +#define DAVINCI_PWM2_BASE (0x01C22800) +#define DAVINCI_SYSTEM_MODULE_BASE (0x01C40000) +#define DAVINCI_PLL_CNTRL0_BASE (0x01C40800) +#define DAVINCI_PLL_CNTRL1_BASE (0x01C40C00) +#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01C41000) +#define DAVINCI_SYSTEM_DFT_BASE (0x01C42000) +#define DAVINCI_IEEE1394_BASE (0x01C60000) +#define DAVINCI_USB_OTG_BASE (0x01C64000) +#define DAVINCI_CFC_ATA_BASE (0x01C66000) +#define DAVINCI_SPI_BASE (0x01C66800) +#define DAVINCI_GPIO_BASE (0x01C67000) +#define DAVINCI_UHPI_BASE (0x01C67800) +#define DAVINCI_VPSS_REGS_BASE (0x01C70000) +#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01C80000) +#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01C81000) +#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01C82000) +#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01C84000) +#define DAVINCI_IMCOP_BASE (0x01CC0000) +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01E00000) +#define DAVINCI_VLYNQ_BASE (0x01E01000) +#define DAVINCI_MCBSP_BASE (0x01E02000) +#define DAVINCI_MMC_SD_BASE (0x01E10000) +#define DAVINCI_MS_BASE (0x01E20000) +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) +#define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000) + #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-davinci/mux.h b/include/asm-arm/arch-davinci/mux.h new file mode 100644 index 00000000000..c24b6782804 --- /dev/null +++ b/include/asm-arm/arch-davinci/mux.h @@ -0,0 +1,55 @@ +/* + * DaVinci pin multiplexing defines + * + * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_MUX_H +#define __ASM_ARCH_MUX_H + +#define DAVINCI_MUX_AEAW0 0 +#define DAVINCI_MUX_AEAW1 1 +#define DAVINCI_MUX_AEAW2 2 +#define DAVINCI_MUX_AEAW3 3 +#define DAVINCI_MUX_AEAW4 4 +#define DAVINCI_MUX_AECS4 10 +#define DAVINCI_MUX_AECS5 11 +#define DAVINCI_MUX_VLYNQWD0 12 +#define DAVINCI_MUX_VLYNQWD1 13 +#define DAVINCI_MUX_VLSCREN 14 +#define DAVINCI_MUX_VLYNQEN 15 +#define DAVINCI_MUX_HDIREN 16 +#define DAVINCI_MUX_ATAEN 17 +#define DAVINCI_MUX_RGB666 22 +#define DAVINCI_MUX_RGB888 23 +#define DAVINCI_MUX_LOEEN 24 +#define DAVINCI_MUX_LFLDEN 25 +#define DAVINCI_MUX_CWEN 26 +#define DAVINCI_MUX_CFLDEN 27 +#define DAVINCI_MUX_HPIEN 29 +#define DAVINCI_MUX_1394EN 30 +#define DAVINCI_MUX_EMACEN 31 + +#define DAVINCI_MUX_LEVEL2 32 +#define DAVINCI_MUX_UART0 (DAVINCI_MUX_LEVEL2 + 0) +#define DAVINCI_MUX_UART1 (DAVINCI_MUX_LEVEL2 + 1) +#define DAVINCI_MUX_UART2 (DAVINCI_MUX_LEVEL2 + 2) +#define DAVINCI_MUX_U2FLO (DAVINCI_MUX_LEVEL2 + 3) +#define DAVINCI_MUX_PWM0 (DAVINCI_MUX_LEVEL2 + 4) +#define DAVINCI_MUX_PWM1 (DAVINCI_MUX_LEVEL2 + 5) +#define DAVINCI_MUX_PWM2 (DAVINCI_MUX_LEVEL2 + 6) +#define DAVINCI_MUX_I2C (DAVINCI_MUX_LEVEL2 + 7) +#define DAVINCI_MUX_SPI (DAVINCI_MUX_LEVEL2 + 8) +#define DAVINCI_MUX_MSTK (DAVINCI_MUX_LEVEL2 + 9) +#define DAVINCI_MUX_ASP (DAVINCI_MUX_LEVEL2 + 10) +#define DAVINCI_MUX_CLK0 (DAVINCI_MUX_LEVEL2 + 16) +#define DAVINCI_MUX_CLK1 (DAVINCI_MUX_LEVEL2 + 17) +#define DAVINCI_MUX_TIMIN (DAVINCI_MUX_LEVEL2 + 18) + +extern void davinci_mux_peripheral(unsigned int mux, unsigned int enable); + +#endif /* __ASM_ARCH_MUX_H */ diff --git a/include/asm-arm/arch-imx/gpio.h b/include/asm-arm/arch-imx/gpio.h new file mode 100644 index 00000000000..486023263f3 --- /dev/null +++ b/include/asm-arm/arch-imx/gpio.h @@ -0,0 +1,102 @@ +#ifndef _IMX_GPIO_H + +#include <asm/arch/imx-regs.h> + +#define IMX_GPIO_ALLOC_MODE_NORMAL 0 +#define IMX_GPIO_ALLOC_MODE_NO_ALLOC 1 +#define IMX_GPIO_ALLOC_MODE_TRY_ALLOC 2 +#define IMX_GPIO_ALLOC_MODE_ALLOC_ONLY 4 +#define IMX_GPIO_ALLOC_MODE_RELEASE 8 + +extern int imx_gpio_request(unsigned gpio, const char *label); + +extern void imx_gpio_free(unsigned gpio); + +extern int imx_gpio_setup_multiple_pins(const int *pin_list, unsigned count, + int alloc_mode, const char *label); + +extern int imx_gpio_direction_input(unsigned gpio); + +extern int imx_gpio_direction_output(unsigned gpio, int value); + +extern void __imx_gpio_set_value(unsigned gpio, int value); + +static inline int imx_gpio_get_value(unsigned gpio) +{ + return SSR(gpio >> GPIO_PORT_SHIFT) & (1 << (gpio & GPIO_PIN_MASK)); +} + +static inline void imx_gpio_set_value_inline(unsigned gpio, int value) +{ + unsigned long flags; + + raw_local_irq_save(flags); + if(value) + DR(gpio >> GPIO_PORT_SHIFT) |= (1 << (gpio & GPIO_PIN_MASK)); + else + DR(gpio >> GPIO_PORT_SHIFT) &= ~(1 << (gpio & GPIO_PIN_MASK)); + raw_local_irq_restore(flags); +} + +static inline void imx_gpio_set_value(unsigned gpio, int value) +{ + if(__builtin_constant_p(gpio)) + imx_gpio_set_value_inline(gpio, value); + else + __imx_gpio_set_value(gpio, value); +} + +extern int imx_gpio_to_irq(unsigned gpio); + +extern int imx_irq_to_gpio(unsigned irq); + +/*-------------------------------------------------------------------------*/ + +/* Wrappers for "new style" GPIO calls. These calls i.MX specific versions + * to allow future extension of GPIO logic. + */ + +static inline int gpio_request(unsigned gpio, const char *label) +{ + return imx_gpio_request(gpio, label); +} + +static inline void gpio_free(unsigned gpio) +{ + imx_gpio_free(gpio); +} + +static inline int gpio_direction_input(unsigned gpio) +{ + return imx_gpio_direction_input(gpio); +} + +static inline int gpio_direction_output(unsigned gpio, int value) +{ + return imx_gpio_direction_output(gpio, value); +} + +static inline int gpio_get_value(unsigned gpio) +{ + return imx_gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + imx_gpio_set_value(gpio, value); +} + +#include <asm-generic/gpio.h> /* cansleep wrappers */ + +static inline int gpio_to_irq(unsigned gpio) +{ + return imx_gpio_to_irq(gpio); +} + +static inline int irq_to_gpio(unsigned irq) +{ + return imx_irq_to_gpio(irq); +} + + +#endif diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h index 30de404c61f..fb9de273387 100644 --- a/include/asm-arm/arch-imx/imx-regs.h +++ b/include/asm-arm/arch-imx/imx-regs.h @@ -77,6 +77,8 @@ #define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8) #define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8) +#define GPIO_PORT_MAX 3 + #define GPIO_PIN_MASK 0x1f #define GPIO_PORT_MASK (0x3 << 5) diff --git a/include/asm-arm/arch-iop13xx/adma.h b/include/asm-arm/arch-iop13xx/adma.h new file mode 100644 index 00000000000..04006c1c5fd --- /dev/null +++ b/include/asm-arm/arch-iop13xx/adma.h @@ -0,0 +1,544 @@ +/* + * Copyright(c) 2006, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + */ +#ifndef _ADMA_H +#define _ADMA_H +#include <linux/types.h> +#include <linux/io.h> +#include <asm/hardware.h> +#include <asm/hardware/iop_adma.h> + +#define ADMA_ACCR(chan) (chan->mmr_base + 0x0) +#define ADMA_ACSR(chan) (chan->mmr_base + 0x4) +#define ADMA_ADAR(chan) (chan->mmr_base + 0x8) +#define ADMA_IIPCR(chan) (chan->mmr_base + 0x18) +#define ADMA_IIPAR(chan) (chan->mmr_base + 0x1c) +#define ADMA_IIPUAR(chan) (chan->mmr_base + 0x20) +#define ADMA_ANDAR(chan) (chan->mmr_base + 0x24) +#define ADMA_ADCR(chan) (chan->mmr_base + 0x28) +#define ADMA_CARMD(chan) (chan->mmr_base + 0x2c) +#define ADMA_ABCR(chan) (chan->mmr_base + 0x30) +#define ADMA_DLADR(chan) (chan->mmr_base + 0x34) +#define ADMA_DUADR(chan) (chan->mmr_base + 0x38) +#define ADMA_SLAR(src, chan) (chan->mmr_base + (0x3c + (src << 3))) +#define ADMA_SUAR(src, chan) (chan->mmr_base + (0x40 + (src << 3))) + +struct iop13xx_adma_src { + u32 src_addr; + union { + u32 upper_src_addr; + struct { + unsigned int pq_upper_src_addr:24; + unsigned int pq_dmlt:8; + }; + }; +}; + +struct iop13xx_adma_desc_ctrl { + unsigned int int_en:1; + unsigned int xfer_dir:2; + unsigned int src_select:4; + unsigned int zero_result:1; + unsigned int block_fill_en:1; + unsigned int crc_gen_en:1; + unsigned int crc_xfer_dis:1; + unsigned int crc_seed_fetch_dis:1; + unsigned int status_write_back_en:1; + unsigned int endian_swap_en:1; + unsigned int reserved0:2; + unsigned int pq_update_xfer_en:1; + unsigned int dual_xor_en:1; + unsigned int pq_xfer_en:1; + unsigned int p_xfer_dis:1; + unsigned int reserved1:10; + unsigned int relax_order_en:1; + unsigned int no_snoop_en:1; +}; + +struct iop13xx_adma_byte_count { + unsigned int byte_count:24; + unsigned int host_if:3; + unsigned int reserved:2; + unsigned int zero_result_err_q:1; + unsigned int zero_result_err:1; + unsigned int tx_complete:1; +}; + +struct iop13xx_adma_desc_hw { + u32 next_desc; + union { + u32 desc_ctrl; + struct iop13xx_adma_desc_ctrl desc_ctrl_field; + }; + union { + u32 crc_addr; + u32 block_fill_data; + u32 q_dest_addr; + }; + union { + u32 byte_count; + struct iop13xx_adma_byte_count byte_count_field; + }; + union { + u32 dest_addr; + u32 p_dest_addr; + }; + union { + u32 upper_dest_addr; + u32 pq_upper_dest_addr; + }; + struct iop13xx_adma_src src[1]; +}; + +struct iop13xx_adma_desc_dual_xor { + u32 next_desc; + u32 desc_ctrl; + u32 reserved; + u32 byte_count; + u32 h_dest_addr; + u32 h_upper_dest_addr; + u32 src0_addr; + u32 upper_src0_addr; + u32 src1_addr; + u32 upper_src1_addr; + u32 h_src_addr; + u32 h_upper_src_addr; + u32 d_src_addr; + u32 d_upper_src_addr; + u32 d_dest_addr; + u32 d_upper_dest_addr; +}; + +struct iop13xx_adma_desc_pq_update { + u32 next_desc; + u32 desc_ctrl; + u32 reserved; + u32 byte_count; + u32 p_dest_addr; + u32 p_upper_dest_addr; + u32 src0_addr; + u32 upper_src0_addr; + u32 src1_addr; + u32 upper_src1_addr; + u32 p_src_addr; + u32 p_upper_src_addr; + u32 q_src_addr; + struct { + unsigned int q_upper_src_addr:24; + unsigned int q_dmlt:8; + }; + u32 q_dest_addr; + u32 q_upper_dest_addr; +}; + +static inline int iop_adma_get_max_xor(void) +{ + return 16; +} + +static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan) +{ + return __raw_readl(ADMA_ADAR(chan)); +} + +static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan, + u32 next_desc_addr) +{ + __raw_writel(next_desc_addr, ADMA_ANDAR(chan)); +} + +#define ADMA_STATUS_BUSY (1 << 13) + +static inline char iop_chan_is_busy(struct iop_adma_chan *chan) +{ + if (__raw_readl(ADMA_ACSR(chan)) & + ADMA_STATUS_BUSY) + return 1; + else + return 0; +} + +static inline int +iop_chan_get_desc_align(struct iop_adma_chan *chan, int num_slots) +{ + return 1; +} +#define iop_desc_is_aligned(x, y) 1 + +static inline int +iop_chan_memcpy_slot_count(size_t len, int *slots_per_op) +{ + *slots_per_op = 1; + return 1; +} + +#define iop_chan_interrupt_slot_count(s, c) iop_chan_memcpy_slot_count(0, s) + +static inline int +iop_chan_memset_slot_count(size_t len, int *slots_per_op) +{ + *slots_per_op = 1; + return 1; +} + +static inline int +iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op) +{ + int num_slots; + /* slots_to_find = 1 for basic descriptor + 1 per 4 sources above 1 + * (1 source => 8 bytes) (1 slot => 32 bytes) + */ + num_slots = 1 + (((src_cnt - 1) << 3) >> 5); + if (((src_cnt - 1) << 3) & 0x1f) + num_slots++; + + *slots_per_op = num_slots; + + return num_slots; +} + +#define ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024) +#define IOP_ADMA_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT +#define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT +#define IOP_ADMA_XOR_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT +#define iop_chan_zero_sum_slot_count(l, s, o) iop_chan_xor_slot_count(l, s, o) + +static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + return hw_desc->dest_addr; +} + +static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + return hw_desc->byte_count_field.byte_count; +} + +static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan, + int src_idx) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + return hw_desc->src[src_idx].src_addr; +} + +static inline u32 iop_desc_get_src_count(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + return hw_desc->desc_ctrl_field.src_select + 1; +} + +static inline void +iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, int int_en) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop13xx_adma_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ + u_desc_ctrl.field.int_en = int_en; + hw_desc->desc_ctrl = u_desc_ctrl.value; + hw_desc->crc_addr = 0; +} + +static inline void +iop_desc_init_memset(struct iop_adma_desc_slot *desc, int int_en) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop13xx_adma_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ + u_desc_ctrl.field.block_fill_en = 1; + u_desc_ctrl.field.int_en = int_en; + hw_desc->desc_ctrl = u_desc_ctrl.value; + hw_desc->crc_addr = 0; +} + +/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */ +static inline void +iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop13xx_adma_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + u_desc_ctrl.field.src_select = src_cnt - 1; + u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ + u_desc_ctrl.field.int_en = int_en; + hw_desc->desc_ctrl = u_desc_ctrl.value; + hw_desc->crc_addr = 0; + +} +#define iop_desc_init_null_xor(d, s, i) iop_desc_init_xor(d, s, i) + +/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */ +static inline int +iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop13xx_adma_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + u_desc_ctrl.field.src_select = src_cnt - 1; + u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ + u_desc_ctrl.field.zero_result = 1; + u_desc_ctrl.field.status_write_back_en = 1; + u_desc_ctrl.field.int_en = int_en; + hw_desc->desc_ctrl = u_desc_ctrl.value; + hw_desc->crc_addr = 0; + + return 1; +} + +static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan, + u32 byte_count) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + hw_desc->byte_count = byte_count; +} + +static inline void +iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len) +{ + int slots_per_op = desc->slots_per_op; + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter; + int i = 0; + + if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) { + hw_desc->byte_count = len; + } else { + do { + iter = iop_hw_desc_slot_idx(hw_desc, i); + iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; + len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; + i += slots_per_op; + } while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT); + + if (len) { + iter = iop_hw_desc_slot_idx(hw_desc, i); + iter->byte_count = len; + } + } +} + + +static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan, + dma_addr_t addr) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + hw_desc->dest_addr = addr; + hw_desc->upper_dest_addr = 0; +} + +static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc, + dma_addr_t addr) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + hw_desc->src[0].src_addr = addr; + hw_desc->src[0].upper_src_addr = 0; +} + +static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc, + int src_idx, dma_addr_t addr) +{ + int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter; + int i = 0; + + do { + iter = iop_hw_desc_slot_idx(hw_desc, i); + iter->src[src_idx].src_addr = addr; + iter->src[src_idx].upper_src_addr = 0; + slot_cnt -= slots_per_op; + if (slot_cnt) { + i += slots_per_op; + addr += IOP_ADMA_XOR_MAX_BYTE_COUNT; + } + } while (slot_cnt); +} + +static inline void +iop_desc_init_interrupt(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan) +{ + iop_desc_init_memcpy(desc, 1); + iop_desc_set_byte_count(desc, chan, 0); + iop_desc_set_dest_addr(desc, chan, 0); + iop_desc_set_memcpy_src_addr(desc, 0); +} + +#define iop_desc_set_zero_sum_src_addr iop_desc_set_xor_src_addr + +static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc, + u32 next_desc_addr) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + BUG_ON(hw_desc->next_desc); + hw_desc->next_desc = next_desc_addr; +} + +static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + return hw_desc->next_desc; +} + +static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + hw_desc->next_desc = 0; +} + +static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc, + u32 val) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + hw_desc->block_fill_data = val; +} + +static inline int iop_desc_get_zero_result(struct iop_adma_desc_slot *desc) +{ + struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; + struct iop13xx_adma_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field; + struct iop13xx_adma_byte_count byte_count = hw_desc->byte_count_field; + + BUG_ON(!(byte_count.tx_complete && desc_ctrl.zero_result)); + + if (desc_ctrl.pq_xfer_en) + return byte_count.zero_result_err_q; + else + return byte_count.zero_result_err; +} + +static inline void iop_chan_append(struct iop_adma_chan *chan) +{ + u32 adma_accr; + + adma_accr = __raw_readl(ADMA_ACCR(chan)); + adma_accr |= 0x2; + __raw_writel(adma_accr, ADMA_ACCR(chan)); +} + +static inline void iop_chan_idle(int busy, struct iop_adma_chan *chan) +{ + do { } while (0); +} + +static inline u32 iop_chan_get_status(struct iop_adma_chan *chan) +{ + return __raw_readl(ADMA_ACSR(chan)); +} + +static inline void iop_chan_disable(struct iop_adma_chan *chan) +{ + u32 adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan)); + adma_chan_ctrl &= ~0x1; + __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan)); +} + +static inline void iop_chan_enable(struct iop_adma_chan *chan) +{ + u32 adma_chan_ctrl; + + adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan)); + adma_chan_ctrl |= 0x1; + __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan)); +} + +static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan) +{ + u32 status = __raw_readl(ADMA_ACSR(chan)); + status &= (1 << 12); + __raw_writel(status, ADMA_ACSR(chan)); +} + +static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan) +{ + u32 status = __raw_readl(ADMA_ACSR(chan)); + status &= (1 << 11); + __raw_writel(status, ADMA_ACSR(chan)); +} + +static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan) +{ + u32 status = __raw_readl(ADMA_ACSR(chan)); + status &= (1 << 9) | (1 << 5) | (1 << 4) | (1 << 3); + __raw_writel(status, ADMA_ACSR(chan)); +} + +static inline int +iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan) +{ + return test_bit(9, &status); +} + +static inline int +iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan) +{ + return test_bit(5, &status); +} + +static inline int +iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan) +{ + return test_bit(4, &status); +} + +static inline int +iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan) +{ + return test_bit(3, &status); +} + +static inline int +iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan) +{ + return 0; +} + +static inline int +iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan) +{ + return 0; +} + +static inline int +iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan) +{ + return 0; +} + +#endif /* _ADMA_H */ diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h index e6736c3d1f7..d4e4f828577 100644 --- a/include/asm-arm/arch-iop13xx/iop13xx.h +++ b/include/asm-arm/arch-iop13xx/iop13xx.h @@ -166,12 +166,22 @@ static inline int iop13xx_cpu_id(void) #define IOP13XX_INIT_I2C_1 (1 << 1) #define IOP13XX_INIT_I2C_2 (1 << 2) -#define IQ81340_NUM_UART 2 -#define IQ81340_NUM_I2C 3 -#define IQ81340_NUM_PHYS_MAP_FLASH 1 -#define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART +\ - IQ81340_NUM_I2C +\ - IQ81340_NUM_PHYS_MAP_FLASH) +/* ADMA selection flags */ +/* INIT_ADMA_DEFAULT = Rely on CONFIG_IOP13XX_ADMA* */ +#define IOP13XX_INIT_ADMA_DEFAULT (0) +#define IOP13XX_INIT_ADMA_0 (1 << 0) +#define IOP13XX_INIT_ADMA_1 (1 << 1) +#define IOP13XX_INIT_ADMA_2 (1 << 2) + +/* Platform devices */ +#define IQ81340_NUM_UART 2 +#define IQ81340_NUM_I2C 3 +#define IQ81340_NUM_PHYS_MAP_FLASH 1 +#define IQ81340_NUM_ADMA 3 +#define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART + \ + IQ81340_NUM_I2C + \ + IQ81340_NUM_PHYS_MAP_FLASH + \ + IQ81340_NUM_ADMA) /*========================== PMMR offsets for key registers ============*/ #define IOP13XX_ATU0_PMMR_OFFSET 0x00048000 @@ -444,22 +454,6 @@ static inline int iop13xx_cpu_id(void) /*==============================ADMA UNITS===============================*/ #define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9)) #define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0) -#define IOP13XX_ADMA_OFFSET(chan, ofs) IOP13XX_REG_ADDR32((chan << 9) + (ofs)) - -#define IOP13XX_ADMA_ACCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x0) -#define IOP13XX_ADMA_ACSR(chan) IOP13XX_ADMA_OFFSET(chan, 0x4) -#define IOP13XX_ADMA_ADAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x8) -#define IOP13XX_ADMA_IIPCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x18) -#define IOP13XX_ADMA_IIPAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x1c) -#define IOP13XX_ADMA_IIPUAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x20) -#define IOP13XX_ADMA_ANDAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x24) -#define IOP13XX_ADMA_ADCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x28) -#define IOP13XX_ADMA_CARMD(chan) IOP13XX_ADMA_OFFSET(chan, 0x2c) -#define IOP13XX_ADMA_ABCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x30) -#define IOP13XX_ADMA_DLADR(chan) IOP13XX_ADMA_OFFSET(chan, 0x34) -#define IOP13XX_ADMA_DUADR(chan) IOP13XX_ADMA_OFFSET(chan, 0x38) -#define IOP13XX_ADMA_SLAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x3c + (src <<3)) -#define IOP13XX_ADMA_SUAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x40 + (src <<3)) /*==============================XSI BRIDGE===============================*/ #define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c) diff --git a/include/asm-arm/arch-iop32x/adma.h b/include/asm-arm/arch-iop32x/adma.h new file mode 100644 index 00000000000..5ed92037dd1 --- /dev/null +++ b/include/asm-arm/arch-iop32x/adma.h @@ -0,0 +1,5 @@ +#ifndef IOP32X_ADMA_H +#define IOP32X_ADMA_H +#include <asm/hardware/iop3xx-adma.h> +#endif + diff --git a/include/asm-arm/arch-iop33x/adma.h b/include/asm-arm/arch-iop33x/adma.h new file mode 100644 index 00000000000..4b92f795f90 --- /dev/null +++ b/include/asm-arm/arch-iop33x/adma.h @@ -0,0 +1,5 @@ +#ifndef IOP33X_ADMA_H +#define IOP33X_ADMA_H +#include <asm/hardware/iop3xx-adma.h> +#endif + diff --git a/include/asm-arm/arch-ixp4xx/ixdp425.h b/include/asm-arm/arch-ixp4xx/ixdp425.h index 3d3820d7ba0..e0791af3bfe 100644 --- a/include/asm-arm/arch-ixp4xx/ixdp425.h +++ b/include/asm-arm/arch-ixp4xx/ixdp425.h @@ -32,4 +32,8 @@ #define IXDP425_PCI_INTC_PIN 9 #define IXDP425_PCI_INTD_PIN 8 +/* NAND Flash pins */ +#define IXDP425_NAND_NCE_PIN 12 +#define IXDP425_NAND_CMD_BYTE 0x01 +#define IXDP425_NAND_ADDR_BYTE 0x02 diff --git a/include/asm-arm/arch-ixp4xx/udc.h b/include/asm-arm/arch-ixp4xx/udc.h index 79b850a3be4..dbdec36ff0d 100644 --- a/include/asm-arm/arch-ixp4xx/udc.h +++ b/include/asm-arm/arch-ixp4xx/udc.h @@ -6,25 +6,3 @@ extern void ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info); -static inline int udc_gpio_to_irq(unsigned gpio) -{ - return 0; -} - -static inline void udc_gpio_init_vbus(unsigned gpio) -{ -} - -static inline void udc_gpio_init_pullup(unsigned gpio) -{ -} - -static inline int udc_gpio_get(unsigned gpio) -{ - return 0; -} - -static inline void udc_gpio_set(unsigned gpio, int is_on) -{ -} - diff --git a/include/asm-arm/arch-ixp4xx/uncompress.h b/include/asm-arm/arch-ixp4xx/uncompress.h index 09ae6c91be6..f7a35b78823 100644 --- a/include/asm-arm/arch-ixp4xx/uncompress.h +++ b/include/asm-arm/arch-ixp4xx/uncompress.h @@ -38,9 +38,10 @@ static void flush(void) static __inline__ void __arch_decomp_setup(unsigned long arch_id) { /* - * Coyote and gtwx5715 only have UART2 connected + * Some boards are using UART2 as console */ - if (machine_is_adi_coyote() || machine_is_gtwx5715()) + if (machine_is_adi_coyote() || machine_is_gtwx5715() || + machine_is_gateway7001() || machine_is_wg302v2()) uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; else uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; diff --git a/include/asm-arm/arch-ks8695/gpio.h b/include/asm-arm/arch-ks8695/gpio.h new file mode 100644 index 00000000000..65ceea28607 --- /dev/null +++ b/include/asm-arm/arch-ks8695/gpio.h @@ -0,0 +1,79 @@ +/* + * include/asm-arm/arch-ks8695/gpio.h + * + * Copyright (C) 2006 Andrew Victor + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_GPIO_H_ +#define __ASM_ARCH_GPIO_H_ + +#define KS8695_GPIO_0 0 +#define KS8695_GPIO_1 1 +#define KS8695_GPIO_2 2 +#define KS8695_GPIO_3 3 +#define KS8695_GPIO_4 4 +#define KS8695_GPIO_5 5 +#define KS8695_GPIO_6 6 +#define KS8695_GPIO_7 7 +#define KS8695_GPIO_8 8 +#define KS8695_GPIO_9 9 +#define KS8695_GPIO_10 10 +#define KS8695_GPIO_11 11 +#define KS8695_GPIO_12 12 +#define KS8695_GPIO_13 13 +#define KS8695_GPIO_14 14 +#define KS8695_GPIO_15 15 + + +/* + * Configure GPIO pin as external interrupt source. + */ +int __init_or_module ks8695_gpio_interrupt(unsigned int pin, unsigned int type); + +/* + * Configure the GPIO line as an input. + */ +int __init_or_module gpio_direction_input(unsigned int pin); + +/* + * Configure the GPIO line as an output, with default state. + */ +int __init_or_module gpio_direction_output(unsigned int pin, unsigned int state); + +/* + * Set the state of an output GPIO line. + */ +void gpio_set_value(unsigned int pin, unsigned int state); + +/* + * Read the state of a GPIO line. + */ +int gpio_get_value(unsigned int pin); + +/* + * Map GPIO line to IRQ number. + */ +int gpio_to_irq(unsigned int pin); + +/* + * Map IRQ number to GPIO line. + */ +int irq_to_gpio(unsigned int irq); + + +#include <asm-generic/gpio.h> + +static inline int gpio_request(unsigned int pin, const char *label) +{ + return 0; +} + +static inline void gpio_free(unsigned int pin) +{ +} + +#endif diff --git a/include/asm-arm/arch-pxa/dma.h b/include/asm-arm/arch-pxa/dma.h index bed042d71d6..3280ee2ddfa 100644 --- a/include/asm-arm/arch-pxa/dma.h +++ b/include/asm-arm/arch-pxa/dma.h @@ -30,30 +30,12 @@ typedef enum { DMA_PRIO_LOW = 2 } pxa_dma_prio; -#if defined(CONFIG_PXA27x) - -#define PXA_DMA_CHANNELS 32 - -#define pxa_for_each_dma_prio(ch, prio) \ -for ( \ - ch = prio * 4; \ - ch != (4 << prio) + 16; \ - ch = (ch + 1 == (4 << prio)) ? (prio * 4 + 16) : (ch + 1) \ -) - -#elif defined(CONFIG_PXA25x) - -#define PXA_DMA_CHANNELS 16 - -#define pxa_for_each_dma_prio(ch, prio) \ - for (ch = prio * 4; ch != (4 << prio); ch++) - -#endif - /* * DMA registration */ +int __init pxa_init_dma(int num_ch); + int pxa_request_dma (char *name, pxa_dma_prio prio, void (*irq_handler)(int, void *), diff --git a/include/asm-arm/arch-pxa/entry-macro.S b/include/asm-arm/arch-pxa/entry-macro.S index 1d5fbb9b379..b7e73085146 100644 --- a/include/asm-arm/arch-pxa/entry-macro.S +++ b/include/asm-arm/arch-pxa/entry-macro.S @@ -20,20 +20,38 @@ .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp -#ifdef CONFIG_PXA27x - mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP - mrc p6, 0, \irqnr, c1, c0, 0 @ ICMR -#else + mrc p15, 0, \tmp, c0, c0, 0 @ CPUID + mov \tmp, \tmp, lsr #13 + and \tmp, \tmp, #0x7 @ Core G + cmp \tmp, #1 + bhi 1004f + mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000 add \base, \base, #0x00d00000 ldr \irqstat, [\base, #0] @ ICIP ldr \irqnr, [\base, #4] @ ICMR -#endif + b 1002f + +1004: + mrc p6, 0, \irqstat, c6, c0, 0 @ ICIP2 + mrc p6, 0, \irqnr, c7, c0, 0 @ ICMR2 + ands \irqstat, \irqstat, \irqnr + beq 1003f + rsb \irqstat, \irqnr, #0 + and \irqstat, \irqstat, \irqnr + clz \irqnr, \irqstat + rsb \irqnr, \irqnr, #31 + add \irqnr, \irqnr, #32 + b 1001f +1003: + mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP + mrc p6, 0, \irqnr, c1, c0, 0 @ ICMR +1002: ands \irqnr, \irqstat, \irqnr beq 1001f rsb \irqstat, \irqnr, #0 and \irqstat, \irqstat, \irqnr clz \irqnr, \irqstat - rsb \irqnr, \irqnr, #(31 - PXA_IRQ_SKIP) + rsb \irqnr, \irqnr, #31 1001: .endm diff --git a/include/asm-arm/arch-pxa/gpio.h b/include/asm-arm/arch-pxa/gpio.h index aeba24347f8..9e99241f3ed 100644 --- a/include/asm-arm/arch-pxa/gpio.h +++ b/include/asm-arm/arch-pxa/gpio.h @@ -45,7 +45,8 @@ static inline int gpio_direction_input(unsigned gpio) static inline int gpio_direction_output(unsigned gpio, int value) { - return pxa_gpio_mode(gpio | GPIO_OUT | (value ? 0 : GPIO_DFLT_LOW)); + return pxa_gpio_mode(gpio | GPIO_OUT | + (value ? GPIO_DFLT_HIGH : GPIO_DFLT_LOW)); } static inline int __gpio_get_value(unsigned gpio) diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h index e2bdc2fbede..38612174641 100644 --- a/include/asm-arm/arch-pxa/hardware.h +++ b/include/asm-arm/arch-pxa/hardware.h @@ -62,6 +62,42 @@ #ifndef __ASSEMBLY__ +#define __cpu_is_pxa21x(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xf3f; \ + _id == 0x212; \ + }) + +#define __cpu_is_pxa25x(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x2d0 || _id == 0x290; \ + }) + +#define __cpu_is_pxa27x(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x411; \ + }) + +#define cpu_is_pxa21x() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa21x(id); \ + }) + +#define cpu_is_pxa25x() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa25x(id); \ + }) + +#define cpu_is_pxa27x() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa27x(id); \ + }) + /* * Handy routine to set GPIO alternate functions */ diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h index 67ed43674c6..a07fe0f928c 100644 --- a/include/asm-arm/arch-pxa/irqs.h +++ b/include/asm-arm/arch-pxa/irqs.h @@ -11,14 +11,9 @@ */ -#ifdef CONFIG_PXA27x -#define PXA_IRQ_SKIP 0 -#else -#define PXA_IRQ_SKIP 7 -#endif - -#define PXA_IRQ(x) ((x) - PXA_IRQ_SKIP) +#define PXA_IRQ(x) (x) +#ifdef CONFIG_PXA27x #define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */ #define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */ #define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI) */ @@ -26,6 +21,8 @@ #define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */ #define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt */ #define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */ +#endif + #define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */ #define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */ #define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */ @@ -58,18 +55,15 @@ #ifdef CONFIG_PXA27x #define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */ #define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */ - -#define PXA_INTERNAL_IRQS 34 -#else -#define PXA_INTERNAL_IRQS 32 #endif -#define GPIO_2_x_TO_IRQ(x) \ - PXA_IRQ((x) - 2 + PXA_INTERNAL_IRQS) +#define PXA_GPIO_IRQ_BASE (64) +#define PXA_GPIO_IRQ_NUM (128) + +#define GPIO_2_x_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x)) #define IRQ_GPIO(x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x)) -#define IRQ_TO_GPIO_2_x(i) \ - ((i) - IRQ_GPIO(2) + 2) +#define IRQ_TO_GPIO_2_x(i) ((i) - PXA_GPIO_IRQ_BASE) #define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i)) #if defined(CONFIG_PXA25x) @@ -84,7 +78,7 @@ * these. If you need more, increase IRQ_BOARD_END, but keep it * within sensible limits. */ -#define IRQ_BOARD_START (IRQ_GPIO(PXA_LAST_GPIO) + 1) +#define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM) #define IRQ_BOARD_END (IRQ_BOARD_START + 16) #define IRQ_SA1111_START (IRQ_BOARD_END) diff --git a/include/asm-arm/arch-pxa/pm.h b/include/asm-arm/arch-pxa/pm.h index 7a8a1cdf430..52243a62c4e 100644 --- a/include/asm-arm/arch-pxa/pm.h +++ b/include/asm-arm/arch-pxa/pm.h @@ -9,4 +9,3 @@ extern int pxa_pm_prepare(suspend_state_t state); extern int pxa_pm_enter(suspend_state_t state); -extern int pxa_pm_finish(suspend_state_t state); diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index dbcc9298b0c..e68b593d69d 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -1765,29 +1765,9 @@ #define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL)) /* - * MultiMediaCard (MMC) controller + * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h */ -#define MMC_STRPCL __REG(0x41100000) /* Control to start and stop MMC clock */ -#define MMC_STAT __REG(0x41100004) /* MMC Status Register (read only) */ -#define MMC_CLKRT __REG(0x41100008) /* MMC clock rate */ -#define MMC_SPI __REG(0x4110000c) /* SPI mode control bits */ -#define MMC_CMDAT __REG(0x41100010) /* Command/response/data sequence control */ -#define MMC_RESTO __REG(0x41100014) /* Expected response time out */ -#define MMC_RDTO __REG(0x41100018) /* Expected data read time out */ -#define MMC_BLKLEN __REG(0x4110001c) /* Block length of data transaction */ -#define MMC_NOB __REG(0x41100020) /* Number of blocks, for block mode */ -#define MMC_PRTBUF __REG(0x41100024) /* Partial MMC_TXFIFO FIFO written */ -#define MMC_I_MASK __REG(0x41100028) /* Interrupt Mask */ -#define MMC_I_REG __REG(0x4110002c) /* Interrupt Register (read only) */ -#define MMC_CMD __REG(0x41100030) /* Index of current command */ -#define MMC_ARGH __REG(0x41100034) /* MSW part of the current command argument */ -#define MMC_ARGL __REG(0x41100038) /* LSW part of the current command argument */ -#define MMC_RES __REG(0x4110003c) /* Response FIFO (read only) */ -#define MMC_RXFIFO __REG(0x41100040) /* Receive FIFO (read only) */ -#define MMC_TXFIFO __REG(0x41100044) /* Transmit FIFO (write only) */ - - /* * Core Clock */ diff --git a/include/asm-arm/arch-pxa/udc.h b/include/asm-arm/arch-pxa/udc.h index 8bc6f9c3e3e..27aa3a91012 100644 --- a/include/asm-arm/arch-pxa/udc.h +++ b/include/asm-arm/arch-pxa/udc.h @@ -1,41 +1,8 @@ /* * linux/include/asm-arm/arch-pxa/udc.h * - * This supports machine-specific differences in how the PXA2xx - * USB Device Controller (UDC) is wired. - * */ #include <asm/mach/udc_pxa2xx.h> extern void pxa_set_udc_info(struct pxa2xx_udc_mach_info *info); -static inline int udc_gpio_to_irq(unsigned gpio) -{ - return IRQ_GPIO(gpio & GPIO_MD_MASK_NR); -} - -static inline void udc_gpio_init_vbus(unsigned gpio) -{ - pxa_gpio_mode((gpio & GPIO_MD_MASK_NR) | GPIO_IN); -} - -static inline void udc_gpio_init_pullup(unsigned gpio) -{ - pxa_gpio_mode((gpio & GPIO_MD_MASK_NR) | GPIO_OUT | GPIO_DFLT_LOW); -} - -static inline int udc_gpio_get(unsigned gpio) -{ - return (GPLR(gpio) & GPIO_bit(gpio)) != 0; -} - -static inline void udc_gpio_set(unsigned gpio, int is_on) -{ - int mask = GPIO_bit(gpio); - - if (is_on) - GPSR(gpio) = mask; - else - GPCR(gpio) = mask; -} - diff --git a/include/asm-arm/arch-s3c2410/anubis-cpld.h b/include/asm-arm/arch-s3c2410/anubis-cpld.h index dcebf6d6190..168b93fee52 100644 --- a/include/asm-arm/arch-s3c2410/anubis-cpld.h +++ b/include/asm-arm/arch-s3c2410/anubis-cpld.h @@ -18,4 +18,8 @@ #define ANUBIS_CTRL1_NANDSEL (0x3) +/* IDREG - revision */ + +#define ANUBIS_IDREG_REVMASK (0x7) + #endif /* __ASM_ARCH_ANUBISCPLD_H */ diff --git a/include/asm-arm/arch-s3c2410/anubis-map.h b/include/asm-arm/arch-s3c2410/anubis-map.h index ab076de4a0d..830d114261d 100644 --- a/include/asm-arm/arch-s3c2410/anubis-map.h +++ b/include/asm-arm/arch-s3c2410/anubis-map.h @@ -27,14 +27,8 @@ #define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000) /* 0x01800000 */ #define ANUBIS_PA_CTRL1 (ANUBIS_PA_CPLD) -#define ANUBIS_VA_CTRL2 ANUBIS_IOADDR(0x00100000) /* 0x01900000 */ -#define ANUBIS_PA_CTRL2 (ANUBIS_PA_CPLD) - -#define ANUBIS_VA_CTRL3 ANUBIS_IOADDR(0x00200000) /* 0x01A00000 */ -#define ANUBIS_PA_CTRL3 (ANUBIS_PA_CPLD) - -#define ANUBIS_VA_CTRL4 ANUBIS_IOADDR(0x00300000) /* 0x01B00000 */ -#define ANUBIS_PA_CTRL4 (ANUBIS_PA_CPLD) +#define ANUBIS_VA_IDREG ANUBIS_IOADDR(0x00300000) /* 0x01B00000 */ +#define ANUBIS_PA_IDREG (ANUBIS_PA_CPLD + (3<<23)) #define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000) #define ANUBIS_IDEPRIAUX ANUBIS_IOADDR(0x01100000) diff --git a/include/asm-arm/arch-s3c2410/osiris-cpld.h b/include/asm-arm/arch-s3c2410/osiris-cpld.h index 3b6498468d6..229ab2351db 100644 --- a/include/asm-arm/arch-s3c2410/osiris-cpld.h +++ b/include/asm-arm/arch-s3c2410/osiris-cpld.h @@ -1,6 +1,6 @@ /* linux/include/asm-arm/arch-s3c2410/osiris-cpld.h * - * Copyright (c) 2005 Simtec Electronics + * Copyright 2005 Simtec Electronics * http://www.simtec.co.uk/products/ * Ben Dooks <ben@simtec.co.uk> * @@ -14,12 +14,17 @@ #ifndef __ASM_ARCH_OSIRISCPLD_H #define __ASM_ARCH_OSIRISCPLD_H -/* CTRL1 - NAND WP control */ +/* CTRL0 - NAND WP control */ -#define OSIRIS_CTRL1_NANDSEL (0x3) -#define OSIRIS_CTRL1_BOOT_INT (1<<3) -#define OSIRIS_CTRL1_PCMCIA (1<<4) -#define OSIRIS_CTRL1_PCMCIA_nWAIT (1<<6) -#define OSIRIS_CTRL1_PCMCIA_nIOIS16 (1<<7) +#define OSIRIS_CTRL0_NANDSEL (0x3) +#define OSIRIS_CTRL0_BOOT_INT (1<<3) +#define OSIRIS_CTRL0_PCMCIA (1<<4) +#define OSIRIS_CTRL0_FIX8 (1<<5) +#define OSIRIS_CTRL0_PCMCIA_nWAIT (1<<6) +#define OSIRIS_CTRL0_PCMCIA_nIOIS16 (1<<7) + +#define OSIRIS_CTRL1_FIX8 (1<<0) + +#define OSIRIS_ID_REVMASK (0x7) #endif /* __ASM_ARCH_OSIRISCPLD_H */ diff --git a/include/asm-arm/arch-s3c2410/osiris-map.h b/include/asm-arm/arch-s3c2410/osiris-map.h index a14164dfa52..b5c74d2b9aa 100644 --- a/include/asm-arm/arch-s3c2410/osiris-map.h +++ b/include/asm-arm/arch-s3c2410/osiris-map.h @@ -24,16 +24,19 @@ /* we put the CPLD registers next, to get them out of the way */ -#define OSIRIS_VA_CTRL1 OSIRIS_IOADDR(0x00000000) -#define OSIRIS_PA_CTRL1 (OSIRIS_PA_CPLD) +#define OSIRIS_VA_CTRL0 OSIRIS_IOADDR(0x00000000) +#define OSIRIS_PA_CTRL0 (OSIRIS_PA_CPLD) -#define OSIRIS_VA_CTRL2 OSIRIS_IOADDR(0x00100000) -#define OSIRIS_PA_CTRL2 (OSIRIS_PA_CPLD + (1<<23)) +#define OSIRIS_VA_CTRL1 OSIRIS_IOADDR(0x00100000) +#define OSIRIS_PA_CTRL1 (OSIRIS_PA_CPLD + (1<<23)) -#define OSIRIS_VA_CTRL3 OSIRIS_IOADDR(0x00200000) -#define OSIRIS_PA_CTRL3 (OSIRIS_PA_CPLD + (2<<23)) +#define OSIRIS_VA_CTRL2 OSIRIS_IOADDR(0x00200000) +#define OSIRIS_PA_CTRL2 (OSIRIS_PA_CPLD + (2<<23)) -#define OSIRIS_VA_CTRL4 OSIRIS_IOADDR(0x00300000) -#define OSIRIS_PA_CTRL4 (OSIRIS_PA_CPLD + (3<<23)) +#define OSIRIS_VA_CTRL3 OSIRIS_IOADDR(0x00300000) +#define OSIRIS_PA_CTRL3 (OSIRIS_PA_CPLD + (2<<23)) + +#define OSIRIS_VA_IDREG OSIRIS_IOADDR(0x00700000) +#define OSIRIS_PA_IDREG (OSIRIS_PA_CPLD + (7<<23)) #endif /* __ASM_ARCH_OSIRISMAP_H */ diff --git a/include/asm-arm/elf.h b/include/asm-arm/elf.h index 3679a8a8922..d7a777f0508 100644 --- a/include/asm-arm/elf.h +++ b/include/asm-arm/elf.h @@ -7,6 +7,7 @@ */ #include <asm/ptrace.h> #include <asm/user.h> +#include <asm/hwcap.h> typedef unsigned long elf_greg_t; typedef unsigned long elf_freg_t[3]; @@ -39,31 +40,9 @@ typedef struct user_fp elf_fpregset_t; #endif #define ELF_ARCH EM_ARM -/* - * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP - */ -#define HWCAP_SWP 1 -#define HWCAP_HALF 2 -#define HWCAP_THUMB 4 -#define HWCAP_26BIT 8 /* Play it safe */ -#define HWCAP_FAST_MULT 16 -#define HWCAP_FPA 32 -#define HWCAP_VFP 64 -#define HWCAP_EDSP 128 -#define HWCAP_JAVA 256 -#define HWCAP_IWMMXT 512 -#define HWCAP_CRUNCH 1024 - #ifdef __KERNEL__ #ifndef __ASSEMBLY__ /* - * This yields a mask that user programs can use to figure out what - * instruction set this cpu supports. - */ -#define ELF_HWCAP (elf_hwcap) -extern unsigned int elf_hwcap; - -/* * This yields a string that ld.so will use to load implementation * specific libraries for optimization. This is more specific in * intent than poking at uname or /proc/cpuinfo. diff --git a/include/asm-arm/hardware/iop3xx-adma.h b/include/asm-arm/hardware/iop3xx-adma.h new file mode 100644 index 00000000000..10834b54f68 --- /dev/null +++ b/include/asm-arm/hardware/iop3xx-adma.h @@ -0,0 +1,892 @@ +/* + * Copyright © 2006, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + */ +#ifndef _ADMA_H +#define _ADMA_H +#include <linux/types.h> +#include <linux/io.h> +#include <asm/hardware.h> +#include <asm/hardware/iop_adma.h> + +/* Memory copy units */ +#define DMA_CCR(chan) (chan->mmr_base + 0x0) +#define DMA_CSR(chan) (chan->mmr_base + 0x4) +#define DMA_DAR(chan) (chan->mmr_base + 0xc) +#define DMA_NDAR(chan) (chan->mmr_base + 0x10) +#define DMA_PADR(chan) (chan->mmr_base + 0x14) +#define DMA_PUADR(chan) (chan->mmr_base + 0x18) +#define DMA_LADR(chan) (chan->mmr_base + 0x1c) +#define DMA_BCR(chan) (chan->mmr_base + 0x20) +#define DMA_DCR(chan) (chan->mmr_base + 0x24) + +/* Application accelerator unit */ +#define AAU_ACR(chan) (chan->mmr_base + 0x0) +#define AAU_ASR(chan) (chan->mmr_base + 0x4) +#define AAU_ADAR(chan) (chan->mmr_base + 0x8) +#define AAU_ANDAR(chan) (chan->mmr_base + 0xc) +#define AAU_SAR(src, chan) (chan->mmr_base + (0x10 + ((src) << 2))) +#define AAU_DAR(chan) (chan->mmr_base + 0x20) +#define AAU_ABCR(chan) (chan->mmr_base + 0x24) +#define AAU_ADCR(chan) (chan->mmr_base + 0x28) +#define AAU_SAR_EDCR(src_edc) (chan->mmr_base + (0x02c + ((src_edc-4) << 2))) +#define AAU_EDCR0_IDX 8 +#define AAU_EDCR1_IDX 17 +#define AAU_EDCR2_IDX 26 + +#define DMA0_ID 0 +#define DMA1_ID 1 +#define AAU_ID 2 + +struct iop3xx_aau_desc_ctrl { + unsigned int int_en:1; + unsigned int blk1_cmd_ctrl:3; + unsigned int blk2_cmd_ctrl:3; + unsigned int blk3_cmd_ctrl:3; + unsigned int blk4_cmd_ctrl:3; + unsigned int blk5_cmd_ctrl:3; + unsigned int blk6_cmd_ctrl:3; + unsigned int blk7_cmd_ctrl:3; + unsigned int blk8_cmd_ctrl:3; + unsigned int blk_ctrl:2; + unsigned int dual_xor_en:1; + unsigned int tx_complete:1; + unsigned int zero_result_err:1; + unsigned int zero_result_en:1; + unsigned int dest_write_en:1; +}; + +struct iop3xx_aau_e_desc_ctrl { + unsigned int reserved:1; + unsigned int blk1_cmd_ctrl:3; + unsigned int blk2_cmd_ctrl:3; + unsigned int blk3_cmd_ctrl:3; + unsigned int blk4_cmd_ctrl:3; + unsigned int blk5_cmd_ctrl:3; + unsigned int blk6_cmd_ctrl:3; + unsigned int blk7_cmd_ctrl:3; + unsigned int blk8_cmd_ctrl:3; + unsigned int reserved2:7; +}; + +struct iop3xx_dma_desc_ctrl { + unsigned int pci_transaction:4; + unsigned int int_en:1; + unsigned int dac_cycle_en:1; + unsigned int mem_to_mem_en:1; + unsigned int crc_data_tx_en:1; + unsigned int crc_gen_en:1; + unsigned int crc_seed_dis:1; + unsigned int reserved:21; + unsigned int crc_tx_complete:1; +}; + +struct iop3xx_desc_dma { + u32 next_desc; + union { + u32 pci_src_addr; + u32 pci_dest_addr; + u32 src_addr; + }; + union { + u32 upper_pci_src_addr; + u32 upper_pci_dest_addr; + }; + union { + u32 local_pci_src_addr; + u32 local_pci_dest_addr; + u32 dest_addr; + }; + u32 byte_count; + union { + u32 desc_ctrl; + struct iop3xx_dma_desc_ctrl desc_ctrl_field; + }; + u32 crc_addr; +}; + +struct iop3xx_desc_aau { + u32 next_desc; + u32 src[4]; + u32 dest_addr; + u32 byte_count; + union { + u32 desc_ctrl; + struct iop3xx_aau_desc_ctrl desc_ctrl_field; + }; + union { + u32 src_addr; + u32 e_desc_ctrl; + struct iop3xx_aau_e_desc_ctrl e_desc_ctrl_field; + } src_edc[31]; +}; + +struct iop3xx_aau_gfmr { + unsigned int gfmr1:8; + unsigned int gfmr2:8; + unsigned int gfmr3:8; + unsigned int gfmr4:8; +}; + +struct iop3xx_desc_pq_xor { + u32 next_desc; + u32 src[3]; + union { + u32 data_mult1; + struct iop3xx_aau_gfmr data_mult1_field; + }; + u32 dest_addr; + u32 byte_count; + union { + u32 desc_ctrl; + struct iop3xx_aau_desc_ctrl desc_ctrl_field; + }; + union { + u32 src_addr; + u32 e_desc_ctrl; + struct iop3xx_aau_e_desc_ctrl e_desc_ctrl_field; + u32 data_multiplier; + struct iop3xx_aau_gfmr data_mult_field; + u32 reserved; + } src_edc_gfmr[19]; +}; + +struct iop3xx_desc_dual_xor { + u32 next_desc; + u32 src0_addr; + u32 src1_addr; + u32 h_src_addr; + u32 d_src_addr; + u32 h_dest_addr; + u32 byte_count; + union { + u32 desc_ctrl; + struct iop3xx_aau_desc_ctrl desc_ctrl_field; + }; + u32 d_dest_addr; +}; + +union iop3xx_desc { + struct iop3xx_desc_aau *aau; + struct iop3xx_desc_dma *dma; + struct iop3xx_desc_pq_xor *pq_xor; + struct iop3xx_desc_dual_xor *dual_xor; + void *ptr; +}; + +static inline int iop_adma_get_max_xor(void) +{ + return 32; +} + +static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan) +{ + int id = chan->device->id; + + switch (id) { + case DMA0_ID: + case DMA1_ID: + return __raw_readl(DMA_DAR(chan)); + case AAU_ID: + return __raw_readl(AAU_ADAR(chan)); + default: + BUG(); + } + return 0; +} + +static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan, + u32 next_desc_addr) +{ + int id = chan->device->id; + + switch (id) { + case DMA0_ID: + case DMA1_ID: + __raw_writel(next_desc_addr, DMA_NDAR(chan)); + break; + case AAU_ID: + __raw_writel(next_desc_addr, AAU_ANDAR(chan)); + break; + } + +} + +#define IOP_ADMA_STATUS_BUSY (1 << 10) +#define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT (1024) +#define IOP_ADMA_XOR_MAX_BYTE_COUNT (16 * 1024 * 1024) +#define IOP_ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024) + +static inline int iop_chan_is_busy(struct iop_adma_chan *chan) +{ + u32 status = __raw_readl(DMA_CSR(chan)); + return (status & IOP_ADMA_STATUS_BUSY) ? 1 : 0; +} + +static inline int iop_desc_is_aligned(struct iop_adma_desc_slot *desc, + int num_slots) +{ + /* num_slots will only ever be 1, 2, 4, or 8 */ + return (desc->idx & (num_slots - 1)) ? 0 : 1; +} + +/* to do: support large (i.e. > hw max) buffer sizes */ +static inline int iop_chan_memcpy_slot_count(size_t len, int *slots_per_op) +{ + *slots_per_op = 1; + return 1; +} + +/* to do: support large (i.e. > hw max) buffer sizes */ +static inline int iop_chan_memset_slot_count(size_t len, int *slots_per_op) +{ + *slots_per_op = 1; + return 1; +} + +static inline int iop3xx_aau_xor_slot_count(size_t len, int src_cnt, + int *slots_per_op) +{ + const static int slot_count_table[] = { 0, + 1, 1, 1, 1, /* 01 - 04 */ + 2, 2, 2, 2, /* 05 - 08 */ + 4, 4, 4, 4, /* 09 - 12 */ + 4, 4, 4, 4, /* 13 - 16 */ + 8, 8, 8, 8, /* 17 - 20 */ + 8, 8, 8, 8, /* 21 - 24 */ + 8, 8, 8, 8, /* 25 - 28 */ + 8, 8, 8, 8, /* 29 - 32 */ + }; + *slots_per_op = slot_count_table[src_cnt]; + return *slots_per_op; +} + +static inline int +iop_chan_interrupt_slot_count(int *slots_per_op, struct iop_adma_chan *chan) +{ + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + return iop_chan_memcpy_slot_count(0, slots_per_op); + case AAU_ID: + return iop3xx_aau_xor_slot_count(0, 2, slots_per_op); + default: + BUG(); + } + return 0; +} + +static inline int iop_chan_xor_slot_count(size_t len, int src_cnt, + int *slots_per_op) +{ + int slot_cnt = iop3xx_aau_xor_slot_count(len, src_cnt, slots_per_op); + + if (len <= IOP_ADMA_XOR_MAX_BYTE_COUNT) + return slot_cnt; + + len -= IOP_ADMA_XOR_MAX_BYTE_COUNT; + while (len > IOP_ADMA_XOR_MAX_BYTE_COUNT) { + len -= IOP_ADMA_XOR_MAX_BYTE_COUNT; + slot_cnt += *slots_per_op; + } + + if (len) + slot_cnt += *slots_per_op; + + return slot_cnt; +} + +/* zero sum on iop3xx is limited to 1k at a time so it requires multiple + * descriptors + */ +static inline int iop_chan_zero_sum_slot_count(size_t len, int src_cnt, + int *slots_per_op) +{ + int slot_cnt = iop3xx_aau_xor_slot_count(len, src_cnt, slots_per_op); + + if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) + return slot_cnt; + + len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; + while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) { + len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; + slot_cnt += *slots_per_op; + } + + if (len) + slot_cnt += *slots_per_op; + + return slot_cnt; +} + +static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan) +{ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + return hw_desc.dma->dest_addr; + case AAU_ID: + return hw_desc.aau->dest_addr; + default: + BUG(); + } + return 0; +} + +static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan) +{ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + return hw_desc.dma->byte_count; + case AAU_ID: + return hw_desc.aau->byte_count; + default: + BUG(); + } + return 0; +} + +/* translate the src_idx to a descriptor word index */ +static inline int __desc_idx(int src_idx) +{ + const static int desc_idx_table[] = { 0, 0, 0, 0, + 0, 1, 2, 3, + 5, 6, 7, 8, + 9, 10, 11, 12, + 14, 15, 16, 17, + 18, 19, 20, 21, + 23, 24, 25, 26, + 27, 28, 29, 30, + }; + + return desc_idx_table[src_idx]; +} + +static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan, + int src_idx) +{ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + return hw_desc.dma->src_addr; + case AAU_ID: + break; + default: + BUG(); + } + + if (src_idx < 4) + return hw_desc.aau->src[src_idx]; + else + return hw_desc.aau->src_edc[__desc_idx(src_idx)].src_addr; +} + +static inline void iop3xx_aau_desc_set_src_addr(struct iop3xx_desc_aau *hw_desc, + int src_idx, dma_addr_t addr) +{ + if (src_idx < 4) + hw_desc->src[src_idx] = addr; + else + hw_desc->src_edc[__desc_idx(src_idx)].src_addr = addr; +} + +static inline void +iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, int int_en) +{ + struct iop3xx_desc_dma *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop3xx_dma_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + u_desc_ctrl.field.mem_to_mem_en = 1; + u_desc_ctrl.field.pci_transaction = 0xe; /* memory read block */ + u_desc_ctrl.field.int_en = int_en; + hw_desc->desc_ctrl = u_desc_ctrl.value; + hw_desc->upper_pci_src_addr = 0; + hw_desc->crc_addr = 0; +} + +static inline void +iop_desc_init_memset(struct iop_adma_desc_slot *desc, int int_en) +{ + struct iop3xx_desc_aau *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop3xx_aau_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + u_desc_ctrl.field.blk1_cmd_ctrl = 0x2; /* memory block fill */ + u_desc_ctrl.field.dest_write_en = 1; + u_desc_ctrl.field.int_en = int_en; + hw_desc->desc_ctrl = u_desc_ctrl.value; +} + +static inline u32 +iop3xx_desc_init_xor(struct iop3xx_desc_aau *hw_desc, int src_cnt, int int_en) +{ + int i, shift; + u32 edcr; + union { + u32 value; + struct iop3xx_aau_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + switch (src_cnt) { + case 25 ... 32: + u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */ + edcr = 0; + shift = 1; + for (i = 24; i < src_cnt; i++) { + edcr |= (1 << shift); + shift += 3; + } + hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = edcr; + src_cnt = 24; + /* fall through */ + case 17 ... 24: + if (!u_desc_ctrl.field.blk_ctrl) { + hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0; + u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */ + } + edcr = 0; + shift = 1; + for (i = 16; i < src_cnt; i++) { + edcr |= (1 << shift); + shift += 3; + } + hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = edcr; + src_cnt = 16; + /* fall through */ + case 9 ... 16: + if (!u_desc_ctrl.field.blk_ctrl) + u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */ + edcr = 0; + shift = 1; + for (i = 8; i < src_cnt; i++) { + edcr |= (1 << shift); + shift += 3; + } + hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = edcr; + src_cnt = 8; + /* fall through */ + case 2 ... 8: + shift = 1; + for (i = 0; i < src_cnt; i++) { + u_desc_ctrl.value |= (1 << shift); + shift += 3; + } + + if (!u_desc_ctrl.field.blk_ctrl && src_cnt > 4) + u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */ + } + + u_desc_ctrl.field.dest_write_en = 1; + u_desc_ctrl.field.blk1_cmd_ctrl = 0x7; /* direct fill */ + u_desc_ctrl.field.int_en = int_en; + hw_desc->desc_ctrl = u_desc_ctrl.value; + + return u_desc_ctrl.value; +} + +static inline void +iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) +{ + iop3xx_desc_init_xor(desc->hw_desc, src_cnt, int_en); +} + +/* return the number of operations */ +static inline int +iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) +{ + int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; + struct iop3xx_desc_aau *hw_desc, *prev_hw_desc, *iter; + union { + u32 value; + struct iop3xx_aau_desc_ctrl field; + } u_desc_ctrl; + int i, j; + + hw_desc = desc->hw_desc; + + for (i = 0, j = 0; (slot_cnt -= slots_per_op) >= 0; + i += slots_per_op, j++) { + iter = iop_hw_desc_slot_idx(hw_desc, i); + u_desc_ctrl.value = iop3xx_desc_init_xor(iter, src_cnt, int_en); + u_desc_ctrl.field.dest_write_en = 0; + u_desc_ctrl.field.zero_result_en = 1; + u_desc_ctrl.field.int_en = int_en; + iter->desc_ctrl = u_desc_ctrl.value; + + /* for the subsequent descriptors preserve the store queue + * and chain them together + */ + if (i) { + prev_hw_desc = + iop_hw_desc_slot_idx(hw_desc, i - slots_per_op); + prev_hw_desc->next_desc = + (u32) (desc->async_tx.phys + (i << 5)); + } + } + + return j; +} + +static inline void +iop_desc_init_null_xor(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) +{ + struct iop3xx_desc_aau *hw_desc = desc->hw_desc; + union { + u32 value; + struct iop3xx_aau_desc_ctrl field; + } u_desc_ctrl; + + u_desc_ctrl.value = 0; + switch (src_cnt) { + case 25 ... 32: + u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */ + hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0; + /* fall through */ + case 17 ... 24: + if (!u_desc_ctrl.field.blk_ctrl) { + hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0; + u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */ + } + hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = 0; + /* fall through */ + case 9 ... 16: + if (!u_desc_ctrl.field.blk_ctrl) + u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */ + hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = 0; + /* fall through */ + case 1 ... 8: + if (!u_desc_ctrl.field.blk_ctrl && src_cnt > 4) + u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */ + } + + u_desc_ctrl.field.dest_write_en = 0; + u_desc_ctrl.field.int_en = int_en; + hw_desc->desc_ctrl = u_desc_ctrl.value; +} + +static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan, + u32 byte_count) +{ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + hw_desc.dma->byte_count = byte_count; + break; + case AAU_ID: + hw_desc.aau->byte_count = byte_count; + break; + default: + BUG(); + } +} + +static inline void +iop_desc_init_interrupt(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan) +{ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + iop_desc_init_memcpy(desc, 1); + hw_desc.dma->byte_count = 0; + hw_desc.dma->dest_addr = 0; + hw_desc.dma->src_addr = 0; + break; + case AAU_ID: + iop_desc_init_null_xor(desc, 2, 1); + hw_desc.aau->byte_count = 0; + hw_desc.aau->dest_addr = 0; + hw_desc.aau->src[0] = 0; + hw_desc.aau->src[1] = 0; + break; + default: + BUG(); + } +} + +static inline void +iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len) +{ + int slots_per_op = desc->slots_per_op; + struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter; + int i = 0; + + if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) { + hw_desc->byte_count = len; + } else { + do { + iter = iop_hw_desc_slot_idx(hw_desc, i); + iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; + len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; + i += slots_per_op; + } while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT); + + if (len) { + iter = iop_hw_desc_slot_idx(hw_desc, i); + iter->byte_count = len; + } + } +} + +static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc, + struct iop_adma_chan *chan, + dma_addr_t addr) +{ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + hw_desc.dma->dest_addr = addr; + break; + case AAU_ID: + hw_desc.aau->dest_addr = addr; + break; + default: + BUG(); + } +} + +static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc, + dma_addr_t addr) +{ + struct iop3xx_desc_dma *hw_desc = desc->hw_desc; + hw_desc->src_addr = addr; +} + +static inline void +iop_desc_set_zero_sum_src_addr(struct iop_adma_desc_slot *desc, int src_idx, + dma_addr_t addr) +{ + + struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter; + int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; + int i; + + for (i = 0; (slot_cnt -= slots_per_op) >= 0; + i += slots_per_op, addr += IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) { + iter = iop_hw_desc_slot_idx(hw_desc, i); + iop3xx_aau_desc_set_src_addr(iter, src_idx, addr); + } +} + +static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc, + int src_idx, dma_addr_t addr) +{ + + struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter; + int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; + int i; + + for (i = 0; (slot_cnt -= slots_per_op) >= 0; + i += slots_per_op, addr += IOP_ADMA_XOR_MAX_BYTE_COUNT) { + iter = iop_hw_desc_slot_idx(hw_desc, i); + iop3xx_aau_desc_set_src_addr(iter, src_idx, addr); + } +} + +static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc, + u32 next_desc_addr) +{ + /* hw_desc->next_desc is the same location for all channels */ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + BUG_ON(hw_desc.dma->next_desc); + hw_desc.dma->next_desc = next_desc_addr; +} + +static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc) +{ + /* hw_desc->next_desc is the same location for all channels */ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + return hw_desc.dma->next_desc; +} + +static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc) +{ + /* hw_desc->next_desc is the same location for all channels */ + union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; + hw_desc.dma->next_desc = 0; +} + +static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc, + u32 val) +{ + struct iop3xx_desc_aau *hw_desc = desc->hw_desc; + hw_desc->src[0] = val; +} + +static inline int iop_desc_get_zero_result(struct iop_adma_desc_slot *desc) +{ + struct iop3xx_desc_aau *hw_desc = desc->hw_desc; + struct iop3xx_aau_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field; + + BUG_ON(!(desc_ctrl.tx_complete && desc_ctrl.zero_result_en)); + return desc_ctrl.zero_result_err; +} + +static inline void iop_chan_append(struct iop_adma_chan *chan) +{ + u32 dma_chan_ctrl; + /* workaround dropped interrupts on 3xx */ + mod_timer(&chan->cleanup_watchdog, jiffies + msecs_to_jiffies(3)); + + dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); + dma_chan_ctrl |= 0x2; + __raw_writel(dma_chan_ctrl, DMA_CCR(chan)); +} + +static inline void iop_chan_idle(int busy, struct iop_adma_chan *chan) +{ + if (!busy) + del_timer(&chan->cleanup_watchdog); +} + +static inline u32 iop_chan_get_status(struct iop_adma_chan *chan) +{ + return __raw_readl(DMA_CSR(chan)); +} + +static inline void iop_chan_disable(struct iop_adma_chan *chan) +{ + u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); + dma_chan_ctrl &= ~1; + __raw_writel(dma_chan_ctrl, DMA_CCR(chan)); +} + +static inline void iop_chan_enable(struct iop_adma_chan *chan) +{ + u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); + + dma_chan_ctrl |= 1; + __raw_writel(dma_chan_ctrl, DMA_CCR(chan)); +} + +static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan) +{ + u32 status = __raw_readl(DMA_CSR(chan)); + status &= (1 << 9); + __raw_writel(status, DMA_CSR(chan)); +} + +static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan) +{ + u32 status = __raw_readl(DMA_CSR(chan)); + status &= (1 << 8); + __raw_writel(status, DMA_CSR(chan)); +} + +static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan) +{ + u32 status = __raw_readl(DMA_CSR(chan)); + + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + status &= (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1); + break; + case AAU_ID: + status &= (1 << 5); + break; + default: + BUG(); + } + + __raw_writel(status, DMA_CSR(chan)); +} + +static inline int +iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan) +{ + return 0; +} + +static inline int +iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan) +{ + return 0; +} + +static inline int +iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan) +{ + return 0; +} + +static inline int +iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan) +{ + return test_bit(5, &status); +} + +static inline int +iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan) +{ + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + return test_bit(2, &status); + default: + return 0; + } +} + +static inline int +iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan) +{ + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + return test_bit(3, &status); + default: + return 0; + } +} + +static inline int +iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan) +{ + switch (chan->device->id) { + case DMA0_ID: + case DMA1_ID: + return test_bit(1, &status); + default: + return 0; + } +} +#endif /* _ADMA_H */ diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h index 63feceb7ede..81ca5d3e2bf 100644 --- a/include/asm-arm/hardware/iop3xx.h +++ b/include/asm-arm/hardware/iop3xx.h @@ -144,24 +144,9 @@ extern int init_atu; #define IOP3XX_IAR (volatile u32 *)IOP3XX_REG_ADDR(0x0380) /* DMA Controller */ -#define IOP3XX_DMA0_CCR (volatile u32 *)IOP3XX_REG_ADDR(0x0400) -#define IOP3XX_DMA0_CSR (volatile u32 *)IOP3XX_REG_ADDR(0x0404) -#define IOP3XX_DMA0_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x040c) -#define IOP3XX_DMA0_NDAR (volatile u32 *)IOP3XX_REG_ADDR(0x0410) -#define IOP3XX_DMA0_PADR (volatile u32 *)IOP3XX_REG_ADDR(0x0414) -#define IOP3XX_DMA0_PUADR (volatile u32 *)IOP3XX_REG_ADDR(0x0418) -#define IOP3XX_DMA0_LADR (volatile u32 *)IOP3XX_REG_ADDR(0x041c) -#define IOP3XX_DMA0_BCR (volatile u32 *)IOP3XX_REG_ADDR(0x0420) -#define IOP3XX_DMA0_DCR (volatile u32 *)IOP3XX_REG_ADDR(0x0424) -#define IOP3XX_DMA1_CCR (volatile u32 *)IOP3XX_REG_ADDR(0x0440) -#define IOP3XX_DMA1_CSR (volatile u32 *)IOP3XX_REG_ADDR(0x0444) -#define IOP3XX_DMA1_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x044c) -#define IOP3XX_DMA1_NDAR (volatile u32 *)IOP3XX_REG_ADDR(0x0450) -#define IOP3XX_DMA1_PADR (volatile u32 *)IOP3XX_REG_ADDR(0x0454) -#define IOP3XX_DMA1_PUADR (volatile u32 *)IOP3XX_REG_ADDR(0x0458) -#define IOP3XX_DMA1_LADR (volatile u32 *)IOP3XX_REG_ADDR(0x045c) -#define IOP3XX_DMA1_BCR (volatile u32 *)IOP3XX_REG_ADDR(0x0460) -#define IOP3XX_DMA1_DCR (volatile u32 *)IOP3XX_REG_ADDR(0x0464) +#define IOP3XX_DMA_PHYS_BASE(chan) (IOP3XX_PERIPHERAL_PHYS_BASE + \ + (0x400 + (chan << 6))) +#define IOP3XX_DMA_UPPER_PA(chan) (IOP3XX_DMA_PHYS_BASE(chan) + 0x27) /* Peripheral bus interface */ #define IOP3XX_PBCR (volatile u32 *)IOP3XX_REG_ADDR(0x0680) @@ -210,48 +195,8 @@ extern int init_atu; #define IOP_TMR_RATIO_1_1 0x00 /* Application accelerator unit */ -#define IOP3XX_AAU_ACR (volatile u32 *)IOP3XX_REG_ADDR(0x0800) -#define IOP3XX_AAU_ASR (volatile u32 *)IOP3XX_REG_ADDR(0x0804) -#define IOP3XX_AAU_ADAR (volatile u32 *)IOP3XX_REG_ADDR(0x0808) -#define IOP3XX_AAU_ANDAR (volatile u32 *)IOP3XX_REG_ADDR(0x080c) -#define IOP3XX_AAU_SAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0810) -#define IOP3XX_AAU_SAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0814) -#define IOP3XX_AAU_SAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0818) -#define IOP3XX_AAU_SAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x081c) -#define IOP3XX_AAU_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x0820) -#define IOP3XX_AAU_ABCR (volatile u32 *)IOP3XX_REG_ADDR(0x0824) -#define IOP3XX_AAU_ADCR (volatile u32 *)IOP3XX_REG_ADDR(0x0828) -#define IOP3XX_AAU_SAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x082c) -#define IOP3XX_AAU_SAR6 (volatile u32 *)IOP3XX_REG_ADDR(0x0830) -#define IOP3XX_AAU_SAR7 (volatile u32 *)IOP3XX_REG_ADDR(0x0834) -#define IOP3XX_AAU_SAR8 (volatile u32 *)IOP3XX_REG_ADDR(0x0838) -#define IOP3XX_AAU_EDCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x083c) -#define IOP3XX_AAU_SAR9 (volatile u32 *)IOP3XX_REG_ADDR(0x0840) -#define IOP3XX_AAU_SAR10 (volatile u32 *)IOP3XX_REG_ADDR(0x0844) -#define IOP3XX_AAU_SAR11 (volatile u32 *)IOP3XX_REG_ADDR(0x0848) -#define IOP3XX_AAU_SAR12 (volatile u32 *)IOP3XX_REG_ADDR(0x084c) -#define IOP3XX_AAU_SAR13 (volatile u32 *)IOP3XX_REG_ADDR(0x0850) -#define IOP3XX_AAU_SAR14 (volatile u32 *)IOP3XX_REG_ADDR(0x0854) -#define IOP3XX_AAU_SAR15 (volatile u32 *)IOP3XX_REG_ADDR(0x0858) -#define IOP3XX_AAU_SAR16 (volatile u32 *)IOP3XX_REG_ADDR(0x085c) -#define IOP3XX_AAU_EDCR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0860) -#define IOP3XX_AAU_SAR17 (volatile u32 *)IOP3XX_REG_ADDR(0x0864) -#define IOP3XX_AAU_SAR18 (volatile u32 *)IOP3XX_REG_ADDR(0x0868) -#define IOP3XX_AAU_SAR19 (volatile u32 *)IOP3XX_REG_ADDR(0x086c) -#define IOP3XX_AAU_SAR20 (volatile u32 *)IOP3XX_REG_ADDR(0x0870) -#define IOP3XX_AAU_SAR21 (volatile u32 *)IOP3XX_REG_ADDR(0x0874) -#define IOP3XX_AAU_SAR22 (volatile u32 *)IOP3XX_REG_ADDR(0x0878) -#define IOP3XX_AAU_SAR23 (volatile u32 *)IOP3XX_REG_ADDR(0x087c) -#define IOP3XX_AAU_SAR24 (volatile u32 *)IOP3XX_REG_ADDR(0x0880) -#define IOP3XX_AAU_EDCR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0884) -#define IOP3XX_AAU_SAR25 (volatile u32 *)IOP3XX_REG_ADDR(0x0888) -#define IOP3XX_AAU_SAR26 (volatile u32 *)IOP3XX_REG_ADDR(0x088c) -#define IOP3XX_AAU_SAR27 (volatile u32 *)IOP3XX_REG_ADDR(0x0890) -#define IOP3XX_AAU_SAR28 (volatile u32 *)IOP3XX_REG_ADDR(0x0894) -#define IOP3XX_AAU_SAR29 (volatile u32 *)IOP3XX_REG_ADDR(0x0898) -#define IOP3XX_AAU_SAR30 (volatile u32 *)IOP3XX_REG_ADDR(0x089c) -#define IOP3XX_AAU_SAR31 (volatile u32 *)IOP3XX_REG_ADDR(0x08a0) -#define IOP3XX_AAU_SAR32 (volatile u32 *)IOP3XX_REG_ADDR(0x08a4) +#define IOP3XX_AAU_PHYS_BASE (IOP3XX_PERIPHERAL_PHYS_BASE + 0x800) +#define IOP3XX_AAU_UPPER_PA (IOP3XX_AAU_PHYS_BASE + 0xa7) /* I2C bus interface unit */ #define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680) @@ -329,6 +274,9 @@ static inline void write_tisr(u32 val) asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val)); } +extern struct platform_device iop3xx_dma_0_channel; +extern struct platform_device iop3xx_dma_1_channel; +extern struct platform_device iop3xx_aau_channel; extern struct platform_device iop3xx_i2c0_device; extern struct platform_device iop3xx_i2c1_device; diff --git a/include/asm-arm/hardware/iop_adma.h b/include/asm-arm/hardware/iop_adma.h new file mode 100644 index 00000000000..ca8e71f4434 --- /dev/null +++ b/include/asm-arm/hardware/iop_adma.h @@ -0,0 +1,118 @@ +/* + * Copyright © 2006, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + */ +#ifndef IOP_ADMA_H +#define IOP_ADMA_H +#include <linux/types.h> +#include <linux/dmaengine.h> +#include <linux/interrupt.h> + +#define IOP_ADMA_SLOT_SIZE 32 +#define IOP_ADMA_THRESHOLD 4 + +/** + * struct iop_adma_device - internal representation of an ADMA device + * @pdev: Platform device + * @id: HW ADMA Device selector + * @dma_desc_pool: base of DMA descriptor region (DMA address) + * @dma_desc_pool_virt: base of DMA descriptor region (CPU address) + * @common: embedded struct dma_device + */ +struct iop_adma_device { + struct platform_device *pdev; + int id; + dma_addr_t dma_desc_pool; + void *dma_desc_pool_virt; + struct dma_device common; +}; + +/** + * struct iop_adma_chan - internal representation of an ADMA device + * @pending: allows batching of hardware operations + * @completed_cookie: identifier for the most recently completed operation + * @lock: serializes enqueue/dequeue operations to the slot pool + * @mmr_base: memory mapped register base + * @chain: device chain view of the descriptors + * @device: parent device + * @common: common dmaengine channel object members + * @last_used: place holder for allocation to continue from where it left off + * @all_slots: complete domain of slots usable by the channel + * @cleanup_watchdog: workaround missed interrupts on iop3xx + * @slots_allocated: records the actual size of the descriptor slot pool + * @irq_tasklet: bottom half where iop_adma_slot_cleanup runs + */ +struct iop_adma_chan { + int pending; + dma_cookie_t completed_cookie; + spinlock_t lock; /* protects the descriptor slot pool */ + void __iomem *mmr_base; + struct list_head chain; + struct iop_adma_device *device; + struct dma_chan common; + struct iop_adma_desc_slot *last_used; + struct list_head all_slots; + struct timer_list cleanup_watchdog; + int slots_allocated; + struct tasklet_struct irq_tasklet; +}; + +/** + * struct iop_adma_desc_slot - IOP-ADMA software descriptor + * @slot_node: node on the iop_adma_chan.all_slots list + * @chain_node: node on the op_adma_chan.chain list + * @hw_desc: virtual address of the hardware descriptor chain + * @phys: hardware address of the hardware descriptor chain + * @group_head: first operation in a transaction + * @slot_cnt: total slots used in an transaction (group of operations) + * @slots_per_op: number of slots per operation + * @idx: pool index + * @unmap_src_cnt: number of xor sources + * @unmap_len: transaction bytecount + * @async_tx: support for the async_tx api + * @group_list: list of slots that make up a multi-descriptor transaction + * for example transfer lengths larger than the supported hw max + * @xor_check_result: result of zero sum + * @crc32_result: result crc calculation + */ +struct iop_adma_desc_slot { + struct list_head slot_node; + struct list_head chain_node; + void *hw_desc; + struct iop_adma_desc_slot *group_head; + u16 slot_cnt; + u16 slots_per_op; + u16 idx; + u16 unmap_src_cnt; + size_t unmap_len; + struct dma_async_tx_descriptor async_tx; + union { + u32 *xor_check_result; + u32 *crc32_result; + }; +}; + +struct iop_adma_platform_data { + int hw_id; + dma_cap_mask_t cap_mask; + size_t pool_size; +}; + +#define to_iop_sw_desc(addr_hw_desc) \ + container_of(addr_hw_desc, struct iop_adma_desc_slot, hw_desc) +#define iop_hw_desc_slot_idx(hw_desc, idx) \ + ( (void *) (((unsigned long) hw_desc) + ((idx) << 5)) ) +#endif diff --git a/include/asm-arm/hwcap.h b/include/asm-arm/hwcap.h new file mode 100644 index 00000000000..01a1391d301 --- /dev/null +++ b/include/asm-arm/hwcap.h @@ -0,0 +1,28 @@ +#ifndef __ASMARM_HWCAP_H +#define __ASMARM_HWCAP_H + +/* + * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP + */ +#define HWCAP_SWP 1 +#define HWCAP_HALF 2 +#define HWCAP_THUMB 4 +#define HWCAP_26BIT 8 /* Play it safe */ +#define HWCAP_FAST_MULT 16 +#define HWCAP_FPA 32 +#define HWCAP_VFP 64 +#define HWCAP_EDSP 128 +#define HWCAP_JAVA 256 +#define HWCAP_IWMMXT 512 +#define HWCAP_CRUNCH 1024 + +#if defined(__KERNEL__) && !defined(__ASSEMBLY__) +/* + * This yields a mask that user programs can use to figure out what + * instruction set this cpu supports. + */ +#define ELF_HWCAP (elf_hwcap) +extern unsigned int elf_hwcap; +#endif + +#endif diff --git a/include/asm-arm/linkage.h b/include/asm-arm/linkage.h index dbe4b4e31a5..5a25632b1bc 100644 --- a/include/asm-arm/linkage.h +++ b/include/asm-arm/linkage.h @@ -4,4 +4,8 @@ #define __ALIGN .align 0 #define __ALIGN_STR ".align 0" +#define ENDPROC(name) \ + .type name, %function; \ + END(name) + #endif diff --git a/include/asm-arm/pci.h b/include/asm-arm/pci.h index f21abd4ddac..ed3f898191f 100644 --- a/include/asm-arm/pci.h +++ b/include/asm-arm/pci.h @@ -26,11 +26,6 @@ static inline void pcibios_penalize_isa_irq(int irq, int active) #define PCI_DMA_BUS_IS_PHYS (0) /* - * We don't support DAC DMA cycles. - */ -#define pci_dac_dma_supported(pci_dev, mask) (0) - -/* * Whether pci_unmap_{single,page} is a nop depends upon the * configuration. */ @@ -76,10 +71,6 @@ pcibios_select_root(struct pci_dev *pdev, struct resource *res) return root; } -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - #endif /* __KERNEL__ */ #endif diff --git a/include/asm-arm/ptrace.h b/include/asm-arm/ptrace.h index 2d0dad8c10a..7aaa206cb54 100644 --- a/include/asm-arm/ptrace.h +++ b/include/asm-arm/ptrace.h @@ -10,6 +10,8 @@ #ifndef __ASM_ARM_PTRACE_H #define __ASM_ARM_PTRACE_H +#include <asm/hwcap.h> + #define PTRACE_GETREGS 12 #define PTRACE_SETREGS 13 #define PTRACE_GETFPREGS 14 @@ -45,6 +47,7 @@ #define PSR_T_BIT 0x00000020 #define PSR_F_BIT 0x00000040 #define PSR_I_BIT 0x00000080 +#define PSR_A_BIT 0x00000100 #define PSR_J_BIT 0x01000000 #define PSR_Q_BIT 0x08000000 #define PSR_V_BIT 0x10000000 @@ -103,6 +106,10 @@ struct pt_regs { #define thumb_mode(regs) (0) #endif +#define isa_mode(regs) \ + ((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \ + (((regs)->ARM_cpsr & PSR_T_BIT) >> 5)) + #define processor_mode(regs) \ ((regs)->ARM_cpsr & MODE_MASK) @@ -112,22 +119,22 @@ struct pt_regs { #define fast_interrupts_enabled(regs) \ (!((regs)->ARM_cpsr & PSR_F_BIT)) -#define condition_codes(regs) \ - ((regs)->ARM_cpsr & (PSR_V_BIT|PSR_C_BIT|PSR_Z_BIT|PSR_N_BIT)) - /* Are the current registers suitable for user mode? * (used to maintain security in signal handlers) */ static inline int valid_user_regs(struct pt_regs *regs) { - if (user_mode(regs) && - (regs->ARM_cpsr & (PSR_F_BIT|PSR_I_BIT)) == 0) + if (user_mode(regs) && (regs->ARM_cpsr & PSR_I_BIT) == 0) { + regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT); return 1; + } /* * Force CPSR to something logical... */ - regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT; + regs->ARM_cpsr &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | PSR_T_BIT | MODE32_BIT; + if (!(elf_hwcap & HWCAP_26BIT)) + regs->ARM_cpsr |= USR_MODE; return 0; } diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h index 250d7f145ac..bfdbebebdc1 100644 --- a/include/asm-arm/unistd.h +++ b/include/asm-arm/unistd.h @@ -367,6 +367,7 @@ #define __NR_get_robust_list (__NR_SYSCALL_BASE+339) #define __NR_splice (__NR_SYSCALL_BASE+340) #define __NR_arm_sync_file_range (__NR_SYSCALL_BASE+341) +#define __NR_sync_file_range2 __NR_arm_sync_file_range #define __NR_tee (__NR_SYSCALL_BASE+342) #define __NR_vmsplice (__NR_SYSCALL_BASE+343) #define __NR_move_pages (__NR_SYSCALL_BASE+344) diff --git a/include/asm-arm26/termbits.h b/include/asm-arm26/termbits.h index a3f4fe1742d..f66b5180473 100644 --- a/include/asm-arm26/termbits.h +++ b/include/asm-arm26/termbits.h @@ -15,7 +15,7 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; -struct ktermios { +struct termios2 { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ tcflag_t c_cflag; /* control mode flags */ @@ -26,6 +26,16 @@ struct ktermios { speed_t c_ospeed; /* output speed */ }; +struct ktermios { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; /* c_cc characters */ #define VINTR 0 diff --git a/include/asm-avr32/arch-at32ap/gpio.h b/include/asm-avr32/arch-at32ap/gpio.h index 80a21aa9ae7..af7f9535bab 100644 --- a/include/asm-avr32/arch-at32ap/gpio.h +++ b/include/asm-avr32/arch-at32ap/gpio.h @@ -14,6 +14,8 @@ int gpio_direction_output(unsigned int gpio, int value); int gpio_get_value(unsigned int gpio); void gpio_set_value(unsigned int gpio, int value); +#include <asm-generic/gpio.h> /* cansleep wrappers */ + static inline int gpio_to_irq(unsigned int gpio) { return gpio + GPIO_IRQ_BASE; diff --git a/include/asm-avr32/cache.h b/include/asm-avr32/cache.h index dabb955f3c0..d3cf35ab11a 100644 --- a/include/asm-avr32/cache.h +++ b/include/asm-avr32/cache.h @@ -4,6 +4,15 @@ #define L1_CACHE_SHIFT 5 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) +/* + * Memory returned by kmalloc() may be used for DMA, so we must make + * sure that all such allocations are cache aligned. Otherwise, + * unrelated code may cause parts of the buffer to be read into the + * cache before the transfer is done, causing old data to be seen by + * the CPU. + */ +#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES + #ifndef __ASSEMBLER__ struct cache_info { unsigned int ways; diff --git a/include/asm-avr32/termbits.h b/include/asm-avr32/termbits.h index c215fafdae4..db2daab31fd 100644 --- a/include/asm-avr32/termbits.h +++ b/include/asm-avr32/termbits.h @@ -17,6 +17,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ diff --git a/include/asm-blackfin/Kbuild b/include/asm-blackfin/Kbuild index c68e1680da0..71f8fe78325 100644 --- a/include/asm-blackfin/Kbuild +++ b/include/asm-blackfin/Kbuild @@ -1 +1,3 @@ include include/asm-generic/Kbuild.asm + +header-y += fixed_code.h diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h index 57f37ccdcdf..c4d6cbbf96d 100644 --- a/include/asm-blackfin/bfin-global.h +++ b/include/asm-blackfin/bfin-global.h @@ -67,6 +67,18 @@ extern void evt14_softirq(void); extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs); extern void bfin_gpio_interrupt_setup(int irq, int irq_pfx, int type); +extern asmlinkage void finish_atomic_sections (struct pt_regs *regs); +extern char fixed_code_start; +extern char fixed_code_end; +extern int atomic_xchg32(void); +extern int atomic_cas32(void); +extern int atomic_add32(void); +extern int atomic_sub32(void); +extern int atomic_ior32(void); +extern int atomic_and32(void); +extern int atomic_xor32(void); +extern void sigreturn_stub(void); + extern void *l1_data_A_sram_alloc(size_t); extern void *l1_data_B_sram_alloc(size_t); extern void *l1_inst_sram_alloc(size_t); diff --git a/include/asm-blackfin/blackfin.h b/include/asm-blackfin/blackfin.h index 14e58de7397..25b934b7f82 100644 --- a/include/asm-blackfin/blackfin.h +++ b/include/asm-blackfin/blackfin.h @@ -6,7 +6,11 @@ #ifndef _BLACKFIN_H_ #define _BLACKFIN_H_ -#include <asm/macros.h> +#define LO(con32) ((con32) & 0xFFFF) +#define lo(con32) ((con32) & 0xFFFF) +#define HI(con32) (((con32) >> 16) & 0xFFFF) +#define hi(con32) (((con32) >> 16) & 0xFFFF) + #include <asm/mach/blackfin.h> #include <asm/bfin-global.h> @@ -35,7 +39,9 @@ static inline void SSYNC (void) #elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244) static inline void SSYNC (void) { - __builtin_bfin_ssync(); + __asm__ __volatile__ ("nop; nop; nop;\n\t" + "ssync;\n\t" + ::); } #elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244) static inline void SSYNC (void) @@ -67,7 +73,9 @@ static inline void CSYNC (void) #elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244) static inline void CSYNC (void) { - __builtin_bfin_csync(); + __asm__ __volatile__ ("nop; nop; nop;\n\t" + "ssync;\n\t" + ::); } #elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244) static inline void CSYNC (void) @@ -76,6 +84,31 @@ static inline void CSYNC (void) } #endif +#else /* __ASSEMBLY__ */ + +/* SSYNC & CSYNC implementations for assembly files */ + +#define ssync(x) SSYNC(x) +#define csync(x) CSYNC(x) + +#if defined(ANOMALY_05000312) && defined(ANOMALY_05000244) +#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch; +#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch; + +#elif defined(ANOMALY_05000312) && !defined(ANOMALY_05000244) +#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch; +#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch; + +#elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244) +#define SSYNC(scratch) nop; nop; nop; SSYNC; +#define CSYNC(scratch) nop; nop; nop; CSYNC; + +#elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244) +#define SSYNC(scratch) SSYNC; +#define CSYNC(scratch) CSYNC; + +#endif /* ANOMALY_05000312 & ANOMALY_05000244 handling */ + #endif /* __ASSEMBLY__ */ #endif /* _BLACKFIN_H_ */ diff --git a/include/asm-blackfin/cplbinit.h b/include/asm-blackfin/cplbinit.h index 3bad2d1e6a8..bec6ecdf1bd 100644 --- a/include/asm-blackfin/cplbinit.h +++ b/include/asm-blackfin/cplbinit.h @@ -57,8 +57,8 @@ struct cplb_tab { u16 size; }; -u_long icplb_table[MAX_CPLBS+1]; -u_long dcplb_table[MAX_CPLBS+1]; +extern u_long icplb_table[MAX_CPLBS+1]; +extern u_long dcplb_table[MAX_CPLBS+1]; /* Till here we are discussing about the static memory management model. * However, the operating envoronments commonly define more CPLB @@ -70,134 +70,27 @@ u_long dcplb_table[MAX_CPLBS+1]; */ #ifdef CONFIG_CPLB_SWITCH_TAB_L1 -u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data)); -u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data)); +extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data)); +extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data)); #ifdef CONFIG_CPLB_INFO -u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data)); -u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data)); +extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data)); +extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data)); #endif /* CONFIG_CPLB_INFO */ #else -u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]; -u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]; +extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]; +extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]; #ifdef CONFIG_CPLB_INFO -u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]; -u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]; +extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]; +extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]; #endif /* CONFIG_CPLB_INFO */ #endif /*CONFIG_CPLB_SWITCH_TAB_L1*/ -struct s_cplb { - struct cplb_tab init_i; - struct cplb_tab init_d; - struct cplb_tab switch_i; - struct cplb_tab switch_d; -}; +extern unsigned long reserved_mem_dcache_on; +extern unsigned long reserved_mem_icache_on; -#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE) -static struct cplb_desc cplb_data[] = { - { - .start = 0, - .end = SIZE_4K, - .psize = SIZE_4K, - .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB, - .i_conf = SDRAM_OOPS, - .d_conf = SDRAM_OOPS, -#if defined(CONFIG_DEBUG_HUNT_FOR_ZERO) - .valid = 1, -#else - .valid = 0, -#endif - .name = "ZERO Pointer Saveguard", - }, - { - .start = L1_CODE_START, - .end = L1_CODE_START + L1_CODE_LENGTH, - .psize = SIZE_4M, - .attr = INITIAL_T | SWITCH_T | I_CPLB, - .i_conf = L1_IMEMORY, - .d_conf = 0, - .valid = 1, - .name = "L1 I-Memory", - }, - { - .start = L1_DATA_A_START, - .end = L1_DATA_B_START + L1_DATA_B_LENGTH, - .psize = SIZE_4M, - .attr = INITIAL_T | SWITCH_T | D_CPLB, - .i_conf = 0, - .d_conf = L1_DMEMORY, -#if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0)) - .valid = 1, -#else - .valid = 0, -#endif - .name = "L1 D-Memory", - }, - { - .start = 0, - .end = 0, /* dynamic */ - .psize = 0, - .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB, - .i_conf = SDRAM_IGENERIC, - .d_conf = SDRAM_DGENERIC, - .valid = 1, - .name = "SDRAM Kernel", - }, - { - .start = 0, /* dynamic */ - .end = 0, /* dynamic */ - .psize = 0, - .attr = INITIAL_T | SWITCH_T | D_CPLB, - .i_conf = SDRAM_IGENERIC, - .d_conf = SDRAM_DNON_CHBL, - .valid = 1, - .name = "SDRAM RAM MTD", - }, - { - .start = 0, /* dynamic */ - .end = 0, /* dynamic */ - .psize = SIZE_1M, - .attr = INITIAL_T | SWITCH_T | D_CPLB, - .d_conf = SDRAM_DNON_CHBL, - .valid = 1,//(DMA_UNCACHED_REGION > 0), - .name = "SDRAM Uncached DMA ZONE", - }, - { - .start = 0, /* dynamic */ - .end = 0, /* dynamic */ - .psize = 0, - .attr = SWITCH_T | D_CPLB, - .i_conf = 0, /* dynamic */ - .d_conf = 0, /* dynamic */ - .valid = 1, - .name = "SDRAM Reserved Memory", - }, - { - .start = ASYNC_BANK0_BASE, - .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE, - .psize = 0, - .attr = SWITCH_T | D_CPLB, - .d_conf = SDRAM_EBIU, - .valid = 1, - .name = "ASYNC Memory", - }, - { -#if defined(CONFIG_BF561) - .start = L2_SRAM, - .end = L2_SRAM_END, - .psize = SIZE_1M, - .attr = SWITCH_T | D_CPLB, - .i_conf = L2_MEMORY, - .d_conf = L2_MEMORY, - .valid = 1, -#else - .valid = 0, -#endif - .name = "L2 Memory", - } -}; -#endif +extern void generate_cpl_tables(void); diff --git a/include/asm-blackfin/dma-mapping.h b/include/asm-blackfin/dma-mapping.h index 7a77d7fe3a3..282fabccf6a 100644 --- a/include/asm-blackfin/dma-mapping.h +++ b/include/asm-blackfin/dma-mapping.h @@ -15,6 +15,8 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr, #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) +#define dma_mapping_error + /* * Map a single buffer of the indicated size for DMA in streaming mode. * The 32-bit bus address to use is returned. diff --git a/include/asm-blackfin/fixed_code.h b/include/asm-blackfin/fixed_code.h new file mode 100644 index 00000000000..e6df84ee155 --- /dev/null +++ b/include/asm-blackfin/fixed_code.h @@ -0,0 +1,20 @@ +/* This file defines the fixed addresses where userspace programs can find + atomic code sequences. */ + +#define FIXED_CODE_START 0x400 + +#define SIGRETURN_STUB 0x400 + +#define ATOMIC_SEQS_START 0x410 + +#define ATOMIC_XCHG32 0x410 +#define ATOMIC_CAS32 0x420 +#define ATOMIC_ADD32 0x430 +#define ATOMIC_SUB32 0x440 +#define ATOMIC_IOR32 0x450 +#define ATOMIC_AND32 0x460 +#define ATOMIC_XOR32 0x470 + +#define ATOMIC_SEQS_END 0x480 + +#define FIXED_CODE_END 0x480 diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h index aa0d5503e23..7480cfa7e2d 100644 --- a/include/asm-blackfin/gpio.h +++ b/include/asm-blackfin/gpio.h @@ -204,8 +204,62 @@ #endif +#ifdef BF548_FAMILY +#include <asm-blackfin/mach-bf548/gpio.h> +#endif + #ifdef BF561_FAMILY #define MAX_BLACKFIN_GPIOS 48 + +#define GPIO_PF0 0 +#define GPIO_PF1 1 +#define GPIO_PF2 2 +#define GPIO_PF3 3 +#define GPIO_PF4 4 +#define GPIO_PF5 5 +#define GPIO_PF6 6 +#define GPIO_PF7 7 +#define GPIO_PF8 8 +#define GPIO_PF9 9 +#define GPIO_PF10 10 +#define GPIO_PF11 11 +#define GPIO_PF12 12 +#define GPIO_PF13 13 +#define GPIO_PF14 14 +#define GPIO_PF15 15 +#define GPIO_PF16 16 +#define GPIO_PF17 17 +#define GPIO_PF18 18 +#define GPIO_PF19 19 +#define GPIO_PF20 20 +#define GPIO_PF21 21 +#define GPIO_PF22 22 +#define GPIO_PF23 23 +#define GPIO_PF24 24 +#define GPIO_PF25 25 +#define GPIO_PF26 26 +#define GPIO_PF27 27 +#define GPIO_PF28 28 +#define GPIO_PF29 29 +#define GPIO_PF30 30 +#define GPIO_PF31 31 +#define GPIO_PF32 32 +#define GPIO_PF33 33 +#define GPIO_PF34 34 +#define GPIO_PF35 35 +#define GPIO_PF36 36 +#define GPIO_PF37 37 +#define GPIO_PF38 38 +#define GPIO_PF39 39 +#define GPIO_PF40 40 +#define GPIO_PF41 41 +#define GPIO_PF42 42 +#define GPIO_PF43 43 +#define GPIO_PF44 44 +#define GPIO_PF45 45 +#define GPIO_PF46 46 +#define GPIO_PF47 47 + #define PORT_FIO0 GPIO_0 #define PORT_FIO1 GPIO_16 #define PORT_FIO2 GPIO_32 @@ -230,6 +284,7 @@ * MODIFICATION HISTORY : **************************************************************/ +#ifndef BF548_FAMILY void set_gpio_dir(unsigned short, unsigned short); void set_gpio_inen(unsigned short, unsigned short); void set_gpio_polar(unsigned short, unsigned short); @@ -299,6 +354,7 @@ struct gpio_port_t { unsigned short dummy16; unsigned short inen; }; +#endif #ifdef CONFIG_PM #define PM_WAKE_RISING 0x1 @@ -332,6 +388,7 @@ struct gpio_port_s { unsigned short inen; unsigned short fer; + unsigned short reserved; }; #endif /*CONFIG_PM*/ @@ -356,8 +413,10 @@ void gpio_free(unsigned short); void gpio_set_value(unsigned short gpio, unsigned short arg); unsigned short gpio_get_value(unsigned short gpio); +#ifndef BF548_FAMILY #define gpio_get_value(gpio) get_gpio_data(gpio) #define gpio_set_value(gpio, value) set_gpio_data(gpio, value) +#endif void gpio_direction_input(unsigned short gpio); void gpio_direction_output(unsigned short gpio); diff --git a/include/asm-blackfin/hardirq.h b/include/asm-blackfin/hardirq.h index 0cab0d35bad..b6b19f1b9da 100644 --- a/include/asm-blackfin/hardirq.h +++ b/include/asm-blackfin/hardirq.h @@ -28,7 +28,11 @@ typedef struct { * SOFTIRQ_MASK: 0x00ff0000 */ +#if NR_IRQS > 256 +#define HARDIRQ_BITS 9 +#else #define HARDIRQ_BITS 8 +#endif #ifdef NR_IRQS # if (1 << HARDIRQ_BITS) < NR_IRQS diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h index eac8bcaf64c..142cb333db2 100644 --- a/include/asm-blackfin/io.h +++ b/include/asm-blackfin/io.h @@ -20,7 +20,7 @@ */ #ifndef __ASSEMBLY__ -static inline unsigned char readb(void __iomem *addr) +static inline unsigned char readb(const volatile void __iomem *addr) { unsigned int val; int tmp; @@ -35,7 +35,7 @@ static inline unsigned char readb(void __iomem *addr) return (unsigned char) val; } -static inline unsigned short readw(void __iomem *addr) +static inline unsigned short readw(const volatile void __iomem *addr) { unsigned int val; int tmp; @@ -50,7 +50,7 @@ static inline unsigned short readw(void __iomem *addr) return (unsigned short) val; } -static inline unsigned int readl(void __iomem *addr) +static inline unsigned int readl(const volatile void __iomem *addr) { unsigned int val; int tmp; diff --git a/include/asm-blackfin/kgdb.h b/include/asm-blackfin/kgdb.h new file mode 100644 index 00000000000..532bd905200 --- /dev/null +++ b/include/asm-blackfin/kgdb.h @@ -0,0 +1,183 @@ +/* + * File: include/asm-blackfin/kgdb.h + * Based on: + * Author: Sonic Zhang + * + * Created: + * Description: + * + * Rev: $Id: kgdb_bfin_linux-2.6.x.patch 4934 2007-02-13 09:32:11Z sonicz $ + * + * Modified: + * Copyright 2005-2006 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __ASM_BLACKFIN_KGDB_H__ +#define __ASM_BLACKFIN_KGDB_H__ + +#include <linux/ptrace.h> + +/* gdb locks */ +#define KGDB_MAX_NO_CPUS 8 + +/************************************************************************/ +/* BUFMAX defines the maximum number of characters in inbound/outbound buffers*/ +/* at least NUMREGBYTES*2 are needed for register packets */ +/* Longer buffer is needed to list all threads */ +#define BUFMAX 2048 + +/* + * Note that this register image is different from + * the register image that Linux produces at interrupt time. + * + * Linux's register image is defined by struct pt_regs in ptrace.h. + */ +enum regnames { + /* Core Registers */ + BFIN_R0 = 0, + BFIN_R1, + BFIN_R2, + BFIN_R3, + BFIN_R4, + BFIN_R5, + BFIN_R6, + BFIN_R7, + BFIN_P0, + BFIN_P1, + BFIN_P2, + BFIN_P3, + BFIN_P4, + BFIN_P5, + BFIN_SP, + BFIN_FP, + BFIN_I0, + BFIN_I1, + BFIN_I2, + BFIN_I3, + BFIN_M0, + BFIN_M1, + BFIN_M2, + BFIN_M3, + BFIN_B0, + BFIN_B1, + BFIN_B2, + BFIN_B3, + BFIN_L0, + BFIN_L1, + BFIN_L2, + BFIN_L3, + BFIN_A0_DOT_X, + BFIN_A0_DOT_W, + BFIN_A1_DOT_X, + BFIN_A1_DOT_W, + BFIN_ASTAT, + BFIN_RETS, + BFIN_LC0, + BFIN_LT0, + BFIN_LB0, + BFIN_LC1, + BFIN_LT1, + BFIN_LB1, + BFIN_CYCLES, + BFIN_CYCLES2, + BFIN_USP, + BFIN_SEQSTAT, + BFIN_SYSCFG, + BFIN_RETI, + BFIN_RETX, + BFIN_RETN, + BFIN_RETE, + + /* Pseudo Registers */ + BFIN_PC, + BFIN_CC, + BFIN_EXTRA1, /* Address of .text section. */ + BFIN_EXTRA2, /* Address of .data section. */ + BFIN_EXTRA3, /* Address of .bss section. */ + BFIN_FDPIC_EXEC, + BFIN_FDPIC_INTERP, + + /* MMRs */ + BFIN_IPEND, + + /* LAST ENTRY SHOULD NOT BE CHANGED. */ + BFIN_NUM_REGS /* The number of all registers. */ +}; + +/* Number of bytes of registers. */ +#define NUMREGBYTES BFIN_NUM_REGS*4 + +#define BREAKPOINT() asm(" EXCPT 2;"); +#define BREAK_INSTR_SIZE 2 +#define HW_BREAKPOINT_NUM 6 + +/* Instruction watchpoint address control register bits mask */ +#define WPPWR 0x1 +#define WPIREN01 0x2 +#define WPIRINV01 0x4 +#define WPIAEN0 0x8 +#define WPIAEN1 0x10 +#define WPICNTEN0 0x20 +#define WPICNTEN1 0x40 +#define EMUSW0 0x80 +#define EMUSW1 0x100 +#define WPIREN23 0x200 +#define WPIRINV23 0x400 +#define WPIAEN2 0x800 +#define WPIAEN3 0x1000 +#define WPICNTEN2 0x2000 +#define WPICNTEN3 0x4000 +#define EMUSW2 0x8000 +#define EMUSW3 0x10000 +#define WPIREN45 0x20000 +#define WPIRINV45 0x40000 +#define WPIAEN4 0x80000 +#define WPIAEN5 0x100000 +#define WPICNTEN4 0x200000 +#define WPICNTEN5 0x400000 +#define EMUSW4 0x800000 +#define EMUSW5 0x1000000 +#define WPAND 0x2000000 + +/* Data watchpoint address control register bits mask */ +#define WPDREN01 0x1 +#define WPDRINV01 0x2 +#define WPDAEN0 0x4 +#define WPDAEN1 0x8 +#define WPDCNTEN0 0x10 +#define WPDCNTEN1 0x20 +#define WPDSRC0 0xc0 +#define WPDACC0 0x300 +#define WPDSRC1 0xc00 +#define WPDACC1 0x3000 + +/* Watchpoint status register bits mask */ +#define STATIA0 0x1 +#define STATIA1 0x2 +#define STATIA2 0x4 +#define STATIA3 0x8 +#define STATIA4 0x10 +#define STATIA5 0x20 +#define STATDA0 0x40 +#define STATDA1 0x80 + +extern void kgdb_print(const char *fmt, ...); + +#endif diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h index a84d3909345..7302f290b93 100644 --- a/include/asm-blackfin/mach-bf533/anomaly.h +++ b/include/asm-blackfin/mach-bf533/anomaly.h @@ -43,7 +43,8 @@ #endif /* Issues that are common to 0.5, 0.4, and 0.3 silicon */ -#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3)) +#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) \ + || defined(CONFIG_BF_REV_0_3)) #define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in slot1 and store of a P register in slot 2 is not supported */ @@ -76,11 +77,16 @@ control */ #define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when killed in a particular stage*/ +#define ANOMALY_05000311 /* Erroneous flag pin operations under specific + sequences */ #define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC registers are interrupted */ -#define ANOMALY_05000311 /* Erroneous flag pin operations under specific sequences*/ - -#endif +#define ANOMALY_05000313 /* PPI Is Level-Sensitive on First Transfer */ +#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously On + * Next System MMR Access */ +#define ANOMALY_05000319 /* Internal Voltage Regulator Values of 1.05V, 1.10V + * and 1.15V Not Allowed for LQFP Packages */ +#endif /* Issues that are common to 0.5, 0.4, and 0.3 silicon */ /* These issues only occur on 0.3 or 0.4 BF533 */ #if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3)) @@ -134,14 +140,14 @@ internal voltage regulator (VDDint) to increase. */ #define ANOMALY_05000270 /* High I/O activity causes the output voltage of the internal voltage regulator (VDDint) to decrease */ -#endif +#endif /* issues only occur on 0.3 or 0.4 BF533 */ /* These issues are only on 0.4 silicon */ #if (defined(CONFIG_BF_REV_0_4)) #define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */ #define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel (TDM) */ -#endif +#endif /* issues are only on 0.4 silicon */ /* These issues are only on 0.3 silicon */ #if defined(CONFIG_BF_REV_0_3) @@ -170,6 +176,72 @@ #define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame Sync Transmit Mode */ #define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */ +#endif /* only on 0.3 silicon */ + +#if defined(CONFIG_BF_REV_0_2) +#define ANOMALY_05000067 /* Watchpoints (Hardware Breakpoints) are not + * supported */ +#define ANOMALY_05000109 /* Reserved bits in SYSCFG register not set at + * power on */ +#define ANOMALY_05000116 /* Trace Buffers may record discontinuities into + * emulation mode and/or exception, NMI, reset + * handlers */ +#define ANOMALY_05000123 /* DTEST_COMMAND initiated memory access may be + * incorrect if data cache or DMA is active */ +#define ANOMALY_05000124 /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, + * or 1:1 */ +#define ANOMALY_05000125 /* Erroneous exception when enabling cache */ +#define ANOMALY_05000126 /* SPI clock polarity and phase bits incorrect + * during booting */ +#define ANOMALY_05000137 /* DMEM_CONTROL is not set on Reset */ +#define ANOMALY_05000138 /* SPI boot will not complete if there is a zero fill + * block in the loader file */ +#define ANOMALY_05000140 /* Allowing the SPORT RX FIFO to fill will cause an + * overflow */ +#define ANOMALY_05000141 /* An Infinite Stall occurs with a particular sequence + * of consecutive dual dag events */ +#define ANOMALY_05000142 /* Interrupts may be lost when a programmable input + * flag is configured to be edge sensitive */ +#define ANOMALY_05000143 /* A read from external memory may return a wrong + * value with data cache enabled */ +#define ANOMALY_05000144 /* DMA and TESTSET conflict when both are accessing + * external memory */ +#define ANOMALY_05000145 /* In PWM_OUT mode, you must enable the PPI block to + * generate a waveform from PPI_CLK */ +#define ANOMALY_05000146 /* MDMA may lose the first few words of a descriptor + * chain */ +#define ANOMALY_05000147 /* The source MDMA descriptor may stop with a DMA + * Error */ +#define ANOMALY_05000148 /* When booting from a 16-bit asynchronous memory + * device, the upper 8-bits of each word must be + * 0x00 */ +#define ANOMALY_05000153 /* Frame Delay in SPORT Multichannel Mode */ +#define ANOMALY_05000154 /* SPORT TFS signal is active in Multi-channel mode + * outside of valid channels */ +#define ANOMALY_05000155 /* Timer1 can not be used for PWMOUT mode when a + * certain PPI mode is in use */ +#define ANOMALY_05000157 /* A killed 32-bit System MMR write will lead to + * the next system MMR access thinking it should be + * 32-bit. */ +#define ANOMALY_05000163 /* SPORT transmit data is not gated by external frame + * sync in certain conditions */ +#define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */ +#define ANOMALY_05000169 /* DATA CPLB page miss can result in lost + * write-through cache data writes */ +#define ANOMALY_05000173 /* DMA vs Core accesses to external memory */ +#define ANOMALY_05000174 /* Cache Fill Buffer Data lost */ +#define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */ +#define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an + * accumulator saturation */ +#define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration + * registers */ +#define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */ +#define ANOMALY_05000191 /* PPI does not invert the Driving PPICLK edge in + * Transmit Modes */ +#define ANOMALY_05000192 /* In PPI Transmit Modes with External Frame Syncs + * POLC */ +#define ANOMALY_05000206 /* Internal Voltage Regulator may not start up */ + #endif #endif /* _MACH_ANOMALY_H_ */ diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h index 23bf76aa345..e043cafa3c4 100644 --- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h @@ -78,6 +78,7 @@ struct bfin_serial_res { }; struct bfin_serial_res bfin_serial_resource[] = { + { 0xFFC00400, IRQ_UART_RX, #ifdef CONFIG_SERIAL_BFIN_DMA @@ -88,6 +89,7 @@ struct bfin_serial_res bfin_serial_resource[] = { CONFIG_UART0_CTS_PIN, CONFIG_UART0_RTS_PIN, #endif + } }; diff --git a/include/asm-blackfin/mach-bf533/dma.h b/include/asm-blackfin/mach-bf533/dma.h index bd9d5e94307..16c672c01d8 100644 --- a/include/asm-blackfin/mach-bf533/dma.h +++ b/include/asm-blackfin/mach-bf533/dma.h @@ -51,4 +51,7 @@ #define CH_MEM_STREAM1_DEST 10 /* TX */ #define CH_MEM_STREAM1_SRC 11 /* RX */ +extern int channel2irq(unsigned int channel); +extern struct dma_register *base_addr[]; + #endif diff --git a/include/asm-blackfin/mach-bf533/portmux.h b/include/asm-blackfin/mach-bf533/portmux.h new file mode 100644 index 00000000000..b88d7a03ee3 --- /dev/null +++ b/include/asm-blackfin/mach-bf533/portmux.h @@ -0,0 +1,65 @@ +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define P_PPI0_CLK (P_DONTCARE) +#define P_PPI0_FS1 (P_DONTCARE) +#define P_PPI0_FS2 (P_DONTCARE) +#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3)) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11)) +#define P_PPI0_D0 (P_DONTCARE) +#define P_PPI0_D1 (P_DONTCARE) +#define P_PPI0_D2 (P_DONTCARE) +#define P_PPI0_D3 (P_DONTCARE) +#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15)) +#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14)) +#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13)) +#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12)) + +#define P_SPORT1_TSCLK (P_DONTCARE) +#define P_SPORT1_RSCLK (P_DONTCARE) +#define P_SPORT0_TSCLK (P_DONTCARE) +#define P_SPORT0_RSCLK (P_DONTCARE) +#define P_UART0_RX (P_DONTCARE) +#define P_UART0_TX (P_DONTCARE) +#define P_SPORT1_DRSEC (P_DONTCARE) +#define P_SPORT1_RFS (P_DONTCARE) +#define P_SPORT1_DTPRI (P_DONTCARE) +#define P_SPORT1_DTSEC (P_DONTCARE) +#define P_SPORT1_TFS (P_DONTCARE) +#define P_SPORT1_DRPRI (P_DONTCARE) +#define P_SPORT0_DRSEC (P_DONTCARE) +#define P_SPORT0_RFS (P_DONTCARE) +#define P_SPORT0_DTPRI (P_DONTCARE) +#define P_SPORT0_DTSEC (P_DONTCARE) +#define P_SPORT0_TFS (P_DONTCARE) +#define P_SPORT0_DRPRI (P_DONTCARE) + +#define P_SPI0_MOSI (P_DONTCARE) +#define P_SPI0_MIS0 (P_DONTCARE) +#define P_SPI0_SCK (P_DONTCARE) +#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7)) +#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6)) +#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5)) +#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2)) +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1)) +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0)) + +#define P_TMR2 (P_DONTCARE) +#define P_TMR1 (P_DONTCARE) +#define P_TMR0 (P_DONTCARE) +#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF1)) + + + + + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h index 7f040f5ba01..4453e614c3b 100644 --- a/include/asm-blackfin/mach-bf537/anomaly.h +++ b/include/asm-blackfin/mach-bf537/anomaly.h @@ -73,8 +73,13 @@ control */ #define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when killed in a particular stage*/ +#define ANOMALY_05000310 /* False hardware errors caused by fetches at the + * boundary of reserved memory */ #define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC registers are interrupted */ +#define ANOMALY_05000313 /* PPI is level sensitive on first transfer */ +#define ANOMALY_05000322 /* EMAC RMII mode at 10-Base-T speed: RX frames not + * received properly */ #endif #if defined(CONFIG_BF_REV_0_2) @@ -114,7 +119,21 @@ DMA system instability */ #define ANOMALY_05000280 /* SPI Master boot mode does not work well with Atmel Dataflash devices */ - +#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context + * is not restored */ +#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic + * control */ +#define ANOMALY_05000283 /* System MMR Write Is Stalled Indefinitely When + * Killed in a Particular Stage */ +#define ANOMALY_05000285 /* New Feature: EMAC TX DMA Word Alignment + * (Not Available On Older Silicon) */ +#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */ +#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously + * On Next System MMR Access */ +#define ANOMALY_05000316 /* EMAC RMII mode: collisions occur in Full Duplex + * mode */ +#define ANOMALY_05000321 /* EMAC RMII mode: TX frames in half duplex fail with + * status No Carrier */ #endif /* CONFIG_BF_REV_0_2 */ #endif /* _MACH_ANOMALY_H_ */ diff --git a/include/asm-blackfin/mach-bf537/dma.h b/include/asm-blackfin/mach-bf537/dma.h index 7a964040870..021991984e6 100644 --- a/include/asm-blackfin/mach-bf537/dma.h +++ b/include/asm-blackfin/mach-bf537/dma.h @@ -52,4 +52,7 @@ #define CH_MEM_STREAM1_DEST 14 /* TX */ #define CH_MEM_STREAM1_SRC 15 /* RX */ +extern int channel2irq(unsigned int channel); +extern struct dma_register *base_addr[]; + #endif diff --git a/include/asm-blackfin/mach-bf537/portmux.h b/include/asm-blackfin/mach-bf537/portmux.h new file mode 100644 index 00000000000..23e13c5abc4 --- /dev/null +++ b/include/asm-blackfin/mach-bf537/portmux.h @@ -0,0 +1,109 @@ +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) +#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) +#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) +#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0)) +#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0)) +#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0)) +#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0)) +#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0)) +#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0)) +#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0)) +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0)) +#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0)) +#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0)) +#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0)) +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0)) +#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0)) +#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1)) +#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1)) +#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1)) +#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1)) +#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1)) +#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1)) +#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1)) +#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1)) +#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1)) +#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) +#define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) +#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) + +#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) +#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) +#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0)) +#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0)) +#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0)) +#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) +#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0)) +#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0)) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) +#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1)) +#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1)) +#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1)) +#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1)) +#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1)) +#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1)) +#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1)) +#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1)) + +#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0)) +#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0)) +#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0)) +#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0)) +#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0)) +#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0)) +#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0)) +#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0)) +#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0)) +#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0)) +#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0)) +#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0)) +#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0)) +#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0)) +#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0)) +#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0)) +#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1)) +#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1)) +#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1)) + +#define PORT_PJ0 (GPIO_PH15 + 1) +#define PORT_PJ1 (GPIO_PH15 + 2) +#define PORT_PJ2 (GPIO_PH15 + 3) +#define PORT_PJ3 (GPIO_PH15 + 4) +#define PORT_PJ4 (GPIO_PH15 + 5) +#define PORT_PJ5 (GPIO_PH15 + 6) +#define PORT_PJ6 (GPIO_PH15 + 7) +#define PORT_PJ7 (GPIO_PH15 + 8) +#define PORT_PJ8 (GPIO_PH15 + 9) +#define PORT_PJ9 (GPIO_PH15 + 10) +#define PORT_PJ10 (GPIO_PH15 + 11) +#define PORT_PJ11 (GPIO_PH15 + 12) + +#define P_MDC (P_DEFINED | P_IDENT(PORT_PJ0) | P_FUNCT(0)) +#define P_MDIO (P_DEFINED | P_IDENT(PORT_PJ1) | P_FUNCT(0)) +#define P_TWI0_SCL (P_DEFINED | P_IDENT(PORT_PJ2) | P_FUNCT(0)) +#define P_TWI0_SDA (P_DEFINED | P_IDENT(PORT_PJ3) | P_FUNCT(0)) +#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(0)) +#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(0)) +#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(PORT_PJ6) | P_FUNCT(0)) +#define P_SPORT0_RFS (P_DEFINED | P_IDENT(PORT_PJ7) | P_FUNCT(0)) +#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0)) +#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0)) +#define P_SPORT0_TFS (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0)) +#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1)) +#define P_CAN0_RX (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1)) +#define P_CAN0_TX (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1)) +#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(2)) + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h new file mode 100644 index 00000000000..aca1d4ba145 --- /dev/null +++ b/include/asm-blackfin/mach-bf548/anomaly.h @@ -0,0 +1,74 @@ + +/* + * File: include/asm-blackfin/mach-bf548/anomaly.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef _MACH_ANOMALY_H_ +#define _MACH_ANOMALY_H_ +#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in + slot1 and store of a P register in slot 2 is not + supported */ +#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive + Channel DMA stops */ +#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR + registers. */ +#define ANOMALY_05000245 /* Spurious Hardware Error from an Access in the + Shadow of a Conditional Branch */ +#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event + interrupt not functional */ +#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on + SPORT external receive and transmit clocks. */ +#define ANOMALY_05000272 /* Certain data cache write through modes fail for + VDDint <=0.9V */ +#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is + not restored */ +#define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the + Boundary of Reserved Memory */ +#define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and + LC Registers Are Interrupted */ +#define ANOMALY_05000324 /* TWI Slave Boot Mode Is Not Functional */ +#define ANOMALY_05000325 /* External FIFO Boot Mode Is Not Functional */ +#define ANOMALY_05000327 /* Data Lost When Core and DMA Accesses Are Made to + the USB FIFO Simultaneously */ +#define ANOMALY_05000328 /* Incorrect Access of OTP_STATUS During otp_write() + function */ +#define ANOMALY_05000329 /* Synchronous Burst Flash Boot Mode Is Not Functional + */ +#define ANOMALY_05000330 /* Host DMA Boot Mode Is Not Functional */ +#define ANOMALY_05000334 /* Inadequate Timing Margins on DDR DQS to DQ and DQM + Skew */ +#define ANOMALY_05000335 /* Inadequate Rotary Debounce Logic Duration */ +#define ANOMALY_05000336 /* Phantom Interrupt Occurs After First Configuration + of Host DMA Port */ +#define ANOMALY_05000337 /* Disallowed Configuration Prevents Subsequent + Allowed Configuration on Host DMA Port */ +#define ANOMALY_05000338 /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ + +#endif /* _MACH_ANOMALY_H_ */ diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h new file mode 100644 index 00000000000..9498313a2cb --- /dev/null +++ b/include/asm-blackfin/mach-bf548/bf548.h @@ -0,0 +1,271 @@ +/* + * File: include/asm-blackfin/mach-bf548/bf548.h + * Based on: + * Author: + * + * Created: + * Description: System MMR register and memory map for ADSP-BF548 + * + * Modified: + * Copyright 2004-2007 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MACH_BF548_H__ +#define __MACH_BF548_H__ + +#define SUPPORTED_REVID 0 + +#define OFFSET_(x) ((x) & 0x0000FFFF) + +/*some misc defines*/ +#define IMASK_IVG15 0x8000 +#define IMASK_IVG14 0x4000 +#define IMASK_IVG13 0x2000 +#define IMASK_IVG12 0x1000 + +#define IMASK_IVG11 0x0800 +#define IMASK_IVG10 0x0400 +#define IMASK_IVG9 0x0200 +#define IMASK_IVG8 0x0100 + +#define IMASK_IVG7 0x0080 +#define IMASK_IVGTMR 0x0040 +#define IMASK_IVGHW 0x0020 + +/***************************/ + + +#define BLKFIN_DSUBBANKS 4 +#define BLKFIN_DWAYS 2 +#define BLKFIN_DLINES 64 +#define BLKFIN_ISUBBANKS 4 +#define BLKFIN_IWAYS 4 +#define BLKFIN_ILINES 32 + +#define WAY0_L 0x1 +#define WAY1_L 0x2 +#define WAY01_L 0x3 +#define WAY2_L 0x4 +#define WAY02_L 0x5 +#define WAY12_L 0x6 +#define WAY012_L 0x7 + +#define WAY3_L 0x8 +#define WAY03_L 0x9 +#define WAY13_L 0xA +#define WAY013_L 0xB + +#define WAY32_L 0xC +#define WAY320_L 0xD +#define WAY321_L 0xE +#define WAYALL_L 0xF + +#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */ + +/********************************* EBIU Settings ************************************/ +#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0) +#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2) + +#ifdef CONFIG_C_AMBEN_ALL +#define V_AMBEN AMBEN_ALL +#endif +#ifdef CONFIG_C_AMBEN +#define V_AMBEN 0x0 +#endif +#ifdef CONFIG_C_AMBEN_B0 +#define V_AMBEN AMBEN_B0 +#endif +#ifdef CONFIG_C_AMBEN_B0_B1 +#define V_AMBEN AMBEN_B0_B1 +#endif +#ifdef CONFIG_C_AMBEN_B0_B1_B2 +#define V_AMBEN AMBEN_B0_B1_B2 +#endif +#ifdef CONFIG_C_AMCKEN +#define V_AMCKEN AMCKEN +#else +#define V_AMCKEN 0x0 +#endif + +#define AMGCTLVAL (V_AMBEN | V_AMCKEN) + +#define MAX_VC 650000000 +#define MIN_VC 50000000 + +/********************************PLL Settings **************************************/ +#ifdef CONFIG_BFIN_KERNEL_CLOCK +#if (CONFIG_VCO_MULT < 0) +#error "VCO Multiplier is less than 0. Please select a different value" +#endif + +#if (CONFIG_VCO_MULT == 0) +#error "VCO Multiplier should be greater than 0. Please select a different value" +#endif + +#if (CONFIG_VCO_MULT > 64) +#error "VCO Multiplier is more than 64. Please select a different value" +#endif + +#ifndef CONFIG_CLKIN_HALF +#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) +#else +#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2) +#endif + +#ifndef CONFIG_PLL_BYPASS +#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV) +#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV) +#else +#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ +#endif + +#if (CONFIG_SCLK_DIV < 1) +#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" +#endif + +#if (CONFIG_SCLK_DIV > 15) +#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value" +#endif + +#if (CONFIG_CCLK_DIV != 1) +#if (CONFIG_CCLK_DIV != 2) +#if (CONFIG_CCLK_DIV != 4) +#if (CONFIG_CCLK_DIV != 8) +#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value" +#endif +#endif +#endif +#endif + +#if (CONFIG_VCO_HZ > MAX_VC) +#error "VCO selected is more than maximum value. Please change the VCO multipler" +#endif + +#if (CONFIG_SCLK_HZ > 133000000) +#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier" +#endif + +#if (CONFIG_SCLK_HZ < 27000000) +#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier" +#endif + +#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ) +#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) +#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ) +#error "Please select sclk less than cclk" +#endif +#endif +#endif + +#if (CONFIG_CCLK_DIV == 1) +#define CONFIG_CCLK_ACT_DIV CCLK_DIV1 +#endif +#if (CONFIG_CCLK_DIV == 2) +#define CONFIG_CCLK_ACT_DIV CCLK_DIV2 +#endif +#if (CONFIG_CCLK_DIV == 4) +#define CONFIG_CCLK_ACT_DIV CCLK_DIV4 +#endif +#if (CONFIG_CCLK_DIV == 8) +#define CONFIG_CCLK_ACT_DIV CCLK_DIV8 +#endif +#ifndef CONFIG_CCLK_ACT_DIV +#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly +#endif + +#endif /* CONFIG_BFIN_KERNEL_CLOCK */ + +#ifdef CONFIG_BF542 +#define CPU "BF542" +#define CPUID 0x027c8000 +#endif +#ifdef CONFIG_BF544 +#define CPU "BF544" +#define CPUID 0x027c8000 +#endif +#ifdef CONFIG_BF548 +#define CPU "BF548" +#define CPUID 0x027c6000 +#endif +#ifdef CONFIG_BF549 +#define CPU "BF549" +#endif +#ifndef CPU +#define CPU "UNKNOWN" +#define CPUID 0x0 +#endif + +#if (CONFIG_MEM_SIZE % 4) +#error "SDRAM mem size must be multible of 4MB" +#endif + +#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) +#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK) +#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) + +/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ + +#define ANOMALY_05000158_WORKAROUND 0x200 +#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ +#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \ + | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#else /*Write Through */ +#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \ + | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) +#endif + + +#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY ) +#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) +#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY ) +#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY ) + +#define SIZE_1K 0x00000400 /* 1K */ +#define SIZE_4K 0x00001000 /* 4K */ +#define SIZE_1M 0x00100000 /* 1M */ +#define SIZE_4M 0x00400000 /* 4M */ + +#define MAX_CPLBS (16 * 2) + +/* +* Number of required data CPLB switchtable entries +* MEMSIZE / 4 (we mostly install 4M page size CPLBs +* approx 16 for smaller 1MB page size CPLBs for allignment purposes +* 1 for L1 Data Memory +* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO +* 1 for ASYNC Memory +*/ + + +#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2) + +/* +* Number of required instruction CPLB switchtable entries +* MEMSIZE / 4 (we mostly install 4M page size CPLBs +* approx 12 for smaller 1MB page size CPLBs for allignment purposes +* 1 for L1 Instruction Memory +* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO +*/ + +#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2) + +#endif /* __MACH_BF48_H__ */ diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h new file mode 100644 index 00000000000..2f4afc90db1 --- /dev/null +++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h @@ -0,0 +1,193 @@ +#include <linux/serial.h> +#include <asm/dma.h> + +#define NR_PORTS 4 + +#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ +#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ +#define OFFSET_GCTL 0x08 /* Global Control Register */ +#define OFFSET_LCR 0x0C /* Line Control Register */ +#define OFFSET_MCR 0x10 /* Modem Control Register */ +#define OFFSET_LSR 0x14 /* Line Status Register */ +#define OFFSET_MSR 0x18 /* Modem Status Register */ +#define OFFSET_SCR 0x1C /* SCR Scratch Register */ +#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */ +#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */ +#define OFFSET_THR 0x28 /* Transmit Holding register */ +#define OFFSET_RBR 0x2C /* Receive Buffer register */ + +#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) +#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) +#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) +#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER_SET)) +#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) +#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR)) +#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) + +#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) +#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) +#define UART_SET_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v) +#define UART_CLEAR_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v) +#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) +#define UART_PUT_LSR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LSR),v) +#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) +#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) + +#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) +# define CONFIG_SERIAL_BFIN_CTSRTS + +# ifndef CONFIG_UART0_CTS_PIN +# define CONFIG_UART0_CTS_PIN -1 +# endif + +# ifndef CONFIG_UART0_RTS_PIN +# define CONFIG_UART0_RTS_PIN -1 +# endif + +# ifndef CONFIG_UART1_CTS_PIN +# define CONFIG_UART1_CTS_PIN -1 +# endif + +# ifndef CONFIG_UART1_RTS_PIN +# define CONFIG_UART1_RTS_PIN -1 +# endif +#endif +/* + * The pin configuration is different from schematic + */ +struct bfin_serial_port { + struct uart_port port; + unsigned int old_status; +#ifdef CONFIG_SERIAL_BFIN_DMA + int tx_done; + int tx_count; + struct circ_buf rx_dma_buf; + struct timer_list rx_dma_timer; + int rx_dma_nrows; + unsigned int tx_dma_channel; + unsigned int rx_dma_channel; + struct work_struct tx_dma_workqueue; +#else + struct work_struct cts_workqueue; +#endif +#ifdef CONFIG_SERIAL_BFIN_CTSRTS + int cts_pin; + int rts_pin; +#endif +}; + +struct bfin_serial_port bfin_serial_ports[NR_PORTS]; +struct bfin_serial_res { + unsigned long uart_base_addr; + int uart_irq; +#ifdef CONFIG_SERIAL_BFIN_DMA + unsigned int uart_tx_dma_channel; + unsigned int uart_rx_dma_channel; +#endif +#ifdef CONFIG_SERIAL_BFIN_CTSRTS + int uart_cts_pin; + int uart_rts_pin; +#endif +}; + +struct bfin_serial_res bfin_serial_resource[] = { +#ifdef CONFIG_SERIAL_BFIN_UART0 + { + 0xFFC00400, + IRQ_UART0_RX, +#ifdef CONFIG_SERIAL_BFIN_DMA + CH_UART0_TX, + CH_UART0_RX, +#endif +#ifdef CONFIG_BFIN_UART0_CTSRTS + CONFIG_UART0_CTS_PIN, + CONFIG_UART0_RTS_PIN, +#endif + }, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 + { + 0xFFC02000, + IRQ_UART1_RX, +#ifdef CONFIG_SERIAL_BFIN_DMA + CH_UART1_TX, + CH_UART1_RX, +#endif + }, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART2 + { + 0xFFC02100, + IRQ_UART2_RX, +#ifdef CONFIG_SERIAL_BFIN_DMA + CH_UART2_TX, + CH_UART2_RX, +#endif +#ifdef CONFIG_BFIN_UART2_CTSRTS + CONFIG_UART2_CTS_PIN, + CONFIG_UART2_RTS_PIN, +#endif + }, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART3 + { + 0xFFC03100, + IRQ_UART3_RX, +#ifdef CONFIG_SERIAL_BFIN_DMA + CH_UART3_TX, + CH_UART3_RX, +#endif + }, +#endif +}; + +int nr_ports = ARRAY_SIZE(bfin_serial_resource); + +static void bfin_serial_hw_init(struct bfin_serial_port *uart) +{ +#ifdef CONFIG_SERIAL_BFIN_UART0 + /* Enable UART0 RX and TX on pin 7 & 8 of PORT E */ + bfin_write_PORTE_FER(0x180 | bfin_read_PORTE_FER()); + bfin_write_PORTE_MUX(0x3C000 | bfin_read_PORTE_MUX()); +#endif + +#ifdef CONFIG_SERIAL_BFIN_UART1 + /* Enable UART1 RX and TX on pin 0 & 1 of PORT H */ + bfin_write_PORTH_FER(0x3 | bfin_read_PORTH_FER()); + bfin_write_PORTH_MUX(~0xF & bfin_read_PORTH_MUX()); +#ifdef CONFIG_BFIN_UART1_CTSRTS + /* Enable UART1 RTS and CTS on pin 9 & 10 of PORT E */ + bfin_write_PORTE_FER(0x600 | bfin_read_PORTE_FER()); + bfin_write_PORTE_MUX(~0x3C0000 & bfin_read_PORTE_MUX()); +#endif +#endif + +#ifdef CONFIG_SERIAL_BFIN_UART2 + /* Enable UART2 RX and TX on pin 4 & 5 of PORT B */ + bfin_write_PORTB_FER(0x30 | bfin_read_PORTB_FER()); + bfin_write_PORTB_MUX(~0xF00 & bfin_read_PORTB_MUX()); +#endif + +#ifdef CONFIG_SERIAL_BFIN_UART3 + /* Enable UART3 RX and TX on pin 6 & 7 of PORT B */ + bfin_write_PORTB_FER(0xC0 | bfin_read_PORTB_FER()); + bfin_write_PORTB_MUX(~0xF000 | bfin_read_PORTB_MUX()); +#ifdef CONFIG_BFIN_UART3_CTSRTS + /* Enable UART3 RTS and CTS on pin 2 & 3 of PORT B */ + bfin_write_PORTB_FER(0xC | bfin_read_PORTB_FER()); + bfin_write_PORTB_MUX(~0xF0 | bfin_read_PORTB_MUX()); +#endif +#endif + SSYNC(); +#ifdef CONFIG_SERIAL_BFIN_CTSRTS + if (uart->cts_pin >= 0) { + gpio_request(uart->cts_pin, NULL); + gpio_direction_input(uart->cts_pin); + } + + if (uart->rts_pin >= 0) { + gpio_request(uart->rts_pin, NULL); + gpio_direction_output(uart->rts_pin); + } +#endif +} diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h new file mode 100644 index 00000000000..791218fe7d9 --- /dev/null +++ b/include/asm-blackfin/mach-bf548/blackfin.h @@ -0,0 +1,168 @@ +/* + * File: include/asm-blackfin/mach-bf548/blackfin.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef _MACH_BLACKFIN_H_ +#define _MACH_BLACKFIN_H_ + +#define BF548_FAMILY + +#include "bf548.h" +#include "mem_map.h" +#include "anomaly.h" + +#ifdef CONFIG_BF542 +#include "defBF542.h" +#endif + +#ifdef CONFIG_BF544 +#include "defBF544.h" +#endif + +#ifdef CONFIG_BF548 +#include "defBF548.h" +#endif + +#ifdef CONFIG_BF549 +#include "defBF549.h" +#endif + +#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY)) +#ifdef CONFIG_BF542 +#include "cdefBF542.h" +#endif + +#ifdef CONFIG_BF544 +#include "cdefBF544.h" +#endif +#ifdef CONFIG_BF548 +#include "cdefBF548.h" +#endif +#ifdef CONFIG_BF549 +#include "cdefBF549.h" +#endif + +/* UART 1*/ +#define bfin_read_UART_THR() bfin_read_UART1_THR() +#define bfin_write_UART_THR(val) bfin_write_UART1_THR(val) +#define bfin_read_UART_RBR() bfin_read_UART1_RBR() +#define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val) +#define bfin_read_UART_DLL() bfin_read_UART1_DLL() +#define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val) +#define bfin_read_UART_IER() bfin_read_UART1_IER() +#define bfin_write_UART_IER(val) bfin_write_UART1_IER(val) +#define bfin_read_UART_DLH() bfin_read_UART1_DLH() +#define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val) +#define bfin_read_UART_IIR() bfin_read_UART1_IIR() +#define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val) +#define bfin_read_UART_LCR() bfin_read_UART1_LCR() +#define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val) +#define bfin_read_UART_MCR() bfin_read_UART1_MCR() +#define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val) +#define bfin_read_UART_LSR() bfin_read_UART1_LSR() +#define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val) +#define bfin_read_UART_SCR() bfin_read_UART1_SCR() +#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val) +#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL() +#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val) + +#endif + +/* MAP used DEFINES from BF533 to BF54x - so we don't need to change + * them in the driver, kernel, etc. */ + +/* UART_IIR Register */ +#define STATUS(x) ((x << 1) & 0x06) +#define STATUS_P1 0x02 +#define STATUS_P0 0x01 + +/* UART 0*/ + +/* DMA Channnel */ +#define bfin_read_CH_UART_RX() bfin_read_CH_UART1_RX() +#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART1_RX(val) +#define bfin_read_CH_UART_TX() bfin_read_CH_UART1_TX() +#define bfin_write_CH_UART_TX(val) bfin_write_CH_UART1_TX(val) +#define CH_UART_RX CH_UART1_RX +#define CH_UART_TX CH_UART1_TX + +/* System Interrupt Controller */ +#define bfin_read_IRQ_UART_RX() bfin_read_IRQ_UART1_RX() +#define bfin_write_IRQ_UART_RX(val) bfin_write_IRQ_UART1_RX(val) +#define bfin_read_IRQ_UART_TX() bfin_read_IRQ_UART1_TX() +#define bfin_write_IRQ_UART_TX(val) bfin_write_IRQ_UART1_TX(val) +#define bfin_read_IRQ_UART_ERROR() bfin_read_IRQ_UART1_ERROR() +#define bfin_write_IRQ_UART_ERROR(val) bfin_write_IRQ_UART1_ERROR(val) +#define IRQ_UART_RX IRQ_UART1_RX +#define IRQ_UART_TX IRQ_UART1_TX +#define IRQ_UART_ERROR IRQ_UART1_ERROR + +/* MMR Registers*/ +#define bfin_read_UART_THR() bfin_read_UART1_THR() +#define bfin_write_UART_THR(val) bfin_write_UART1_THR(val) +#define bfin_read_UART_RBR() bfin_read_UART1_RBR() +#define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val) +#define bfin_read_UART_DLL() bfin_read_UART1_DLL() +#define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val) +#define bfin_read_UART_IER() bfin_read_UART1_IER() +#define bfin_write_UART_IER(val) bfin_write_UART1_IER(val) +#define bfin_read_UART_DLH() bfin_read_UART1_DLH() +#define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val) +#define bfin_read_UART_IIR() bfin_read_UART1_IIR() +#define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val) +#define bfin_read_UART_LCR() bfin_read_UART1_LCR() +#define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val) +#define bfin_read_UART_MCR() bfin_read_UART1_MCR() +#define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val) +#define bfin_read_UART_LSR() bfin_read_UART1_LSR() +#define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val) +#define bfin_read_UART_SCR() bfin_read_UART1_SCR() +#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val) +#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL() +#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val) +#define UART_THR UART1_THR +#define UART_RBR UART1_RBR +#define UART_DLL UART1_DLL +#define UART_IER UART1_IER +#define UART_DLH UART1_DLH +#define UART_IIR UART1_IIR +#define UART_LCR UART1_LCR +#define UART_MCR UART1_MCR +#define UART_LSR UART1_LSR +#define UART_SCR UART1_SCR +#define UART_GCTL UART1_GCTL + +/* PLL_DIV Masks */ +#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ +#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ +#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */ +#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */ + +#endif diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h index 6bbcefeb362..98d35a92911 100644 --- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h @@ -31,7 +31,8 @@ #ifndef _CDEF_BF54X_H #define _CDEF_BF54X_H -#include <defBF54x_base.h> +#include "defBF54x_base.h" +#include <asm/system.h> /* ************************************************************** */ /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ @@ -44,7 +45,30 @@ #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) #define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) +/* Writing to VR_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_VR_CTL(unsigned int val) +{ + unsigned long flags, iwr0, iwr1, iwr2; + + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr0 = bfin_read32(SIC_IWR0); + iwr1 = bfin_read32(SIC_IWR1); + iwr2 = bfin_read32(SIC_IWR2); + /* Only allow PPL Wakeup) */ + bfin_write32(SIC_IWR0, IWR_ENABLE(0)); + bfin_write32(SIC_IWR1, 0); + bfin_write32(SIC_IWR2, 0); + + bfin_write16(VR_CTL, val); + __builtin_bfin_ssync(); + + local_irq_save(flags); + asm("IDLE;"); + local_irq_restore(flags); + bfin_write32(SIC_IWR0, iwr0); + bfin_write32(SIC_IWR1, iwr1); + bfin_write32(SIC_IWR2, iwr2); +} #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) @@ -70,12 +94,18 @@ #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) #define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2) #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) +#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 2)) +#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 2)), val) + #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) #define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2) #define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) +#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 2)) +#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val) + #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) #define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) @@ -710,21 +740,21 @@ #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR) #define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR) +#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) #define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) #define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) #define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY) +#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) #define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) #define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY) +#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) -#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR) +#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val) #define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) -#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR) +#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val) #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) @@ -734,23 +764,23 @@ #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR) +#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val) #define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR) +#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val) #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) #define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) #define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY) +#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) #define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) #define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY) +#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) -#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR) +#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val) #define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) -#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR) +#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val) #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) @@ -763,9 +793,9 @@ /* MDMA Stream 1 Registers */ #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR) +#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val) #define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) -#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR) +#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val) #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) #define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) @@ -777,9 +807,9 @@ #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY) #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) -#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR) +#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) #define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) -#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR) +#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val) #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) @@ -789,9 +819,9 @@ #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR) +#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val) #define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) -#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR) +#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val) #define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) #define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) @@ -803,9 +833,9 @@ #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY) #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) -#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR) +#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) #define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) -#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR) +#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val) #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) diff --git a/include/asm-blackfin/mach-bf548/defBF542.h b/include/asm-blackfin/mach-bf548/defBF542.h index ac968fca5cc..32d07130200 100644 --- a/include/asm-blackfin/mach-bf548/defBF542.h +++ b/include/asm-blackfin/mach-bf548/defBF542.h @@ -362,7 +362,6 @@ /* Bit masks for KPAD_CTL */ #define KPAD_EN 0x1 /* Keypad Enable */ -#define nKPAD_EN 0x0 #define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ #define KPAD_ROWEN 0x1c00 /* Row Enable Width */ #define KPAD_COLEN 0xe000 /* Column Enable Width */ @@ -384,29 +383,21 @@ /* Bit masks for KPAD_STAT */ #define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ -#define nKPAD_IRQ 0x0 #define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ #define KPAD_PRESSED 0x8 /* Key press current status */ -#define nKPAD_PRESSED 0x0 /* Bit masks for KPAD_SOFTEVAL */ #define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ -#define nKPAD_SOFTEVAL_E 0x0 /* Bit masks for SDH_COMMAND */ #define CMD_IDX 0x3f /* Command Index */ #define CMD_RSP 0x40 /* Response */ -#define nCMD_RSP 0x0 #define CMD_L_RSP 0x80 /* Long Response */ -#define nCMD_L_RSP 0x0 #define CMD_INT_E 0x100 /* Command Interrupt */ -#define nCMD_INT_E 0x0 #define CMD_PEND_E 0x200 /* Command Pending */ -#define nCMD_PEND_E 0x0 #define CMD_E 0x400 /* Command Enable */ -#define nCMD_E 0x0 /* Bit masks for SDH_PWR_CTL */ @@ -415,21 +406,15 @@ #define TBD 0x3c /* TBD */ #endif #define SD_CMD_OD 0x40 /* Open Drain Output */ -#define nSD_CMD_OD 0x0 #define ROD_CTL 0x80 /* Rod Control */ -#define nROD_CTL 0x0 /* Bit masks for SDH_CLK_CTL */ #define CLKDIV 0xff /* MC_CLK Divisor */ #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ -#define nCLK_E 0x0 #define PWR_SV_E 0x200 /* Power Save Enable */ -#define nPWR_SV_E 0x0 #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ -#define nCLKDIV_BYPASS 0x0 #define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ -#define nWIDE_BUS 0x0 /* Bit masks for SDH_RESP_CMD */ @@ -438,133 +423,74 @@ /* Bit masks for SDH_DATA_CTL */ #define DTX_E 0x1 /* Data Transfer Enable */ -#define nDTX_E 0x0 #define DTX_DIR 0x2 /* Data Transfer Direction */ -#define nDTX_DIR 0x0 #define DTX_MODE 0x4 /* Data Transfer Mode */ -#define nDTX_MODE 0x0 #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ -#define nDTX_DMA_E 0x0 #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ /* Bit masks for SDH_STATUS */ #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ -#define nCMD_CRC_FAIL 0x0 #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ -#define nDAT_CRC_FAIL 0x0 #define CMD_TIMEOUT 0x4 /* CMD Time Out */ -#define nCMD_TIMEOUT 0x0 #define DAT_TIMEOUT 0x8 /* Data Time Out */ -#define nDAT_TIMEOUT 0x0 #define TX_UNDERRUN 0x10 /* Transmit Underrun */ -#define nTX_UNDERRUN 0x0 #define RX_OVERRUN 0x20 /* Receive Overrun */ -#define nRX_OVERRUN 0x0 #define CMD_RESP_END 0x40 /* CMD Response End */ -#define nCMD_RESP_END 0x0 #define CMD_SENT 0x80 /* CMD Sent */ -#define nCMD_SENT 0x0 #define DAT_END 0x100 /* Data End */ -#define nDAT_END 0x0 #define START_BIT_ERR 0x200 /* Start Bit Error */ -#define nSTART_BIT_ERR 0x0 #define DAT_BLK_END 0x400 /* Data Block End */ -#define nDAT_BLK_END 0x0 #define CMD_ACT 0x800 /* CMD Active */ -#define nCMD_ACT 0x0 #define TX_ACT 0x1000 /* Transmit Active */ -#define nTX_ACT 0x0 #define RX_ACT 0x2000 /* Receive Active */ -#define nRX_ACT 0x0 #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ -#define nTX_FIFO_STAT 0x0 #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ -#define nRX_FIFO_STAT 0x0 #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ -#define nTX_FIFO_FULL 0x0 #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ -#define nRX_FIFO_FULL 0x0 #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ -#define nTX_FIFO_ZERO 0x0 #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ -#define nRX_DAT_ZERO 0x0 #define TX_DAT_RDY 0x100000 /* Transmit Data Available */ -#define nTX_DAT_RDY 0x0 #define RX_FIFO_RDY 0x200000 /* Receive Data Available */ -#define nRX_FIFO_RDY 0x0 /* Bit masks for SDH_STATUS_CLR */ #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ -#define nCMD_CRC_FAIL_STAT 0x0 #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ -#define nDAT_CRC_FAIL_STAT 0x0 #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ -#define nCMD_TIMEOUT_STAT 0x0 #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ -#define nDAT_TIMEOUT_STAT 0x0 #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ -#define nTX_UNDERRUN_STAT 0x0 #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ -#define nRX_OVERRUN_STAT 0x0 #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ -#define nCMD_RESP_END_STAT 0x0 #define CMD_SENT_STAT 0x80 /* CMD Sent Status */ -#define nCMD_SENT_STAT 0x0 #define DAT_END_STAT 0x100 /* Data End Status */ -#define nDAT_END_STAT 0x0 #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ -#define nSTART_BIT_ERR_STAT 0x0 #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ -#define nDAT_BLK_END_STAT 0x0 /* Bit masks for SDH_MASK0 */ #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ -#define nCMD_CRC_FAIL_MASK 0x0 #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ -#define nDAT_CRC_FAIL_MASK 0x0 #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ -#define nCMD_TIMEOUT_MASK 0x0 #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ -#define nDAT_TIMEOUT_MASK 0x0 #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ -#define nTX_UNDERRUN_MASK 0x0 #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ -#define nRX_OVERRUN_MASK 0x0 #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ -#define nCMD_RESP_END_MASK 0x0 #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ -#define nCMD_SENT_MASK 0x0 #define DAT_END_MASK 0x100 /* Data End Mask */ -#define nDAT_END_MASK 0x0 #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ -#define nSTART_BIT_ERR_MASK 0x0 #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ -#define nDAT_BLK_END_MASK 0x0 #define CMD_ACT_MASK 0x800 /* CMD Active Mask */ -#define nCMD_ACT_MASK 0x0 #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ -#define nTX_ACT_MASK 0x0 #define RX_ACT_MASK 0x2000 /* Receive Active Mask */ -#define nRX_ACT_MASK 0x0 #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ -#define nTX_FIFO_STAT_MASK 0x0 #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ -#define nRX_FIFO_STAT_MASK 0x0 #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ -#define nTX_FIFO_FULL_MASK 0x0 #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ -#define nRX_FIFO_FULL_MASK 0x0 #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ -#define nTX_FIFO_ZERO_MASK 0x0 #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ -#define nRX_DAT_ZERO_MASK 0x0 #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ -#define nTX_DAT_RDY_MASK 0x0 #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ -#define nRX_FIFO_RDY_MASK 0x0 /* Bit masks for SDH_FIFO_CNT */ @@ -573,73 +499,47 @@ /* Bit masks for SDH_E_STATUS */ #define SDIO_INT_DET 0x2 /* SDIO Int Detected */ -#define nSDIO_INT_DET 0x0 #define SD_CARD_DET 0x10 /* SD Card Detect */ -#define nSD_CARD_DET 0x0 /* Bit masks for SDH_E_MASK */ #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ -#define nSDIO_MSK 0x0 #define SCD_MSK 0x40 /* Mask Card Detect */ -#define nSCD_MSK 0x0 /* Bit masks for SDH_CFG */ #define CLKS_EN 0x1 /* Clocks Enable */ -#define nCLKS_EN 0x0 #define SD4E 0x4 /* SDIO 4-Bit Enable */ -#define nSD4E 0x0 #define MWE 0x8 /* Moving Window Enable */ -#define nMWE 0x0 #define SD_RST 0x10 /* SDMMC Reset */ -#define nSD_RST 0x0 #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ -#define nPUP_SDDAT 0x0 #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ -#define nPUP_SDDAT3 0x0 #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ -#define nPD_SDDAT3 0x0 /* Bit masks for SDH_RD_WAIT_EN */ #define RWR 0x1 /* Read Wait Request */ -#define nRWR 0x0 /* Bit masks for ATAPI_CONTROL */ #define PIO_START 0x1 /* Start PIO/Reg Op */ -#define nPIO_START 0x0 #define MULTI_START 0x2 /* Start Multi-DMA Op */ -#define nMULTI_START 0x0 #define ULTRA_START 0x4 /* Start Ultra-DMA Op */ -#define nULTRA_START 0x0 #define XFER_DIR 0x8 /* Transfer Direction */ -#define nXFER_DIR 0x0 #define IORDY_EN 0x10 /* IORDY Enable */ -#define nIORDY_EN 0x0 #define FIFO_FLUSH 0x20 /* Flush FIFOs */ -#define nFIFO_FLUSH 0x0 #define SOFT_RST 0x40 /* Soft Reset */ -#define nSOFT_RST 0x0 #define DEV_RST 0x80 /* Device Reset */ -#define nDEV_RST 0x0 #define TFRCNT_RST 0x100 /* Trans Count Reset */ -#define nTFRCNT_RST 0x0 #define END_ON_TERM 0x200 /* End/Terminate Select */ -#define nEND_ON_TERM 0x0 #define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ -#define nPIO_USE_DMA 0x0 #define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ /* Bit masks for ATAPI_STATUS */ #define PIO_XFER_ON 0x1 /* PIO transfer in progress */ -#define nPIO_XFER_ON 0x0 #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ -#define nMULTI_XFER_ON 0x0 #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ -#define nULTRA_XFER_ON 0x0 #define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ /* Bit masks for ATAPI_DEV_ADDR */ @@ -649,66 +549,39 @@ /* Bit masks for ATAPI_INT_MASK */ #define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ -#define nATAPI_DEV_INT_MASK 0x0 #define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ -#define nPIO_DONE_MASK 0x0 #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ -#define nMULTI_DONE_MASK 0x0 #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ -#define nUDMAIN_DONE_MASK 0x0 #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ -#define nUDMAOUT_DONE_MASK 0x0 #define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ -#define nHOST_TERM_XFER_MASK 0x0 #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ -#define nMULTI_TERM_MASK 0x0 #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ -#define nUDMAIN_TERM_MASK 0x0 #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ -#define nUDMAOUT_TERM_MASK 0x0 /* Bit masks for ATAPI_INT_STATUS */ #define ATAPI_DEV_INT 0x1 /* Device interrupt status */ -#define nATAPI_DEV_INT 0x0 #define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ -#define nPIO_DONE_INT 0x0 #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ -#define nMULTI_DONE_INT 0x0 #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ -#define nUDMAIN_DONE_INT 0x0 #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ -#define nUDMAOUT_DONE_INT 0x0 #define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ -#define nHOST_TERM_XFER_INT 0x0 #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ -#define nMULTI_TERM_INT 0x0 #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ -#define nUDMAIN_TERM_INT 0x0 #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ -#define nUDMAOUT_TERM_INT 0x0 /* Bit masks for ATAPI_LINE_STATUS */ #define ATAPI_INTR 0x1 /* Device interrupt to host line status */ -#define nATAPI_INTR 0x0 #define ATAPI_DASP 0x2 /* Device dasp to host line status */ -#define nATAPI_DASP 0x0 #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ -#define nATAPI_CS0N 0x0 #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ -#define nATAPI_CS1N 0x0 #define ATAPI_ADDR 0x70 /* ATAPI address line status */ #define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ -#define nATAPI_DMAREQ 0x0 #define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ -#define nATAPI_DMAACKN 0x0 #define ATAPI_DIOWN 0x200 /* ATAPI write line status */ -#define nATAPI_DIOWN 0x0 #define ATAPI_DIORN 0x400 /* ATAPI read line status */ -#define nATAPI_DIORN 0x0 #define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ -#define nATAPI_IORDY 0x0 /* Bit masks for ATAPI_SM_STATE */ @@ -720,7 +593,6 @@ /* Bit masks for ATAPI_TERMINATE */ #define ATAPI_HOST_TERM 0x1 /* Host terminationation */ -#define nATAPI_HOST_TERM 0x0 /* Bit masks for ATAPI_REG_TIM_0 */ @@ -779,131 +651,77 @@ /* Bit masks for USB_POWER */ #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ -#define nENABLE_SUSPENDM 0x0 #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ -#define nSUSPEND_MODE 0x0 #define RESUME_MODE 0x4 /* DMA Mode */ -#define nRESUME_MODE 0x0 #define RESET 0x8 /* Reset indicator */ -#define nRESET 0x0 #define HS_MODE 0x10 /* High Speed mode indicator */ -#define nHS_MODE 0x0 #define HS_ENABLE 0x20 /* high Speed Enable */ -#define nHS_ENABLE 0x0 #define SOFT_CONN 0x40 /* Soft connect */ -#define nSOFT_CONN 0x0 #define ISO_UPDATE 0x80 /* Isochronous update */ -#define nISO_UPDATE 0x0 /* Bit masks for USB_INTRTX */ #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ -#define nEP0_TX 0x0 #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ -#define nEP1_TX 0x0 #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ -#define nEP2_TX 0x0 #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ -#define nEP3_TX 0x0 #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ -#define nEP4_TX 0x0 #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ -#define nEP5_TX 0x0 #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ -#define nEP6_TX 0x0 #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ -#define nEP7_TX 0x0 /* Bit masks for USB_INTRRX */ #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ -#define nEP1_RX 0x0 #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ -#define nEP2_RX 0x0 #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ -#define nEP3_RX 0x0 #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ -#define nEP4_RX 0x0 #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ -#define nEP5_RX 0x0 #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ -#define nEP6_RX 0x0 #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ -#define nEP7_RX 0x0 /* Bit masks for USB_INTRTXE */ #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ -#define nEP0_TX_E 0x0 #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ -#define nEP1_TX_E 0x0 #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ -#define nEP2_TX_E 0x0 #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ -#define nEP3_TX_E 0x0 #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ -#define nEP4_TX_E 0x0 #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ -#define nEP5_TX_E 0x0 #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ -#define nEP6_TX_E 0x0 #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ -#define nEP7_TX_E 0x0 /* Bit masks for USB_INTRRXE */ #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ -#define nEP1_RX_E 0x0 #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ -#define nEP2_RX_E 0x0 #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ -#define nEP3_RX_E 0x0 #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ -#define nEP4_RX_E 0x0 #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ -#define nEP5_RX_E 0x0 #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ -#define nEP6_RX_E 0x0 #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ -#define nEP7_RX_E 0x0 /* Bit masks for USB_INTRUSB */ #define SUSPEND_B 0x1 /* Suspend indicator */ -#define nSUSPEND_B 0x0 #define RESUME_B 0x2 /* Resume indicator */ -#define nRESUME_B 0x0 #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ -#define nRESET_OR_BABLE_B 0x0 #define SOF_B 0x8 /* Start of frame */ -#define nSOF_B 0x0 #define CONN_B 0x10 /* Connection indicator */ -#define nCONN_B 0x0 #define DISCON_B 0x20 /* Disconnect indicator */ -#define nDISCON_B 0x0 #define SESSION_REQ_B 0x40 /* Session Request */ -#define nSESSION_REQ_B 0x0 #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ -#define nVBUS_ERROR_B 0x0 /* Bit masks for USB_INTRUSBE */ #define SUSPEND_BE 0x1 /* Suspend indicator int enable */ -#define nSUSPEND_BE 0x0 #define RESUME_BE 0x2 /* Resume indicator int enable */ -#define nRESUME_BE 0x0 #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ -#define nRESET_OR_BABLE_BE 0x0 #define SOF_BE 0x8 /* Start of frame int enable */ -#define nSOF_BE 0x0 #define CONN_BE 0x10 /* Connection indicator int enable */ -#define nCONN_BE 0x0 #define DISCON_BE 0x20 /* Disconnect indicator int enable */ -#define nDISCON_BE 0x0 #define SESSION_REQ_BE 0x40 /* Session Request int enable */ -#define nSESSION_REQ_BE 0x0 #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ -#define nVBUS_ERROR_BE 0x0 /* Bit masks for USB_FRAME */ @@ -916,117 +734,67 @@ /* Bit masks for USB_GLOBAL_CTL */ #define GLOBAL_ENA 0x1 /* enables USB module */ -#define nGLOBAL_ENA 0x0 #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ -#define nEP1_TX_ENA 0x0 #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ -#define nEP2_TX_ENA 0x0 #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ -#define nEP3_TX_ENA 0x0 #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ -#define nEP4_TX_ENA 0x0 #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ -#define nEP5_TX_ENA 0x0 #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ -#define nEP6_TX_ENA 0x0 #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ -#define nEP7_TX_ENA 0x0 #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ -#define nEP1_RX_ENA 0x0 #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ -#define nEP2_RX_ENA 0x0 #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ -#define nEP3_RX_ENA 0x0 #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ -#define nEP4_RX_ENA 0x0 #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ -#define nEP5_RX_ENA 0x0 #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ -#define nEP6_RX_ENA 0x0 #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ -#define nEP7_RX_ENA 0x0 /* Bit masks for USB_OTG_DEV_CTL */ #define SESSION 0x1 /* session indicator */ -#define nSESSION 0x0 #define HOST_REQ 0x2 /* Host negotiation request */ -#define nHOST_REQ 0x0 #define HOST_MODE 0x4 /* indicates USBDRC is a host */ -#define nHOST_MODE 0x0 #define VBUS0 0x8 /* Vbus level indicator[0] */ -#define nVBUS0 0x0 #define VBUS1 0x10 /* Vbus level indicator[1] */ -#define nVBUS1 0x0 #define LSDEV 0x20 /* Low-speed indicator */ -#define nLSDEV 0x0 #define FSDEV 0x40 /* Full or High-speed indicator */ -#define nFSDEV 0x0 #define B_DEVICE 0x80 /* A' or 'B' device indicator */ -#define nB_DEVICE 0x0 /* Bit masks for USB_OTG_VBUS_IRQ */ #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ -#define nDRIVE_VBUS_ON 0x0 #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ -#define nDRIVE_VBUS_OFF 0x0 #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ -#define nCHRG_VBUS_START 0x0 #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ -#define nCHRG_VBUS_END 0x0 #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ -#define nDISCHRG_VBUS_START 0x0 #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ -#define nDISCHRG_VBUS_END 0x0 /* Bit masks for USB_OTG_VBUS_MASK */ #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ -#define nDRIVE_VBUS_ON_ENA 0x0 #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ -#define nDRIVE_VBUS_OFF_ENA 0x0 #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ -#define nCHRG_VBUS_START_ENA 0x0 #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ -#define nCHRG_VBUS_END_ENA 0x0 #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ -#define nDISCHRG_VBUS_START_ENA 0x0 #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ -#define nDISCHRG_VBUS_END_ENA 0x0 /* Bit masks for USB_CSR0 */ #define RXPKTRDY 0x1 /* data packet receive indicator */ -#define nRXPKTRDY 0x0 #define TXPKTRDY 0x2 /* data packet in FIFO indicator */ -#define nTXPKTRDY 0x0 #define STALL_SENT 0x4 /* STALL handshake sent */ -#define nSTALL_SENT 0x0 #define DATAEND 0x8 /* Data end indicator */ -#define nDATAEND 0x0 #define SETUPEND 0x10 /* Setup end */ -#define nSETUPEND 0x0 #define SENDSTALL 0x20 /* Send STALL handshake */ -#define nSENDSTALL 0x0 #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ -#define nSERVICED_RXPKTRDY 0x0 #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ -#define nSERVICED_SETUPEND 0x0 #define FLUSHFIFO 0x100 /* flush endpoint FIFO */ -#define nFLUSHFIFO 0x0 #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ -#define nSTALL_RECEIVED_H 0x0 #define SETUPPKT_H 0x8 /* send Setup token host mode */ -#define nSETUPPKT_H 0x0 #define ERROR_H 0x10 /* timeout error indicator host mode */ -#define nERROR_H 0x0 #define REQPKT_H 0x20 /* Request an IN transaction host mode */ -#define nREQPKT_H 0x0 #define STATUSPKT_H 0x40 /* Status stage transaction host mode */ -#define nSTATUSPKT_H 0x0 #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ -#define nNAK_TIMEOUT_H 0x0 /* Bit masks for USB_COUNT0 */ @@ -1047,37 +815,21 @@ /* Bit masks for USB_TXCSR */ #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ -#define nTXPKTRDY_T 0x0 #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ -#define nFIFO_NOT_EMPTY_T 0x0 #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ -#define nUNDERRUN_T 0x0 #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ -#define nFLUSHFIFO_T 0x0 #define STALL_SEND_T 0x10 /* issue a Stall handshake */ -#define nSTALL_SEND_T 0x0 #define STALL_SENT_T 0x20 /* Stall handshake transmitted */ -#define nSTALL_SENT_T 0x0 #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ -#define nCLEAR_DATATOGGLE_T 0x0 #define INCOMPTX_T 0x80 /* indicates that a large packet is split */ -#define nINCOMPTX_T 0x0 #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ -#define nDMAREQMODE_T 0x0 #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ -#define nFORCE_DATATOGGLE_T 0x0 #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ -#define nDMAREQ_ENA_T 0x0 #define ISO_T 0x4000 /* enable Isochronous transfers */ -#define nISO_T 0x0 #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ -#define nAUTOSET_T 0x0 #define ERROR_TH 0x4 /* error condition host mode */ -#define nERROR_TH 0x0 #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ -#define nSTALL_RECEIVED_TH 0x0 #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ -#define nNAK_TIMEOUT_TH 0x0 /* Bit masks for USB_TXCOUNT */ @@ -1086,45 +838,25 @@ /* Bit masks for USB_RXCSR */ #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ -#define nRXPKTRDY_R 0x0 #define FIFO_FULL_R 0x2 /* FIFO not empty */ -#define nFIFO_FULL_R 0x0 #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ -#define nOVERRUN_R 0x0 #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ -#define nDATAERROR_R 0x0 #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ -#define nFLUSHFIFO_R 0x0 #define STALL_SEND_R 0x20 /* issue a Stall handshake */ -#define nSTALL_SEND_R 0x0 #define STALL_SENT_R 0x40 /* Stall handshake transmitted */ -#define nSTALL_SENT_R 0x0 #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ -#define nCLEAR_DATATOGGLE_R 0x0 #define INCOMPRX_R 0x100 /* indicates that a large packet is split */ -#define nINCOMPRX_R 0x0 #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ -#define nDMAREQMODE_R 0x0 #define DISNYET_R 0x1000 /* disable Nyet handshakes */ -#define nDISNYET_R 0x0 #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ -#define nDMAREQ_ENA_R 0x0 #define ISO_R 0x4000 /* enable Isochronous transfers */ -#define nISO_R 0x0 #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ -#define nAUTOCLEAR_R 0x0 #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ -#define nERROR_RH 0x0 #define REQPKT_RH 0x20 /* request an IN transaction host mode */ -#define nREQPKT_RH 0x0 #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ -#define nSTALL_RECEIVED_RH 0x0 #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ -#define nINCOMPRX_RH 0x0 #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ -#define nDMAREQMODE_RH 0x0 #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ -#define nAUTOREQ_RH 0x0 /* Bit masks for USB_RXCOUNT */ @@ -1151,35 +883,22 @@ /* Bit masks for USB_DMA_INTERRUPT */ #define DMA0_INT 0x1 /* DMA0 pending interrupt */ -#define nDMA0_INT 0x0 #define DMA1_INT 0x2 /* DMA1 pending interrupt */ -#define nDMA1_INT 0x0 #define DMA2_INT 0x4 /* DMA2 pending interrupt */ -#define nDMA2_INT 0x0 #define DMA3_INT 0x8 /* DMA3 pending interrupt */ -#define nDMA3_INT 0x0 #define DMA4_INT 0x10 /* DMA4 pending interrupt */ -#define nDMA4_INT 0x0 #define DMA5_INT 0x20 /* DMA5 pending interrupt */ -#define nDMA5_INT 0x0 #define DMA6_INT 0x40 /* DMA6 pending interrupt */ -#define nDMA6_INT 0x0 #define DMA7_INT 0x80 /* DMA7 pending interrupt */ -#define nDMA7_INT 0x0 /* Bit masks for USB_DMAxCONTROL */ #define DMA_ENA 0x1 /* DMA enable */ -#define nDMA_ENA 0x0 #define DIRECTION 0x2 /* direction of DMA transfer */ -#define nDIRECTION 0x0 #define MODE 0x4 /* DMA Bus error */ -#define nMODE 0x0 #define INT_ENA 0x8 /* Interrupt enable */ -#define nINT_ENA 0x0 #define EPNUM 0xf0 /* EP number */ #define BUSERROR 0x100 /* DMA Bus error */ -#define nBUSERROR 0x0 /* Bit masks for USB_DMAxADDRHIGH */ diff --git a/include/asm-blackfin/mach-bf548/defBF544.h b/include/asm-blackfin/mach-bf548/defBF544.h index 8fc77ea12aa..dd955dcd39b 100644 --- a/include/asm-blackfin/mach-bf548/defBF544.h +++ b/include/asm-blackfin/mach-bf548/defBF544.h @@ -538,21 +538,13 @@ /* Bit masks for PIXC_CTL */ #define PIXC_EN 0x1 /* Pixel Compositor Enable */ -#define nPIXC_EN 0x0 #define OVR_A_EN 0x2 /* Overlay A Enable */ -#define nOVR_A_EN 0x0 #define OVR_B_EN 0x4 /* Overlay B Enable */ -#define nOVR_B_EN 0x0 #define IMG_FORM 0x8 /* Image Data Format */ -#define nIMG_FORM 0x0 #define OVR_FORM 0x10 /* Overlay Data Format */ -#define nOVR_FORM 0x0 #define OUT_FORM 0x20 /* Output Data Format */ -#define nOUT_FORM 0x0 #define UDS_MOD 0x40 /* Resampling Mode */ -#define nUDS_MOD 0x0 #define TC_EN 0x80 /* Transparent Color Enable */ -#define nTC_EN 0x0 #define IMG_STAT 0x300 /* Image FIFO Status */ #define OVR_STAT 0xc00 /* Overlay FIFO Status */ #define WM_LVL 0x3000 /* FIFO Watermark Level */ @@ -600,13 +592,9 @@ /* Bit masks for PIXC_INTRSTAT */ #define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ -#define nOVR_INT_EN 0x0 #define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ -#define nFRM_INT_EN 0x0 #define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ -#define nOVR_INT_STAT 0x0 #define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ -#define nFRM_INT_STAT 0x0 /* Bit masks for PIXC_RYCON */ @@ -614,7 +602,6 @@ #define A12 0xffc00 /* A12 in the Coefficient Matrix */ #define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ #define RY_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nRY_MULT4 0x0 /* Bit masks for PIXC_GUCON */ @@ -622,7 +609,6 @@ #define A22 0xffc00 /* A22 in the Coefficient Matrix */ #define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ #define GU_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nGU_MULT4 0x0 /* Bit masks for PIXC_BVCON */ @@ -630,7 +616,6 @@ #define A32 0xffc00 /* A32 in the Coefficient Matrix */ #define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ #define BV_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nBV_MULT4 0x0 /* Bit masks for PIXC_CCBIAS */ @@ -647,48 +632,28 @@ /* Bit masks for HOST_CONTROL */ #define HOST_EN 0x1 /* Host Enable */ -#define nHOST_EN 0x0 #define HOST_END 0x2 /* Host Endianess */ -#define nHOST_END 0x0 #define DATA_SIZE 0x4 /* Data Size */ -#define nDATA_SIZE 0x0 #define HOST_RST 0x8 /* Host Reset */ -#define nHOST_RST 0x0 #define HRDY_OVR 0x20 /* Host Ready Override */ -#define nHRDY_OVR 0x0 #define INT_MODE 0x40 /* Interrupt Mode */ -#define nINT_MODE 0x0 #define BT_EN 0x80 /* Bus Timeout Enable */ -#define nBT_EN 0x0 #define EHW 0x100 /* Enable Host Write */ -#define nEHW 0x0 #define EHR 0x200 /* Enable Host Read */ -#define nEHR 0x0 #define BDR 0x400 /* Burst DMA Requests */ -#define nBDR 0x0 /* Bit masks for HOST_STATUS */ #define READY 0x1 /* DMA Ready */ -#define nREADY 0x0 #define FIFOFULL 0x2 /* FIFO Full */ -#define nFIFOFULL 0x0 #define FIFOEMPTY 0x4 /* FIFO Empty */ -#define nFIFOEMPTY 0x0 #define COMPLETE 0x8 /* DMA Complete */ -#define nCOMPLETE 0x0 #define HSHK 0x10 /* Host Handshake */ -#define nHSHK 0x0 #define TIMEOUT 0x20 /* Host Timeout */ -#define nTIMEOUT 0x0 #define HIRQ 0x40 /* Host Interrupt Request */ -#define nHIRQ 0x0 #define ALLOW_CNFG 0x80 /* Allow New Configuration */ -#define nALLOW_CNFG 0x0 #define DMA_DIR 0x100 /* DMA Direction */ -#define nDMA_DIR 0x0 #define BTE 0x200 /* Bus Timeout Enabled */ -#define nBTE 0x0 /* Bit masks for HOST_TIMEOUT */ @@ -697,67 +662,42 @@ /* Bit masks for TIMER_ENABLE1 */ #define TIMEN8 0x1 /* Timer 8 Enable */ -#define nTIMEN8 0x0 #define TIMEN9 0x2 /* Timer 9 Enable */ -#define nTIMEN9 0x0 #define TIMEN10 0x4 /* Timer 10 Enable */ -#define nTIMEN10 0x0 /* Bit masks for TIMER_DISABLE1 */ #define TIMDIS8 0x1 /* Timer 8 Disable */ -#define nTIMDIS8 0x0 #define TIMDIS9 0x2 /* Timer 9 Disable */ -#define nTIMDIS9 0x0 #define TIMDIS10 0x4 /* Timer 10 Disable */ -#define nTIMDIS10 0x0 /* Bit masks for TIMER_STATUS1 */ #define TIMIL8 0x1 /* Timer 8 Interrupt */ -#define nTIMIL8 0x0 #define TIMIL9 0x2 /* Timer 9 Interrupt */ -#define nTIMIL9 0x0 #define TIMIL10 0x4 /* Timer 10 Interrupt */ -#define nTIMIL10 0x0 #define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ -#define nTOVF_ERR8 0x0 #define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ -#define nTOVF_ERR9 0x0 #define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ -#define nTOVF_ERR10 0x0 #define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ -#define nTRUN8 0x0 #define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ -#define nTRUN9 0x0 #define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ -#define nTRUN10 0x0 /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ /* Bit masks for HMDMAx_CONTROL */ #define HMDMAEN 0x1 /* Handshake MDMA Enable */ -#define nHMDMAEN 0x0 #define REP 0x2 /* Handshake MDMA Request Polarity */ -#define nREP 0x0 #define UTE 0x8 /* Urgency Threshold Enable */ -#define nUTE 0x0 #define OIE 0x10 /* Overflow Interrupt Enable */ -#define nOIE 0x0 #define BDIE 0x20 /* Block Done Interrupt Enable */ -#define nBDIE 0x0 #define MBDI 0x40 /* Mask Block Done Interrupt */ -#define nMBDI 0x0 #define DRQ 0x300 /* Handshake MDMA Request Type */ #define RBC 0x1000 /* Force Reload of BCOUNT */ -#define nRBC 0x0 #define PS 0x2000 /* Pin Status */ -#define nPS 0x0 #define OI 0x4000 /* Overflow Interrupt Generated */ -#define nOI 0x0 #define BDI 0x8000 /* Block Done Interrupt Generated */ -#define nBDI 0x0 /* ******************************************* */ /* MULTI BIT MACRO ENUMERATIONS */ diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h index d9e3062a911..8d4214e0807 100644 --- a/include/asm-blackfin/mach-bf548/defBF548.h +++ b/include/asm-blackfin/mach-bf548/defBF548.h @@ -899,21 +899,13 @@ /* Bit masks for PIXC_CTL */ #define PIXC_EN 0x1 /* Pixel Compositor Enable */ -#define nPIXC_EN 0x0 #define OVR_A_EN 0x2 /* Overlay A Enable */ -#define nOVR_A_EN 0x0 #define OVR_B_EN 0x4 /* Overlay B Enable */ -#define nOVR_B_EN 0x0 #define IMG_FORM 0x8 /* Image Data Format */ -#define nIMG_FORM 0x0 #define OVR_FORM 0x10 /* Overlay Data Format */ -#define nOVR_FORM 0x0 #define OUT_FORM 0x20 /* Output Data Format */ -#define nOUT_FORM 0x0 #define UDS_MOD 0x40 /* Resampling Mode */ -#define nUDS_MOD 0x0 #define TC_EN 0x80 /* Transparent Color Enable */ -#define nTC_EN 0x0 #define IMG_STAT 0x300 /* Image FIFO Status */ #define OVR_STAT 0xc00 /* Overlay FIFO Status */ #define WM_LVL 0x3000 /* FIFO Watermark Level */ @@ -961,13 +953,9 @@ /* Bit masks for PIXC_INTRSTAT */ #define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ -#define nOVR_INT_EN 0x0 #define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ -#define nFRM_INT_EN 0x0 #define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ -#define nOVR_INT_STAT 0x0 #define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ -#define nFRM_INT_STAT 0x0 /* Bit masks for PIXC_RYCON */ @@ -975,7 +963,6 @@ #define A12 0xffc00 /* A12 in the Coefficient Matrix */ #define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ #define RY_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nRY_MULT4 0x0 /* Bit masks for PIXC_GUCON */ @@ -983,7 +970,6 @@ #define A22 0xffc00 /* A22 in the Coefficient Matrix */ #define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ #define GU_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nGU_MULT4 0x0 /* Bit masks for PIXC_BVCON */ @@ -991,7 +977,6 @@ #define A32 0xffc00 /* A32 in the Coefficient Matrix */ #define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ #define BV_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nBV_MULT4 0x0 /* Bit masks for PIXC_CCBIAS */ @@ -1008,48 +993,28 @@ /* Bit masks for HOST_CONTROL */ #define HOST_EN 0x1 /* Host Enable */ -#define nHOST_EN 0x0 #define HOST_END 0x2 /* Host Endianess */ -#define nHOST_END 0x0 #define DATA_SIZE 0x4 /* Data Size */ -#define nDATA_SIZE 0x0 #define HOST_RST 0x8 /* Host Reset */ -#define nHOST_RST 0x0 #define HRDY_OVR 0x20 /* Host Ready Override */ -#define nHRDY_OVR 0x0 #define INT_MODE 0x40 /* Interrupt Mode */ -#define nINT_MODE 0x0 #define BT_EN 0x80 /* Bus Timeout Enable */ -#define nBT_EN 0x0 #define EHW 0x100 /* Enable Host Write */ -#define nEHW 0x0 #define EHR 0x200 /* Enable Host Read */ -#define nEHR 0x0 #define BDR 0x400 /* Burst DMA Requests */ -#define nBDR 0x0 /* Bit masks for HOST_STATUS */ #define READY 0x1 /* DMA Ready */ -#define nREADY 0x0 #define FIFOFULL 0x2 /* FIFO Full */ -#define nFIFOFULL 0x0 #define FIFOEMPTY 0x4 /* FIFO Empty */ -#define nFIFOEMPTY 0x0 #define COMPLETE 0x8 /* DMA Complete */ -#define nCOMPLETE 0x0 #define HSHK 0x10 /* Host Handshake */ -#define nHSHK 0x0 #define TIMEOUT 0x20 /* Host Timeout */ -#define nTIMEOUT 0x0 #define HIRQ 0x40 /* Host Interrupt Request */ -#define nHIRQ 0x0 #define ALLOW_CNFG 0x80 /* Allow New Configuration */ -#define nALLOW_CNFG 0x0 #define DMA_DIR 0x100 /* DMA Direction */ -#define nDMA_DIR 0x0 #define BTE 0x200 /* Bus Timeout Enabled */ -#define nBTE 0x0 /* Bit masks for HOST_TIMEOUT */ @@ -1058,7 +1023,6 @@ /* Bit masks for KPAD_CTL */ #define KPAD_EN 0x1 /* Keypad Enable */ -#define nKPAD_EN 0x0 #define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ #define KPAD_ROWEN 0x1c00 /* Row Enable Width */ #define KPAD_COLEN 0xe000 /* Column Enable Width */ @@ -1080,29 +1044,21 @@ /* Bit masks for KPAD_STAT */ #define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ -#define nKPAD_IRQ 0x0 #define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ #define KPAD_PRESSED 0x8 /* Key press current status */ -#define nKPAD_PRESSED 0x0 /* Bit masks for KPAD_SOFTEVAL */ #define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ -#define nKPAD_SOFTEVAL_E 0x0 /* Bit masks for SDH_COMMAND */ #define CMD_IDX 0x3f /* Command Index */ #define CMD_RSP 0x40 /* Response */ -#define nCMD_RSP 0x0 #define CMD_L_RSP 0x80 /* Long Response */ -#define nCMD_L_RSP 0x0 #define CMD_INT_E 0x100 /* Command Interrupt */ -#define nCMD_INT_E 0x0 #define CMD_PEND_E 0x200 /* Command Pending */ -#define nCMD_PEND_E 0x0 #define CMD_E 0x400 /* Command Enable */ -#define nCMD_E 0x0 /* Bit masks for SDH_PWR_CTL */ @@ -1111,21 +1067,15 @@ #define TBD 0x3c /* TBD */ #endif #define SD_CMD_OD 0x40 /* Open Drain Output */ -#define nSD_CMD_OD 0x0 #define ROD_CTL 0x80 /* Rod Control */ -#define nROD_CTL 0x0 /* Bit masks for SDH_CLK_CTL */ #define CLKDIV 0xff /* MC_CLK Divisor */ #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ -#define nCLK_E 0x0 #define PWR_SV_E 0x200 /* Power Save Enable */ -#define nPWR_SV_E 0x0 #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ -#define nCLKDIV_BYPASS 0x0 #define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ -#define nWIDE_BUS 0x0 /* Bit masks for SDH_RESP_CMD */ @@ -1134,133 +1084,74 @@ /* Bit masks for SDH_DATA_CTL */ #define DTX_E 0x1 /* Data Transfer Enable */ -#define nDTX_E 0x0 #define DTX_DIR 0x2 /* Data Transfer Direction */ -#define nDTX_DIR 0x0 #define DTX_MODE 0x4 /* Data Transfer Mode */ -#define nDTX_MODE 0x0 #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ -#define nDTX_DMA_E 0x0 #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ /* Bit masks for SDH_STATUS */ #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ -#define nCMD_CRC_FAIL 0x0 #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ -#define nDAT_CRC_FAIL 0x0 #define CMD_TIMEOUT 0x4 /* CMD Time Out */ -#define nCMD_TIMEOUT 0x0 #define DAT_TIMEOUT 0x8 /* Data Time Out */ -#define nDAT_TIMEOUT 0x0 #define TX_UNDERRUN 0x10 /* Transmit Underrun */ -#define nTX_UNDERRUN 0x0 #define RX_OVERRUN 0x20 /* Receive Overrun */ -#define nRX_OVERRUN 0x0 #define CMD_RESP_END 0x40 /* CMD Response End */ -#define nCMD_RESP_END 0x0 #define CMD_SENT 0x80 /* CMD Sent */ -#define nCMD_SENT 0x0 #define DAT_END 0x100 /* Data End */ -#define nDAT_END 0x0 #define START_BIT_ERR 0x200 /* Start Bit Error */ -#define nSTART_BIT_ERR 0x0 #define DAT_BLK_END 0x400 /* Data Block End */ -#define nDAT_BLK_END 0x0 #define CMD_ACT 0x800 /* CMD Active */ -#define nCMD_ACT 0x0 #define TX_ACT 0x1000 /* Transmit Active */ -#define nTX_ACT 0x0 #define RX_ACT 0x2000 /* Receive Active */ -#define nRX_ACT 0x0 #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ -#define nTX_FIFO_STAT 0x0 #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ -#define nRX_FIFO_STAT 0x0 #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ -#define nTX_FIFO_FULL 0x0 #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ -#define nRX_FIFO_FULL 0x0 #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ -#define nTX_FIFO_ZERO 0x0 #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ -#define nRX_DAT_ZERO 0x0 #define TX_DAT_RDY 0x100000 /* Transmit Data Available */ -#define nTX_DAT_RDY 0x0 #define RX_FIFO_RDY 0x200000 /* Receive Data Available */ -#define nRX_FIFO_RDY 0x0 /* Bit masks for SDH_STATUS_CLR */ #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ -#define nCMD_CRC_FAIL_STAT 0x0 #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ -#define nDAT_CRC_FAIL_STAT 0x0 #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ -#define nCMD_TIMEOUT_STAT 0x0 #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ -#define nDAT_TIMEOUT_STAT 0x0 #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ -#define nTX_UNDERRUN_STAT 0x0 #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ -#define nRX_OVERRUN_STAT 0x0 #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ -#define nCMD_RESP_END_STAT 0x0 #define CMD_SENT_STAT 0x80 /* CMD Sent Status */ -#define nCMD_SENT_STAT 0x0 #define DAT_END_STAT 0x100 /* Data End Status */ -#define nDAT_END_STAT 0x0 #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ -#define nSTART_BIT_ERR_STAT 0x0 #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ -#define nDAT_BLK_END_STAT 0x0 /* Bit masks for SDH_MASK0 */ #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ -#define nCMD_CRC_FAIL_MASK 0x0 #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ -#define nDAT_CRC_FAIL_MASK 0x0 #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ -#define nCMD_TIMEOUT_MASK 0x0 #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ -#define nDAT_TIMEOUT_MASK 0x0 #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ -#define nTX_UNDERRUN_MASK 0x0 #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ -#define nRX_OVERRUN_MASK 0x0 #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ -#define nCMD_RESP_END_MASK 0x0 #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ -#define nCMD_SENT_MASK 0x0 #define DAT_END_MASK 0x100 /* Data End Mask */ -#define nDAT_END_MASK 0x0 #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ -#define nSTART_BIT_ERR_MASK 0x0 #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ -#define nDAT_BLK_END_MASK 0x0 #define CMD_ACT_MASK 0x800 /* CMD Active Mask */ -#define nCMD_ACT_MASK 0x0 #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ -#define nTX_ACT_MASK 0x0 #define RX_ACT_MASK 0x2000 /* Receive Active Mask */ -#define nRX_ACT_MASK 0x0 #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ -#define nTX_FIFO_STAT_MASK 0x0 #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ -#define nRX_FIFO_STAT_MASK 0x0 #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ -#define nTX_FIFO_FULL_MASK 0x0 #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ -#define nRX_FIFO_FULL_MASK 0x0 #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ -#define nTX_FIFO_ZERO_MASK 0x0 #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ -#define nRX_DAT_ZERO_MASK 0x0 #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ -#define nTX_DAT_RDY_MASK 0x0 #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ -#define nRX_FIFO_RDY_MASK 0x0 /* Bit masks for SDH_FIFO_CNT */ @@ -1269,73 +1160,47 @@ /* Bit masks for SDH_E_STATUS */ #define SDIO_INT_DET 0x2 /* SDIO Int Detected */ -#define nSDIO_INT_DET 0x0 #define SD_CARD_DET 0x10 /* SD Card Detect */ -#define nSD_CARD_DET 0x0 /* Bit masks for SDH_E_MASK */ #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ -#define nSDIO_MSK 0x0 #define SCD_MSK 0x40 /* Mask Card Detect */ -#define nSCD_MSK 0x0 /* Bit masks for SDH_CFG */ #define CLKS_EN 0x1 /* Clocks Enable */ -#define nCLKS_EN 0x0 #define SD4E 0x4 /* SDIO 4-Bit Enable */ -#define nSD4E 0x0 #define MWE 0x8 /* Moving Window Enable */ -#define nMWE 0x0 #define SD_RST 0x10 /* SDMMC Reset */ -#define nSD_RST 0x0 #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ -#define nPUP_SDDAT 0x0 #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ -#define nPUP_SDDAT3 0x0 #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ -#define nPD_SDDAT3 0x0 /* Bit masks for SDH_RD_WAIT_EN */ #define RWR 0x1 /* Read Wait Request */ -#define nRWR 0x0 /* Bit masks for ATAPI_CONTROL */ #define PIO_START 0x1 /* Start PIO/Reg Op */ -#define nPIO_START 0x0 #define MULTI_START 0x2 /* Start Multi-DMA Op */ -#define nMULTI_START 0x0 #define ULTRA_START 0x4 /* Start Ultra-DMA Op */ -#define nULTRA_START 0x0 #define XFER_DIR 0x8 /* Transfer Direction */ -#define nXFER_DIR 0x0 #define IORDY_EN 0x10 /* IORDY Enable */ -#define nIORDY_EN 0x0 #define FIFO_FLUSH 0x20 /* Flush FIFOs */ -#define nFIFO_FLUSH 0x0 #define SOFT_RST 0x40 /* Soft Reset */ -#define nSOFT_RST 0x0 #define DEV_RST 0x80 /* Device Reset */ -#define nDEV_RST 0x0 #define TFRCNT_RST 0x100 /* Trans Count Reset */ -#define nTFRCNT_RST 0x0 #define END_ON_TERM 0x200 /* End/Terminate Select */ -#define nEND_ON_TERM 0x0 #define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ -#define nPIO_USE_DMA 0x0 #define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ /* Bit masks for ATAPI_STATUS */ #define PIO_XFER_ON 0x1 /* PIO transfer in progress */ -#define nPIO_XFER_ON 0x0 #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ -#define nMULTI_XFER_ON 0x0 #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ -#define nULTRA_XFER_ON 0x0 #define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ /* Bit masks for ATAPI_DEV_ADDR */ @@ -1345,66 +1210,39 @@ /* Bit masks for ATAPI_INT_MASK */ #define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ -#define nATAPI_DEV_INT_MASK 0x0 #define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ -#define nPIO_DONE_MASK 0x0 #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ -#define nMULTI_DONE_MASK 0x0 #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ -#define nUDMAIN_DONE_MASK 0x0 #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ -#define nUDMAOUT_DONE_MASK 0x0 #define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ -#define nHOST_TERM_XFER_MASK 0x0 #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ -#define nMULTI_TERM_MASK 0x0 #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ -#define nUDMAIN_TERM_MASK 0x0 #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ -#define nUDMAOUT_TERM_MASK 0x0 /* Bit masks for ATAPI_INT_STATUS */ #define ATAPI_DEV_INT 0x1 /* Device interrupt status */ -#define nATAPI_DEV_INT 0x0 #define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ -#define nPIO_DONE_INT 0x0 #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ -#define nMULTI_DONE_INT 0x0 #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ -#define nUDMAIN_DONE_INT 0x0 #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ -#define nUDMAOUT_DONE_INT 0x0 #define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ -#define nHOST_TERM_XFER_INT 0x0 #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ -#define nMULTI_TERM_INT 0x0 #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ -#define nUDMAIN_TERM_INT 0x0 #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ -#define nUDMAOUT_TERM_INT 0x0 /* Bit masks for ATAPI_LINE_STATUS */ #define ATAPI_INTR 0x1 /* Device interrupt to host line status */ -#define nATAPI_INTR 0x0 #define ATAPI_DASP 0x2 /* Device dasp to host line status */ -#define nATAPI_DASP 0x0 #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ -#define nATAPI_CS0N 0x0 #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ -#define nATAPI_CS1N 0x0 #define ATAPI_ADDR 0x70 /* ATAPI address line status */ #define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ -#define nATAPI_DMAREQ 0x0 #define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ -#define nATAPI_DMAACKN 0x0 #define ATAPI_DIOWN 0x200 /* ATAPI write line status */ -#define nATAPI_DIOWN 0x0 #define ATAPI_DIORN 0x400 /* ATAPI read line status */ -#define nATAPI_DIORN 0x0 #define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ -#define nATAPI_IORDY 0x0 /* Bit masks for ATAPI_SM_STATE */ @@ -1416,7 +1254,6 @@ /* Bit masks for ATAPI_TERMINATE */ #define ATAPI_HOST_TERM 0x1 /* Host terminationation */ -#define nATAPI_HOST_TERM 0x0 /* Bit masks for ATAPI_REG_TIM_0 */ @@ -1471,41 +1308,26 @@ /* Bit masks for TIMER_ENABLE1 */ #define TIMEN8 0x1 /* Timer 8 Enable */ -#define nTIMEN8 0x0 #define TIMEN9 0x2 /* Timer 9 Enable */ -#define nTIMEN9 0x0 #define TIMEN10 0x4 /* Timer 10 Enable */ -#define nTIMEN10 0x0 /* Bit masks for TIMER_DISABLE1 */ #define TIMDIS8 0x1 /* Timer 8 Disable */ -#define nTIMDIS8 0x0 #define TIMDIS9 0x2 /* Timer 9 Disable */ -#define nTIMDIS9 0x0 #define TIMDIS10 0x4 /* Timer 10 Disable */ -#define nTIMDIS10 0x0 /* Bit masks for TIMER_STATUS1 */ #define TIMIL8 0x1 /* Timer 8 Interrupt */ -#define nTIMIL8 0x0 #define TIMIL9 0x2 /* Timer 9 Interrupt */ -#define nTIMIL9 0x0 #define TIMIL10 0x4 /* Timer 10 Interrupt */ -#define nTIMIL10 0x0 #define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ -#define nTOVF_ERR8 0x0 #define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ -#define nTOVF_ERR9 0x0 #define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ -#define nTOVF_ERR10 0x0 #define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ -#define nTRUN8 0x0 #define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ -#define nTRUN9 0x0 #define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ -#define nTRUN10 0x0 /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ @@ -1516,131 +1338,77 @@ /* Bit masks for USB_POWER */ #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ -#define nENABLE_SUSPENDM 0x0 #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ -#define nSUSPEND_MODE 0x0 #define RESUME_MODE 0x4 /* DMA Mode */ -#define nRESUME_MODE 0x0 #define RESET 0x8 /* Reset indicator */ -#define nRESET 0x0 #define HS_MODE 0x10 /* High Speed mode indicator */ -#define nHS_MODE 0x0 #define HS_ENABLE 0x20 /* high Speed Enable */ -#define nHS_ENABLE 0x0 #define SOFT_CONN 0x40 /* Soft connect */ -#define nSOFT_CONN 0x0 #define ISO_UPDATE 0x80 /* Isochronous update */ -#define nISO_UPDATE 0x0 /* Bit masks for USB_INTRTX */ #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ -#define nEP0_TX 0x0 #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ -#define nEP1_TX 0x0 #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ -#define nEP2_TX 0x0 #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ -#define nEP3_TX 0x0 #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ -#define nEP4_TX 0x0 #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ -#define nEP5_TX 0x0 #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ -#define nEP6_TX 0x0 #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ -#define nEP7_TX 0x0 /* Bit masks for USB_INTRRX */ #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ -#define nEP1_RX 0x0 #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ -#define nEP2_RX 0x0 #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ -#define nEP3_RX 0x0 #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ -#define nEP4_RX 0x0 #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ -#define nEP5_RX 0x0 #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ -#define nEP6_RX 0x0 #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ -#define nEP7_RX 0x0 /* Bit masks for USB_INTRTXE */ #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ -#define nEP0_TX_E 0x0 #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ -#define nEP1_TX_E 0x0 #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ -#define nEP2_TX_E 0x0 #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ -#define nEP3_TX_E 0x0 #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ -#define nEP4_TX_E 0x0 #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ -#define nEP5_TX_E 0x0 #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ -#define nEP6_TX_E 0x0 #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ -#define nEP7_TX_E 0x0 /* Bit masks for USB_INTRRXE */ #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ -#define nEP1_RX_E 0x0 #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ -#define nEP2_RX_E 0x0 #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ -#define nEP3_RX_E 0x0 #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ -#define nEP4_RX_E 0x0 #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ -#define nEP5_RX_E 0x0 #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ -#define nEP6_RX_E 0x0 #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ -#define nEP7_RX_E 0x0 /* Bit masks for USB_INTRUSB */ #define SUSPEND_B 0x1 /* Suspend indicator */ -#define nSUSPEND_B 0x0 #define RESUME_B 0x2 /* Resume indicator */ -#define nRESUME_B 0x0 #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ -#define nRESET_OR_BABLE_B 0x0 #define SOF_B 0x8 /* Start of frame */ -#define nSOF_B 0x0 #define CONN_B 0x10 /* Connection indicator */ -#define nCONN_B 0x0 #define DISCON_B 0x20 /* Disconnect indicator */ -#define nDISCON_B 0x0 #define SESSION_REQ_B 0x40 /* Session Request */ -#define nSESSION_REQ_B 0x0 #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ -#define nVBUS_ERROR_B 0x0 /* Bit masks for USB_INTRUSBE */ #define SUSPEND_BE 0x1 /* Suspend indicator int enable */ -#define nSUSPEND_BE 0x0 #define RESUME_BE 0x2 /* Resume indicator int enable */ -#define nRESUME_BE 0x0 #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ -#define nRESET_OR_BABLE_BE 0x0 #define SOF_BE 0x8 /* Start of frame int enable */ -#define nSOF_BE 0x0 #define CONN_BE 0x10 /* Connection indicator int enable */ -#define nCONN_BE 0x0 #define DISCON_BE 0x20 /* Disconnect indicator int enable */ -#define nDISCON_BE 0x0 #define SESSION_REQ_BE 0x40 /* Session Request int enable */ -#define nSESSION_REQ_BE 0x0 #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ -#define nVBUS_ERROR_BE 0x0 /* Bit masks for USB_FRAME */ @@ -1653,117 +1421,67 @@ /* Bit masks for USB_GLOBAL_CTL */ #define GLOBAL_ENA 0x1 /* enables USB module */ -#define nGLOBAL_ENA 0x0 #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ -#define nEP1_TX_ENA 0x0 #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ -#define nEP2_TX_ENA 0x0 #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ -#define nEP3_TX_ENA 0x0 #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ -#define nEP4_TX_ENA 0x0 #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ -#define nEP5_TX_ENA 0x0 #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ -#define nEP6_TX_ENA 0x0 #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ -#define nEP7_TX_ENA 0x0 #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ -#define nEP1_RX_ENA 0x0 #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ -#define nEP2_RX_ENA 0x0 #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ -#define nEP3_RX_ENA 0x0 #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ -#define nEP4_RX_ENA 0x0 #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ -#define nEP5_RX_ENA 0x0 #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ -#define nEP6_RX_ENA 0x0 #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ -#define nEP7_RX_ENA 0x0 /* Bit masks for USB_OTG_DEV_CTL */ #define SESSION 0x1 /* session indicator */ -#define nSESSION 0x0 #define HOST_REQ 0x2 /* Host negotiation request */ -#define nHOST_REQ 0x0 #define HOST_MODE 0x4 /* indicates USBDRC is a host */ -#define nHOST_MODE 0x0 #define VBUS0 0x8 /* Vbus level indicator[0] */ -#define nVBUS0 0x0 #define VBUS1 0x10 /* Vbus level indicator[1] */ -#define nVBUS1 0x0 #define LSDEV 0x20 /* Low-speed indicator */ -#define nLSDEV 0x0 #define FSDEV 0x40 /* Full or High-speed indicator */ -#define nFSDEV 0x0 #define B_DEVICE 0x80 /* A' or 'B' device indicator */ -#define nB_DEVICE 0x0 /* Bit masks for USB_OTG_VBUS_IRQ */ #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ -#define nDRIVE_VBUS_ON 0x0 #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ -#define nDRIVE_VBUS_OFF 0x0 #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ -#define nCHRG_VBUS_START 0x0 #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ -#define nCHRG_VBUS_END 0x0 #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ -#define nDISCHRG_VBUS_START 0x0 #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ -#define nDISCHRG_VBUS_END 0x0 /* Bit masks for USB_OTG_VBUS_MASK */ #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ -#define nDRIVE_VBUS_ON_ENA 0x0 #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ -#define nDRIVE_VBUS_OFF_ENA 0x0 #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ -#define nCHRG_VBUS_START_ENA 0x0 #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ -#define nCHRG_VBUS_END_ENA 0x0 #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ -#define nDISCHRG_VBUS_START_ENA 0x0 #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ -#define nDISCHRG_VBUS_END_ENA 0x0 /* Bit masks for USB_CSR0 */ #define RXPKTRDY 0x1 /* data packet receive indicator */ -#define nRXPKTRDY 0x0 #define TXPKTRDY 0x2 /* data packet in FIFO indicator */ -#define nTXPKTRDY 0x0 #define STALL_SENT 0x4 /* STALL handshake sent */ -#define nSTALL_SENT 0x0 #define DATAEND 0x8 /* Data end indicator */ -#define nDATAEND 0x0 #define SETUPEND 0x10 /* Setup end */ -#define nSETUPEND 0x0 #define SENDSTALL 0x20 /* Send STALL handshake */ -#define nSENDSTALL 0x0 #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ -#define nSERVICED_RXPKTRDY 0x0 #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ -#define nSERVICED_SETUPEND 0x0 #define FLUSHFIFO 0x100 /* flush endpoint FIFO */ -#define nFLUSHFIFO 0x0 #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ -#define nSTALL_RECEIVED_H 0x0 #define SETUPPKT_H 0x8 /* send Setup token host mode */ -#define nSETUPPKT_H 0x0 #define ERROR_H 0x10 /* timeout error indicator host mode */ -#define nERROR_H 0x0 #define REQPKT_H 0x20 /* Request an IN transaction host mode */ -#define nREQPKT_H 0x0 #define STATUSPKT_H 0x40 /* Status stage transaction host mode */ -#define nSTATUSPKT_H 0x0 #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ -#define nNAK_TIMEOUT_H 0x0 /* Bit masks for USB_COUNT0 */ @@ -1784,37 +1502,21 @@ /* Bit masks for USB_TXCSR */ #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ -#define nTXPKTRDY_T 0x0 #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ -#define nFIFO_NOT_EMPTY_T 0x0 #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ -#define nUNDERRUN_T 0x0 #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ -#define nFLUSHFIFO_T 0x0 #define STALL_SEND_T 0x10 /* issue a Stall handshake */ -#define nSTALL_SEND_T 0x0 #define STALL_SENT_T 0x20 /* Stall handshake transmitted */ -#define nSTALL_SENT_T 0x0 #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ -#define nCLEAR_DATATOGGLE_T 0x0 #define INCOMPTX_T 0x80 /* indicates that a large packet is split */ -#define nINCOMPTX_T 0x0 #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ -#define nDMAREQMODE_T 0x0 #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ -#define nFORCE_DATATOGGLE_T 0x0 #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ -#define nDMAREQ_ENA_T 0x0 #define ISO_T 0x4000 /* enable Isochronous transfers */ -#define nISO_T 0x0 #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ -#define nAUTOSET_T 0x0 #define ERROR_TH 0x4 /* error condition host mode */ -#define nERROR_TH 0x0 #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ -#define nSTALL_RECEIVED_TH 0x0 #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ -#define nNAK_TIMEOUT_TH 0x0 /* Bit masks for USB_TXCOUNT */ @@ -1823,45 +1525,25 @@ /* Bit masks for USB_RXCSR */ #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ -#define nRXPKTRDY_R 0x0 #define FIFO_FULL_R 0x2 /* FIFO not empty */ -#define nFIFO_FULL_R 0x0 #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ -#define nOVERRUN_R 0x0 #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ -#define nDATAERROR_R 0x0 #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ -#define nFLUSHFIFO_R 0x0 #define STALL_SEND_R 0x20 /* issue a Stall handshake */ -#define nSTALL_SEND_R 0x0 #define STALL_SENT_R 0x40 /* Stall handshake transmitted */ -#define nSTALL_SENT_R 0x0 #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ -#define nCLEAR_DATATOGGLE_R 0x0 #define INCOMPRX_R 0x100 /* indicates that a large packet is split */ -#define nINCOMPRX_R 0x0 #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ -#define nDMAREQMODE_R 0x0 #define DISNYET_R 0x1000 /* disable Nyet handshakes */ -#define nDISNYET_R 0x0 #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ -#define nDMAREQ_ENA_R 0x0 #define ISO_R 0x4000 /* enable Isochronous transfers */ -#define nISO_R 0x0 #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ -#define nAUTOCLEAR_R 0x0 #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ -#define nERROR_RH 0x0 #define REQPKT_RH 0x20 /* request an IN transaction host mode */ -#define nREQPKT_RH 0x0 #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ -#define nSTALL_RECEIVED_RH 0x0 #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ -#define nINCOMPRX_RH 0x0 #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ -#define nDMAREQMODE_RH 0x0 #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ -#define nAUTOREQ_RH 0x0 /* Bit masks for USB_RXCOUNT */ @@ -1888,35 +1570,22 @@ /* Bit masks for USB_DMA_INTERRUPT */ #define DMA0_INT 0x1 /* DMA0 pending interrupt */ -#define nDMA0_INT 0x0 #define DMA1_INT 0x2 /* DMA1 pending interrupt */ -#define nDMA1_INT 0x0 #define DMA2_INT 0x4 /* DMA2 pending interrupt */ -#define nDMA2_INT 0x0 #define DMA3_INT 0x8 /* DMA3 pending interrupt */ -#define nDMA3_INT 0x0 #define DMA4_INT 0x10 /* DMA4 pending interrupt */ -#define nDMA4_INT 0x0 #define DMA5_INT 0x20 /* DMA5 pending interrupt */ -#define nDMA5_INT 0x0 #define DMA6_INT 0x40 /* DMA6 pending interrupt */ -#define nDMA6_INT 0x0 #define DMA7_INT 0x80 /* DMA7 pending interrupt */ -#define nDMA7_INT 0x0 /* Bit masks for USB_DMAxCONTROL */ #define DMA_ENA 0x1 /* DMA enable */ -#define nDMA_ENA 0x0 #define DIRECTION 0x2 /* direction of DMA transfer */ -#define nDIRECTION 0x0 #define MODE 0x4 /* DMA Bus error */ -#define nMODE 0x0 #define INT_ENA 0x8 /* Interrupt enable */ -#define nINT_ENA 0x0 #define EPNUM 0xf0 /* EP number */ #define BUSERROR 0x100 /* DMA Bus error */ -#define nBUSERROR 0x0 /* Bit masks for USB_DMAxADDRHIGH */ @@ -1937,26 +1606,16 @@ /* Bit masks for HMDMAx_CONTROL */ #define HMDMAEN 0x1 /* Handshake MDMA Enable */ -#define nHMDMAEN 0x0 #define REP 0x2 /* Handshake MDMA Request Polarity */ -#define nREP 0x0 #define UTE 0x8 /* Urgency Threshold Enable */ -#define nUTE 0x0 #define OIE 0x10 /* Overflow Interrupt Enable */ -#define nOIE 0x0 #define BDIE 0x20 /* Block Done Interrupt Enable */ -#define nBDIE 0x0 #define MBDI 0x40 /* Mask Block Done Interrupt */ -#define nMBDI 0x0 #define DRQ 0x300 /* Handshake MDMA Request Type */ #define RBC 0x1000 /* Force Reload of BCOUNT */ -#define nRBC 0x0 #define PS 0x2000 /* Pin Status */ -#define nPS 0x0 #define OI 0x4000 /* Overflow Interrupt Generated */ -#define nOI 0x0 #define BDI 0x8000 /* Block Done Interrupt Generated */ -#define nBDI 0x0 /* ******************************************* */ /* MULTI BIT MACRO ENUMERATIONS */ diff --git a/include/asm-blackfin/mach-bf548/defBF549.h b/include/asm-blackfin/mach-bf548/defBF549.h index b1cc1c073b4..c2f4734da48 100644 --- a/include/asm-blackfin/mach-bf548/defBF549.h +++ b/include/asm-blackfin/mach-bf548/defBF549.h @@ -1070,21 +1070,13 @@ /* Bit masks for PIXC_CTL */ #define PIXC_EN 0x1 /* Pixel Compositor Enable */ -#define nPIXC_EN 0x0 #define OVR_A_EN 0x2 /* Overlay A Enable */ -#define nOVR_A_EN 0x0 #define OVR_B_EN 0x4 /* Overlay B Enable */ -#define nOVR_B_EN 0x0 #define IMG_FORM 0x8 /* Image Data Format */ -#define nIMG_FORM 0x0 #define OVR_FORM 0x10 /* Overlay Data Format */ -#define nOVR_FORM 0x0 #define OUT_FORM 0x20 /* Output Data Format */ -#define nOUT_FORM 0x0 #define UDS_MOD 0x40 /* Resampling Mode */ -#define nUDS_MOD 0x0 #define TC_EN 0x80 /* Transparent Color Enable */ -#define nTC_EN 0x0 #define IMG_STAT 0x300 /* Image FIFO Status */ #define OVR_STAT 0xc00 /* Overlay FIFO Status */ #define WM_LVL 0x3000 /* FIFO Watermark Level */ @@ -1132,13 +1124,9 @@ /* Bit masks for PIXC_INTRSTAT */ #define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ -#define nOVR_INT_EN 0x0 #define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ -#define nFRM_INT_EN 0x0 #define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ -#define nOVR_INT_STAT 0x0 #define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ -#define nFRM_INT_STAT 0x0 /* Bit masks for PIXC_RYCON */ @@ -1146,7 +1134,6 @@ #define A12 0xffc00 /* A12 in the Coefficient Matrix */ #define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ #define RY_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nRY_MULT4 0x0 /* Bit masks for PIXC_GUCON */ @@ -1154,7 +1141,6 @@ #define A22 0xffc00 /* A22 in the Coefficient Matrix */ #define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ #define GU_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nGU_MULT4 0x0 /* Bit masks for PIXC_BVCON */ @@ -1162,7 +1148,6 @@ #define A32 0xffc00 /* A32 in the Coefficient Matrix */ #define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ #define BV_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nBV_MULT4 0x0 /* Bit masks for PIXC_CCBIAS */ @@ -1179,48 +1164,28 @@ /* Bit masks for HOST_CONTROL */ #define HOST_EN 0x1 /* Host Enable */ -#define nHOST_EN 0x0 #define HOST_END 0x2 /* Host Endianess */ -#define nHOST_END 0x0 #define DATA_SIZE 0x4 /* Data Size */ -#define nDATA_SIZE 0x0 #define HOST_RST 0x8 /* Host Reset */ -#define nHOST_RST 0x0 #define HRDY_OVR 0x20 /* Host Ready Override */ -#define nHRDY_OVR 0x0 #define INT_MODE 0x40 /* Interrupt Mode */ -#define nINT_MODE 0x0 #define BT_EN 0x80 /* Bus Timeout Enable */ -#define nBT_EN 0x0 #define EHW 0x100 /* Enable Host Write */ -#define nEHW 0x0 #define EHR 0x200 /* Enable Host Read */ -#define nEHR 0x0 #define BDR 0x400 /* Burst DMA Requests */ -#define nBDR 0x0 /* Bit masks for HOST_STATUS */ #define READY 0x1 /* DMA Ready */ -#define nREADY 0x0 #define FIFOFULL 0x2 /* FIFO Full */ -#define nFIFOFULL 0x0 #define FIFOEMPTY 0x4 /* FIFO Empty */ -#define nFIFOEMPTY 0x0 -#define COMPLETE 0x8 /* DMA Complete */ -#define nCOMPLETE 0x0 +#define DMA_COMPLETE 0x8 /* DMA Complete */ #define HSHK 0x10 /* Host Handshake */ -#define nHSHK 0x0 #define TIMEOUT 0x20 /* Host Timeout */ -#define nTIMEOUT 0x0 #define HIRQ 0x40 /* Host Interrupt Request */ -#define nHIRQ 0x0 #define ALLOW_CNFG 0x80 /* Allow New Configuration */ -#define nALLOW_CNFG 0x0 #define DMA_DIR 0x100 /* DMA Direction */ -#define nDMA_DIR 0x0 #define BTE 0x200 /* Bus Timeout Enabled */ -#define nBTE 0x0 /* Bit masks for HOST_TIMEOUT */ @@ -1229,71 +1194,41 @@ /* Bit masks for MXVR_CONFIG */ #define MXVREN 0x1 /* MXVR Enable */ -#define nMXVREN 0x0 #define MMSM 0x2 /* MXVR Master/Slave Mode Select */ -#define nMMSM 0x0 #define ACTIVE 0x4 /* Active Mode */ -#define nACTIVE 0x0 #define SDELAY 0x8 /* Synchronous Data Delay */ -#define nSDELAY 0x0 #define NCMRXEN 0x10 /* Normal Control Message Receive Enable */ -#define nNCMRXEN 0x0 #define RWRRXEN 0x20 /* Remote Write Receive Enable */ -#define nRWRRXEN 0x0 #define MTXEN 0x40 /* MXVR Transmit Data Enable */ -#define nMTXEN 0x0 #define MTXONB 0x80 /* MXVR Phy Transmitter On */ -#define nMTXONB 0x0 #define EPARITY 0x100 /* Even Parity Select */ -#define nEPARITY 0x0 #define MSB 0x1e00 /* Master Synchronous Boundary */ #define APRXEN 0x2000 /* Asynchronous Packet Receive Enable */ -#define nAPRXEN 0x0 #define WAKEUP 0x4000 /* Wake-Up */ -#define nWAKEUP 0x0 #define LMECH 0x8000 /* Lock Mechanism Select */ -#define nLMECH 0x0 /* Bit masks for MXVR_STATE_0 */ #define NACT 0x1 /* Network Activity */ -#define nNACT 0x0 #define SBLOCK 0x2 /* Super Block Lock */ -#define nSBLOCK 0x0 #define FMPLLST 0xc /* Frequency Multiply PLL SM State */ #define CDRPLLST 0xe0 /* Clock/Data Recovery PLL SM State */ #define APBSY 0x100 /* Asynchronous Packet Transmit Buffer Busy */ -#define nAPBSY 0x0 #define APARB 0x200 /* Asynchronous Packet Arbitrating */ -#define nAPARB 0x0 #define APTX 0x400 /* Asynchronous Packet Transmitting */ -#define nAPTX 0x0 #define APRX 0x800 /* Receiving Asynchronous Packet */ -#define nAPRX 0x0 #define CMBSY 0x1000 /* Control Message Transmit Buffer Busy */ -#define nCMBSY 0x0 #define CMARB 0x2000 /* Control Message Arbitrating */ -#define nCMARB 0x0 #define CMTX 0x4000 /* Control Message Transmitting */ -#define nCMTX 0x0 #define CMRX 0x8000 /* Receiving Control Message */ -#define nCMRX 0x0 #define MRXONB 0x10000 /* MRXONB Pin State */ -#define nMRXONB 0x0 #define RGSIP 0x20000 /* Remote Get Source In Progress */ -#define nRGSIP 0x0 #define DALIP 0x40000 /* Resource Deallocate In Progress */ -#define nDALIP 0x0 #define ALIP 0x80000 /* Resource Allocate In Progress */ -#define nALIP 0x0 #define RRDIP 0x100000 /* Remote Read In Progress */ -#define nRRDIP 0x0 #define RWRIP 0x200000 /* Remote Write In Progress */ -#define nRWRIP 0x0 #define FLOCK 0x400000 /* Frame Lock */ -#define nFLOCK 0x0 #define BLOCK 0x800000 /* Block Lock */ -#define nBLOCK 0x0 #define RSB 0xf000000 /* Received Synchronous Boundary */ #define DERRNUM 0xf0000000 /* DMA Error Channel Number */ @@ -1302,535 +1237,343 @@ #define SRXNUMB 0xf /* Synchronous Receive FIFO Number of Bytes */ #define STXNUMB 0xf0 /* Synchronous Transmit FIFO Number of Bytes */ #define APCONT 0x100 /* Asynchronous Packet Continuation */ -#define nAPCONT 0x0 #define OBERRNUM 0xe00 /* DMA Out of Bounds Error Channel Number */ #define DMAACTIVE0 0x10000 /* DMA0 Active */ -#define nDMAACTIVE0 0x0 #define DMAACTIVE1 0x20000 /* DMA1 Active */ -#define nDMAACTIVE1 0x0 #define DMAACTIVE2 0x40000 /* DMA2 Active */ -#define nDMAACTIVE2 0x0 #define DMAACTIVE3 0x80000 /* DMA3 Active */ -#define nDMAACTIVE3 0x0 #define DMAACTIVE4 0x100000 /* DMA4 Active */ -#define nDMAACTIVE4 0x0 #define DMAACTIVE5 0x200000 /* DMA5 Active */ -#define nDMAACTIVE5 0x0 #define DMAACTIVE6 0x400000 /* DMA6 Active */ -#define nDMAACTIVE6 0x0 #define DMAACTIVE7 0x800000 /* DMA7 Active */ -#define nDMAACTIVE7 0x0 #define DMAPMEN0 0x1000000 /* DMA0 Pattern Matching Enabled */ -#define nDMAPMEN0 0x0 #define DMAPMEN1 0x2000000 /* DMA1 Pattern Matching Enabled */ -#define nDMAPMEN1 0x0 #define DMAPMEN2 0x4000000 /* DMA2 Pattern Matching Enabled */ -#define nDMAPMEN2 0x0 #define DMAPMEN3 0x8000000 /* DMA3 Pattern Matching Enabled */ -#define nDMAPMEN3 0x0 #define DMAPMEN4 0x10000000 /* DMA4 Pattern Matching Enabled */ -#define nDMAPMEN4 0x0 #define DMAPMEN5 0x20000000 /* DMA5 Pattern Matching Enabled */ -#define nDMAPMEN5 0x0 #define DMAPMEN6 0x40000000 /* DMA6 Pattern Matching Enabled */ -#define nDMAPMEN6 0x0 #define DMAPMEN7 0x80000000 /* DMA7 Pattern Matching Enabled */ -#define nDMAPMEN7 0x0 /* Bit masks for MXVR_INT_STAT_0 */ #define NI2A 0x1 /* Network Inactive to Active */ -#define nNI2A 0x0 #define NA2I 0x2 /* Network Active to Inactive */ -#define nNA2I 0x0 #define SBU2L 0x4 /* Super Block Unlock to Lock */ -#define nSBU2L 0x0 #define SBL2U 0x8 /* Super Block Lock to Unlock */ -#define nSBL2U 0x0 #define PRU 0x10 /* Position Register Updated */ -#define nPRU 0x0 #define MPRU 0x20 /* Maximum Position Register Updated */ -#define nMPRU 0x0 #define DRU 0x40 /* Delay Register Updated */ -#define nDRU 0x0 #define MDRU 0x80 /* Maximum Delay Register Updated */ -#define nMDRU 0x0 #define SBU 0x100 /* Synchronous Boundary Updated */ -#define nSBU 0x0 #define ATU 0x200 /* Allocation Table Updated */ -#define nATU 0x0 #define FCZ0 0x400 /* Frame Counter 0 Zero */ -#define nFCZ0 0x0 #define FCZ1 0x800 /* Frame Counter 1 Zero */ -#define nFCZ1 0x0 #define PERR 0x1000 /* Parity Error */ -#define nPERR 0x0 #define MH2L 0x2000 /* MRXONB High to Low */ -#define nMH2L 0x0 #define ML2H 0x4000 /* MRXONB Low to High */ -#define nML2H 0x0 #define WUP 0x8000 /* Wake-Up Preamble Received */ -#define nWUP 0x0 #define FU2L 0x10000 /* Frame Unlock to Lock */ -#define nFU2L 0x0 #define FL2U 0x20000 /* Frame Lock to Unlock */ -#define nFL2U 0x0 #define BU2L 0x40000 /* Block Unlock to Lock */ -#define nBU2L 0x0 #define BL2U 0x80000 /* Block Lock to Unlock */ -#define nBL2U 0x0 #define OBERR 0x100000 /* DMA Out of Bounds Error */ -#define nOBERR 0x0 #define PFL 0x200000 /* PLL Frequency Locked */ -#define nPFL 0x0 #define SCZ 0x400000 /* System Clock Counter Zero */ -#define nSCZ 0x0 #define FERR 0x800000 /* FIFO Error */ -#define nFERR 0x0 #define CMR 0x1000000 /* Control Message Received */ -#define nCMR 0x0 #define CMROF 0x2000000 /* Control Message Receive Buffer Overflow */ -#define nCMROF 0x0 #define CMTS 0x4000000 /* Control Message Transmit Buffer Successfully Sent */ -#define nCMTS 0x0 #define CMTC 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled */ -#define nCMTC 0x0 #define RWRC 0x10000000 /* Remote Write Control Message Completed */ -#define nRWRC 0x0 #define BCZ 0x20000000 /* Block Counter Zero */ -#define nBCZ 0x0 #define BMERR 0x40000000 /* Biphase Mark Coding Error */ -#define nBMERR 0x0 #define DERR 0x80000000 /* DMA Error */ -#define nDERR 0x0 /* Bit masks for MXVR_INT_STAT_1 */ #define HDONE0 0x1 /* DMA0 Half Done */ -#define nHDONE0 0x0 #define DONE0 0x2 /* DMA0 Done */ -#define nDONE0 0x0 #define APR 0x4 /* Asynchronous Packet Received */ -#define nAPR 0x0 #define APROF 0x8 /* Asynchronous Packet Receive Buffer Overflow */ -#define nAPROF 0x0 #define HDONE1 0x10 /* DMA1 Half Done */ -#define nHDONE1 0x0 #define DONE1 0x20 /* DMA1 Done */ -#define nDONE1 0x0 #define APTS 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent */ -#define nAPTS 0x0 #define APTC 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled */ -#define nAPTC 0x0 #define HDONE2 0x100 /* DMA2 Half Done */ -#define nHDONE2 0x0 #define DONE2 0x200 /* DMA2 Done */ -#define nDONE2 0x0 #define APRCE 0x400 /* Asynchronous Packet Receive CRC Error */ -#define nAPRCE 0x0 #define APRPE 0x800 /* Asynchronous Packet Receive Packet Error */ -#define nAPRPE 0x0 #define HDONE3 0x1000 /* DMA3 Half Done */ -#define nHDONE3 0x0 #define DONE3 0x2000 /* DMA3 Done */ -#define nDONE3 0x0 #define HDONE4 0x10000 /* DMA4 Half Done */ -#define nHDONE4 0x0 #define DONE4 0x20000 /* DMA4 Done */ -#define nDONE4 0x0 #define HDONE5 0x100000 /* DMA5 Half Done */ -#define nHDONE5 0x0 #define DONE5 0x200000 /* DMA5 Done */ -#define nDONE5 0x0 #define HDONE6 0x1000000 /* DMA6 Half Done */ -#define nHDONE6 0x0 #define DONE6 0x2000000 /* DMA6 Done */ -#define nDONE6 0x0 #define HDONE7 0x10000000 /* DMA7 Half Done */ -#define nHDONE7 0x0 #define DONE7 0x20000000 /* DMA7 Done */ -#define nDONE7 0x0 /* Bit masks for MXVR_INT_EN_0 */ #define NI2AEN 0x1 /* Network Inactive to Active Interrupt Enable */ -#define nNI2AEN 0x0 #define NA2IEN 0x2 /* Network Active to Inactive Interrupt Enable */ -#define nNA2IEN 0x0 #define SBU2LEN 0x4 /* Super Block Unlock to Lock Interrupt Enable */ -#define nSBU2LEN 0x0 #define SBL2UEN 0x8 /* Super Block Lock to Unlock Interrupt Enable */ -#define nSBL2UEN 0x0 #define PRUEN 0x10 /* Position Register Updated Interrupt Enable */ -#define nPRUEN 0x0 #define MPRUEN 0x20 /* Maximum Position Register Updated Interrupt Enable */ -#define nMPRUEN 0x0 #define DRUEN 0x40 /* Delay Register Updated Interrupt Enable */ -#define nDRUEN 0x0 #define MDRUEN 0x80 /* Maximum Delay Register Updated Interrupt Enable */ -#define nMDRUEN 0x0 #define SBUEN 0x100 /* Synchronous Boundary Updated Interrupt Enable */ -#define nSBUEN 0x0 #define ATUEN 0x200 /* Allocation Table Updated Interrupt Enable */ -#define nATUEN 0x0 #define FCZ0EN 0x400 /* Frame Counter 0 Zero Interrupt Enable */ -#define nFCZ0EN 0x0 #define FCZ1EN 0x800 /* Frame Counter 1 Zero Interrupt Enable */ -#define nFCZ1EN 0x0 #define PERREN 0x1000 /* Parity Error Interrupt Enable */ -#define nPERREN 0x0 #define MH2LEN 0x2000 /* MRXONB High to Low Interrupt Enable */ -#define nMH2LEN 0x0 #define ML2HEN 0x4000 /* MRXONB Low to High Interrupt Enable */ -#define nML2HEN 0x0 #define WUPEN 0x8000 /* Wake-Up Preamble Received Interrupt Enable */ -#define nWUPEN 0x0 #define FU2LEN 0x10000 /* Frame Unlock to Lock Interrupt Enable */ -#define nFU2LEN 0x0 #define FL2UEN 0x20000 /* Frame Lock to Unlock Interrupt Enable */ -#define nFL2UEN 0x0 #define BU2LEN 0x40000 /* Block Unlock to Lock Interrupt Enable */ -#define nBU2LEN 0x0 #define BL2UEN 0x80000 /* Block Lock to Unlock Interrupt Enable */ -#define nBL2UEN 0x0 #define OBERREN 0x100000 /* DMA Out of Bounds Error Interrupt Enable */ -#define nOBERREN 0x0 #define PFLEN 0x200000 /* PLL Frequency Locked Interrupt Enable */ -#define nPFLEN 0x0 #define SCZEN 0x400000 /* System Clock Counter Zero Interrupt Enable */ -#define nSCZEN 0x0 #define FERREN 0x800000 /* FIFO Error Interrupt Enable */ -#define nFERREN 0x0 #define CMREN 0x1000000 /* Control Message Received Interrupt Enable */ -#define nCMREN 0x0 #define CMROFEN 0x2000000 /* Control Message Receive Buffer Overflow Interrupt Enable */ -#define nCMROFEN 0x0 #define CMTSEN 0x4000000 /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */ -#define nCMTSEN 0x0 #define CMTCEN 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */ -#define nCMTCEN 0x0 #define RWRCEN 0x10000000 /* Remote Write Control Message Completed Interrupt Enable */ -#define nRWRCEN 0x0 #define BCZEN 0x20000000 /* Block Counter Zero Interrupt Enable */ -#define nBCZEN 0x0 #define BMERREN 0x40000000 /* Biphase Mark Coding Error Interrupt Enable */ -#define nBMERREN 0x0 #define DERREN 0x80000000 /* DMA Error Interrupt Enable */ -#define nDERREN 0x0 /* Bit masks for MXVR_INT_EN_1 */ #define HDONEEN0 0x1 /* DMA0 Half Done Interrupt Enable */ -#define nHDONEEN0 0x0 #define DONEEN0 0x2 /* DMA0 Done Interrupt Enable */ -#define nDONEEN0 0x0 #define APREN 0x4 /* Asynchronous Packet Received Interrupt Enable */ -#define nAPREN 0x0 #define APROFEN 0x8 /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */ -#define nAPROFEN 0x0 #define HDONEEN1 0x10 /* DMA1 Half Done Interrupt Enable */ -#define nHDONEEN1 0x0 #define DONEEN1 0x20 /* DMA1 Done Interrupt Enable */ -#define nDONEEN1 0x0 #define APTSEN 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */ -#define nAPTSEN 0x0 #define APTCEN 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */ -#define nAPTCEN 0x0 #define HDONEEN2 0x100 /* DMA2 Half Done Interrupt Enable */ -#define nHDONEEN2 0x0 #define DONEEN2 0x200 /* DMA2 Done Interrupt Enable */ -#define nDONEEN2 0x0 #define APRCEEN 0x400 /* Asynchronous Packet Receive CRC Error Interrupt Enable */ -#define nAPRCEEN 0x0 #define APRPEEN 0x800 /* Asynchronous Packet Receive Packet Error Interrupt Enable */ -#define nAPRPEEN 0x0 #define HDONEEN3 0x1000 /* DMA3 Half Done Interrupt Enable */ -#define nHDONEEN3 0x0 #define DONEEN3 0x2000 /* DMA3 Done Interrupt Enable */ -#define nDONEEN3 0x0 #define HDONEEN4 0x10000 /* DMA4 Half Done Interrupt Enable */ -#define nHDONEEN4 0x0 #define DONEEN4 0x20000 /* DMA4 Done Interrupt Enable */ -#define nDONEEN4 0x0 #define HDONEEN5 0x100000 /* DMA5 Half Done Interrupt Enable */ -#define nHDONEEN5 0x0 #define DONEEN5 0x200000 /* DMA5 Done Interrupt Enable */ -#define nDONEEN5 0x0 #define HDONEEN6 0x1000000 /* DMA6 Half Done Interrupt Enable */ -#define nHDONEEN6 0x0 #define DONEEN6 0x2000000 /* DMA6 Done Interrupt Enable */ -#define nDONEEN6 0x0 #define HDONEEN7 0x10000000 /* DMA7 Half Done Interrupt Enable */ -#define nHDONEEN7 0x0 #define DONEEN7 0x20000000 /* DMA7 Done Interrupt Enable */ -#define nDONEEN7 0x0 /* Bit masks for MXVR_POSITION */ #define POSITION 0x3f /* Node Position */ #define PVALID 0x8000 /* Node Position Valid */ -#define nPVALID 0x0 /* Bit masks for MXVR_MAX_POSITION */ #define MPOSITION 0x3f /* Maximum Node Position */ #define MPVALID 0x8000 /* Maximum Node Position Valid */ -#define nMPVALID 0x0 /* Bit masks for MXVR_DELAY */ #define DELAY 0x3f /* Node Frame Delay */ #define DVALID 0x8000 /* Node Frame Delay Valid */ -#define nDVALID 0x0 /* Bit masks for MXVR_MAX_DELAY */ #define MDELAY 0x3f /* Maximum Node Frame Delay */ #define MDVALID 0x8000 /* Maximum Node Frame Delay Valid */ -#define nMDVALID 0x0 /* Bit masks for MXVR_LADDR */ #define LADDR 0xffff /* Logical Address */ #define LVALID 0x80000000 /* Logical Address Valid */ -#define nLVALID 0x0 /* Bit masks for MXVR_GADDR */ #define GADDRL 0xff /* Group Address Lower Byte */ #define GVALID 0x8000 /* Group Address Valid */ -#define nGVALID 0x0 /* Bit masks for MXVR_AADDR */ #define AADDR 0xffff /* Alternate Address */ #define AVALID 0x80000000 /* Alternate Address Valid */ -#define nAVALID 0x0 /* Bit masks for MXVR_ALLOC_0 */ #define CL0 0x7f /* Channel 0 Connection Label */ #define CIU0 0x80 /* Channel 0 In Use */ -#define nCIU0 0x0 #define CL1 0x7f00 /* Channel 0 Connection Label */ #define CIU1 0x8000 /* Channel 0 In Use */ -#define nCIU1 0x0 #define CL2 0x7f0000 /* Channel 0 Connection Label */ #define CIU2 0x800000 /* Channel 0 In Use */ -#define nCIU2 0x0 #define CL3 0x7f000000 /* Channel 0 Connection Label */ #define CIU3 0x80000000 /* Channel 0 In Use */ -#define nCIU3 0x0 /* Bit masks for MXVR_ALLOC_1 */ #define CL4 0x7f /* Channel 4 Connection Label */ #define CIU4 0x80 /* Channel 4 In Use */ -#define nCIU4 0x0 #define CL5 0x7f00 /* Channel 5 Connection Label */ #define CIU5 0x8000 /* Channel 5 In Use */ -#define nCIU5 0x0 #define CL6 0x7f0000 /* Channel 6 Connection Label */ #define CIU6 0x800000 /* Channel 6 In Use */ -#define nCIU6 0x0 #define CL7 0x7f000000 /* Channel 7 Connection Label */ #define CIU7 0x80000000 /* Channel 7 In Use */ -#define nCIU7 0x0 /* Bit masks for MXVR_ALLOC_2 */ #define CL8 0x7f /* Channel 8 Connection Label */ #define CIU8 0x80 /* Channel 8 In Use */ -#define nCIU8 0x0 #define CL9 0x7f00 /* Channel 9 Connection Label */ #define CIU9 0x8000 /* Channel 9 In Use */ -#define nCIU9 0x0 #define CL10 0x7f0000 /* Channel 10 Connection Label */ #define CIU10 0x800000 /* Channel 10 In Use */ -#define nCIU10 0x0 #define CL11 0x7f000000 /* Channel 11 Connection Label */ #define CIU11 0x80000000 /* Channel 11 In Use */ -#define nCIU11 0x0 /* Bit masks for MXVR_ALLOC_3 */ #define CL12 0x7f /* Channel 12 Connection Label */ #define CIU12 0x80 /* Channel 12 In Use */ -#define nCIU12 0x0 #define CL13 0x7f00 /* Channel 13 Connection Label */ #define CIU13 0x8000 /* Channel 13 In Use */ -#define nCIU13 0x0 #define CL14 0x7f0000 /* Channel 14 Connection Label */ #define CIU14 0x800000 /* Channel 14 In Use */ -#define nCIU14 0x0 #define CL15 0x7f000000 /* Channel 15 Connection Label */ #define CIU15 0x80000000 /* Channel 15 In Use */ -#define nCIU15 0x0 /* Bit masks for MXVR_ALLOC_4 */ #define CL16 0x7f /* Channel 16 Connection Label */ #define CIU16 0x80 /* Channel 16 In Use */ -#define nCIU16 0x0 #define CL17 0x7f00 /* Channel 17 Connection Label */ #define CIU17 0x8000 /* Channel 17 In Use */ -#define nCIU17 0x0 #define CL18 0x7f0000 /* Channel 18 Connection Label */ #define CIU18 0x800000 /* Channel 18 In Use */ -#define nCIU18 0x0 #define CL19 0x7f000000 /* Channel 19 Connection Label */ #define CIU19 0x80000000 /* Channel 19 In Use */ -#define nCIU19 0x0 /* Bit masks for MXVR_ALLOC_5 */ #define CL20 0x7f /* Channel 20 Connection Label */ #define CIU20 0x80 /* Channel 20 In Use */ -#define nCIU20 0x0 #define CL21 0x7f00 /* Channel 21 Connection Label */ #define CIU21 0x8000 /* Channel 21 In Use */ -#define nCIU21 0x0 #define CL22 0x7f0000 /* Channel 22 Connection Label */ #define CIU22 0x800000 /* Channel 22 In Use */ -#define nCIU22 0x0 #define CL23 0x7f000000 /* Channel 23 Connection Label */ #define CIU23 0x80000000 /* Channel 23 In Use */ -#define nCIU23 0x0 /* Bit masks for MXVR_ALLOC_6 */ #define CL24 0x7f /* Channel 24 Connection Label */ #define CIU24 0x80 /* Channel 24 In Use */ -#define nCIU24 0x0 #define CL25 0x7f00 /* Channel 25 Connection Label */ #define CIU25 0x8000 /* Channel 25 In Use */ -#define nCIU25 0x0 #define CL26 0x7f0000 /* Channel 26 Connection Label */ #define CIU26 0x800000 /* Channel 26 In Use */ -#define nCIU26 0x0 #define CL27 0x7f000000 /* Channel 27 Connection Label */ #define CIU27 0x80000000 /* Channel 27 In Use */ -#define nCIU27 0x0 /* Bit masks for MXVR_ALLOC_7 */ #define CL28 0x7f /* Channel 28 Connection Label */ #define CIU28 0x80 /* Channel 28 In Use */ -#define nCIU28 0x0 #define CL29 0x7f00 /* Channel 29 Connection Label */ #define CIU29 0x8000 /* Channel 29 In Use */ -#define nCIU29 0x0 #define CL30 0x7f0000 /* Channel 30 Connection Label */ #define CIU30 0x800000 /* Channel 30 In Use */ -#define nCIU30 0x0 #define CL31 0x7f000000 /* Channel 31 Connection Label */ #define CIU31 0x80000000 /* Channel 31 In Use */ -#define nCIU31 0x0 /* Bit masks for MXVR_ALLOC_8 */ #define CL32 0x7f /* Channel 32 Connection Label */ #define CIU32 0x80 /* Channel 32 In Use */ -#define nCIU32 0x0 #define CL33 0x7f00 /* Channel 33 Connection Label */ #define CIU33 0x8000 /* Channel 33 In Use */ -#define nCIU33 0x0 #define CL34 0x7f0000 /* Channel 34 Connection Label */ #define CIU34 0x800000 /* Channel 34 In Use */ -#define nCIU34 0x0 #define CL35 0x7f000000 /* Channel 35 Connection Label */ #define CIU35 0x80000000 /* Channel 35 In Use */ -#define nCIU35 0x0 /* Bit masks for MXVR_ALLOC_9 */ #define CL36 0x7f /* Channel 36 Connection Label */ #define CIU36 0x80 /* Channel 36 In Use */ -#define nCIU36 0x0 #define CL37 0x7f00 /* Channel 37 Connection Label */ #define CIU37 0x8000 /* Channel 37 In Use */ -#define nCIU37 0x0 #define CL38 0x7f0000 /* Channel 38 Connection Label */ #define CIU38 0x800000 /* Channel 38 In Use */ -#define nCIU38 0x0 #define CL39 0x7f000000 /* Channel 39 Connection Label */ #define CIU39 0x80000000 /* Channel 39 In Use */ -#define nCIU39 0x0 /* Bit masks for MXVR_ALLOC_10 */ #define CL40 0x7f /* Channel 40 Connection Label */ #define CIU40 0x80 /* Channel 40 In Use */ -#define nCIU40 0x0 #define CL41 0x7f00 /* Channel 41 Connection Label */ #define CIU41 0x8000 /* Channel 41 In Use */ -#define nCIU41 0x0 #define CL42 0x7f0000 /* Channel 42 Connection Label */ #define CIU42 0x800000 /* Channel 42 In Use */ -#define nCIU42 0x0 #define CL43 0x7f000000 /* Channel 43 Connection Label */ #define CIU43 0x80000000 /* Channel 43 In Use */ -#define nCIU43 0x0 /* Bit masks for MXVR_ALLOC_11 */ #define CL44 0x7f /* Channel 44 Connection Label */ #define CIU44 0x80 /* Channel 44 In Use */ -#define nCIU44 0x0 #define CL45 0x7f00 /* Channel 45 Connection Label */ #define CIU45 0x8000 /* Channel 45 In Use */ -#define nCIU45 0x0 #define CL46 0x7f0000 /* Channel 46 Connection Label */ #define CIU46 0x800000 /* Channel 46 In Use */ -#define nCIU46 0x0 #define CL47 0x7f000000 /* Channel 47 Connection Label */ #define CIU47 0x80000000 /* Channel 47 In Use */ -#define nCIU47 0x0 /* Bit masks for MXVR_ALLOC_12 */ #define CL48 0x7f /* Channel 48 Connection Label */ #define CIU48 0x80 /* Channel 48 In Use */ -#define nCIU48 0x0 #define CL49 0x7f00 /* Channel 49 Connection Label */ #define CIU49 0x8000 /* Channel 49 In Use */ -#define nCIU49 0x0 #define CL50 0x7f0000 /* Channel 50 Connection Label */ #define CIU50 0x800000 /* Channel 50 In Use */ -#define nCIU50 0x0 #define CL51 0x7f000000 /* Channel 51 Connection Label */ #define CIU51 0x80000000 /* Channel 51 In Use */ -#define nCIU51 0x0 /* Bit masks for MXVR_ALLOC_13 */ #define CL52 0x7f /* Channel 52 Connection Label */ #define CIU52 0x80 /* Channel 52 In Use */ -#define nCIU52 0x0 #define CL53 0x7f00 /* Channel 53 Connection Label */ #define CIU53 0x8000 /* Channel 53 In Use */ -#define nCIU53 0x0 #define CL54 0x7f0000 /* Channel 54 Connection Label */ #define CIU54 0x800000 /* Channel 54 In Use */ -#define nCIU54 0x0 #define CL55 0x7f000000 /* Channel 55 Connection Label */ #define CIU55 0x80000000 /* Channel 55 In Use */ -#define nCIU55 0x0 /* Bit masks for MXVR_ALLOC_14 */ #define CL56 0x7f /* Channel 56 Connection Label */ #define CIU56 0x80 /* Channel 56 In Use */ -#define nCIU56 0x0 #define CL57 0x7f00 /* Channel 57 Connection Label */ #define CIU57 0x8000 /* Channel 57 In Use */ -#define nCIU57 0x0 #define CL58 0x7f0000 /* Channel 58 Connection Label */ #define CIU58 0x800000 /* Channel 58 In Use */ -#define nCIU58 0x0 #define CL59 0x7f000000 /* Channel 59 Connection Label */ #define CIU59 0x80000000 /* Channel 59 In Use */ -#define nCIU59 0x0 /* MXVR_SYNC_LCHAN_0 Masks */ @@ -1926,19 +1669,13 @@ /* Bit masks for MXVR_DMAx_CONFIG */ #define MDMAEN 0x1 /* DMA Channel Enable */ -#define nMDMAEN 0x0 #define DD 0x2 /* DMA Channel Direction */ -#define nDD 0x0 #define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */ -#define nBY4SWAPEN 0x0 #define LCHAN 0x3c0 /* DMA Channel Logical Channel */ #define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */ -#define nBITSWAPEN 0x0 #define BY2SWAPEN 0x800 /* DMA Channel Two Byte Swap Enable */ -#define nBY2SWAPEN 0x0 #define MFLOW 0x7000 /* DMA Channel Operation Flow */ #define FIXEDPM 0x80000 /* DMA Channel Fixed Pattern Matching Select */ -#define nFIXEDPM 0x0 #define STARTPAT 0x300000 /* DMA Channel Start Pattern Select */ #define STOPPAT 0xc00000 /* DMA Channel Stop Pattern Select */ #define COUNTPOS 0x1c000000 /* DMA Channel Count Position */ @@ -1946,94 +1683,71 @@ /* Bit masks for MXVR_AP_CTL */ #define STARTAP 0x1 /* Start Asynchronous Packet Transmission */ -#define nSTARTAP 0x0 #define CANCELAP 0x2 /* Cancel Asynchronous Packet Transmission */ -#define nCANCELAP 0x0 #define RESETAP 0x4 /* Reset Asynchronous Packet Arbitration */ -#define nRESETAP 0x0 #define APRBE0 0x4000 /* Asynchronous Packet Receive Buffer Entry 0 */ -#define nAPRBE0 0x0 #define APRBE1 0x8000 /* Asynchronous Packet Receive Buffer Entry 1 */ -#define nAPRBE1 0x0 /* Bit masks for MXVR_APRB_START_ADDR */ -#define MXVR_APRB_START_ADDR 0x1fffffe /* Asynchronous Packet Receive Buffer Start Address */ +#define MXVR_APRB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Receive Buffer Start Address */ /* Bit masks for MXVR_APRB_CURR_ADDR */ -#define MXVR_APRB_CURR_ADDR 0xffffffff /* Asynchronous Packet Receive Buffer Current Address */ +#define MXVR_APRB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Receive Buffer Current Address */ /* Bit masks for MXVR_APTB_START_ADDR */ -#define MXVR_APTB_START_ADDR 0x1fffffe /* Asynchronous Packet Transmit Buffer Start Address */ +#define MXVR_APTB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Transmit Buffer Start Address */ /* Bit masks for MXVR_APTB_CURR_ADDR */ -#define MXVR_APTB_CURR_ADDR 0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */ +#define MXVR_APTB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */ /* Bit masks for MXVR_CM_CTL */ #define STARTCM 0x1 /* Start Control Message Transmission */ -#define nSTARTCM 0x0 #define CANCELCM 0x2 /* Cancel Control Message Transmission */ -#define nCANCELCM 0x0 #define CMRBE0 0x10000 /* Control Message Receive Buffer Entry 0 */ -#define nCMRBE0 0x0 #define CMRBE1 0x20000 /* Control Message Receive Buffer Entry 1 */ -#define nCMRBE1 0x0 #define CMRBE2 0x40000 /* Control Message Receive Buffer Entry 2 */ -#define nCMRBE2 0x0 #define CMRBE3 0x80000 /* Control Message Receive Buffer Entry 3 */ -#define nCMRBE3 0x0 #define CMRBE4 0x100000 /* Control Message Receive Buffer Entry 4 */ -#define nCMRBE4 0x0 #define CMRBE5 0x200000 /* Control Message Receive Buffer Entry 5 */ -#define nCMRBE5 0x0 #define CMRBE6 0x400000 /* Control Message Receive Buffer Entry 6 */ -#define nCMRBE6 0x0 #define CMRBE7 0x800000 /* Control Message Receive Buffer Entry 7 */ -#define nCMRBE7 0x0 #define CMRBE8 0x1000000 /* Control Message Receive Buffer Entry 8 */ -#define nCMRBE8 0x0 #define CMRBE9 0x2000000 /* Control Message Receive Buffer Entry 9 */ -#define nCMRBE9 0x0 #define CMRBE10 0x4000000 /* Control Message Receive Buffer Entry 10 */ -#define nCMRBE10 0x0 #define CMRBE11 0x8000000 /* Control Message Receive Buffer Entry 11 */ -#define nCMRBE11 0x0 #define CMRBE12 0x10000000 /* Control Message Receive Buffer Entry 12 */ -#define nCMRBE12 0x0 #define CMRBE13 0x20000000 /* Control Message Receive Buffer Entry 13 */ -#define nCMRBE13 0x0 #define CMRBE14 0x40000000 /* Control Message Receive Buffer Entry 14 */ -#define nCMRBE14 0x0 #define CMRBE15 0x80000000 /* Control Message Receive Buffer Entry 15 */ -#define nCMRBE15 0x0 /* Bit masks for MXVR_CMRB_START_ADDR */ -#define MXVR_CMRB_START_ADDR 0x1fffffe /* Control Message Receive Buffer Start Address */ +#define MXVR_CMRB_START_ADDR_MASK 0x1fffffe /* Control Message Receive Buffer Start Address */ /* Bit masks for MXVR_CMRB_CURR_ADDR */ -#define MXVR_CMRB_CURR_ADDR 0xffffffff /* Control Message Receive Buffer Current Address */ +#define MXVR_CMRB_CURR_ADDR_MASK 0xffffffff /* Control Message Receive Buffer Current Address */ /* Bit masks for MXVR_CMTB_START_ADDR */ -#define MXVR_CMTB_START_ADDR 0x1fffffe /* Control Message Transmit Buffer Start Address */ +#define MXVR_CMTB_START_ADDR_MASK 0x1fffffe /* Control Message Transmit Buffer Start Address */ /* Bit masks for MXVR_CMTB_CURR_ADDR */ -#define MXVR_CMTB_CURR_ADDR 0xffffffff /* Control Message Transmit Buffer Current Address */ +#define MXVR_CMTB_CURR_ADDR_MASK 0xffffffff /* Control Message Transmit Buffer Current Address */ /* Bit masks for MXVR_RRDB_START_ADDR */ -#define MXVR_RRDB_START_ADDR 0x1fffffe /* Remote Read Buffer Start Address */ +#define MXVR_RRDB_START_ADDR_MASK 0x1fffffe /* Remote Read Buffer Start Address */ /* Bit masks for MXVR_RRDB_CURR_ADDR */ -#define MXVR_RRDB_CURR_ADDR 0xffffffff /* Remote Read Buffer Current Address */ +#define MXVR_RRDB_CURR_ADDR_MASK 0xffffffff /* Remote Read Buffer Current Address */ /* Bit masks for MXVR_PAT_DATAx */ @@ -2045,136 +1759,72 @@ /* Bit masks for MXVR_PAT_EN_0 */ #define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */ -#define nMATCH_EN_0_0 0x0 #define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */ -#define nMATCH_EN_0_1 0x0 #define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */ -#define nMATCH_EN_0_2 0x0 #define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */ -#define nMATCH_EN_0_3 0x0 #define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */ -#define nMATCH_EN_0_4 0x0 #define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */ -#define nMATCH_EN_0_5 0x0 #define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */ -#define nMATCH_EN_0_6 0x0 #define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */ -#define nMATCH_EN_0_7 0x0 #define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */ -#define nMATCH_EN_1_0 0x0 #define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */ -#define nMATCH_EN_1_1 0x0 #define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */ -#define nMATCH_EN_1_2 0x0 #define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */ -#define nMATCH_EN_1_3 0x0 #define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */ -#define nMATCH_EN_1_4 0x0 #define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */ -#define nMATCH_EN_1_5 0x0 #define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */ -#define nMATCH_EN_1_6 0x0 #define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */ -#define nMATCH_EN_1_7 0x0 #define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */ -#define nMATCH_EN_2_0 0x0 #define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */ -#define nMATCH_EN_2_1 0x0 #define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */ -#define nMATCH_EN_2_2 0x0 #define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */ -#define nMATCH_EN_2_3 0x0 #define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */ -#define nMATCH_EN_2_4 0x0 #define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */ -#define nMATCH_EN_2_5 0x0 #define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */ -#define nMATCH_EN_2_6 0x0 #define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */ -#define nMATCH_EN_2_7 0x0 #define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */ -#define nMATCH_EN_3_0 0x0 #define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */ -#define nMATCH_EN_3_1 0x0 #define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */ -#define nMATCH_EN_3_2 0x0 #define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */ -#define nMATCH_EN_3_3 0x0 #define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */ -#define nMATCH_EN_3_4 0x0 #define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */ -#define nMATCH_EN_3_5 0x0 #define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */ -#define nMATCH_EN_3_6 0x0 #define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */ -#define nMATCH_EN_3_7 0x0 /* Bit masks for MXVR_PAT_EN_1 */ #define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */ -#define nMATCH_EN_0_0 0x0 #define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */ -#define nMATCH_EN_0_1 0x0 #define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */ -#define nMATCH_EN_0_2 0x0 #define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */ -#define nMATCH_EN_0_3 0x0 #define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */ -#define nMATCH_EN_0_4 0x0 #define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */ -#define nMATCH_EN_0_5 0x0 #define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */ -#define nMATCH_EN_0_6 0x0 #define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */ -#define nMATCH_EN_0_7 0x0 #define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */ -#define nMATCH_EN_1_0 0x0 #define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */ -#define nMATCH_EN_1_1 0x0 #define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */ -#define nMATCH_EN_1_2 0x0 #define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */ -#define nMATCH_EN_1_3 0x0 #define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */ -#define nMATCH_EN_1_4 0x0 #define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */ -#define nMATCH_EN_1_5 0x0 #define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */ -#define nMATCH_EN_1_6 0x0 #define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */ -#define nMATCH_EN_1_7 0x0 #define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */ -#define nMATCH_EN_2_0 0x0 #define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */ -#define nMATCH_EN_2_1 0x0 #define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */ -#define nMATCH_EN_2_2 0x0 #define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */ -#define nMATCH_EN_2_3 0x0 #define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */ -#define nMATCH_EN_2_4 0x0 #define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */ -#define nMATCH_EN_2_5 0x0 #define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */ -#define nMATCH_EN_2_6 0x0 #define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */ -#define nMATCH_EN_2_7 0x0 #define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */ -#define nMATCH_EN_3_0 0x0 #define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */ -#define nMATCH_EN_3_1 0x0 #define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */ -#define nMATCH_EN_3_2 0x0 #define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */ -#define nMATCH_EN_3_3 0x0 #define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */ -#define nMATCH_EN_3_4 0x0 #define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */ -#define nMATCH_EN_3_5 0x0 #define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */ -#define nMATCH_EN_3_6 0x0 #define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */ -#define nMATCH_EN_3_7 0x0 /* Bit masks for MXVR_FRAME_CNT_0 */ @@ -2188,226 +1838,166 @@ #define TX_CH0 0x3f /* Transmit Channel 0 */ #define MUTE_CH0 0x80 /* Mute Channel 0 */ -#define nMUTE_CH0 0x0 #define TX_CH1 0x3f00 /* Transmit Channel 0 */ #define MUTE_CH1 0x8000 /* Mute Channel 0 */ -#define nMUTE_CH1 0x0 #define TX_CH2 0x3f0000 /* Transmit Channel 0 */ #define MUTE_CH2 0x800000 /* Mute Channel 0 */ -#define nMUTE_CH2 0x0 #define TX_CH3 0x3f000000 /* Transmit Channel 0 */ #define MUTE_CH3 0x80000000 /* Mute Channel 0 */ -#define nMUTE_CH3 0x0 /* Bit masks for MXVR_ROUTING_1 */ #define TX_CH4 0x3f /* Transmit Channel 4 */ #define MUTE_CH4 0x80 /* Mute Channel 4 */ -#define nMUTE_CH4 0x0 #define TX_CH5 0x3f00 /* Transmit Channel 5 */ #define MUTE_CH5 0x8000 /* Mute Channel 5 */ -#define nMUTE_CH5 0x0 #define TX_CH6 0x3f0000 /* Transmit Channel 6 */ #define MUTE_CH6 0x800000 /* Mute Channel 6 */ -#define nMUTE_CH6 0x0 #define TX_CH7 0x3f000000 /* Transmit Channel 7 */ #define MUTE_CH7 0x80000000 /* Mute Channel 7 */ -#define nMUTE_CH7 0x0 /* Bit masks for MXVR_ROUTING_2 */ #define TX_CH8 0x3f /* Transmit Channel 8 */ #define MUTE_CH8 0x80 /* Mute Channel 8 */ -#define nMUTE_CH8 0x0 #define TX_CH9 0x3f00 /* Transmit Channel 9 */ #define MUTE_CH9 0x8000 /* Mute Channel 9 */ -#define nMUTE_CH9 0x0 #define TX_CH10 0x3f0000 /* Transmit Channel 10 */ #define MUTE_CH10 0x800000 /* Mute Channel 10 */ -#define nMUTE_CH10 0x0 #define TX_CH11 0x3f000000 /* Transmit Channel 11 */ #define MUTE_CH11 0x80000000 /* Mute Channel 11 */ -#define nMUTE_CH11 0x0 /* Bit masks for MXVR_ROUTING_3 */ #define TX_CH12 0x3f /* Transmit Channel 12 */ #define MUTE_CH12 0x80 /* Mute Channel 12 */ -#define nMUTE_CH12 0x0 #define TX_CH13 0x3f00 /* Transmit Channel 13 */ #define MUTE_CH13 0x8000 /* Mute Channel 13 */ -#define nMUTE_CH13 0x0 #define TX_CH14 0x3f0000 /* Transmit Channel 14 */ #define MUTE_CH14 0x800000 /* Mute Channel 14 */ -#define nMUTE_CH14 0x0 #define TX_CH15 0x3f000000 /* Transmit Channel 15 */ #define MUTE_CH15 0x80000000 /* Mute Channel 15 */ -#define nMUTE_CH15 0x0 /* Bit masks for MXVR_ROUTING_4 */ #define TX_CH16 0x3f /* Transmit Channel 16 */ #define MUTE_CH16 0x80 /* Mute Channel 16 */ -#define nMUTE_CH16 0x0 #define TX_CH17 0x3f00 /* Transmit Channel 17 */ #define MUTE_CH17 0x8000 /* Mute Channel 17 */ -#define nMUTE_CH17 0x0 #define TX_CH18 0x3f0000 /* Transmit Channel 18 */ #define MUTE_CH18 0x800000 /* Mute Channel 18 */ -#define nMUTE_CH18 0x0 #define TX_CH19 0x3f000000 /* Transmit Channel 19 */ #define MUTE_CH19 0x80000000 /* Mute Channel 19 */ -#define nMUTE_CH19 0x0 /* Bit masks for MXVR_ROUTING_5 */ #define TX_CH20 0x3f /* Transmit Channel 20 */ #define MUTE_CH20 0x80 /* Mute Channel 20 */ -#define nMUTE_CH20 0x0 #define TX_CH21 0x3f00 /* Transmit Channel 21 */ #define MUTE_CH21 0x8000 /* Mute Channel 21 */ -#define nMUTE_CH21 0x0 #define TX_CH22 0x3f0000 /* Transmit Channel 22 */ #define MUTE_CH22 0x800000 /* Mute Channel 22 */ -#define nMUTE_CH22 0x0 #define TX_CH23 0x3f000000 /* Transmit Channel 23 */ #define MUTE_CH23 0x80000000 /* Mute Channel 23 */ -#define nMUTE_CH23 0x0 /* Bit masks for MXVR_ROUTING_6 */ #define TX_CH24 0x3f /* Transmit Channel 24 */ #define MUTE_CH24 0x80 /* Mute Channel 24 */ -#define nMUTE_CH24 0x0 #define TX_CH25 0x3f00 /* Transmit Channel 25 */ #define MUTE_CH25 0x8000 /* Mute Channel 25 */ -#define nMUTE_CH25 0x0 #define TX_CH26 0x3f0000 /* Transmit Channel 26 */ #define MUTE_CH26 0x800000 /* Mute Channel 26 */ -#define nMUTE_CH26 0x0 #define TX_CH27 0x3f000000 /* Transmit Channel 27 */ #define MUTE_CH27 0x80000000 /* Mute Channel 27 */ -#define nMUTE_CH27 0x0 /* Bit masks for MXVR_ROUTING_7 */ #define TX_CH28 0x3f /* Transmit Channel 28 */ #define MUTE_CH28 0x80 /* Mute Channel 28 */ -#define nMUTE_CH28 0x0 #define TX_CH29 0x3f00 /* Transmit Channel 29 */ #define MUTE_CH29 0x8000 /* Mute Channel 29 */ -#define nMUTE_CH29 0x0 #define TX_CH30 0x3f0000 /* Transmit Channel 30 */ #define MUTE_CH30 0x800000 /* Mute Channel 30 */ -#define nMUTE_CH30 0x0 #define TX_CH31 0x3f000000 /* Transmit Channel 31 */ #define MUTE_CH31 0x80000000 /* Mute Channel 31 */ -#define nMUTE_CH31 0x0 /* Bit masks for MXVR_ROUTING_8 */ #define TX_CH32 0x3f /* Transmit Channel 32 */ #define MUTE_CH32 0x80 /* Mute Channel 32 */ -#define nMUTE_CH32 0x0 #define TX_CH33 0x3f00 /* Transmit Channel 33 */ #define MUTE_CH33 0x8000 /* Mute Channel 33 */ -#define nMUTE_CH33 0x0 #define TX_CH34 0x3f0000 /* Transmit Channel 34 */ #define MUTE_CH34 0x800000 /* Mute Channel 34 */ -#define nMUTE_CH34 0x0 #define TX_CH35 0x3f000000 /* Transmit Channel 35 */ #define MUTE_CH35 0x80000000 /* Mute Channel 35 */ -#define nMUTE_CH35 0x0 /* Bit masks for MXVR_ROUTING_9 */ #define TX_CH36 0x3f /* Transmit Channel 36 */ #define MUTE_CH36 0x80 /* Mute Channel 36 */ -#define nMUTE_CH36 0x0 #define TX_CH37 0x3f00 /* Transmit Channel 37 */ #define MUTE_CH37 0x8000 /* Mute Channel 37 */ -#define nMUTE_CH37 0x0 #define TX_CH38 0x3f0000 /* Transmit Channel 38 */ #define MUTE_CH38 0x800000 /* Mute Channel 38 */ -#define nMUTE_CH38 0x0 #define TX_CH39 0x3f000000 /* Transmit Channel 39 */ #define MUTE_CH39 0x80000000 /* Mute Channel 39 */ -#define nMUTE_CH39 0x0 /* Bit masks for MXVR_ROUTING_10 */ #define TX_CH40 0x3f /* Transmit Channel 40 */ #define MUTE_CH40 0x80 /* Mute Channel 40 */ -#define nMUTE_CH40 0x0 #define TX_CH41 0x3f00 /* Transmit Channel 41 */ #define MUTE_CH41 0x8000 /* Mute Channel 41 */ -#define nMUTE_CH41 0x0 #define TX_CH42 0x3f0000 /* Transmit Channel 42 */ #define MUTE_CH42 0x800000 /* Mute Channel 42 */ -#define nMUTE_CH42 0x0 #define TX_CH43 0x3f000000 /* Transmit Channel 43 */ #define MUTE_CH43 0x80000000 /* Mute Channel 43 */ -#define nMUTE_CH43 0x0 /* Bit masks for MXVR_ROUTING_11 */ #define TX_CH44 0x3f /* Transmit Channel 44 */ #define MUTE_CH44 0x80 /* Mute Channel 44 */ -#define nMUTE_CH44 0x0 #define TX_CH45 0x3f00 /* Transmit Channel 45 */ #define MUTE_CH45 0x8000 /* Mute Channel 45 */ -#define nMUTE_CH45 0x0 #define TX_CH46 0x3f0000 /* Transmit Channel 46 */ #define MUTE_CH46 0x800000 /* Mute Channel 46 */ -#define nMUTE_CH46 0x0 #define TX_CH47 0x3f000000 /* Transmit Channel 47 */ #define MUTE_CH47 0x80000000 /* Mute Channel 47 */ -#define nMUTE_CH47 0x0 /* Bit masks for MXVR_ROUTING_12 */ #define TX_CH48 0x3f /* Transmit Channel 48 */ #define MUTE_CH48 0x80 /* Mute Channel 48 */ -#define nMUTE_CH48 0x0 #define TX_CH49 0x3f00 /* Transmit Channel 49 */ #define MUTE_CH49 0x8000 /* Mute Channel 49 */ -#define nMUTE_CH49 0x0 #define TX_CH50 0x3f0000 /* Transmit Channel 50 */ #define MUTE_CH50 0x800000 /* Mute Channel 50 */ -#define nMUTE_CH50 0x0 #define TX_CH51 0x3f000000 /* Transmit Channel 51 */ #define MUTE_CH51 0x80000000 /* Mute Channel 51 */ -#define nMUTE_CH51 0x0 /* Bit masks for MXVR_ROUTING_13 */ #define TX_CH52 0x3f /* Transmit Channel 52 */ #define MUTE_CH52 0x80 /* Mute Channel 52 */ -#define nMUTE_CH52 0x0 #define TX_CH53 0x3f00 /* Transmit Channel 53 */ #define MUTE_CH53 0x8000 /* Mute Channel 53 */ -#define nMUTE_CH53 0x0 #define TX_CH54 0x3f0000 /* Transmit Channel 54 */ #define MUTE_CH54 0x800000 /* Mute Channel 54 */ -#define nMUTE_CH54 0x0 #define TX_CH55 0x3f000000 /* Transmit Channel 55 */ #define MUTE_CH55 0x80000000 /* Mute Channel 55 */ -#define nMUTE_CH55 0x0 /* Bit masks for MXVR_ROUTING_14 */ #define TX_CH56 0x3f /* Transmit Channel 56 */ #define MUTE_CH56 0x80 /* Mute Channel 56 */ -#define nMUTE_CH56 0x0 #define TX_CH57 0x3f00 /* Transmit Channel 57 */ #define MUTE_CH57 0x8000 /* Mute Channel 57 */ -#define nMUTE_CH57 0x0 #define TX_CH58 0x3f0000 /* Transmit Channel 58 */ #define MUTE_CH58 0x800000 /* Mute Channel 58 */ -#define nMUTE_CH58 0x0 #define TX_CH59 0x3f000000 /* Transmit Channel 59 */ #define MUTE_CH59 0x80000000 /* Mute Channel 59 */ -#define nMUTE_CH59 0x0 /* Bit masks for MXVR_BLOCK_CNT */ @@ -2416,53 +2006,37 @@ /* Bit masks for MXVR_CLK_CTL */ #define MXTALCEN 0x1 /* MXVR Crystal Oscillator Clock Enable */ -#define nMXTALCEN 0x0 #define MXTALFEN 0x2 /* MXVR Crystal Oscillator Feedback Enable */ -#define nMXTALFEN 0x0 #define MXTALMUL 0x30 /* MXVR Crystal Multiplier */ #define CLKX3SEL 0x80 /* Clock Generation Source Select */ -#define nCLKX3SEL 0x0 #define MMCLKEN 0x100 /* Master Clock Enable */ -#define nMMCLKEN 0x0 #define MMCLKMUL 0x1e00 /* Master Clock Multiplication Factor */ #define PLLSMPS 0xe000 /* MXVR PLL State Machine Prescaler */ #define MBCLKEN 0x10000 /* Bit Clock Enable */ -#define nMBCLKEN 0x0 #define MBCLKDIV 0x1e0000 /* Bit Clock Divide Factor */ #define INVRX 0x800000 /* Invert Receive Data */ -#define nINVRX 0x0 #define MFSEN 0x1000000 /* Frame Sync Enable */ -#define nMFSEN 0x0 #define MFSDIV 0x1e000000 /* Frame Sync Divide Factor */ #define MFSSEL 0x60000000 /* Frame Sync Select */ #define MFSSYNC 0x80000000 /* Frame Sync Synchronization Select */ -#define nMFSSYNC 0x0 /* Bit masks for MXVR_CDRPLL_CTL */ #define CDRSMEN 0x1 /* MXVR CDRPLL State Machine Enable */ -#define nCDRSMEN 0x0 #define CDRRSTB 0x2 /* MXVR CDRPLL Reset */ -#define nCDRRSTB 0x0 #define CDRSVCO 0x4 /* MXVR CDRPLL Start VCO */ -#define nCDRSVCO 0x0 #define CDRMODE 0x8 /* MXVR CDRPLL CDR Mode Select */ -#define nCDRMODE 0x0 #define CDRSCNT 0x3f0 /* MXVR CDRPLL Start Counter */ #define CDRLCNT 0xfc00 /* MXVR CDRPLL Lock Counter */ #define CDRSHPSEL 0x3f0000 /* MXVR CDRPLL Shaper Select */ #define CDRSHPEN 0x800000 /* MXVR CDRPLL Shaper Enable */ -#define nCDRSHPEN 0x0 #define CDRCPSEL 0xff000000 /* MXVR CDRPLL Charge Pump Current Select */ /* Bit masks for MXVR_FMPLL_CTL */ #define FMSMEN 0x1 /* MXVR FMPLL State Machine Enable */ -#define nFMSMEN 0x0 #define FMRSTB 0x2 /* MXVR FMPLL Reset */ -#define nFMRSTB 0x0 #define FMSVCO 0x4 /* MXVR FMPLL Start VCO */ -#define nFMSVCO 0x0 #define FMSCNT 0x3f0 /* MXVR FMPLL Start Counter */ #define FMLCNT 0xfc00 /* MXVR FMPLL Lock Counter */ #define FMCPSEL 0xff000000 /* MXVR FMPLL Charge Pump Current Select */ @@ -2470,15 +2044,10 @@ /* Bit masks for MXVR_PIN_CTL */ #define MTXONBOD 0x1 /* MTXONB Open Drain Select */ -#define nMTXONBOD 0x0 #define MTXONBG 0x2 /* MTXONB Gates MTX Select */ -#define nMTXONBG 0x0 #define MFSOE 0x10 /* MFS Output Enable */ -#define nMFSOE 0x0 #define MFSGPSEL 0x20 /* MFS General Purpose Output Select */ -#define nMFSGPSEL 0x0 #define MFSGPDAT 0x40 /* MFS General Purpose Output Data */ -#define nMFSGPDAT 0x0 /* Bit masks for MXVR_SCLK_CNT */ @@ -2487,7 +2056,6 @@ /* Bit masks for KPAD_CTL */ #define KPAD_EN 0x1 /* Keypad Enable */ -#define nKPAD_EN 0x0 #define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ #define KPAD_ROWEN 0x1c00 /* Row Enable Width */ #define KPAD_COLEN 0xe000 /* Column Enable Width */ @@ -2509,29 +2077,21 @@ /* Bit masks for KPAD_STAT */ #define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ -#define nKPAD_IRQ 0x0 #define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ #define KPAD_PRESSED 0x8 /* Key press current status */ -#define nKPAD_PRESSED 0x0 /* Bit masks for KPAD_SOFTEVAL */ #define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ -#define nKPAD_SOFTEVAL_E 0x0 /* Bit masks for SDH_COMMAND */ #define CMD_IDX 0x3f /* Command Index */ #define CMD_RSP 0x40 /* Response */ -#define nCMD_RSP 0x0 #define CMD_L_RSP 0x80 /* Long Response */ -#define nCMD_L_RSP 0x0 #define CMD_INT_E 0x100 /* Command Interrupt */ -#define nCMD_INT_E 0x0 #define CMD_PEND_E 0x200 /* Command Pending */ -#define nCMD_PEND_E 0x0 #define CMD_E 0x400 /* Command Enable */ -#define nCMD_E 0x0 /* Bit masks for SDH_PWR_CTL */ @@ -2540,21 +2100,15 @@ #define TBD 0x3c /* TBD */ #endif #define SD_CMD_OD 0x40 /* Open Drain Output */ -#define nSD_CMD_OD 0x0 #define ROD_CTL 0x80 /* Rod Control */ -#define nROD_CTL 0x0 /* Bit masks for SDH_CLK_CTL */ #define CLKDIV 0xff /* MC_CLK Divisor */ #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ -#define nCLK_E 0x0 #define PWR_SV_E 0x200 /* Power Save Enable */ -#define nPWR_SV_E 0x0 #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ -#define nCLKDIV_BYPASS 0x0 #define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ -#define nWIDE_BUS 0x0 /* Bit masks for SDH_RESP_CMD */ @@ -2563,133 +2117,74 @@ /* Bit masks for SDH_DATA_CTL */ #define DTX_E 0x1 /* Data Transfer Enable */ -#define nDTX_E 0x0 #define DTX_DIR 0x2 /* Data Transfer Direction */ -#define nDTX_DIR 0x0 #define DTX_MODE 0x4 /* Data Transfer Mode */ -#define nDTX_MODE 0x0 #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ -#define nDTX_DMA_E 0x0 #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ /* Bit masks for SDH_STATUS */ #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ -#define nCMD_CRC_FAIL 0x0 #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ -#define nDAT_CRC_FAIL 0x0 -#define CMD_TIMEOUT 0x4 /* CMD Time Out */ -#define nCMD_TIMEOUT 0x0 -#define DAT_TIMEOUT 0x8 /* Data Time Out */ -#define nDAT_TIMEOUT 0x0 +#define CMD_TIME_OUT 0x4 /* CMD Time Out */ +#define DAT_TIME_OUT 0x8 /* Data Time Out */ #define TX_UNDERRUN 0x10 /* Transmit Underrun */ -#define nTX_UNDERRUN 0x0 #define RX_OVERRUN 0x20 /* Receive Overrun */ -#define nRX_OVERRUN 0x0 #define CMD_RESP_END 0x40 /* CMD Response End */ -#define nCMD_RESP_END 0x0 #define CMD_SENT 0x80 /* CMD Sent */ -#define nCMD_SENT 0x0 #define DAT_END 0x100 /* Data End */ -#define nDAT_END 0x0 #define START_BIT_ERR 0x200 /* Start Bit Error */ -#define nSTART_BIT_ERR 0x0 #define DAT_BLK_END 0x400 /* Data Block End */ -#define nDAT_BLK_END 0x0 #define CMD_ACT 0x800 /* CMD Active */ -#define nCMD_ACT 0x0 #define TX_ACT 0x1000 /* Transmit Active */ -#define nTX_ACT 0x0 #define RX_ACT 0x2000 /* Receive Active */ -#define nRX_ACT 0x0 #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ -#define nTX_FIFO_STAT 0x0 #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ -#define nRX_FIFO_STAT 0x0 #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ -#define nTX_FIFO_FULL 0x0 #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ -#define nRX_FIFO_FULL 0x0 #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ -#define nTX_FIFO_ZERO 0x0 #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ -#define nRX_DAT_ZERO 0x0 #define TX_DAT_RDY 0x100000 /* Transmit Data Available */ -#define nTX_DAT_RDY 0x0 #define RX_FIFO_RDY 0x200000 /* Receive Data Available */ -#define nRX_FIFO_RDY 0x0 /* Bit masks for SDH_STATUS_CLR */ #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ -#define nCMD_CRC_FAIL_STAT 0x0 #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ -#define nDAT_CRC_FAIL_STAT 0x0 #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ -#define nCMD_TIMEOUT_STAT 0x0 #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ -#define nDAT_TIMEOUT_STAT 0x0 #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ -#define nTX_UNDERRUN_STAT 0x0 #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ -#define nRX_OVERRUN_STAT 0x0 #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ -#define nCMD_RESP_END_STAT 0x0 #define CMD_SENT_STAT 0x80 /* CMD Sent Status */ -#define nCMD_SENT_STAT 0x0 #define DAT_END_STAT 0x100 /* Data End Status */ -#define nDAT_END_STAT 0x0 #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ -#define nSTART_BIT_ERR_STAT 0x0 #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ -#define nDAT_BLK_END_STAT 0x0 /* Bit masks for SDH_MASK0 */ #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ -#define nCMD_CRC_FAIL_MASK 0x0 #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ -#define nDAT_CRC_FAIL_MASK 0x0 #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ -#define nCMD_TIMEOUT_MASK 0x0 #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ -#define nDAT_TIMEOUT_MASK 0x0 #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ -#define nTX_UNDERRUN_MASK 0x0 #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ -#define nRX_OVERRUN_MASK 0x0 #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ -#define nCMD_RESP_END_MASK 0x0 #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ -#define nCMD_SENT_MASK 0x0 #define DAT_END_MASK 0x100 /* Data End Mask */ -#define nDAT_END_MASK 0x0 #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ -#define nSTART_BIT_ERR_MASK 0x0 #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ -#define nDAT_BLK_END_MASK 0x0 #define CMD_ACT_MASK 0x800 /* CMD Active Mask */ -#define nCMD_ACT_MASK 0x0 #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ -#define nTX_ACT_MASK 0x0 #define RX_ACT_MASK 0x2000 /* Receive Active Mask */ -#define nRX_ACT_MASK 0x0 #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ -#define nTX_FIFO_STAT_MASK 0x0 #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ -#define nRX_FIFO_STAT_MASK 0x0 #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ -#define nTX_FIFO_FULL_MASK 0x0 #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ -#define nRX_FIFO_FULL_MASK 0x0 #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ -#define nTX_FIFO_ZERO_MASK 0x0 #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ -#define nRX_DAT_ZERO_MASK 0x0 #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ -#define nTX_DAT_RDY_MASK 0x0 #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ -#define nRX_FIFO_RDY_MASK 0x0 /* Bit masks for SDH_FIFO_CNT */ @@ -2698,73 +2193,47 @@ /* Bit masks for SDH_E_STATUS */ #define SDIO_INT_DET 0x2 /* SDIO Int Detected */ -#define nSDIO_INT_DET 0x0 #define SD_CARD_DET 0x10 /* SD Card Detect */ -#define nSD_CARD_DET 0x0 /* Bit masks for SDH_E_MASK */ #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ -#define nSDIO_MSK 0x0 #define SCD_MSK 0x40 /* Mask Card Detect */ -#define nSCD_MSK 0x0 /* Bit masks for SDH_CFG */ #define CLKS_EN 0x1 /* Clocks Enable */ -#define nCLKS_EN 0x0 #define SD4E 0x4 /* SDIO 4-Bit Enable */ -#define nSD4E 0x0 #define MWE 0x8 /* Moving Window Enable */ -#define nMWE 0x0 #define SD_RST 0x10 /* SDMMC Reset */ -#define nSD_RST 0x0 #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ -#define nPUP_SDDAT 0x0 #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ -#define nPUP_SDDAT3 0x0 #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ -#define nPD_SDDAT3 0x0 /* Bit masks for SDH_RD_WAIT_EN */ #define RWR 0x1 /* Read Wait Request */ -#define nRWR 0x0 /* Bit masks for ATAPI_CONTROL */ #define PIO_START 0x1 /* Start PIO/Reg Op */ -#define nPIO_START 0x0 #define MULTI_START 0x2 /* Start Multi-DMA Op */ -#define nMULTI_START 0x0 #define ULTRA_START 0x4 /* Start Ultra-DMA Op */ -#define nULTRA_START 0x0 #define XFER_DIR 0x8 /* Transfer Direction */ -#define nXFER_DIR 0x0 #define IORDY_EN 0x10 /* IORDY Enable */ -#define nIORDY_EN 0x0 #define FIFO_FLUSH 0x20 /* Flush FIFOs */ -#define nFIFO_FLUSH 0x0 #define SOFT_RST 0x40 /* Soft Reset */ -#define nSOFT_RST 0x0 #define DEV_RST 0x80 /* Device Reset */ -#define nDEV_RST 0x0 #define TFRCNT_RST 0x100 /* Trans Count Reset */ -#define nTFRCNT_RST 0x0 #define END_ON_TERM 0x200 /* End/Terminate Select */ -#define nEND_ON_TERM 0x0 #define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ -#define nPIO_USE_DMA 0x0 #define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ /* Bit masks for ATAPI_STATUS */ #define PIO_XFER_ON 0x1 /* PIO transfer in progress */ -#define nPIO_XFER_ON 0x0 #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ -#define nMULTI_XFER_ON 0x0 #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ -#define nULTRA_XFER_ON 0x0 #define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ /* Bit masks for ATAPI_DEV_ADDR */ @@ -2774,66 +2243,39 @@ /* Bit masks for ATAPI_INT_MASK */ #define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ -#define nATAPI_DEV_INT_MASK 0x0 #define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ -#define nPIO_DONE_MASK 0x0 #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ -#define nMULTI_DONE_MASK 0x0 #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ -#define nUDMAIN_DONE_MASK 0x0 #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ -#define nUDMAOUT_DONE_MASK 0x0 #define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ -#define nHOST_TERM_XFER_MASK 0x0 #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ -#define nMULTI_TERM_MASK 0x0 #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ -#define nUDMAIN_TERM_MASK 0x0 #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ -#define nUDMAOUT_TERM_MASK 0x0 /* Bit masks for ATAPI_INT_STATUS */ #define ATAPI_DEV_INT 0x1 /* Device interrupt status */ -#define nATAPI_DEV_INT 0x0 #define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ -#define nPIO_DONE_INT 0x0 #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ -#define nMULTI_DONE_INT 0x0 #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ -#define nUDMAIN_DONE_INT 0x0 #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ -#define nUDMAOUT_DONE_INT 0x0 #define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ -#define nHOST_TERM_XFER_INT 0x0 #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ -#define nMULTI_TERM_INT 0x0 #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ -#define nUDMAIN_TERM_INT 0x0 #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ -#define nUDMAOUT_TERM_INT 0x0 /* Bit masks for ATAPI_LINE_STATUS */ #define ATAPI_INTR 0x1 /* Device interrupt to host line status */ -#define nATAPI_INTR 0x0 #define ATAPI_DASP 0x2 /* Device dasp to host line status */ -#define nATAPI_DASP 0x0 #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ -#define nATAPI_CS0N 0x0 #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ -#define nATAPI_CS1N 0x0 #define ATAPI_ADDR 0x70 /* ATAPI address line status */ #define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ -#define nATAPI_DMAREQ 0x0 #define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ -#define nATAPI_DMAACKN 0x0 #define ATAPI_DIOWN 0x200 /* ATAPI write line status */ -#define nATAPI_DIOWN 0x0 #define ATAPI_DIORN 0x400 /* ATAPI read line status */ -#define nATAPI_DIORN 0x0 #define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ -#define nATAPI_IORDY 0x0 /* Bit masks for ATAPI_SM_STATE */ @@ -2845,7 +2287,6 @@ /* Bit masks for ATAPI_TERMINATE */ #define ATAPI_HOST_TERM 0x1 /* Host terminationation */ -#define nATAPI_HOST_TERM 0x0 /* Bit masks for ATAPI_REG_TIM_0 */ @@ -2900,41 +2341,26 @@ /* Bit masks for TIMER_ENABLE1 */ #define TIMEN8 0x1 /* Timer 8 Enable */ -#define nTIMEN8 0x0 #define TIMEN9 0x2 /* Timer 9 Enable */ -#define nTIMEN9 0x0 #define TIMEN10 0x4 /* Timer 10 Enable */ -#define nTIMEN10 0x0 /* Bit masks for TIMER_DISABLE1 */ #define TIMDIS8 0x1 /* Timer 8 Disable */ -#define nTIMDIS8 0x0 #define TIMDIS9 0x2 /* Timer 9 Disable */ -#define nTIMDIS9 0x0 #define TIMDIS10 0x4 /* Timer 10 Disable */ -#define nTIMDIS10 0x0 /* Bit masks for TIMER_STATUS1 */ #define TIMIL8 0x1 /* Timer 8 Interrupt */ -#define nTIMIL8 0x0 #define TIMIL9 0x2 /* Timer 9 Interrupt */ -#define nTIMIL9 0x0 #define TIMIL10 0x4 /* Timer 10 Interrupt */ -#define nTIMIL10 0x0 #define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ -#define nTOVF_ERR8 0x0 #define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ -#define nTOVF_ERR9 0x0 #define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ -#define nTOVF_ERR10 0x0 #define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ -#define nTRUN8 0x0 #define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ -#define nTRUN9 0x0 #define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ -#define nTRUN10 0x0 /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ @@ -2945,131 +2371,77 @@ /* Bit masks for USB_POWER */ #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ -#define nENABLE_SUSPENDM 0x0 #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ -#define nSUSPEND_MODE 0x0 #define RESUME_MODE 0x4 /* DMA Mode */ -#define nRESUME_MODE 0x0 #define RESET 0x8 /* Reset indicator */ -#define nRESET 0x0 #define HS_MODE 0x10 /* High Speed mode indicator */ -#define nHS_MODE 0x0 #define HS_ENABLE 0x20 /* high Speed Enable */ -#define nHS_ENABLE 0x0 #define SOFT_CONN 0x40 /* Soft connect */ -#define nSOFT_CONN 0x0 #define ISO_UPDATE 0x80 /* Isochronous update */ -#define nISO_UPDATE 0x0 /* Bit masks for USB_INTRTX */ #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ -#define nEP0_TX 0x0 #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ -#define nEP1_TX 0x0 #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ -#define nEP2_TX 0x0 #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ -#define nEP3_TX 0x0 #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ -#define nEP4_TX 0x0 #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ -#define nEP5_TX 0x0 #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ -#define nEP6_TX 0x0 #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ -#define nEP7_TX 0x0 /* Bit masks for USB_INTRRX */ #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ -#define nEP1_RX 0x0 #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ -#define nEP2_RX 0x0 #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ -#define nEP3_RX 0x0 #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ -#define nEP4_RX 0x0 #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ -#define nEP5_RX 0x0 #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ -#define nEP6_RX 0x0 #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ -#define nEP7_RX 0x0 /* Bit masks for USB_INTRTXE */ #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ -#define nEP0_TX_E 0x0 #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ -#define nEP1_TX_E 0x0 #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ -#define nEP2_TX_E 0x0 #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ -#define nEP3_TX_E 0x0 #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ -#define nEP4_TX_E 0x0 #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ -#define nEP5_TX_E 0x0 #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ -#define nEP6_TX_E 0x0 #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ -#define nEP7_TX_E 0x0 /* Bit masks for USB_INTRRXE */ #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ -#define nEP1_RX_E 0x0 #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ -#define nEP2_RX_E 0x0 #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ -#define nEP3_RX_E 0x0 #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ -#define nEP4_RX_E 0x0 #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ -#define nEP5_RX_E 0x0 #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ -#define nEP6_RX_E 0x0 #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ -#define nEP7_RX_E 0x0 /* Bit masks for USB_INTRUSB */ #define SUSPEND_B 0x1 /* Suspend indicator */ -#define nSUSPEND_B 0x0 #define RESUME_B 0x2 /* Resume indicator */ -#define nRESUME_B 0x0 #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ -#define nRESET_OR_BABLE_B 0x0 #define SOF_B 0x8 /* Start of frame */ -#define nSOF_B 0x0 #define CONN_B 0x10 /* Connection indicator */ -#define nCONN_B 0x0 #define DISCON_B 0x20 /* Disconnect indicator */ -#define nDISCON_B 0x0 #define SESSION_REQ_B 0x40 /* Session Request */ -#define nSESSION_REQ_B 0x0 #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ -#define nVBUS_ERROR_B 0x0 /* Bit masks for USB_INTRUSBE */ #define SUSPEND_BE 0x1 /* Suspend indicator int enable */ -#define nSUSPEND_BE 0x0 #define RESUME_BE 0x2 /* Resume indicator int enable */ -#define nRESUME_BE 0x0 #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ -#define nRESET_OR_BABLE_BE 0x0 #define SOF_BE 0x8 /* Start of frame int enable */ -#define nSOF_BE 0x0 #define CONN_BE 0x10 /* Connection indicator int enable */ -#define nCONN_BE 0x0 #define DISCON_BE 0x20 /* Disconnect indicator int enable */ -#define nDISCON_BE 0x0 #define SESSION_REQ_BE 0x40 /* Session Request int enable */ -#define nSESSION_REQ_BE 0x0 #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ -#define nVBUS_ERROR_BE 0x0 /* Bit masks for USB_FRAME */ @@ -3082,117 +2454,67 @@ /* Bit masks for USB_GLOBAL_CTL */ #define GLOBAL_ENA 0x1 /* enables USB module */ -#define nGLOBAL_ENA 0x0 #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ -#define nEP1_TX_ENA 0x0 #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ -#define nEP2_TX_ENA 0x0 #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ -#define nEP3_TX_ENA 0x0 #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ -#define nEP4_TX_ENA 0x0 #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ -#define nEP5_TX_ENA 0x0 #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ -#define nEP6_TX_ENA 0x0 #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ -#define nEP7_TX_ENA 0x0 #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ -#define nEP1_RX_ENA 0x0 #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ -#define nEP2_RX_ENA 0x0 #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ -#define nEP3_RX_ENA 0x0 #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ -#define nEP4_RX_ENA 0x0 #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ -#define nEP5_RX_ENA 0x0 #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ -#define nEP6_RX_ENA 0x0 #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ -#define nEP7_RX_ENA 0x0 /* Bit masks for USB_OTG_DEV_CTL */ #define SESSION 0x1 /* session indicator */ -#define nSESSION 0x0 #define HOST_REQ 0x2 /* Host negotiation request */ -#define nHOST_REQ 0x0 #define HOST_MODE 0x4 /* indicates USBDRC is a host */ -#define nHOST_MODE 0x0 #define VBUS0 0x8 /* Vbus level indicator[0] */ -#define nVBUS0 0x0 #define VBUS1 0x10 /* Vbus level indicator[1] */ -#define nVBUS1 0x0 #define LSDEV 0x20 /* Low-speed indicator */ -#define nLSDEV 0x0 #define FSDEV 0x40 /* Full or High-speed indicator */ -#define nFSDEV 0x0 #define B_DEVICE 0x80 /* A' or 'B' device indicator */ -#define nB_DEVICE 0x0 /* Bit masks for USB_OTG_VBUS_IRQ */ #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ -#define nDRIVE_VBUS_ON 0x0 #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ -#define nDRIVE_VBUS_OFF 0x0 #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ -#define nCHRG_VBUS_START 0x0 #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ -#define nCHRG_VBUS_END 0x0 #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ -#define nDISCHRG_VBUS_START 0x0 #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ -#define nDISCHRG_VBUS_END 0x0 /* Bit masks for USB_OTG_VBUS_MASK */ #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ -#define nDRIVE_VBUS_ON_ENA 0x0 #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ -#define nDRIVE_VBUS_OFF_ENA 0x0 #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ -#define nCHRG_VBUS_START_ENA 0x0 #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ -#define nCHRG_VBUS_END_ENA 0x0 #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ -#define nDISCHRG_VBUS_START_ENA 0x0 #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ -#define nDISCHRG_VBUS_END_ENA 0x0 /* Bit masks for USB_CSR0 */ #define RXPKTRDY 0x1 /* data packet receive indicator */ -#define nRXPKTRDY 0x0 #define TXPKTRDY 0x2 /* data packet in FIFO indicator */ -#define nTXPKTRDY 0x0 #define STALL_SENT 0x4 /* STALL handshake sent */ -#define nSTALL_SENT 0x0 #define DATAEND 0x8 /* Data end indicator */ -#define nDATAEND 0x0 #define SETUPEND 0x10 /* Setup end */ -#define nSETUPEND 0x0 #define SENDSTALL 0x20 /* Send STALL handshake */ -#define nSENDSTALL 0x0 #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ -#define nSERVICED_RXPKTRDY 0x0 #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ -#define nSERVICED_SETUPEND 0x0 #define FLUSHFIFO 0x100 /* flush endpoint FIFO */ -#define nFLUSHFIFO 0x0 #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ -#define nSTALL_RECEIVED_H 0x0 #define SETUPPKT_H 0x8 /* send Setup token host mode */ -#define nSETUPPKT_H 0x0 #define ERROR_H 0x10 /* timeout error indicator host mode */ -#define nERROR_H 0x0 #define REQPKT_H 0x20 /* Request an IN transaction host mode */ -#define nREQPKT_H 0x0 #define STATUSPKT_H 0x40 /* Status stage transaction host mode */ -#define nSTATUSPKT_H 0x0 #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ -#define nNAK_TIMEOUT_H 0x0 /* Bit masks for USB_COUNT0 */ @@ -3213,37 +2535,21 @@ /* Bit masks for USB_TXCSR */ #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ -#define nTXPKTRDY_T 0x0 #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ -#define nFIFO_NOT_EMPTY_T 0x0 #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ -#define nUNDERRUN_T 0x0 #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ -#define nFLUSHFIFO_T 0x0 #define STALL_SEND_T 0x10 /* issue a Stall handshake */ -#define nSTALL_SEND_T 0x0 #define STALL_SENT_T 0x20 /* Stall handshake transmitted */ -#define nSTALL_SENT_T 0x0 #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ -#define nCLEAR_DATATOGGLE_T 0x0 #define INCOMPTX_T 0x80 /* indicates that a large packet is split */ -#define nINCOMPTX_T 0x0 #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ -#define nDMAREQMODE_T 0x0 #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ -#define nFORCE_DATATOGGLE_T 0x0 #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ -#define nDMAREQ_ENA_T 0x0 #define ISO_T 0x4000 /* enable Isochronous transfers */ -#define nISO_T 0x0 #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ -#define nAUTOSET_T 0x0 #define ERROR_TH 0x4 /* error condition host mode */ -#define nERROR_TH 0x0 #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ -#define nSTALL_RECEIVED_TH 0x0 #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ -#define nNAK_TIMEOUT_TH 0x0 /* Bit masks for USB_TXCOUNT */ @@ -3252,45 +2558,25 @@ /* Bit masks for USB_RXCSR */ #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ -#define nRXPKTRDY_R 0x0 #define FIFO_FULL_R 0x2 /* FIFO not empty */ -#define nFIFO_FULL_R 0x0 #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ -#define nOVERRUN_R 0x0 #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ -#define nDATAERROR_R 0x0 #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ -#define nFLUSHFIFO_R 0x0 #define STALL_SEND_R 0x20 /* issue a Stall handshake */ -#define nSTALL_SEND_R 0x0 #define STALL_SENT_R 0x40 /* Stall handshake transmitted */ -#define nSTALL_SENT_R 0x0 #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ -#define nCLEAR_DATATOGGLE_R 0x0 #define INCOMPRX_R 0x100 /* indicates that a large packet is split */ -#define nINCOMPRX_R 0x0 #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ -#define nDMAREQMODE_R 0x0 #define DISNYET_R 0x1000 /* disable Nyet handshakes */ -#define nDISNYET_R 0x0 #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ -#define nDMAREQ_ENA_R 0x0 #define ISO_R 0x4000 /* enable Isochronous transfers */ -#define nISO_R 0x0 #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ -#define nAUTOCLEAR_R 0x0 #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ -#define nERROR_RH 0x0 #define REQPKT_RH 0x20 /* request an IN transaction host mode */ -#define nREQPKT_RH 0x0 #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ -#define nSTALL_RECEIVED_RH 0x0 #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ -#define nINCOMPRX_RH 0x0 #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ -#define nDMAREQMODE_RH 0x0 #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ -#define nAUTOREQ_RH 0x0 /* Bit masks for USB_RXCOUNT */ @@ -3317,35 +2603,22 @@ /* Bit masks for USB_DMA_INTERRUPT */ #define DMA0_INT 0x1 /* DMA0 pending interrupt */ -#define nDMA0_INT 0x0 #define DMA1_INT 0x2 /* DMA1 pending interrupt */ -#define nDMA1_INT 0x0 #define DMA2_INT 0x4 /* DMA2 pending interrupt */ -#define nDMA2_INT 0x0 #define DMA3_INT 0x8 /* DMA3 pending interrupt */ -#define nDMA3_INT 0x0 #define DMA4_INT 0x10 /* DMA4 pending interrupt */ -#define nDMA4_INT 0x0 #define DMA5_INT 0x20 /* DMA5 pending interrupt */ -#define nDMA5_INT 0x0 #define DMA6_INT 0x40 /* DMA6 pending interrupt */ -#define nDMA6_INT 0x0 #define DMA7_INT 0x80 /* DMA7 pending interrupt */ -#define nDMA7_INT 0x0 /* Bit masks for USB_DMAxCONTROL */ #define DMA_ENA 0x1 /* DMA enable */ -#define nDMA_ENA 0x0 #define DIRECTION 0x2 /* direction of DMA transfer */ -#define nDIRECTION 0x0 #define MODE 0x4 /* DMA Bus error */ -#define nMODE 0x0 #define INT_ENA 0x8 /* Interrupt enable */ -#define nINT_ENA 0x0 #define EPNUM 0xf0 /* EP number */ #define BUSERROR 0x100 /* DMA Bus error */ -#define nBUSERROR 0x0 /* Bit masks for USB_DMAxADDRHIGH */ @@ -3366,26 +2639,16 @@ /* Bit masks for HMDMAx_CONTROL */ #define HMDMAEN 0x1 /* Handshake MDMA Enable */ -#define nHMDMAEN 0x0 #define REP 0x2 /* Handshake MDMA Request Polarity */ -#define nREP 0x0 #define UTE 0x8 /* Urgency Threshold Enable */ -#define nUTE 0x0 #define OIE 0x10 /* Overflow Interrupt Enable */ -#define nOIE 0x0 #define BDIE 0x20 /* Block Done Interrupt Enable */ -#define nBDIE 0x0 #define MBDI 0x40 /* Mask Block Done Interrupt */ -#define nMBDI 0x0 #define DRQ 0x300 /* Handshake MDMA Request Type */ #define RBC 0x1000 /* Force Reload of BCOUNT */ -#define nRBC 0x0 #define PS 0x2000 /* Pin Status */ -#define nPS 0x0 #define OI 0x4000 /* Overflow Interrupt Generated */ -#define nOI 0x0 #define BDI 0x8000 /* Block Done Interrupt Generated */ -#define nBDI 0x0 /* ******************************************* */ /* MULTI BIT MACRO ENUMERATIONS */ diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h index a1b200fe6a1..895ddd40a83 100644 --- a/include/asm-blackfin/mach-bf548/defBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h @@ -46,7 +46,7 @@ /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */ -#define CHIPID 0xffc00014 +#define CHIPID 0xffc00014 /* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */ @@ -1512,231 +1512,144 @@ /* and MULTI BIT READ MACROS */ /* ********************************************************** */ +/* SIC_IMASK Masks */ +#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ +#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ +#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */ +#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */ + +/* SIC_IWR Masks */ +#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ +#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ +#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ +#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ + /* Bit masks for SIC_IAR0 */ -#define IRQ_PLL_WAKEUP 0x1 /* PLL Wakeup */ -#define nIRQ_PLL_WAKEUP 0x0 +#define PLL_WAKEUP 0x1 /* PLL Wakeup */ /* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */ -#define IRQ_DMA0_ERR 0x2 /* DMA Controller 0 Error */ -#define nIRQ_DMA0_ERR 0x0 -#define IRQ_EPPI0_ERR 0x4 /* EPPI0 Error */ -#define nIRQ_EPPI0_ERR 0x0 -#define IRQ_SPORT0_ERR 0x8 /* SPORT0 Error */ -#define nIRQ_SPORT0_ERR 0x0 -#define IRQ_SPORT1_ERR 0x10 /* SPORT1 Error */ -#define nIRQ_SPORT1_ERR 0x0 -#define IRQ_SPI0_ERR 0x20 /* SPI0 Error */ -#define nIRQ_SPI0_ERR 0x0 -#define IRQ_UART0_ERR 0x40 /* UART0 Error */ -#define nIRQ_UART0_ERR 0x0 -#define IRQ_RTC 0x80 /* Real-Time Clock */ -#define nIRQ_RTC 0x0 -#define IRQ_DMA12 0x100 /* DMA Channel 12 */ -#define nIRQ_DMA12 0x0 -#define IRQ_DMA0 0x200 /* DMA Channel 0 */ -#define nIRQ_DMA0 0x0 -#define IRQ_DMA1 0x400 /* DMA Channel 1 */ -#define nIRQ_DMA1 0x0 -#define IRQ_DMA2 0x800 /* DMA Channel 2 */ -#define nIRQ_DMA2 0x0 -#define IRQ_DMA3 0x1000 /* DMA Channel 3 */ -#define nIRQ_DMA3 0x0 -#define IRQ_DMA4 0x2000 /* DMA Channel 4 */ -#define nIRQ_DMA4 0x0 -#define IRQ_DMA6 0x4000 /* DMA Channel 6 */ -#define nIRQ_DMA6 0x0 -#define IRQ_DMA7 0x8000 /* DMA Channel 7 */ -#define nIRQ_DMA7 0x0 -#define IRQ_PINT0 0x80000 /* Pin Interrupt 0 */ -#define nIRQ_PINT0 0x0 -#define IRQ_PINT1 0x100000 /* Pin Interrupt 1 */ -#define nIRQ_PINT1 0x0 -#define IRQ_MDMA0 0x200000 /* Memory DMA Stream 0 */ -#define nIRQ_MDMA0 0x0 -#define IRQ_MDMA1 0x400000 /* Memory DMA Stream 1 */ -#define nIRQ_MDMA1 0x0 -#define IRQ_WDOG 0x800000 /* Watchdog Timer */ -#define nIRQ_WDOG 0x0 -#define IRQ_DMA1_ERR 0x1000000 /* DMA Controller 1 Error */ -#define nIRQ_DMA1_ERR 0x0 -#define IRQ_SPORT2_ERR 0x2000000 /* SPORT2 Error */ -#define nIRQ_SPORT2_ERR 0x0 -#define IRQ_SPORT3_ERR 0x4000000 /* SPORT3 Error */ -#define nIRQ_SPORT3_ERR 0x0 -#define IRQ_MXVR_SD 0x8000000 /* MXVR Synchronous Data */ -#define nIRQ_MXVR_SD 0x0 -#define IRQ_SPI1_ERR 0x10000000 /* SPI1 Error */ -#define nIRQ_SPI1_ERR 0x0 -#define IRQ_SPI2_ERR 0x20000000 /* SPI2 Error */ -#define nIRQ_SPI2_ERR 0x0 -#define IRQ_UART1_ERR 0x40000000 /* UART1 Error */ -#define nIRQ_UART1_ERR 0x0 -#define IRQ_UART2_ERR 0x80000000 /* UART2 Error */ -#define nIRQ_UART2_ERR 0x0 +#define DMA0_ERR 0x2 /* DMA Controller 0 Error */ +#define EPPI0_ERR 0x4 /* EPPI0 Error */ +#define SPORT0_ERR 0x8 /* SPORT0 Error */ +#define SPORT1_ERR 0x10 /* SPORT1 Error */ +#define SPI0_ERR 0x20 /* SPI0 Error */ +#define UART0_ERR 0x40 /* UART0 Error */ +#define RTC 0x80 /* Real-Time Clock */ +#define DMA12 0x100 /* DMA Channel 12 */ +#define DMA0 0x200 /* DMA Channel 0 */ +#define DMA1 0x400 /* DMA Channel 1 */ +#define DMA2 0x800 /* DMA Channel 2 */ +#define DMA3 0x1000 /* DMA Channel 3 */ +#define DMA4 0x2000 /* DMA Channel 4 */ +#define DMA6 0x4000 /* DMA Channel 6 */ +#define DMA7 0x8000 /* DMA Channel 7 */ +#define PINT0 0x80000 /* Pin Interrupt 0 */ +#define PINT1 0x100000 /* Pin Interrupt 1 */ +#define MDMA0 0x200000 /* Memory DMA Stream 0 */ +#define MDMA1 0x400000 /* Memory DMA Stream 1 */ +#define WDOG 0x800000 /* Watchdog Timer */ +#define DMA1_ERR 0x1000000 /* DMA Controller 1 Error */ +#define SPORT2_ERR 0x2000000 /* SPORT2 Error */ +#define SPORT3_ERR 0x4000000 /* SPORT3 Error */ +#define MXVR_SD 0x8000000 /* MXVR Synchronous Data */ +#define SPI1_ERR 0x10000000 /* SPI1 Error */ +#define SPI2_ERR 0x20000000 /* SPI2 Error */ +#define UART1_ERR 0x40000000 /* UART1 Error */ +#define UART2_ERR 0x80000000 /* UART2 Error */ /* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */ -#define IRQ_CAN0_ERR 0x1 /* CAN0 Error */ -#define nIRQ_CAN0_ERR 0x0 -#define IRQ_DMA18 0x2 /* DMA Channel 18 */ -#define nIRQ_DMA18 0x0 -#define IRQ_DMA19 0x4 /* DMA Channel 19 */ -#define nIRQ_DMA19 0x0 -#define IRQ_DMA20 0x8 /* DMA Channel 20 */ -#define nIRQ_DMA20 0x0 -#define IRQ_DMA21 0x10 /* DMA Channel 21 */ -#define nIRQ_DMA21 0x0 -#define IRQ_DMA13 0x20 /* DMA Channel 13 */ -#define nIRQ_DMA13 0x0 -#define IRQ_DMA14 0x40 /* DMA Channel 14 */ -#define nIRQ_DMA14 0x0 -#define IRQ_DMA5 0x80 /* DMA Channel 5 */ -#define nIRQ_DMA5 0x0 -#define IRQ_DMA23 0x100 /* DMA Channel 23 */ -#define nIRQ_DMA23 0x0 -#define IRQ_DMA8 0x200 /* DMA Channel 8 */ -#define nIRQ_DMA8 0x0 -#define IRQ_DMA9 0x400 /* DMA Channel 9 */ -#define nIRQ_DMA9 0x0 -#define IRQ_DMA10 0x800 /* DMA Channel 10 */ -#define nIRQ_DMA10 0x0 -#define IRQ_DMA11 0x1000 /* DMA Channel 11 */ -#define nIRQ_DMA11 0x0 -#define IRQ_TWI0 0x2000 /* TWI0 */ -#define nIRQ_TWI0 0x0 -#define IRQ_TWI1 0x4000 /* TWI1 */ -#define nIRQ_TWI1 0x0 -#define IRQ_CAN0_RX 0x8000 /* CAN0 Receive */ -#define nIRQ_CAN0_RX 0x0 -#define IRQ_CAN0_TX 0x10000 /* CAN0 Transmit */ -#define nIRQ_CAN0_TX 0x0 -#define IRQ_MDMA2 0x20000 /* Memory DMA Stream 0 */ -#define nIRQ_MDMA2 0x0 -#define IRQ_MDMA3 0x40000 /* Memory DMA Stream 1 */ -#define nIRQ_MDMA3 0x0 -#define IRQ_MXVR_STAT 0x80000 /* MXVR Status */ -#define nIRQ_MXVR_STAT 0x0 -#define IRQ_MXVR_CM 0x100000 /* MXVR Control Message */ -#define nIRQ_MXVR_CM 0x0 -#define IRQ_MXVR_AP 0x200000 /* MXVR Asynchronous Packet */ -#define nIRQ_MXVR_AP 0x0 -#define IRQ_EPPI1_ERR 0x400000 /* EPPI1 Error */ -#define nIRQ_EPPI1_ERR 0x0 -#define IRQ_EPPI2_ERR 0x800000 /* EPPI2 Error */ -#define nIRQ_EPPI2_ERR 0x0 -#define IRQ_UART3_ERR 0x1000000 /* UART3 Error */ -#define nIRQ_UART3_ERR 0x0 -#define IRQ_HOST_ERR 0x2000000 /* Host DMA Port Error */ -#define nIRQ_HOST_ERR 0x0 -#define IRQ_USB_ERR 0x4000000 /* USB Error */ -#define nIRQ_USB_ERR 0x0 -#define IRQ_PIXC_ERR 0x8000000 /* Pixel Compositor Error */ -#define nIRQ_PIXC_ERR 0x0 -#define IRQ_NFC_ERR 0x10000000 /* Nand Flash Controller Error */ -#define nIRQ_NFC_ERR 0x0 -#define IRQ_ATAPI_ERR 0x20000000 /* ATAPI Error */ -#define nIRQ_ATAPI_ERR 0x0 -#define IRQ_CAN1_ERR 0x40000000 /* CAN1 Error */ -#define nIRQ_CAN1_ERR 0x0 -#define IRQ_DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */ -#define nIRQ_DMAR0_ERR 0x0 -#define IRQ_DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */ -#define nIRQ_DMAR1_ERR 0x0 -#define IRQ_DMAR0 0x80000000 /* DMAR0 Block */ -#define nIRQ_DMAR0 0x0 -#define IRQ_DMAR1 0x80000000 /* DMAR1 Block */ -#define nIRQ_DMAR1 0x0 +#define CAN0_ERR 0x1 /* CAN0 Error */ +#define DMA18 0x2 /* DMA Channel 18 */ +#define DMA19 0x4 /* DMA Channel 19 */ +#define DMA20 0x8 /* DMA Channel 20 */ +#define DMA21 0x10 /* DMA Channel 21 */ +#define DMA13 0x20 /* DMA Channel 13 */ +#define DMA14 0x40 /* DMA Channel 14 */ +#define DMA5 0x80 /* DMA Channel 5 */ +#define DMA23 0x100 /* DMA Channel 23 */ +#define DMA8 0x200 /* DMA Channel 8 */ +#define DMA9 0x400 /* DMA Channel 9 */ +#define DMA10 0x800 /* DMA Channel 10 */ +#define DMA11 0x1000 /* DMA Channel 11 */ +#define TWI0 0x2000 /* TWI0 */ +#define TWI1 0x4000 /* TWI1 */ +#define CAN0_RX 0x8000 /* CAN0 Receive */ +#define CAN0_TX 0x10000 /* CAN0 Transmit */ +#define MDMA2 0x20000 /* Memory DMA Stream 0 */ +#define MDMA3 0x40000 /* Memory DMA Stream 1 */ +#define MXVR_STAT 0x80000 /* MXVR Status */ +#define MXVR_CM 0x100000 /* MXVR Control Message */ +#define MXVR_AP 0x200000 /* MXVR Asynchronous Packet */ +#define EPPI1_ERR 0x400000 /* EPPI1 Error */ +#define EPPI2_ERR 0x800000 /* EPPI2 Error */ +#define UART3_ERR 0x1000000 /* UART3 Error */ +#define HOST_ERR 0x2000000 /* Host DMA Port Error */ +#define USB_ERR 0x4000000 /* USB Error */ +#define PIXC_ERR 0x8000000 /* Pixel Compositor Error */ +#define NFC_ERR 0x10000000 /* Nand Flash Controller Error */ +#define ATAPI_ERR 0x20000000 /* ATAPI Error */ +#define CAN1_ERR 0x40000000 /* CAN1 Error */ +#define DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */ +#define DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */ +#define DMAR0 0x80000000 /* DMAR0 Block */ +#define DMAR1 0x80000000 /* DMAR1 Block */ /* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */ -#define IRQ_DMA15 0x1 /* DMA Channel 15 */ -#define nIRQ_DMA15 0x0 -#define IRQ_DMA16 0x2 /* DMA Channel 16 */ -#define nIRQ_DMA16 0x0 -#define IRQ_DMA17 0x4 /* DMA Channel 17 */ -#define nIRQ_DMA17 0x0 -#define IRQ_DMA22 0x8 /* DMA Channel 22 */ -#define nIRQ_DMA22 0x0 -#define IRQ_CNT 0x10 /* Counter */ -#define nIRQ_CNT 0x0 -#define IRQ_KEY 0x20 /* Keypad */ -#define nIRQ_KEY 0x0 -#define IRQ_CAN1_RX 0x40 /* CAN1 Receive */ -#define nIRQ_CAN1_RX 0x0 -#define IRQ_CAN1_TX 0x80 /* CAN1 Transmit */ -#define nIRQ_CAN1_TX 0x0 -#define IRQ_SDH_MASK0 0x100 /* SDH Mask 0 */ -#define nIRQ_SDH_MASK0 0x0 -#define IRQ_SDH_MASK1 0x200 /* SDH Mask 1 */ -#define nIRQ_SDH_MASK1 0x0 -#define IRQ_USB_EINT 0x400 /* USB Exception */ -#define nIRQ_USB_EINT 0x0 -#define IRQ_USB_INT0 0x800 /* USB Interrupt 0 */ -#define nIRQ_USB_INT0 0x0 -#define IRQ_USB_INT1 0x1000 /* USB Interrupt 1 */ -#define nIRQ_USB_INT1 0x0 -#define IRQ_USB_INT2 0x2000 /* USB Interrupt 2 */ -#define nIRQ_USB_INT2 0x0 -#define IRQ_USB_DMAINT 0x4000 /* USB DMA */ -#define nIRQ_USB_DMAINT 0x0 -#define IRQ_OTPSEC 0x8000 /* OTP Access Complete */ -#define nIRQ_OTPSEC 0x0 -#define IRQ_TIMER0 0x400000 /* Timer 0 */ -#define nIRQ_TIMER0 0x0 -#define IRQ_TIMER1 0x800000 /* Timer 1 */ -#define nIRQ_TIMER1 0x0 -#define IRQ_TIMER2 0x1000000 /* Timer 2 */ -#define nIRQ_TIMER2 0x0 -#define IRQ_TIMER3 0x2000000 /* Timer 3 */ -#define nIRQ_TIMER3 0x0 -#define IRQ_TIMER4 0x4000000 /* Timer 4 */ -#define nIRQ_TIMER4 0x0 -#define IRQ_TIMER5 0x8000000 /* Timer 5 */ -#define nIRQ_TIMER5 0x0 -#define IRQ_TIMER6 0x10000000 /* Timer 6 */ -#define nIRQ_TIMER6 0x0 -#define IRQ_TIMER7 0x20000000 /* Timer 7 */ -#define nIRQ_TIMER7 0x0 -#define IRQ_PINT2 0x40000000 /* Pin Interrupt 2 */ -#define nIRQ_PINT2 0x0 -#define IRQ_PINT3 0x80000000 /* Pin Interrupt 3 */ -#define nIRQ_PINT3 0x0 +#define DMA15 0x1 /* DMA Channel 15 */ +#define DMA16 0x2 /* DMA Channel 16 */ +#define DMA17 0x4 /* DMA Channel 17 */ +#define DMA22 0x8 /* DMA Channel 22 */ +#define CNT 0x10 /* Counter */ +#define KEY 0x20 /* Keypad */ +#define CAN1_RX 0x40 /* CAN1 Receive */ +#define CAN1_TX 0x80 /* CAN1 Transmit */ +#define SDH_INT_MASK0 0x100 /* SDH Mask 0 */ +#define SDH_INT_MASK1 0x200 /* SDH Mask 1 */ +#define USB_EINT 0x400 /* USB Exception */ +#define USB_INT0 0x800 /* USB Interrupt 0 */ +#define USB_INT1 0x1000 /* USB Interrupt 1 */ +#define USB_INT2 0x2000 /* USB Interrupt 2 */ +#define USB_DMAINT 0x4000 /* USB DMA */ +#define OTPSEC 0x8000 /* OTP Access Complete */ +#define TIMER0 0x400000 /* Timer 0 */ +#define TIMER1 0x800000 /* Timer 1 */ +#define TIMER2 0x1000000 /* Timer 2 */ +#define TIMER3 0x2000000 /* Timer 3 */ +#define TIMER4 0x4000000 /* Timer 4 */ +#define TIMER5 0x8000000 /* Timer 5 */ +#define TIMER6 0x10000000 /* Timer 6 */ +#define TIMER7 0x20000000 /* Timer 7 */ +#define PINT2 0x40000000 /* Pin Interrupt 2 */ +#define PINT3 0x80000000 /* Pin Interrupt 3 */ /* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */ #define DMAEN 0x1 /* DMA Channel Enable */ -#define nDMAEN 0x0 #define WNR 0x2 /* DMA Direction */ -#define nWNR 0x0 -#define WDSIZE 0xc /* Transfer Word Size */ +#define WDSIZE_8 0x0 /* Transfer Word Size = 8 */ +#define WDSIZE_16 0x4 /* Transfer Word Size = 16 */ +#define WDSIZE_32 0x8 /* Transfer Word Size = 32 */ #define DMA2D 0x10 /* DMA Mode */ -#define nDMA2D 0x0 #define RESTART 0x20 /* Work Unit Transitions */ -#define nRESTART 0x0 #define DI_SEL 0x40 /* Data Interrupt Timing Select */ -#define nDI_SEL 0x0 #define DI_EN 0x80 /* Data Interrupt Enable */ -#define nDI_EN 0x0 #define NDSIZE 0xf00 /* Flex Descriptor Size */ #define DMAFLOW 0xf000 /* Next Operation */ /* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ #define DMA_DONE 0x1 /* DMA Completion Interrupt Status */ -#define nDMA_DONE 0x0 #define DMA_ERR 0x2 /* DMA Error Interrupt Status */ -#define nDMA_ERR 0x0 #define DFETCH 0x4 /* DMA Descriptor Fetch */ -#define nDFETCH 0x0 #define DMA_RUN 0x8 /* DMA Channel Running */ -#define nDMA_RUN 0x0 /* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ #define CTYPE 0x40 /* DMA Channel Type */ -#define nCTYPE 0x0 #define PMAP 0xf000 /* Peripheral Mapped To This Channel */ /* Bit masks for DMACx_TCPER */ @@ -1756,29 +1669,28 @@ /* Bit masks for DMAC1_PERIMUX */ #define PMUXSDH 0x1 /* Peripheral Select for DMA22 channel */ -#define nPMUXSDH 0x0 -/* Bit masks for EBIU_AMGCTL */ +/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ +/* EBIU_AMGCTL Masks */ +#define AMCKEN 0x0001 /* Enable CLKOUT */ +#define AMBEN_NONE 0x0000 /* All Banks Disabled */ +#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */ +#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */ +#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */ +#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */ -#define AMCKEN 0x1 /* Async Memory Enable */ -#define nAMCKEN 0x0 -#define AMBEN 0xe /* Async bank enable */ /* Bit masks for EBIU_AMBCTL0 */ #define B0RDYEN 0x1 /* Bank 0 ARDY Enable */ -#define nB0RDYEN 0x0 #define B0RDYPOL 0x2 /* Bank 0 ARDY Polarity */ -#define nB0RDYPOL 0x0 #define B0TT 0xc /* Bank 0 transition time */ #define B0ST 0x30 /* Bank 0 Setup time */ #define B0HT 0xc0 /* Bank 0 Hold time */ #define B0RAT 0xf00 /* Bank 0 Read access time */ #define B0WAT 0xf000 /* Bank 0 write access time */ #define B1RDYEN 0x10000 /* Bank 1 ARDY Enable */ -#define nB1RDYEN 0x0 #define B1RDYPOL 0x20000 /* Bank 1 ARDY Polarity */ -#define nB1RDYPOL 0x0 #define B1TT 0xc0000 /* Bank 1 transition time */ #define B1ST 0x300000 /* Bank 1 Setup time */ #define B1HT 0xc00000 /* Bank 1 Hold time */ @@ -1788,18 +1700,14 @@ /* Bit masks for EBIU_AMBCTL1 */ #define B2RDYEN 0x1 /* Bank 2 ARDY Enable */ -#define nB2RDYEN 0x0 #define B2RDYPOL 0x2 /* Bank 2 ARDY Polarity */ -#define nB2RDYPOL 0x0 #define B2TT 0xc /* Bank 2 transition time */ #define B2ST 0x30 /* Bank 2 Setup time */ #define B2HT 0xc0 /* Bank 2 Hold time */ #define B2RAT 0xf00 /* Bank 2 Read access time */ #define B2WAT 0xf000 /* Bank 2 write access time */ #define B3RDYEN 0x10000 /* Bank 3 ARDY Enable */ -#define nB3RDYEN 0x0 #define B3RDYPOL 0x20000 /* Bank 3 ARDY Polarity */ -#define nB3RDYPOL 0x0 #define B3TT 0xc0000 /* Bank 3 transition time */ #define B3ST 0x300000 /* Bank 3 Setup time */ #define B3HT 0xc00000 /* Bank 3 Hold time */ @@ -1823,19 +1731,15 @@ /* Bit masks for EBIU_FCTL */ #define TESTSETLOCK 0x1 /* Test set lock */ -#define nTESTSETLOCK 0x0 #define BCLK 0x6 /* Burst clock frequency */ #define PGWS 0x38 /* Page wait states */ #define PGSZ 0x40 /* Page size */ -#define nPGSZ 0x0 #define RDDL 0x380 /* Read data delay */ /* Bit masks for EBIU_ARBSTAT */ #define ARBSTAT 0x1 /* Arbitration status */ -#define nARBSTAT 0x0 #define BGSTAT 0x2 /* Bus grant status */ -#define nBGSTAT 0x0 /* Bit masks for EBIU_DDRCTL0 */ @@ -1861,9 +1765,7 @@ #define BURSTLENGTH 0x7 /* Burst length */ #define CASLATENCY 0x70 /* CAS latency */ #define DLLRESET 0x100 /* DLL Reset */ -#define nDLLRESET 0x0 #define REGE 0x1000 /* Register mode enable */ -#define nREGE 0x0 /* Bit masks for EBIU_DDRCTL3 */ @@ -1876,30 +1778,19 @@ #define DEB3_PFLEN 0x30 /* Pre fetch length for DEB3 accesses */ #define DEB_ARB_PRIORITY 0x700 /* Arbitration between DEB busses */ #define DEB1_URGENT 0x1000 /* DEB1 Urgent */ -#define nDEB1_URGENT 0x0 #define DEB2_URGENT 0x2000 /* DEB2 Urgent */ -#define nDEB2_URGENT 0x0 #define DEB3_URGENT 0x4000 /* DEB3 Urgent */ -#define nDEB3_URGENT 0x0 /* Bit masks for EBIU_ERRMST */ #define DEB1_ERROR 0x1 /* DEB1 Error */ -#define nDEB1_ERROR 0x0 #define DEB2_ERROR 0x2 /* DEB2 Error */ -#define nDEB2_ERROR 0x0 #define DEB3_ERROR 0x4 /* DEB3 Error */ -#define nDEB3_ERROR 0x0 #define CORE_ERROR 0x8 /* Core error */ -#define nCORE_ERROR 0x0 #define DEB_MERROR 0x10 /* DEB1 Error (2nd) */ -#define nDEB_MERROR 0x0 #define DEB2_MERROR 0x20 /* DEB2 Error (2nd) */ -#define nDEB2_MERROR 0x0 #define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */ -#define nDEB3_MERROR 0x0 #define CORE_MERROR 0x80 /* Core Error (2nd) */ -#define nCORE_MERROR 0x0 /* Bit masks for EBIU_ERRADD */ @@ -1908,15 +1799,10 @@ /* Bit masks for EBIU_RSTCTL */ #define DDRSRESET 0x1 /* DDR soft reset */ -#define nDDRSRESET 0x0 #define PFTCHSRESET 0x4 /* DDR prefetch reset */ -#define nPFTCHSRESET 0x0 #define SRREQ 0x8 /* Self-refresh request */ -#define nSRREQ 0x0 #define SRACK 0x10 /* Self-refresh acknowledge */ -#define nSRACK 0x0 #define MDDRENABLE 0x20 /* Mobile DDR enable */ -#define nMDDRENABLE 0x0 /* Bit masks for EBIU_DDRBRC0 */ @@ -2013,136 +1899,74 @@ /* Bit masks for EBIU_DDRMCEN */ #define B0WCENABLE 0x1 /* Bank 0 write count enable */ -#define nB0WCENABLE 0x0 #define B1WCENABLE 0x2 /* Bank 1 write count enable */ -#define nB1WCENABLE 0x0 #define B2WCENABLE 0x4 /* Bank 2 write count enable */ -#define nB2WCENABLE 0x0 #define B3WCENABLE 0x8 /* Bank 3 write count enable */ -#define nB3WCENABLE 0x0 #define B4WCENABLE 0x10 /* Bank 4 write count enable */ -#define nB4WCENABLE 0x0 #define B5WCENABLE 0x20 /* Bank 5 write count enable */ -#define nB5WCENABLE 0x0 #define B6WCENABLE 0x40 /* Bank 6 write count enable */ -#define nB6WCENABLE 0x0 #define B7WCENABLE 0x80 /* Bank 7 write count enable */ -#define nB7WCENABLE 0x0 #define B0RCENABLE 0x100 /* Bank 0 read count enable */ -#define nB0RCENABLE 0x0 #define B1RCENABLE 0x200 /* Bank 1 read count enable */ -#define nB1RCENABLE 0x0 #define B2RCENABLE 0x400 /* Bank 2 read count enable */ -#define nB2RCENABLE 0x0 #define B3RCENABLE 0x800 /* Bank 3 read count enable */ -#define nB3RCENABLE 0x0 #define B4RCENABLE 0x1000 /* Bank 4 read count enable */ -#define nB4RCENABLE 0x0 #define B5RCENABLE 0x2000 /* Bank 5 read count enable */ -#define nB5RCENABLE 0x0 #define B6RCENABLE 0x4000 /* Bank 6 read count enable */ -#define nB6RCENABLE 0x0 #define B7RCENABLE 0x8000 /* Bank 7 read count enable */ -#define nB7RCENABLE 0x0 #define ROWACTCENABLE 0x10000 /* DDR Row activate count enable */ -#define nROWACTCENABLE 0x0 #define RWTCENABLE 0x20000 /* DDR R/W Turn around count enable */ -#define nRWTCENABLE 0x0 #define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */ -#define nARCENABLE 0x0 #define GC0ENABLE 0x100000 /* DDR Grant count 0 enable */ -#define nGC0ENABLE 0x0 #define GC1ENABLE 0x200000 /* DDR Grant count 1 enable */ -#define nGC1ENABLE 0x0 #define GC2ENABLE 0x400000 /* DDR Grant count 2 enable */ -#define nGC2ENABLE 0x0 #define GC3ENABLE 0x800000 /* DDR Grant count 3 enable */ -#define nGC3ENABLE 0x0 #define GCCONTROL 0x3000000 /* DDR Grant Count Control */ /* Bit masks for EBIU_DDRMCCL */ #define CB0WCOUNT 0x1 /* Clear write count 0 */ -#define nCB0WCOUNT 0x0 #define CB1WCOUNT 0x2 /* Clear write count 1 */ -#define nCB1WCOUNT 0x0 #define CB2WCOUNT 0x4 /* Clear write count 2 */ -#define nCB2WCOUNT 0x0 #define CB3WCOUNT 0x8 /* Clear write count 3 */ -#define nCB3WCOUNT 0x0 #define CB4WCOUNT 0x10 /* Clear write count 4 */ -#define nCB4WCOUNT 0x0 #define CB5WCOUNT 0x20 /* Clear write count 5 */ -#define nCB5WCOUNT 0x0 #define CB6WCOUNT 0x40 /* Clear write count 6 */ -#define nCB6WCOUNT 0x0 #define CB7WCOUNT 0x80 /* Clear write count 7 */ -#define nCB7WCOUNT 0x0 #define CBRCOUNT 0x100 /* Clear read count 0 */ -#define nCBRCOUNT 0x0 #define CB1RCOUNT 0x200 /* Clear read count 1 */ -#define nCB1RCOUNT 0x0 #define CB2RCOUNT 0x400 /* Clear read count 2 */ -#define nCB2RCOUNT 0x0 #define CB3RCOUNT 0x800 /* Clear read count 3 */ -#define nCB3RCOUNT 0x0 #define CB4RCOUNT 0x1000 /* Clear read count 4 */ -#define nCB4RCOUNT 0x0 #define CB5RCOUNT 0x2000 /* Clear read count 5 */ -#define nCB5RCOUNT 0x0 #define CB6RCOUNT 0x4000 /* Clear read count 6 */ -#define nCB6RCOUNT 0x0 #define CB7RCOUNT 0x8000 /* Clear read count 7 */ -#define nCB7RCOUNT 0x0 #define CRACOUNT 0x10000 /* Clear row activation count */ -#define nCRACOUNT 0x0 #define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */ -#define nCRWTACOUNT 0x0 #define CARCOUNT 0x40000 /* Clear auto-refresh count */ -#define nCARCOUNT 0x0 #define CG0COUNT 0x100000 /* Clear grant count 0 */ -#define nCG0COUNT 0x0 #define CG1COUNT 0x200000 /* Clear grant count 1 */ -#define nCG1COUNT 0x0 #define CG2COUNT 0x400000 /* Clear grant count 2 */ -#define nCG2COUNT 0x0 #define CG3COUNT 0x800000 /* Clear grant count 3 */ -#define nCG3COUNT 0x0 /* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */ #define Px0 0x1 /* GPIO 0 */ -#define nPx0 0x0 #define Px1 0x2 /* GPIO 1 */ -#define nPx1 0x0 #define Px2 0x4 /* GPIO 2 */ -#define nPx2 0x0 #define Px3 0x8 /* GPIO 3 */ -#define nPx3 0x0 #define Px4 0x10 /* GPIO 4 */ -#define nPx4 0x0 #define Px5 0x20 /* GPIO 5 */ -#define nPx5 0x0 #define Px6 0x40 /* GPIO 6 */ -#define nPx6 0x0 #define Px7 0x80 /* GPIO 7 */ -#define nPx7 0x0 #define Px8 0x100 /* GPIO 8 */ -#define nPx8 0x0 #define Px9 0x200 /* GPIO 9 */ -#define nPx9 0x0 #define Px10 0x400 /* GPIO 10 */ -#define nPx10 0x0 #define Px11 0x800 /* GPIO 11 */ -#define nPx11 0x0 #define Px12 0x1000 /* GPIO 12 */ -#define nPx12 0x0 #define Px13 0x2000 /* GPIO 13 */ -#define nPx13 0x0 #define Px14 0x4000 /* GPIO 14 */ -#define nPx14 0x0 #define Px15 0x8000 /* GPIO 15 */ -#define nPx15 0x0 /* Bit masks for PORTA_MUX - PORTJ_MUX */ @@ -2167,223 +1991,129 @@ /* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */ #define IB0 0x1 /* Interrupt Bit 0 */ -#define nIB0 0x0 #define IB1 0x2 /* Interrupt Bit 1 */ -#define nIB1 0x0 #define IB2 0x4 /* Interrupt Bit 2 */ -#define nIB2 0x0 #define IB3 0x8 /* Interrupt Bit 3 */ -#define nIB3 0x0 #define IB4 0x10 /* Interrupt Bit 4 */ -#define nIB4 0x0 #define IB5 0x20 /* Interrupt Bit 5 */ -#define nIB5 0x0 #define IB6 0x40 /* Interrupt Bit 6 */ -#define nIB6 0x0 #define IB7 0x80 /* Interrupt Bit 7 */ -#define nIB7 0x0 #define IB8 0x100 /* Interrupt Bit 8 */ -#define nIB8 0x0 #define IB9 0x200 /* Interrupt Bit 9 */ -#define nIB9 0x0 #define IB10 0x400 /* Interrupt Bit 10 */ -#define nIB10 0x0 #define IB11 0x800 /* Interrupt Bit 11 */ -#define nIB11 0x0 #define IB12 0x1000 /* Interrupt Bit 12 */ -#define nIB12 0x0 #define IB13 0x2000 /* Interrupt Bit 13 */ -#define nIB13 0x0 #define IB14 0x4000 /* Interrupt Bit 14 */ -#define nIB14 0x0 #define IB15 0x8000 /* Interrupt Bit 15 */ -#define nIB15 0x0 /* Bit masks for TIMERx_CONFIG */ #define TMODE 0x3 /* Timer Mode */ #define PULSE_HI 0x4 /* Pulse Polarity */ -#define nPULSE_HI 0x0 #define PERIOD_CNT 0x8 /* Period Count */ -#define nPERIOD_CNT 0x0 #define IRQ_ENA 0x10 /* Interrupt Request Enable */ -#define nIRQ_ENA 0x0 #define TIN_SEL 0x20 /* Timer Input Select */ -#define nTIN_SEL 0x0 #define OUT_DIS 0x40 /* Output Pad Disable */ -#define nOUT_DIS 0x0 #define CLK_SEL 0x80 /* Timer Clock Select */ -#define nCLK_SEL 0x0 #define TOGGLE_HI 0x100 /* Toggle Mode */ -#define nTOGGLE_HI 0x0 #define EMU_RUN 0x200 /* Emulation Behavior Select */ -#define nEMU_RUN 0x0 #define ERR_TYP 0xc000 /* Error Type */ /* Bit masks for TIMER_ENABLE0 */ #define TIMEN0 0x1 /* Timer 0 Enable */ -#define nTIMEN0 0x0 #define TIMEN1 0x2 /* Timer 1 Enable */ -#define nTIMEN1 0x0 #define TIMEN2 0x4 /* Timer 2 Enable */ -#define nTIMEN2 0x0 #define TIMEN3 0x8 /* Timer 3 Enable */ -#define nTIMEN3 0x0 #define TIMEN4 0x10 /* Timer 4 Enable */ -#define nTIMEN4 0x0 #define TIMEN5 0x20 /* Timer 5 Enable */ -#define nTIMEN5 0x0 #define TIMEN6 0x40 /* Timer 6 Enable */ -#define nTIMEN6 0x0 #define TIMEN7 0x80 /* Timer 7 Enable */ -#define nTIMEN7 0x0 /* Bit masks for TIMER_DISABLE0 */ #define TIMDIS0 0x1 /* Timer 0 Disable */ -#define nTIMDIS0 0x0 #define TIMDIS1 0x2 /* Timer 1 Disable */ -#define nTIMDIS1 0x0 #define TIMDIS2 0x4 /* Timer 2 Disable */ -#define nTIMDIS2 0x0 #define TIMDIS3 0x8 /* Timer 3 Disable */ -#define nTIMDIS3 0x0 #define TIMDIS4 0x10 /* Timer 4 Disable */ -#define nTIMDIS4 0x0 #define TIMDIS5 0x20 /* Timer 5 Disable */ -#define nTIMDIS5 0x0 #define TIMDIS6 0x40 /* Timer 6 Disable */ -#define nTIMDIS6 0x0 #define TIMDIS7 0x80 /* Timer 7 Disable */ -#define nTIMDIS7 0x0 /* Bit masks for TIMER_STATUS0 */ #define TIMIL0 0x1 /* Timer 0 Interrupt */ -#define nTIMIL0 0x0 #define TIMIL1 0x2 /* Timer 1 Interrupt */ -#define nTIMIL1 0x0 #define TIMIL2 0x4 /* Timer 2 Interrupt */ -#define nTIMIL2 0x0 #define TIMIL3 0x8 /* Timer 3 Interrupt */ -#define nTIMIL3 0x0 #define TOVF_ERR0 0x10 /* Timer 0 Counter Overflow */ -#define nTOVF_ERR0 0x0 #define TOVF_ERR1 0x20 /* Timer 1 Counter Overflow */ -#define nTOVF_ERR1 0x0 #define TOVF_ERR2 0x40 /* Timer 2 Counter Overflow */ -#define nTOVF_ERR2 0x0 #define TOVF_ERR3 0x80 /* Timer 3 Counter Overflow */ -#define nTOVF_ERR3 0x0 #define TRUN0 0x1000 /* Timer 0 Slave Enable Status */ -#define nTRUN0 0x0 #define TRUN1 0x2000 /* Timer 1 Slave Enable Status */ -#define nTRUN1 0x0 #define TRUN2 0x4000 /* Timer 2 Slave Enable Status */ -#define nTRUN2 0x0 #define TRUN3 0x8000 /* Timer 3 Slave Enable Status */ -#define nTRUN3 0x0 #define TIMIL4 0x10000 /* Timer 4 Interrupt */ -#define nTIMIL4 0x0 #define TIMIL5 0x20000 /* Timer 5 Interrupt */ -#define nTIMIL5 0x0 #define TIMIL6 0x40000 /* Timer 6 Interrupt */ -#define nTIMIL6 0x0 #define TIMIL7 0x80000 /* Timer 7 Interrupt */ -#define nTIMIL7 0x0 #define TOVF_ERR4 0x100000 /* Timer 4 Counter Overflow */ -#define nTOVF_ERR4 0x0 #define TOVF_ERR5 0x200000 /* Timer 5 Counter Overflow */ -#define nTOVF_ERR5 0x0 #define TOVF_ERR6 0x400000 /* Timer 6 Counter Overflow */ -#define nTOVF_ERR6 0x0 #define TOVF_ERR7 0x800000 /* Timer 7 Counter Overflow */ -#define nTOVF_ERR7 0x0 #define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ -#define nTRUN4 0x0 #define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ -#define nTRUN5 0x0 #define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ -#define nTRUN6 0x0 #define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ -#define nTRUN7 0x0 /* Bit masks for WDOG_CTL */ #define WDEV 0x6 /* Watchdog Event */ #define WDEN 0xff0 /* Watchdog Enable */ #define WDRO 0x8000 /* Watchdog Rolled Over */ -#define nWDRO 0x0 /* Bit masks for CNT_CONFIG */ #define CNTE 0x1 /* Counter Enable */ -#define nCNTE 0x0 #define DEBE 0x2 /* Debounce Enable */ -#define nDEBE 0x0 #define CDGINV 0x10 /* CDG Pin Polarity Invert */ -#define nCDGINV 0x0 #define CUDINV 0x20 /* CUD Pin Polarity Invert */ -#define nCUDINV 0x0 #define CZMINV 0x40 /* CZM Pin Polarity Invert */ -#define nCZMINV 0x0 #define CNTMODE 0x700 /* Counter Operating Mode */ #define ZMZC 0x800 /* CZM Zeroes Counter Enable */ -#define nZMZC 0x0 #define BNDMODE 0x3000 /* Boundary register Mode */ #define INPDIS 0x8000 /* CUG and CDG Input Disable */ -#define nINPDIS 0x0 /* Bit masks for CNT_IMASK */ #define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */ -#define nICIE 0x0 #define UCIE 0x2 /* Up count Interrupt Enable */ -#define nUCIE 0x0 #define DCIE 0x4 /* Down count Interrupt Enable */ -#define nDCIE 0x0 #define MINCIE 0x8 /* Min Count Interrupt Enable */ -#define nMINCIE 0x0 #define MAXCIE 0x10 /* Max Count Interrupt Enable */ -#define nMAXCIE 0x0 #define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */ -#define nCOV31IE 0x0 #define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */ -#define nCOV15IE 0x0 #define CZEROIE 0x80 /* Count to Zero Interrupt Enable */ -#define nCZEROIE 0x0 #define CZMIE 0x100 /* CZM Pin Interrupt Enable */ -#define nCZMIE 0x0 #define CZMEIE 0x200 /* CZM Error Interrupt Enable */ -#define nCZMEIE 0x0 #define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */ -#define nCZMZIE 0x0 /* Bit masks for CNT_STATUS */ #define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */ -#define nICII 0x0 #define UCII 0x2 /* Up count Interrupt Identifier */ -#define nUCII 0x0 #define DCII 0x4 /* Down count Interrupt Identifier */ -#define nDCII 0x0 #define MINCII 0x8 /* Min Count Interrupt Identifier */ -#define nMINCII 0x0 #define MAXCII 0x10 /* Max Count Interrupt Identifier */ -#define nMAXCII 0x0 #define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */ -#define nCOV31II 0x0 #define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */ -#define nCOV15II 0x0 #define CZEROII 0x80 /* Count to Zero Interrupt Identifier */ -#define nCZEROII 0x0 #define CZMII 0x100 /* CZM Pin Interrupt Identifier */ -#define nCZMII 0x0 #define CZMEII 0x200 /* CZM Error Interrupt Identifier */ -#define nCZMEII 0x0 #define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */ -#define nCZMZII 0x0 /* Bit masks for CNT_COMMAND */ @@ -2391,7 +2121,6 @@ #define W1LMIN 0xf0 /* Load Min Register */ #define W1LMAX 0xf00 /* Load Max Register */ #define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */ -#define nW1ZMONCE 0x0 /* Bit masks for CNT_DEBOUNCE */ @@ -2407,42 +2136,25 @@ /* Bit masks for RTC_ICTL */ #define STOPWATCH_INTERRUPT_ENABLE 0x1 /* Stopwatch Interrupt Enable */ -#define nSTOPWATCH_INTERRUPT_ENABLE 0x0 #define ALARM_INTERRUPT_ENABLE 0x2 /* Alarm Interrupt Enable */ -#define nALARM_INTERRUPT_ENABLE 0x0 #define SECONDS_INTERRUPT_ENABLE 0x4 /* Seconds Interrupt Enable */ -#define nSECONDS_INTERRUPT_ENABLE 0x0 #define MINUTES_INTERRUPT_ENABLE 0x8 /* Minutes Interrupt Enable */ -#define nMINUTES_INTERRUPT_ENABLE 0x0 #define HOURS_INTERRUPT_ENABLE 0x10 /* Hours Interrupt Enable */ -#define nHOURS_INTERRUPT_ENABLE 0x0 #define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x20 /* 24 Hours Interrupt Enable */ -#define nTWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x0 #define DAY_ALARM_INTERRUPT_ENABLE 0x40 /* Day Alarm Interrupt Enable */ -#define nDAY_ALARM_INTERRUPT_ENABLE 0x0 #define WRITE_COMPLETE_INTERRUPT_ENABLE 0x8000 /* Write Complete Interrupt Enable */ -#define nWRITE_COMPLETE_INTERRUPT_ENABLE 0x0 /* Bit masks for RTC_ISTAT */ #define STOPWATCH_EVENT_FLAG 0x1 /* Stopwatch Event Flag */ -#define nSTOPWATCH_EVENT_FLAG 0x0 #define ALARM_EVENT_FLAG 0x2 /* Alarm Event Flag */ -#define nALARM_EVENT_FLAG 0x0 #define SECONDS_EVENT_FLAG 0x4 /* Seconds Event Flag */ -#define nSECONDS_EVENT_FLAG 0x0 #define MINUTES_EVENT_FLAG 0x8 /* Minutes Event Flag */ -#define nMINUTES_EVENT_FLAG 0x0 #define HOURS_EVENT_FLAG 0x10 /* Hours Event Flag */ -#define nHOURS_EVENT_FLAG 0x0 #define TWENTY_FOUR_HOURS_EVENT_FLAG 0x20 /* 24 Hours Event Flag */ -#define nTWENTY_FOUR_HOURS_EVENT_FLAG 0x0 #define DAY_ALARM_EVENT_FLAG 0x40 /* Day Alarm Event Flag */ -#define nDAY_ALARM_EVENT_FLAG 0x0 #define WRITE_PENDING__STATUS 0x4000 /* Write Pending Status */ -#define nWRITE_PENDING__STATUS 0x0 #define WRITE_COMPLETE 0x8000 /* Write Complete */ -#define nWRITE_COMPLETE 0x0 /* Bit masks for RTC_SWCNT */ @@ -2458,21 +2170,15 @@ /* Bit masks for RTC_PREN */ #define PREN 0x1 /* Prescaler Enable */ -#define nPREN 0x0 /* Bit masks for OTP_CONTROL */ #define FUSE_FADDR 0x1ff /* OTP/Fuse Address */ #define FIEN 0x800 /* OTP/Fuse Interrupt Enable */ -#define nFIEN 0x0 #define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */ -#define nFTESTDEC 0x0 #define FWRTEST 0x2000 /* OTP/Fuse Write Test */ -#define nFWRTEST 0x0 #define FRDEN 0x4000 /* OTP/Fuse Read Enable */ -#define nFRDEN 0x0 #define FWREN 0x8000 /* OTP/Fuse Write Enable */ -#define nFWREN 0x0 /* Bit masks for OTP_BEN */ @@ -2481,15 +2187,10 @@ /* Bit masks for OTP_STATUS */ #define FCOMP 0x1 /* OTP/Fuse Access Complete */ -#define nFCOMP 0x0 #define FERROR 0x2 /* OTP/Fuse Access Error */ -#define nFERROR 0x0 #define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */ -#define nMMRGLOAD 0x0 #define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */ -#define nMMRGLOCK 0x0 #define FPGMEN 0x40 /* OTP/Fuse Program Enable */ -#define nFPGMEN 0x0 /* Bit masks for OTP_TIMING */ @@ -2503,42 +2204,29 @@ /* Bit masks for SECURE_SYSSWT */ #define EMUDABL 0x1 /* Emulation Disable. */ -#define nEMUDABL 0x0 #define RSTDABL 0x2 /* Reset Disable */ -#define nRSTDABL 0x0 #define L1IDABL 0x1c /* L1 Instruction Memory Disable. */ #define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */ #define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */ #define DMA0OVR 0x800 /* DMA0 Memory Access Override */ -#define nDMA0OVR 0x0 #define DMA1OVR 0x1000 /* DMA1 Memory Access Override */ -#define nDMA1OVR 0x0 #define EMUOVR 0x4000 /* Emulation Override */ -#define nEMUOVR 0x0 #define OTPSEN 0x8000 /* OTP Secrets Enable. */ -#define nOTPSEN 0x0 #define L2DABL 0x70000 /* L2 Memory Disable. */ /* Bit masks for SECURE_CONTROL */ #define SECURE0 0x1 /* SECURE 0 */ -#define nSECURE0 0x0 #define SECURE1 0x2 /* SECURE 1 */ -#define nSECURE1 0x0 #define SECURE2 0x4 /* SECURE 2 */ -#define nSECURE2 0x0 #define SECURE3 0x8 /* SECURE 3 */ -#define nSECURE3 0x0 /* Bit masks for SECURE_STATUS */ #define SECMODE 0x3 /* Secured Mode Control State */ #define NMI 0x4 /* Non Maskable Interrupt */ -#define nNMI 0x0 #define AFVALID 0x8 /* Authentication Firmware Valid */ -#define nAFVALID 0x0 #define AFEXIT 0x10 /* Authentication Firmware Exit */ -#define nAFEXIT 0x0 #define SECSTAT 0xe0 /* Secure Status */ /* Bit masks for PLL_DIV */ @@ -2550,42 +2238,25 @@ #define MSEL 0x7e00 /* Multiplier Select */ #define BYPASS 0x100 /* PLL Bypass Enable */ -#define nBYPASS 0x0 #define OUTPUT_DELAY 0x80 /* External Memory Output Delay Enable */ -#define nOUTPUT_DELAY 0x0 #define INPUT_DELAY 0x40 /* External Memory Input Delay Enable */ -#define nINPUT_DELAY 0x0 #define PDWN 0x20 /* Power Down */ -#define nPDWN 0x0 #define STOPCK 0x8 /* Stop Clock */ -#define nSTOPCK 0x0 #define PLL_OFF 0x2 /* Disable PLL */ -#define nPLL_OFF 0x0 #define DF 0x1 /* Divide Frequency */ -#define nDF 0x0 /* Bit masks for PLL_STAT */ #define PLL_LOCKED 0x20 /* PLL Locked Status */ -#define nPLL_LOCKED 0x0 #define ACTIVE_PLLDISABLED 0x4 /* Active Mode With PLL Disabled */ -#define nACTIVE_PLLDISABLED 0x0 #define FULL_ON 0x2 /* Full-On Mode */ -#define nFULL_ON 0x0 #define ACTIVE_PLLENABLED 0x1 /* Active Mode With PLL Enabled */ -#define nACTIVE_PLLENABLED 0x0 #define RTCWS 0x400 /* RTC/Reset Wake-Up Status */ -#define nRTCWS 0x0 #define CANWS 0x800 /* CAN Wake-Up Status */ -#define nCANWS 0x0 #define USBWS 0x2000 /* USB Wake-Up Status */ -#define nUSBWS 0x0 #define KPADWS 0x4000 /* Keypad Wake-Up Status */ -#define nKPADWS 0x0 #define ROTWS 0x8000 /* Rotary Wake-Up Status */ -#define nROTWS 0x0 #define GPWS 0x1000 /* General-Purpose Wake-Up Status */ -#define nGPWS 0x0 /* Bit masks for VR_CTL */ @@ -2593,79 +2264,52 @@ #define GAIN 0xc /* Voltage Output Level Gain */ #define VLEV 0xf0 /* Internal Voltage Level */ #define SCKELOW 0x8000 /* Drive SCKE Low During Reset Enable */ -#define nSCKELOW 0x0 #define WAKE 0x100 /* RTC/Reset Wake-Up Enable */ -#define nWAKE 0x0 #define CANWE 0x200 /* CAN0/1 Wake-Up Enable */ -#define nCANWE 0x0 #define GPWE 0x400 /* General-Purpose Wake-Up Enable */ -#define nGPWE 0x0 #define USBWE 0x800 /* USB Wake-Up Enable */ -#define nUSBWE 0x0 #define KPADWE 0x1000 /* Keypad Wake-Up Enable */ -#define nKPADWE 0x0 #define ROTWE 0x2000 /* Rotary Wake-Up Enable */ -#define nROTWE 0x0 /* Bit masks for NFC_CTL */ #define WR_DLY 0xf /* Write Strobe Delay */ #define RD_DLY 0xf0 /* Read Strobe Delay */ #define NWIDTH 0x100 /* NAND Data Width */ -#define nNWIDTH 0x0 #define PG_SIZE 0x200 /* Page Size */ -#define nPG_SIZE 0x0 /* Bit masks for NFC_STAT */ #define NBUSY 0x1 /* Not Busy */ -#define nNBUSY 0x0 #define WB_FULL 0x2 /* Write Buffer Full */ -#define nWB_FULL 0x0 #define PG_WR_STAT 0x4 /* Page Write Pending */ -#define nPG_WR_STAT 0x0 #define PG_RD_STAT 0x8 /* Page Read Pending */ -#define nPG_RD_STAT 0x0 #define WB_EMPTY 0x10 /* Write Buffer Empty */ -#define nWB_EMPTY 0x0 /* Bit masks for NFC_IRQSTAT */ #define NBUSYIRQ 0x1 /* Not Busy IRQ */ -#define nNBUSYIRQ 0x0 #define WB_OVF 0x2 /* Write Buffer Overflow */ -#define nWB_OVF 0x0 #define WB_EDGE 0x4 /* Write Buffer Edge Detect */ -#define nWB_EDGE 0x0 #define RD_RDY 0x8 /* Read Data Ready */ -#define nRD_RDY 0x0 #define WR_DONE 0x10 /* Page Write Done */ -#define nWR_DONE 0x0 /* Bit masks for NFC_IRQMASK */ #define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */ -#define nMASK_BUSYIRQ 0x0 #define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */ -#define nMASK_WBOVF 0x0 #define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */ -#define nMASK_WBEMPTY 0x0 #define MASK_RDRDY 0x8 /* Mask Read Data Ready */ -#define nMASK_RDRDY 0x0 #define MASK_WRDONE 0x10 /* Mask Write Done */ -#define nMASK_WRDONE 0x0 /* Bit masks for NFC_RST */ #define ECC_RST 0x1 /* ECC (and NFC counters) Reset */ -#define nECC_RST 0x0 /* Bit masks for NFC_PGCTL */ #define PG_RD_START 0x1 /* Page Read Start */ -#define nPG_RD_START 0x0 #define PG_WR_START 0x2 /* Page Write Start */ -#define nPG_WR_START 0x0 /* Bit masks for NFC_ECC0 */ @@ -2690,56 +2334,34 @@ /* Bit masks for CAN0_CONTROL */ #define SRS 0x1 /* Software Reset */ -#define nSRS 0x0 #define DNM 0x2 /* DeviceNet Mode */ -#define nDNM 0x0 #define ABO 0x4 /* Auto Bus On */ -#define nABO 0x0 #define WBA 0x10 /* Wakeup On CAN Bus Activity */ -#define nWBA 0x0 #define SMR 0x20 /* Sleep Mode Request */ -#define nSMR 0x0 #define CSR 0x40 /* CAN Suspend Mode Request */ -#define nCSR 0x0 #define CCR 0x80 /* CAN Configuration Mode Request */ -#define nCCR 0x0 /* Bit masks for CAN0_STATUS */ #define WT 0x1 /* CAN Transmit Warning Flag */ -#define nWT 0x0 #define WR 0x2 /* CAN Receive Warning Flag */ -#define nWR 0x0 #define EP 0x4 /* CAN Error Passive Mode */ -#define nEP 0x0 #define EBO 0x8 /* CAN Error Bus Off Mode */ -#define nEBO 0x0 #define CSA 0x40 /* CAN Suspend Mode Acknowledge */ -#define nCSA 0x0 #define CCA 0x80 /* CAN Configuration Mode Acknowledge */ -#define nCCA 0x0 #define MBPTR 0x1f00 /* Mailbox Pointer */ #define TRM 0x4000 /* Transmit Mode Status */ -#define nTRM 0x0 #define REC 0x8000 /* Receive Mode Status */ -#define nREC 0x0 /* Bit masks for CAN0_DEBUG */ #define DEC 0x1 /* Disable Transmit/Receive Error Counters */ -#define nDEC 0x0 #define DRI 0x2 /* Disable CANRX Input Pin */ -#define nDRI 0x0 #define DTO 0x4 /* Disable CANTX Output Pin */ -#define nDTO 0x0 #define DIL 0x8 /* Disable Internal Loop */ -#define nDIL 0x0 #define MAA 0x10 /* Mode Auto-Acknowledge */ -#define nMAA 0x0 #define MRB 0x20 /* Mode Read Back */ -#define nMRB 0x0 #define CDE 0x8000 /* CAN Debug Mode Enable */ -#define nCDE 0x0 /* Bit masks for CAN0_CLOCK */ @@ -2749,111 +2371,69 @@ #define SJW 0x300 /* Synchronization Jump Width */ #define SAM 0x80 /* Sampling */ -#define nSAM 0x0 #define TSEG2 0x70 /* Time Segment 2 */ #define TSEG1 0xf /* Time Segment 1 */ /* Bit masks for CAN0_INTR */ #define CANRX 0x80 /* Serial Input From Transceiver */ -#define nCANRX 0x0 #define CANTX 0x40 /* Serial Output To Transceiver */ -#define nCANTX 0x0 #define SMACK 0x8 /* Sleep Mode Acknowledge */ -#define nSMACK 0x0 #define GIRQ 0x4 /* Global Interrupt Request Status */ -#define nGIRQ 0x0 #define MBTIRQ 0x2 /* Mailbox Transmit Interrupt Request */ -#define nMBTIRQ 0x0 #define MBRIRQ 0x1 /* Mailbox Receive Interrupt Request */ -#define nMBRIRQ 0x0 /* Bit masks for CAN0_GIM */ #define EWTIM 0x1 /* Error Warning Transmit Interrupt Mask */ -#define nEWTIM 0x0 #define EWRIM 0x2 /* Error Warning Receive Interrupt Mask */ -#define nEWRIM 0x0 #define EPIM 0x4 /* Error Passive Interrupt Mask */ -#define nEPIM 0x0 #define BOIM 0x8 /* Bus Off Interrupt Mask */ -#define nBOIM 0x0 #define WUIM 0x10 /* Wakeup Interrupt Mask */ -#define nWUIM 0x0 #define UIAIM 0x20 /* Unimplemented Address Interrupt Mask */ -#define nUIAIM 0x0 #define AAIM 0x40 /* Abort Acknowledge Interrupt Mask */ -#define nAAIM 0x0 #define RMLIM 0x80 /* Receive Message Lost Interrupt Mask */ -#define nRMLIM 0x0 #define UCEIM 0x100 /* Universal Counter Exceeded Interrupt Mask */ -#define nUCEIM 0x0 #define ADIM 0x400 /* Access Denied Interrupt Mask */ -#define nADIM 0x0 /* Bit masks for CAN0_GIS */ #define EWTIS 0x1 /* Error Warning Transmit Interrupt Status */ -#define nEWTIS 0x0 #define EWRIS 0x2 /* Error Warning Receive Interrupt Status */ -#define nEWRIS 0x0 #define EPIS 0x4 /* Error Passive Interrupt Status */ -#define nEPIS 0x0 #define BOIS 0x8 /* Bus Off Interrupt Status */ -#define nBOIS 0x0 #define WUIS 0x10 /* Wakeup Interrupt Status */ -#define nWUIS 0x0 #define UIAIS 0x20 /* Unimplemented Address Interrupt Status */ -#define nUIAIS 0x0 #define AAIS 0x40 /* Abort Acknowledge Interrupt Status */ -#define nAAIS 0x0 #define RMLIS 0x80 /* Receive Message Lost Interrupt Status */ -#define nRMLIS 0x0 #define UCEIS 0x100 /* Universal Counter Exceeded Interrupt Status */ -#define nUCEIS 0x0 #define ADIS 0x400 /* Access Denied Interrupt Status */ -#define nADIS 0x0 /* Bit masks for CAN0_GIF */ #define EWTIF 0x1 /* Error Warning Transmit Interrupt Flag */ -#define nEWTIF 0x0 #define EWRIF 0x2 /* Error Warning Receive Interrupt Flag */ -#define nEWRIF 0x0 #define EPIF 0x4 /* Error Passive Interrupt Flag */ -#define nEPIF 0x0 #define BOIF 0x8 /* Bus Off Interrupt Flag */ -#define nBOIF 0x0 #define WUIF 0x10 /* Wakeup Interrupt Flag */ -#define nWUIF 0x0 #define UIAIF 0x20 /* Unimplemented Address Interrupt Flag */ -#define nUIAIF 0x0 #define AAIF 0x40 /* Abort Acknowledge Interrupt Flag */ -#define nAAIF 0x0 #define RMLIF 0x80 /* Receive Message Lost Interrupt Flag */ -#define nRMLIF 0x0 #define UCEIF 0x100 /* Universal Counter Exceeded Interrupt Flag */ -#define nUCEIF 0x0 #define ADIF 0x400 /* Access Denied Interrupt Flag */ -#define nADIF 0x0 /* Bit masks for CAN0_MBTD */ #define TDR 0x80 /* Temporary Disable Request */ -#define nTDR 0x0 #define TDA 0x40 /* Temporary Disable Acknowledge */ -#define nTDA 0x0 #define TDPTR 0x1f /* Temporary Disable Pointer */ /* Bit masks for CAN0_UCCNF */ #define UCCNF 0xf /* Universal Counter Configuration */ #define UCRC 0x20 /* Universal Counter Reload/Clear */ -#define nUCRC 0x0 #define UCCT 0x40 /* Universal Counter CAN Trigger */ -#define nUCCT 0x0 #define UCE 0x80 /* Universal Counter Enable */ -#define nUCE 0x0 /* Bit masks for CAN0_UCCNT */ @@ -2871,17 +2451,11 @@ /* Bit masks for CAN0_ESR */ #define FER 0x80 /* Form Error */ -#define nFER 0x0 #define BEF 0x40 /* Bit Error Flag */ -#define nBEF 0x0 #define SA0 0x20 /* Stuck At Dominant */ -#define nSA0 0x0 #define CRCE 0x10 /* CRC Error */ -#define nCRCE 0x0 #define SER 0x8 /* Stuff Bit Error */ -#define nSER 0x0 #define ACKE 0x4 /* Acknowledge Error */ -#define nACKE 0x0 /* Bit masks for CAN0_EWR */ @@ -2891,11 +2465,8 @@ /* Bit masks for CAN0_AMxx_H */ #define FDF 0x8000 /* Filter On Data Field */ -#define nFDF 0x0 #define FMD 0x4000 /* Full Mask Data */ -#define nFMD 0x0 #define AMIDE 0x2000 /* Acceptance Mask Identifier Extension */ -#define nAMIDE 0x0 #define BASEID 0x1ffc /* Base Identifier */ #define EXTID_HI 0x3 /* Extended Identifier High Bits */ @@ -2907,11 +2478,8 @@ /* Bit masks for CAN0_MBxx_ID1 */ #define AME 0x8000 /* Acceptance Mask Enable */ -#define nAME 0x0 #define RTR 0x4000 /* Remote Transmission Request */ -#define nRTR 0x0 #define IDE 0x2000 /* Identifier Extension */ -#define nIDE 0x0 #define BASEID 0x1ffc /* Base Identifier */ #define EXTID_HI 0x3 /* Extended Identifier High Bits */ @@ -2951,980 +2519,546 @@ /* Bit masks for CAN0_MC1 */ #define MC0 0x1 /* Mailbox 0 Enable */ -#define nMC0 0x0 #define MC1 0x2 /* Mailbox 1 Enable */ -#define nMC1 0x0 #define MC2 0x4 /* Mailbox 2 Enable */ -#define nMC2 0x0 #define MC3 0x8 /* Mailbox 3 Enable */ -#define nMC3 0x0 #define MC4 0x10 /* Mailbox 4 Enable */ -#define nMC4 0x0 #define MC5 0x20 /* Mailbox 5 Enable */ -#define nMC5 0x0 #define MC6 0x40 /* Mailbox 6 Enable */ -#define nMC6 0x0 #define MC7 0x80 /* Mailbox 7 Enable */ -#define nMC7 0x0 #define MC8 0x100 /* Mailbox 8 Enable */ -#define nMC8 0x0 #define MC9 0x200 /* Mailbox 9 Enable */ -#define nMC9 0x0 #define MC10 0x400 /* Mailbox 10 Enable */ -#define nMC10 0x0 #define MC11 0x800 /* Mailbox 11 Enable */ -#define nMC11 0x0 #define MC12 0x1000 /* Mailbox 12 Enable */ -#define nMC12 0x0 #define MC13 0x2000 /* Mailbox 13 Enable */ -#define nMC13 0x0 #define MC14 0x4000 /* Mailbox 14 Enable */ -#define nMC14 0x0 #define MC15 0x8000 /* Mailbox 15 Enable */ -#define nMC15 0x0 /* Bit masks for CAN0_MC2 */ #define MC16 0x1 /* Mailbox 16 Enable */ -#define nMC16 0x0 #define MC17 0x2 /* Mailbox 17 Enable */ -#define nMC17 0x0 #define MC18 0x4 /* Mailbox 18 Enable */ -#define nMC18 0x0 #define MC19 0x8 /* Mailbox 19 Enable */ -#define nMC19 0x0 #define MC20 0x10 /* Mailbox 20 Enable */ -#define nMC20 0x0 #define MC21 0x20 /* Mailbox 21 Enable */ -#define nMC21 0x0 #define MC22 0x40 /* Mailbox 22 Enable */ -#define nMC22 0x0 #define MC23 0x80 /* Mailbox 23 Enable */ -#define nMC23 0x0 #define MC24 0x100 /* Mailbox 24 Enable */ -#define nMC24 0x0 #define MC25 0x200 /* Mailbox 25 Enable */ -#define nMC25 0x0 #define MC26 0x400 /* Mailbox 26 Enable */ -#define nMC26 0x0 #define MC27 0x800 /* Mailbox 27 Enable */ -#define nMC27 0x0 #define MC28 0x1000 /* Mailbox 28 Enable */ -#define nMC28 0x0 #define MC29 0x2000 /* Mailbox 29 Enable */ -#define nMC29 0x0 #define MC30 0x4000 /* Mailbox 30 Enable */ -#define nMC30 0x0 #define MC31 0x8000 /* Mailbox 31 Enable */ -#define nMC31 0x0 /* Bit masks for CAN0_MD1 */ #define MD0 0x1 /* Mailbox 0 Receive Enable */ -#define nMD0 0x0 #define MD1 0x2 /* Mailbox 1 Receive Enable */ -#define nMD1 0x0 #define MD2 0x4 /* Mailbox 2 Receive Enable */ -#define nMD2 0x0 #define MD3 0x8 /* Mailbox 3 Receive Enable */ -#define nMD3 0x0 #define MD4 0x10 /* Mailbox 4 Receive Enable */ -#define nMD4 0x0 #define MD5 0x20 /* Mailbox 5 Receive Enable */ -#define nMD5 0x0 #define MD6 0x40 /* Mailbox 6 Receive Enable */ -#define nMD6 0x0 #define MD7 0x80 /* Mailbox 7 Receive Enable */ -#define nMD7 0x0 #define MD8 0x100 /* Mailbox 8 Receive Enable */ -#define nMD8 0x0 #define MD9 0x200 /* Mailbox 9 Receive Enable */ -#define nMD9 0x0 #define MD10 0x400 /* Mailbox 10 Receive Enable */ -#define nMD10 0x0 #define MD11 0x800 /* Mailbox 11 Receive Enable */ -#define nMD11 0x0 #define MD12 0x1000 /* Mailbox 12 Receive Enable */ -#define nMD12 0x0 #define MD13 0x2000 /* Mailbox 13 Receive Enable */ -#define nMD13 0x0 #define MD14 0x4000 /* Mailbox 14 Receive Enable */ -#define nMD14 0x0 #define MD15 0x8000 /* Mailbox 15 Receive Enable */ -#define nMD15 0x0 /* Bit masks for CAN0_MD2 */ #define MD16 0x1 /* Mailbox 16 Receive Enable */ -#define nMD16 0x0 #define MD17 0x2 /* Mailbox 17 Receive Enable */ -#define nMD17 0x0 #define MD18 0x4 /* Mailbox 18 Receive Enable */ -#define nMD18 0x0 #define MD19 0x8 /* Mailbox 19 Receive Enable */ -#define nMD19 0x0 #define MD20 0x10 /* Mailbox 20 Receive Enable */ -#define nMD20 0x0 #define MD21 0x20 /* Mailbox 21 Receive Enable */ -#define nMD21 0x0 #define MD22 0x40 /* Mailbox 22 Receive Enable */ -#define nMD22 0x0 #define MD23 0x80 /* Mailbox 23 Receive Enable */ -#define nMD23 0x0 #define MD24 0x100 /* Mailbox 24 Receive Enable */ -#define nMD24 0x0 #define MD25 0x200 /* Mailbox 25 Receive Enable */ -#define nMD25 0x0 #define MD26 0x400 /* Mailbox 26 Receive Enable */ -#define nMD26 0x0 #define MD27 0x800 /* Mailbox 27 Receive Enable */ -#define nMD27 0x0 #define MD28 0x1000 /* Mailbox 28 Receive Enable */ -#define nMD28 0x0 #define MD29 0x2000 /* Mailbox 29 Receive Enable */ -#define nMD29 0x0 #define MD30 0x4000 /* Mailbox 30 Receive Enable */ -#define nMD30 0x0 #define MD31 0x8000 /* Mailbox 31 Receive Enable */ -#define nMD31 0x0 /* Bit masks for CAN0_RMP1 */ #define RMP0 0x1 /* Mailbox 0 Receive Message Pending */ -#define nRMP0 0x0 #define RMP1 0x2 /* Mailbox 1 Receive Message Pending */ -#define nRMP1 0x0 #define RMP2 0x4 /* Mailbox 2 Receive Message Pending */ -#define nRMP2 0x0 #define RMP3 0x8 /* Mailbox 3 Receive Message Pending */ -#define nRMP3 0x0 #define RMP4 0x10 /* Mailbox 4 Receive Message Pending */ -#define nRMP4 0x0 #define RMP5 0x20 /* Mailbox 5 Receive Message Pending */ -#define nRMP5 0x0 #define RMP6 0x40 /* Mailbox 6 Receive Message Pending */ -#define nRMP6 0x0 #define RMP7 0x80 /* Mailbox 7 Receive Message Pending */ -#define nRMP7 0x0 #define RMP8 0x100 /* Mailbox 8 Receive Message Pending */ -#define nRMP8 0x0 #define RMP9 0x200 /* Mailbox 9 Receive Message Pending */ -#define nRMP9 0x0 #define RMP10 0x400 /* Mailbox 10 Receive Message Pending */ -#define nRMP10 0x0 #define RMP11 0x800 /* Mailbox 11 Receive Message Pending */ -#define nRMP11 0x0 #define RMP12 0x1000 /* Mailbox 12 Receive Message Pending */ -#define nRMP12 0x0 #define RMP13 0x2000 /* Mailbox 13 Receive Message Pending */ -#define nRMP13 0x0 #define RMP14 0x4000 /* Mailbox 14 Receive Message Pending */ -#define nRMP14 0x0 #define RMP15 0x8000 /* Mailbox 15 Receive Message Pending */ -#define nRMP15 0x0 /* Bit masks for CAN0_RMP2 */ #define RMP16 0x1 /* Mailbox 16 Receive Message Pending */ -#define nRMP16 0x0 #define RMP17 0x2 /* Mailbox 17 Receive Message Pending */ -#define nRMP17 0x0 #define RMP18 0x4 /* Mailbox 18 Receive Message Pending */ -#define nRMP18 0x0 #define RMP19 0x8 /* Mailbox 19 Receive Message Pending */ -#define nRMP19 0x0 #define RMP20 0x10 /* Mailbox 20 Receive Message Pending */ -#define nRMP20 0x0 #define RMP21 0x20 /* Mailbox 21 Receive Message Pending */ -#define nRMP21 0x0 #define RMP22 0x40 /* Mailbox 22 Receive Message Pending */ -#define nRMP22 0x0 #define RMP23 0x80 /* Mailbox 23 Receive Message Pending */ -#define nRMP23 0x0 #define RMP24 0x100 /* Mailbox 24 Receive Message Pending */ -#define nRMP24 0x0 #define RMP25 0x200 /* Mailbox 25 Receive Message Pending */ -#define nRMP25 0x0 #define RMP26 0x400 /* Mailbox 26 Receive Message Pending */ -#define nRMP26 0x0 #define RMP27 0x800 /* Mailbox 27 Receive Message Pending */ -#define nRMP27 0x0 #define RMP28 0x1000 /* Mailbox 28 Receive Message Pending */ -#define nRMP28 0x0 #define RMP29 0x2000 /* Mailbox 29 Receive Message Pending */ -#define nRMP29 0x0 #define RMP30 0x4000 /* Mailbox 30 Receive Message Pending */ -#define nRMP30 0x0 #define RMP31 0x8000 /* Mailbox 31 Receive Message Pending */ -#define nRMP31 0x0 /* Bit masks for CAN0_RML1 */ #define RML0 0x1 /* Mailbox 0 Receive Message Lost */ -#define nRML0 0x0 #define RML1 0x2 /* Mailbox 1 Receive Message Lost */ -#define nRML1 0x0 #define RML2 0x4 /* Mailbox 2 Receive Message Lost */ -#define nRML2 0x0 #define RML3 0x8 /* Mailbox 3 Receive Message Lost */ -#define nRML3 0x0 #define RML4 0x10 /* Mailbox 4 Receive Message Lost */ -#define nRML4 0x0 #define RML5 0x20 /* Mailbox 5 Receive Message Lost */ -#define nRML5 0x0 #define RML6 0x40 /* Mailbox 6 Receive Message Lost */ -#define nRML6 0x0 #define RML7 0x80 /* Mailbox 7 Receive Message Lost */ -#define nRML7 0x0 #define RML8 0x100 /* Mailbox 8 Receive Message Lost */ -#define nRML8 0x0 #define RML9 0x200 /* Mailbox 9 Receive Message Lost */ -#define nRML9 0x0 #define RML10 0x400 /* Mailbox 10 Receive Message Lost */ -#define nRML10 0x0 #define RML11 0x800 /* Mailbox 11 Receive Message Lost */ -#define nRML11 0x0 #define RML12 0x1000 /* Mailbox 12 Receive Message Lost */ -#define nRML12 0x0 #define RML13 0x2000 /* Mailbox 13 Receive Message Lost */ -#define nRML13 0x0 #define RML14 0x4000 /* Mailbox 14 Receive Message Lost */ -#define nRML14 0x0 #define RML15 0x8000 /* Mailbox 15 Receive Message Lost */ -#define nRML15 0x0 /* Bit masks for CAN0_RML2 */ #define RML16 0x1 /* Mailbox 16 Receive Message Lost */ -#define nRML16 0x0 #define RML17 0x2 /* Mailbox 17 Receive Message Lost */ -#define nRML17 0x0 #define RML18 0x4 /* Mailbox 18 Receive Message Lost */ -#define nRML18 0x0 #define RML19 0x8 /* Mailbox 19 Receive Message Lost */ -#define nRML19 0x0 #define RML20 0x10 /* Mailbox 20 Receive Message Lost */ -#define nRML20 0x0 #define RML21 0x20 /* Mailbox 21 Receive Message Lost */ -#define nRML21 0x0 #define RML22 0x40 /* Mailbox 22 Receive Message Lost */ -#define nRML22 0x0 #define RML23 0x80 /* Mailbox 23 Receive Message Lost */ -#define nRML23 0x0 #define RML24 0x100 /* Mailbox 24 Receive Message Lost */ -#define nRML24 0x0 #define RML25 0x200 /* Mailbox 25 Receive Message Lost */ -#define nRML25 0x0 #define RML26 0x400 /* Mailbox 26 Receive Message Lost */ -#define nRML26 0x0 #define RML27 0x800 /* Mailbox 27 Receive Message Lost */ -#define nRML27 0x0 #define RML28 0x1000 /* Mailbox 28 Receive Message Lost */ -#define nRML28 0x0 #define RML29 0x2000 /* Mailbox 29 Receive Message Lost */ -#define nRML29 0x0 #define RML30 0x4000 /* Mailbox 30 Receive Message Lost */ -#define nRML30 0x0 #define RML31 0x8000 /* Mailbox 31 Receive Message Lost */ -#define nRML31 0x0 /* Bit masks for CAN0_OPSS1 */ #define OPSS0 0x1 /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS0 0x0 #define OPSS1 0x2 /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS1 0x0 #define OPSS2 0x4 /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS2 0x0 #define OPSS3 0x8 /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS3 0x0 #define OPSS4 0x10 /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS4 0x0 #define OPSS5 0x20 /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS5 0x0 #define OPSS6 0x40 /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS6 0x0 #define OPSS7 0x80 /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS7 0x0 #define OPSS8 0x100 /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS8 0x0 #define OPSS9 0x200 /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS9 0x0 #define OPSS10 0x400 /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS10 0x0 #define OPSS11 0x800 /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS11 0x0 #define OPSS12 0x1000 /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS12 0x0 #define OPSS13 0x2000 /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS13 0x0 #define OPSS14 0x4000 /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS14 0x0 #define OPSS15 0x8000 /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS15 0x0 /* Bit masks for CAN0_OPSS2 */ #define OPSS16 0x1 /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS16 0x0 #define OPSS17 0x2 /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS17 0x0 #define OPSS18 0x4 /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS18 0x0 #define OPSS19 0x8 /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS19 0x0 #define OPSS20 0x10 /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS20 0x0 #define OPSS21 0x20 /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS21 0x0 #define OPSS22 0x40 /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS22 0x0 #define OPSS23 0x80 /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS23 0x0 #define OPSS24 0x100 /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS24 0x0 #define OPSS25 0x200 /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS25 0x0 #define OPSS26 0x400 /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS26 0x0 #define OPSS27 0x800 /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS27 0x0 #define OPSS28 0x1000 /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS28 0x0 #define OPSS29 0x2000 /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS29 0x0 #define OPSS30 0x4000 /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS30 0x0 #define OPSS31 0x8000 /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */ -#define nOPSS31 0x0 /* Bit masks for CAN0_TRS1 */ #define TRS0 0x1 /* Mailbox 0 Transmit Request Set */ -#define nTRS0 0x0 #define TRS1 0x2 /* Mailbox 1 Transmit Request Set */ -#define nTRS1 0x0 #define TRS2 0x4 /* Mailbox 2 Transmit Request Set */ -#define nTRS2 0x0 #define TRS3 0x8 /* Mailbox 3 Transmit Request Set */ -#define nTRS3 0x0 #define TRS4 0x10 /* Mailbox 4 Transmit Request Set */ -#define nTRS4 0x0 #define TRS5 0x20 /* Mailbox 5 Transmit Request Set */ -#define nTRS5 0x0 #define TRS6 0x40 /* Mailbox 6 Transmit Request Set */ -#define nTRS6 0x0 #define TRS7 0x80 /* Mailbox 7 Transmit Request Set */ -#define nTRS7 0x0 #define TRS8 0x100 /* Mailbox 8 Transmit Request Set */ -#define nTRS8 0x0 #define TRS9 0x200 /* Mailbox 9 Transmit Request Set */ -#define nTRS9 0x0 #define TRS10 0x400 /* Mailbox 10 Transmit Request Set */ -#define nTRS10 0x0 #define TRS11 0x800 /* Mailbox 11 Transmit Request Set */ -#define nTRS11 0x0 #define TRS12 0x1000 /* Mailbox 12 Transmit Request Set */ -#define nTRS12 0x0 #define TRS13 0x2000 /* Mailbox 13 Transmit Request Set */ -#define nTRS13 0x0 #define TRS14 0x4000 /* Mailbox 14 Transmit Request Set */ -#define nTRS14 0x0 #define TRS15 0x8000 /* Mailbox 15 Transmit Request Set */ -#define nTRS15 0x0 /* Bit masks for CAN0_TRS2 */ #define TRS16 0x1 /* Mailbox 16 Transmit Request Set */ -#define nTRS16 0x0 #define TRS17 0x2 /* Mailbox 17 Transmit Request Set */ -#define nTRS17 0x0 #define TRS18 0x4 /* Mailbox 18 Transmit Request Set */ -#define nTRS18 0x0 #define TRS19 0x8 /* Mailbox 19 Transmit Request Set */ -#define nTRS19 0x0 #define TRS20 0x10 /* Mailbox 20 Transmit Request Set */ -#define nTRS20 0x0 #define TRS21 0x20 /* Mailbox 21 Transmit Request Set */ -#define nTRS21 0x0 #define TRS22 0x40 /* Mailbox 22 Transmit Request Set */ -#define nTRS22 0x0 #define TRS23 0x80 /* Mailbox 23 Transmit Request Set */ -#define nTRS23 0x0 #define TRS24 0x100 /* Mailbox 24 Transmit Request Set */ -#define nTRS24 0x0 #define TRS25 0x200 /* Mailbox 25 Transmit Request Set */ -#define nTRS25 0x0 #define TRS26 0x400 /* Mailbox 26 Transmit Request Set */ -#define nTRS26 0x0 #define TRS27 0x800 /* Mailbox 27 Transmit Request Set */ -#define nTRS27 0x0 #define TRS28 0x1000 /* Mailbox 28 Transmit Request Set */ -#define nTRS28 0x0 #define TRS29 0x2000 /* Mailbox 29 Transmit Request Set */ -#define nTRS29 0x0 #define TRS30 0x4000 /* Mailbox 30 Transmit Request Set */ -#define nTRS30 0x0 #define TRS31 0x8000 /* Mailbox 31 Transmit Request Set */ -#define nTRS31 0x0 /* Bit masks for CAN0_TRR1 */ #define TRR0 0x1 /* Mailbox 0 Transmit Request Reset */ -#define nTRR0 0x0 #define TRR1 0x2 /* Mailbox 1 Transmit Request Reset */ -#define nTRR1 0x0 #define TRR2 0x4 /* Mailbox 2 Transmit Request Reset */ -#define nTRR2 0x0 #define TRR3 0x8 /* Mailbox 3 Transmit Request Reset */ -#define nTRR3 0x0 #define TRR4 0x10 /* Mailbox 4 Transmit Request Reset */ -#define nTRR4 0x0 #define TRR5 0x20 /* Mailbox 5 Transmit Request Reset */ -#define nTRR5 0x0 #define TRR6 0x40 /* Mailbox 6 Transmit Request Reset */ -#define nTRR6 0x0 #define TRR7 0x80 /* Mailbox 7 Transmit Request Reset */ -#define nTRR7 0x0 #define TRR8 0x100 /* Mailbox 8 Transmit Request Reset */ -#define nTRR8 0x0 #define TRR9 0x200 /* Mailbox 9 Transmit Request Reset */ -#define nTRR9 0x0 #define TRR10 0x400 /* Mailbox 10 Transmit Request Reset */ -#define nTRR10 0x0 #define TRR11 0x800 /* Mailbox 11 Transmit Request Reset */ -#define nTRR11 0x0 #define TRR12 0x1000 /* Mailbox 12 Transmit Request Reset */ -#define nTRR12 0x0 #define TRR13 0x2000 /* Mailbox 13 Transmit Request Reset */ -#define nTRR13 0x0 #define TRR14 0x4000 /* Mailbox 14 Transmit Request Reset */ -#define nTRR14 0x0 #define TRR15 0x8000 /* Mailbox 15 Transmit Request Reset */ -#define nTRR15 0x0 /* Bit masks for CAN0_TRR2 */ #define TRR16 0x1 /* Mailbox 16 Transmit Request Reset */ -#define nTRR16 0x0 #define TRR17 0x2 /* Mailbox 17 Transmit Request Reset */ -#define nTRR17 0x0 #define TRR18 0x4 /* Mailbox 18 Transmit Request Reset */ -#define nTRR18 0x0 #define TRR19 0x8 /* Mailbox 19 Transmit Request Reset */ -#define nTRR19 0x0 #define TRR20 0x10 /* Mailbox 20 Transmit Request Reset */ -#define nTRR20 0x0 #define TRR21 0x20 /* Mailbox 21 Transmit Request Reset */ -#define nTRR21 0x0 #define TRR22 0x40 /* Mailbox 22 Transmit Request Reset */ -#define nTRR22 0x0 #define TRR23 0x80 /* Mailbox 23 Transmit Request Reset */ -#define nTRR23 0x0 #define TRR24 0x100 /* Mailbox 24 Transmit Request Reset */ -#define nTRR24 0x0 #define TRR25 0x200 /* Mailbox 25 Transmit Request Reset */ -#define nTRR25 0x0 #define TRR26 0x400 /* Mailbox 26 Transmit Request Reset */ -#define nTRR26 0x0 #define TRR27 0x800 /* Mailbox 27 Transmit Request Reset */ -#define nTRR27 0x0 #define TRR28 0x1000 /* Mailbox 28 Transmit Request Reset */ -#define nTRR28 0x0 #define TRR29 0x2000 /* Mailbox 29 Transmit Request Reset */ -#define nTRR29 0x0 #define TRR30 0x4000 /* Mailbox 30 Transmit Request Reset */ -#define nTRR30 0x0 #define TRR31 0x8000 /* Mailbox 31 Transmit Request Reset */ -#define nTRR31 0x0 /* Bit masks for CAN0_AA1 */ #define AA0 0x1 /* Mailbox 0 Abort Acknowledge */ -#define nAA0 0x0 #define AA1 0x2 /* Mailbox 1 Abort Acknowledge */ -#define nAA1 0x0 #define AA2 0x4 /* Mailbox 2 Abort Acknowledge */ -#define nAA2 0x0 #define AA3 0x8 /* Mailbox 3 Abort Acknowledge */ -#define nAA3 0x0 #define AA4 0x10 /* Mailbox 4 Abort Acknowledge */ -#define nAA4 0x0 #define AA5 0x20 /* Mailbox 5 Abort Acknowledge */ -#define nAA5 0x0 #define AA6 0x40 /* Mailbox 6 Abort Acknowledge */ -#define nAA6 0x0 #define AA7 0x80 /* Mailbox 7 Abort Acknowledge */ -#define nAA7 0x0 #define AA8 0x100 /* Mailbox 8 Abort Acknowledge */ -#define nAA8 0x0 #define AA9 0x200 /* Mailbox 9 Abort Acknowledge */ -#define nAA9 0x0 #define AA10 0x400 /* Mailbox 10 Abort Acknowledge */ -#define nAA10 0x0 #define AA11 0x800 /* Mailbox 11 Abort Acknowledge */ -#define nAA11 0x0 #define AA12 0x1000 /* Mailbox 12 Abort Acknowledge */ -#define nAA12 0x0 #define AA13 0x2000 /* Mailbox 13 Abort Acknowledge */ -#define nAA13 0x0 #define AA14 0x4000 /* Mailbox 14 Abort Acknowledge */ -#define nAA14 0x0 #define AA15 0x8000 /* Mailbox 15 Abort Acknowledge */ -#define nAA15 0x0 /* Bit masks for CAN0_AA2 */ #define AA16 0x1 /* Mailbox 16 Abort Acknowledge */ -#define nAA16 0x0 #define AA17 0x2 /* Mailbox 17 Abort Acknowledge */ -#define nAA17 0x0 #define AA18 0x4 /* Mailbox 18 Abort Acknowledge */ -#define nAA18 0x0 #define AA19 0x8 /* Mailbox 19 Abort Acknowledge */ -#define nAA19 0x0 #define AA20 0x10 /* Mailbox 20 Abort Acknowledge */ -#define nAA20 0x0 #define AA21 0x20 /* Mailbox 21 Abort Acknowledge */ -#define nAA21 0x0 #define AA22 0x40 /* Mailbox 22 Abort Acknowledge */ -#define nAA22 0x0 #define AA23 0x80 /* Mailbox 23 Abort Acknowledge */ -#define nAA23 0x0 #define AA24 0x100 /* Mailbox 24 Abort Acknowledge */ -#define nAA24 0x0 #define AA25 0x200 /* Mailbox 25 Abort Acknowledge */ -#define nAA25 0x0 #define AA26 0x400 /* Mailbox 26 Abort Acknowledge */ -#define nAA26 0x0 #define AA27 0x800 /* Mailbox 27 Abort Acknowledge */ -#define nAA27 0x0 #define AA28 0x1000 /* Mailbox 28 Abort Acknowledge */ -#define nAA28 0x0 #define AA29 0x2000 /* Mailbox 29 Abort Acknowledge */ -#define nAA29 0x0 #define AA30 0x4000 /* Mailbox 30 Abort Acknowledge */ -#define nAA30 0x0 #define AA31 0x8000 /* Mailbox 31 Abort Acknowledge */ -#define nAA31 0x0 /* Bit masks for CAN0_TA1 */ #define TA0 0x1 /* Mailbox 0 Transmit Acknowledge */ -#define nTA0 0x0 #define TA1 0x2 /* Mailbox 1 Transmit Acknowledge */ -#define nTA1 0x0 #define TA2 0x4 /* Mailbox 2 Transmit Acknowledge */ -#define nTA2 0x0 #define TA3 0x8 /* Mailbox 3 Transmit Acknowledge */ -#define nTA3 0x0 #define TA4 0x10 /* Mailbox 4 Transmit Acknowledge */ -#define nTA4 0x0 #define TA5 0x20 /* Mailbox 5 Transmit Acknowledge */ -#define nTA5 0x0 #define TA6 0x40 /* Mailbox 6 Transmit Acknowledge */ -#define nTA6 0x0 #define TA7 0x80 /* Mailbox 7 Transmit Acknowledge */ -#define nTA7 0x0 #define TA8 0x100 /* Mailbox 8 Transmit Acknowledge */ -#define nTA8 0x0 #define TA9 0x200 /* Mailbox 9 Transmit Acknowledge */ -#define nTA9 0x0 #define TA10 0x400 /* Mailbox 10 Transmit Acknowledge */ -#define nTA10 0x0 #define TA11 0x800 /* Mailbox 11 Transmit Acknowledge */ -#define nTA11 0x0 #define TA12 0x1000 /* Mailbox 12 Transmit Acknowledge */ -#define nTA12 0x0 #define TA13 0x2000 /* Mailbox 13 Transmit Acknowledge */ -#define nTA13 0x0 #define TA14 0x4000 /* Mailbox 14 Transmit Acknowledge */ -#define nTA14 0x0 #define TA15 0x8000 /* Mailbox 15 Transmit Acknowledge */ -#define nTA15 0x0 /* Bit masks for CAN0_TA2 */ #define TA16 0x1 /* Mailbox 16 Transmit Acknowledge */ -#define nTA16 0x0 #define TA17 0x2 /* Mailbox 17 Transmit Acknowledge */ -#define nTA17 0x0 #define TA18 0x4 /* Mailbox 18 Transmit Acknowledge */ -#define nTA18 0x0 #define TA19 0x8 /* Mailbox 19 Transmit Acknowledge */ -#define nTA19 0x0 #define TA20 0x10 /* Mailbox 20 Transmit Acknowledge */ -#define nTA20 0x0 #define TA21 0x20 /* Mailbox 21 Transmit Acknowledge */ -#define nTA21 0x0 #define TA22 0x40 /* Mailbox 22 Transmit Acknowledge */ -#define nTA22 0x0 #define TA23 0x80 /* Mailbox 23 Transmit Acknowledge */ -#define nTA23 0x0 #define TA24 0x100 /* Mailbox 24 Transmit Acknowledge */ -#define nTA24 0x0 #define TA25 0x200 /* Mailbox 25 Transmit Acknowledge */ -#define nTA25 0x0 #define TA26 0x400 /* Mailbox 26 Transmit Acknowledge */ -#define nTA26 0x0 #define TA27 0x800 /* Mailbox 27 Transmit Acknowledge */ -#define nTA27 0x0 #define TA28 0x1000 /* Mailbox 28 Transmit Acknowledge */ -#define nTA28 0x0 #define TA29 0x2000 /* Mailbox 29 Transmit Acknowledge */ -#define nTA29 0x0 #define TA30 0x4000 /* Mailbox 30 Transmit Acknowledge */ -#define nTA30 0x0 #define TA31 0x8000 /* Mailbox 31 Transmit Acknowledge */ -#define nTA31 0x0 /* Bit masks for CAN0_RFH1 */ #define RFH0 0x1 /* Mailbox 0 Remote Frame Handling Enable */ -#define nRFH0 0x0 #define RFH1 0x2 /* Mailbox 1 Remote Frame Handling Enable */ -#define nRFH1 0x0 #define RFH2 0x4 /* Mailbox 2 Remote Frame Handling Enable */ -#define nRFH2 0x0 #define RFH3 0x8 /* Mailbox 3 Remote Frame Handling Enable */ -#define nRFH3 0x0 #define RFH4 0x10 /* Mailbox 4 Remote Frame Handling Enable */ -#define nRFH4 0x0 #define RFH5 0x20 /* Mailbox 5 Remote Frame Handling Enable */ -#define nRFH5 0x0 #define RFH6 0x40 /* Mailbox 6 Remote Frame Handling Enable */ -#define nRFH6 0x0 #define RFH7 0x80 /* Mailbox 7 Remote Frame Handling Enable */ -#define nRFH7 0x0 #define RFH8 0x100 /* Mailbox 8 Remote Frame Handling Enable */ -#define nRFH8 0x0 #define RFH9 0x200 /* Mailbox 9 Remote Frame Handling Enable */ -#define nRFH9 0x0 #define RFH10 0x400 /* Mailbox 10 Remote Frame Handling Enable */ -#define nRFH10 0x0 #define RFH11 0x800 /* Mailbox 11 Remote Frame Handling Enable */ -#define nRFH11 0x0 #define RFH12 0x1000 /* Mailbox 12 Remote Frame Handling Enable */ -#define nRFH12 0x0 #define RFH13 0x2000 /* Mailbox 13 Remote Frame Handling Enable */ -#define nRFH13 0x0 #define RFH14 0x4000 /* Mailbox 14 Remote Frame Handling Enable */ -#define nRFH14 0x0 #define RFH15 0x8000 /* Mailbox 15 Remote Frame Handling Enable */ -#define nRFH15 0x0 /* Bit masks for CAN0_RFH2 */ #define RFH16 0x1 /* Mailbox 16 Remote Frame Handling Enable */ -#define nRFH16 0x0 #define RFH17 0x2 /* Mailbox 17 Remote Frame Handling Enable */ -#define nRFH17 0x0 #define RFH18 0x4 /* Mailbox 18 Remote Frame Handling Enable */ -#define nRFH18 0x0 #define RFH19 0x8 /* Mailbox 19 Remote Frame Handling Enable */ -#define nRFH19 0x0 #define RFH20 0x10 /* Mailbox 20 Remote Frame Handling Enable */ -#define nRFH20 0x0 #define RFH21 0x20 /* Mailbox 21 Remote Frame Handling Enable */ -#define nRFH21 0x0 #define RFH22 0x40 /* Mailbox 22 Remote Frame Handling Enable */ -#define nRFH22 0x0 #define RFH23 0x80 /* Mailbox 23 Remote Frame Handling Enable */ -#define nRFH23 0x0 #define RFH24 0x100 /* Mailbox 24 Remote Frame Handling Enable */ -#define nRFH24 0x0 #define RFH25 0x200 /* Mailbox 25 Remote Frame Handling Enable */ -#define nRFH25 0x0 #define RFH26 0x400 /* Mailbox 26 Remote Frame Handling Enable */ -#define nRFH26 0x0 #define RFH27 0x800 /* Mailbox 27 Remote Frame Handling Enable */ -#define nRFH27 0x0 #define RFH28 0x1000 /* Mailbox 28 Remote Frame Handling Enable */ -#define nRFH28 0x0 #define RFH29 0x2000 /* Mailbox 29 Remote Frame Handling Enable */ -#define nRFH29 0x0 #define RFH30 0x4000 /* Mailbox 30 Remote Frame Handling Enable */ -#define nRFH30 0x0 #define RFH31 0x8000 /* Mailbox 31 Remote Frame Handling Enable */ -#define nRFH31 0x0 /* Bit masks for CAN0_MBIM1 */ #define MBIM0 0x1 /* Mailbox 0 Mailbox Interrupt Mask */ -#define nMBIM0 0x0 #define MBIM1 0x2 /* Mailbox 1 Mailbox Interrupt Mask */ -#define nMBIM1 0x0 #define MBIM2 0x4 /* Mailbox 2 Mailbox Interrupt Mask */ -#define nMBIM2 0x0 #define MBIM3 0x8 /* Mailbox 3 Mailbox Interrupt Mask */ -#define nMBIM3 0x0 #define MBIM4 0x10 /* Mailbox 4 Mailbox Interrupt Mask */ -#define nMBIM4 0x0 #define MBIM5 0x20 /* Mailbox 5 Mailbox Interrupt Mask */ -#define nMBIM5 0x0 #define MBIM6 0x40 /* Mailbox 6 Mailbox Interrupt Mask */ -#define nMBIM6 0x0 #define MBIM7 0x80 /* Mailbox 7 Mailbox Interrupt Mask */ -#define nMBIM7 0x0 #define MBIM8 0x100 /* Mailbox 8 Mailbox Interrupt Mask */ -#define nMBIM8 0x0 #define MBIM9 0x200 /* Mailbox 9 Mailbox Interrupt Mask */ -#define nMBIM9 0x0 #define MBIM10 0x400 /* Mailbox 10 Mailbox Interrupt Mask */ -#define nMBIM10 0x0 #define MBIM11 0x800 /* Mailbox 11 Mailbox Interrupt Mask */ -#define nMBIM11 0x0 #define MBIM12 0x1000 /* Mailbox 12 Mailbox Interrupt Mask */ -#define nMBIM12 0x0 #define MBIM13 0x2000 /* Mailbox 13 Mailbox Interrupt Mask */ -#define nMBIM13 0x0 #define MBIM14 0x4000 /* Mailbox 14 Mailbox Interrupt Mask */ -#define nMBIM14 0x0 #define MBIM15 0x8000 /* Mailbox 15 Mailbox Interrupt Mask */ -#define nMBIM15 0x0 /* Bit masks for CAN0_MBIM2 */ #define MBIM16 0x1 /* Mailbox 16 Mailbox Interrupt Mask */ -#define nMBIM16 0x0 #define MBIM17 0x2 /* Mailbox 17 Mailbox Interrupt Mask */ -#define nMBIM17 0x0 #define MBIM18 0x4 /* Mailbox 18 Mailbox Interrupt Mask */ -#define nMBIM18 0x0 #define MBIM19 0x8 /* Mailbox 19 Mailbox Interrupt Mask */ -#define nMBIM19 0x0 #define MBIM20 0x10 /* Mailbox 20 Mailbox Interrupt Mask */ -#define nMBIM20 0x0 #define MBIM21 0x20 /* Mailbox 21 Mailbox Interrupt Mask */ -#define nMBIM21 0x0 #define MBIM22 0x40 /* Mailbox 22 Mailbox Interrupt Mask */ -#define nMBIM22 0x0 #define MBIM23 0x80 /* Mailbox 23 Mailbox Interrupt Mask */ -#define nMBIM23 0x0 #define MBIM24 0x100 /* Mailbox 24 Mailbox Interrupt Mask */ -#define nMBIM24 0x0 #define MBIM25 0x200 /* Mailbox 25 Mailbox Interrupt Mask */ -#define nMBIM25 0x0 #define MBIM26 0x400 /* Mailbox 26 Mailbox Interrupt Mask */ -#define nMBIM26 0x0 #define MBIM27 0x800 /* Mailbox 27 Mailbox Interrupt Mask */ -#define nMBIM27 0x0 #define MBIM28 0x1000 /* Mailbox 28 Mailbox Interrupt Mask */ -#define nMBIM28 0x0 #define MBIM29 0x2000 /* Mailbox 29 Mailbox Interrupt Mask */ -#define nMBIM29 0x0 #define MBIM30 0x4000 /* Mailbox 30 Mailbox Interrupt Mask */ -#define nMBIM30 0x0 #define MBIM31 0x8000 /* Mailbox 31 Mailbox Interrupt Mask */ -#define nMBIM31 0x0 /* Bit masks for CAN0_MBTIF1 */ #define MBTIF0 0x1 /* Mailbox 0 Mailbox Transmit Interrupt Flag */ -#define nMBTIF0 0x0 #define MBTIF1 0x2 /* Mailbox 1 Mailbox Transmit Interrupt Flag */ -#define nMBTIF1 0x0 #define MBTIF2 0x4 /* Mailbox 2 Mailbox Transmit Interrupt Flag */ -#define nMBTIF2 0x0 #define MBTIF3 0x8 /* Mailbox 3 Mailbox Transmit Interrupt Flag */ -#define nMBTIF3 0x0 #define MBTIF4 0x10 /* Mailbox 4 Mailbox Transmit Interrupt Flag */ -#define nMBTIF4 0x0 #define MBTIF5 0x20 /* Mailbox 5 Mailbox Transmit Interrupt Flag */ -#define nMBTIF5 0x0 #define MBTIF6 0x40 /* Mailbox 6 Mailbox Transmit Interrupt Flag */ -#define nMBTIF6 0x0 #define MBTIF7 0x80 /* Mailbox 7 Mailbox Transmit Interrupt Flag */ -#define nMBTIF7 0x0 #define MBTIF8 0x100 /* Mailbox 8 Mailbox Transmit Interrupt Flag */ -#define nMBTIF8 0x0 #define MBTIF9 0x200 /* Mailbox 9 Mailbox Transmit Interrupt Flag */ -#define nMBTIF9 0x0 #define MBTIF10 0x400 /* Mailbox 10 Mailbox Transmit Interrupt Flag */ -#define nMBTIF10 0x0 #define MBTIF11 0x800 /* Mailbox 11 Mailbox Transmit Interrupt Flag */ -#define nMBTIF11 0x0 #define MBTIF12 0x1000 /* Mailbox 12 Mailbox Transmit Interrupt Flag */ -#define nMBTIF12 0x0 #define MBTIF13 0x2000 /* Mailbox 13 Mailbox Transmit Interrupt Flag */ -#define nMBTIF13 0x0 #define MBTIF14 0x4000 /* Mailbox 14 Mailbox Transmit Interrupt Flag */ -#define nMBTIF14 0x0 #define MBTIF15 0x8000 /* Mailbox 15 Mailbox Transmit Interrupt Flag */ -#define nMBTIF15 0x0 /* Bit masks for CAN0_MBTIF2 */ #define MBTIF16 0x1 /* Mailbox 16 Mailbox Transmit Interrupt Flag */ -#define nMBTIF16 0x0 #define MBTIF17 0x2 /* Mailbox 17 Mailbox Transmit Interrupt Flag */ -#define nMBTIF17 0x0 #define MBTIF18 0x4 /* Mailbox 18 Mailbox Transmit Interrupt Flag */ -#define nMBTIF18 0x0 #define MBTIF19 0x8 /* Mailbox 19 Mailbox Transmit Interrupt Flag */ -#define nMBTIF19 0x0 #define MBTIF20 0x10 /* Mailbox 20 Mailbox Transmit Interrupt Flag */ -#define nMBTIF20 0x0 #define MBTIF21 0x20 /* Mailbox 21 Mailbox Transmit Interrupt Flag */ -#define nMBTIF21 0x0 #define MBTIF22 0x40 /* Mailbox 22 Mailbox Transmit Interrupt Flag */ -#define nMBTIF22 0x0 #define MBTIF23 0x80 /* Mailbox 23 Mailbox Transmit Interrupt Flag */ -#define nMBTIF23 0x0 #define MBTIF24 0x100 /* Mailbox 24 Mailbox Transmit Interrupt Flag */ -#define nMBTIF24 0x0 #define MBTIF25 0x200 /* Mailbox 25 Mailbox Transmit Interrupt Flag */ -#define nMBTIF25 0x0 #define MBTIF26 0x400 /* Mailbox 26 Mailbox Transmit Interrupt Flag */ -#define nMBTIF26 0x0 #define MBTIF27 0x800 /* Mailbox 27 Mailbox Transmit Interrupt Flag */ -#define nMBTIF27 0x0 #define MBTIF28 0x1000 /* Mailbox 28 Mailbox Transmit Interrupt Flag */ -#define nMBTIF28 0x0 #define MBTIF29 0x2000 /* Mailbox 29 Mailbox Transmit Interrupt Flag */ -#define nMBTIF29 0x0 #define MBTIF30 0x4000 /* Mailbox 30 Mailbox Transmit Interrupt Flag */ -#define nMBTIF30 0x0 #define MBTIF31 0x8000 /* Mailbox 31 Mailbox Transmit Interrupt Flag */ -#define nMBTIF31 0x0 /* Bit masks for CAN0_MBRIF1 */ #define MBRIF0 0x1 /* Mailbox 0 Mailbox Receive Interrupt Flag */ -#define nMBRIF0 0x0 #define MBRIF1 0x2 /* Mailbox 1 Mailbox Receive Interrupt Flag */ -#define nMBRIF1 0x0 #define MBRIF2 0x4 /* Mailbox 2 Mailbox Receive Interrupt Flag */ -#define nMBRIF2 0x0 #define MBRIF3 0x8 /* Mailbox 3 Mailbox Receive Interrupt Flag */ -#define nMBRIF3 0x0 #define MBRIF4 0x10 /* Mailbox 4 Mailbox Receive Interrupt Flag */ -#define nMBRIF4 0x0 #define MBRIF5 0x20 /* Mailbox 5 Mailbox Receive Interrupt Flag */ -#define nMBRIF5 0x0 #define MBRIF6 0x40 /* Mailbox 6 Mailbox Receive Interrupt Flag */ -#define nMBRIF6 0x0 #define MBRIF7 0x80 /* Mailbox 7 Mailbox Receive Interrupt Flag */ -#define nMBRIF7 0x0 #define MBRIF8 0x100 /* Mailbox 8 Mailbox Receive Interrupt Flag */ -#define nMBRIF8 0x0 #define MBRIF9 0x200 /* Mailbox 9 Mailbox Receive Interrupt Flag */ -#define nMBRIF9 0x0 #define MBRIF10 0x400 /* Mailbox 10 Mailbox Receive Interrupt Flag */ -#define nMBRIF10 0x0 #define MBRIF11 0x800 /* Mailbox 11 Mailbox Receive Interrupt Flag */ -#define nMBRIF11 0x0 #define MBRIF12 0x1000 /* Mailbox 12 Mailbox Receive Interrupt Flag */ -#define nMBRIF12 0x0 #define MBRIF13 0x2000 /* Mailbox 13 Mailbox Receive Interrupt Flag */ -#define nMBRIF13 0x0 #define MBRIF14 0x4000 /* Mailbox 14 Mailbox Receive Interrupt Flag */ -#define nMBRIF14 0x0 #define MBRIF15 0x8000 /* Mailbox 15 Mailbox Receive Interrupt Flag */ -#define nMBRIF15 0x0 /* Bit masks for CAN0_MBRIF2 */ #define MBRIF16 0x1 /* Mailbox 16 Mailbox Receive Interrupt Flag */ -#define nMBRIF16 0x0 #define MBRIF17 0x2 /* Mailbox 17 Mailbox Receive Interrupt Flag */ -#define nMBRIF17 0x0 #define MBRIF18 0x4 /* Mailbox 18 Mailbox Receive Interrupt Flag */ -#define nMBRIF18 0x0 #define MBRIF19 0x8 /* Mailbox 19 Mailbox Receive Interrupt Flag */ -#define nMBRIF19 0x0 #define MBRIF20 0x10 /* Mailbox 20 Mailbox Receive Interrupt Flag */ -#define nMBRIF20 0x0 #define MBRIF21 0x20 /* Mailbox 21 Mailbox Receive Interrupt Flag */ -#define nMBRIF21 0x0 #define MBRIF22 0x40 /* Mailbox 22 Mailbox Receive Interrupt Flag */ -#define nMBRIF22 0x0 #define MBRIF23 0x80 /* Mailbox 23 Mailbox Receive Interrupt Flag */ -#define nMBRIF23 0x0 #define MBRIF24 0x100 /* Mailbox 24 Mailbox Receive Interrupt Flag */ -#define nMBRIF24 0x0 #define MBRIF25 0x200 /* Mailbox 25 Mailbox Receive Interrupt Flag */ -#define nMBRIF25 0x0 #define MBRIF26 0x400 /* Mailbox 26 Mailbox Receive Interrupt Flag */ -#define nMBRIF26 0x0 #define MBRIF27 0x800 /* Mailbox 27 Mailbox Receive Interrupt Flag */ -#define nMBRIF27 0x0 #define MBRIF28 0x1000 /* Mailbox 28 Mailbox Receive Interrupt Flag */ -#define nMBRIF28 0x0 #define MBRIF29 0x2000 /* Mailbox 29 Mailbox Receive Interrupt Flag */ -#define nMBRIF29 0x0 #define MBRIF30 0x4000 /* Mailbox 30 Mailbox Receive Interrupt Flag */ -#define nMBRIF30 0x0 #define MBRIF31 0x8000 /* Mailbox 31 Mailbox Receive Interrupt Flag */ -#define nMBRIF31 0x0 /* Bit masks for EPPIx_STATUS */ #define CFIFO_ERR 0x1 /* Chroma FIFO Error */ -#define nCFIFO_ERR 0x0 #define YFIFO_ERR 0x2 /* Luma FIFO Error */ -#define nYFIFO_ERR 0x0 #define LTERR_OVR 0x4 /* Line Track Overflow */ -#define nLTERR_OVR 0x0 #define LTERR_UNDR 0x8 /* Line Track Underflow */ -#define nLTERR_UNDR 0x0 #define FTERR_OVR 0x10 /* Frame Track Overflow */ -#define nFTERR_OVR 0x0 #define FTERR_UNDR 0x20 /* Frame Track Underflow */ -#define nFTERR_UNDR 0x0 #define ERR_NCOR 0x40 /* Preamble Error Not Corrected */ -#define nERR_NCOR 0x0 #define DMA1URQ 0x80 /* DMA1 Urgent Request */ -#define nDMA1URQ 0x0 #define DMA0URQ 0x100 /* DMA0 Urgent Request */ -#define nDMA0URQ 0x0 #define ERR_DET 0x4000 /* Preamble Error Detected */ -#define nERR_DET 0x0 #define FLD 0x8000 /* Field */ -#define nFLD 0x0 /* Bit masks for EPPIx_CONTROL */ #define EPPI_EN 0x1 /* Enable */ -#define nEPPI_EN 0x0 #define EPPI_DIR 0x2 /* Direction */ -#define nEPPI_DIR 0x0 #define XFR_TYPE 0xc /* Operating Mode */ #define FS_CFG 0x30 /* Frame Sync Configuration */ #define FLD_SEL 0x40 /* Field Select/Trigger */ -#define nFLD_SEL 0x0 #define ITU_TYPE 0x80 /* ITU Interlaced or Progressive */ -#define nITU_TYPE 0x0 #define BLANKGEN 0x100 /* ITU Output Mode with Internal Blanking Generation */ -#define nBLANKGEN 0x0 #define ICLKGEN 0x200 /* Internal Clock Generation */ -#define nICLKGEN 0x0 #define IFSGEN 0x400 /* Internal Frame Sync Generation */ -#define nIFSGEN 0x0 #define POLC 0x1800 /* Frame Sync and Data Driving/Sampling Edges */ #define POLS 0x6000 /* Frame Sync Polarity */ #define DLENGTH 0x38000 /* Data Length */ #define SKIP_EN 0x40000 /* Skip Enable */ -#define nSKIP_EN 0x0 #define SKIP_EO 0x80000 /* Skip Even or Odd */ -#define nSKIP_EO 0x0 #define PACKEN 0x100000 /* Packing/Unpacking Enable */ -#define nPACKEN 0x0 #define SWAPEN 0x200000 /* Swap Enable */ -#define nSWAPEN 0x0 #define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format */ -#define nSIGN_EXT 0x0 #define SPLT_EVEN_ODD 0x800000 /* Split Even and Odd Data Samples */ -#define nSPLT_EVEN_ODD 0x0 #define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */ -#define nSUBSPLT_ODD 0x0 #define DMACFG 0x2000000 /* One or Two DMA Channels Mode */ -#define nDMACFG 0x0 #define RGB_FMT_EN 0x4000000 /* RGB Formatting Enable */ -#define nRGB_FMT_EN 0x0 #define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */ #define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */ +#define DLEN_8 (0 << 15) /* 000 - 8 bits */ +#define DLEN_10 (1 << 15) /* 001 - 10 bits */ +#define DLEN_12 (2 << 15) /* 010 - 12 bits */ +#define DLEN_14 (3 << 15) /* 011 - 14 bits */ +#define DLEN_16 (4 << 15) /* 100 - 16 bits */ +#define DLEN_18 (5 << 15) /* 101 - 18 bits */ +#define DLEN_24 (6 << 15) /* 110 - 24 bits */ + + /* Bit masks for EPPIx_FS2W_LVB */ #define F1VB_BD 0xff /* Vertical Blanking before Field 1 Active Data */ @@ -3951,60 +3085,36 @@ /* Bit masks for SPIx_CTL */ #define SPE 0x4000 /* SPI Enable */ -#define nSPE 0x0 #define WOM 0x2000 /* Write Open Drain Master */ -#define nWOM 0x0 #define MSTR 0x1000 /* Master Mode */ -#define nMSTR 0x0 #define CPOL 0x800 /* Clock Polarity */ -#define nCPOL 0x0 #define CPHA 0x400 /* Clock Phase */ -#define nCPHA 0x0 #define LSBF 0x200 /* LSB First */ -#define nLSBF 0x0 #define SIZE 0x100 /* Size of Words */ -#define nSIZE 0x0 #define EMISO 0x20 /* Enable MISO Output */ -#define nEMISO 0x0 #define PSSE 0x10 /* Slave-Select Enable */ -#define nPSSE 0x0 #define GM 0x8 /* Get More Data */ -#define nGM 0x0 #define SZ 0x4 /* Send Zero */ -#define nSZ 0x0 #define TIMOD 0x3 /* Transfer Initiation Mode */ /* Bit masks for SPIx_FLG */ #define FLS1 0x2 /* Slave Select Enable 1 */ -#define nFLS1 0x0 #define FLS2 0x4 /* Slave Select Enable 2 */ -#define nFLS2 0x0 #define FLS3 0x8 /* Slave Select Enable 3 */ -#define nFLS3 0x0 #define FLG1 0x200 /* Slave Select Value 1 */ -#define nFLG1 0x0 #define FLG2 0x400 /* Slave Select Value 2 */ -#define nFLG2 0x0 #define FLG3 0x800 /* Slave Select Value 3 */ -#define nFLG3 0x0 /* Bit masks for SPIx_STAT */ #define TXCOL 0x40 /* Transmit Collision Error */ -#define nTXCOL 0x0 #define RXS 0x20 /* RDBR Data Buffer Status */ -#define nRXS 0x0 #define RBSY 0x10 /* Receive Error */ -#define nRBSY 0x0 #define TXS 0x8 /* TDBR Data Buffer Status */ -#define nTXS 0x0 #define TXE 0x4 /* Transmission Error */ -#define nTXE 0x0 #define MODF 0x2 /* Mode Fault Error */ -#define nMODF 0x0 #define SPIF 0x1 /* SPI Finished */ -#define nSPIF 0x0 /* Bit masks for SPIx_TDBR */ @@ -4028,9 +3138,7 @@ #define PRESCALE 0x7f /* Prescale Value */ #define TWI_ENA 0x80 /* TWI Enable */ -#define nTWI_ENA 0x0 #define SCCB 0x200 /* Serial Camera Control Bus */ -#define nSCCB 0x0 /* Bit maskes for TWIx_CLKDIV */ @@ -4040,13 +3148,9 @@ /* Bit maskes for TWIx_SLAVE_CTL */ #define SEN 0x1 /* Slave Enable */ -#define nSEN 0x0 #define STDVAL 0x4 /* Slave Transmit Data Valid */ -#define nSTDVAL 0x0 #define NAK 0x8 /* Not Acknowledge */ -#define nNAK 0x0 #define GEN 0x10 /* General Call Enable */ -#define nGEN 0x0 /* Bit maskes for TWIx_SLAVE_ADDR */ @@ -4055,27 +3159,18 @@ /* Bit maskes for TWIx_SLAVE_STAT */ #define SDIR 0x1 /* Slave Transfer Direction */ -#define nSDIR 0x0 #define GCALL 0x2 /* General Call */ -#define nGCALL 0x0 /* Bit maskes for TWIx_MASTER_CTL */ #define MEN 0x1 /* Master Mode Enable */ -#define nMEN 0x0 #define MDIR 0x4 /* Master Transfer Direction */ -#define nMDIR 0x0 #define FAST 0x8 /* Fast Mode */ -#define nFAST 0x0 #define STOP 0x10 /* Issue Stop Condition */ -#define nSTOP 0x0 #define RSTART 0x20 /* Repeat Start */ -#define nRSTART 0x0 #define DCNT 0x3fc0 /* Data Transfer Count */ #define SDAOVR 0x4000 /* Serial Data Override */ -#define nSDAOVR 0x0 #define SCLOVR 0x8000 /* Serial Clock Override */ -#define nSCLOVR 0x0 /* Bit maskes for TWIx_MASTER_ADDR */ @@ -4084,34 +3179,21 @@ /* Bit maskes for TWIx_MASTER_STAT */ #define MPROG 0x1 /* Master Transfer in Progress */ -#define nMPROG 0x0 #define LOSTARB 0x2 /* Lost Arbitration */ -#define nLOSTARB 0x0 #define ANAK 0x4 /* Address Not Acknowledged */ -#define nANAK 0x0 #define DNAK 0x8 /* Data Not Acknowledged */ -#define nDNAK 0x0 #define BUFRDERR 0x10 /* Buffer Read Error */ -#define nBUFRDERR 0x0 #define BUFWRERR 0x20 /* Buffer Write Error */ -#define nBUFWRERR 0x0 #define SDASEN 0x40 /* Serial Data Sense */ -#define nSDASEN 0x0 #define SCLSEN 0x80 /* Serial Clock Sense */ -#define nSCLSEN 0x0 #define BUSBUSY 0x100 /* Bus Busy */ -#define nBUSBUSY 0x0 /* Bit maskes for TWIx_FIFO_CTL */ #define XMTFLUSH 0x1 /* Transmit Buffer Flush */ -#define nXMTFLUSH 0x0 #define RCVFLUSH 0x2 /* Receive Buffer Flush */ -#define nRCVFLUSH 0x0 #define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */ -#define nXMTINTLEN 0x0 #define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */ -#define nRCVINTLEN 0x0 /* Bit maskes for TWIx_FIFO_STAT */ @@ -4121,40 +3203,24 @@ /* Bit maskes for TWIx_INT_MASK */ #define SINITM 0x1 /* Slave Transfer Initiated Interrupt Mask */ -#define nSINITM 0x0 #define SCOMPM 0x2 /* Slave Transfer Complete Interrupt Mask */ -#define nSCOMPM 0x0 #define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */ -#define nSERRM 0x0 #define SOVFM 0x8 /* Slave Overflow Interrupt Mask */ -#define nSOVFM 0x0 #define MCOMPM 0x10 /* Master Transfer Complete Interrupt Mask */ -#define nMCOMPM 0x0 #define MERRM 0x20 /* Master Transfer Error Interrupt Mask */ -#define nMERRM 0x0 #define XMTSERVM 0x40 /* Transmit FIFO Service Interrupt Mask */ -#define nXMTSERVM 0x0 #define RCVSERVM 0x80 /* Receive FIFO Service Interrupt Mask */ -#define nRCVSERVM 0x0 /* Bit maskes for TWIx_INT_STAT */ #define SINIT 0x1 /* Slave Transfer Initiated */ -#define nSINIT 0x0 #define SCOMP 0x2 /* Slave Transfer Complete */ -#define nSCOMP 0x0 #define SERR 0x4 /* Slave Transfer Error */ -#define nSERR 0x0 #define SOVF 0x8 /* Slave Overflow */ -#define nSOVF 0x0 #define MCOMP 0x10 /* Master Transfer Complete */ -#define nMCOMP 0x0 #define MERR 0x20 /* Master Transfer Error */ -#define nMERR 0x0 #define XMTSERV 0x40 /* Transmit FIFO Service */ -#define nXMTSERV 0x0 #define RCVSERV 0x80 /* Receive FIFO Service */ -#define nRCVSERV 0x0 /* Bit maskes for TWIx_XMT_DATA8 */ @@ -4175,81 +3241,51 @@ /* Bit masks for SPORTx_TCR1 */ #define TCKFE 0x4000 /* Clock Falling Edge Select */ -#define nTCKFE 0x0 #define LATFS 0x2000 /* Late Transmit Frame Sync */ -#define nLATFS 0x0 #define LTFS 0x1000 /* Low Transmit Frame Sync Select */ -#define nLTFS 0x0 #define DITFS 0x800 /* Data-Independent Transmit Frame Sync Select */ -#define nDITFS 0x0 #define TFSR 0x400 /* Transmit Frame Sync Required Select */ -#define nTFSR 0x0 #define ITFS 0x200 /* Internal Transmit Frame Sync Select */ -#define nITFS 0x0 #define TLSBIT 0x10 /* Transmit Bit Order */ -#define nTLSBIT 0x0 #define TDTYPE 0xc /* Data Formatting Type Select */ #define ITCLK 0x2 /* Internal Transmit Clock Select */ -#define nITCLK 0x0 #define TSPEN 0x1 /* Transmit Enable */ -#define nTSPEN 0x0 /* Bit masks for SPORTx_TCR2 */ #define TRFST 0x400 /* Left/Right Order */ -#define nTRFST 0x0 #define TSFSE 0x200 /* Transmit Stereo Frame Sync Enable */ -#define nTSFSE 0x0 #define TXSE 0x100 /* TxSEC Enable */ -#define nTXSE 0x0 #define SLEN_T 0x1f /* SPORT Word Length */ /* Bit masks for SPORTx_RCR1 */ #define RCKFE 0x4000 /* Clock Falling Edge Select */ -#define nRCKFE 0x0 #define LARFS 0x2000 /* Late Receive Frame Sync */ -#define nLARFS 0x0 #define LRFS 0x1000 /* Low Receive Frame Sync Select */ -#define nLRFS 0x0 #define RFSR 0x400 /* Receive Frame Sync Required Select */ -#define nRFSR 0x0 #define IRFS 0x200 /* Internal Receive Frame Sync Select */ -#define nIRFS 0x0 #define RLSBIT 0x10 /* Receive Bit Order */ -#define nRLSBIT 0x0 #define RDTYPE 0xc /* Data Formatting Type Select */ #define IRCLK 0x2 /* Internal Receive Clock Select */ -#define nIRCLK 0x0 #define RSPEN 0x1 /* Receive Enable */ -#define nRSPEN 0x0 /* Bit masks for SPORTx_RCR2 */ #define RRFST 0x400 /* Left/Right Order */ -#define nRRFST 0x0 #define RSFSE 0x200 /* Receive Stereo Frame Sync Enable */ -#define nRSFSE 0x0 #define RXSE 0x100 /* RxSEC Enable */ -#define nRXSE 0x0 #define SLEN_R 0x1f /* SPORT Word Length */ /* Bit masks for SPORTx_STAT */ #define TXHRE 0x40 /* Transmit Hold Register Empty */ -#define nTXHRE 0x0 #define TOVF 0x20 /* Sticky Transmit Overflow Status */ -#define nTOVF 0x0 #define TUVF 0x10 /* Sticky Transmit Underflow Status */ -#define nTUVF 0x0 #define TXF 0x8 /* Transmit FIFO Full Status */ -#define nTXF 0x0 #define ROVF 0x4 /* Sticky Receive Overflow Status */ -#define nROVF 0x0 #define RUVF 0x2 /* Sticky Receive Underflow Status */ -#define nRUVF 0x0 #define RXNE 0x1 /* Receive FIFO Not Empty Status */ -#define nRXNE 0x0 /* Bit masks for SPORTx_MCMC1 */ @@ -4260,13 +3296,9 @@ #define MFD 0xf000 /* Multi channel Frame Delay */ #define FSDR 0x80 /* Frame Sync to Data Relationship */ -#define nFSDR 0x0 #define MCMEM 0x10 /* Multi channel Frame Mode Enable */ -#define nMCMEM 0x0 #define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */ -#define nMCDRXPE 0x0 #define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */ -#define nMCDTXPE 0x0 #define MCCRM 0x3 /* 2X Clock Recovery Mode */ /* Bit masks for SPORTx_CHNL */ @@ -4280,115 +3312,59 @@ #define WLS 0x3 /* Word Length Select */ #endif #define STB 0x4 /* Stop Bits */ -#define nSTB 0x0 #define PEN 0x8 /* Parity Enable */ -#define nPEN 0x0 #define EPS 0x10 /* Even Parity Select */ -#define nEPS 0x0 #define STP 0x20 /* Sticky Parity */ -#define nSTP 0x0 #define SB 0x40 /* Set Break */ -#define nSB 0x0 /* Bit masks for UARTx_MCR */ #define XOFF 0x1 /* Transmitter Off */ -#define nXOFF 0x0 #define MRTS 0x2 /* Manual Request To Send */ -#define nMRTS 0x0 #define RFIT 0x4 /* Receive FIFO IRQ Threshold */ -#define nRFIT 0x0 #define RFRT 0x8 /* Receive FIFO RTS Threshold */ -#define nRFRT 0x0 #define LOOP_ENA 0x10 /* Loopback Mode Enable */ -#define nLOOP_ENA 0x0 #define FCPOL 0x20 /* Flow Control Pin Polarity */ -#define nFCPOL 0x0 #define ARTS 0x40 /* Automatic Request To Send */ -#define nARTS 0x0 #define ACTS 0x80 /* Automatic Clear To Send */ -#define nACTS 0x0 /* Bit masks for UARTx_LSR */ #define DR 0x1 /* Data Ready */ -#define nDR 0x0 #define OE 0x2 /* Overrun Error */ -#define nOE 0x0 #define PE 0x4 /* Parity Error */ -#define nPE 0x0 #define FE 0x8 /* Framing Error */ -#define nFE 0x0 #define BI 0x10 /* Break Interrupt */ -#define nBI 0x0 #define THRE 0x20 /* THR Empty */ -#define nTHRE 0x0 #define TEMT 0x40 /* Transmitter Empty */ -#define nTEMT 0x0 #define TFI 0x80 /* Transmission Finished Indicator */ -#define nTFI 0x0 /* Bit masks for UARTx_MSR */ #define SCTS 0x1 /* Sticky CTS */ -#define nSCTS 0x0 #define CTS 0x10 /* Clear To Send */ -#define nCTS 0x0 #define RFCS 0x20 /* Receive FIFO Count Status */ -#define nRFCS 0x0 - -/* Bit masks for UARTx_IER_SET */ - -#define ERBFI_S 0x1 /* Enable Receive Buffer Full Interrupt */ -#define nERBFI_S 0x0 -#define ETBEI_S 0x2 /* Enable Transmit Buffer Empty Interrupt */ -#define nETBEI_S 0x0 -#define ELSI_S 0x4 /* Enable Receive Status Interrupt */ -#define nELSI_S 0x0 -#define EDSSI_S 0x8 /* Enable Modem Status Interrupt */ -#define nEDSSI_S 0x0 -#define EDTPTI_S 0x10 /* Enable DMA Transmit PIRQ Interrupt */ -#define nEDTPTI_S 0x0 -#define ETFI_S 0x20 /* Enable Transmission Finished Interrupt */ -#define nETFI_S 0x0 -#define ERFCI_S 0x40 /* Enable Receive FIFO Count Interrupt */ -#define nERFCI_S 0x0 - -/* Bit masks for UARTx_IER_CLEAR */ - -#define ERBFI_C 0x1 /* Enable Receive Buffer Full Interrupt */ -#define nERBFI_C 0x0 -#define ETBEI_C 0x2 /* Enable Transmit Buffer Empty Interrupt */ -#define nETBEI_C 0x0 -#define ELSI_C 0x4 /* Enable Receive Status Interrupt */ -#define nELSI_C 0x0 -#define EDSSI_C 0x8 /* Enable Modem Status Interrupt */ -#define nEDSSI_C 0x0 -#define EDTPTI_C 0x10 /* Enable DMA Transmit PIRQ Interrupt */ -#define nEDTPTI_C 0x0 -#define ETFI_C 0x20 /* Enable Transmission Finished Interrupt */ -#define nETFI_C 0x0 -#define ERFCI_C 0x40 /* Enable Receive FIFO Count Interrupt */ -#define nERFCI_C 0x0 + +/* Bit masks for UARTx_IER_SET & UARTx_IER_CLEAR */ + +#define ERBFI 0x1 /* Enable Receive Buffer Full Interrupt */ +#define ETBEI 0x2 /* Enable Transmit Buffer Empty Interrupt */ +#define ELSI 0x4 /* Enable Receive Status Interrupt */ +#define EDSSI 0x8 /* Enable Modem Status Interrupt */ +#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */ +#define ETFI 0x20 /* Enable Transmission Finished Interrupt */ +#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */ /* Bit masks for UARTx_GCTL */ #define UCEN 0x1 /* UART Enable */ -#define nUCEN 0x0 #define IREN 0x2 /* IrDA Mode Enable */ -#define nIREN 0x0 #define TPOLC 0x4 /* IrDA TX Polarity Change */ -#define nTPOLC 0x0 #define RPOLC 0x8 /* IrDA RX Polarity Change */ -#define nRPOLC 0x0 #define FPE 0x10 /* Force Parity Error */ -#define nFPE 0x0 #define FFE 0x20 /* Force Framing Error */ -#define nFFE 0x0 #define EDBO 0x40 /* Enable Divide-by-One */ -#define nEDBO 0x0 #define EGLSI 0x80 /* Enable Global LS Interrupt */ -#define nEGLSI 0x0 /* ******************************************* */ @@ -4398,32 +3374,32 @@ /* BCODE bit field options (SYSCFG register) */ #define BCODE_WAKEUP 0x0000 /* boot according to wake-up condition */ -#define BCODE_FULLBOOT 0x0010 /* always perform full boot */ +#define BCODE_FULLBOOT 0x0010 /* always perform full boot */ #define BCODE_QUICKBOOT 0x0020 /* always perform quick boot */ #define BCODE_NOBOOT 0x0030 /* always perform full boot */ /* CNT_COMMAND bit field options */ - + #define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */ #define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */ #define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */ - + #define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */ #define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */ #define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */ - + #define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */ #define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */ #define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */ - + /* CNT_CONFIG bit field options */ - + #define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */ #define CNTMODE_BINENC 0x0100 /* binary encoder mode */ #define CNTMODE_UDCNT 0x0200 /* up/down counter mode */ #define CNTMODE_DIRCNT 0x0400 /* direction counter mode */ #define CNTMODE_DIRTMR 0x0500 /* direction timer mode */ - + #define BNDMODE_COMP 0x0000 /* boundary compare mode */ #define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */ #define BNDMODE_CAPT 0x2000 /* boundary capture mode */ @@ -4436,7 +3412,7 @@ #define EXT_CLK 0x0003 /* UARTx_LCR bit field options */ - + #define WLS_5 0x0000 /* 5 data bits */ #define WLS_6 0x0001 /* 6 data bits */ #define WLS_7 0x0002 /* 7 data bits */ @@ -4484,7 +3460,7 @@ #define PIQ30 0x40000000 #define PIQ31 0x80000000 -/* PORT A Bit Definitions for the registers +/* PORT A Bit Definitions for the registers PORTA, PORTA_SET, PORTA_CLEAR, PORTA_DIR_SET, PORTA_DIR_CLEAR, PORTA_INEN, PORTA_FER registers @@ -4507,7 +3483,7 @@ PORTA_FER registers #define PA14 0x4000 #define PA15 0x8000 -/* PORT B Bit Definitions for the registers +/* PORT B Bit Definitions for the registers PORTB, PORTB_SET, PORTB_CLEAR, PORTB_DIR_SET, PORTB_DIR_CLEAR, PORTB_INEN, PORTB_FER registers @@ -4530,7 +3506,7 @@ PORTB_FER registers #define PB14 0x4000 -/* PORT C Bit Definitions for the registers +/* PORT C Bit Definitions for the registers PORTC, PORTC_SET, PORTC_CLEAR, PORTC_DIR_SET, PORTC_DIR_CLEAR, PORTC_INEN, PORTC_FER registers @@ -4553,7 +3529,7 @@ PORTC_FER registers #define PC13 0x2000 -/* PORT D Bit Definitions for the registers +/* PORT D Bit Definitions for the registers PORTD, PORTD_SET, PORTD_CLEAR, PORTD_DIR_SET, PORTD_DIR_CLEAR, PORTD_INEN, PORTD_FER registers @@ -4576,7 +3552,7 @@ PORTD_FER registers #define PD14 0x4000 #define PD15 0x8000 -/* PORT E Bit Definitions for the registers +/* PORT E Bit Definitions for the registers PORTE, PORTE_SET, PORTE_CLEAR, PORTE_DIR_SET, PORTE_DIR_CLEAR, PORTE_INEN, PORTE_FER registers @@ -4600,7 +3576,7 @@ PORTE_FER registers #define PE14 0x4000 #define PE15 0x8000 -/* PORT F Bit Definitions for the registers +/* PORT F Bit Definitions for the registers PORTF, PORTF_SET, PORTF_CLEAR, PORTF_DIR_SET, PORTF_DIR_CLEAR, PORTF_INEN, PORTF_FER registers @@ -4624,7 +3600,7 @@ PORTF_FER registers #define PF14 0x4000 #define PF15 0x8000 -/* PORT G Bit Definitions for the registers +/* PORT G Bit Definitions for the registers PORTG, PORTG_SET, PORTG_CLEAR, PORTG_DIR_SET, PORTG_DIR_CLEAR, PORTG_INEN, PORTG_FER registers @@ -4648,7 +3624,7 @@ PORTG_FER registers #define PG14 0x4000 #define PG15 0x8000 -/* PORT H Bit Definitions for the registers +/* PORT H Bit Definitions for the registers PORTH, PORTH_SET, PORTH_CLEAR, PORTH_DIR_SET, PORTH_DIR_CLEAR, PORTH_INEN, PORTH_FER registers @@ -4671,7 +3647,7 @@ PORTH_FER registers #define PH13 0x2000 -/* PORT I Bit Definitions for the registers +/* PORT I Bit Definitions for the registers PORTI, PORTI_SET, PORTI_CLEAR, PORTI_DIR_SET, PORTI_DIR_CLEAR, PORTI_INEN, PORTI_FER registers @@ -4695,7 +3671,7 @@ PORTI_FER registers #define PI14 0x4000 #define PI15 0x8000 -/* PORT J Bit Definitions for the registers +/* PORT J Bit Definitions for the registers PORTJ, PORTJ_SET, PORTJ_CLEAR, PORTJ_DIR_SET, PORTJ_DIR_CLEAR, PORTJ_INEN, PORTJ_FER registers @@ -4716,7 +3692,7 @@ PORTJ_FER registers #define PJ11 0x0800 #define PJ12 0x1000 #define PJ13 0x2000 - + /* Port Muxing Bit Fields for PORTx_MUX Registers */ @@ -4860,7 +3836,7 @@ PORTJ_FER registers #define B0MAP_PIL 0x00000006 /* Map Port I Low to Byte 0 */ #define B0MAP_PJL 0x00000007 /* Map Port J Low to Byte 0 */ -#define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */ +#define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */ #define B1MAP_PDH 0x00000100 /* Map Port D High to Byte 1 */ #define B1MAP_PEH 0x00000200 /* Map Port E High to Byte 1 */ #define B1MAP_PFH 0x00000300 /* Map Port F High to Byte 1 */ @@ -4869,27 +3845,27 @@ PORTJ_FER registers #define B1MAP_PIH 0x00000600 /* Map Port I High to Byte 1 */ #define B1MAP_PJH 0x00000700 /* Map Port J High to Byte 1 */ -#define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */ -#define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */ -#define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */ -#define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */ -#define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */ -#define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */ -#define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */ -#define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */ - -#define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */ -#define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */ -#define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */ -#define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */ -#define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */ -#define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */ -#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */ -#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */ +#define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */ +#define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */ +#define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */ +#define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */ +#define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */ +#define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */ +#define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */ +#define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */ + +#define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */ +#define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */ +#define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */ +#define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */ +#define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */ +#define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */ +#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */ +#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */ /* for legacy compatibility */ - + #define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ #define W1LMAX_MAX W1LMAX_MIN #define EBIU_AMCBCTL0 EBIU_AMBCTL0 diff --git a/include/asm-blackfin/mach-bf548/dma.h b/include/asm-blackfin/mach-bf548/dma.h new file mode 100644 index 00000000000..fcc8b4c34c6 --- /dev/null +++ b/include/asm-blackfin/mach-bf548/dma.h @@ -0,0 +1,73 @@ +/* + * file: include/asm-blackfin/mach-bf548/dma.h + * based on: + * author: + * + * created: + * description: + * system mmr register map + * rev: + * + * modified: + * + * + * bugs: enter bugs at http://blackfin.uclinux.org/ + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license as published by + * the free software foundation; either version 2, or (at your option) + * any later version. + * + * this program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * merchantability or fitness for a particular purpose. see the + * gnu general public license for more details. + * + * you should have received a copy of the gnu general public license + * along with this program; see the file copying. + * if not, write to the free software foundation, + * 59 temple place - suite 330, boston, ma 02111-1307, usa. + */ + +#ifndef _MACH_DMA_H_ +#define _MACH_DMA_H_ + +#define CH_SPORT0_RX 0 +#define CH_SPORT0_TX 1 +#define CH_SPORT1_RX 2 +#define CH_SPORT1_TX 3 +#define CH_SPI0 4 +#define CH_SPI1 5 +#define CH_UART0_RX 6 +#define CH_UART0_TX 7 +#define CH_UART1_RX 8 +#define CH_UART1_TX 9 +#define CH_ATAPI_RX 10 +#define CH_ATAPI_TX 11 +#define CH_EPPI0 12 +#define CH_EPPI1 13 +#define CH_EPPI2 14 +#define CH_PIXC_IMAGE 15 +#define CH_PIXC_OVERLAY 16 +#define CH_PIXC_OUTPUT 17 +#define CH_SPORT2_RX 18 +#define CH_SPORT2_TX 19 +#define CH_SPORT3_RX 20 +#define CH_SPORT3_TX 21 +#define CH_SDH 22 +#define CH_SPI2 23 + +#define CH_MEM_STREAM0_DEST 24 +#define CH_MEM_STREAM0_SRC 25 +#define CH_MEM_STREAM1_DEST 26 +#define CH_MEM_STREAM1_SRC 27 +#define CH_MEM_STREAM2_DEST 28 +#define CH_MEM_STREAM2_SRC 29 +#define CH_MEM_STREAM3_DEST 30 +#define CH_MEM_STREAM3_SRC 31 + +#define MAX_BLACKFIN_DMA_CHANNEL 32 + +extern int channel2irq(unsigned int channel); +extern struct dma_register *base_addr[]; +#endif diff --git a/include/asm-blackfin/mach-bf548/gpio.h b/include/asm-blackfin/mach-bf548/gpio.h new file mode 100644 index 00000000000..dbf66bcabe3 --- /dev/null +++ b/include/asm-blackfin/mach-bf548/gpio.h @@ -0,0 +1,216 @@ +/* + * File: include/asm-blackfin/mach-bf548/gpio.h + * Based on: + * Author: Michael Hennerich (hennerich@blackfin.uclinux.org) + * + * Created: + * Description: + * + * Modified: + * Copyright 2004-2007 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + + +#define GPIO_PA0 0 +#define GPIO_PA1 1 +#define GPIO_PA2 2 +#define GPIO_PA3 3 +#define GPIO_PA4 4 +#define GPIO_PA5 5 +#define GPIO_PA6 6 +#define GPIO_PA7 7 +#define GPIO_PA8 8 +#define GPIO_PA9 9 +#define GPIO_PA10 10 +#define GPIO_PA11 11 +#define GPIO_PA12 12 +#define GPIO_PA13 13 +#define GPIO_PA14 14 +#define GPIO_PA15 15 +#define GPIO_PB0 16 +#define GPIO_PB1 17 +#define GPIO_PB2 18 +#define GPIO_PB3 19 +#define GPIO_PB4 20 +#define GPIO_PB5 21 +#define GPIO_PB6 22 +#define GPIO_PB7 23 +#define GPIO_PB8 24 +#define GPIO_PB9 25 +#define GPIO_PB10 26 +#define GPIO_PB11 27 +#define GPIO_PB12 28 +#define GPIO_PB13 29 +#define GPIO_PB14 30 +#define GPIO_PB15 31 /* N/A */ +#define GPIO_PC0 32 +#define GPIO_PC1 33 +#define GPIO_PC2 34 +#define GPIO_PC3 35 +#define GPIO_PC4 36 +#define GPIO_PC5 37 +#define GPIO_PC6 38 +#define GPIO_PC7 39 +#define GPIO_PC8 40 +#define GPIO_PC9 41 +#define GPIO_PC10 42 +#define GPIO_PC11 43 +#define GPIO_PC12 44 +#define GPIO_PC13 45 +#define GPIO_PC14 46 /* N/A */ +#define GPIO_PC15 47 /* N/A */ +#define GPIO_PD0 48 +#define GPIO_PD1 49 +#define GPIO_PD2 50 +#define GPIO_PD3 51 +#define GPIO_PD4 52 +#define GPIO_PD5 53 +#define GPIO_PD6 54 +#define GPIO_PD7 55 +#define GPIO_PD8 56 +#define GPIO_PD9 57 +#define GPIO_PD10 58 +#define GPIO_PD11 59 +#define GPIO_PD12 60 +#define GPIO_PD13 61 +#define GPIO_PD14 62 +#define GPIO_PD15 63 +#define GPIO_PE0 64 +#define GPIO_PE1 65 +#define GPIO_PE2 66 +#define GPIO_PE3 67 +#define GPIO_PE4 68 +#define GPIO_PE5 69 +#define GPIO_PE6 70 +#define GPIO_PE7 71 +#define GPIO_PE8 72 +#define GPIO_PE9 73 +#define GPIO_PE10 74 +#define GPIO_PE11 75 +#define GPIO_PE12 76 +#define GPIO_PE13 77 +#define GPIO_PE14 78 +#define GPIO_PE15 79 +#define GPIO_PF0 80 +#define GPIO_PF1 81 +#define GPIO_PF2 82 +#define GPIO_PF3 83 +#define GPIO_PF4 84 +#define GPIO_PF5 85 +#define GPIO_PF6 86 +#define GPIO_PF7 87 +#define GPIO_PF8 88 +#define GPIO_PF9 89 +#define GPIO_PF10 90 +#define GPIO_PF11 91 +#define GPIO_PF12 92 +#define GPIO_PF13 93 +#define GPIO_PF14 94 +#define GPIO_PF15 95 +#define GPIO_PG0 96 +#define GPIO_PG1 97 +#define GPIO_PG2 98 +#define GPIO_PG3 99 +#define GPIO_PG4 100 +#define GPIO_PG5 101 +#define GPIO_PG6 102 +#define GPIO_PG7 103 +#define GPIO_PG8 104 +#define GPIO_PG9 105 +#define GPIO_PG10 106 +#define GPIO_PG11 107 +#define GPIO_PG12 108 +#define GPIO_PG13 109 +#define GPIO_PG14 110 +#define GPIO_PG15 111 +#define GPIO_PH0 112 +#define GPIO_PH1 113 +#define GPIO_PH2 114 +#define GPIO_PH3 115 +#define GPIO_PH4 116 +#define GPIO_PH5 117 +#define GPIO_PH6 118 +#define GPIO_PH7 119 +#define GPIO_PH8 120 +#define GPIO_PH9 121 +#define GPIO_PH10 122 +#define GPIO_PH11 123 +#define GPIO_PH12 124 +#define GPIO_PH13 125 +#define GPIO_PH14 126 /* N/A */ +#define GPIO_PH15 127 /* N/A */ +#define GPIO_PI0 128 +#define GPIO_PI1 129 +#define GPIO_PI2 130 +#define GPIO_PI3 131 +#define GPIO_PI4 132 +#define GPIO_PI5 133 +#define GPIO_PI6 134 +#define GPIO_PI7 135 +#define GPIO_PI8 136 +#define GPIO_PI9 137 +#define GPIO_PI10 138 +#define GPIO_PI11 139 +#define GPIO_PI12 140 +#define GPIO_PI13 141 +#define GPIO_PI14 142 +#define GPIO_PI15 143 +#define GPIO_PJ0 144 +#define GPIO_PJ1 145 +#define GPIO_PJ2 146 +#define GPIO_PJ3 147 +#define GPIO_PJ4 148 +#define GPIO_PJ5 149 +#define GPIO_PJ6 150 +#define GPIO_PJ7 151 +#define GPIO_PJ8 152 +#define GPIO_PJ9 153 +#define GPIO_PJ10 154 +#define GPIO_PJ11 155 +#define GPIO_PJ12 156 +#define GPIO_PJ13 157 +#define GPIO_PJ14 158 /* N/A */ +#define GPIO_PJ15 159 /* N/A */ + +#define MAX_BLACKFIN_GPIOS 160 + +struct gpio_port_t { + unsigned short port_fer; + unsigned short dummy1; + unsigned short port_data; + unsigned short dummy2; + unsigned short port_set; + unsigned short dummy3; + unsigned short port_clear; + unsigned short dummy4; + unsigned short port_dir_set; + unsigned short dummy5; + unsigned short port_dir_clear; + unsigned short dummy6; + unsigned short port_inen; + unsigned short dummy7; + unsigned int port_mux; +}; + +int gpio_request(unsigned short gpio, const char *label); +void peripheral_free(unsigned short per); +int peripheral_request_list(unsigned short per[], const char *label); +void peripheral_free_list(unsigned short per[]); diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h new file mode 100644 index 00000000000..0b3325bb1ff --- /dev/null +++ b/include/asm-blackfin/mach-bf548/irq.h @@ -0,0 +1,467 @@ +/* + * file: include/asm-blackfin/mach-bf548/irq.h + * based on: include/asm-blackfin/mach-bf537/irq.h + * author: Roy Huang (roy.huang@analog.com) + * + * created: + * description: + * system mmr register map + * rev: + * + * modified: + * + * + * bugs: enter bugs at http://blackfin.uclinux.org/ + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license as published by + * the free software foundation; either version 2, or (at your option) + * any later version. + * + * this program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * merchantability or fitness for a particular purpose. see the + * gnu general public license for more details. + * + * you should have received a copy of the gnu general public license + * along with this program; see the file copying. + * if not, write to the free software foundation, + * 59 temple place - suite 330, boston, ma 02111-1307, usa. + */ + +#ifndef _BF548_IRQ_H_ +#define _BF548_IRQ_H_ + +/* + * Interrupt source definitions + Event Source Core Event Name +Core Emulation ** +Events (highest priority) EMU 0 + Reset RST 1 + NMI NMI 2 + Exception EVX 3 + Reserved -- 4 + Hardware Error IVHW 5 + Core Timer IVTMR 6 * + +..... + + Software Interrupt 1 IVG14 31 + Software Interrupt 2 -- + (lowest priority) IVG15 32 * + */ + +#define NR_PERI_INTS (32 * 3) + +/* The ABSTRACT IRQ definitions */ +/** the first seven of the following are fixed, the rest you change if you need to **/ +#define IRQ_EMU 0 /* Emulation */ +#define IRQ_RST 1 /* reset */ +#define IRQ_NMI 2 /* Non Maskable */ +#define IRQ_EVX 3 /* Exception */ +#define IRQ_UNUSED 4 /* - unused interrupt*/ +#define IRQ_HWERR 5 /* Hardware Error */ +#define IRQ_CORETMR 6 /* Core timer */ + +#define BFIN_IRQ(x) ((x) + 7) + +#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ +#define IRQ_DMAC0_ERR BFIN_IRQ(1) /* DMAC0 Status Interrupt */ +#define IRQ_EPPI0_ERR BFIN_IRQ(2) /* EPPI0 Error Interrupt */ +#define IRQ_SPORT0_ERR BFIN_IRQ(3) /* SPORT0 Error Interrupt */ +#define IRQ_SPORT1_ERR BFIN_IRQ(4) /* SPORT1 Error Interrupt */ +#define IRQ_SPI0_ERR BFIN_IRQ(5) /* SPI0 Status(Error) Interrupt */ +#define IRQ_UART0_ERR BFIN_IRQ(6) /* UART0 Status(Error) Interrupt */ +#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */ +#define IRQ_EPPI0 BFIN_IRQ(8) /* EPPI0 Interrupt (DMA12) */ +#define IRQ_SPORT0_RX BFIN_IRQ(9) /* SPORT0 RX Interrupt (DMA0) */ +#define IRQ_SPORT0_TX BFIN_IRQ(10) /* SPORT0 TX Interrupt (DMA1) */ +#define IRQ_SPORT1_RX BFIN_IRQ(11) /* SPORT1 RX Interrupt (DMA2) */ +#define IRQ_SPORT1_TX BFIN_IRQ(12) /* SPORT1 TX Interrupt (DMA3) */ +#define IRQ_SPI0 BFIN_IRQ(13) /* SPI0 Interrupt (DMA4) */ +#define IRQ_UART0_RX BFIN_IRQ(14) /* UART0 RX Interrupt (DMA6) */ +#define IRQ_UART0_TX BFIN_IRQ(15) /* UART0 TX Interrupt (DMA7) */ +#define IRQ_TIMER8 BFIN_IRQ(16) /* TIMER 8 Interrupt */ +#define IRQ_TIMER9 BFIN_IRQ(17) /* TIMER 9 Interrupt */ +#define IRQ_TIMER10 BFIN_IRQ(18) /* TIMER 10 Interrupt */ +#define IRQ_PINT0 BFIN_IRQ(19) /* PINT0 Interrupt */ +#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */ +#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */ +#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */ +#define IRQ_WATCHDOG BFIN_IRQ(23) /* Watchdog Interrupt */ +#define IRQ_DMAC1_ERR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */ +#define IRQ_SPORT2_ERR BFIN_IRQ(25) /* SPORT2 Error Interrupt */ +#define IRQ_SPORT3_ERR BFIN_IRQ(26) /* SPORT3 Error Interrupt */ +#define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */ +#define IRQ_SPI1_ERR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */ +#define IRQ_SPI2_ERR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */ +#define IRQ_UART1_ERR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */ +#define IRQ_UART2_ERR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */ +#define IRQ_CAN0_ERR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */ +#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */ +#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ +#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ +#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ +#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ +#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ +#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ +#define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */ +#define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */ +#define IRQ_UART1_TX BFIN_IRQ(42) /* UART1 TX (DMA9) Interrupt */ +#define IRQ_ATAPI_RX BFIN_IRQ(43) /* ATAPI RX (DMA10) Interrupt */ +#define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */ +#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */ +#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */ +#define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */ +#define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */ +#define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */ +#define IRQ_MDMAS3 BFIN_IRQ(50) /* MDMA Stream 3 Interrupt */ +#define IRQ_MXVR_ERR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */ +#define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */ +#define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */ +#define IRQ_EPP1_ERR BFIN_IRQ(54) /* EPPI1 Error Interrupt */ +#define IRQ_EPP2_ERR BFIN_IRQ(55) /* EPPI2 Error Interrupt */ +#define IRQ_UART3_ERR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */ +#define IRQ_HOST_ERR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */ +#define IRQ_PIXC_ERR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */ +#define IRQ_NFC_ERR BFIN_IRQ(60) /* NFC Error Interrupt */ +#define IRQ_ATAPI_ERR BFIN_IRQ(61) /* ATAPI Error Interrupt */ +#define IRQ_CAN1_ERR BFIN_IRQ(62) /* CAN1 Status (Error) Interrupt */ +#define IRQ_HS_DMA_ERR BFIN_IRQ(63) /* Handshake DMA Status Interrupt */ +#define IRQ_PIXC_IN0 BFIN_IRQ(64) /* PIXC IN0 (DMA15) Interrupt */ +#define IRQ_PIXC_IN1 BFIN_IRQ(65) /* PIXC IN1 (DMA16) Interrupt */ +#define IRQ_PIXC_OUT BFIN_IRQ(66) /* PIXC OUT (DMA17) Interrupt */ +#define IRQ_SDH BFIN_IRQ(67) /* SDH/NFC (DMA22) Interrupt */ +#define IRQ_CNT BFIN_IRQ(68) /* CNT Interrupt */ +#define IRQ_KEY BFIN_IRQ(69) /* KEY Interrupt */ +#define IRQ_CAN1_RX BFIN_IRQ(70) /* CAN1 RX Interrupt */ +#define IRQ_CAN1_TX BFIN_IRQ(71) /* CAN1 TX Interrupt */ +#define IRQ_SDH_MASK0 BFIN_IRQ(72) /* SDH Mask 0 Interrupt */ +#define IRQ_SDH_MASK1 BFIN_IRQ(73) /* SDH Mask 1 Interrupt */ +#define IRQ_USB_INT0 BFIN_IRQ(75) /* USB INT0 Interrupt */ +#define IRQ_USB_INT1 BFIN_IRQ(76) /* USB INT1 Interrupt */ +#define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */ +#define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */ +#define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */ +#define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */ +#define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */ +#define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */ +#define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */ +#define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */ +#define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */ +#define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */ +#define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */ +#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */ +#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */ + +#define SYS_IRQS IRQ_PINT3 + +#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1) +#define IRQ_PA0 BFIN_PA_IRQ(0) +#define IRQ_PA1 BFIN_PA_IRQ(1) +#define IRQ_PA2 BFIN_PA_IRQ(2) +#define IRQ_PA3 BFIN_PA_IRQ(3) +#define IRQ_PA4 BFIN_PA_IRQ(4) +#define IRQ_PA5 BFIN_PA_IRQ(5) +#define IRQ_PA6 BFIN_PA_IRQ(6) +#define IRQ_PA7 BFIN_PA_IRQ(7) +#define IRQ_PA8 BFIN_PA_IRQ(8) +#define IRQ_PA9 BFIN_PA_IRQ(9) +#define IRQ_PA10 BFIN_PA_IRQ(10) +#define IRQ_PA11 BFIN_PA_IRQ(11) +#define IRQ_PA12 BFIN_PA_IRQ(12) +#define IRQ_PA13 BFIN_PA_IRQ(13) +#define IRQ_PA14 BFIN_PA_IRQ(14) +#define IRQ_PA15 BFIN_PA_IRQ(15) + +#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1) +#define IRQ_PB0 BFIN_PB_IRQ(0) +#define IRQ_PB1 BFIN_PB_IRQ(1) +#define IRQ_PB2 BFIN_PB_IRQ(2) +#define IRQ_PB3 BFIN_PB_IRQ(3) +#define IRQ_PB4 BFIN_PB_IRQ(4) +#define IRQ_PB5 BFIN_PB_IRQ(5) +#define IRQ_PB6 BFIN_PB_IRQ(6) +#define IRQ_PB7 BFIN_PB_IRQ(7) +#define IRQ_PB8 BFIN_PB_IRQ(8) +#define IRQ_PB9 BFIN_PB_IRQ(9) +#define IRQ_PB10 BFIN_PB_IRQ(10) +#define IRQ_PB11 BFIN_PB_IRQ(11) +#define IRQ_PB12 BFIN_PB_IRQ(12) +#define IRQ_PB13 BFIN_PB_IRQ(13) +#define IRQ_PB14 BFIN_PB_IRQ(14) +#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */ + +#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1) +#define IRQ_PC0 BFIN_PC_IRQ(0) +#define IRQ_PC1 BFIN_PC_IRQ(1) +#define IRQ_PC2 BFIN_PC_IRQ(2) +#define IRQ_PC3 BFIN_PC_IRQ(3) +#define IRQ_PC4 BFIN_PC_IRQ(4) +#define IRQ_PC5 BFIN_PC_IRQ(5) +#define IRQ_PC6 BFIN_PC_IRQ(6) +#define IRQ_PC7 BFIN_PC_IRQ(7) +#define IRQ_PC8 BFIN_PC_IRQ(8) +#define IRQ_PC9 BFIN_PC_IRQ(9) +#define IRQ_PC10 BFIN_PC_IRQ(10) +#define IRQ_PC11 BFIN_PC_IRQ(11) +#define IRQ_PC12 BFIN_PC_IRQ(12) +#define IRQ_PC13 BFIN_PC_IRQ(13) +#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */ +#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */ + +#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1) +#define IRQ_PD0 BFIN_PD_IRQ(0) +#define IRQ_PD1 BFIN_PD_IRQ(1) +#define IRQ_PD2 BFIN_PD_IRQ(2) +#define IRQ_PD3 BFIN_PD_IRQ(3) +#define IRQ_PD4 BFIN_PD_IRQ(4) +#define IRQ_PD5 BFIN_PD_IRQ(5) +#define IRQ_PD6 BFIN_PD_IRQ(6) +#define IRQ_PD7 BFIN_PD_IRQ(7) +#define IRQ_PD8 BFIN_PD_IRQ(8) +#define IRQ_PD9 BFIN_PD_IRQ(9) +#define IRQ_PD10 BFIN_PD_IRQ(10) +#define IRQ_PD11 BFIN_PD_IRQ(11) +#define IRQ_PD12 BFIN_PD_IRQ(12) +#define IRQ_PD13 BFIN_PD_IRQ(13) +#define IRQ_PD14 BFIN_PD_IRQ(14) +#define IRQ_PD15 BFIN_PD_IRQ(15) + +#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1) +#define IRQ_PE0 BFIN_PE_IRQ(0) +#define IRQ_PE1 BFIN_PE_IRQ(1) +#define IRQ_PE2 BFIN_PE_IRQ(2) +#define IRQ_PE3 BFIN_PE_IRQ(3) +#define IRQ_PE4 BFIN_PE_IRQ(4) +#define IRQ_PE5 BFIN_PE_IRQ(5) +#define IRQ_PE6 BFIN_PE_IRQ(6) +#define IRQ_PE7 BFIN_PE_IRQ(7) +#define IRQ_PE8 BFIN_PE_IRQ(8) +#define IRQ_PE9 BFIN_PE_IRQ(9) +#define IRQ_PE10 BFIN_PE_IRQ(10) +#define IRQ_PE11 BFIN_PE_IRQ(11) +#define IRQ_PE12 BFIN_PE_IRQ(12) +#define IRQ_PE13 BFIN_PE_IRQ(13) +#define IRQ_PE14 BFIN_PE_IRQ(14) +#define IRQ_PE15 BFIN_PE_IRQ(15) + +#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1) +#define IRQ_PF0 BFIN_PF_IRQ(0) +#define IRQ_PF1 BFIN_PF_IRQ(1) +#define IRQ_PF2 BFIN_PF_IRQ(2) +#define IRQ_PF3 BFIN_PF_IRQ(3) +#define IRQ_PF4 BFIN_PF_IRQ(4) +#define IRQ_PF5 BFIN_PF_IRQ(5) +#define IRQ_PF6 BFIN_PF_IRQ(6) +#define IRQ_PF7 BFIN_PF_IRQ(7) +#define IRQ_PF8 BFIN_PF_IRQ(8) +#define IRQ_PF9 BFIN_PF_IRQ(9) +#define IRQ_PF10 BFIN_PF_IRQ(10) +#define IRQ_PF11 BFIN_PF_IRQ(11) +#define IRQ_PF12 BFIN_PF_IRQ(12) +#define IRQ_PF13 BFIN_PF_IRQ(13) +#define IRQ_PF14 BFIN_PF_IRQ(14) +#define IRQ_PF15 BFIN_PF_IRQ(15) + +#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1) +#define IRQ_PG0 BFIN_PG_IRQ(0) +#define IRQ_PG1 BFIN_PG_IRQ(1) +#define IRQ_PG2 BFIN_PG_IRQ(2) +#define IRQ_PG3 BFIN_PG_IRQ(3) +#define IRQ_PG4 BFIN_PG_IRQ(4) +#define IRQ_PG5 BFIN_PG_IRQ(5) +#define IRQ_PG6 BFIN_PG_IRQ(6) +#define IRQ_PG7 BFIN_PG_IRQ(7) +#define IRQ_PG8 BFIN_PG_IRQ(8) +#define IRQ_PG9 BFIN_PG_IRQ(9) +#define IRQ_PG10 BFIN_PG_IRQ(10) +#define IRQ_PG11 BFIN_PG_IRQ(11) +#define IRQ_PG12 BFIN_PG_IRQ(12) +#define IRQ_PG13 BFIN_PG_IRQ(13) +#define IRQ_PG14 BFIN_PG_IRQ(14) +#define IRQ_PG15 BFIN_PG_IRQ(15) + +#define BFIN_PH_IRQ(x) ((x) + IRQ_PG15 + 1) +#define IRQ_PH0 BFIN_PH_IRQ(0) +#define IRQ_PH1 BFIN_PH_IRQ(1) +#define IRQ_PH2 BFIN_PH_IRQ(2) +#define IRQ_PH3 BFIN_PH_IRQ(3) +#define IRQ_PH4 BFIN_PH_IRQ(4) +#define IRQ_PH5 BFIN_PH_IRQ(5) +#define IRQ_PH6 BFIN_PH_IRQ(6) +#define IRQ_PH7 BFIN_PH_IRQ(7) +#define IRQ_PH8 BFIN_PH_IRQ(8) +#define IRQ_PH9 BFIN_PH_IRQ(9) +#define IRQ_PH10 BFIN_PH_IRQ(10) +#define IRQ_PH11 BFIN_PH_IRQ(11) +#define IRQ_PH12 BFIN_PH_IRQ(12) +#define IRQ_PH13 BFIN_PH_IRQ(13) +#define IRQ_PH14 BFIN_PH_IRQ(14) /* N/A */ +#define IRQ_PH15 BFIN_PH_IRQ(15) /* N/A */ + +#define BFIN_PI_IRQ(x) ((x) + IRQ_PH15 + 1) +#define IRQ_PI0 BFIN_PI_IRQ(0) +#define IRQ_PI1 BFIN_PI_IRQ(1) +#define IRQ_PI2 BFIN_PI_IRQ(2) +#define IRQ_PI3 BFIN_PI_IRQ(3) +#define IRQ_PI4 BFIN_PI_IRQ(4) +#define IRQ_PI5 BFIN_PI_IRQ(5) +#define IRQ_PI6 BFIN_PI_IRQ(6) +#define IRQ_PI7 BFIN_PI_IRQ(7) +#define IRQ_PI8 BFIN_PI_IRQ(8) +#define IRQ_PI9 BFIN_PI_IRQ(9) +#define IRQ_PI10 BFIN_PI_IRQ(10) +#define IRQ_PI11 BFIN_PI_IRQ(11) +#define IRQ_PI12 BFIN_PI_IRQ(12) +#define IRQ_PI13 BFIN_PI_IRQ(13) +#define IRQ_PI14 BFIN_PI_IRQ(14) +#define IRQ_PI15 BFIN_PI_IRQ(15) + +#define BFIN_PJ_IRQ(x) ((x) + IRQ_PI15 + 1) +#define IRQ_PJ0 BFIN_PJ_IRQ(0) +#define IRQ_PJ1 BFIN_PJ_IRQ(1) +#define IRQ_PJ2 BFIN_PJ_IRQ(2) +#define IRQ_PJ3 BFIN_PJ_IRQ(3) +#define IRQ_PJ4 BFIN_PJ_IRQ(4) +#define IRQ_PJ5 BFIN_PJ_IRQ(5) +#define IRQ_PJ6 BFIN_PJ_IRQ(6) +#define IRQ_PJ7 BFIN_PJ_IRQ(7) +#define IRQ_PJ8 BFIN_PJ_IRQ(8) +#define IRQ_PJ9 BFIN_PJ_IRQ(9) +#define IRQ_PJ10 BFIN_PJ_IRQ(10) +#define IRQ_PJ11 BFIN_PJ_IRQ(11) +#define IRQ_PJ12 BFIN_PJ_IRQ(12) +#define IRQ_PJ13 BFIN_PJ_IRQ(13) +#define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */ +#define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */ + +#ifdef CONFIG_IRQCHIP_DEMUX_GPIO +#define NR_IRQS (IRQ_PJ15+1) +#else +#define NR_IRQS (SYS_IRQS+1) +#endif + +#define IVG7 7 +#define IVG8 8 +#define IVG9 9 +#define IVG10 10 +#define IVG11 11 +#define IVG12 12 +#define IVG13 13 +#define IVG14 14 +#define IVG15 15 + +/* IAR0 BIT FIELDS */ +#define IRQ_PLL_WAKEUP_POS 0 +#define IRQ_DMAC0_ERR_POS 4 +#define IRQ_EPPI0_ERR_POS 8 +#define IRQ_SPORT0_ERR_POS 12 +#define IRQ_SPORT1_ERR_POS 16 +#define IRQ_SPI0_ERR_POS 20 +#define IRQ_UART0_ERR_POS 24 +#define IRQ_RTC_POS 28 + +/* IAR1 BIT FIELDS */ +#define IRQ_EPPI0_POS 0 +#define IRQ_SPORT0_RX_POS 4 +#define IRQ_SPORT0_TX_POS 8 +#define IRQ_SPORT1_RX_POS 12 +#define IRQ_SPORT1_TX_POS 16 +#define IRQ_SPI0_POS 20 +#define IRQ_UART0_RX_POS 24 +#define IRQ_UART0_TX_POS 28 + +/* IAR2 BIT FIELDS */ +#define IRQ_TIMER8_POS 0 +#define IRQ_TIMER9_POS 4 +#define IRQ_TIMER10_POS 8 +#define IRQ_PINT0_POS 12 +#define IRQ_PINT1_POS 16 +#define IRQ_MDMAS0_POS 20 +#define IRQ_MDMAS1_POS 24 +#define IRQ_WATCHDOG_POS 28 + +/* IAR3 BIT FIELDS */ +#define IRQ_DMAC1_ERR_POS 0 +#define IRQ_SPORT2_ERR_POS 4 +#define IRQ_SPORT3_ERR_POS 8 +#define IRQ_MXVR_DATA_POS 12 +#define IRQ_SPI1_ERR_POS 16 +#define IRQ_SPI2_ERR_POS 20 +#define IRQ_UART1_ERR_POS 24 +#define IRQ_UART2_ERR_POS 28 + +/* IAR4 BIT FILEDS */ +#define IRQ_CAN0_ERR_POS 0 +#define IRQ_SPORT2_RX_POS 4 +#define IRQ_SPORT2_TX_POS 8 +#define IRQ_SPORT3_RX_POS 12 +#define IRQ_SPORT3_TX_POS 16 +#define IRQ_EPPI1_POS 20 +#define IRQ_EPPI2_POS 24 +#define IRQ_SPI1_POS 28 + +/* IAR5 BIT FIELDS */ +#define IRQ_SPI2_POS 0 +#define IRQ_UART1_RX_POS 4 +#define IRQ_UART1_TX_POS 8 +#define IRQ_ATAPI_RX_POS 12 +#define IRQ_ATAPI_TX_POS 16 +#define IRQ_TWI0_POS 20 +#define IRQ_TWI1_POS 24 +#define IRQ_CAN0_RX_POS 28 + +/* IAR6 BIT FIELDS */ +#define IRQ_CAN0_TX_POS 0 +#define IRQ_MDMAS2_POS 4 +#define IRQ_MDMAS3_POS 8 +#define IRQ_MXVR_ERR_POS 12 +#define IRQ_MXVR_MSG_POS 16 +#define IRQ_MXVR_PKT_POS 20 +#define IRQ_EPPI1_ERR_POS 24 +#define IRQ_EPPI2_ERR_POS 28 + +/* IAR7 BIT FIELDS */ +#define IRQ_UART3_ERR_POS 0 +#define IRQ_HOST_ERR_POS 4 +#define IRQ_PIXC_ERR_POS 12 +#define IRQ_NFC_ERR_POS 16 +#define IRQ_ATAPI_ERR_POS 20 +#define IRQ_CAN1_ERR_POS 24 +#define IRQ_HS_DMA_ERR_POS 28 + +/* IAR8 BIT FIELDS */ +#define IRQ_PIXC_IN0_POS 0 +#define IRQ_PIXC_IN1_POS 4 +#define IRQ_PIXC_OUT_POS 8 +#define IRQ_SDH_POS 12 +#define IRQ_CNT_POS 16 +#define IRQ_KEY_POS 20 +#define IRQ_CAN1_RX_POS 24 +#define IRQ_CAN1_TX_POS 28 + +/* IAR9 BIT FIELDS */ +#define IRQ_SDH_MASK0_POS 0 +#define IRQ_SDH_MASK1_POS 4 +#define IRQ_USB_INT0_POS 12 +#define IRQ_USB_INT1_POS 16 +#define IRQ_USB_INT2_POS 20 +#define IRQ_USB_DMA_POS 24 +#define IRQ_OTPSEC_POS 28 + +/* IAR10 BIT FIELDS */ +#define IRQ_TIMER0_POS 24 +#define IRQ_TIMER1_POS 28 + +/* IAR11 BIT FIELDS */ +#define IRQ_TIMER2_POS 0 +#define IRQ_TIMER3_POS 4 +#define IRQ_TIMER4_POS 8 +#define IRQ_TIMER5_POS 12 +#define IRQ_TIMER6_POS 16 +#define IRQ_TIMER7_POS 20 +#define IRQ_PINT2_POS 24 +#define IRQ_PINT3_POS 28 + +#endif /* _BF548_IRQ_H_ */ diff --git a/include/asm-blackfin/mach-bf548/mem_init.h b/include/asm-blackfin/mach-bf548/mem_init.h new file mode 100644 index 00000000000..0cb279e973d --- /dev/null +++ b/include/asm-blackfin/mach-bf548/mem_init.h @@ -0,0 +1,189 @@ +/* + * File: include/asm-blackfin/mach-bf548/mem_init.h + * Based on: + * Author: + * + * Created: + * Description: + * + * Rev: + * + * Modified: + * Copyright 2004-2006 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. + * If not, write to the Free Software Foundation, + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#if (CONFIG_MEM_MT46V32M16) + +#if defined CONFIG_CLKIN_HALF +#define CLKIN_HALF 1 +#else +#define CLKIN_HALF 0 +#endif + +#if defined CONFIG_PLL_BYPASS +#define PLL_BYPASS 1 +#else +#define PLL_BYPASS 0 +#endif + +/***************************************Currently Not Being Used *********************************/ +#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 +#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 +#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ)) +#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 +#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 + +#if (flash_EBIU_AMBCTL_TT > 3) +#define flash_EBIU_AMBCTL0_TT B0TT_4 +#endif +#if (flash_EBIU_AMBCTL_TT == 3) +#define flash_EBIU_AMBCTL0_TT B0TT_3 +#endif +#if (flash_EBIU_AMBCTL_TT == 2) +#define flash_EBIU_AMBCTL0_TT B0TT_2 +#endif +#if (flash_EBIU_AMBCTL_TT < 2) +#define flash_EBIU_AMBCTL0_TT B0TT_1 +#endif + +#if (flash_EBIU_AMBCTL_ST > 3) +#define flash_EBIU_AMBCTL0_ST B0ST_4 +#endif +#if (flash_EBIU_AMBCTL_ST == 3) +#define flash_EBIU_AMBCTL0_ST B0ST_3 +#endif +#if (flash_EBIU_AMBCTL_ST == 2) +#define flash_EBIU_AMBCTL0_ST B0ST_2 +#endif +#if (flash_EBIU_AMBCTL_ST < 2) +#define flash_EBIU_AMBCTL0_ST B0ST_1 +#endif + +#if (flash_EBIU_AMBCTL_HT > 2) +#define flash_EBIU_AMBCTL0_HT B0HT_3 +#endif +#if (flash_EBIU_AMBCTL_HT == 2) +#define flash_EBIU_AMBCTL0_HT B0HT_2 +#endif +#if (flash_EBIU_AMBCTL_HT == 1) +#define flash_EBIU_AMBCTL0_HT B0HT_1 +#endif +#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0) +#define flash_EBIU_AMBCTL0_HT B0HT_0 +#endif +#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0) +#define flash_EBIU_AMBCTL0_HT B0HT_1 +#endif + +#if (flash_EBIU_AMBCTL_WAT > 14) +#define flash_EBIU_AMBCTL0_WAT B0WAT_15 +#endif +#if (flash_EBIU_AMBCTL_WAT == 14) +#define flash_EBIU_AMBCTL0_WAT B0WAT_14 +#endif +#if (flash_EBIU_AMBCTL_WAT == 13) +#define flash_EBIU_AMBCTL0_WAT B0WAT_13 +#endif +#if (flash_EBIU_AMBCTL_WAT == 12) +#define flash_EBIU_AMBCTL0_WAT B0WAT_12 +#endif +#if (flash_EBIU_AMBCTL_WAT == 11) +#define flash_EBIU_AMBCTL0_WAT B0WAT_11 +#endif +#if (flash_EBIU_AMBCTL_WAT == 10) +#define flash_EBIU_AMBCTL0_WAT B0WAT_10 +#endif +#if (flash_EBIU_AMBCTL_WAT == 9) +#define flash_EBIU_AMBCTL0_WAT B0WAT_9 +#endif +#if (flash_EBIU_AMBCTL_WAT == 8) +#define flash_EBIU_AMBCTL0_WAT B0WAT_8 +#endif +#if (flash_EBIU_AMBCTL_WAT == 7) +#define flash_EBIU_AMBCTL0_WAT B0WAT_7 +#endif +#if (flash_EBIU_AMBCTL_WAT == 6) +#define flash_EBIU_AMBCTL0_WAT B0WAT_6 +#endif +#if (flash_EBIU_AMBCTL_WAT == 5) +#define flash_EBIU_AMBCTL0_WAT B0WAT_5 +#endif +#if (flash_EBIU_AMBCTL_WAT == 4) +#define flash_EBIU_AMBCTL0_WAT B0WAT_4 +#endif +#if (flash_EBIU_AMBCTL_WAT == 3) +#define flash_EBIU_AMBCTL0_WAT B0WAT_3 +#endif +#if (flash_EBIU_AMBCTL_WAT == 2) +#define flash_EBIU_AMBCTL0_WAT B0WAT_2 +#endif +#if (flash_EBIU_AMBCTL_WAT == 1) +#define flash_EBIU_AMBCTL0_WAT B0WAT_1 +#endif + +#if (flash_EBIU_AMBCTL_RAT > 14) +#define flash_EBIU_AMBCTL0_RAT B0RAT_15 +#endif +#if (flash_EBIU_AMBCTL_RAT == 14) +#define flash_EBIU_AMBCTL0_RAT B0RAT_14 +#endif +#if (flash_EBIU_AMBCTL_RAT == 13) +#define flash_EBIU_AMBCTL0_RAT B0RAT_13 +#endif +#if (flash_EBIU_AMBCTL_RAT == 12) +#define flash_EBIU_AMBCTL0_RAT B0RAT_12 +#endif +#if (flash_EBIU_AMBCTL_RAT == 11) +#define flash_EBIU_AMBCTL0_RAT B0RAT_11 +#endif +#if (flash_EBIU_AMBCTL_RAT == 10) +#define flash_EBIU_AMBCTL0_RAT B0RAT_10 +#endif +#if (flash_EBIU_AMBCTL_RAT == 9) +#define flash_EBIU_AMBCTL0_RAT B0RAT_9 +#endif +#if (flash_EBIU_AMBCTL_RAT == 8) +#define flash_EBIU_AMBCTL0_RAT B0RAT_8 +#endif +#if (flash_EBIU_AMBCTL_RAT == 7) +#define flash_EBIU_AMBCTL0_RAT B0RAT_7 +#endif +#if (flash_EBIU_AMBCTL_RAT == 6) +#define flash_EBIU_AMBCTL0_RAT B0RAT_6 +#endif +#if (flash_EBIU_AMBCTL_RAT == 5) +#define flash_EBIU_AMBCTL0_RAT B0RAT_5 +#endif +#if (flash_EBIU_AMBCTL_RAT == 4) +#define flash_EBIU_AMBCTL0_RAT B0RAT_4 +#endif +#if (flash_EBIU_AMBCTL_RAT == 3) +#define flash_EBIU_AMBCTL0_RAT B0RAT_3 +#endif +#if (flash_EBIU_AMBCTL_RAT == 2) +#define flash_EBIU_AMBCTL0_RAT B0RAT_2 +#endif +#if (flash_EBIU_AMBCTL_RAT == 1) +#define flash_EBIU_AMBCTL0_RAT B0RAT_1 +#endif + +#define flash_EBIU_AMBCTL0 \ + (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \ + flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN) diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h new file mode 100644 index 00000000000..72d80e8a6e8 --- /dev/null +++ b/include/asm-blackfin/mach-bf548/mem_map.h @@ -0,0 +1,97 @@ +/* + * file: include/asm-blackfin/mach-bf548/mem_map.h + * based on: + * author: + * + * created: + * description: + * Memory MAP Common header file for blackfin BF537/6/4 of processors. + * rev: + * + * modified: + * + * bugs: enter bugs at http://blackfin.uclinux.org/ + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license as published by + * the free software foundation; either version 2, or (at your option) + * any later version. + * + * this program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * merchantability or fitness for a particular purpose. see the + * gnu general public license for more details. + * + * you should have received a copy of the gnu general public license + * along with this program; see the file copying. + * if not, write to the free software foundation, + * 59 temple place - suite 330, boston, ma 02111-1307, usa. + */ + +#ifndef _MEM_MAP_548_H_ +#define _MEM_MAP_548_H_ + +#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ +#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ + +/* Async Memory Banks */ +#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ +#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */ +#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */ +#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */ +#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */ +#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */ +#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ +#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */ + +/* Boot ROM Memory */ + +#define BOOT_ROM_START 0xEF000000 + +/* Level 1 Memory */ + +/* Memory Map for ADSP-BF548 processors */ +#ifdef CONFIG_BLKFIN_ICACHE +#define BLKFIN_ICACHESIZE (16*1024) +#else +#define BLKFIN_ICACHESIZE (0*1024) +#endif + +#define L1_CODE_START 0xFFA00000 +#define L1_DATA_A_START 0xFF800000 +#define L1_DATA_B_START 0xFF900000 + +#define L1_CODE_LENGTH 0xC000 + +#ifdef CONFIG_BLKFIN_DCACHE + +#ifdef CONFIG_BLKFIN_DCACHE_BANKA +#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) +#define L1_DATA_A_LENGTH (0x8000 - 0x4000) +#define L1_DATA_B_LENGTH 0x8000 +#define BLKFIN_DCACHESIZE (16*1024) +#define BLKFIN_DSUPBANKS 1 +#else +#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) +#define L1_DATA_A_LENGTH (0x8000 - 0x4000) +#define L1_DATA_B_LENGTH (0x8000 - 0x4000) +#define BLKFIN_DCACHESIZE (32*1024) +#define BLKFIN_DSUPBANKS 2 +#endif + +#else +#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) +#define L1_DATA_A_LENGTH 0x8000 +#define L1_DATA_B_LENGTH 0x8000 +#define BLKFIN_DCACHESIZE (0*1024) +#define BLKFIN_DSUPBANKS 0 +#endif /*CONFIG_BLKFIN_DCACHE*/ + +/* Scratch Pad Memory */ + +#if defined(CONFIG_BF54x) +#define L1_SCRATCH_START 0xFFB00000 +#define L1_SCRATCH_LENGTH 0x1000 +#endif + +#endif/* _MEM_MAP_548_H_ */ diff --git a/include/asm-blackfin/mach-bf548/portmux.h b/include/asm-blackfin/mach-bf548/portmux.h new file mode 100644 index 00000000000..b382deb501a --- /dev/null +++ b/include/asm-blackfin/mach-bf548/portmux.h @@ -0,0 +1,270 @@ +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0)) +#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0)) +#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0)) +#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0)) +#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0)) +#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0)) +#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0)) +#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0)) +#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0)) +#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0)) +#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0)) +#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0)) +#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0)) +#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0)) +#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0)) +#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0)) +#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1)) +#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1)) +#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1)) +#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1)) + +#define P_TWI1_SCL (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0)) +#define P_TWI1_SDA (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0)) +#define P_UART3_RTS (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0)) +#define P_UART3_CTS (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0)) +#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0)) +#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0)) +#define P_UART3_TX (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0)) +#define P_UART3_RX (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0)) +#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0)) +#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(0)) +#define P_SPI2_SSEL2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0)) +#define P_SPI2_SSEL3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0)) +#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(0)) +#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0)) +#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0)) +#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1)) +#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(1)) +#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(1)) +#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(1)) + +#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0)) +#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0)) +#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0)) +#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0)) +#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0)) +#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0)) +#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0)) +#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0)) +#define P_SD_D0 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(0)) +#define P_SD_D1 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0)) +#define P_SD_D2 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(0)) +#define P_SD_D3 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(0)) +#define P_SD_CLK (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0)) +#define P_SD_CMD (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0)) +#define P_MMCLK (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1)) +#define P_MBCLK (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1)) + +#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0)) +#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0)) +#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0)) +#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0)) +#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0)) +#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0)) +#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0)) +#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(0)) +#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(0)) +#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0)) +#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0)) +#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0)) +#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0)) +#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0)) +#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0)) +#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(0)) + +#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1)) +#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1)) +#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(1)) +#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(1)) +#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(1)) +#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(1)) +#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1)) +#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1)) +#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1)) +#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1)) +#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1)) +#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(1)) +#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1)) +#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(1)) +#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(1)) +#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1)) +#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2)) +#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2)) +#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(2)) +#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(2)) +#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(2)) +#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(2)) +#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(2)) +#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(2)) +#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(2)) +#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2)) +#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2)) +#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(2)) +#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2)) +#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(2)) +#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(2)) +#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2)) +#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(3)) +#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(3)) +#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(3)) +#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(3)) +#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(3)) +#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(3)) +#define P_KEY_ROW0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(3)) +#define P_KEY_ROW1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(3)) +#define P_KEY_ROW2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(3)) +#define P_KEY_ROW3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3)) +#define P_KEY_COL0 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3)) +#define P_KEY_COL1 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(3)) +#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3)) +#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3)) + +#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0)) +#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0)) +#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0)) +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(0)) +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(0)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(0)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0)) +#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0)) +#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(0)) +#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(0)) +#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0)) +#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0)) +#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0)) +#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0)) +#define P_TWI0_SCL (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0)) +#define P_TWI0_SDA (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0)) +#define P_KEY_COL7 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1)) +#define P_KEY_ROW6 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1)) +#define P_KEY_COL6 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1)) +#define P_KEY_ROW5 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1)) +#define P_KEY_COL5 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1)) +#define P_KEY_ROW4 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1)) +#define P_KEY_COL4 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1)) +#define P_KEY_ROW7 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1)) + +#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) +#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) +#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) +#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0)) +#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0)) +#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0)) +#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0)) +#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0)) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0)) +#define P_ATAPI_D0A (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1)) +#define P_ATAPI_D1A (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1)) +#define P_ATAPI_D2A (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1)) +#define P_ATAPI_D3A (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1)) +#define P_ATAPI_D4A (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1)) +#define P_ATAPI_D5A (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1)) +#define P_ATAPI_D6A (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1)) +#define P_ATAPI_D7A (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1)) +#define P_ATAPI_D8A (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1)) +#define P_ATAPI_D9A (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) +#define P_ATAPI_D10A (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1)) +#define P_ATAPI_D11A (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1)) +#define P_ATAPI_D12A (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1)) +#define P_ATAPI_D13A (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1)) +#define P_ATAPI_D14A (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) +#define P_ATAPI_D15A (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) + +#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) +#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) +#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0)) +#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0)) +#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0)) +#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) +#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0)) +#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0)) +#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0)) +#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0)) +#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0)) +#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) +#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0)) +#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0)) +#define P_CAN1_TX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0)) +#define P_CAN1_RX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) +#define P_ATAPI_A0A (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1)) +#define P_ATAPI_A1A (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1)) +#define P_ATAPI_A2A (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1)) +#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1)) +#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1)) +#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1)) +#define P_MTXONB (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1)) +#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2)) +#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2)) +#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2)) +#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(3)) + +#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0)) +#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0)) +#define P_ATAPI_RESET (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0)) +#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0)) +#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0)) +#define P_MTX (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0)) +#define P_MRX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0)) +#define P_MRXONB (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0)) +#define P_A4 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0)) +#define P_A5 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0)) +#define P_A6 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0)) +#define P_A7 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0)) +#define P_A8 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0)) +#define P_A9 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0)) +#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1)) +#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1)) +#define P_TMR8 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1)) +#define P_TMR9 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1)) +#define P_TMR10 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1)) +#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1)) +#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1)) +#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2)) +#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2)) +#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2)) + +#define P_A10 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI0) | P_FUNCT(0)) +#define P_A11 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI1) | P_FUNCT(0)) +#define P_A12 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI2) | P_FUNCT(0)) +#define P_A13 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI3) | P_FUNCT(0)) +#define P_A14 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI4) | P_FUNCT(0)) +#define P_A15 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI5) | P_FUNCT(0)) +#define P_A16 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI6) | P_FUNCT(0)) +#define P_A17 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI7) | P_FUNCT(0)) +#define P_A18 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI8) | P_FUNCT(0)) +#define P_A19 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI9) | P_FUNCT(0)) +#define P_A20 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI10) | P_FUNCT(0)) +#define P_A21 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI11) | P_FUNCT(0)) +#define P_A22 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI12) | P_FUNCT(0)) +#define P_A23 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI13) | P_FUNCT(0)) +#define P_A24 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI14) | P_FUNCT(0)) +#define P_A25 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(0)) +#define P_NOR_CLK (P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(1)) + +#define P_AMC_ARDY_NOR_WAIT (P_DEFINED | P_IDENT(GPIO_PJ0) | P_FUNCT(0)) +#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PJ1) | P_FUNCT(0)) +#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PJ2) | P_FUNCT(0)) +#define P_ATAPI_DIOR (P_DEFINED | P_IDENT(GPIO_PJ3) | P_FUNCT(0)) +#define P_ATAPI_DIOW (P_DEFINED | P_IDENT(GPIO_PJ4) | P_FUNCT(0)) +#define P_ATAPI_CS0 (P_DEFINED | P_IDENT(GPIO_PJ5) | P_FUNCT(0)) +#define P_ATAPI_CS1 (P_DEFINED | P_IDENT(GPIO_PJ6) | P_FUNCT(0)) +#define P_ATAPI_DMACK (P_DEFINED | P_IDENT(GPIO_PJ7) | P_FUNCT(0)) +#define P_ATAPI_DMARQ (P_DEFINED | P_IDENT(GPIO_PJ8) | P_FUNCT(0)) +#define P_ATAPI_INTRQ (P_DEFINED | P_IDENT(GPIO_PJ9) | P_FUNCT(0)) +#define P_ATAPI_IORDY (P_DEFINED | P_IDENT(GPIO_PJ10) | P_FUNCT(0)) +#define P_AMC_BR (P_DEFINED | P_IDENT(GPIO_PJ11) | P_FUNCT(0)) +#define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0)) +#define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0)) + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h index 23bf76aa345..e043cafa3c4 100644 --- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h @@ -78,6 +78,7 @@ struct bfin_serial_res { }; struct bfin_serial_res bfin_serial_resource[] = { + { 0xFFC00400, IRQ_UART_RX, #ifdef CONFIG_SERIAL_BFIN_DMA @@ -88,6 +89,7 @@ struct bfin_serial_res bfin_serial_resource[] = { CONFIG_UART0_CTS_PIN, CONFIG_UART0_RTS_PIN, #endif + } }; diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h index b14f872e570..1a8ec9e4692 100644 --- a/include/asm-blackfin/mach-bf561/cdefBF561.h +++ b/include/asm-blackfin/mach-bf561/cdefBF561.h @@ -57,12 +57,14 @@ /* Writing to VR_CTL initiates a PLL relock sequence. */ static __inline__ void bfin_write_VR_CTL(unsigned int val) { - unsigned long flags, iwr; + unsigned long flags, iwr0, iwr1; /* Enable the PLL Wakeup bit in SIC IWR */ - iwr = bfin_read32(SICA_IWR0); + iwr0 = bfin_read32(SICA_IWR0); + iwr1 = bfin_read32(SICA_IWR1); /* Only allow PPL Wakeup) */ bfin_write32(SICA_IWR0, IWR_ENABLE(0)); + bfin_write32(SICA_IWR1, 0); bfin_write16(VR_CTL, val); __builtin_bfin_ssync(); @@ -70,7 +72,8 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) local_irq_save(flags); asm("IDLE;"); local_irq_restore(flags); - bfin_write32(SICA_IWR0, iwr); + bfin_write32(SICA_IWR0, iwr0); + bfin_write32(SICA_IWR1, iwr1); } #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) diff --git a/include/asm-blackfin/mach-bf561/dma.h b/include/asm-blackfin/mach-bf561/dma.h index 21d982003e7..766334b7d8a 100644 --- a/include/asm-blackfin/mach-bf561/dma.h +++ b/include/asm-blackfin/mach-bf561/dma.h @@ -32,4 +32,7 @@ #define CH_IMEM_STREAM1_SRC 34 #define CH_IMEM_STREAM1_DEST 35 +extern int channel2irq(unsigned int channel); +extern struct dma_register *base_addr[]; + #endif diff --git a/include/asm-blackfin/mach-bf561/portmux.h b/include/asm-blackfin/mach-bf561/portmux.h new file mode 100644 index 00000000000..10d11d5ffe2 --- /dev/null +++ b/include/asm-blackfin/mach-bf561/portmux.h @@ -0,0 +1,87 @@ +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define P_PPI0_CLK (P_DONTCARE) +#define P_PPI0_FS1 (P_DONTCARE) +#define P_PPI0_FS2 (P_DONTCARE) +#define P_PPI0_FS3 (P_DONTCARE) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF47)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF46)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF45)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF44)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF43)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF42)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF41)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF40)) +#define P_PPI0_D0 (P_DONTCARE) +#define P_PPI0_D1 (P_DONTCARE) +#define P_PPI0_D2 (P_DONTCARE) +#define P_PPI0_D3 (P_DONTCARE) +#define P_PPI0_D4 (P_DONTCARE) +#define P_PPI0_D5 (P_DONTCARE) +#define P_PPI0_D6 (P_DONTCARE) +#define P_PPI0_D7 (P_DONTCARE) +#define P_PPI1_CLK (P_DONTCARE) +#define P_PPI1_FS1 (P_DONTCARE) +#define P_PPI1_FS2 (P_DONTCARE) +#define P_PPI1_FS3 (P_DONTCARE) +#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PF39)) +#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PF38)) +#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PF37)) +#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PF36)) +#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PF35)) +#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PF34)) +#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PF33)) +#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PF32)) +#define P_PPI1_D0 (P_DONTCARE) +#define P_PPI1_D1 (P_DONTCARE) +#define P_PPI1_D2 (P_DONTCARE) +#define P_PPI1_D3 (P_DONTCARE) +#define P_PPI1_D4 (P_DONTCARE) +#define P_PPI1_D5 (P_DONTCARE) +#define P_PPI1_D6 (P_DONTCARE) +#define P_PPI1_D7 (P_DONTCARE) +#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF31)) +#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF30)) +#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF29)) +#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF28)) +#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF27)) +#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF26)) +#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF25)) +#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF24)) +#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF23)) +#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF22)) +#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF21)) +#define P_SPORT1_DRPRI (P_DONTCARE) +#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF20)) +#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF19)) +#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF18)) +#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF17)) +#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF16)) +#define P_SPORT0_DRPRI (P_DONTCARE) +#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15)) +#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7)) +#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6)) +#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5)) +#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2)) +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1)) +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0)) +#define P_TMR11 (P_DONTCARE) +#define P_TMR10 (P_DONTCARE) +#define P_TMR9 (P_DONTCARE) +#define P_TMR8 (P_DONTCARE) +#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF7)) +#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF6)) +#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF5)) +#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF4)) +#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF3)) +#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF2)) +#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1)) +#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0)) +#define P_SPI0_MOSI (P_DONTCARE) +#define P_SPI0_MIS0 (P_DONTCARE) +#define P_SPI0_SCK (P_DONTCARE) + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h index d39c396f850..94ed381e560 100644 --- a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h +++ b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h @@ -39,7 +39,11 @@ #define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS) #define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val) #define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) +#ifdef ANOMALY_05000125 +extern void bfin_write_DMEM_CONTROL(unsigned int val); +#else #define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val) +#endif #define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) #define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val) #define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR) @@ -125,7 +129,11 @@ #define DTEST_DATA3 0xFFE0040C */ #define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) +#ifdef ANOMALY_05000125 +extern void bfin_write_IMEM_CONTROL(unsigned int val); +#else #define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val) +#endif #define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) #define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS,val) #define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR) diff --git a/include/asm-blackfin/mach-common/def_LPBlackfin.h b/include/asm-blackfin/mach-common/def_LPBlackfin.h index 76103526aec..be1ece8c0c2 100644 --- a/include/asm-blackfin/mach-common/def_LPBlackfin.h +++ b/include/asm-blackfin/mach-common/def_LPBlackfin.h @@ -42,6 +42,12 @@ #if defined(ANOMALY_05000198) +#define bfin_read8(addr) ({ unsigned char __v; \ + __asm__ __volatile__ ("NOP;\n\t" \ + "%0 = b[%1] (z);\n\t" \ + : "=d"(__v) : "a"(addr)); \ + __v; }) + #define bfin_read16(addr) ({ unsigned __v; \ __asm__ __volatile__ ("NOP;\n\t"\ "%0 = w[%1] (z);\n\t"\ @@ -52,6 +58,11 @@ "%0 = [%1];\n\t"\ : "=d"(__v) : "a"(addr)); __v; }) +#define bfin_write8(addr, val) ({ \ + __asm__ __volatile__ ("NOP;\n\t" \ + "b[%0] = %1;\n\t" \ + : : "a"(addr), "d"(val) : "memory");}) + #define bfin_write16(addr,val) ({\ __asm__ __volatile__ ("NOP;\n\t"\ "w[%0] = %1;\n\t"\ @@ -64,6 +75,12 @@ #else +#define bfin_read8(addr) ({ unsigned char __v; \ + __asm__ __volatile__ ( \ + "%0 = b[%1] (z);\n\t" \ + :"=d"(__v) : "a"(addr)); \ + __v; }) + #define bfin_read16(addr) ({ unsigned __v; \ __asm__ __volatile__ (\ "%0 = w[%1] (z);\n\t"\ @@ -74,6 +91,11 @@ "%0 = [%1];\n\t"\ : "=d"(__v) : "a"(addr)); __v; }) +#define bfin_write8(addr, val) ({ \ + __asm__ __volatile__ ( \ + "b[%0] = %1; \n\t" \ + ::"a"(addr), "d"(val) : "memory");}) + #define bfin_write16(addr,val) ({\ __asm__ __volatile__ (\ "w[%0] = %1;\n\t"\ diff --git a/include/asm-blackfin/macros.h b/include/asm-blackfin/macros.h deleted file mode 100644 index c0c04a2f2dd..00000000000 --- a/include/asm-blackfin/macros.h +++ /dev/null @@ -1,95 +0,0 @@ -/************************************************************************ - * - * macros.h - * - * (c) Copyright 2001-2003 Analog Devices, Inc. All rights reserved. - * - ************************************************************************/ - -/* Defines various assembly macros. */ - -#ifndef _MACROS_H -#define _MACROS_H - -#define LO(con32) ((con32) & 0xFFFF) -#define lo(con32) ((con32) & 0xFFFF) -#define HI(con32) (((con32) >> 16) & 0xFFFF) -#define hi(con32) (((con32) >> 16) & 0xFFFF) - -/* - * Set the corresponding bits in a System Register (SR); - * All bits set in "mask" will be set in the system register - * specified by "sys_reg" bitset_SR(sys_reg, mask), where - * sys_reg is the system register and mask are the bits to be set. - */ -#define bitset_SR(sys_reg, mask)\ - [--SP] = (R7:6);\ - r7 = sys_reg;\ - r6.l = (mask) & 0xffff;\ - r6.h = (mask) >> 16;\ - r7 = r7 | r6;\ - sys_reg = r7;\ - csync;\ - (R7:6) = [SP++] - -/* - * Clear the corresponding bits in a System Register (SR); - * All bits set in "mask" will be cleared in the SR - * specified by "sys_reg" bitclr_SR(sys_reg, mask), where - * sys_reg is the SR and mask are the bits to be cleared. - */ -#define bitclr_SR(sys_reg, mask)\ - [--SP] = (R7:6);\ - r7 = sys_reg;\ - r7 =~ r7;\ - r6.l = (mask) & 0xffff;\ - r6.h = (mask) >> 16;\ - r7 = r7 | r6;\ - r7 =~ r7;\ - sys_reg = r7;\ - csync;\ - (R7:6) = [SP++] - -/* - * Set the corresponding bits in a Memory Mapped Register (MMR); - * All bits set in "mask" will be set in the MMR specified by "mmr_reg" - * bitset_MMR(mmr_reg, mask), where mmr_reg is the MMR and mask are - * the bits to be set. - */ -#define bitset_MMR(mmr_reg, mask)\ - [--SP] = (R7:6);\ - [--SP] = P5;\ - p5.l = mmr_reg & 0xffff;\ - p5.h = mmr_reg >> 16;\ - r7 = [p5];\ - r6.l = (mask) & 0xffff;\ - r6.h = (mask) >> 16;\ - r7 = r7 | r6;\ - [p5] = r7;\ - csync;\ - p5 = [SP++];\ - (R7:6) = [SP++] - -/* - * Clear the corresponding bits in a Memory Mapped Register (MMR); - * All bits set in "mask" will be cleared in the MMR specified by "mmr_reg" - * bitclr_MMRreg(mmr_reg, mask), where sys_reg is the MMR and mask are - * the bits to be cleared. - */ -#define bitclr_MMR(mmr_reg, mask)\ - [--SP] = (R7:6);\ - [--SP] = P5;\ - p5.l = mmr_reg & 0xffff;\ - p5.h = mmr_reg >> 16;\ - r7 = [p5];\ - r7 =~ r7;\ - r6.l = (mask) & 0xffff;\ - r6.h = (mask) >> 16;\ - r7 = r7 | r6;\ - r7 =~ r7;\ - [p5] = r7;\ - csync;\ - p5 = [SP++];\ - (R7:6) = [SP++] - -#endif /* _MACROS_H */ diff --git a/include/asm-blackfin/mman.h b/include/asm-blackfin/mman.h index 4d504f908c0..b58f5ad3f02 100644 --- a/include/asm-blackfin/mman.h +++ b/include/asm-blackfin/mman.h @@ -22,8 +22,6 @@ #define MAP_NORESERVE 0x4000 /* don't check for reservations */ #define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ #define MAP_NONBLOCK 0x10000 /* do not block on IO */ -#define MAP_UNINITIALIZE 0x4000000 /* For anonymous mmap, memory could - be uninitialized. */ #define MS_ASYNC 1 /* sync memory asynchronously */ #define MS_INVALIDATE 2 /* invalidate the caches */ diff --git a/include/asm-blackfin/page.h b/include/asm-blackfin/page.h index ffad947f1b2..8bc86717021 100644 --- a/include/asm-blackfin/page.h +++ b/include/asm-blackfin/page.h @@ -4,7 +4,11 @@ /* PAGE_SHIFT determines the page size */ #define PAGE_SHIFT 12 +#ifdef __ASSEMBLY__ +#define PAGE_SIZE (1 << PAGE_SHIFT) +#else #define PAGE_SIZE (1UL << PAGE_SHIFT) +#endif #define PAGE_MASK (~(PAGE_SIZE-1)) #ifdef __KERNEL__ diff --git a/include/asm-blackfin/portmux.h b/include/asm-blackfin/portmux.h new file mode 100644 index 00000000000..9d3681e4211 --- /dev/null +++ b/include/asm-blackfin/portmux.h @@ -0,0 +1,1133 @@ +/* + * Common header file for blackfin family of processors. + * + */ + +#ifndef _PORTMUX_H_ +#define _PORTMUX_H_ + +#define P_IDENT(x) ((x) & 0x1FF) +#define P_FUNCT(x) (((x) & 0x3) << 9) +#define P_FUNCT2MUX(x) (((x) >> 9) & 0x3) +#define P_DEFINED 0x8000 +#define P_UNDEF 0x4000 +#define P_MAYSHARE 0x2000 +#define P_DONTCARE 0x1000 + +#include <asm/gpio.h> +#include <asm/mach/portmux.h> + +#ifndef P_SPORT2_TFS +#define P_SPORT2_TFS P_UNDEF +#endif + +#ifndef P_SPORT2_DTSEC +#define P_SPORT2_DTSEC P_UNDEF +#endif + +#ifndef P_SPORT2_DTPRI +#define P_SPORT2_DTPRI P_UNDEF +#endif + +#ifndef P_SPORT2_TSCLK +#define P_SPORT2_TSCLK P_UNDEF +#endif + +#ifndef P_SPORT2_RFS +#define P_SPORT2_RFS P_UNDEF +#endif + +#ifndef P_SPORT2_DRSEC +#define P_SPORT2_DRSEC P_UNDEF +#endif + +#ifndef P_SPORT2_DRPRI +#define P_SPORT2_DRPRI P_UNDEF +#endif + +#ifndef P_SPORT2_RSCLK +#define P_SPORT2_RSCLK P_UNDEF +#endif + +#ifndef P_SPORT3_TFS +#define P_SPORT3_TFS P_UNDEF +#endif + +#ifndef P_SPORT3_DTSEC +#define P_SPORT3_DTSEC P_UNDEF +#endif + +#ifndef P_SPORT3_DTPRI +#define P_SPORT3_DTPRI P_UNDEF +#endif + +#ifndef P_SPORT3_TSCLK +#define P_SPORT3_TSCLK P_UNDEF +#endif + +#ifndef P_SPORT3_RFS +#define P_SPORT3_RFS P_UNDEF +#endif + +#ifndef P_SPORT3_DRSEC +#define P_SPORT3_DRSEC P_UNDEF +#endif + +#ifndef P_SPORT3_DRPRI +#define P_SPORT3_DRPRI P_UNDEF +#endif + +#ifndef P_SPORT3_RSCLK +#define P_SPORT3_RSCLK P_UNDEF +#endif + +#ifndef P_TMR4 +#define P_TMR4 P_UNDEF +#endif + +#ifndef P_TMR5 +#define P_TMR5 P_UNDEF +#endif + +#ifndef P_TMR6 +#define P_TMR6 P_UNDEF +#endif + +#ifndef P_TMR7 +#define P_TMR7 P_UNDEF +#endif + +#ifndef P_TWI1_SCL +#define P_TWI1_SCL P_UNDEF +#endif + +#ifndef P_TWI1_SDA +#define P_TWI1_SDA P_UNDEF +#endif + +#ifndef P_UART3_RTS +#define P_UART3_RTS P_UNDEF +#endif + +#ifndef P_UART3_CTS +#define P_UART3_CTS P_UNDEF +#endif + +#ifndef P_UART2_TX +#define P_UART2_TX P_UNDEF +#endif + +#ifndef P_UART2_RX +#define P_UART2_RX P_UNDEF +#endif + +#ifndef P_UART3_TX +#define P_UART3_TX P_UNDEF +#endif + +#ifndef P_UART3_RX +#define P_UART3_RX P_UNDEF +#endif + +#ifndef P_SPI2_SS +#define P_SPI2_SS P_UNDEF +#endif + +#ifndef P_SPI2_SSEL1 +#define P_SPI2_SSEL1 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL2 +#define P_SPI2_SSEL2 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL3 +#define P_SPI2_SSEL3 P_UNDEF +#endif + +#ifndef P_SPI2_SCK +#define P_SPI2_SCK P_UNDEF +#endif + +#ifndef P_SPI2_MOSI +#define P_SPI2_MOSI P_UNDEF +#endif + +#ifndef P_SPI2_MISO +#define P_SPI2_MISO P_UNDEF +#endif + +#ifndef P_TMR0 +#define P_TMR0 P_UNDEF +#endif + +#ifndef P_TMR1 +#define P_TMR1 P_UNDEF +#endif + +#ifndef P_TMR2 +#define P_TMR2 P_UNDEF +#endif + +#ifndef P_TMR3 +#define P_TMR3 P_UNDEF +#endif + +#ifndef P_SPORT0_TFS +#define P_SPORT0_TFS P_UNDEF +#endif + +#ifndef P_SPORT0_DTSEC +#define P_SPORT0_DTSEC P_UNDEF +#endif + +#ifndef P_SPORT0_DTPRI +#define P_SPORT0_DTPRI P_UNDEF +#endif + +#ifndef P_SPORT0_TSCLK +#define P_SPORT0_TSCLK P_UNDEF +#endif + +#ifndef P_SPORT0_RFS +#define P_SPORT0_RFS P_UNDEF +#endif + +#ifndef P_SPORT0_DRSEC +#define P_SPORT0_DRSEC P_UNDEF +#endif + +#ifndef P_SPORT0_DRPRI +#define P_SPORT0_DRPRI P_UNDEF +#endif + +#ifndef P_SPORT0_RSCLK +#define P_SPORT0_RSCLK P_UNDEF +#endif + +#ifndef P_SD_D0 +#define P_SD_D0 P_UNDEF +#endif + +#ifndef P_SD_D1 +#define P_SD_D1 P_UNDEF +#endif + +#ifndef P_SD_D2 +#define P_SD_D2 P_UNDEF +#endif + +#ifndef P_SD_D3 +#define P_SD_D3 P_UNDEF +#endif + +#ifndef P_SD_CLK +#define P_SD_CLK P_UNDEF +#endif + +#ifndef P_SD_CMD +#define P_SD_CMD P_UNDEF +#endif + +#ifndef P_MMCLK +#define P_MMCLK P_UNDEF +#endif + +#ifndef P_MBCLK +#define P_MBCLK P_UNDEF +#endif + +#ifndef P_PPI1_D0 +#define P_PPI1_D0 P_UNDEF +#endif + +#ifndef P_PPI1_D1 +#define P_PPI1_D1 P_UNDEF +#endif + +#ifndef P_PPI1_D2 +#define P_PPI1_D2 P_UNDEF +#endif + +#ifndef P_PPI1_D3 +#define P_PPI1_D3 P_UNDEF +#endif + +#ifndef P_PPI1_D4 +#define P_PPI1_D4 P_UNDEF +#endif + +#ifndef P_PPI1_D5 +#define P_PPI1_D5 P_UNDEF +#endif + +#ifndef P_PPI1_D6 +#define P_PPI1_D6 P_UNDEF +#endif + +#ifndef P_PPI1_D7 +#define P_PPI1_D7 P_UNDEF +#endif + +#ifndef P_PPI1_D8 +#define P_PPI1_D8 P_UNDEF +#endif + +#ifndef P_PPI1_D9 +#define P_PPI1_D9 P_UNDEF +#endif + +#ifndef P_PPI1_D10 +#define P_PPI1_D10 P_UNDEF +#endif + +#ifndef P_PPI1_D11 +#define P_PPI1_D11 P_UNDEF +#endif + +#ifndef P_PPI1_D12 +#define P_PPI1_D12 P_UNDEF +#endif + +#ifndef P_PPI1_D13 +#define P_PPI1_D13 P_UNDEF +#endif + +#ifndef P_PPI1_D14 +#define P_PPI1_D14 P_UNDEF +#endif + +#ifndef P_PPI1_D15 +#define P_PPI1_D15 P_UNDEF +#endif + +#ifndef P_HOST_D8 +#define P_HOST_D8 P_UNDEF +#endif + +#ifndef P_HOST_D9 +#define P_HOST_D9 P_UNDEF +#endif + +#ifndef P_HOST_D10 +#define P_HOST_D10 P_UNDEF +#endif + +#ifndef P_HOST_D11 +#define P_HOST_D11 P_UNDEF +#endif + +#ifndef P_HOST_D12 +#define P_HOST_D12 P_UNDEF +#endif + +#ifndef P_HOST_D13 +#define P_HOST_D13 P_UNDEF +#endif + +#ifndef P_HOST_D14 +#define P_HOST_D14 P_UNDEF +#endif + +#ifndef P_HOST_D15 +#define P_HOST_D15 P_UNDEF +#endif + +#ifndef P_HOST_D0 +#define P_HOST_D0 P_UNDEF +#endif + +#ifndef P_HOST_D1 +#define P_HOST_D1 P_UNDEF +#endif + +#ifndef P_HOST_D2 +#define P_HOST_D2 P_UNDEF +#endif + +#ifndef P_HOST_D3 +#define P_HOST_D3 P_UNDEF +#endif + +#ifndef P_HOST_D4 +#define P_HOST_D4 P_UNDEF +#endif + +#ifndef P_HOST_D5 +#define P_HOST_D5 P_UNDEF +#endif + +#ifndef P_HOST_D6 +#define P_HOST_D6 P_UNDEF +#endif + +#ifndef P_HOST_D7 +#define P_HOST_D7 P_UNDEF +#endif + +#ifndef P_SPORT1_TFS +#define P_SPORT1_TFS P_UNDEF +#endif + +#ifndef P_SPORT1_DTSEC +#define P_SPORT1_DTSEC P_UNDEF +#endif + +#ifndef P_SPORT1_DTPRI +#define P_SPORT1_DTPRI P_UNDEF +#endif + +#ifndef P_SPORT1_TSCLK +#define P_SPORT1_TSCLK P_UNDEF +#endif + +#ifndef P_SPORT1_RFS +#define P_SPORT1_RFS P_UNDEF +#endif + +#ifndef P_SPORT1_DRSEC +#define P_SPORT1_DRSEC P_UNDEF +#endif + +#ifndef P_SPORT1_DRPRI +#define P_SPORT1_DRPRI P_UNDEF +#endif + +#ifndef P_SPORT1_RSCLK +#define P_SPORT1_RSCLK P_UNDEF +#endif + +#ifndef P_PPI2_D0 +#define P_PPI2_D0 P_UNDEF +#endif + +#ifndef P_PPI2_D1 +#define P_PPI2_D1 P_UNDEF +#endif + +#ifndef P_PPI2_D2 +#define P_PPI2_D2 P_UNDEF +#endif + +#ifndef P_PPI2_D3 +#define P_PPI2_D3 P_UNDEF +#endif + +#ifndef P_PPI2_D4 +#define P_PPI2_D4 P_UNDEF +#endif + +#ifndef P_PPI2_D5 +#define P_PPI2_D5 P_UNDEF +#endif + +#ifndef P_PPI2_D6 +#define P_PPI2_D6 P_UNDEF +#endif + +#ifndef P_PPI2_D7 +#define P_PPI2_D7 P_UNDEF +#endif + +#ifndef P_PPI0_D18 +#define P_PPI0_D18 P_UNDEF +#endif + +#ifndef P_PPI0_D19 +#define P_PPI0_D19 P_UNDEF +#endif + +#ifndef P_PPI0_D20 +#define P_PPI0_D20 P_UNDEF +#endif + +#ifndef P_PPI0_D21 +#define P_PPI0_D21 P_UNDEF +#endif + +#ifndef P_PPI0_D22 +#define P_PPI0_D22 P_UNDEF +#endif + +#ifndef P_PPI0_D23 +#define P_PPI0_D23 P_UNDEF +#endif + +#ifndef P_KEY_ROW0 +#define P_KEY_ROW0 P_UNDEF +#endif + +#ifndef P_KEY_ROW1 +#define P_KEY_ROW1 P_UNDEF +#endif + +#ifndef P_KEY_ROW2 +#define P_KEY_ROW2 P_UNDEF +#endif + +#ifndef P_KEY_ROW3 +#define P_KEY_ROW3 P_UNDEF +#endif + +#ifndef P_KEY_COL0 +#define P_KEY_COL0 P_UNDEF +#endif + +#ifndef P_KEY_COL1 +#define P_KEY_COL1 P_UNDEF +#endif + +#ifndef P_KEY_COL2 +#define P_KEY_COL2 P_UNDEF +#endif + +#ifndef P_KEY_COL3 +#define P_KEY_COL3 P_UNDEF +#endif + +#ifndef P_SPI0_SCK +#define P_SPI0_SCK P_UNDEF +#endif + +#ifndef P_SPI0_MISO +#define P_SPI0_MISO P_UNDEF +#endif + +#ifndef P_SPI0_MOSI +#define P_SPI0_MOSI P_UNDEF +#endif + +#ifndef P_SPI0_SS +#define P_SPI0_SS P_UNDEF +#endif + +#ifndef P_SPI0_SSEL1 +#define P_SPI0_SSEL1 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL2 +#define P_SPI0_SSEL2 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL3 +#define P_SPI0_SSEL3 P_UNDEF +#endif + +#ifndef P_UART0_TX +#define P_UART0_TX P_UNDEF +#endif + +#ifndef P_UART0_RX +#define P_UART0_RX P_UNDEF +#endif + +#ifndef P_UART1_RTS +#define P_UART1_RTS P_UNDEF +#endif + +#ifndef P_UART1_CTS +#define P_UART1_CTS P_UNDEF +#endif + +#ifndef P_PPI1_CLK +#define P_PPI1_CLK P_UNDEF +#endif + +#ifndef P_PPI1_FS1 +#define P_PPI1_FS1 P_UNDEF +#endif + +#ifndef P_PPI1_FS2 +#define P_PPI1_FS2 P_UNDEF +#endif + +#ifndef P_TWI0_SCL +#define P_TWI0_SCL P_UNDEF +#endif + +#ifndef P_TWI0_SDA +#define P_TWI0_SDA P_UNDEF +#endif + +#ifndef P_KEY_COL7 +#define P_KEY_COL7 P_UNDEF +#endif + +#ifndef P_KEY_ROW6 +#define P_KEY_ROW6 P_UNDEF +#endif + +#ifndef P_KEY_COL6 +#define P_KEY_COL6 P_UNDEF +#endif + +#ifndef P_KEY_ROW5 +#define P_KEY_ROW5 P_UNDEF +#endif + +#ifndef P_KEY_COL5 +#define P_KEY_COL5 P_UNDEF +#endif + +#ifndef P_KEY_ROW4 +#define P_KEY_ROW4 P_UNDEF +#endif + +#ifndef P_KEY_COL4 +#define P_KEY_COL4 P_UNDEF +#endif + +#ifndef P_KEY_ROW7 +#define P_KEY_ROW7 P_UNDEF +#endif + +#ifndef P_PPI0_D0 +#define P_PPI0_D0 P_UNDEF +#endif + +#ifndef P_PPI0_D1 +#define P_PPI0_D1 P_UNDEF +#endif + +#ifndef P_PPI0_D2 +#define P_PPI0_D2 P_UNDEF +#endif + +#ifndef P_PPI0_D3 +#define P_PPI0_D3 P_UNDEF +#endif + +#ifndef P_PPI0_D4 +#define P_PPI0_D4 P_UNDEF +#endif + +#ifndef P_PPI0_D5 +#define P_PPI0_D5 P_UNDEF +#endif + +#ifndef P_PPI0_D6 +#define P_PPI0_D6 P_UNDEF +#endif + +#ifndef P_PPI0_D7 +#define P_PPI0_D7 P_UNDEF +#endif + +#ifndef P_PPI0_D8 +#define P_PPI0_D8 P_UNDEF +#endif + +#ifndef P_PPI0_D9 +#define P_PPI0_D9 P_UNDEF +#endif + +#ifndef P_PPI0_D10 +#define P_PPI0_D10 P_UNDEF +#endif + +#ifndef P_PPI0_D11 +#define P_PPI0_D11 P_UNDEF +#endif + +#ifndef P_PPI0_D12 +#define P_PPI0_D12 P_UNDEF +#endif + +#ifndef P_PPI0_D13 +#define P_PPI0_D13 P_UNDEF +#endif + +#ifndef P_PPI0_D14 +#define P_PPI0_D14 P_UNDEF +#endif + +#ifndef P_PPI0_D15 +#define P_PPI0_D15 P_UNDEF +#endif + +#ifndef P_ATAPI_D0A +#define P_ATAPI_D0A P_UNDEF +#endif + +#ifndef P_ATAPI_D1A +#define P_ATAPI_D1A P_UNDEF +#endif + +#ifndef P_ATAPI_D2A +#define P_ATAPI_D2A P_UNDEF +#endif + +#ifndef P_ATAPI_D3A +#define P_ATAPI_D3A P_UNDEF +#endif + +#ifndef P_ATAPI_D4A +#define P_ATAPI_D4A P_UNDEF +#endif + +#ifndef P_ATAPI_D5A +#define P_ATAPI_D5A P_UNDEF +#endif + +#ifndef P_ATAPI_D6A +#define P_ATAPI_D6A P_UNDEF +#endif + +#ifndef P_ATAPI_D7A +#define P_ATAPI_D7A P_UNDEF +#endif + +#ifndef P_ATAPI_D8A +#define P_ATAPI_D8A P_UNDEF +#endif + +#ifndef P_ATAPI_D9A +#define P_ATAPI_D9A P_UNDEF +#endif + +#ifndef P_ATAPI_D10A +#define P_ATAPI_D10A P_UNDEF +#endif + +#ifndef P_ATAPI_D11A +#define P_ATAPI_D11A P_UNDEF +#endif + +#ifndef P_ATAPI_D12A +#define P_ATAPI_D12A P_UNDEF +#endif + +#ifndef P_ATAPI_D13A +#define P_ATAPI_D13A P_UNDEF +#endif + +#ifndef P_ATAPI_D14A +#define P_ATAPI_D14A P_UNDEF +#endif + +#ifndef P_ATAPI_D15A +#define P_ATAPI_D15A P_UNDEF +#endif + +#ifndef P_PPI0_CLK +#define P_PPI0_CLK P_UNDEF +#endif + +#ifndef P_PPI0_FS1 +#define P_PPI0_FS1 P_UNDEF +#endif + +#ifndef P_PPI0_FS2 +#define P_PPI0_FS2 P_UNDEF +#endif + +#ifndef P_PPI0_D16 +#define P_PPI0_D16 P_UNDEF +#endif + +#ifndef P_PPI0_D17 +#define P_PPI0_D17 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL1 +#define P_SPI1_SSEL1 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL2 +#define P_SPI1_SSEL2 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL3 +#define P_SPI1_SSEL3 P_UNDEF +#endif + +#ifndef P_SPI1_SCK +#define P_SPI1_SCK P_UNDEF +#endif + +#ifndef P_SPI1_MISO +#define P_SPI1_MISO P_UNDEF +#endif + +#ifndef P_SPI1_MOSI +#define P_SPI1_MOSI P_UNDEF +#endif + +#ifndef P_SPI1_SS +#define P_SPI1_SS P_UNDEF +#endif + +#ifndef P_CAN0_TX +#define P_CAN0_TX P_UNDEF +#endif + +#ifndef P_CAN0_RX +#define P_CAN0_RX P_UNDEF +#endif + +#ifndef P_CAN1_TX +#define P_CAN1_TX P_UNDEF +#endif + +#ifndef P_CAN1_RX +#define P_CAN1_RX P_UNDEF +#endif + +#ifndef P_ATAPI_A0A +#define P_ATAPI_A0A P_UNDEF +#endif + +#ifndef P_ATAPI_A1A +#define P_ATAPI_A1A P_UNDEF +#endif + +#ifndef P_ATAPI_A2A +#define P_ATAPI_A2A P_UNDEF +#endif + +#ifndef P_HOST_CE +#define P_HOST_CE P_UNDEF +#endif + +#ifndef P_HOST_RD +#define P_HOST_RD P_UNDEF +#endif + +#ifndef P_HOST_WR +#define P_HOST_WR P_UNDEF +#endif + +#ifndef P_MTXONB +#define P_MTXONB P_UNDEF +#endif + +#ifndef P_PPI2_FS2 +#define P_PPI2_FS2 P_UNDEF +#endif + +#ifndef P_PPI2_FS1 +#define P_PPI2_FS1 P_UNDEF +#endif + +#ifndef P_PPI2_CLK +#define P_PPI2_CLK P_UNDEF +#endif + +#ifndef P_CNT_CZM +#define P_CNT_CZM P_UNDEF +#endif + +#ifndef P_UART1_TX +#define P_UART1_TX P_UNDEF +#endif + +#ifndef P_UART1_RX +#define P_UART1_RX P_UNDEF +#endif + +#ifndef P_ATAPI_RESET +#define P_ATAPI_RESET P_UNDEF +#endif + +#ifndef P_HOST_ADDR +#define P_HOST_ADDR P_UNDEF +#endif + +#ifndef P_HOST_ACK +#define P_HOST_ACK P_UNDEF +#endif + +#ifndef P_MTX +#define P_MTX P_UNDEF +#endif + +#ifndef P_MRX +#define P_MRX P_UNDEF +#endif + +#ifndef P_MRXONB +#define P_MRXONB P_UNDEF +#endif + +#ifndef P_A4 +#define P_A4 P_UNDEF +#endif + +#ifndef P_A5 +#define P_A5 P_UNDEF +#endif + +#ifndef P_A6 +#define P_A6 P_UNDEF +#endif + +#ifndef P_A7 +#define P_A7 P_UNDEF +#endif + +#ifndef P_A8 +#define P_A8 P_UNDEF +#endif + +#ifndef P_A9 +#define P_A9 P_UNDEF +#endif + +#ifndef P_PPI1_FS3 +#define P_PPI1_FS3 P_UNDEF +#endif + +#ifndef P_PPI2_FS3 +#define P_PPI2_FS3 P_UNDEF +#endif + +#ifndef P_TMR8 +#define P_TMR8 P_UNDEF +#endif + +#ifndef P_TMR9 +#define P_TMR9 P_UNDEF +#endif + +#ifndef P_TMR10 +#define P_TMR10 P_UNDEF +#endif +#ifndef P_TMR11 +#define P_TMR11 P_UNDEF +#endif + +#ifndef P_DMAR0 +#define P_DMAR0 P_UNDEF +#endif + +#ifndef P_DMAR1 +#define P_DMAR1 P_UNDEF +#endif + +#ifndef P_PPI0_FS3 +#define P_PPI0_FS3 P_UNDEF +#endif + +#ifndef P_CNT_CDG +#define P_CNT_CDG P_UNDEF +#endif + +#ifndef P_CNT_CUD +#define P_CNT_CUD P_UNDEF +#endif + +#ifndef P_A10 +#define P_A10 P_UNDEF +#endif + +#ifndef P_A11 +#define P_A11 P_UNDEF +#endif + +#ifndef P_A12 +#define P_A12 P_UNDEF +#endif + +#ifndef P_A13 +#define P_A13 P_UNDEF +#endif + +#ifndef P_A14 +#define P_A14 P_UNDEF +#endif + +#ifndef P_A15 +#define P_A15 P_UNDEF +#endif + +#ifndef P_A16 +#define P_A16 P_UNDEF +#endif + +#ifndef P_A17 +#define P_A17 P_UNDEF +#endif + +#ifndef P_A18 +#define P_A18 P_UNDEF +#endif + +#ifndef P_A19 +#define P_A19 P_UNDEF +#endif + +#ifndef P_A20 +#define P_A20 P_UNDEF +#endif + +#ifndef P_A21 +#define P_A21 P_UNDEF +#endif + +#ifndef P_A22 +#define P_A22 P_UNDEF +#endif + +#ifndef P_A23 +#define P_A23 P_UNDEF +#endif + +#ifndef P_A24 +#define P_A24 P_UNDEF +#endif + +#ifndef P_A25 +#define P_A25 P_UNDEF +#endif + +#ifndef P_NOR_CLK +#define P_NOR_CLK P_UNDEF +#endif + +#ifndef P_TMRCLK +#define P_TMRCLK P_UNDEF +#endif + +#ifndef P_AMC_ARDY_NOR_WAIT +#define P_AMC_ARDY_NOR_WAIT P_UNDEF +#endif + +#ifndef P_NAND_CE +#define P_NAND_CE P_UNDEF +#endif + +#ifndef P_NAND_RB +#define P_NAND_RB P_UNDEF +#endif + +#ifndef P_ATAPI_DIOR +#define P_ATAPI_DIOR P_UNDEF +#endif + +#ifndef P_ATAPI_DIOW +#define P_ATAPI_DIOW P_UNDEF +#endif + +#ifndef P_ATAPI_CS0 +#define P_ATAPI_CS0 P_UNDEF +#endif + +#ifndef P_ATAPI_CS1 +#define P_ATAPI_CS1 P_UNDEF +#endif + +#ifndef P_ATAPI_DMACK +#define P_ATAPI_DMACK P_UNDEF +#endif + +#ifndef P_ATAPI_DMARQ +#define P_ATAPI_DMARQ P_UNDEF +#endif + +#ifndef P_ATAPI_INTRQ +#define P_ATAPI_INTRQ P_UNDEF +#endif + +#ifndef P_ATAPI_IORDY +#define P_ATAPI_IORDY P_UNDEF +#endif + +#ifndef P_AMC_BR +#define P_AMC_BR P_UNDEF +#endif + +#ifndef P_AMC_BG +#define P_AMC_BG P_UNDEF +#endif + +#ifndef P_AMC_BGH +#define P_AMC_BGH P_UNDEF +#endif + +/* EMAC */ + +#ifndef P_MII0_ETxD0 +#define P_MII0_ETxD0 P_UNDEF +#endif + +#ifndef P_MII0_ETxD1 +#define P_MII0_ETxD1 P_UNDEF +#endif + +#ifndef P_MII0_ETxD2 +#define P_MII0_ETxD2 P_UNDEF +#endif + +#ifndef P_MII0_ETxD3 +#define P_MII0_ETxD3 P_UNDEF +#endif + +#ifndef P_MII0_ETxEN +#define P_MII0_ETxEN P_UNDEF +#endif + +#ifndef P_MII0_TxCLK +#define P_MII0_TxCLK P_UNDEF +#endif + +#ifndef P_MII0_PHYINT +#define P_MII0_PHYINT P_UNDEF +#endif + +#ifndef P_MII0_COL +#define P_MII0_COL P_UNDEF +#endif + +#ifndef P_MII0_ERxD0 +#define P_MII0_ERxD0 P_UNDEF +#endif + +#ifndef P_MII0_ERxD1 +#define P_MII0_ERxD1 P_UNDEF +#endif + +#ifndef P_MII0_ERxD2 +#define P_MII0_ERxD2 P_UNDEF +#endif + +#ifndef P_MII0_ERxD3 +#define P_MII0_ERxD3 P_UNDEF +#endif + +#ifndef P_MII0_ERxDV +#define P_MII0_ERxDV P_UNDEF +#endif + +#ifndef P_MII0_ERxCLK +#define P_MII0_ERxCLK P_UNDEF +#endif + +#ifndef P_MII0_ERxER +#define P_MII0_ERxER P_UNDEF +#endif + +#ifndef P_MII0_CRS +#define P_MII0_CRS P_UNDEF +#endif + +#ifndef P_RMII0_REF_CLK +#define P_RMII0_REF_CLK P_UNDEF +#endif + +#ifndef P_RMII0_MDINT +#define P_RMII0_MDINT P_UNDEF +#endif + +#ifndef P_RMII0_CRS_DV +#define P_RMII0_CRS_DV P_UNDEF +#endif + +#ifndef P_MDC +#define P_MDC P_UNDEF +#endif + +#ifndef P_MDIO +#define P_MDIO P_UNDEF +#endif + +#endif /* _PORTMUX_H_ */ diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h index aba2b30a8ed..6bb3e0d4705 100644 --- a/include/asm-blackfin/processor.h +++ b/include/asm-blackfin/processor.h @@ -124,6 +124,10 @@ static inline __attribute_pure__ uint32_t bfin_compiled_revid(void) return 4; #elif defined(CONFIG_BF_REV_0_5) return 5; +#elif defined(CONFIG_BF_REV_ANY) + return 0xffff; +#else + return -1; #endif } diff --git a/include/asm-blackfin/termbits.h b/include/asm-blackfin/termbits.h index 2fd9dabdba7..4eac38de8ce 100644 --- a/include/asm-blackfin/termbits.h +++ b/include/asm-blackfin/termbits.h @@ -17,6 +17,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ diff --git a/include/asm-blackfin/trace.h b/include/asm-blackfin/trace.h new file mode 100644 index 00000000000..9c2474c9a58 --- /dev/null +++ b/include/asm-blackfin/trace.h @@ -0,0 +1,52 @@ +/* + * Common header file for blackfin family of processors. + * + */ + +#ifndef _BLACKFIN_TRACE_ +#define _BLACKFIN_TRACE_ + +#ifndef __ASSEMBLY__ +/* Trace Macros for C files */ + +#define trace_buffer_save(x) \ + do { \ + (x) = bfin_read_TBUFCTL(); \ + bfin_write_TBUFCTL((x) & ~TBUFEN); \ + } while (0) + +#define trace_buffer_restore(x) \ + do { \ + bfin_write_TBUFCTL((x)); \ + } while (0) + +#else +/* Trace Macros for Assembly files */ + +#define TRACE_BUFFER_START(preg, dreg) trace_buffer_start(preg, dreg) +#define TRACE_BUFFER_STOP(preg, dreg) trace_buffer_stop(preg, dreg) + +#define trace_buffer_stop(preg, dreg) \ + preg.L = LO(TBUFCTL); \ + preg.H = HI(TBUFCTL); \ + dreg = 0x1; \ + [preg] = dreg; + +#define trace_buffer_start(preg, dreg) \ + preg.L = LO(TBUFCTL); \ + preg.H = HI(TBUFCTL); \ + dreg = 0x13; \ + [preg] = dreg; + +#ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE +# define DEBUG_START_HWTRACE(preg, dreg) trace_buffer_start(preg, dreg) +# define DEBUG_STOP_HWTRACE(preg, dreg) trace_buffer_stop(preg, dreg) + +#else +# define DEBUG_START_HWTRACE(preg, dreg) +# define DEBUG_STOP_HWTRACE(preg, dreg) +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* _BLACKFIN_TRACE_ */ diff --git a/include/asm-blackfin/unistd.h b/include/asm-blackfin/unistd.h index 4df8790a67d..0df9f2d322a 100644 --- a/include/asm-blackfin/unistd.h +++ b/include/asm-blackfin/unistd.h @@ -369,7 +369,6 @@ #define __ARCH_WANT_SYS_NICE #define __ARCH_WANT_SYS_RT_SIGACTION #define __ARCH_WANT_SYS_RT_SIGSUSPEND -#endif /* * "Conditional" syscalls @@ -379,4 +378,6 @@ */ #define cond_syscall(x) asm(".weak\t_" #x "\n\t.set\t_" #x ",_sys_ni_syscall"); +#endif /* __KERNEL__ */ + #endif /* __ASM_BFIN_UNISTD_H */ diff --git a/include/asm-cris/pci.h b/include/asm-cris/pci.h index b2ac8a331da..730ce40fdd0 100644 --- a/include/asm-cris/pci.h +++ b/include/asm-cris/pci.h @@ -52,47 +52,11 @@ struct pci_dev; #define pci_unmap_len(PTR, LEN_NAME) (0) #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) -/* This is always fine. */ -#define pci_dac_dma_supported(pci_dev, mask) (1) - -static inline dma64_addr_t -pci_dac_page_to_dma(struct pci_dev *pdev, struct page *page, unsigned long offset, int direction) -{ - return ((dma64_addr_t) page_to_phys(page) + - (dma64_addr_t) offset); -} - -static inline struct page * -pci_dac_dma_to_page(struct pci_dev *pdev, dma64_addr_t dma_addr) -{ - return pfn_to_page(dma_addr >> PAGE_SHIFT); -} - -static inline unsigned long -pci_dac_dma_to_offset(struct pci_dev *pdev, dma64_addr_t dma_addr) -{ - return (dma_addr & ~PAGE_MASK); -} - -static inline void -pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction) -{ -} - -static inline void -pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction) -{ -} - #define HAVE_PCI_MMAP extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, enum pci_mmap_state mmap_state, int write_combine); -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - #endif /* __KERNEL__ */ /* implement the pci_ DMA API in terms of the generic device dma_ one */ diff --git a/include/asm-cris/termbits.h b/include/asm-cris/termbits.h index 8d8cec225fe..6cc2e2736f7 100644 --- a/include/asm-cris/termbits.h +++ b/include/asm-cris/termbits.h @@ -19,6 +19,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ diff --git a/include/asm-frv/pci.h b/include/asm-frv/pci.h index f35a4511e7b..585d9b49949 100644 --- a/include/asm-frv/pci.h +++ b/include/asm-frv/pci.h @@ -22,10 +22,6 @@ struct pci_dev; #define pcibios_assign_all_busses() 0 -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - extern void pcibios_set_master(struct pci_dev *dev); extern void pcibios_penalize_isa_irq(int irq); @@ -44,9 +40,6 @@ extern void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, extern void pci_free_consistent(struct pci_dev *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle); -/* This is always fine. */ -#define pci_dac_dma_supported(pci_dev, mask) (1) - /* Return the index of the PCI controller for device PDEV. */ #define pci_controller_num(PDEV) (0) diff --git a/include/asm-frv/pgtable.h b/include/asm-frv/pgtable.h index 2687c771512..114aefae270 100644 --- a/include/asm-frv/pgtable.h +++ b/include/asm-frv/pgtable.h @@ -25,7 +25,7 @@ #include <linux/slab.h> #include <linux/list.h> #include <linux/spinlock.h> -struct mm_struct; +#include <linux/sched.h> struct vm_area_struct; #endif diff --git a/include/asm-frv/system.h b/include/asm-frv/system.h index be303b3eef4..6931af525da 100644 --- a/include/asm-frv/system.h +++ b/include/asm-frv/system.h @@ -12,6 +12,7 @@ #ifndef _ASM_SYSTEM_H #define _ASM_SYSTEM_H +#include <linux/types.h> #include <linux/linkage.h> struct thread_struct; diff --git a/include/asm-frv/termbits.h b/include/asm-frv/termbits.h index 2d6d389cff4..74851b424d4 100644 --- a/include/asm-frv/termbits.h +++ b/include/asm-frv/termbits.h @@ -17,6 +17,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ diff --git a/include/asm-frv/uaccess.h b/include/asm-frv/uaccess.h index 3d90e1018ee..53650c958f4 100644 --- a/include/asm-frv/uaccess.h +++ b/include/asm-frv/uaccess.h @@ -277,6 +277,8 @@ extern long __memcpy_user(void *dst, const void *src, unsigned long count); #endif +#define __clear_user clear_user + static inline unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n) { diff --git a/include/asm-generic/bitops/sched.h b/include/asm-generic/bitops/sched.h index 815bb014806..604fab7031a 100644 --- a/include/asm-generic/bitops/sched.h +++ b/include/asm-generic/bitops/sched.h @@ -6,28 +6,23 @@ /* * Every architecture must define this function. It's the fastest - * way of searching a 140-bit bitmap where the first 100 bits are - * unlikely to be set. It's guaranteed that at least one of the 140 - * bits is cleared. + * way of searching a 100-bit bitmap. It's guaranteed that at least + * one of the 100 bits is cleared. */ static inline int sched_find_first_bit(const unsigned long *b) { #if BITS_PER_LONG == 64 - if (unlikely(b[0])) + if (b[0]) return __ffs(b[0]); - if (likely(b[1])) - return __ffs(b[1]) + 64; - return __ffs(b[2]) + 128; + return __ffs(b[1]) + 64; #elif BITS_PER_LONG == 32 - if (unlikely(b[0])) + if (b[0]) return __ffs(b[0]); - if (unlikely(b[1])) + if (b[1]) return __ffs(b[1]) + 32; - if (unlikely(b[2])) + if (b[2]) return __ffs(b[2]) + 64; - if (b[3]) - return __ffs(b[3]) + 96; - return __ffs(b[4]) + 128; + return __ffs(b[3]) + 96; #else #error BITS_PER_LONG not defined #endif diff --git a/include/asm-generic/pgtable.h b/include/asm-generic/pgtable.h index dc8f99ee305..7d7bcf990e9 100644 --- a/include/asm-generic/pgtable.h +++ b/include/asm-generic/pgtable.h @@ -27,13 +27,20 @@ do { \ * Largely same as above, but only sets the access flags (dirty, * accessed, and writable). Furthermore, we know it always gets set * to a "more permissive" setting, which allows most architectures - * to optimize this. + * to optimize this. We return whether the PTE actually changed, which + * in turn instructs the caller to do things like update__mmu_cache. + * This used to be done in the caller, but sparc needs minor faults to + * force that call on sun4c so we changed this macro slightly */ #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \ -do { \ - set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \ - flush_tlb_page(__vma, __address); \ -} while (0) +({ \ + int __changed = !pte_same(*(__ptep), __entry); \ + if (__changed) { \ + set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \ + flush_tlb_page(__vma, __address); \ + } \ + __changed; \ +}) #endif #ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h index 8307b1bb337..84155eb67f1 100644 --- a/include/asm-generic/vmlinux.lds.h +++ b/include/asm-generic/vmlinux.lds.h @@ -14,8 +14,8 @@ *(.data) \ *(.data.init.refok) -#define RODATA \ - . = ALIGN(4096); \ +#define RO_DATA(align) \ + . = ALIGN((align)); \ .rodata : AT(ADDR(.rodata) - LOAD_OFFSET) { \ VMLINUX_SYMBOL(__start_rodata) = .; \ *(.rodata) *(.rodata.*) \ @@ -135,7 +135,11 @@ VMLINUX_SYMBOL(__end_rodata) = .; \ } \ \ - . = ALIGN(4096); + . = ALIGN((align)); + +/* RODATA provided for backward compatibility. + * All archs are supposed to use RO_DATA() */ +#define RODATA RO_DATA(4096) #define SECURITY_INIT \ .security_initcall.init : AT(ADDR(.security_initcall.init) - LOAD_OFFSET) { \ diff --git a/include/asm-h8300/pci.h b/include/asm-h8300/pci.h index 0c771b05fdd..97389b35aa3 100644 --- a/include/asm-h8300/pci.h +++ b/include/asm-h8300/pci.h @@ -22,8 +22,4 @@ static inline void pcibios_penalize_isa_irq(int irq, int active) #define PCI_DMA_BUS_IS_PHYS (1) -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - #endif /* _ASM_H8300_PCI_H */ diff --git a/include/asm-h8300/processor.h b/include/asm-h8300/processor.h index 99b664aa208..49fc886a623 100644 --- a/include/asm-h8300/processor.h +++ b/include/asm-h8300/processor.h @@ -78,7 +78,7 @@ struct thread_struct { do { \ set_fs(USER_DS); /* reads from user space */ \ (_regs)->pc = (_pc); \ - (_regs)->ccr &= 0x00; /* clear kernel flag */ \ + (_regs)->ccr = 0x00; /* clear all flags */ \ (_regs)->er5 = current->mm->start_data; /* GOT base */ \ wrusp((unsigned long)(_usp) - sizeof(unsigned long)*3); \ } while(0) diff --git a/include/asm-h8300/termbits.h b/include/asm-h8300/termbits.h index 6a1f4d3807b..e877b40ac5b 100644 --- a/include/asm-h8300/termbits.h +++ b/include/asm-h8300/termbits.h @@ -17,6 +17,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ diff --git a/include/asm-i386/boot.h b/include/asm-i386/boot.h index bd024ab4fe5..ed8affbf96c 100644 --- a/include/asm-i386/boot.h +++ b/include/asm-i386/boot.h @@ -1,5 +1,5 @@ -#ifndef _LINUX_BOOT_H -#define _LINUX_BOOT_H +#ifndef _ASM_BOOT_H +#define _ASM_BOOT_H /* Don't touch these, unless you really know what you're doing. */ #define DEF_INITSEG 0x9000 @@ -17,4 +17,4 @@ + (CONFIG_PHYSICAL_ALIGN - 1)) \ & ~(CONFIG_PHYSICAL_ALIGN - 1)) -#endif /* _LINUX_BOOT_H */ +#endif /* _ASM_BOOT_H */ diff --git a/include/asm-i386/bootparam.h b/include/asm-i386/bootparam.h new file mode 100644 index 00000000000..427d8652bfd --- /dev/null +++ b/include/asm-i386/bootparam.h @@ -0,0 +1,85 @@ +#ifndef _ASM_BOOTPARAM_H +#define _ASM_BOOTPARAM_H + +#include <linux/types.h> +#include <linux/screen_info.h> +#include <linux/apm_bios.h> +#include <asm/e820.h> +#include <linux/edd.h> +#include <video/edid.h> + +struct setup_header { + u8 setup_sects; + u16 root_flags; + u32 syssize; + u16 ram_size; + u16 vid_mode; + u16 root_dev; + u16 boot_flag; + u16 jump; + u32 header; + u16 version; + u32 realmode_swtch; + u16 start_sys; + u16 kernel_version; + u8 type_of_loader; + u8 loadflags; +#define LOADED_HIGH 0x01 +#define CAN_USE_HEAP 0x80 + u16 setup_move_size; + u32 code32_start; + u32 ramdisk_image; + u32 ramdisk_size; + u32 bootsect_kludge; + u16 heap_end_ptr; + u16 _pad1; + u32 cmd_line_ptr; + u32 initrd_addr_max; + u32 kernel_alignment; + u8 relocatable_kernel; +} __attribute__((packed)); + +struct sys_desc_table { + u16 length; + u8 table[14]; +}; + +struct efi_info { + u32 _pad1; + u32 efi_systab; + u32 efi_memdesc_size; + u32 efi_memdec_version; + u32 efi_memmap; + u32 fi_memmap_size; + u32 _pad2[2]; +}; + +/* The so-called "zeropage" */ +struct boot_params { + struct screen_info screen_info; /* 0x000 */ + struct apm_bios_info apm_bios_info; /* 0x040 */ + u8 _pad2[12]; /* 0x054 */ + u32 speedstep_info[4]; /* 0x060 */ + u8 _pad3[16]; /* 0x070 */ + u8 hd0_info[16]; /* obsolete! */ /* 0x080 */ + u8 hd1_info[16]; /* obsolete! */ /* 0x090 */ + struct sys_desc_table sys_desc_table; /* 0x0a0 */ + u8 _pad4[144]; /* 0x0b0 */ + struct edid_info edid_info; /* 0x140 */ + struct efi_info efi_info; /* 0x1c0 */ + u32 alt_mem_k; /* 0x1e0 */ + u32 scratch; /* Scratch field! */ /* 0x1e4 */ + u8 e820_entries; /* 0x1e8 */ + u8 eddbuf_entries; /* 0x1e9 */ + u8 edd_mbr_sig_buf_entries; /* 0x1ea */ + u8 _pad6[6]; /* 0x1eb */ + struct setup_header hdr; /* setup header */ /* 0x1f1 */ + u8 _pad7[0x290-0x1f1-sizeof(struct setup_header)]; + u32 edd_mbr_sig_buffer[EDD_MBR_SIG_MAX]; /* 0x290 */ + struct e820entry e820_map[E820MAX]; /* 0x2d0 */ + u8 _pad8[48]; /* 0xcd0 */ + struct edd_info eddbuf[EDDMAXNR]; /* 0xd00 */ + u8 _pad9[276]; /* 0xeec */ +} __attribute__((packed)); + +#endif /* _ASM_BOOTPARAM_H */ diff --git a/include/asm-i386/cpufeature.h b/include/asm-i386/cpufeature.h index f514e906643..c961c03cf1e 100644 --- a/include/asm-i386/cpufeature.h +++ b/include/asm-i386/cpufeature.h @@ -12,7 +12,7 @@ #endif #include <asm/required-features.h> -#define NCAPINTS 7 /* N 32-bit words worth of info */ +#define NCAPINTS 8 /* N 32-bit words worth of info */ /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ #define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */ @@ -81,6 +81,7 @@ #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ #define X86_FEATURE_LAPIC_TIMER_BROKEN (3*32+ 14) /* lapic timer broken in C1 */ #define X86_FEATURE_SYNC_RDTSC (3*32+15) /* RDTSC synchronizes the CPU */ +#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */ /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ @@ -108,11 +109,24 @@ #define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ #define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ -#define cpu_has(c, bit) \ - ((__builtin_constant_p(bit) && (bit) < 32 && \ - (1UL << (bit)) & REQUIRED_MASK1) ? \ - 1 : \ - test_bit(bit, (c)->x86_capability)) +/* + * Auxiliary flags: Linux defined - For features scattered in various + * CPUID levels like 0x6, 0xA etc + */ +#define X86_FEATURE_IDA (7*32+ 0) /* Intel Dynamic Acceleration */ + +#define cpu_has(c, bit) \ + (__builtin_constant_p(bit) && \ + ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \ + (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) || \ + (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) || \ + (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) || \ + (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || \ + (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || \ + (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || \ + (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) ) \ + ? 1 : \ + test_bit(bit, (c)->x86_capability)) #define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit) #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) diff --git a/include/asm-i386/dma-mapping.h b/include/asm-i386/dma-mapping.h index 183eebeebbd..f1d72d177f6 100644 --- a/include/asm-i386/dma-mapping.h +++ b/include/asm-i386/dma-mapping.h @@ -123,6 +123,8 @@ dma_mapping_error(dma_addr_t dma_addr) return 0; } +extern int forbid_dac; + static inline int dma_supported(struct device *dev, u64 mask) { @@ -134,6 +136,10 @@ dma_supported(struct device *dev, u64 mask) if(mask < 0x00ffffff) return 0; + /* Work around chipset bugs */ + if (forbid_dac > 0 && mask > 0xffffffffULL) + return 0; + return 1; } diff --git a/include/asm-i386/e820.h b/include/asm-i386/e820.h index 096a2a8eb1d..c03290ccecb 100644 --- a/include/asm-i386/e820.h +++ b/include/asm-i386/e820.h @@ -25,13 +25,15 @@ #ifndef __ASSEMBLY__ +struct e820entry { + u64 addr; /* start of memory segment */ + u64 size; /* size of memory segment */ + u32 type; /* type of memory segment */ +} __attribute__((packed)); + struct e820map { - int nr_map; - struct e820entry { - unsigned long long addr; /* start of memory segment */ - unsigned long long size; /* size of memory segment */ - unsigned long type; /* type of memory segment */ - } map[E820MAX]; + u32 nr_map; + struct e820entry map[E820MAX]; }; extern struct e820map e820; diff --git a/include/asm-i386/mach-es7000/mach_apic.h b/include/asm-i386/mach-es7000/mach_apic.h index 2d978928a39..caec64be516 100644 --- a/include/asm-i386/mach-es7000/mach_apic.h +++ b/include/asm-i386/mach-es7000/mach_apic.h @@ -73,6 +73,10 @@ static inline void init_apic_ldr(void) apic_write_around(APIC_LDR, val); } +#ifndef CONFIG_X86_GENERICARCH +extern void enable_apic_mode(void); +#endif + extern int apic_version [MAX_APICS]; static inline void setup_apic_routing(void) { diff --git a/include/asm-i386/mach-es7000/mach_mpparse.h b/include/asm-i386/mach-es7000/mach_mpparse.h index b9fb784e1fd..8aa10547b4b 100644 --- a/include/asm-i386/mach-es7000/mach_mpparse.h +++ b/include/asm-i386/mach-es7000/mach_mpparse.h @@ -18,6 +18,12 @@ extern int parse_unisys_oem (char *oemptr); extern int find_unisys_acpi_oem_table(unsigned long *oem_addr); extern void setup_unisys(void); +#ifndef CONFIG_X86_GENERICARCH +extern int acpi_madt_oem_check(char *oem_id, char *oem_table_id); +extern int mps_oem_check(struct mp_config_table *mpc, char *oem, + char *productid); +#endif + #ifdef CONFIG_ACPI static inline int es7000_check_dsdt(void) diff --git a/include/asm-i386/paravirt.h b/include/asm-i386/paravirt.h index d7a0512f88e..7f846a7d6bc 100644 --- a/include/asm-i386/paravirt.h +++ b/include/asm-i386/paravirt.h @@ -539,7 +539,7 @@ static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high) val = paravirt_read_msr(msr, &_err); \ } while(0) -#define wrmsrl(msr,val) ((void)paravirt_write_msr(msr, val, 0)) +#define wrmsrl(msr,val) wrmsr(msr, (u32)((u64)(val)), ((u64)(val))>>32) #define wrmsr_safe(msr,a,b) paravirt_write_msr(msr, a, b) /* rdmsr with exception handling */ diff --git a/include/asm-i386/pci.h b/include/asm-i386/pci.h index 64b6d0baedb..392d3fe5d45 100644 --- a/include/asm-i386/pci.h +++ b/include/asm-i386/pci.h @@ -56,48 +56,11 @@ struct pci_dev; #define pci_unmap_len(PTR, LEN_NAME) (0) #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) -/* This is always fine. */ -#define pci_dac_dma_supported(pci_dev, mask) (1) - -static inline dma64_addr_t -pci_dac_page_to_dma(struct pci_dev *pdev, struct page *page, unsigned long offset, int direction) -{ - return ((dma64_addr_t) page_to_phys(page) + - (dma64_addr_t) offset); -} - -static inline struct page * -pci_dac_dma_to_page(struct pci_dev *pdev, dma64_addr_t dma_addr) -{ - return pfn_to_page(dma_addr >> PAGE_SHIFT); -} - -static inline unsigned long -pci_dac_dma_to_offset(struct pci_dev *pdev, dma64_addr_t dma_addr) -{ - return (dma_addr & ~PAGE_MASK); -} - -static inline void -pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction) -{ -} - -static inline void -pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction) -{ - flush_write_buffers(); -} - #define HAVE_PCI_MMAP extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, enum pci_mmap_state mmap_state, int write_combine); -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - #ifdef CONFIG_PCI static inline void pci_dma_burst_advice(struct pci_dev *pdev, enum pci_dma_burst_strategy *strat, diff --git a/include/asm-i386/pgtable.h b/include/asm-i386/pgtable.h index 2394589786b..628fa7747d0 100644 --- a/include/asm-i386/pgtable.h +++ b/include/asm-i386/pgtable.h @@ -285,32 +285,36 @@ static inline pte_t native_local_ptep_get_and_clear(pte_t *ptep) */ #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS #define ptep_set_access_flags(vma, address, ptep, entry, dirty) \ -do { \ - if (dirty) { \ +({ \ + int __changed = !pte_same(*(ptep), entry); \ + if (__changed && dirty) { \ (ptep)->pte_low = (entry).pte_low; \ pte_update_defer((vma)->vm_mm, (address), (ptep)); \ flush_tlb_page(vma, address); \ } \ -} while (0) + __changed; \ +}) #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY #define ptep_test_and_clear_dirty(vma, addr, ptep) ({ \ - int ret = 0; \ - if (pte_dirty(*ptep)) \ - ret = test_and_clear_bit(_PAGE_BIT_DIRTY, &ptep->pte_low); \ - if (ret) \ - pte_update_defer(vma->vm_mm, addr, ptep); \ - ret; \ + int __ret = 0; \ + if (pte_dirty(*(ptep))) \ + __ret = test_and_clear_bit(_PAGE_BIT_DIRTY, \ + &(ptep)->pte_low); \ + if (__ret) \ + pte_update((vma)->vm_mm, addr, ptep); \ + __ret; \ }) #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG #define ptep_test_and_clear_young(vma, addr, ptep) ({ \ - int ret = 0; \ - if (pte_young(*ptep)) \ - ret = test_and_clear_bit(_PAGE_BIT_ACCESSED, &ptep->pte_low); \ - if (ret) \ - pte_update_defer(vma->vm_mm, addr, ptep); \ - ret; \ + int __ret = 0; \ + if (pte_young(*(ptep))) \ + __ret = test_and_clear_bit(_PAGE_BIT_ACCESSED, \ + &(ptep)->pte_low); \ + if (__ret) \ + pte_update((vma)->vm_mm, addr, ptep); \ + __ret; \ }) /* diff --git a/include/asm-i386/processor.h b/include/asm-i386/processor.h index 338668bfb0a..94e0c147c16 100644 --- a/include/asm-i386/processor.h +++ b/include/asm-i386/processor.h @@ -119,6 +119,7 @@ void __init cpu_detect(struct cpuinfo_x86 *c); extern void identify_boot_cpu(void); extern void identify_secondary_cpu(struct cpuinfo_x86 *); extern void print_cpu_info(struct cpuinfo_x86 *); +extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); extern unsigned short num_cache_leaves; diff --git a/include/asm-i386/required-features.h b/include/asm-i386/required-features.h index 9db866c1e64..65848a00705 100644 --- a/include/asm-i386/required-features.h +++ b/include/asm-i386/required-features.h @@ -3,32 +3,53 @@ /* Define minimum CPUID feature set for kernel These bits are checked really early to actually display a visible error message before the - kernel dies. Only add word 0 bits here + kernel dies. Make sure to assign features to the proper mask! Some requirements that are not in CPUID yet are also in the - CONFIG_X86_MINIMUM_CPU mode which is checked too. + CONFIG_X86_MINIMUM_CPU_FAMILY which is checked too. The real information is in arch/i386/Kconfig.cpu, this just converts the CONFIGs into a bitmask */ +#ifndef CONFIG_MATH_EMULATION +# define NEED_FPU (1<<(X86_FEATURE_FPU & 31)) +#else +# define NEED_FPU 0 +#endif + #ifdef CONFIG_X86_PAE -#define NEED_PAE (1<<X86_FEATURE_PAE) +# define NEED_PAE (1<<(X86_FEATURE_PAE & 31)) #else -#define NEED_PAE 0 +# define NEED_PAE 0 #endif #ifdef CONFIG_X86_CMOV -#define NEED_CMOV (1<<X86_FEATURE_CMOV) +# define NEED_CMOV (1<<(X86_FEATURE_CMOV & 31)) #else -#define NEED_CMOV 0 +# define NEED_CMOV 0 #endif #ifdef CONFIG_X86_CMPXCHG64 -#define NEED_CMPXCHG64 (1<<X86_FEATURE_CX8) +# define NEED_CX8 (1<<(X86_FEATURE_CX8 & 31)) +#else +# define NEED_CX8 0 +#endif + +#define REQUIRED_MASK0 (NEED_FPU|NEED_PAE|NEED_CMOV|NEED_CX8) + +#ifdef CONFIG_X86_USE_3DNOW +# define NEED_3DNOW (1<<(X86_FEATURE_3DNOW & 31)) #else -#define NEED_CMPXCHG64 0 +# define NEED_3DNOW 0 #endif -#define REQUIRED_MASK1 (NEED_PAE|NEED_CMOV|NEED_CMPXCHG64) +#define REQUIRED_MASK1 (NEED_3DNOW) + +#define REQUIRED_MASK2 0 +#define REQUIRED_MASK3 0 +#define REQUIRED_MASK4 0 +#define REQUIRED_MASK5 0 +#define REQUIRED_MASK6 0 +#define REQUIRED_MASK7 0 #endif diff --git a/include/asm-i386/setup.h b/include/asm-i386/setup.h index 0e8077cbfda..0d5bff9dc4a 100644 --- a/include/asm-i386/setup.h +++ b/include/asm-i386/setup.h @@ -26,12 +26,15 @@ #define NEW_CL_POINTER 0x228 /* Relative to real mode data */ #ifndef __ASSEMBLY__ + +#include <asm/bootparam.h> + /* * This is set up by the setup-routine at boot-time */ -extern unsigned char boot_params[PARAM_SIZE]; +extern struct boot_params boot_params; -#define PARAM (boot_params) +#define PARAM ((char *)&boot_params) #define SCREEN_INFO (*(struct screen_info *) (PARAM+0)) #define EXT_MEM_K (*(unsigned short *) (PARAM+2)) #define ALT_MEM_K (*(unsigned long *) (PARAM+0x1e0)) @@ -39,8 +42,7 @@ extern unsigned char boot_params[PARAM_SIZE]; #define E820_MAP ((struct e820entry *) (PARAM+E820MAP)) #define APM_BIOS_INFO (*(struct apm_bios_info *) (PARAM+0x40)) #define IST_INFO (*(struct ist_info *) (PARAM+0x60)) -#define DRIVE_INFO (*(struct drive_info_struct *) (PARAM+0x80)) -#define SYS_DESC_TABLE (*(struct sys_desc_table_struct*)(PARAM+0xa0)) +#define SYS_DESC_TABLE (*(struct sys_desc_table *)(PARAM+0xa0)) #define EFI_SYSTAB ((efi_system_table_t *) *((unsigned long *)(PARAM+0x1c4))) #define EFI_MEMDESC_SIZE (*((unsigned long *) (PARAM+0x1c8))) #define EFI_MEMDESC_VERSION (*((unsigned long *) (PARAM+0x1cc))) diff --git a/include/asm-ia64/mca.h b/include/asm-ia64/mca.h index 41098f45968..edd5d01028d 100644 --- a/include/asm-ia64/mca.h +++ b/include/asm-ia64/mca.h @@ -48,6 +48,7 @@ enum { IA64_MCA_RENDEZ_CHECKIN_NOTDONE = 0x0, IA64_MCA_RENDEZ_CHECKIN_DONE = 0x1, IA64_MCA_RENDEZ_CHECKIN_INIT = 0x2, + IA64_MCA_RENDEZ_CHECKIN_CONCURRENT_MCA = 0x3, }; /* Information maintained by the MC infrastructure */ diff --git a/include/asm-ia64/pci.h b/include/asm-ia64/pci.h index 5a5d1c2ce39..0149097b736 100644 --- a/include/asm-ia64/pci.h +++ b/include/asm-ia64/pci.h @@ -71,14 +71,6 @@ pcibios_penalize_isa_irq (int irq, int active) #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ (((PTR)->LEN_NAME) = (VAL)) -/* The ia64 platform always supports 64-bit addressing. */ -#define pci_dac_dma_supported(pci_dev, mask) (1) -#define pci_dac_page_to_dma(dev,pg,off,dir) ((dma_addr_t) page_to_bus(pg) + (off)) -#define pci_dac_dma_to_page(dev,dma_addr) (virt_to_page(bus_to_virt(dma_addr))) -#define pci_dac_dma_to_offset(dev,dma_addr) offset_in_page(dma_addr) -#define pci_dac_dma_sync_single_for_cpu(dev,dma_addr,len,dir) do { } while (0) -#define pci_dac_dma_sync_single_for_device(dev,dma_addr,len,dir) do { mb(); } while (0) - #ifdef CONFIG_PCI static inline void pci_dma_burst_advice(struct pci_dev *pdev, enum pci_dma_burst_strategy *strat, @@ -104,10 +96,12 @@ extern int pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma, #define HAVE_PCI_LEGACY extern int pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma); -extern ssize_t pci_read_legacy_io(struct kobject *kobj, char *buf, loff_t off, - size_t count); -extern ssize_t pci_write_legacy_io(struct kobject *kobj, char *buf, loff_t off, - size_t count); +extern ssize_t pci_read_legacy_io(struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count); +extern ssize_t pci_write_legacy_io(struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count); extern int pci_mmap_legacy_mem(struct kobject *kobj, struct bin_attribute *attr, struct vm_area_struct *vma); @@ -143,10 +137,6 @@ static inline int pci_proc_domain(struct pci_bus *bus) return (pci_domain_nr(bus) != 0); } -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - extern void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, struct resource *res); diff --git a/include/asm-ia64/pgtable.h b/include/asm-ia64/pgtable.h index 670b706411b..6580f31b313 100644 --- a/include/asm-ia64/pgtable.h +++ b/include/asm-ia64/pgtable.h @@ -533,16 +533,23 @@ extern void lazy_mmu_prot_update (pte_t pte); * daccess_bit in ivt.S). */ #ifdef CONFIG_SMP -# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \ -do { \ - if (__safely_writable) { \ - set_pte(__ptep, __entry); \ - flush_tlb_page(__vma, __addr); \ - } \ -} while (0) +# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \ +({ \ + int __changed = !pte_same(*(__ptep), __entry); \ + if (__changed && __safely_writable) { \ + set_pte(__ptep, __entry); \ + flush_tlb_page(__vma, __addr); \ + } \ + __changed; \ +}) #else -# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \ - ptep_establish(__vma, __addr, __ptep, __entry) +# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \ +({ \ + int __changed = !pte_same(*(__ptep), __entry); \ + if (__changed) \ + ptep_establish(__vma, __addr, __ptep, __entry); \ + __changed; \ +}) #endif # ifdef CONFIG_VIRTUAL_MEM_MAP diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h index 291e8ceed6e..676b31a08c6 100644 --- a/include/asm-ia64/sn/sn_sal.h +++ b/include/asm-ia64/sn/sn_sal.h @@ -32,6 +32,7 @@ #define SN_SAL_NO_FAULT_ZONE_VIRTUAL 0x02000010 #define SN_SAL_NO_FAULT_ZONE_PHYSICAL 0x02000011 #define SN_SAL_PRINT_ERROR 0x02000012 +#define SN_SAL_REGISTER_PMI_HANDLER 0x02000014 #define SN_SAL_SET_ERROR_HANDLING_FEATURES 0x0200001a // reentrant #define SN_SAL_GET_FIT_COMPT 0x0200001b // reentrant #define SN_SAL_GET_SAPIC_INFO 0x0200001d @@ -680,6 +681,25 @@ sn_register_nofault_code(u64 start_addr, u64 end_addr, u64 return_addr, } /* + * Register or unregister a function to handle a PMI received by a CPU. + * Before calling the registered handler, SAL sets r1 to the value that + * was passed in as the global_pointer. + * + * If the handler pointer is NULL, then the currently registered handler + * will be unregistered. + * + * Returns 0 on success, or a negative value if an error occurred. + */ +static inline int +sn_register_pmi_handler(u64 handler, u64 global_pointer) +{ + struct ia64_sal_retval ret_stuff; + ia64_sal_oemcall(&ret_stuff, SN_SAL_REGISTER_PMI_HANDLER, handler, + global_pointer, 0, 0, 0, 0, 0); + return ret_stuff.status; +} + +/* * Change or query the coherence domain for this partition. Each cpu-based * nasid is represented by a bit in an array of 64-bit words: * 0 = not in this partition's coherency domain @@ -696,8 +716,8 @@ static inline int sn_change_coherence(u64 *new_domain, u64 *old_domain) { struct ia64_sal_retval ret_stuff; - ia64_sal_oemcall(&ret_stuff, SN_SAL_COHERENCE, (u64)new_domain, - (u64)old_domain, 0, 0, 0, 0, 0); + ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_COHERENCE, (u64)new_domain, + (u64)old_domain, 0, 0, 0, 0, 0); return ret_stuff.status; } diff --git a/include/asm-ia64/termbits.h b/include/asm-ia64/termbits.h index 4531a511bde..7fae3109ef4 100644 --- a/include/asm-ia64/termbits.h +++ b/include/asm-ia64/termbits.h @@ -26,6 +26,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ diff --git a/include/asm-m32r/termbits.h b/include/asm-m32r/termbits.h index e402641dfba..6be3b8a3984 100644 --- a/include/asm-m32r/termbits.h +++ b/include/asm-m32r/termbits.h @@ -17,6 +17,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ diff --git a/include/asm-m68k/mmzone.h b/include/asm-m68k/mmzone.h new file mode 100644 index 00000000000..e1f1ec7b700 --- /dev/null +++ b/include/asm-m68k/mmzone.h @@ -0,0 +1,9 @@ +#ifndef _ASM_M68K_MMZONE_H_ +#define _ASM_M68K_MMZONE_H_ + +extern pg_data_t pg_data_map[]; + +#define NODE_DATA(nid) (&pg_data_map[nid]) +#define NODE_MEM_MAP(nid) (NODE_DATA(nid)->node_mem_map) + +#endif /* _ASM_M68K_MMZONE_H_ */ diff --git a/include/asm-m68k/module.h b/include/asm-m68k/module.h index c6d75af2d8d..382d20a6fc1 100644 --- a/include/asm-m68k/module.h +++ b/include/asm-m68k/module.h @@ -1,7 +1,39 @@ #ifndef _ASM_M68K_MODULE_H #define _ASM_M68K_MODULE_H -struct mod_arch_specific { }; + +struct mod_arch_specific { + struct m68k_fixup_info *fixup_start, *fixup_end; +}; + +#define MODULE_ARCH_INIT { \ + .fixup_start = __start_fixup, \ + .fixup_end = __stop_fixup, \ +} + #define Elf_Shdr Elf32_Shdr #define Elf_Sym Elf32_Sym #define Elf_Ehdr Elf32_Ehdr + + +enum m68k_fixup_type { + m68k_fixup_memoffset, + m68k_fixup_vnode_shift, +}; + +struct m68k_fixup_info { + enum m68k_fixup_type type; + void *addr; +}; + +#define m68k_fixup(type, addr) \ + " .section \".m68k_fixup\",\"aw\"\n" \ + " .long " #type "," #addr "\n" \ + " .previous\n" + +extern struct m68k_fixup_info __start_fixup[], __stop_fixup[]; + +struct module; +extern void module_fixup(struct module *mod, struct m68k_fixup_info *start, + struct m68k_fixup_info *end); + #endif /* _ASM_M68K_MODULE_H */ diff --git a/include/asm-m68k/motorola_pgtable.h b/include/asm-m68k/motorola_pgtable.h index 61e4406ed96..b5b78c01eb6 100644 --- a/include/asm-m68k/motorola_pgtable.h +++ b/include/asm-m68k/motorola_pgtable.h @@ -130,7 +130,7 @@ static inline void pgd_set(pgd_t *pgdp, pmd_t *pmdp) #define pte_present(pte) (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROTNONE)) #define pte_clear(mm,addr,ptep) ({ pte_val(*(ptep)) = 0; }) -#define pte_page(pte) (mem_map + ((unsigned long)(__va(pte_val(pte)) - PAGE_OFFSET) >> PAGE_SHIFT)) +#define pte_page(pte) virt_to_page(__va(pte_val(pte))) #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) #define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) @@ -143,7 +143,7 @@ static inline void pgd_set(pgd_t *pgdp, pmd_t *pmdp) while (--__i >= 0) \ *__ptr++ = 0; \ }) -#define pmd_page(pmd) (mem_map + ((unsigned long)(__va(pmd_val(pmd)) - PAGE_OFFSET) >> PAGE_SHIFT)) +#define pmd_page(pmd) virt_to_page(__va(pmd_val(pmd))) #define pgd_none(pgd) (!pgd_val(pgd)) @@ -223,10 +223,10 @@ static inline pte_t *pte_offset_kernel(pmd_t *pmdp, unsigned long address) return (pte_t *)__pmd_page(*pmdp) + ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)); } -#define pte_offset_map(pmdp,address) ((pte_t *)kmap(pmd_page(*pmdp)) + ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) +#define pte_offset_map(pmdp,address) ((pte_t *)__pmd_page(*pmdp) + (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) #define pte_offset_map_nested(pmdp, address) pte_offset_map(pmdp, address) -#define pte_unmap(pte) kunmap(pte) -#define pte_unmap_nested(pte) kunmap(pte) +#define pte_unmap(pte) ((void)0) +#define pte_unmap_nested(pte) ((void)0) /* * Allocate and free page tables. The xxx_kernel() versions are diff --git a/include/asm-m68k/page.h b/include/asm-m68k/page.h index fcc165ddd09..9e6d0d6debd 100644 --- a/include/asm-m68k/page.h +++ b/include/asm-m68k/page.h @@ -27,6 +27,8 @@ #ifndef __ASSEMBLY__ +#include <asm/module.h> + #define get_user_page(vaddr) __get_free_page(GFP_KERNEL) #define free_user_page(page, addr) free_page(addr) @@ -114,18 +116,33 @@ typedef struct { unsigned long pgprot; } pgprot_t; #ifndef __ASSEMBLY__ +extern unsigned long m68k_memoffset; + #ifndef CONFIG_SUN3 #define WANT_PAGE_VIRTUAL -#ifdef CONFIG_SINGLE_MEMORY_CHUNK -extern unsigned long m68k_memoffset; -#define __pa(vaddr) ((unsigned long)(vaddr)+m68k_memoffset) -#define __va(paddr) ((void *)((unsigned long)(paddr)-m68k_memoffset)) -#else -#define __pa(vaddr) virt_to_phys((void *)(vaddr)) -#define __va(paddr) phys_to_virt((unsigned long)(paddr)) -#endif +static inline unsigned long ___pa(void *vaddr) +{ + unsigned long paddr; + asm ( + "1: addl #0,%0\n" + m68k_fixup(%c2, 1b+2) + : "=r" (paddr) + : "0" (vaddr), "i" (m68k_fixup_memoffset)); + return paddr; +} +#define __pa(vaddr) ___pa((void *)(vaddr)) +static inline void *__va(unsigned long paddr) +{ + void *vaddr; + asm ( + "1: subl #0,%0\n" + m68k_fixup(%c2, 1b+2) + : "=r" (vaddr) + : "0" (paddr), "i" (m68k_fixup_memoffset)); + return vaddr; +} #else /* !CONFIG_SUN3 */ /* This #define is a horrible hack to suppress lots of warnings. --m */ @@ -161,11 +178,47 @@ static inline void *__va(unsigned long x) #define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT) #define pfn_to_virt(pfn) __va((pfn) << PAGE_SHIFT) -#define virt_to_page(kaddr) (mem_map + (((unsigned long)(kaddr)-PAGE_OFFSET) >> PAGE_SHIFT)) -#define page_to_virt(page) ((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET) +extern int m68k_virt_to_node_shift; + +#ifdef CONFIG_SINGLE_MEMORY_CHUNK +#define __virt_to_node(addr) (&pg_data_map[0]) +#else +extern struct pglist_data *pg_data_table[]; + +static inline __attribute_const__ int __virt_to_node_shift(void) +{ + int shift; + + asm ( + "1: moveq #0,%0\n" + m68k_fixup(%c1, 1b) + : "=d" (shift) + : "i" (m68k_fixup_vnode_shift)); + return shift; +} + +#define __virt_to_node(addr) (pg_data_table[(unsigned long)(addr) >> __virt_to_node_shift()]) +#endif -#define pfn_to_page(pfn) virt_to_page(pfn_to_virt(pfn)) -#define page_to_pfn(page) virt_to_pfn(page_to_virt(page)) +#define virt_to_page(addr) ({ \ + pfn_to_page(virt_to_pfn(addr)); \ +}) +#define page_to_virt(page) ({ \ + pfn_to_virt(page_to_pfn(page)); \ +}) + +#define pfn_to_page(pfn) ({ \ + unsigned long __pfn = (pfn); \ + struct pglist_data *pgdat; \ + pgdat = __virt_to_node((unsigned long)pfn_to_virt(__pfn)); \ + pgdat->node_mem_map + (__pfn - pgdat->node_start_pfn); \ +}) +#define page_to_pfn(_page) ({ \ + struct page *__p = (_page); \ + struct pglist_data *pgdat; \ + pgdat = &pg_data_map[page_to_nid(__p)]; \ + ((__p) - pgdat->node_mem_map) + pgdat->node_start_pfn; \ +}) #define virt_addr_valid(kaddr) ((void *)(kaddr) >= (void *)PAGE_OFFSET && (void *)(kaddr) < high_memory) #define pfn_valid(pfn) virt_addr_valid(pfn_to_virt(pfn)) diff --git a/include/asm-m68k/pci.h b/include/asm-m68k/pci.h index 9d2c07abe44..678cb0b5231 100644 --- a/include/asm-m68k/pci.h +++ b/include/asm-m68k/pci.h @@ -54,8 +54,4 @@ static inline void pcibios_penalize_isa_irq(int irq, int active) */ #define PCI_DMA_BUS_IS_PHYS (1) -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - #endif /* _ASM_M68K_PCI_H */ diff --git a/include/asm-m68k/pgalloc.h b/include/asm-m68k/pgalloc.h index a9cfb4b99d8..4cb1a57ab76 100644 --- a/include/asm-m68k/pgalloc.h +++ b/include/asm-m68k/pgalloc.h @@ -8,11 +8,12 @@ #include <asm/virtconvert.h> - #ifdef CONFIG_SUN3 #include <asm/sun3_pgalloc.h> #else #include <asm/motorola_pgalloc.h> #endif +extern void m68k_setup_node(int node); + #endif /* M68K_PGALLOC_H */ diff --git a/include/asm-m68k/pgtable.h b/include/asm-m68k/pgtable.h index 555b87a1f7e..778a4c538eb 100644 --- a/include/asm-m68k/pgtable.h +++ b/include/asm-m68k/pgtable.h @@ -107,22 +107,7 @@ extern void *empty_zero_page; /* 64-bit machines, beware! SRB. */ #define SIZEOF_PTR_LOG2 2 -/* - * Check if the addr/len goes up to the end of a physical - * memory chunk. Used for DMA functions. - */ -#ifdef CONFIG_SINGLE_MEMORY_CHUNK -/* - * It makes no sense to consider whether we cross a memory boundary if - * we support just one physical chunk of memory. - */ -static inline int mm_end_of_chunk(unsigned long addr, int len) -{ - return 0; -} -#else -int mm_end_of_chunk (unsigned long addr, int len); -#endif +#define mm_end_of_chunk(addr, len) 0 extern void kernel_set_cachemode(void *addr, unsigned long size, int cmode); diff --git a/include/asm-m68k/sun3_pgtable.h b/include/asm-m68k/sun3_pgtable.h index 5156a28a18d..b9e62c1e7ae 100644 --- a/include/asm-m68k/sun3_pgtable.h +++ b/include/asm-m68k/sun3_pgtable.h @@ -132,8 +132,8 @@ static inline void pte_clear (struct mm_struct *mm, unsigned long addr, pte_t *p #define pfn_pte(pfn, pgprot) \ ({ pte_t __pte; pte_val(__pte) = pfn | pgprot_val(pgprot); __pte; }) -#define pte_page(pte) (mem_map+((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT)) -#define pmd_page(pmd) (mem_map+((__pmd_page(pmd) - PAGE_OFFSET) >> PAGE_SHIFT)) +#define pte_page(pte) virt_to_page(__pte_page(pte)) +#define pmd_page(pmd) virt_to_page(__pmd_page(pmd)) static inline int pmd_none2 (pmd_t *pmd) { return !pmd_val (*pmd); } diff --git a/include/asm-m68k/termbits.h b/include/asm-m68k/termbits.h index a194092240f..0e520f328f5 100644 --- a/include/asm-m68k/termbits.h +++ b/include/asm-m68k/termbits.h @@ -17,6 +17,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ diff --git a/include/asm-m68k/virtconvert.h b/include/asm-m68k/virtconvert.h index 83a87c9b1a1..dea32fbc7e5 100644 --- a/include/asm-m68k/virtconvert.h +++ b/include/asm-m68k/virtconvert.h @@ -8,56 +8,35 @@ #ifdef __KERNEL__ #include <linux/compiler.h> +#include <linux/mmzone.h> #include <asm/setup.h> #include <asm/page.h> -#ifdef CONFIG_AMIGA -#include <asm/amigahw.h> -#endif - /* * Change virtual addresses to physical addresses and vv. */ -#ifndef CONFIG_SUN3 -extern unsigned long mm_vtop(unsigned long addr) __attribute_const__; -extern unsigned long mm_ptov(unsigned long addr) __attribute_const__; -#else -static inline unsigned long mm_vtop(unsigned long vaddr) -{ - return __pa(vaddr); -} - -static inline unsigned long mm_ptov(unsigned long paddr) -{ - return (unsigned long)__va(paddr); -} -#endif - -#ifdef CONFIG_SINGLE_MEMORY_CHUNK -static inline unsigned long virt_to_phys(void *vaddr) -{ - return (unsigned long)vaddr - PAGE_OFFSET + m68k_memory[0].addr; -} - -static inline void * phys_to_virt(unsigned long paddr) -{ - return (void *)(paddr - m68k_memory[0].addr + PAGE_OFFSET); -} -#else static inline unsigned long virt_to_phys(void *address) { - return mm_vtop((unsigned long)address); + return __pa(address); } static inline void *phys_to_virt(unsigned long address) { - return (void *) mm_ptov(address); + return __va(address); } -#endif /* Permanent address of a page. */ -#define __page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT)) -#define page_to_phys(page) virt_to_phys((void *)__page_address(page)) +#ifdef CONFIG_SINGLE_MEMORY_CHUNK +#define page_to_phys(page) \ + __pa(PAGE_OFFSET + (((page) - pg_data_map[0].node_mem_map) << PAGE_SHIFT)) +#else +#define page_to_phys(_page) ({ \ + struct page *__page = _page; \ + struct pglist_data *pgdat; \ + pgdat = pg_data_table[page_to_nid(__page)]; \ + page_to_pfn(__page) << PAGE_SHIFT; \ +}) +#endif /* * IO bus memory addresses are 1:1 with the physical address, diff --git a/include/asm-m68knommu/pci.h b/include/asm-m68knommu/pci.h index e04c77e1184..a13f3cc8745 100644 --- a/include/asm-m68knommu/pci.h +++ b/include/asm-m68knommu/pci.h @@ -24,16 +24,6 @@ static inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask) return 1; } -/* - * Not supporting more than 32-bit PCI bus addresses now, but - * must satisfy references to this function. Change if needed. - */ -#define pci_dac_dma_supported(pci_dev, mask) (0) - -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - #endif /* CONFIG_COMEMPCI */ #endif /* M68KNOMMU_PCI_H */ diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h index c6275088cf6..0b3ff9c4840 100644 --- a/include/asm-mips/addrspace.h +++ b/include/asm-mips/addrspace.h @@ -129,28 +129,12 @@ #define PHYS_TO_XKPHYS(cm,a) (_CONST64_(0x8000000000000000) | \ ((cm)<<59) | (a)) -#if defined (CONFIG_CPU_R4300) \ - || defined (CONFIG_CPU_R4X00) \ - || defined (CONFIG_CPU_R5000) \ - || defined (CONFIG_CPU_RM7000) \ - || defined (CONFIG_CPU_NEVADA) \ - || defined (CONFIG_CPU_TX49XX) \ - || defined (CONFIG_CPU_MIPS64) -#define TO_PHYS_MASK _CONST64_(0x0000000fffffffff) /* 2^^36 - 1 */ -#endif - -#if defined (CONFIG_CPU_R8000) -/* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */ -#define TO_PHYS_MASK _CONST64_(0x000000ffffffffff) /* 2^^40 - 1 */ -#endif - -#if defined (CONFIG_CPU_R10000) -#define TO_PHYS_MASK _CONST64_(0x000000ffffffffff) /* 2^^40 - 1 */ -#endif - -#if defined(CONFIG_CPU_SB1) || defined(CONFIG_CPU_SB1A) -#define TO_PHYS_MASK _CONST64_(0x00000fffffffffff) /* 2^^44 - 1 */ -#endif +/* + * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting + * the region, 3 bits for the CCA mode. This leaves 59 bits of which the + * R8000 implements most with its 48-bit physical address space. + */ +#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ #ifndef CONFIG_CPU_R8000 diff --git a/include/asm-mips/asmmacro.h b/include/asm-mips/asmmacro.h index 92e62ef711e..c5f20df780e 100644 --- a/include/asm-mips/asmmacro.h +++ b/include/asm-mips/asmmacro.h @@ -52,21 +52,6 @@ .endm #endif /* CONFIG_MIPS_MT_SMTC */ -#ifdef CONFIG_CPU_SB1 - .macro fpu_enable_hazard - .set push - .set noreorder - .set mips2 - SSNOP - bnezl $0, .+4 - SSNOP - .set pop - .endm -#else - .macro fpu_enable_hazard - .endm -#endif - /* * Temporary until all gas have MT ASE support */ diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index d995413e11f..d9e81af53f7 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -238,10 +238,11 @@ static inline int test_and_set_bit(unsigned long nr, volatile unsigned long *addr) { unsigned short bit = nr & SZLONG_MASK; + unsigned long res; if (cpu_has_llsc && R10000_LLSC_WAR) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - unsigned long temp, res; + unsigned long temp; __asm__ __volatile__( " .set mips3 \n" @@ -254,11 +255,9 @@ static inline int test_and_set_bit(unsigned long nr, : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << bit), "m" (*m) : "memory"); - - return res != 0; } else if (cpu_has_llsc) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - unsigned long temp, res; + unsigned long temp; __asm__ __volatile__( " .set push \n" @@ -277,25 +276,22 @@ static inline int test_and_set_bit(unsigned long nr, : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << bit), "m" (*m) : "memory"); - - return res != 0; } else { volatile unsigned long *a = addr; unsigned long mask; - int retval; unsigned long flags; a += nr >> SZLONG_LOG; mask = 1UL << bit; raw_local_irq_save(flags); - retval = (mask & *a) != 0; + res = (mask & *a); *a |= mask; raw_local_irq_restore(flags); - - return retval; } smp_mb(); + + return res != 0; } /* @@ -310,10 +306,11 @@ static inline int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr) { unsigned short bit = nr & SZLONG_MASK; + unsigned long res; if (cpu_has_llsc && R10000_LLSC_WAR) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - unsigned long temp, res; + unsigned long temp; __asm__ __volatile__( " .set mips3 \n" @@ -327,12 +324,10 @@ static inline int test_and_clear_bit(unsigned long nr, : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << bit), "m" (*m) : "memory"); - - return res != 0; #ifdef CONFIG_CPU_MIPSR2 } else if (__builtin_constant_p(nr)) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - unsigned long temp, res; + unsigned long temp; __asm__ __volatile__( "1: " __LL "%0, %1 # test_and_clear_bit \n" @@ -346,12 +341,10 @@ static inline int test_and_clear_bit(unsigned long nr, : "=&r" (temp), "=m" (*m), "=&r" (res) : "ri" (bit), "m" (*m) : "memory"); - - return res; #endif } else if (cpu_has_llsc) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - unsigned long temp, res; + unsigned long temp; __asm__ __volatile__( " .set push \n" @@ -371,25 +364,22 @@ static inline int test_and_clear_bit(unsigned long nr, : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << bit), "m" (*m) : "memory"); - - return res != 0; } else { volatile unsigned long *a = addr; unsigned long mask; - int retval; unsigned long flags; a += nr >> SZLONG_LOG; mask = 1UL << bit; raw_local_irq_save(flags); - retval = (mask & *a) != 0; + res = (mask & *a); *a &= ~mask; raw_local_irq_restore(flags); - - return retval; } smp_mb(); + + return res != 0; } /* @@ -404,10 +394,11 @@ static inline int test_and_change_bit(unsigned long nr, volatile unsigned long *addr) { unsigned short bit = nr & SZLONG_MASK; + unsigned long res; if (cpu_has_llsc && R10000_LLSC_WAR) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - unsigned long temp, res; + unsigned long temp; __asm__ __volatile__( " .set mips3 \n" @@ -420,11 +411,9 @@ static inline int test_and_change_bit(unsigned long nr, : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << bit), "m" (*m) : "memory"); - - return res != 0; } else if (cpu_has_llsc) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); - unsigned long temp, res; + unsigned long temp; __asm__ __volatile__( " .set push \n" @@ -443,24 +432,22 @@ static inline int test_and_change_bit(unsigned long nr, : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << bit), "m" (*m) : "memory"); - - return res != 0; } else { volatile unsigned long *a = addr; - unsigned long mask, retval; + unsigned long mask; unsigned long flags; a += nr >> SZLONG_LOG; mask = 1UL << bit; raw_local_irq_save(flags); - retval = (mask & *a) != 0; + res = (mask & *a); *a ^= mask; raw_local_irq_restore(flags); - - return retval; } smp_mb(); + + return res != 0; } #include <asm-generic/bitops/non-atomic.h> diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index b0c329783ac..087126a5faf 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h @@ -109,18 +109,12 @@ #define MACH_COSINE_ORION 0 /* - * Valid machtype for group GALILEO - */ -#define MACH_GROUP_GALILEO 11 /* Galileo Eval Boards */ -#define MACH_EV64120A 0 /* EV64120A */ - -/* * Valid machtype for group MOMENCO */ #define MACH_GROUP_MOMENCO 12 /* Momentum Boards */ #define MACH_MOMENCO_OCELOT 0 #define MACH_MOMENCO_OCELOT_G 1 /* no more supported (may 2007) */ -#define MACH_MOMENCO_OCELOT_C 2 +#define MACH_MOMENCO_OCELOT_C 2 /* no more supported (jun 2007) */ #define MACH_MOMENCO_JAGUAR_ATX 3 /* no more supported (may 2007) */ #define MACH_MOMENCO_OCELOT_3 4 @@ -194,13 +188,6 @@ #define MACH_HP_LASERJET 1 /* - * Valid machtype for group LASAT - */ -#define MACH_GROUP_LASAT 21 -#define MACH_LASAT_100 0 /* Masquerade II/SP100/SP50/SP25 */ -#define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */ - -/* * Valid machtype for group TITAN */ #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */ @@ -213,6 +200,27 @@ #define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */ #define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */ +/* + * Valid machtype for group LEMOTE + */ +#define MACH_GROUP_LEMOTE 27 +#define MACH_LEMOTE_FULONG 0 + +/* + * Valid machtype for group PMC-MSP + */ +#define MACH_GROUP_MSP 26 /* PMC-Sierra MSP boards/CPUs */ +#define MACH_MSP4200_EVAL 0 /* PMC-Sierra MSP4200 Evaluation */ +#define MACH_MSP4200_GW 1 /* PMC-Sierra MSP4200 Gateway demo */ +#define MACH_MSP4200_FPGA 2 /* PMC-Sierra MSP4200 Emulation */ +#define MACH_MSP7120_EVAL 3 /* PMC-Sierra MSP7120 Evaluation */ +#define MACH_MSP7120_GW 4 /* PMC-Sierra MSP7120 Residential GW */ +#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */ +#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */ + +#define MACH_GROUP_WINDRIVER 28 /* Windriver boards */ +#define MACH_WRPPMC 1 + #define CL_SIZE COMMAND_LINE_SIZE const char *get_system_type(void); diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h index c4a1ec31ff6..df7f2deb3b5 100644 --- a/include/asm-mips/cacheops.h +++ b/include/asm-mips/cacheops.h @@ -20,7 +20,11 @@ #define Index_Load_Tag_D 0x05 #define Index_Store_Tag_I 0x08 #define Index_Store_Tag_D 0x09 +#if defined(CONFIG_CPU_LOONGSON2) +#define Hit_Invalidate_I 0x00 +#else #define Hit_Invalidate_I 0x10 +#endif #define Hit_Invalidate_D 0x11 #define Hit_Writeback_Inv_D 0x15 diff --git a/include/asm-mips/compat-signal.h b/include/asm-mips/compat-signal.h index 6599a901b63..368a99e5c3e 100644 --- a/include/asm-mips/compat-signal.h +++ b/include/asm-mips/compat-signal.h @@ -10,6 +10,68 @@ #include <asm/uaccess.h> +#define SI_PAD_SIZE32 ((SI_MAX_SIZE/sizeof(int)) - 3) + +typedef struct compat_siginfo { + int si_signo; + int si_code; + int si_errno; + + union { + int _pad[SI_PAD_SIZE32]; + + /* kill() */ + struct { + compat_pid_t _pid; /* sender's pid */ + compat_uid_t _uid; /* sender's uid */ + } _kill; + + /* SIGCHLD */ + struct { + compat_pid_t _pid; /* which child */ + compat_uid_t _uid; /* sender's uid */ + int _status; /* exit code */ + compat_clock_t _utime; + compat_clock_t _stime; + } _sigchld; + + /* IRIX SIGCHLD */ + struct { + compat_pid_t _pid; /* which child */ + compat_clock_t _utime; + int _status; /* exit code */ + compat_clock_t _stime; + } _irix_sigchld; + + /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */ + struct { + s32 _addr; /* faulting insn/memory ref. */ + } _sigfault; + + /* SIGPOLL, SIGXFSZ (To do ...) */ + struct { + int _band; /* POLL_IN, POLL_OUT, POLL_MSG */ + int _fd; + } _sigpoll; + + /* POSIX.1b timers */ + struct { + timer_t _tid; /* timer id */ + int _overrun; /* overrun count */ + compat_sigval_t _sigval;/* same as below */ + int _sys_private; /* not to be passed to user */ + } _timer; + + /* POSIX.1b signals */ + struct { + compat_pid_t _pid; /* sender's pid */ + compat_uid_t _uid; /* sender's uid */ + compat_sigval_t _sigval; + } _rt; + + } _sifields; +} compat_siginfo_t; + static inline int __copy_conv_sigset_to_user(compat_sigset_t __user *d, const sigset_t *s) { diff --git a/include/asm-mips/compat.h b/include/asm-mips/compat.h index 432653d7ae0..67c3f8ec030 100644 --- a/include/asm-mips/compat.h +++ b/include/asm-mips/compat.h @@ -132,7 +132,8 @@ typedef u32 compat_uptr_t; static inline void __user *compat_ptr(compat_uptr_t uptr) { - return (void __user *)(long)uptr; + /* cast to a __user pointer via "unsigned long" makes sparse happy */ + return (void __user *)(unsigned long)(long)uptr; } static inline compat_uptr_t ptr_to_compat(void __user *uptr) diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h index 5e4bed123b4..d95a83e3e1d 100644 --- a/include/asm-mips/cpu-features.h +++ b/include/asm-mips/cpu-features.h @@ -150,6 +150,10 @@ #define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) #endif +#ifndef cpu_has_userlocal +#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI) +#endif + #ifdef CONFIG_32BIT # ifndef cpu_has_nofpuex # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index d38fdbf845b..3857358fb6d 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -89,6 +89,8 @@ #define PRID_IMP_34K 0x9500 #define PRID_IMP_24KE 0x9600 #define PRID_IMP_74K 0x9700 +#define PRID_IMP_LOONGSON1 0x4200 +#define PRID_IMP_LOONGSON2 0x6300 /* * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE @@ -107,6 +109,7 @@ * Definitions for 7:0 on legacy processors */ +#define PRID_REV_MASK 0x00ff #define PRID_REV_TX4927 0x0022 #define PRID_REV_TX4937 0x0030 @@ -123,6 +126,18 @@ #define PRID_REV_VR4122 0x0070 #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ #define PRID_REV_VR4130 0x0080 +#define PRID_REV_34K_V1_0_2 0x0022 + +/* + * Older processors used to encode processor version and revision in two + * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores + * have switched to use the 8-bits as 3:3:2 bitfield with the last field as + * the patch number. *ARGH* + */ +#define PRID_REV_ENCODE_44(ver, rev) \ + ((ver) << 4 | (rev)) +#define PRID_REV_ENCODE_332(ver, rev, patch) \ + ((ver) << 5 | (rev) << 2 | (patch)) /* * FPU implementation/revision register (CP1 control register 0). @@ -200,7 +215,10 @@ #define CPU_SB1A 62 #define CPU_74K 63 #define CPU_R14000 64 -#define CPU_LAST 64 +#define CPU_LOONGSON1 65 +#define CPU_LOONGSON2 66 + +#define CPU_LAST 66 /* * ISA Level encodings @@ -246,6 +264,7 @@ #define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */ #define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */ #define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */ +#define MIPS_CPU_ULRI 0x00400000 /* CPU has ULRI feature */ /* * CPU ASE encodings diff --git a/include/asm-mips/div64.h b/include/asm-mips/div64.h index 66189f5f639..716371bd098 100644 --- a/include/asm-mips/div64.h +++ b/include/asm-mips/div64.h @@ -20,7 +20,7 @@ */ #define do_div64_32(res, high, low, base) ({ \ - unsigned long __quot, __mod; \ + unsigned long __quot32, __mod32; \ unsigned long __cf, __tmp, __tmp2, __i; \ \ __asm__(".set push\n\t" \ @@ -48,12 +48,13 @@ "bnez %4, 0b\n\t" \ " srl %5, %1, 0x1f\n\t" \ ".set pop" \ - : "=&r" (__mod), "=&r" (__tmp), "=&r" (__quot), "=&r" (__cf), \ + : "=&r" (__mod32), "=&r" (__tmp), \ + "=&r" (__quot32), "=&r" (__cf), \ "=&r" (__i), "=&r" (__tmp2) \ : "Jr" (base), "0" (high), "1" (low)); \ \ - (res) = __quot; \ - __mod; }) + (res) = __quot32; \ + __mod32; }) #define do_div(n, base) ({ \ unsigned long long __quot; \ diff --git a/include/asm-mips/gpio.h b/include/asm-mips/gpio.h new file mode 100644 index 00000000000..06e46faf862 --- /dev/null +++ b/include/asm-mips/gpio.h @@ -0,0 +1,6 @@ +#ifndef __ASM_MIPS_GPIO_H +#define __ASM_MIPS_GPIO_H + +#include <gpio.h> + +#endif /* __ASM_MIPS_GPIO_H */ diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index 92ec2618560..7ba92890ea1 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -178,6 +178,11 @@ extern void __iounmap(const volatile void __iomem *addr); static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, unsigned long flags) { + void __iomem *addr = plat_ioremap(offset, size, flags); + + if (addr) + return addr; + #define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL)) if (cpu_has_64bit_addresses) { @@ -207,7 +212,8 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, */ if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) && flags == _CACHE_UNCACHED) - return (void __iomem *)CKSEG1ADDR(phys_addr); + return (void __iomem *) + (unsigned long)CKSEG1ADDR(phys_addr); } return __ioremap(offset, size, flags); @@ -282,6 +288,9 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, static inline void iounmap(const volatile void __iomem *addr) { + if (plat_iounmap(addr)) + return; + #define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1) if (cpu_has_64bit_addresses || diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h index 91803ba30ff..97102ebc54b 100644 --- a/include/asm-mips/irq.h +++ b/include/asm-mips/irq.h @@ -24,7 +24,7 @@ static inline int irq_canonicalize(int irq) #define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */ #endif -#ifdef CONFIG_MIPS_MT_SMTC +#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP /* * Clear interrupt mask handling "backstop" if irq_hwmask * entry so indicates. This implies that the ack() or end() @@ -72,4 +72,13 @@ extern int allocate_irqno(void); extern void alloc_legacy_irqno(void); extern void free_irqno(unsigned int irq); +/* + * Before R2 the timer and performance counter interrupts were both fixed to + * IE7. Since R2 their number has to be read from the c0_intctl register. + */ +#define CP0_LEGACY_COMPARE_IRQ 7 + +extern int cp0_compare_irq; +extern int cp0_perfcount_irq; + #endif /* _ASM_IRQ_H */ diff --git a/include/asm-mips/lasat/ds1603.h b/include/asm-mips/lasat/ds1603.h deleted file mode 100644 index edcd7544b35..00000000000 --- a/include/asm-mips/lasat/ds1603.h +++ /dev/null @@ -1,18 +0,0 @@ -#include <asm/addrspace.h> - -/* Lasat 100 */ -#define DS1603_REG_100 (KSEG1ADDR(0x1c810000)) -#define DS1603_RST_100 (1 << 2) -#define DS1603_CLK_100 (1 << 0) -#define DS1603_DATA_SHIFT_100 1 -#define DS1603_DATA_100 (1 << DS1603_DATA_SHIFT_100) - -/* Lasat 200 */ -#define DS1603_REG_200 (KSEG1ADDR(0x11000000)) -#define DS1603_RST_200 (1 << 3) -#define DS1603_CLK_200 (1 << 4) -#define DS1603_DATA_200 (1 << 5) - -#define DS1603_DATA_REG_200 (DS1603_REG_200 + 0x10000) -#define DS1603_DATA_READ_SHIFT_200 9 -#define DS1603_DATA_READ_200 (1 << DS1603_DATA_READ_SHIFT_200) diff --git a/include/asm-mips/lasat/eeprom.h b/include/asm-mips/lasat/eeprom.h deleted file mode 100644 index 7b53edd5cd5..00000000000 --- a/include/asm-mips/lasat/eeprom.h +++ /dev/null @@ -1,17 +0,0 @@ -#include <asm/addrspace.h> - -/* lasat 100 */ -#define AT93C_REG_100 KSEG1ADDR(0x1c810000) -#define AT93C_RDATA_REG_100 AT93C_REG_100 -#define AT93C_RDATA_SHIFT_100 4 -#define AT93C_WDATA_SHIFT_100 4 -#define AT93C_CS_M_100 ( 1 << 5 ) -#define AT93C_CLK_M_100 ( 1 << 3 ) - -/* lasat 200 */ -#define AT93C_REG_200 KSEG1ADDR(0x11000000) -#define AT93C_RDATA_REG_200 (AT93C_REG_200+0x10000) -#define AT93C_RDATA_SHIFT_200 8 -#define AT93C_WDATA_SHIFT_200 2 -#define AT93C_CS_M_200 ( 1 << 0 ) -#define AT93C_CLK_M_200 ( 1 << 1 ) diff --git a/include/asm-mips/lasat/head.h b/include/asm-mips/lasat/head.h deleted file mode 100644 index f5589f31a19..00000000000 --- a/include/asm-mips/lasat/head.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Image header stuff - */ -#ifndef _HEAD_H -#define _HEAD_H - -#define LASAT_K_MAGIC0_VAL 0xfedeabba -#define LASAT_K_MAGIC1_VAL 0x00bedead - -#ifndef _LANGUAGE_ASSEMBLY -#include <linux/types.h> -struct bootloader_header { - u32 magic[2]; - u32 version; - u32 image_start; - u32 image_size; - u32 kernel_start; - u32 kernel_entry; -}; -#endif - -#endif /* _HEAD_H */ diff --git a/include/asm-mips/lasat/lasat.h b/include/asm-mips/lasat/lasat.h deleted file mode 100644 index 42077e367a5..00000000000 --- a/include/asm-mips/lasat/lasat.h +++ /dev/null @@ -1,253 +0,0 @@ -/* - * lasat.h - * - * Thomas Horsten <thh@lasat.com> - * Copyright (C) 2000 LASAT Networks A/S. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Configuration for LASAT boards, loads the appropriate include files. - */ -#ifndef _LASAT_H -#define _LASAT_H - -#ifndef _LANGUAGE_ASSEMBLY - -extern struct lasat_misc { - volatile u32 *reset_reg; - volatile u32 *flash_wp_reg; - u32 flash_wp_bit; -} *lasat_misc; - -enum lasat_mtdparts { - LASAT_MTD_BOOTLOADER, - LASAT_MTD_SERVICE, - LASAT_MTD_NORMAL, - LASAT_MTD_CONFIG, - LASAT_MTD_FS, - LASAT_MTD_LAST -}; - -/* - * The format of the data record in the EEPROM. - * See Documentation/LASAT/eeprom.txt for a detailed description - * of the fields in this struct, and the LASAT Hardware Configuration - * field specification for a detailed description of the config - * field. - */ -#include <linux/types.h> - -#define LASAT_EEPROM_VERSION 7 -struct lasat_eeprom_struct { - unsigned int version; - unsigned int cfg[3]; - unsigned char hwaddr[6]; - unsigned char print_partno[12]; - unsigned char term0; - unsigned char print_serial[14]; - unsigned char term1; - unsigned char prod_partno[12]; - unsigned char term2; - unsigned char prod_serial[14]; - unsigned char term3; - unsigned char passwd_hash[16]; - unsigned char pwdnull; - unsigned char vendid; - unsigned char ts_ref; - unsigned char ts_signoff; - unsigned char reserved[11]; - unsigned char debugaccess; - unsigned short prid; - unsigned int serviceflag; - unsigned int ipaddr; - unsigned int netmask; - unsigned int crc32; -}; - -struct lasat_eeprom_struct_pre7 { - unsigned int version; - unsigned int flags[3]; - unsigned char hwaddr0[6]; - unsigned char hwaddr1[6]; - unsigned char print_partno[9]; - unsigned char term0; - unsigned char print_serial[14]; - unsigned char term1; - unsigned char prod_partno[9]; - unsigned char term2; - unsigned char prod_serial[14]; - unsigned char term3; - unsigned char passwd_hash[24]; - unsigned char pwdnull; - unsigned char vendor; - unsigned char ts_ref; - unsigned char ts_signoff; - unsigned char reserved[6]; - unsigned int writecount; - unsigned int ipaddr; - unsigned int netmask; - unsigned int crc32; -}; - -/* Configuration descriptor encoding - see the doc for details */ - -#define LASAT_W0_DSCTYPE(v) ( ( (v) ) & 0xf ) -#define LASAT_W0_BMID(v) ( ( (v) >> 0x04 ) & 0xf ) -#define LASAT_W0_CPUTYPE(v) ( ( (v) >> 0x08 ) & 0xf ) -#define LASAT_W0_BUSSPEED(v) ( ( (v) >> 0x0c ) & 0xf ) -#define LASAT_W0_CPUCLK(v) ( ( (v) >> 0x10 ) & 0xf ) -#define LASAT_W0_SDRAMBANKSZ(v) ( ( (v) >> 0x14 ) & 0xf ) -#define LASAT_W0_SDRAMBANKS(v) ( ( (v) >> 0x18 ) & 0xf ) -#define LASAT_W0_L2CACHE(v) ( ( (v) >> 0x1c ) & 0xf ) - -#define LASAT_W1_EDHAC(v) ( ( (v) ) & 0xf ) -#define LASAT_W1_HIFN(v) ( ( (v) >> 0x04 ) & 0x1 ) -#define LASAT_W1_ISDN(v) ( ( (v) >> 0x05 ) & 0x1 ) -#define LASAT_W1_IDE(v) ( ( (v) >> 0x06 ) & 0x1 ) -#define LASAT_W1_HDLC(v) ( ( (v) >> 0x07 ) & 0x1 ) -#define LASAT_W1_USVERSION(v) ( ( (v) >> 0x08 ) & 0x1 ) -#define LASAT_W1_4MACS(v) ( ( (v) >> 0x09 ) & 0x1 ) -#define LASAT_W1_EXTSERIAL(v) ( ( (v) >> 0x0a ) & 0x1 ) -#define LASAT_W1_FLASHSIZE(v) ( ( (v) >> 0x0c ) & 0xf ) -#define LASAT_W1_PCISLOTS(v) ( ( (v) >> 0x10 ) & 0xf ) -#define LASAT_W1_PCI1OPT(v) ( ( (v) >> 0x14 ) & 0xf ) -#define LASAT_W1_PCI2OPT(v) ( ( (v) >> 0x18 ) & 0xf ) -#define LASAT_W1_PCI3OPT(v) ( ( (v) >> 0x1c ) & 0xf ) - -/* Routines specific to LASAT boards */ - -#define LASAT_BMID_MASQUERADE2 0 -#define LASAT_BMID_MASQUERADEPRO 1 -#define LASAT_BMID_SAFEPIPE25 2 -#define LASAT_BMID_SAFEPIPE50 3 -#define LASAT_BMID_SAFEPIPE100 4 -#define LASAT_BMID_SAFEPIPE5000 5 -#define LASAT_BMID_SAFEPIPE7000 6 -#define LASAT_BMID_SAFEPIPE1000 7 -//#define LASAT_BMID_SAFEPIPE30 7 -//#define LASAT_BMID_SAFEPIPE5100 8 -//#define LASAT_BMID_SAFEPIPE7100 9 -#define LASAT_BMID_UNKNOWN 0xf -#define LASAT_MAX_BMID_NAMES 9 // no larger than 15! - -#define LASAT_HAS_EDHAC ( 1 << 0 ) -#define LASAT_EDHAC_FAST ( 1 << 1 ) -#define LASAT_HAS_EADI ( 1 << 2 ) -#define LASAT_HAS_HIFN ( 1 << 3 ) -#define LASAT_HAS_ISDN ( 1 << 4 ) -#define LASAT_HAS_LEASEDLINE_IF ( 1 << 5 ) -#define LASAT_HAS_HDC ( 1 << 6 ) - -#define LASAT_PRID_MASQUERADE2 0 -#define LASAT_PRID_MASQUERADEPRO 1 -#define LASAT_PRID_SAFEPIPE25 2 -#define LASAT_PRID_SAFEPIPE50 3 -#define LASAT_PRID_SAFEPIPE100 4 -#define LASAT_PRID_SAFEPIPE5000 5 -#define LASAT_PRID_SAFEPIPE7000 6 -#define LASAT_PRID_SAFEPIPE30 7 -#define LASAT_PRID_SAFEPIPE5100 8 -#define LASAT_PRID_SAFEPIPE7100 9 - -#define LASAT_PRID_SAFEPIPE1110 10 -#define LASAT_PRID_SAFEPIPE3020 11 -#define LASAT_PRID_SAFEPIPE3030 12 -#define LASAT_PRID_SAFEPIPE5020 13 -#define LASAT_PRID_SAFEPIPE5030 14 -#define LASAT_PRID_SAFEPIPE1120 15 -#define LASAT_PRID_SAFEPIPE1130 16 -#define LASAT_PRID_SAFEPIPE6010 17 -#define LASAT_PRID_SAFEPIPE6110 18 -#define LASAT_PRID_SAFEPIPE6210 19 -#define LASAT_PRID_SAFEPIPE1020 20 -#define LASAT_PRID_SAFEPIPE1040 21 -#define LASAT_PRID_SAFEPIPE1060 22 - -struct lasat_info { - unsigned int li_cpu_hz; - unsigned int li_bus_hz; - unsigned int li_bmid; - unsigned int li_memsize; - unsigned int li_flash_size; - unsigned int li_prid; - unsigned char li_bmstr[16]; - unsigned char li_namestr[32]; - unsigned char li_typestr[16]; - /* Info on the Flash layout */ - unsigned int li_flash_base; - unsigned long li_flashpart_base[LASAT_MTD_LAST]; - unsigned long li_flashpart_size[LASAT_MTD_LAST]; - struct lasat_eeprom_struct li_eeprom_info; - unsigned int li_eeprom_upgrade_version; - unsigned int li_debugaccess; -}; - -extern struct lasat_info lasat_board_info; - -static inline unsigned long lasat_flash_partition_start(int partno) -{ - if (partno < 0 || partno >= LASAT_MTD_LAST) - return 0; - - return lasat_board_info.li_flashpart_base[partno]; -} - -static inline unsigned long lasat_flash_partition_size(int partno) -{ - if (partno < 0 || partno >= LASAT_MTD_LAST) - return 0; - - return lasat_board_info.li_flashpart_size[partno]; -} - -/* Called from setup() to initialize the global board_info struct */ -extern int lasat_init_board_info(void); - -/* Write the modified EEPROM info struct */ -extern void lasat_write_eeprom_info(void); - -#define N_MACHTYPES 2 -/* for calibration of delays */ - -/* the lasat_ndelay function is necessary because it is used at an - * early stage of the boot process where ndelay is not calibrated. - * It is used for the bit-banging rtc and eeprom drivers */ - -#include <asm/delay.h> -/* calculating with the slowest board with 100 MHz clock */ -#define LASAT_100_DIVIDER 20 -/* All 200's run at 250 MHz clock */ -#define LASAT_200_DIVIDER 8 - -extern unsigned int lasat_ndelay_divider; - -static inline void lasat_ndelay(unsigned int ns) -{ - __delay(ns / lasat_ndelay_divider); -} - -#endif /* !defined (_LANGUAGE_ASSEMBLY) */ - -#define LASAT_SERVICEMODE_MAGIC_1 0xdeadbeef -#define LASAT_SERVICEMODE_MAGIC_2 0xfedeabba - -/* Lasat 100 boards */ -#define LASAT_GT_BASE (KSEG1ADDR(0x14000000)) - -/* Lasat 200 boards */ -#define Vrc5074_PHYS_BASE 0x1fa00000 -#define Vrc5074_BASE (KSEG1ADDR(Vrc5074_PHYS_BASE)) -#define PCI_WINDOW1 0x1a000000 - -#endif /* _LASAT_H */ diff --git a/include/asm-mips/lasat/lasatint.h b/include/asm-mips/lasat/lasatint.h deleted file mode 100644 index 065474feecc..00000000000 --- a/include/asm-mips/lasat/lasatint.h +++ /dev/null @@ -1,12 +0,0 @@ -#define LASATINT_END 16 - -/* lasat 100 */ -#define LASAT_INT_STATUS_REG_100 (KSEG1ADDR(0x1c880000)) -#define LASAT_INT_MASK_REG_100 (KSEG1ADDR(0x1c890000)) -#define LASATINT_MASK_SHIFT_100 0 - -/* lasat 200 */ -#define LASAT_INT_STATUS_REG_200 (KSEG1ADDR(0x1104003c)) -#define LASAT_INT_MASK_REG_200 (KSEG1ADDR(0x1104003c)) -#define LASATINT_MASK_SHIFT_200 16 - diff --git a/include/asm-mips/lasat/picvue.h b/include/asm-mips/lasat/picvue.h deleted file mode 100644 index 42a492edc40..00000000000 --- a/include/asm-mips/lasat/picvue.h +++ /dev/null @@ -1,15 +0,0 @@ -/* Lasat 100 */ -#define PVC_REG_100 KSEG1ADDR(0x1c820000) -#define PVC_DATA_SHIFT_100 0 -#define PVC_DATA_M_100 0xFF -#define PVC_E_100 (1 << 8) -#define PVC_RW_100 (1 << 9) -#define PVC_RS_100 (1 << 10) - -/* Lasat 200 */ -#define PVC_REG_200 KSEG1ADDR(0x11000000) -#define PVC_DATA_SHIFT_200 24 -#define PVC_DATA_M_200 (0xFF << PVC_DATA_SHIFT_200) -#define PVC_E_200 (1 << 16) -#define PVC_RW_200 (1 << 17) -#define PVC_RS_200 (1 << 18) diff --git a/include/asm-mips/lasat/serial.h b/include/asm-mips/lasat/serial.h deleted file mode 100644 index 9e88c7669c7..00000000000 --- a/include/asm-mips/lasat/serial.h +++ /dev/null @@ -1,13 +0,0 @@ -#include <asm/lasat/lasat.h> - -/* Lasat 100 boards serial configuration */ -#define LASAT_BASE_BAUD_100 ( 7372800 / 16 ) -#define LASAT_UART_REGS_BASE_100 0x1c8b0000 -#define LASAT_UART_REGS_SHIFT_100 2 -#define LASATINT_UART_100 8 - -/* * LASAT 200 boards serial configuration */ -#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12) -#define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300) -#define LASAT_UART_REGS_SHIFT_200 3 -#define LASATINT_UART_200 13 diff --git a/include/asm-mips/mach-au1x00/au1xxx_gpio.h b/include/asm-mips/mach-au1x00/au1xxx_gpio.h deleted file mode 100644 index 27911e054ff..00000000000 --- a/include/asm-mips/mach-au1x00/au1xxx_gpio.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef __AU1XXX_GPIO_H -#define __AU1XXX_GPIO_H - -void au1xxx_gpio1_set_inputs(void); -void au1xxx_gpio_tristate(int signal); -void au1xxx_gpio_write(int signal, int value); -int au1xxx_gpio_read(int signal); - -typedef volatile struct -{ - u32 dir; - u32 reserved; - u32 output; - u32 pinstate; - u32 inten; - u32 enable; - -} AU1X00_GPIO2; - -#endif //__AU1XXX_GPIO_H diff --git a/include/asm-mips/mach-au1x00/au1xxx_ide.h b/include/asm-mips/mach-au1x00/au1xxx_ide.h index 8fcae21adbd..4663e8b415c 100644 --- a/include/asm-mips/mach-au1x00/au1xxx_ide.h +++ b/include/asm-mips/mach-au1x00/au1xxx_ide.h @@ -88,26 +88,26 @@ static const struct drive_list_entry dma_white_list [] = { /* * Hitachi */ - { "HITACHI_DK14FA-20" , "ALL" }, - { "HTS726060M9AT00" , "ALL" }, + { "HITACHI_DK14FA-20" , NULL }, + { "HTS726060M9AT00" , NULL }, /* * Maxtor */ - { "Maxtor 6E040L0" , "ALL" }, - { "Maxtor 6Y080P0" , "ALL" }, - { "Maxtor 6Y160P0" , "ALL" }, + { "Maxtor 6E040L0" , NULL }, + { "Maxtor 6Y080P0" , NULL }, + { "Maxtor 6Y160P0" , NULL }, /* * Seagate */ - { "ST3120026A" , "ALL" }, - { "ST320014A" , "ALL" }, - { "ST94011A" , "ALL" }, - { "ST340016A" , "ALL" }, + { "ST3120026A" , NULL }, + { "ST320014A" , NULL }, + { "ST94011A" , NULL }, + { "ST340016A" , NULL }, /* * Western Digital */ - { "WDC WD400UE-00HCT0" , "ALL" }, - { "WDC WD400JB-00JJC0" , "ALL" }, + { "WDC WD400UE-00HCT0" , NULL }, + { "WDC WD400JB-00JJC0" , NULL }, { NULL , NULL } }; @@ -116,9 +116,9 @@ static const struct drive_list_entry dma_black_list [] = { /* * Western Digital */ - { "WDC WD100EB-00CGH0" , "ALL" }, - { "WDC WD200BB-00AUA1" , "ALL" }, - { "WDC AC24300L" , "ALL" }, + { "WDC WD100EB-00CGH0" , NULL }, + { "WDC WD200BB-00AUA1" , NULL }, + { "WDC AC24300L" , NULL }, { NULL , NULL } }; #endif diff --git a/include/asm-mips/mach-au1x00/gpio.h b/include/asm-mips/mach-au1x00/gpio.h new file mode 100644 index 00000000000..2dc61e009a0 --- /dev/null +++ b/include/asm-mips/mach-au1x00/gpio.h @@ -0,0 +1,69 @@ +#ifndef _AU1XXX_GPIO_H_ +#define _AU1XXX_GPIO_H_ + +#include <linux/types.h> + +#define AU1XXX_GPIO_BASE 200 + +struct au1x00_gpio2 { + u32 dir; + u32 reserved; + u32 output; + u32 pinstate; + u32 inten; + u32 enable; +}; + +extern int au1xxx_gpio_get_value(unsigned gpio); +extern void au1xxx_gpio_set_value(unsigned gpio, int value); +extern int au1xxx_gpio_direction_input(unsigned gpio); +extern int au1xxx_gpio_direction_output(unsigned gpio, int value); + + +/* Wrappers for the arch-neutral GPIO API */ + +static inline int gpio_request(unsigned gpio, const char *label) +{ + /* Not yet implemented */ + return 0; +} + +static inline void gpio_free(unsigned gpio) +{ + /* Not yet implemented */ +} + +static inline int gpio_direction_input(unsigned gpio) +{ + return au1xxx_gpio_direction_input(gpio); +} + +static inline int gpio_direction_output(unsigned gpio, int value) +{ + return au1xxx_gpio_direction_output(gpio, value); +} + +static inline int gpio_get_value(unsigned gpio) +{ + return au1xxx_gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + au1xxx_gpio_set_value(gpio, value); +} + +static inline int gpio_to_irq(unsigned gpio) +{ + return gpio; +} + +static inline int irq_to_gpio(unsigned irq) +{ + return irq; +} + +/* For cansleep */ +#include <asm-generic/gpio.h> + +#endif /* _AU1XXX_GPIO_H_ */ diff --git a/include/asm-mips/mach-au1x00/ioremap.h b/include/asm-mips/mach-au1x00/ioremap.h index 098fca4289b..364cea2dc71 100644 --- a/include/asm-mips/mach-au1x00/ioremap.h +++ b/include/asm-mips/mach-au1x00/ioremap.h @@ -28,4 +28,15 @@ static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) return __fixup_bigphys_addr(phys_addr, size); } +static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, + unsigned long flags) +{ + return NULL; +} + +static inline int plat_iounmap(const volatile void __iomem *addr) +{ + return 0; +} + #endif /* __ASM_MACH_AU1X00_IOREMAP_H */ diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h index 684a501c04c..9c9d2b998ca 100644 --- a/include/asm-mips/mach-cobalt/cobalt.h +++ b/include/asm-mips/mach-cobalt/cobalt.h @@ -30,7 +30,6 @@ #define COBALT_CPU_IRQ MIPS_CPU_IRQ_BASE #define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2) -#define COBALT_SCC_IRQ (COBALT_CPU_IRQ + 3) /* pre-production has 85C30 */ #define COBALT_RAQ_SCSI_IRQ (COBALT_CPU_IRQ + 3) #define COBALT_ETH0_IRQ (COBALT_CPU_IRQ + 3) #define COBALT_QUBE1_ETH0_IRQ (COBALT_CPU_IRQ + 4) @@ -71,10 +70,6 @@ extern int cobalt_board_id; -#define PCI_CFG_SET(devfn,where) \ - GT_WRITE(GT_PCI0_CFGADDR_OFS, (0x80000000 | (PCI_SLOT (devfn) << 11) | \ - (PCI_FUNC (devfn) << 8) | (where))) - #define COBALT_LED_PORT (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000)) # define COBALT_LED_BAR_LEFT (1 << 0) /* Qube */ # define COBALT_LED_BAR_RIGHT (1 << 1) /* Qube */ diff --git a/include/asm-mips/mach-ev64120/mach-gt64120.h b/include/asm-mips/mach-ev64120/mach-gt64120.h deleted file mode 100644 index 7e272ce57ea..00000000000 --- a/include/asm-mips/mach-ev64120/mach-gt64120.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This is a direct copy of the ev96100.h file, with a global - * search and replace. The numbers are the same. - * - * The reason I'm duplicating this is so that the 64120/96100 - * defines won't be confusing in the source code. - */ -#ifndef __ASM_GALILEO_BOARDS_MIPS_EV64120_H -#define __ASM_GALILEO_BOARDS_MIPS_EV64120_H - -/* - * GT64120 config space base address - */ -extern unsigned long gt64120_base; - -#define GT64120_BASE (gt64120_base) - -/* - * PCI Bus allocation - */ -#define GT_PCI_MEM_BASE 0x12000000UL -#define GT_PCI_MEM_SIZE 0x02000000UL -#define GT_PCI_IO_BASE 0x10000000UL -#define GT_PCI_IO_SIZE 0x02000000UL -#define GT_ISA_IO_BASE PCI_IO_BASE - -/* - * Duart I/O ports. - */ -#define EV64120_COM1_BASE_ADDR (0x1d000000 + 0x20) -#define EV64120_COM2_BASE_ADDR (0x1d000000 + 0x00) - - -/* - * EV64120 interrupt controller register base. - */ -#define EV64120_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000)) - -/* - * EV64120 UART register base. - */ -#define EV64120_UART0_REGS_BASE (KSEG1ADDR(EV64120_COM1_BASE_ADDR)) -#define EV64120_UART1_REGS_BASE (KSEG1ADDR(EV64120_COM2_BASE_ADDR)) -#define EV64120_BASE_BAUD ( 3686400 / 16 ) -#define EV64120_UART_IRQ 6 - -/* - * PCI interrupts will come in on either the INTA or INTD interrups lines, - * which are mapped to the #2 and #5 interrupt pins of the MIPS. On our - * boards, they all either come in on IntD or they all come in on IntA, they - * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the - * "requested" interrupt numbers and go through the list whenever we get an - * IntA/D. - * - * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and - * INTD is 11. - */ -#define GT_TIMER 4 -#define GT_INTA 2 -#define GT_INTD 5 - -#endif /* __ASM_GALILEO_BOARDS_MIPS_EV64120_H */ diff --git a/include/asm-mips/mach-generic/gpio.h b/include/asm-mips/mach-generic/gpio.h new file mode 100644 index 00000000000..6eaf5efedf3 --- /dev/null +++ b/include/asm-mips/mach-generic/gpio.h @@ -0,0 +1,15 @@ +#ifndef __ASM_MACH_GENERIC_GPIO_H +#define __ASM_MACH_GENERIC_GPIO_H + +int gpio_request(unsigned gpio, const char *label); +void gpio_free(unsigned gpio); +int gpio_direction_input(unsigned gpio); +int gpio_direction_output(unsigned gpio, int value); +int gpio_get_value(unsigned gpio); +void gpio_set_value(unsigned gpio, int value); +int gpio_to_irq(unsigned gpio); +int irq_to_gpio(unsigned irq); + +#include <asm-generic/gpio.h> /* cansleep wrappers */ + +#endif /* __ASM_MACH_GENERIC_GPIO_H */ diff --git a/include/asm-mips/mach-generic/ioremap.h b/include/asm-mips/mach-generic/ioremap.h index 9b64ff6e485..b379938d47f 100644 --- a/include/asm-mips/mach-generic/ioremap.h +++ b/include/asm-mips/mach-generic/ioremap.h @@ -20,4 +20,15 @@ static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) return phys_addr; } +static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, + unsigned long flags) +{ + return NULL; +} + +static inline int plat_iounmap(const volatile void __iomem *addr) +{ + return 0; +} + #endif /* __ASM_MACH_GENERIC_IOREMAP_H */ diff --git a/include/asm-mips/mach-generic/spaces.h b/include/asm-mips/mach-generic/spaces.h index 0ae9997bc9a..c9fa4b14968 100644 --- a/include/asm-mips/mach-generic/spaces.h +++ b/include/asm-mips/mach-generic/spaces.h @@ -10,38 +10,54 @@ #ifndef _ASM_MACH_GENERIC_SPACES_H #define _ASM_MACH_GENERIC_SPACES_H +#include <linux/const.h> + +/* + * This gives the physical RAM offset. + */ +#ifndef PHYS_OFFSET +#define PHYS_OFFSET _AC(0, UL) +#endif #ifdef CONFIG_32BIT -#define CAC_BASE 0x80000000 -#define IO_BASE 0xa0000000 -#define UNCAC_BASE 0xa0000000 -#define MAP_BASE 0xc0000000 +#define CAC_BASE _AC(0x80000000, UL) +#define IO_BASE _AC(0xa0000000, UL) +#define UNCAC_BASE _AC(0xa0000000, UL) -/* - * This handles the memory map. - * We handle pages at KSEG0 for kernels with 32 bit address space. - */ -#define PAGE_OFFSET 0x80000000UL +#ifndef MAP_BASE +#define MAP_BASE _AC(0xc0000000, UL) +#endif /* * Memory above this physical address will be considered highmem. */ #ifndef HIGHMEM_START -#define HIGHMEM_START 0x20000000UL +#define HIGHMEM_START _AC(0x20000000, UL) #endif #endif /* CONFIG_32BIT */ #ifdef CONFIG_64BIT -/* - * This handles the memory map. - */ +#ifndef CAC_BASE #ifdef CONFIG_DMA_NONCOHERENT -#define PAGE_OFFSET 0x9800000000000000UL +#define CAC_BASE _AC(0x9800000000000000, UL) #else -#define PAGE_OFFSET 0xa800000000000000UL +#define CAC_BASE _AC(0xa800000000000000, UL) +#endif +#endif + +#ifndef IO_BASE +#define IO_BASE _AC(0x9000000000000000, UL) +#endif + +#ifndef UNCAC_BASE +#define UNCAC_BASE _AC(0x9000000000000000, UL) +#endif + +#ifndef MAP_BASE +#define MAP_BASE _AC(0xc000000000000000, UL) #endif /* @@ -50,22 +66,20 @@ * in the distant future. Nobody will care for a few years :-) */ #ifndef HIGHMEM_START -#define HIGHMEM_START (1UL << 59UL) +#define HIGHMEM_START (_AC(1, UL) << _AC(59, UL)) #endif -#ifdef CONFIG_DMA_NONCOHERENT -#define CAC_BASE 0x9800000000000000UL -#else -#define CAC_BASE 0xa800000000000000UL -#endif -#define IO_BASE 0x9000000000000000UL -#define UNCAC_BASE 0x9000000000000000UL -#define MAP_BASE 0xc000000000000000UL - #define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) #define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) #define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) #endif /* CONFIG_64BIT */ +/* + * This handles the memory map. + */ +#ifndef PAGE_OFFSET +#define PAGE_OFFSET (CAC_BASE + PHYS_OFFSET) +#endif + #endif /* __ASM_MACH_GENERIC_SPACES_H */ diff --git a/include/asm-mips/mach-ip22/spaces.h b/include/asm-mips/mach-ip22/spaces.h index ab20c026fd1..7f9fa6f6605 100644 --- a/include/asm-mips/mach-ip22/spaces.h +++ b/include/asm-mips/mach-ip22/spaces.h @@ -11,44 +11,17 @@ #define _ASM_MACH_IP22_SPACES_H -#ifdef CONFIG_32BIT - -#define CAC_BASE 0x80000000 -#define IO_BASE 0xa0000000 -#define UNCAC_BASE 0xa0000000 -#define MAP_BASE 0xc0000000 - -/* - * This handles the memory map. - * We handle pages at KSEG0 for kernels with 32 bit address space. - */ -#define PAGE_OFFSET 0x80000000UL - -/* - * Memory above this physical address will be considered highmem. - */ -#ifndef HIGHMEM_START -#define HIGHMEM_START 0x20000000UL -#endif - -#endif /* CONFIG_32BIT */ - #ifdef CONFIG_64BIT -#define PAGE_OFFSET 0xffffffff80000000UL -#ifndef HIGHMEM_START -#define HIGHMEM_START (1UL << 59UL) -#endif +#define PAGE_OFFSET 0xffffffff80000000UL #define CAC_BASE 0xffffffff80000000 #define IO_BASE 0xffffffffa0000000 #define UNCAC_BASE 0xffffffffa0000000 #define MAP_BASE 0xc000000000000000 -#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) -#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) -#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) - #endif /* CONFIG_64BIT */ +#include <asm/mach-generic/spaces.h> + #endif /* __ASM_MACH_IP22_SPACES_H */ diff --git a/include/asm-mips/mach-ip27/spaces.h b/include/asm-mips/mach-ip27/spaces.h index 45e61785ef4..b18802a0b17 100644 --- a/include/asm-mips/mach-ip27/spaces.h +++ b/include/asm-mips/mach-ip27/spaces.h @@ -14,22 +14,17 @@ * IP27 uses the R10000's uncached attribute feature. Attribute 3 selects * uncached memory addressing. */ -#define CAC_BASE 0xa800000000000000 #define HSPEC_BASE 0x9000000000000000 #define IO_BASE 0x9200000000000000 #define MSPEC_BASE 0x9400000000000000 #define UNCAC_BASE 0x9600000000000000 -#define MAP_BASE 0xc000000000000000 -#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) -#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) -#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) #define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK)) #define TO_HSPEC(x) (HSPEC_BASE | ((x) & TO_PHYS_MASK)) -#define PAGE_OFFSET CAC_BASE - #define HIGHMEM_START (~0UL) +#include <asm/mach-generic/spaces.h> + #endif /* _ASM_MACH_IP27_SPACES_H */ diff --git a/include/asm-mips/mach-ip32/dma-coherence.h b/include/asm-mips/mach-ip32/dma-coherence.h index c3f9a6a20eb..a5511ebb2d5 100644 --- a/include/asm-mips/mach-ip32/dma-coherence.h +++ b/include/asm-mips/mach-ip32/dma-coherence.h @@ -6,8 +6,8 @@ * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org> * */ -#ifndef __ASM_MACH_IP35_DMA_COHERENCE_H -#define __ASM_MACH_IP35_DMA_COHERENCE_H +#ifndef __ASM_MACH_IP32_DMA_COHERENCE_H +#define __ASM_MACH_IP32_DMA_COHERENCE_H #include <asm/ip32/crime.h> @@ -69,4 +69,4 @@ static inline int plat_device_is_coherent(struct device *dev) return 0; /* IP32 is non-cohernet */ } -#endif /* __ASM_MACH_IP35_DMA_COHERENCE_H */ +#endif /* __ASM_MACH_IP32_DMA_COHERENCE_H */ diff --git a/include/asm-mips/mach-ip32/spaces.h b/include/asm-mips/mach-ip32/spaces.h deleted file mode 100644 index 44abe5c0238..00000000000 --- a/include/asm-mips/mach-ip32/spaces.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 - 1999, 2000, 03, 04, 05 Ralf Baechle (ralf@linux-mips.org) - * Copyright (C) 2000, 2002 Maciej W. Rozycki - * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_MACH_IP32_SPACES_H -#define _ASM_MACH_IP32_SPACES_H - -/* - * Memory above this physical address will be considered highmem. - * Fixme: 59 bits is a fictive number and makes assumptions about processors - * in the distant future. Nobody will care for a few years :-) - */ -#ifndef HIGHMEM_START -#define HIGHMEM_START (1UL << 59UL) -#endif - -#define CAC_BASE 0x9800000000000000UL -#define IO_BASE 0x9000000000000000UL -#define UNCAC_BASE 0x9000000000000000UL -#define MAP_BASE 0xc000000000000000UL - -#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) -#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) -#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) - -/* - * This handles the memory map. - */ -#define PAGE_OFFSET CAC_BASE - -#endif /* __ASM_MACH_IP32_SPACES_H */ diff --git a/include/asm-mips/mach-jmr3927/ioremap.h b/include/asm-mips/mach-jmr3927/ioremap.h new file mode 100644 index 00000000000..aa131ad7f71 --- /dev/null +++ b/include/asm-mips/mach-jmr3927/ioremap.h @@ -0,0 +1,38 @@ +/* + * include/asm-mips/mach-jmr3927/ioremap.h + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#ifndef __ASM_MACH_JMR3927_IOREMAP_H +#define __ASM_MACH_JMR3927_IOREMAP_H + +#include <linux/types.h> + +/* + * Allow physical addresses to be fixed up to help peripherals located + * outside the low 32-bit range -- generic pass-through version. + */ +static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) +{ + return phys_addr; +} + +static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, + unsigned long flags) +{ +#define TXX9_DIRECTMAP_BASE 0xff000000ul + if (offset >= TXX9_DIRECTMAP_BASE && + offset < TXX9_DIRECTMAP_BASE + 0xf0000) + return (void __iomem *)offset; + return NULL; +} + +static inline int plat_iounmap(const volatile void __iomem *addr) +{ + return (unsigned long)addr >= TXX9_DIRECTMAP_BASE; +} + +#endif /* __ASM_MACH_JMR3927_IOREMAP_H */ diff --git a/include/asm-mips/mach-lasat/mach-gt64120.h b/include/asm-mips/mach-lasat/mach-gt64120.h deleted file mode 100644 index 1a9ad45cc13..00000000000 --- a/include/asm-mips/mach-lasat/mach-gt64120.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This is a direct copy of the ev96100.h file, with a global - * search and replace. The numbers are the same. - * - * The reason I'm duplicating this is so that the 64120/96100 - * defines won't be confusing in the source code. - */ -#ifndef _ASM_GT64120_LASAT_GT64120_DEP_H -#define _ASM_GT64120_LASAT_GT64120_DEP_H - -/* - * GT64120 config space base address on Lasat 100 - */ -#define GT64120_BASE (KSEG1ADDR(0x14000000)) - -/* - * PCI Bus allocation - * - * (Guessing ...) - */ -#define GT_PCI_MEM_BASE 0x12000000UL -#define GT_PCI_MEM_SIZE 0x02000000UL -#define GT_PCI_IO_BASE 0x10000000UL -#define GT_PCI_IO_SIZE 0x02000000UL -#define GT_ISA_IO_BASE PCI_IO_BASE - -#endif /* _ASM_GT64120_LASAT_GT64120_DEP_H */ diff --git a/include/asm-mips/mach-lemote/dma-coherence.h b/include/asm-mips/mach-lemote/dma-coherence.h new file mode 100644 index 00000000000..7e914777ebc --- /dev/null +++ b/include/asm-mips/mach-lemote/dma-coherence.h @@ -0,0 +1,42 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2006, 07 Ralf Baechle <ralf@linux-mips.org> + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + */ +#ifndef __ASM_MACH_LEMOTE_DMA_COHERENCE_H +#define __ASM_MACH_LEMOTE_DMA_COHERENCE_H + +struct device; + +static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, + size_t size) +{ + return virt_to_phys(addr) | 0x80000000; +} + +static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, + struct page *page) +{ + return page_to_phys(page) | 0x80000000; +} + +static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) +{ + return dma_addr & 0x7fffffff; +} + +static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) +{ +} + +static inline int plat_device_is_coherent(struct device *dev) +{ + return 0; +} + +#endif /* __ASM_MACH_LEMOTE_DMA_COHERENCE_H */ diff --git a/include/asm-mips/mach-lemote/mc146818rtc.h b/include/asm-mips/mach-lemote/mc146818rtc.h new file mode 100644 index 00000000000..ed5147e1108 --- /dev/null +++ b/include/asm-mips/mach-lemote/mc146818rtc.h @@ -0,0 +1,36 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1998, 2001, 03, 07 by Ralf Baechle (ralf@linux-mips.org) + * + * RTC routines for PC style attached Dallas chip. + */ +#ifndef __ASM_MACH_LEMOTE_MC146818RTC_H +#define __ASM_MACH_LEMOTE_MC146818RTC_H + +#include <linux/io.h> + +#define RTC_PORT(x) (0x70 + (x)) +#define RTC_IRQ 8 + +static inline unsigned char CMOS_READ(unsigned long addr) +{ + outb_p(addr, RTC_PORT(0)); + return inb_p(RTC_PORT(1)); +} + +static inline void CMOS_WRITE(unsigned char data, unsigned long addr) +{ + outb_p(addr, RTC_PORT(0)); + outb_p(data, RTC_PORT(1)); +} + +#define RTC_ALWAYS_BCD 0 + +#ifndef mc146818_decode_year +#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970) +#endif + +#endif /* __ASM_MACH_LEMOTE_MC146818RTC_H */ diff --git a/include/asm-mips/mach-mips/kernel-entry-init.h b/include/asm-mips/mach-mips/kernel-entry-init.h new file mode 100644 index 00000000000..0b793e7bf67 --- /dev/null +++ b/include/asm-mips/mach-mips/kernel-entry-init.h @@ -0,0 +1,52 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Chris Dearman (chris@mips.com) + * Copyright (C) 2007 Mips Technologies, Inc. + */ +#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H +#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H + + .macro kernel_entry_setup +#ifdef CONFIG_MIPS_MT_SMTC + mfc0 t0, CP0_CONFIG + bgez t0, 9f + mfc0 t0, CP0_CONFIG, 1 + bgez t0, 9f + mfc0 t0, CP0_CONFIG, 2 + bgez t0, 9f + mfc0 t0, CP0_CONFIG, 3 + and t0, 1<<2 + bnez t0, 0f +9: + /* Assume we came from YAMON... */ + PTR_LA v0, 0x9fc00534 /* YAMON print */ + lw v0, (v0) + move a0, zero + PTR_LA a1, nonmt_processor + jal v0 + + PTR_LA v0, 0x9fc00520 /* YAMON exit */ + lw v0, (v0) + li a0, 1 + jal v0 + +1: b 1b + + __INITDATA +nonmt_processor: + .asciz "SMTC kernel requires the MT ASE to run\n" + __FINIT +0: +#endif + .endm + +/* + * Do SMP slave processor setup necessary before we can safely execute C code. + */ + .macro smp_slave_setup + .endm + +#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */ diff --git a/include/asm-mips/mach-sim/cpu-feature-overrides.h b/include/asm-mips/mach-mipssim/cpu-feature-overrides.h index 779b0220573..779b0220573 100644 --- a/include/asm-mips/mach-sim/cpu-feature-overrides.h +++ b/include/asm-mips/mach-mipssim/cpu-feature-overrides.h diff --git a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h deleted file mode 100644 index 57a12ded061..00000000000 --- a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004 MontaVista Software Inc. - * Author: Manish Lachwani, mlachwani@mvista.com - * Copyright (C) 2004 Ralf Baechle - */ -#ifndef __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H - -/* - * Momentum Ocelot-3 is based on Rm7900 processor which - * is based on the E9000 core. - */ -#define cpu_has_watch 1 -#define cpu_has_mips16 0 -#define cpu_has_divec 0 -#define cpu_has_vce 0 -#define cpu_has_cache_cdex_p 0 -#define cpu_has_cache_cdex_s 0 -#define cpu_has_prefetch 1 -#define cpu_has_mcheck 0 -#define cpu_has_ejtag 0 - -#define cpu_has_llsc 1 -#define cpu_has_vtag_icache 0 -#define cpu_has_dc_aliases 0 -#define cpu_has_ic_fills_f_dc 0 -#define cpu_has_dsp 0 -#define cpu_icache_snoops_remote_store 0 - -#define cpu_has_nofpuex 0 -#define cpu_has_64bits 1 - -#define cpu_has_inclusive_pcaches 0 - -#define cpu_dcache_line_size() 32 -#define cpu_icache_line_size() 32 -#define cpu_scache_line_size() 32 - -#define cpu_has_mips32r1 0 -#define cpu_has_mips32r2 0 -#define cpu_has_mips64r1 0 -#define cpu_has_mips64r2 0 - -#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-tx49xx/ioremap.h b/include/asm-mips/mach-tx49xx/ioremap.h new file mode 100644 index 00000000000..1e7beae7222 --- /dev/null +++ b/include/asm-mips/mach-tx49xx/ioremap.h @@ -0,0 +1,43 @@ +/* + * include/asm-mips/mach-tx49xx/ioremap.h + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#ifndef __ASM_MACH_TX49XX_IOREMAP_H +#define __ASM_MACH_TX49XX_IOREMAP_H + +#include <linux/types.h> + +/* + * Allow physical addresses to be fixed up to help peripherals located + * outside the low 32-bit range -- generic pass-through version. + */ +static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) +{ + return phys_addr; +} + +static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, + unsigned long flags) +{ +#ifdef CONFIG_64BIT +#define TXX9_DIRECTMAP_BASE 0xfff000000ul +#else +#define TXX9_DIRECTMAP_BASE 0xff000000ul +#endif + if (offset >= TXX9_DIRECTMAP_BASE && + offset < TXX9_DIRECTMAP_BASE + 0x400000) + return (void __iomem *)(unsigned long)(int)offset; + return NULL; +} + +static inline int plat_iounmap(const volatile void __iomem *addr) +{ + return (unsigned long)addr >= + (unsigned long)(int)(TXX9_DIRECTMAP_BASE & 0xffffffff); +} + +#endif /* __ASM_MACH_TX49XX_IOREMAP_H */ diff --git a/include/asm-mips/mips-boards/atlasint.h b/include/asm-mips/mips-boards/atlasint.h index 76add42e486..93ba1c1b2a4 100644 --- a/include/asm-mips/mips-boards/atlasint.h +++ b/include/asm-mips/mips-boards/atlasint.h @@ -28,11 +28,6 @@ #include <irq.h> -/* - * Interrupts 0..7 are used for Atlas CPU interrupts (nonEIC mode) - */ -#define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE - /* CPU interrupt offsets */ #define MIPSCPU_INT_SW0 0 #define MIPSCPU_INT_SW1 1 @@ -42,7 +37,6 @@ #define MIPSCPU_INT_MB2 4 #define MIPSCPU_INT_MB3 5 #define MIPSCPU_INT_MB4 6 -#define MIPSCPU_INT_CPUCTR 7 /* * Interrupts 8..39 are used for Atlas interrupt controller interrupts diff --git a/include/asm-mips/mips-boards/bonito64.h b/include/asm-mips/mips-boards/bonito64.h index cd712561010..dc3fc32eedd 100644 --- a/include/asm-mips/mips-boards/bonito64.h +++ b/include/asm-mips/mips-boards/bonito64.h @@ -26,7 +26,12 @@ /* offsets from base register */ #define BONITO(x) (x) -#else /* !__ASSEMBLY__ */ +#elif defined(CONFIG_LEMOTE_FULONG) + +#define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x))) +#define BONITO_IRQ_BASE 32 + +#else /* * Algorithmics Bonito64 system controller register base. diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h index b98f1658cfd..c8ebcc3e126 100644 --- a/include/asm-mips/mips-boards/generic.h +++ b/include/asm-mips/mips-boards/generic.h @@ -73,12 +73,28 @@ * CoreEMUL with Bonito System Controller is treated like a Core20K * CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC */ -#define MIPS_REVISION_CORID_CORE_EMUL_BON 0x63 -#define MIPS_REVISION_CORID_CORE_EMUL_MSC 0x65 +#define MIPS_REVISION_CORID_CORE_EMUL_BON -1 +#define MIPS_REVISION_CORID_CORE_EMUL_MSC -2 #define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f) -extern unsigned int mips_revision_corid; +extern int mips_revision_corid; + +#define MIPS_REVISION_SCON_OTHER 0 +#define MIPS_REVISION_SCON_SOCITSC 1 +#define MIPS_REVISION_SCON_SOCITSCP 2 + +/* Artificial SCON defines for MIPS_REVISION_SCON_OTHER */ +#define MIPS_REVISION_SCON_UNKNOWN -1 +#define MIPS_REVISION_SCON_GT64120 -2 +#define MIPS_REVISION_SCON_BONITO -3 +#define MIPS_REVISION_SCON_BRTL -4 +#define MIPS_REVISION_SCON_SOCIT -5 +#define MIPS_REVISION_SCON_ROCIT -6 + +#define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff) + +extern int mips_revision_sconid; #ifdef CONFIG_PCI extern void mips_pcibios_init(void); diff --git a/include/asm-mips/mips-boards/maltaint.h b/include/asm-mips/mips-boards/maltaint.h index 9180d646611..7461318f1cd 100644 --- a/include/asm-mips/mips-boards/maltaint.h +++ b/include/asm-mips/mips-boards/maltaint.h @@ -32,11 +32,6 @@ */ #define MALTA_INT_BASE 0 -/* - * Interrupts 16..23 are used for Malta CPU interrupts (nonEIC mode) - */ -#define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE - /* CPU interrupt offsets */ #define MIPSCPU_INT_SW0 0 #define MIPSCPU_INT_SW1 1 @@ -49,7 +44,6 @@ #define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3 #define MIPSCPU_INT_MB4 6 #define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4 -#define MIPSCPU_INT_CPUCTR 7 /* * Interrupts 64..127 are used for Soc-it Classic interrupts diff --git a/include/asm-mips/mips-boards/msc01_pci.h b/include/asm-mips/mips-boards/msc01_pci.h index 8eaefb837b9..e036b7dd6de 100644 --- a/include/asm-mips/mips-boards/msc01_pci.h +++ b/include/asm-mips/mips-boards/msc01_pci.h @@ -208,6 +208,7 @@ * latter, they should be moved elsewhere. */ #define MIPS_MSC01_PCI_REG_BASE 0x1bd00000 +#define MIPS_SOCITSC_PCI_REG_BASE 0x1ff10000 extern unsigned long _pcictrl_msc; diff --git a/include/asm-mips/mips-boards/prom.h b/include/asm-mips/mips-boards/prom.h index daaf9f98fc6..a9db576a976 100644 --- a/include/asm-mips/mips-boards/prom.h +++ b/include/asm-mips/mips-boards/prom.h @@ -33,6 +33,7 @@ extern void prom_meminit(void); extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem); extern void mips_display_message(const char *str); extern void mips_display_word(unsigned int num); +extern void mips_scroll_message(void); extern int get_ethernet_addr(char *ethernet_addr); /* Memory descriptor management. */ diff --git a/include/asm-mips/mips-boards/seadint.h b/include/asm-mips/mips-boards/seadint.h index 4f6a3933699..e710bae0734 100644 --- a/include/asm-mips/mips-boards/seadint.h +++ b/include/asm-mips/mips-boards/seadint.h @@ -22,14 +22,7 @@ #include <irq.h> -/* - * Interrupts 0..7 are used for SEAD CPU interrupts - */ -#define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE - #define MIPSCPU_INT_UART0 2 #define MIPSCPU_INT_UART1 3 -#define MIPSCPU_INT_CPUCTR 7 - #endif /* !(_MIPS_SEADINT_H) */ diff --git a/include/asm-mips/mips-boards/simint.h b/include/asm-mips/mips-boards/simint.h index 54f2fe621d6..8ef6db76d5c 100644 --- a/include/asm-mips/mips-boards/simint.h +++ b/include/asm-mips/mips-boards/simint.h @@ -21,15 +21,11 @@ #define SIM_INT_BASE 0 #define MIPSCPU_INT_MB0 2 -#define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE #define MIPS_CPU_TIMER_IRQ 7 -#define MIPSCPU_INT_CPUCTR 7 - #define MSC01E_INT_BASE 64 -#define MIPSCPU_INT_CPUCTR 7 #define MSC01E_INT_CPUCTR 11 #endif diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 9985cb7c16e..18f47f1e8cd 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -7,7 +7,7 @@ * Copyright (C) 2000 Silicon Graphics, Inc. * Modified for further R[236]000 support by Paul M. Antoine, 1996. * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2000, 07 MIPS Technologies, Inc. * Copyright (C) 2003, 2004 Maciej W. Rozycki */ #ifndef _ASM_MIPSREGS_H @@ -15,6 +15,7 @@ #include <linux/linkage.h> #include <asm/hazards.h> +#include <asm/war.h> /* * The following macros are especially useful for __asm__ @@ -533,6 +534,12 @@ #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) +#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) + +#define MIPS_CONF7_WII (_ULCAST_(1) << 31) + +#define MIPS_CONF7_RPS (_ULCAST_(1) << 2) + /* * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. @@ -700,10 +707,10 @@ do { \ */ #define __read_64bit_c0_split(source, sel) \ ({ \ - unsigned long long val; \ - unsigned long flags; \ + unsigned long long __val; \ + unsigned long __flags; \ \ - local_irq_save(flags); \ + local_irq_save(__flags); \ if (sel == 0) \ __asm__ __volatile__( \ ".set\tmips64\n\t" \ @@ -712,7 +719,7 @@ do { \ "dsrl\t%M0, %M0, 32\n\t" \ "dsrl\t%L0, %L0, 32\n\t" \ ".set\tmips0" \ - : "=r" (val)); \ + : "=r" (__val)); \ else \ __asm__ __volatile__( \ ".set\tmips64\n\t" \ @@ -721,17 +728,17 @@ do { \ "dsrl\t%M0, %M0, 32\n\t" \ "dsrl\t%L0, %L0, 32\n\t" \ ".set\tmips0" \ - : "=r" (val)); \ - local_irq_restore(flags); \ + : "=r" (__val)); \ + local_irq_restore(__flags); \ \ - val; \ + __val; \ }) #define __write_64bit_c0_split(source, sel, val) \ do { \ - unsigned long flags; \ + unsigned long __flags; \ \ - local_irq_save(flags); \ + local_irq_save(__flags); \ if (sel == 0) \ __asm__ __volatile__( \ ".set\tmips64\n\t" \ @@ -752,7 +759,7 @@ do { \ "dmtc0\t%L0, " #source ", " #sel "\n\t" \ ".set\tmips0" \ : : "r" (val)); \ - local_irq_restore(flags); \ + local_irq_restore(__flags); \ } while (0) #define read_c0_index() __read_32bit_c0_register($0, 0) @@ -770,6 +777,9 @@ do { \ #define read_c0_context() __read_ulong_c0_register($4, 0) #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) +#define read_c0_userlocal() __read_ulong_c0_register($4, 2) +#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) + #define read_c0_pagemask() __read_32bit_c0_register($5, 0) #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) @@ -1292,10 +1302,39 @@ static inline void tlb_probe(void) static inline void tlb_read(void) { +#if MIPS34K_MISSED_ITLB_WAR + int res = 0; + + __asm__ __volatile__( + " .set push \n" + " .set noreorder \n" + " .set noat \n" + " .set mips32r2 \n" + " .word 0x41610001 # dvpe $1 \n" + " move %0, $1 \n" + " ehb \n" + " .set pop \n" + : "=r" (res)); + + instruction_hazard(); +#endif + __asm__ __volatile__( ".set noreorder\n\t" "tlbr\n\t" ".set reorder"); + +#if MIPS34K_MISSED_ITLB_WAR + if ((res & _ULCAST_(1))) + __asm__ __volatile__( + " .set push \n" + " .set noreorder \n" + " .set noat \n" + " .set mips32r2 \n" + " .word 0x41600021 # evpe \n" + " ehb \n" + " .set pop \n"); +#endif } static inline void tlb_write_indexed(void) diff --git a/include/asm-mips/module.h b/include/asm-mips/module.h index 399d03f1c4f..de6d09ebbd8 100644 --- a/include/asm-mips/module.h +++ b/include/asm-mips/module.h @@ -112,6 +112,8 @@ search_module_dbetables(unsigned long addr) #define MODULE_PROC_FAMILY "RM9000 " #elif defined CONFIG_CPU_SB1 #define MODULE_PROC_FAMILY "SB1 " +#elif defined CONFIG_CPU_LOONGSON2 +#define MODULE_PROC_FAMILY "LOONGSON2 " #else #error MODULE_PROC_FAMILY undefined for your processor configuration #endif @@ -122,6 +124,13 @@ search_module_dbetables(unsigned long addr) #define MODULE_KERNEL_TYPE "64BIT " #endif -#define MODULE_ARCH_VERMAGIC MODULE_PROC_FAMILY MODULE_KERNEL_TYPE +#ifdef CONFIG_MIPS_MT_SMTC +#define MODULE_KERNEL_SMTC "MT_SMTC " +#else +#define MODULE_KERNEL_SMTC "" +#endif + +#define MODULE_ARCH_VERMAGIC \ + MODULE_PROC_FAMILY MODULE_KERNEL_TYPE MODULE_KERNEL_SMTC #endif /* _ASM_MODULE_H */ diff --git a/include/asm-mips/nile4.h b/include/asm-mips/nile4.h deleted file mode 100644 index c3ca959aa4d..00000000000 --- a/include/asm-mips/nile4.h +++ /dev/null @@ -1,310 +0,0 @@ -/* - * asm-mips/nile4.h -- NEC Vrc-5074 Nile 4 definitions - * - * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> - * Sony Software Development Center Europe (SDCE), Brussels - * - * This file is based on the following documentation: - * - * NEC Vrc 5074 System Controller Data Sheet, June 1998 - */ - -#ifndef _ASM_NILE4_H -#define _ASM_NILE4_H - -#define NILE4_BASE 0xbfa00000 -#define NILE4_SIZE 0x00200000 /* 2 MB */ - - - /* - * Physical Device Address Registers (PDARs) - */ - -#define NILE4_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */ -#define NILE4_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */ -#define NILE4_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */ -#define NILE4_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */ -#define NILE4_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */ -#define NILE4_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */ -#define NILE4_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */ -#define NILE4_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */ -#define NILE4_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */ -#define NILE4_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */ -#define NILE4_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */ -#define NILE4_INTCS 0x0070 /* Controller Internal Registers and Devices */ - /* [R/W] */ -#define NILE4_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */ - - - /* - * CPU Interface Registers - */ - -#define NILE4_CPUSTAT 0x0080 /* CPU Status [R/W] */ -#define NILE4_INTCTRL 0x0088 /* Interrupt Control [R/W] */ -#define NILE4_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */ -#define NILE4_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */ - /* Enable [R/W] */ -#define NILE4_INTCLR 0x00A0 /* Interrupt Clear [R/W] */ -#define NILE4_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */ - - - /* - * Memory-Interface Registers - */ - -#define NILE4_MEMCTRL 0x00C0 /* Memory Control */ -#define NILE4_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */ -#define NILE4_CHKERR 0x00D0 /* Memory Check Error Status [R] */ - - - /* - * PCI-Bus Registers - */ - -#define NILE4_PCICTRL 0x00E0 /* PCI Control [R/W] */ -#define NILE4_PCIARB 0x00E8 /* PCI Arbiter [R/W] */ -#define NILE4_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */ -#define NILE4_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */ -#define NILE4_PCIERR 0x00B8 /* PCI Error [R/W] */ - - - /* - * Local-Bus Registers - */ - -#define NILE4_LCNFG 0x0100 /* Local Bus Configuration [R/W] */ -#define NILE4_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */ -#define NILE4_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */ -#define NILE4_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */ -#define NILE4_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */ -#define NILE4_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */ -#define NILE4_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */ -#define NILE4_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */ -#define NILE4_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */ - /* Enables [R/W] */ -#define NILE4_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */ -#define NILE4_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */ - - - /* - * DMA Registers - */ - -#define NILE4_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */ -#define NILE4_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */ -#define NILE4_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */ -#define NILE4_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */ -#define NILE4_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */ -#define NILE4_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */ - - - /* - * Timer Registers - */ - -#define NILE4_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */ -#define NILE4_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */ -#define NILE4_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */ -#define NILE4_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */ -#define NILE4_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */ -#define NILE4_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */ -#define NILE4_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */ -#define NILE4_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */ - - - /* - * PCI Configuration Space Registers - */ - -#define NILE4_PCI_BASE 0x0200 - -#define NILE4_VID 0x0200 /* PCI Vendor ID [R] */ -#define NILE4_DID 0x0202 /* PCI Device ID [R] */ -#define NILE4_PCICMD 0x0204 /* PCI Command [R/W] */ -#define NILE4_PCISTS 0x0206 /* PCI Status [R/W] */ -#define NILE4_REVID 0x0208 /* PCI Revision ID [R] */ -#define NILE4_CLASS 0x0209 /* PCI Class Code [R] */ -#define NILE4_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */ -#define NILE4_MLTIM 0x020D /* PCI Latency Timer [R/W] */ -#define NILE4_HTYPE 0x020E /* PCI Header Type [R] */ -#define NILE4_BIST 0x020F /* BIST [R] (unimplemented) */ -#define NILE4_BARC 0x0210 /* PCI Base Address Register Control [R/W] */ -#define NILE4_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */ -#define NILE4_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */ -#define NILE4_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */ - /* (unimplemented) */ -#define NILE4_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */ -#define NILE4_SSID 0x022E /* PCI Sub-System ID [R/W] */ -#define NILE4_ROM 0x0230 /* Expansion ROM Base Address [R] */ - /* (unimplemented) */ -#define NILE4_INTLIN 0x023C /* PCI Interrupt Line [R/W] */ -#define NILE4_INTPIN 0x023D /* PCI Interrupt Pin [R] */ -#define NILE4_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */ -#define NILE4_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */ -#define NILE4_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */ -#define NILE4_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */ -#define NILE4_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */ -#define NILE4_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */ -#define NILE4_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */ -#define NILE4_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */ -#define NILE4_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */ -#define NILE4_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */ - - - /* - * Serial-Port Registers - */ - -#define NILE4_UART_BASE 0x0300 - -#define NILE4_UARTRBR 0x0300 /* UART Receiver Data Buffer [R] */ -#define NILE4_UARTTHR 0x0300 /* UART Transmitter Data Holding [W] */ -#define NILE4_UARTIER 0x0308 /* UART Interrupt Enable [R/W] */ -#define NILE4_UARTDLL 0x0300 /* UART Divisor Latch LSB [R/W] */ -#define NILE4_UARTDLM 0x0308 /* UART Divisor Latch MSB [R/W] */ -#define NILE4_UARTIIR 0x0310 /* UART Interrupt ID [R] */ -#define NILE4_UARTFCR 0x0310 /* UART FIFO Control [W] */ -#define NILE4_UARTLCR 0x0318 /* UART Line Control [R/W] */ -#define NILE4_UARTMCR 0x0320 /* UART Modem Control [R/W] */ -#define NILE4_UARTLSR 0x0328 /* UART Line Status [R/W] */ -#define NILE4_UARTMSR 0x0330 /* UART Modem Status [R/W] */ -#define NILE4_UARTSCR 0x0338 /* UART Scratch [R/W] */ - -#define NILE4_UART_BASE_BAUD 520833 /* 100 MHz / 12 / 16 */ - - - /* - * Interrupt Lines - */ - -#define NILE4_INT_CPCE 0 /* CPU-Interface Parity-Error Interrupt */ -#define NILE4_INT_CNTD 1 /* CPU No-Target Decode Interrupt */ -#define NILE4_INT_MCE 2 /* Memory-Check Error Interrupt */ -#define NILE4_INT_DMA 3 /* DMA Controller Interrupt */ -#define NILE4_INT_UART 4 /* UART Interrupt */ -#define NILE4_INT_WDOG 5 /* Watchdog Timer Interrupt */ -#define NILE4_INT_GPT 6 /* General-Purpose Timer Interrupt */ -#define NILE4_INT_LBRTD 7 /* Local-Bus Ready Timer Interrupt */ -#define NILE4_INT_INTA 8 /* PCI Interrupt Signal INTA# */ -#define NILE4_INT_INTB 9 /* PCI Interrupt Signal INTB# */ -#define NILE4_INT_INTC 10 /* PCI Interrupt Signal INTC# */ -#define NILE4_INT_INTD 11 /* PCI Interrupt Signal INTD# */ -#define NILE4_INT_INTE 12 /* PCI Interrupt Signal INTE# (ISA cascade) */ -#define NILE4_INT_RESV 13 /* Reserved */ -#define NILE4_INT_PCIS 14 /* PCI SERR# Interrupt */ -#define NILE4_INT_PCIE 15 /* PCI Internal Error Interrupt */ - - - /* - * Nile 4 Register Access - */ - -static inline void nile4_sync(void) -{ - volatile u32 *p = (volatile u32 *)0xbfc00000; - (void)(*p); -} - -static inline void nile4_out32(u32 offset, u32 val) -{ - *(volatile u32 *)(NILE4_BASE+offset) = val; - nile4_sync(); -} - -static inline u32 nile4_in32(u32 offset) -{ - u32 val = *(volatile u32 *)(NILE4_BASE+offset); - nile4_sync(); - return val; -} - -static inline void nile4_out16(u32 offset, u16 val) -{ - *(volatile u16 *)(NILE4_BASE+offset) = val; - nile4_sync(); -} - -static inline u16 nile4_in16(u32 offset) -{ - u16 val = *(volatile u16 *)(NILE4_BASE+offset); - nile4_sync(); - return val; -} - -static inline void nile4_out8(u32 offset, u8 val) -{ - *(volatile u8 *)(NILE4_BASE+offset) = val; - nile4_sync(); -} - -static inline u8 nile4_in8(u32 offset) -{ - u8 val = *(volatile u8 *)(NILE4_BASE+offset); - nile4_sync(); - return val; -} - - - /* - * Physical Device Address Registers - */ - -extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width, - int on_memory_bus, int visible); - - - /* - * PCI Master Registers - */ - -#define NILE4_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */ -#define NILE4_PCICMD_IO 1 /* PCI I/O Space */ -#define NILE4_PCICMD_MEM 3 /* PCI Memory Space */ -#define NILE4_PCICMD_CFG 5 /* PCI Configuration Space */ - - - /* - * PCI Address Spaces - * - * Note that these are multiplexed using PCIINIT[01]! - */ - -#define NILE4_PCI_IO_BASE 0xa6000000 -#define NILE4_PCI_MEM_BASE 0xa8000000 -#define NILE4_PCI_CFG_BASE NILE4_PCI_MEM_BASE -#define NILE4_PCI_IACK_BASE NILE4_PCI_IO_BASE - - -extern void nile4_set_pmr(u32 pmr, u32 type, u32 addr); - - - /* - * Interrupt Programming - */ - -#define NUM_I8259_INTERRUPTS 16 -#define NUM_NILE4_INTERRUPTS 16 - -#define IRQ_I8259_CASCADE NILE4_INT_INTE -#define is_i8259_irq(irq) ((irq) < NUM_I8259_INTERRUPTS) -#define nile4_to_irq(n) ((n)+NUM_I8259_INTERRUPTS) -#define irq_to_nile4(n) ((n)-NUM_I8259_INTERRUPTS) - -extern void nile4_map_irq(int nile4_irq, int cpu_irq); -extern void nile4_map_irq_all(int cpu_irq); -extern void nile4_enable_irq(unsigned int nile4_irq); -extern void nile4_disable_irq(unsigned int nile4_irq); -extern void nile4_disable_irq_all(void); -extern u16 nile4_get_irq_stat(int cpu_irq); -extern void nile4_enable_irq_output(int cpu_irq); -extern void nile4_disable_irq_output(int cpu_irq); -extern void nile4_set_pci_irq_polarity(int pci_irq, int high); -extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level); -extern void nile4_clear_irq(int nile4_irq); -extern void nile4_clear_irq_mask(u32 mask); -extern u8 nile4_i8259_iack(void); -extern void nile4_dump_irq_status(void); /* Debug */ - -#endif - diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h index 5c3239dad0f..b92dd8c760d 100644 --- a/include/asm-mips/page.h +++ b/include/asm-mips/page.h @@ -34,12 +34,8 @@ #ifndef __ASSEMBLY__ -/* - * This gives the physical RAM offset. - */ -#ifndef PHYS_OFFSET -#define PHYS_OFFSET 0UL -#endif +#include <linux/pfn.h> +#include <asm/io.h> /* * It's normally defined only for FLATMEM config but it's @@ -48,9 +44,6 @@ */ #define ARCH_PFN_OFFSET PFN_UP(PHYS_OFFSET) -#include <linux/pfn.h> -#include <asm/io.h> - extern void clear_page(void * page); extern void copy_page(void * to, void * from); @@ -150,11 +143,15 @@ typedef struct { unsigned long pgprot; } pgprot_t; * __pa()/__va() should be used only during mem init. */ #if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64) -#define __pa_page_offset(x) ((unsigned long)(x) < CKSEG0 ? PAGE_OFFSET : CKSEG0) +#define __pa(x) \ +({ \ + unsigned long __x = (unsigned long)(x); \ + __x < CKSEG0 ? XPHYSADDR(__x) : CPHYSADDR(__x); \ +}) #else -#define __pa_page_offset(x) PAGE_OFFSET +#define __pa(x) \ + ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET) #endif -#define __pa(x) ((unsigned long)(x) - __pa_page_offset(x) + PHYS_OFFSET) #define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET)) #define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x),0)) diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h index 3eea3ba0fca..4fcc185cb2d 100644 --- a/include/asm-mips/pci.h +++ b/include/asm-mips/pci.h @@ -56,7 +56,7 @@ extern void register_pci_controller(struct pci_controller *hose); /* * board supplied pci irq fixup routine */ -extern int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin); +extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); /* Can be used to override the logic in pci_scan_bus for skipping @@ -121,20 +121,6 @@ extern unsigned int PCI_DMA_BUS_IS_PHYS; #endif /* CONFIG_DMA_NEED_PCI_MAP_STATE */ -/* This is always fine. */ -#define pci_dac_dma_supported(pci_dev, mask) (1) - -extern dma64_addr_t pci_dac_page_to_dma(struct pci_dev *pdev, - struct page *page, unsigned long offset, int direction); -extern struct page *pci_dac_dma_to_page(struct pci_dev *pdev, - dma64_addr_t dma_addr); -extern unsigned long pci_dac_dma_to_offset(struct pci_dev *pdev, - dma64_addr_t dma_addr); -extern void pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev, - dma64_addr_t dma_addr, size_t len, int direction); -extern void pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, - dma64_addr_t dma_addr, size_t len, int direction); - #ifdef CONFIG_PCI static inline void pci_dma_burst_advice(struct pci_dev *pdev, enum pci_dma_burst_strategy *strat, @@ -181,10 +167,6 @@ static inline int pci_proc_domain(struct pci_bus *bus) /* implement the pci_ DMA API in terms of the generic device dma_ one */ #include <asm-generic/pci-dma-compat.h> -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - /* Do platform specific device initialization at pci_enable_device() time */ extern int pcibios_plat_dev_init(struct pci_dev *dev); diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h b/include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h new file mode 100644 index 00000000000..c84bcf9570b --- /dev/null +++ b/include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h @@ -0,0 +1,151 @@ +/* + * Defines for the MSP interrupt controller. + * + * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved. + * Author: Carsten Langgaard, carstenl@mips.com + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + */ + +#ifndef _MSP_CIC_INT_H +#define _MSP_CIC_INT_H + +/* + * The PMC-Sierra CIC interrupts are all centrally managed by the + * CIC sub-system. + * We attempt to keep the interrupt numbers as consistent as possible + * across all of the MSP devices, but some differences will creep in ... + * The interrupts which are directly forwarded to the MIPS core interrupts + * are assigned interrupts in the range 0-7, interrupts cascaded through + * the CIC are assigned interrupts 8-39. The cascade occurs on C_IRQ4 + * (MSP_INT_CIC). Currently we don't really distinguish between VPE1 + * and VPE0 (or thread contexts for that matter). Will have to fix. + * The PER interrupts are assigned interrupts in the range 40-71. +*/ + + +/* + * IRQs directly forwarded to the CPU + */ +#define MSP_MIPS_INTBASE 0 +#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */ +#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */ +#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */ +#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */ +#define MSP_INT_USB 4 /* IRQ for USB, C_IRQ2 */ +#define MSP_INT_SAR 5 /* IRQ for ADSL2+ SAR, C_IRQ3 */ +#define MSP_INT_CIC 6 /* IRQ for CIC block, C_IRQ4 */ +#define MSP_INT_SEC 7 /* IRQ for Sec engine, C_IRQ5 */ + +/* + * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4) + * These defines should be tied to the register definitions for the CIC + * interrupt routine. For now, just use hard-coded values. + */ +#define MSP_CIC_INTBASE (MSP_MIPS_INTBASE + 8) +#define MSP_INT_EXT0 (MSP_CIC_INTBASE + 0) + /* External interrupt 0 */ +#define MSP_INT_EXT1 (MSP_CIC_INTBASE + 1) + /* External interrupt 1 */ +#define MSP_INT_EXT2 (MSP_CIC_INTBASE + 2) + /* External interrupt 2 */ +#define MSP_INT_EXT3 (MSP_CIC_INTBASE + 3) + /* External interrupt 3 */ +#define MSP_INT_CPUIF (MSP_CIC_INTBASE + 4) + /* CPU interface interrupt */ +#define MSP_INT_EXT4 (MSP_CIC_INTBASE + 5) + /* External interrupt 4 */ +#define MSP_INT_CIC_USB (MSP_CIC_INTBASE + 6) + /* Cascaded IRQ for USB */ +#define MSP_INT_MBOX (MSP_CIC_INTBASE + 7) + /* Sec engine mailbox IRQ */ +#define MSP_INT_EXT5 (MSP_CIC_INTBASE + 8) + /* External interrupt 5 */ +#define MSP_INT_TDM (MSP_CIC_INTBASE + 9) + /* TDM interrupt */ +#define MSP_INT_CIC_MAC0 (MSP_CIC_INTBASE + 10) + /* Cascaded IRQ for MAC 0 */ +#define MSP_INT_CIC_MAC1 (MSP_CIC_INTBASE + 11) + /* Cascaded IRQ for MAC 1 */ +#define MSP_INT_CIC_SEC (MSP_CIC_INTBASE + 12) + /* Cascaded IRQ for sec engine */ +#define MSP_INT_PER (MSP_CIC_INTBASE + 13) + /* Peripheral interrupt */ +#define MSP_INT_TIMER0 (MSP_CIC_INTBASE + 14) + /* SLP timer 0 */ +#define MSP_INT_TIMER1 (MSP_CIC_INTBASE + 15) + /* SLP timer 1 */ +#define MSP_INT_TIMER2 (MSP_CIC_INTBASE + 16) + /* SLP timer 2 */ +#define MSP_INT_VPE0_TIMER (MSP_CIC_INTBASE + 17) + /* VPE0 MIPS timer */ +#define MSP_INT_BLKCP (MSP_CIC_INTBASE + 18) + /* Block Copy */ +#define MSP_INT_UART0 (MSP_CIC_INTBASE + 19) + /* UART 0 */ +#define MSP_INT_PCI (MSP_CIC_INTBASE + 20) + /* PCI subsystem */ +#define MSP_INT_EXT6 (MSP_CIC_INTBASE + 21) + /* External interrupt 5 */ +#define MSP_INT_PCI_MSI (MSP_CIC_INTBASE + 22) + /* PCI Message Signal */ +#define MSP_INT_CIC_SAR (MSP_CIC_INTBASE + 23) + /* Cascaded ADSL2+ SAR IRQ */ +#define MSP_INT_DSL (MSP_CIC_INTBASE + 24) + /* ADSL2+ IRQ */ +#define MSP_INT_CIC_ERR (MSP_CIC_INTBASE + 25) + /* SLP error condition */ +#define MSP_INT_VPE1_TIMER (MSP_CIC_INTBASE + 26) + /* VPE1 MIPS timer */ +#define MSP_INT_VPE0_PC (MSP_CIC_INTBASE + 27) + /* VPE0 Performance counter */ +#define MSP_INT_VPE1_PC (MSP_CIC_INTBASE + 28) + /* VPE1 Performance counter */ +#define MSP_INT_EXT7 (MSP_CIC_INTBASE + 29) + /* External interrupt 5 */ +#define MSP_INT_VPE0_SW (MSP_CIC_INTBASE + 30) + /* VPE0 Software interrupt */ +#define MSP_INT_VPE1_SW (MSP_CIC_INTBASE + 31) + /* VPE0 Software interrupt */ + +/* + * IRQs cascaded on CIC PER interrupt (MSP_INT_PER) + */ +#define MSP_PER_INTBASE (MSP_CIC_INTBASE + 32) +/* Reserved 0-1 */ +#define MSP_INT_UART1 (MSP_PER_INTBASE + 2) + /* UART 1 */ +/* Reserved 3-5 */ +#define MSP_INT_2WIRE (MSP_PER_INTBASE + 6) + /* 2-wire */ +#define MSP_INT_TM0 (MSP_PER_INTBASE + 7) + /* Peripheral timer block out 0 */ +#define MSP_INT_TM1 (MSP_PER_INTBASE + 8) + /* Peripheral timer block out 1 */ +/* Reserved 9 */ +#define MSP_INT_SPRX (MSP_PER_INTBASE + 10) + /* SPI RX complete */ +#define MSP_INT_SPTX (MSP_PER_INTBASE + 11) + /* SPI TX complete */ +#define MSP_INT_GPIO (MSP_PER_INTBASE + 12) + /* GPIO */ +#define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13) + /* Peripheral error */ +/* Reserved 14-31 */ + +#endif /* !_MSP_CIC_INT_H */ diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_int.h b/include/asm-mips/pmc-sierra/msp71xx/msp_int.h new file mode 100644 index 00000000000..1d9f0547482 --- /dev/null +++ b/include/asm-mips/pmc-sierra/msp71xx/msp_int.h @@ -0,0 +1,43 @@ +/* + * Defines for the MSP interrupt handlers. + * + * Copyright (C) 2005, PMC-Sierra, Inc. All rights reserved. + * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + */ + +#ifndef _MSP_INT_H +#define _MSP_INT_H + +/* + * The PMC-Sierra MSP product line has at least two different interrupt + * controllers, the SLP register based scheme and the CIC interrupt + * controller block mechanism. This file distinguishes between them + * so that devices see a uniform interface. + */ + +#if defined(CONFIG_IRQ_MSP_SLP) + #include "msp_slp_int.h" +#elif defined(CONFIG_IRQ_MSP_CIC) + #include "msp_cic_int.h" +#else + #error "What sort of interrupt controller does *your* MSP have?" +#endif + +#endif /* !_MSP_INT_H */ diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_pci.h b/include/asm-mips/pmc-sierra/msp71xx/msp_pci.h new file mode 100644 index 00000000000..41560690361 --- /dev/null +++ b/include/asm-mips/pmc-sierra/msp71xx/msp_pci.h @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2000-2006 PMC-Sierra INC. + * + * This program is free software; you can redistribute it + * and/or modify it under the terms of the GNU General + * Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be + * useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR + * PURPOSE. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write to the Free + * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA + * 02139, USA. + * + * PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS + * SOFTWARE. + */ + +#ifndef _MSP_PCI_H_ +#define _MSP_PCI_H_ + +#define MSP_HAS_PCI(ID) (((u32)(ID) <= 0x4236) && ((u32)(ID) >= 0x4220)) + +/* + * It is convenient to program the OATRAN register so that + * Athena virtual address space and PCI address space are + * the same. This is not a requirement, just a convenience. + * + * The only hard restrictions on the value of OATRAN is that + * OATRAN must not be programmed to allow translated memory + * addresses to fall within the lowest 512MB of + * PCI address space. This region is hardcoded + * for use as Athena PCI Host Controller target + * access memory space to the Athena's SDRAM. + * + * Note that OATRAN applies only to memory accesses, not + * to I/O accesses. + * + * To program OATRAN to make Athena virtual address space + * and PCI address space have the same values, OATRAN + * is to be programmed to 0xB8000000. The top seven + * bits of the value mimic the seven bits clipped off + * by the PCI Host controller. + * + * With OATRAN at the said value, when the CPU does + * an access to its virtual address at, say 0xB900_5000, + * the address appearing on the PCI bus will be + * 0xB900_5000. + * - Michael Penner + */ +#define MSP_PCI_OATRAN 0xB8000000UL + +#define MSP_PCI_SPACE_BASE (MSP_PCI_OATRAN + 0x1002000UL) +#define MSP_PCI_SPACE_SIZE (0x3000000UL - 0x2000) +#define MSP_PCI_SPACE_END \ + (MSP_PCI_SPACE_BASE + MSP_PCI_SPACE_SIZE - 1) +#define MSP_PCI_IOSPACE_BASE (MSP_PCI_OATRAN + 0x1001000UL) +#define MSP_PCI_IOSPACE_SIZE 0x1000 +#define MSP_PCI_IOSPACE_END \ + (MSP_PCI_IOSPACE_BASE + MSP_PCI_IOSPACE_SIZE - 1) + +/* IRQ for PCI status interrupts */ +#define PCI_STAT_IRQ 20 + +#define QFLUSH_REG_1 0xB7F40000 + +typedef volatile unsigned int pcireg; +typedef void * volatile ppcireg; + +struct pci_block_copy +{ + pcireg unused1; /* +0x00 */ + pcireg unused2; /* +0x04 */ + ppcireg unused3; /* +0x08 */ + ppcireg unused4; /* +0x0C */ + pcireg unused5; /* +0x10 */ + pcireg unused6; /* +0x14 */ + pcireg unused7; /* +0x18 */ + ppcireg unused8; /* +0x1C */ + ppcireg unused9; /* +0x20 */ + pcireg unusedA; /* +0x24 */ + ppcireg unusedB; /* +0x28 */ + ppcireg unusedC; /* +0x2C */ +}; + +enum +{ + config_device_vendor, /* 0 */ + config_status_command, /* 1 */ + config_class_revision, /* 2 */ + config_BIST_header_latency_cache, /* 3 */ + config_BAR0, /* 4 */ + config_BAR1, /* 5 */ + config_BAR2, /* 6 */ + config_not_used7, /* 7 */ + config_not_used8, /* 8 */ + config_not_used9, /* 9 */ + config_CIS, /* 10 */ + config_subsystem, /* 11 */ + config_not_used12, /* 12 */ + config_capabilities, /* 13 */ + config_not_used14, /* 14 */ + config_lat_grant_irq, /* 15 */ + config_message_control,/* 16 */ + config_message_addr, /* 17 */ + config_message_data, /* 18 */ + config_VPD_addr, /* 19 */ + config_VPD_data, /* 20 */ + config_maxregs /* 21 - number of registers */ +}; + +struct msp_pci_regs +{ + pcireg hop_unused_00; /* +0x00 */ + pcireg hop_unused_04; /* +0x04 */ + pcireg hop_unused_08; /* +0x08 */ + pcireg hop_unused_0C; /* +0x0C */ + pcireg hop_unused_10; /* +0x10 */ + pcireg hop_unused_14; /* +0x14 */ + pcireg hop_unused_18; /* +0x18 */ + pcireg hop_unused_1C; /* +0x1C */ + pcireg hop_unused_20; /* +0x20 */ + pcireg hop_unused_24; /* +0x24 */ + pcireg hop_unused_28; /* +0x28 */ + pcireg hop_unused_2C; /* +0x2C */ + pcireg hop_unused_30; /* +0x30 */ + pcireg hop_unused_34; /* +0x34 */ + pcireg if_control; /* +0x38 */ + pcireg oatran; /* +0x3C */ + pcireg reset_ctl; /* +0x40 */ + pcireg config_addr; /* +0x44 */ + pcireg hop_unused_48; /* +0x48 */ + pcireg msg_signaled_int_status; /* +0x4C */ + pcireg msg_signaled_int_mask; /* +0x50 */ + pcireg if_status; /* +0x54 */ + pcireg if_mask; /* +0x58 */ + pcireg hop_unused_5C; /* +0x5C */ + pcireg hop_unused_60; /* +0x60 */ + pcireg hop_unused_64; /* +0x64 */ + pcireg hop_unused_68; /* +0x68 */ + pcireg hop_unused_6C; /* +0x6C */ + pcireg hop_unused_70; /* +0x70 */ + + struct pci_block_copy pci_bc[2] __attribute__((aligned(64))); + + pcireg error_hdr1; /* +0xE0 */ + pcireg error_hdr2; /* +0xE4 */ + + pcireg config[config_maxregs] __attribute__((aligned(256))); + +}; + +#define BPCI_CFGADDR_BUSNUM_SHF 16 +#define BPCI_CFGADDR_FUNCTNUM_SHF 8 +#define BPCI_CFGADDR_REGNUM_SHF 2 +#define BPCI_CFGADDR_ENABLE (1<<31) + +#define BPCI_IFCONTROL_RTO (1<<20) /* Retry timeout */ +#define BPCI_IFCONTROL_HCE (1<<16) /* Host configuration enable */ +#define BPCI_IFCONTROL_CTO_SHF 12 /* Shift count for CTO bits */ +#define BPCI_IFCONTROL_SE (1<<5) /* Enable exceptions on errors */ +#define BPCI_IFCONTROL_BIST (1<<4) /* Use BIST in per. mode */ +#define BPCI_IFCONTROL_CAP (1<<3) /* Enable capabilities */ +#define BPCI_IFCONTROL_MMC_SHF 0 /* Shift count for MMC bits */ + +#define BPCI_IFSTATUS_MGT (1<<8) /* Master Grant timeout */ +#define BPCI_IFSTATUS_MTT (1<<9) /* Master TRDY timeout */ +#define BPCI_IFSTATUS_MRT (1<<10) /* Master retry timeout */ +#define BPCI_IFSTATUS_BC0F (1<<13) /* Block copy 0 fault */ +#define BPCI_IFSTATUS_BC1F (1<<14) /* Block copy 1 fault */ +#define BPCI_IFSTATUS_PCIU (1<<15) /* PCI unable to respond */ +#define BPCI_IFSTATUS_BSIZ (1<<16) /* PCI access with illegal size */ +#define BPCI_IFSTATUS_BADD (1<<17) /* PCI access with illegal addr */ +#define BPCI_IFSTATUS_RTO (1<<18) /* Retry time out */ +#define BPCI_IFSTATUS_SER (1<<19) /* System error */ +#define BPCI_IFSTATUS_PER (1<<20) /* Parity error */ +#define BPCI_IFSTATUS_LCA (1<<21) /* Local CPU abort */ +#define BPCI_IFSTATUS_MEM (1<<22) /* Memory prot. violation */ +#define BPCI_IFSTATUS_ARB (1<<23) /* Arbiter timed out */ +#define BPCI_IFSTATUS_STA (1<<27) /* Signaled target abort */ +#define BPCI_IFSTATUS_TA (1<<28) /* Target abort */ +#define BPCI_IFSTATUS_MA (1<<29) /* Master abort */ +#define BPCI_IFSTATUS_PEI (1<<30) /* Parity error as initiator */ +#define BPCI_IFSTATUS_PET (1<<31) /* Parity error as target */ + +#define BPCI_RESETCTL_PR (1<<0) /* True if reset asserted */ +#define BPCI_RESETCTL_RT (1<<4) /* Release time */ +#define BPCI_RESETCTL_CT (1<<8) /* Config time */ +#define BPCI_RESETCTL_PE (1<<12) /* PCI enabled */ +#define BPCI_RESETCTL_HM (1<<13) /* PCI host mode */ +#define BPCI_RESETCTL_RI (1<<14) /* PCI reset in */ + +extern struct msp_pci_regs msp_pci_regs + __attribute__((section(".register"))); +extern unsigned long msp_pci_config_space + __attribute__((section(".register"))); + +#endif /* !_MSP_PCI_H_ */ diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_prom.h b/include/asm-mips/pmc-sierra/msp71xx/msp_prom.h new file mode 100644 index 00000000000..14ca7dc382a --- /dev/null +++ b/include/asm-mips/pmc-sierra/msp71xx/msp_prom.h @@ -0,0 +1,176 @@ +/* + * MIPS boards bootprom interface for the Linux kernel. + * + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * Author: Carsten Langgaard, carstenl@mips.com + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + */ + +#ifndef _ASM_MSP_PROM_H +#define _ASM_MSP_PROM_H + +#include <linux/types.h> + +#define DEVICEID "deviceid" +#define FEATURES "features" +#define PROM_ENV "prom_env" +#define PROM_ENV_FILE "/proc/"PROM_ENV +#define PROM_ENV_SIZE 256 + +#define CPU_DEVID_FAMILY 0x0000ff00 +#define CPU_DEVID_REVISION 0x000000ff + +#define FPGA_IS_POLO(revision) \ + (((revision >= 0xb0) && (revision < 0xd0))) +#define FPGA_IS_5000(revision) \ + ((revision >= 0x80) && (revision <= 0x90)) +#define FPGA_IS_ZEUS(revision) ((revision < 0x7f)) +#define FPGA_IS_DUET(revision) \ + (((revision >= 0xa0) && (revision < 0xb0))) +#define FPGA_IS_MSP4200(revision) ((revision >= 0xd0)) +#define FPGA_IS_MSP7100(revision) ((revision >= 0xd0)) + +#define MACHINE_TYPE_POLO "POLO" +#define MACHINE_TYPE_DUET "DUET" +#define MACHINE_TYPE_ZEUS "ZEUS" +#define MACHINE_TYPE_MSP2000REVB "MSP2000REVB" +#define MACHINE_TYPE_MSP5000 "MSP5000" +#define MACHINE_TYPE_MSP4200 "MSP4200" +#define MACHINE_TYPE_MSP7120 "MSP7120" +#define MACHINE_TYPE_MSP7130 "MSP7130" +#define MACHINE_TYPE_OTHER "OTHER" + +#define MACHINE_TYPE_POLO_FPGA "POLO-FPGA" +#define MACHINE_TYPE_DUET_FPGA "DUET-FPGA" +#define MACHINE_TYPE_ZEUS_FPGA "ZEUS_FPGA" +#define MACHINE_TYPE_MSP2000REVB_FPGA "MSP2000REVB-FPGA" +#define MACHINE_TYPE_MSP5000_FPGA "MSP5000-FPGA" +#define MACHINE_TYPE_MSP4200_FPGA "MSP4200-FPGA" +#define MACHINE_TYPE_MSP7100_FPGA "MSP7100-FPGA" +#define MACHINE_TYPE_OTHER_FPGA "OTHER-FPGA" + +/* Device Family definitions */ +#define FAMILY_FPGA 0x0000 +#define FAMILY_ZEUS 0x1000 +#define FAMILY_POLO 0x2000 +#define FAMILY_DUET 0x4000 +#define FAMILY_TRIAD 0x5000 +#define FAMILY_MSP4200 0x4200 +#define FAMILY_MSP4200_FPGA 0x4f00 +#define FAMILY_MSP7100 0x7100 +#define FAMILY_MSP7100_FPGA 0x7f00 + +/* Device Type definitions */ +#define TYPE_MSP7120 0x7120 +#define TYPE_MSP7130 0x7130 + +#define ENET_KEY 'E' +#define ENETTXD_KEY 'e' +#define PCI_KEY 'P' +#define PCIMUX_KEY 'p' +#define SEC_KEY 'S' +#define SPAD_KEY 'D' +#define TDM_KEY 'T' +#define ZSP_KEY 'Z' + +#define FEATURE_NOEXIST '-' +#define FEATURE_EXIST '+' + +#define ENET_MII 'M' +#define ENET_RMII 'R' + +#define ENETTXD_FALLING 'F' +#define ENETTXD_RISING 'R' + +#define PCI_HOST 'H' +#define PCI_PERIPHERAL 'P' + +#define PCIMUX_FULL 'F' +#define PCIMUX_SINGLE 'S' + +#define SEC_DUET 'D' +#define SEC_POLO 'P' +#define SEC_SLOW 'S' +#define SEC_TRIAD 'T' + +#define SPAD_POLO 'P' + +#define TDM_DUET 'D' /* DUET TDMs might exist */ +#define TDM_POLO 'P' /* POLO TDMs might exist */ +#define TDM_TRIAD 'T' /* TRIAD TDMs might exist */ + +#define ZSP_DUET 'D' /* one DUET zsp engine */ +#define ZSP_TRIAD 'T' /* two TRIAD zsp engines */ + +extern char *prom_getcmdline(void); +extern char *prom_getenv(char *name); +extern void prom_init_cmdline(void); +extern void prom_meminit(void); +extern void prom_fixup_mem_map(unsigned long start_mem, + unsigned long end_mem); + +#ifdef CONFIG_MTD_PMC_MSP_RAMROOT +extern bool get_ramroot(void **start, unsigned long *size); +#endif + +extern int get_ethernet_addr(char *ethaddr_name, char *ethernet_addr); +extern unsigned long get_deviceid(void); +extern char identify_enet(unsigned long interface_num); +extern char identify_enetTxD(unsigned long interface_num); +extern char identify_pci(void); +extern char identify_sec(void); +extern char identify_spad(void); +extern char identify_sec(void); +extern char identify_tdm(void); +extern char identify_zsp(void); +extern unsigned long identify_family(void); +extern unsigned long identify_revision(void); + +/* + * The following macro calls prom_printf and puts the format string + * into an init section so it can be reclaimed. + */ +#define ppfinit(f, x...) \ + do { \ + static char _f[] __initdata = KERN_INFO f; \ + printk(_f, ## x); \ + } while (0) + +/* Memory descriptor management. */ +#define PROM_MAX_PMEMBLOCKS 7 /* 6 used */ + +enum yamon_memtypes { + yamon_dontuse, + yamon_prom, + yamon_free, +}; + +struct prom_pmemblock { + unsigned long base; /* Within KSEG0. */ + unsigned int size; /* In bytes. */ + unsigned int type; /* free or prom memory */ +}; + +extern int prom_argc; +extern char **prom_argv; +extern char **prom_envp; +extern int *prom_vec; +extern struct prom_pmemblock *prom_getmdesc(void); + +#endif /* !_ASM_MSP_PROM_H */ diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_regops.h b/include/asm-mips/pmc-sierra/msp71xx/msp_regops.h new file mode 100644 index 00000000000..60a5a38dd5b --- /dev/null +++ b/include/asm-mips/pmc-sierra/msp71xx/msp_regops.h @@ -0,0 +1,236 @@ +/* + * SMP/VPE-safe functions to access "registers" (see note). + * + * NOTES: +* - These macros use ll/sc instructions, so it is your responsibility to + * ensure these are available on your platform before including this file. + * - The MIPS32 spec states that ll/sc results are undefined for uncached + * accesses. This means they can't be used on HW registers accessed + * through kseg1. Code which requires these macros for this purpose must + * front-end the registers with cached memory "registers" and have a single + * thread update the actual HW registers. + * - A maximum of 2k of code can be inserted between ll and sc. Every + * memory accesses between the instructions will increase the chance of + * sc failing and having to loop. + * - When using custom_read_reg32/custom_write_reg32 only perform the + * necessary logical operations on the register value in between these + * two calls. All other logic should be performed before the first call. + * - There is a bug on the R10000 chips which has a workaround. If you + * are affected by this bug, make sure to define the symbol 'R10000_LLSC_WAR' + * to be non-zero. If you are using this header from within linux, you may + * include <asm/war.h> before including this file to have this defined + * appropriately for you. + * + * Copyright 2005-2007 PMC-Sierra, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., 675 + * Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_REGOPS_H__ +#define __ASM_REGOPS_H__ + +#include <linux/types.h> + +#include <asm/war.h> + +#ifndef R10000_LLSC_WAR +#define R10000_LLSC_WAR 0 +#endif + +#if R10000_LLSC_WAR == 1 +#define __beqz "beqzl " +#else +#define __beqz "beqz " +#endif + +#ifndef _LINUX_TYPES_H +typedef unsigned int u32; +#endif + +/* + * Sets all the masked bits to the corresponding value bits + */ +static inline void set_value_reg32(volatile u32 *const addr, + u32 const mask, + u32 const value) +{ + u32 temp; + + __asm__ __volatile__( + " .set push \n" + " .set mips3 \n" + "1: ll %0, %1 # set_value_reg32 \n" + " and %0, %2 \n" + " or %0, %3 \n" + " sc %0, %1 \n" + " "__beqz"%0, 1b \n" + " nop \n" + " .set pop \n" + : "=&r" (temp), "=m" (*addr) + : "ir" (~mask), "ir" (value), "m" (*addr)); +} + +/* + * Sets all the masked bits to '1' + */ +static inline void set_reg32(volatile u32 *const addr, + u32 const mask) +{ + u32 temp; + + __asm__ __volatile__( + " .set push \n" + " .set mips3 \n" + "1: ll %0, %1 # set_reg32 \n" + " or %0, %2 \n" + " sc %0, %1 \n" + " "__beqz"%0, 1b \n" + " nop \n" + " .set pop \n" + : "=&r" (temp), "=m" (*addr) + : "ir" (mask), "m" (*addr)); +} + +/* + * Sets all the masked bits to '0' + */ +static inline void clear_reg32(volatile u32 *const addr, + u32 const mask) +{ + u32 temp; + + __asm__ __volatile__( + " .set push \n" + " .set mips3 \n" + "1: ll %0, %1 # clear_reg32 \n" + " and %0, %2 \n" + " sc %0, %1 \n" + " "__beqz"%0, 1b \n" + " nop \n" + " .set pop \n" + : "=&r" (temp), "=m" (*addr) + : "ir" (~mask), "m" (*addr)); +} + +/* + * Toggles all masked bits from '0' to '1' and '1' to '0' + */ +static inline void toggle_reg32(volatile u32 *const addr, + u32 const mask) +{ + u32 temp; + + __asm__ __volatile__( + " .set push \n" + " .set mips3 \n" + "1: ll %0, %1 # toggle_reg32 \n" + " xor %0, %2 \n" + " sc %0, %1 \n" + " "__beqz"%0, 1b \n" + " nop \n" + " .set pop \n" + : "=&r" (temp), "=m" (*addr) + : "ir" (mask), "m" (*addr)); +} + +/* + * Read all masked bits others are returned as '0' + */ +static inline u32 read_reg32(volatile u32 *const addr, + u32 const mask) +{ + u32 temp; + + __asm__ __volatile__( + " .set push \n" + " .set noreorder \n" + " lw %0, %1 # read \n" + " and %0, %2 # mask \n" + " .set pop \n" + : "=&r" (temp) + : "m" (*addr), "ir" (mask)); + + return temp; +} + +/* + * blocking_read_reg32 - Read address with blocking load + * + * Uncached writes need to be read back to ensure they reach RAM. + * The returned value must be 'used' to prevent from becoming a + * non-blocking load. + */ +static inline u32 blocking_read_reg32(volatile u32 *const addr) +{ + u32 temp; + + __asm__ __volatile__( + " .set push \n" + " .set noreorder \n" + " lw %0, %1 # read \n" + " move %0, %0 # block \n" + " .set pop \n" + : "=&r" (temp) + : "m" (*addr)); + + return temp; +} + +/* + * For special strange cases only: + * + * If you need custom processing within a ll/sc loop, use the following macros + * VERY CAREFULLY: + * + * u32 tmp; <-- Define a variable to hold the data + * + * custom_read_reg32(address, tmp); <-- Reads the address and put the value + * in the 'tmp' variable given + * + * From here on out, you are (basicly) atomic, so don't do anything too + * fancy! + * Also, this code may loop if the end of this block fails to write + * everything back safely due do the other CPU, so do NOT do anything + * with side-effects! + * + * custom_write_reg32(address, tmp); <-- Writes back 'tmp' safely. + */ +#define custom_read_reg32(address, tmp) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set mips3 \n" \ + "1: ll %0, %1 #custom_read_reg32 \n" \ + " .set pop \n" \ + : "=r" (tmp), "=m" (*address) \ + : "m" (*address)) + +#define custom_write_reg32(address, tmp) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set mips3 \n" \ + " sc %0, %1 #custom_write_reg32 \n" \ + " "__beqz"%0, 1b \n" \ + " nop \n" \ + " .set pop \n" \ + : "=&r" (tmp), "=m" (*address) \ + : "0" (tmp), "m" (*address)) + +#endif /* __ASM_REGOPS_H__ */ diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h b/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h new file mode 100644 index 00000000000..0b56f55206c --- /dev/null +++ b/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h @@ -0,0 +1,667 @@ +/* + * Defines for the address space, registers and register configuration + * (bit masks, access macros etc) for the PMC-Sierra line of MSP products. + * This file contains addess maps for all the devices in the line of + * products but only has register definitions and configuration masks for + * registers which aren't definitely associated with any device. Things + * like clock settings, reset access, the ELB etc. Individual device + * drivers will reference the appropriate XXX_BASE value defined here + * and have individual registers offset from that. + * + * Copyright (C) 2005-2007 PMC-Sierra, Inc. All rights reserved. + * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + */ + +#include <asm/addrspace.h> +#include <linux/types.h> + +#ifndef _ASM_MSP_REGS_H +#define _ASM_MSP_REGS_H + +/* + ######################################################################## + # Address space and device base definitions # + ######################################################################## + */ + +/* + *************************************************************************** + * System Logic and Peripherals (ELB, UART0, etc) device address space * + *************************************************************************** + */ +#define MSP_SLP_BASE 0x1c000000 + /* System Logic and Peripherals */ +#define MSP_RST_BASE (MSP_SLP_BASE + 0x10) + /* System reset register base */ +#define MSP_RST_SIZE 0x0C /* System reset register space */ + +#define MSP_WTIMER_BASE (MSP_SLP_BASE + 0x04C) + /* watchdog timer base */ +#define MSP_ITIMER_BASE (MSP_SLP_BASE + 0x054) + /* internal timer base */ +#define MSP_UART0_BASE (MSP_SLP_BASE + 0x100) + /* UART0 controller base */ +#define MSP_BCPY_CTRL_BASE (MSP_SLP_BASE + 0x120) + /* Block Copy controller base */ +#define MSP_BCPY_DESC_BASE (MSP_SLP_BASE + 0x160) + /* Block Copy descriptor base */ + +/* + *************************************************************************** + * PCI address space * + *************************************************************************** + */ +#define MSP_PCI_BASE 0x19000000 + +/* + *************************************************************************** + * MSbus device address space * + *************************************************************************** + */ +#define MSP_MSB_BASE 0x18000000 + /* MSbus address start */ +#define MSP_PER_BASE (MSP_MSB_BASE + 0x400000) + /* Peripheral device registers */ +#define MSP_MAC0_BASE (MSP_MSB_BASE + 0x600000) + /* MAC A device registers */ +#define MSP_MAC1_BASE (MSP_MSB_BASE + 0x700000) + /* MAC B device registers */ +#define MSP_MAC_SIZE 0xE0 /* MAC register space */ + +#define MSP_SEC_BASE (MSP_MSB_BASE + 0x800000) + /* Security Engine registers */ +#define MSP_MAC2_BASE (MSP_MSB_BASE + 0x900000) + /* MAC C device registers */ +#define MSP_ADSL2_BASE (MSP_MSB_BASE + 0xA80000) + /* ADSL2 device registers */ +#define MSP_USB_BASE (MSP_MSB_BASE + 0xB40000) + /* USB device registers */ +#define MSP_USB_BASE_START (MSP_MSB_BASE + 0xB40100) + /* USB device registers */ +#define MSP_USB_BASE_END (MSP_MSB_BASE + 0xB401FF) + /* USB device registers */ +#define MSP_CPUIF_BASE (MSP_MSB_BASE + 0xC00000) + /* CPU interface registers */ + +/* Devices within the MSbus peripheral block */ +#define MSP_UART1_BASE (MSP_PER_BASE + 0x030) + /* UART1 controller base */ +#define MSP_SPI_BASE (MSP_PER_BASE + 0x058) + /* SPI/MPI control registers */ +#define MSP_TWI_BASE (MSP_PER_BASE + 0x090) + /* Two-wire control registers */ +#define MSP_PTIMER_BASE (MSP_PER_BASE + 0x0F0) + /* Programmable timer control */ + +/* + *************************************************************************** + * Physical Memory configuration address space * + *************************************************************************** + */ +#define MSP_MEM_CFG_BASE 0x17f00000 + +#define MSP_MEM_INDIRECT_CTL_10 0x10 + +/* + * Notes: + * 1) The SPI registers are split into two blocks, one offset from the + * MSP_SPI_BASE by 0x00 and the other offset from the MSP_SPI_BASE by + * 0x68. The SPI driver definitions for the register must be aware + * of this. + * 2) The block copy engine register are divided into two regions, one + * for the control/configuration of the engine proper and one for the + * values of the descriptors used in the copy process. These have + * different base defines (CTRL_BASE vs DESC_BASE) + * 3) These constants are for physical addresses which means that they + * work correctly with "ioremap" and friends. This means that device + * drivers will need to remap these addresses using ioremap and perhaps + * the readw/writew macros. Or they could use the regptr() macro + * defined below, but the readw/writew calls are the correct thing. + * 4) The UARTs have an additional status register offset from the base + * address. This register isn't used in the standard 8250 driver but + * may be used in other software. Consult the hardware datasheet for + * offset details. + * 5) For some unknown reason the security engine (MSP_SEC_BASE) registers + * start at an offset of 0x84 from the base address but the block of + * registers before this is reserved for the security engine. The + * driver will have to be aware of this but it makes the register + * definitions line up better with the documentation. + */ + +/* + ######################################################################## + # System register definitions. Not associated with a specific device # + ######################################################################## + */ + +/* + * This macro maps the physical register number into uncached space + * and (for C code) casts it into a u32 pointer so it can be dereferenced + * Normally these would be accessed with ioremap and readX/writeX, but + * these are convenient for a lot of internal kernel code. + */ +#ifdef __ASSEMBLER__ + #define regptr(addr) (KSEG1ADDR(addr)) +#else + #define regptr(addr) ((volatile u32 *const)(KSEG1ADDR(addr))) +#endif + +/* + *************************************************************************** + * System Logic and Peripherals (RESET, ELB, etc) registers * + *************************************************************************** + */ + +/* System Control register definitions */ +#define DEV_ID_REG regptr(MSP_SLP_BASE + 0x00) + /* Device-ID RO */ +#define FWR_ID_REG regptr(MSP_SLP_BASE + 0x04) + /* Firmware-ID Register RW */ +#define SYS_ID_REG0 regptr(MSP_SLP_BASE + 0x08) + /* System-ID Register-0 RW */ +#define SYS_ID_REG1 regptr(MSP_SLP_BASE + 0x0C) + /* System-ID Register-1 RW */ + +/* System Reset register definitions */ +#define RST_STS_REG regptr(MSP_SLP_BASE + 0x10) + /* System Reset Status RO */ +#define RST_SET_REG regptr(MSP_SLP_BASE + 0x14) + /* System Set Reset WO */ +#define RST_CLR_REG regptr(MSP_SLP_BASE + 0x18) + /* System Clear Reset WO */ + +/* System Clock Registers */ +#define PCI_SLP_REG regptr(MSP_SLP_BASE + 0x1C) + /* PCI clock generator RW */ +#define URT_SLP_REG regptr(MSP_SLP_BASE + 0x20) + /* UART clock generator RW */ +/* reserved (MSP_SLP_BASE + 0x24) */ +/* reserved (MSP_SLP_BASE + 0x28) */ +#define PLL1_SLP_REG regptr(MSP_SLP_BASE + 0x2C) + /* PLL1 clock generator RW */ +#define PLL0_SLP_REG regptr(MSP_SLP_BASE + 0x30) + /* PLL0 clock generator RW */ +#define MIPS_SLP_REG regptr(MSP_SLP_BASE + 0x34) + /* MIPS clock generator RW */ +#define VE_SLP_REG regptr(MSP_SLP_BASE + 0x38) + /* Voice Eng clock generator RW */ +/* reserved (MSP_SLP_BASE + 0x3C) */ +#define MSB_SLP_REG regptr(MSP_SLP_BASE + 0x40) + /* MS-Bus clock generator RW */ +#define SMAC_SLP_REG regptr(MSP_SLP_BASE + 0x44) + /* Sec & MAC clock generator RW */ +#define PERF_SLP_REG regptr(MSP_SLP_BASE + 0x48) + /* Per & TDM clock generator RW */ + +/* Interrupt Controller Registers */ +#define SLP_INT_STS_REG regptr(MSP_SLP_BASE + 0x70) + /* Interrupt status register RW */ +#define SLP_INT_MSK_REG regptr(MSP_SLP_BASE + 0x74) + /* Interrupt enable/mask RW */ +#define SE_MBOX_REG regptr(MSP_SLP_BASE + 0x78) + /* Security Engine mailbox RW */ +#define VE_MBOX_REG regptr(MSP_SLP_BASE + 0x7C) + /* Voice Engine mailbox RW */ + +/* ELB Controller Registers */ +#define CS0_CNFG_REG regptr(MSP_SLP_BASE + 0x80) + /* ELB CS0 Configuration Reg */ +#define CS0_ADDR_REG regptr(MSP_SLP_BASE + 0x84) + /* ELB CS0 Base Address Reg */ +#define CS0_MASK_REG regptr(MSP_SLP_BASE + 0x88) + /* ELB CS0 Mask Register */ +#define CS0_ACCESS_REG regptr(MSP_SLP_BASE + 0x8C) + /* ELB CS0 access register */ + +#define CS1_CNFG_REG regptr(MSP_SLP_BASE + 0x90) + /* ELB CS1 Configuration Reg */ +#define CS1_ADDR_REG regptr(MSP_SLP_BASE + 0x94) + /* ELB CS1 Base Address Reg */ +#define CS1_MASK_REG regptr(MSP_SLP_BASE + 0x98) + /* ELB CS1 Mask Register */ +#define CS1_ACCESS_REG regptr(MSP_SLP_BASE + 0x9C) + /* ELB CS1 access register */ + +#define CS2_CNFG_REG regptr(MSP_SLP_BASE + 0xA0) + /* ELB CS2 Configuration Reg */ +#define CS2_ADDR_REG regptr(MSP_SLP_BASE + 0xA4) + /* ELB CS2 Base Address Reg */ +#define CS2_MASK_REG regptr(MSP_SLP_BASE + 0xA8) + /* ELB CS2 Mask Register */ +#define CS2_ACCESS_REG regptr(MSP_SLP_BASE + 0xAC) + /* ELB CS2 access register */ + +#define CS3_CNFG_REG regptr(MSP_SLP_BASE + 0xB0) + /* ELB CS3 Configuration Reg */ +#define CS3_ADDR_REG regptr(MSP_SLP_BASE + 0xB4) + /* ELB CS3 Base Address Reg */ +#define CS3_MASK_REG regptr(MSP_SLP_BASE + 0xB8) + /* ELB CS3 Mask Register */ +#define CS3_ACCESS_REG regptr(MSP_SLP_BASE + 0xBC) + /* ELB CS3 access register */ + +#define CS4_CNFG_REG regptr(MSP_SLP_BASE + 0xC0) + /* ELB CS4 Configuration Reg */ +#define CS4_ADDR_REG regptr(MSP_SLP_BASE + 0xC4) + /* ELB CS4 Base Address Reg */ +#define CS4_MASK_REG regptr(MSP_SLP_BASE + 0xC8) + /* ELB CS4 Mask Register */ +#define CS4_ACCESS_REG regptr(MSP_SLP_BASE + 0xCC) + /* ELB CS4 access register */ + +#define CS5_CNFG_REG regptr(MSP_SLP_BASE + 0xD0) + /* ELB CS5 Configuration Reg */ +#define CS5_ADDR_REG regptr(MSP_SLP_BASE + 0xD4) + /* ELB CS5 Base Address Reg */ +#define CS5_MASK_REG regptr(MSP_SLP_BASE + 0xD8) + /* ELB CS5 Mask Register */ +#define CS5_ACCESS_REG regptr(MSP_SLP_BASE + 0xDC) + /* ELB CS5 access register */ + +/* reserved 0xE0 - 0xE8 */ +#define ELB_1PC_EN_REG regptr(MSP_SLP_BASE + 0xEC) + /* ELB single PC card detect */ + +/* reserved 0xF0 - 0xF8 */ +#define ELB_CLK_CFG_REG regptr(MSP_SLP_BASE + 0xFC) + /* SDRAM read/ELB timing Reg */ + +/* Extended UART status registers */ +#define UART0_STATUS_REG regptr(MSP_UART0_BASE + 0x0c0) + /* UART Status Register 0 */ +#define UART1_STATUS_REG regptr(MSP_UART1_BASE + 0x170) + /* UART Status Register 1 */ + +/* Performance monitoring registers */ +#define PERF_MON_CTRL_REG regptr(MSP_SLP_BASE + 0x140) + /* Performance monitor control */ +#define PERF_MON_CLR_REG regptr(MSP_SLP_BASE + 0x144) + /* Performance monitor clear */ +#define PERF_MON_CNTH_REG regptr(MSP_SLP_BASE + 0x148) + /* Perf monitor counter high */ +#define PERF_MON_CNTL_REG regptr(MSP_SLP_BASE + 0x14C) + /* Perf monitor counter low */ + +/* System control registers */ +#define SYS_CTRL_REG regptr(MSP_SLP_BASE + 0x150) + /* System control register */ +#define SYS_ERR1_REG regptr(MSP_SLP_BASE + 0x154) + /* System Error status 1 */ +#define SYS_ERR2_REG regptr(MSP_SLP_BASE + 0x158) + /* System Error status 2 */ +#define SYS_INT_CFG_REG regptr(MSP_SLP_BASE + 0x15C) + /* System Interrupt config */ + +/* Voice Engine Memory configuration */ +#define VE_MEM_REG regptr(MSP_SLP_BASE + 0x17C) + /* Voice engine memory config */ + +/* CPU/SLP Error Status registers */ +#define CPU_ERR1_REG regptr(MSP_SLP_BASE + 0x180) + /* CPU/SLP Error status 1 */ +#define CPU_ERR2_REG regptr(MSP_SLP_BASE + 0x184) + /* CPU/SLP Error status 1 */ + +#define EXTENDED_GPIO_REG regptr(MSP_SLP_BASE + 0x188) + /* Extended GPIO register */ + +/* System Error registers */ +#define SLP_ERR_STS_REG regptr(MSP_SLP_BASE + 0x190) + /* Int status for SLP errors */ +#define SLP_ERR_MSK_REG regptr(MSP_SLP_BASE + 0x194) + /* Int mask for SLP errors */ +#define SLP_ELB_ERST_REG regptr(MSP_SLP_BASE + 0x198) + /* External ELB reset */ +#define SLP_BOOT_STS_REG regptr(MSP_SLP_BASE + 0x19C) + /* Boot Status */ + +/* Extended ELB addressing */ +#define CS0_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A0) + /* CS0 Extended address */ +#define CS1_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A4) + /* CS1 Extended address */ +#define CS2_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A8) + /* CS2 Extended address */ +#define CS3_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1AC) + /* CS3 Extended address */ +/* reserved 0x1B0 */ +#define CS5_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1B4) + /* CS5 Extended address */ + +/* PLL Adjustment registers */ +#define PLL_LOCK_REG regptr(MSP_SLP_BASE + 0x200) + /* PLL0 lock status */ +#define PLL_ARST_REG regptr(MSP_SLP_BASE + 0x204) + /* PLL Analog reset status */ +#define PLL0_ADJ_REG regptr(MSP_SLP_BASE + 0x208) + /* PLL0 Adjustment value */ +#define PLL1_ADJ_REG regptr(MSP_SLP_BASE + 0x20C) + /* PLL1 Adjustment value */ + +/* + *************************************************************************** + * Peripheral Register definitions * + *************************************************************************** + */ + +/* Peripheral status */ +#define PER_CTRL_REG regptr(MSP_PER_BASE + 0x50) + /* Peripheral control register */ +#define PER_STS_REG regptr(MSP_PER_BASE + 0x54) + /* Peripheral status register */ + +/* SPI/MPI Registers */ +#define SMPI_TX_SZ_REG regptr(MSP_PER_BASE + 0x58) + /* SPI/MPI Tx Size register */ +#define SMPI_RX_SZ_REG regptr(MSP_PER_BASE + 0x5C) + /* SPI/MPI Rx Size register */ +#define SMPI_CTL_REG regptr(MSP_PER_BASE + 0x60) + /* SPI/MPI Control register */ +#define SMPI_MS_REG regptr(MSP_PER_BASE + 0x64) + /* SPI/MPI Chip Select reg */ +#define SMPI_CORE_DATA_REG regptr(MSP_PER_BASE + 0xC0) + /* SPI/MPI Core Data reg */ +#define SMPI_CORE_CTRL_REG regptr(MSP_PER_BASE + 0xC4) + /* SPI/MPI Core Control reg */ +#define SMPI_CORE_STAT_REG regptr(MSP_PER_BASE + 0xC8) + /* SPI/MPI Core Status reg */ +#define SMPI_CORE_SSEL_REG regptr(MSP_PER_BASE + 0xCC) + /* SPI/MPI Core Ssel reg */ +#define SMPI_FIFO_REG regptr(MSP_PER_BASE + 0xD0) + /* SPI/MPI Data FIFO reg */ + +/* Peripheral Block Error Registers */ +#define PER_ERR_STS_REG regptr(MSP_PER_BASE + 0x70) + /* Error Bit Status Register */ +#define PER_ERR_MSK_REG regptr(MSP_PER_BASE + 0x74) + /* Error Bit Mask Register */ +#define PER_HDR1_REG regptr(MSP_PER_BASE + 0x78) + /* Error Header 1 Register */ +#define PER_HDR2_REG regptr(MSP_PER_BASE + 0x7C) + /* Error Header 2 Register */ + +/* Peripheral Block Interrupt Registers */ +#define PER_INT_STS_REG regptr(MSP_PER_BASE + 0x80) + /* Interrupt status register */ +#define PER_INT_MSK_REG regptr(MSP_PER_BASE + 0x84) + /* Interrupt Mask Register */ +#define GPIO_INT_STS_REG regptr(MSP_PER_BASE + 0x88) + /* GPIO interrupt status reg */ +#define GPIO_INT_MSK_REG regptr(MSP_PER_BASE + 0x8C) + /* GPIO interrupt MASK Reg */ + +/* POLO GPIO registers */ +#define POLO_GPIO_DAT1_REG regptr(MSP_PER_BASE + 0x0E0) + /* Polo GPIO[8:0] data reg */ +#define POLO_GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x0E4) + /* Polo GPIO[7:0] config reg */ +#define POLO_GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x0E8) + /* Polo GPIO[15:8] config reg */ +#define POLO_GPIO_OD1_REG regptr(MSP_PER_BASE + 0x0EC) + /* Polo GPIO[31:0] output drive */ +#define POLO_GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x170) + /* Polo GPIO[23:16] config reg */ +#define POLO_GPIO_DAT2_REG regptr(MSP_PER_BASE + 0x174) + /* Polo GPIO[15:9] data reg */ +#define POLO_GPIO_DAT3_REG regptr(MSP_PER_BASE + 0x178) + /* Polo GPIO[23:16] data reg */ +#define POLO_GPIO_DAT4_REG regptr(MSP_PER_BASE + 0x17C) + /* Polo GPIO[31:24] data reg */ +#define POLO_GPIO_DAT5_REG regptr(MSP_PER_BASE + 0x180) + /* Polo GPIO[39:32] data reg */ +#define POLO_GPIO_DAT6_REG regptr(MSP_PER_BASE + 0x184) + /* Polo GPIO[47:40] data reg */ +#define POLO_GPIO_DAT7_REG regptr(MSP_PER_BASE + 0x188) + /* Polo GPIO[54:48] data reg */ +#define POLO_GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C) + /* Polo GPIO[31:24] config reg */ +#define POLO_GPIO_CFG5_REG regptr(MSP_PER_BASE + 0x190) + /* Polo GPIO[39:32] config reg */ +#define POLO_GPIO_CFG6_REG regptr(MSP_PER_BASE + 0x194) + /* Polo GPIO[47:40] config reg */ +#define POLO_GPIO_CFG7_REG regptr(MSP_PER_BASE + 0x198) + /* Polo GPIO[54:48] config reg */ +#define POLO_GPIO_OD2_REG regptr(MSP_PER_BASE + 0x19C) + /* Polo GPIO[54:32] output drive */ + +/* Generic GPIO registers */ +#define GPIO_DATA1_REG regptr(MSP_PER_BASE + 0x170) + /* GPIO[1:0] data register */ +#define GPIO_DATA2_REG regptr(MSP_PER_BASE + 0x174) + /* GPIO[5:2] data register */ +#define GPIO_DATA3_REG regptr(MSP_PER_BASE + 0x178) + /* GPIO[9:6] data register */ +#define GPIO_DATA4_REG regptr(MSP_PER_BASE + 0x17C) + /* GPIO[15:10] data register */ +#define GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x180) + /* GPIO[1:0] config register */ +#define GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x184) + /* GPIO[5:2] config register */ +#define GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x188) + /* GPIO[9:6] config register */ +#define GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C) + /* GPIO[15:10] config register */ +#define GPIO_OD_REG regptr(MSP_PER_BASE + 0x190) + /* GPIO[15:0] output drive */ + +/* + *************************************************************************** + * CPU Interface register definitions * + *************************************************************************** + */ +#define PCI_FLUSH_REG regptr(MSP_CPUIF_BASE + 0x00) + /* PCI-SDRAM queue flush trigger */ +#define OCP_ERR1_REG regptr(MSP_CPUIF_BASE + 0x04) + /* OCP Error Attribute 1 */ +#define OCP_ERR2_REG regptr(MSP_CPUIF_BASE + 0x08) + /* OCP Error Attribute 2 */ +#define OCP_STS_REG regptr(MSP_CPUIF_BASE + 0x0C) + /* OCP Error Status */ +#define CPUIF_PM_REG regptr(MSP_CPUIF_BASE + 0x10) + /* CPU policy configuration */ +#define CPUIF_CFG_REG regptr(MSP_CPUIF_BASE + 0x10) + /* Misc configuration options */ + +/* Central Interrupt Controller Registers */ +#define MSP_CIC_BASE (MSP_CPUIF_BASE + 0x8000) + /* Central Interrupt registers */ +#define CIC_EXT_CFG_REG regptr(MSP_CIC_BASE + 0x00) + /* External interrupt config */ +#define CIC_STS_REG regptr(MSP_CIC_BASE + 0x04) + /* CIC Interrupt Status */ +#define CIC_VPE0_MSK_REG regptr(MSP_CIC_BASE + 0x08) + /* VPE0 Interrupt Mask */ +#define CIC_VPE1_MSK_REG regptr(MSP_CIC_BASE + 0x0C) + /* VPE1 Interrupt Mask */ +#define CIC_TC0_MSK_REG regptr(MSP_CIC_BASE + 0x10) + /* Thread Context 0 Int Mask */ +#define CIC_TC1_MSK_REG regptr(MSP_CIC_BASE + 0x14) + /* Thread Context 1 Int Mask */ +#define CIC_TC2_MSK_REG regptr(MSP_CIC_BASE + 0x18) + /* Thread Context 2 Int Mask */ +#define CIC_TC3_MSK_REG regptr(MSP_CIC_BASE + 0x18) + /* Thread Context 3 Int Mask */ +#define CIC_TC4_MSK_REG regptr(MSP_CIC_BASE + 0x18) + /* Thread Context 4 Int Mask */ +#define CIC_PCIMSI_STS_REG regptr(MSP_CIC_BASE + 0x18) +#define CIC_PCIMSI_MSK_REG regptr(MSP_CIC_BASE + 0x18) +#define CIC_PCIFLSH_REG regptr(MSP_CIC_BASE + 0x18) +#define CIC_VPE0_SWINT_REG regptr(MSP_CIC_BASE + 0x08) + + +/* + *************************************************************************** + * Memory controller registers * + *************************************************************************** + */ +#define MEM_CFG1_REG regptr(MSP_MEM_CFG_BASE + 0x00) +#define MEM_SS_ADDR regptr(MSP_MEM_CFG_BASE + 0x00) +#define MEM_SS_DATA regptr(MSP_MEM_CFG_BASE + 0x04) +#define MEM_SS_WRITE regptr(MSP_MEM_CFG_BASE + 0x08) + +/* + *************************************************************************** + * PCI controller registers * + *************************************************************************** + */ +#define PCI_BASE_REG regptr(MSP_PCI_BASE + 0x00) +#define PCI_CONFIG_SPACE_REG regptr(MSP_PCI_BASE + 0x800) +#define PCI_JTAG_DEVID_REG regptr(MSP_SLP_BASE + 0x13c) + +/* + ######################################################################## + # Register content & macro definitions # + ######################################################################## + */ + +/* + *************************************************************************** + * DEV_ID defines * + *************************************************************************** + */ +#define DEV_ID_PCI_DIS (1 << 26) /* Set if PCI disabled */ +#define DEV_ID_PCI_HOST (1 << 20) /* Set if PCI host */ +#define DEV_ID_SINGLE_PC (1 << 19) /* Set if single PC Card */ +#define DEV_ID_FAMILY (0xff << 8) /* family ID code */ +#define POLO_ZEUS_SUB_FAMILY (0x7 << 16) /* sub family for Polo/Zeus */ + +#define MSPFPGA_ID (0x00 << 8) /* you are on your own here */ +#define MSP5000_ID (0x50 << 8) +#define MSP4F00_ID (0x4f << 8) /* FPGA version of MSP4200 */ +#define MSP4E00_ID (0x4f << 8) /* FPGA version of MSP7120 */ +#define MSP4200_ID (0x42 << 8) +#define MSP4000_ID (0x40 << 8) +#define MSP2XXX_ID (0x20 << 8) +#define MSPZEUS_ID (0x10 << 8) + +#define MSP2004_SUB_ID (0x0 << 16) +#define MSP2005_SUB_ID (0x1 << 16) +#define MSP2006_SUB_ID (0x1 << 16) +#define MSP2007_SUB_ID (0x2 << 16) +#define MSP2010_SUB_ID (0x3 << 16) +#define MSP2015_SUB_ID (0x4 << 16) +#define MSP2020_SUB_ID (0x5 << 16) +#define MSP2100_SUB_ID (0x6 << 16) + +/* + *************************************************************************** + * RESET defines * + *************************************************************************** + */ +#define MSP_GR_RST (0x01 << 0) /* Global reset bit */ +#define MSP_MR_RST (0x01 << 1) /* MIPS reset bit */ +#define MSP_PD_RST (0x01 << 2) /* PVC DMA reset bit */ +#define MSP_PP_RST (0x01 << 3) /* PVC reset bit */ +/* reserved */ +#define MSP_EA_RST (0x01 << 6) /* Mac A reset bit */ +#define MSP_EB_RST (0x01 << 7) /* Mac B reset bit */ +#define MSP_SE_RST (0x01 << 8) /* Security Eng reset bit */ +#define MSP_PB_RST (0x01 << 9) /* Per block reset bit */ +#define MSP_EC_RST (0x01 << 10) /* Mac C reset bit */ +#define MSP_TW_RST (0x01 << 11) /* TWI reset bit */ +#define MSP_SPI_RST (0x01 << 12) /* SPI/MPI reset bit */ +#define MSP_U1_RST (0x01 << 13) /* UART1 reset bit */ +#define MSP_U0_RST (0x01 << 14) /* UART0 reset bit */ + +/* + *************************************************************************** + * UART defines * + *************************************************************************** + */ +#ifndef CONFIG_MSP_FPGA +#define MSP_BASE_BAUD 25000000 +#else +#define MSP_BASE_BAUD 6000000 +#endif +#define MSP_UART_REG_LEN 0x20 + +/* + *************************************************************************** + * ELB defines * + *************************************************************************** + */ +#define PCCARD_32 0x02 /* Set if is PCCARD 32 (Cardbus) */ +#define SINGLE_PCCARD 0x01 /* Set to enable single PC card */ + +/* + *************************************************************************** + * CIC defines * + *************************************************************************** + */ + +/* CIC_EXT_CFG_REG */ +#define EXT_INT_POL(eirq) (1 << (eirq + 8)) +#define EXT_INT_EDGE(eirq) (1 << eirq) + +#define CIC_EXT_SET_TRIGGER_LEVEL(reg, eirq) (reg &= ~EXT_INT_EDGE(eirq)) +#define CIC_EXT_SET_TRIGGER_EDGE(reg, eirq) (reg |= EXT_INT_EDGE(eirq)) +#define CIC_EXT_SET_ACTIVE_HI(reg, eirq) (reg |= EXT_INT_POL(eirq)) +#define CIC_EXT_SET_ACTIVE_LO(reg, eirq) (reg &= ~EXT_INT_POL(eirq)) +#define CIC_EXT_SET_ACTIVE_RISING CIC_EXT_SET_ACTIVE_HI +#define CIC_EXT_SET_ACTIVE_FALLING CIC_EXT_SET_ACTIVE_LO + +#define CIC_EXT_IS_TRIGGER_LEVEL(reg, eirq) \ + ((reg & EXT_INT_EDGE(eirq)) == 0) +#define CIC_EXT_IS_TRIGGER_EDGE(reg, eirq) (reg & EXT_INT_EDGE(eirq)) +#define CIC_EXT_IS_ACTIVE_HI(reg, eirq) (reg & EXT_INT_POL(eirq)) +#define CIC_EXT_IS_ACTIVE_LO(reg, eirq) \ + ((reg & EXT_INT_POL(eirq)) == 0) +#define CIC_EXT_IS_ACTIVE_RISING CIC_EXT_IS_ACTIVE_HI +#define CIC_EXT_IS_ACTIVE_FALLING CIC_EXT_IS_ACTIVE_LO + +/* + *************************************************************************** + * Memory Controller defines * + *************************************************************************** + */ + +/* Indirect memory controller registers */ +#define DDRC_CFG(n) (n) +#define DDRC_DEBUG(n) (0x04 + n) +#define DDRC_CTL(n) (0x40 + n) + +/* Macro to perform DDRC indirect write */ +#define DDRC_INDIRECT_WRITE(reg, mask, value) \ +({ \ + *MEM_SS_ADDR = (((mask) & 0xf) << 8) | ((reg) & 0xff); \ + *MEM_SS_DATA = (value); \ + *MEM_SS_WRITE = 1; \ +}) + +/* + *************************************************************************** + * SPI/MPI Mode * + *************************************************************************** + */ +#define SPI_MPI_RX_BUSY 0x00008000 /* SPI/MPI Receive Busy */ +#define SPI_MPI_FIFO_EMPTY 0x00004000 /* SPI/MPI Fifo Empty */ +#define SPI_MPI_TX_BUSY 0x00002000 /* SPI/MPI Transmit Busy */ +#define SPI_MPI_FIFO_FULL 0x00001000 /* SPI/MPU FIFO full */ + +/* + *************************************************************************** + * SPI/MPI Control Register * + *************************************************************************** + */ +#define SPI_MPI_RX_START 0x00000004 /* Start receive command */ +#define SPI_MPI_FLUSH_Q 0x00000002 /* Flush SPI/MPI Queue */ +#define SPI_MPI_TX_START 0x00000001 /* Start Transmit Command */ + +#endif /* !_ASM_MSP_REGS_H */ diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h b/include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h new file mode 100644 index 00000000000..96d4c8ce8c8 --- /dev/null +++ b/include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h @@ -0,0 +1,141 @@ +/* + * Defines for the MSP interrupt controller. + * + * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved. + * Author: Carsten Langgaard, carstenl@mips.com + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + */ + +#ifndef _MSP_SLP_INT_H +#define _MSP_SLP_INT_H + +/* + * The PMC-Sierra SLP interrupts are arranged in a 3 level cascaded + * hierarchical system. The first level are the direct MIPS interrupts + * and are assigned the interrupt range 0-7. The second level is the SLM + * interrupt controller and is assigned the range 8-39. The third level + * comprises the Peripherial block, the PCI block, the PCI MSI block and + * the SLP. The PCI interrupts and the SLP errors are handled by the + * relevant subsystems so the core interrupt code needs only concern + * itself with the Peripheral block. These are assigned interrupts in + * the range 40-71. + */ + +/* + * IRQs directly connected to CPU + */ +#define MSP_MIPS_INTBASE 0 +#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */ +#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */ +#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */ +#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */ +#define MSP_INT_C_IRQ2 4 /* Wired off, C_IRQ2 */ +#define MSP_INT_VE 5 /* IRQ for Voice Engine, C_IRQ3 */ +#define MSP_INT_SLP 6 /* IRQ for SLM block, C_IRQ4 */ +#define MSP_INT_TIMER 7 /* IRQ for the MIPS timer, C_IRQ5 */ + +/* + * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4) + * These defines should be tied to the register definition for the SLM + * interrupt routine. For now, just use hard-coded values. + */ +#define MSP_SLP_INTBASE (MSP_MIPS_INTBASE + 8) +#define MSP_INT_EXT0 (MSP_SLP_INTBASE + 0) + /* External interrupt 0 */ +#define MSP_INT_EXT1 (MSP_SLP_INTBASE + 1) + /* External interrupt 1 */ +#define MSP_INT_EXT2 (MSP_SLP_INTBASE + 2) + /* External interrupt 2 */ +#define MSP_INT_EXT3 (MSP_SLP_INTBASE + 3) + /* External interrupt 3 */ +/* Reserved 4-7 */ + +/* + ************************************************************************* + * DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER * + * Some MSP produces have this interrupt labelled as Voice and some are * + * SEC mbox ... * + ************************************************************************* + */ +#define MSP_INT_SLP_VE (MSP_SLP_INTBASE + 8) + /* Cascaded IRQ for Voice Engine*/ +#define MSP_INT_SLP_TDM (MSP_SLP_INTBASE + 9) + /* TDM interrupt */ +#define MSP_INT_SLP_MAC0 (MSP_SLP_INTBASE + 10) + /* Cascaded IRQ for MAC 0 */ +#define MSP_INT_SLP_MAC1 (MSP_SLP_INTBASE + 11) + /* Cascaded IRQ for MAC 1 */ +#define MSP_INT_SEC (MSP_SLP_INTBASE + 12) + /* IRQ for security engine */ +#define MSP_INT_PER (MSP_SLP_INTBASE + 13) + /* Peripheral interrupt */ +#define MSP_INT_TIMER0 (MSP_SLP_INTBASE + 14) + /* SLP timer 0 */ +#define MSP_INT_TIMER1 (MSP_SLP_INTBASE + 15) + /* SLP timer 1 */ +#define MSP_INT_TIMER2 (MSP_SLP_INTBASE + 16) + /* SLP timer 2 */ +#define MSP_INT_SLP_TIMER (MSP_SLP_INTBASE + 17) + /* Cascaded MIPS timer */ +#define MSP_INT_BLKCP (MSP_SLP_INTBASE + 18) + /* Block Copy */ +#define MSP_INT_UART0 (MSP_SLP_INTBASE + 19) + /* UART 0 */ +#define MSP_INT_PCI (MSP_SLP_INTBASE + 20) + /* PCI subsystem */ +#define MSP_INT_PCI_DBELL (MSP_SLP_INTBASE + 21) + /* PCI doorbell */ +#define MSP_INT_PCI_MSI (MSP_SLP_INTBASE + 22) + /* PCI Message Signal */ +#define MSP_INT_PCI_BC0 (MSP_SLP_INTBASE + 23) + /* PCI Block Copy 0 */ +#define MSP_INT_PCI_BC1 (MSP_SLP_INTBASE + 24) + /* PCI Block Copy 1 */ +#define MSP_INT_SLP_ERR (MSP_SLP_INTBASE + 25) + /* SLP error condition */ +#define MSP_INT_MAC2 (MSP_SLP_INTBASE + 26) + /* IRQ for MAC2 */ +/* Reserved 26-31 */ + +/* + * IRQs cascaded on SLP PER interrupt (MSP_INT_PER) + */ +#define MSP_PER_INTBASE (MSP_SLP_INTBASE + 32) +/* Reserved 0-1 */ +#define MSP_INT_UART1 (MSP_PER_INTBASE + 2) + /* UART 1 */ +/* Reserved 3-5 */ +#define MSP_INT_2WIRE (MSP_PER_INTBASE + 6) + /* 2-wire */ +#define MSP_INT_TM0 (MSP_PER_INTBASE + 7) + /* Peripheral timer block out 0 */ +#define MSP_INT_TM1 (MSP_PER_INTBASE + 8) + /* Peripheral timer block out 1 */ +/* Reserved 9 */ +#define MSP_INT_SPRX (MSP_PER_INTBASE + 10) + /* SPI RX complete */ +#define MSP_INT_SPTX (MSP_PER_INTBASE + 11) + /* SPI TX complete */ +#define MSP_INT_GPIO (MSP_PER_INTBASE + 12) + /* GPIO */ +#define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13) + /* Peripheral error */ +/* Reserved 14-31 */ + +#endif /* !_MSP_SLP_INT_H */ diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h index 5f80ba71ab9..1d8b9a8ae32 100644 --- a/include/asm-mips/processor.h +++ b/include/asm-mips/processor.h @@ -82,10 +82,6 @@ struct mips_fpu_struct { unsigned int fcr31; }; -#define INIT_FPU { \ - {0,} \ -} - #define NUM_DSP_REGS 6 typedef __u32 dspreg_t; @@ -95,8 +91,6 @@ struct mips_dsp_state { unsigned int dspcontrol; }; -#define INIT_DSP {{0,},} - #define INIT_CPUMASK { \ {0,} \ } @@ -155,41 +149,63 @@ struct thread_struct { #define MF_N64 0 #ifdef CONFIG_MIPS_MT_FPAFF -#define FPAFF_INIT 0, INIT_CPUMASK, +#define FPAFF_INIT \ + .emulated_fp = 0, \ + .user_cpus_allowed = INIT_CPUMASK, #else #define FPAFF_INIT #endif /* CONFIG_MIPS_MT_FPAFF */ -#define INIT_THREAD { \ - /* \ - * saved main processor registers \ - */ \ - 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, \ - /* \ - * saved cp0 stuff \ - */ \ - 0, \ - /* \ - * saved fpu/fpu emulator stuff \ - */ \ - INIT_FPU, \ - /* \ - * fpu affinity state (null if not FPAFF) \ - */ \ - FPAFF_INIT \ - /* \ - * saved dsp/dsp emulator stuff \ - */ \ - INIT_DSP, \ - /* \ - * Other stuff associated with the process \ - */ \ - 0, 0, 0, 0, \ - /* \ - * For now the default is to fix address errors \ - */ \ - MF_FIXADE, 0, 0 \ +#define INIT_THREAD { \ + /* \ + * Saved main processor registers \ + */ \ + .reg16 = 0, \ + .reg17 = 0, \ + .reg18 = 0, \ + .reg19 = 0, \ + .reg20 = 0, \ + .reg21 = 0, \ + .reg22 = 0, \ + .reg23 = 0, \ + .reg29 = 0, \ + .reg30 = 0, \ + .reg31 = 0, \ + /* \ + * Saved cp0 stuff \ + */ \ + .cp0_status = 0, \ + /* \ + * Saved FPU/FPU emulator stuff \ + */ \ + .fpu = { \ + .fpr = {0,}, \ + .fcr31 = 0, \ + }, \ + /* \ + * FPU affinity state (null if not FPAFF) \ + */ \ + FPAFF_INIT \ + /* \ + * Saved DSP stuff \ + */ \ + .dsp = { \ + .dspr = {0, }, \ + .dspcontrol = 0, \ + }, \ + /* \ + * Other stuff associated with the process \ + */ \ + .cp0_badvaddr = 0, \ + .cp0_baduaddr = 0, \ + .error_code = 0, \ + .trap_no = 0, \ + /* \ + * For now the default is to fix address errors \ + */ \ + .mflags = MF_FIXADE, \ + .irix_trampoline = 0, \ + .irix_oldctx = 0, \ } struct task_struct; @@ -237,7 +253,7 @@ unsigned long get_wchan(struct task_struct *p); #define ARCH_HAS_PREFETCH -extern inline void prefetch(const void *addr) +static inline void prefetch(const void *addr) { __asm__ __volatile__( " .set mips4 \n" diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h index 1906938285c..85b44366343 100644 --- a/include/asm-mips/ptrace.h +++ b/include/asm-mips/ptrace.h @@ -86,7 +86,7 @@ struct pt_regs { extern asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit); -extern NORET_TYPE void die(const char *, struct pt_regs *); +extern NORET_TYPE void die(const char *, struct pt_regs *) ATTRIB_NORET; static inline void die_if_kernel(const char *str, struct pt_regs *regs) { diff --git a/include/asm-mips/rtc.h b/include/asm-mips/rtc.h deleted file mode 100644 index 82ad401c7dc..00000000000 --- a/include/asm-mips/rtc.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * include/asm-mips/rtc.h - * - * (Really an interface for drivers/char/genrtc.c) - * - * Copyright (C) 2004 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * Please read the COPYING file for all license details. - */ - -#ifndef _MIPS_RTC_H -#define _MIPS_RTC_H - -#ifdef __KERNEL__ - -#include <linux/rtc.h> -#include <asm/time.h> - -#define RTC_PIE 0x40 /* periodic interrupt enable */ -#define RTC_AIE 0x20 /* alarm interrupt enable */ -#define RTC_UIE 0x10 /* update-finished interrupt enable */ - -/* some dummy definitions */ -#define RTC_BATT_BAD 0x100 /* battery bad */ -#define RTC_SQWE 0x08 /* enable square-wave output */ -#define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */ -#define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ -#define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ - -static inline unsigned int get_rtc_time(struct rtc_time *time) -{ - unsigned long nowtime; - - nowtime = rtc_mips_get_time(); - to_tm(nowtime, time); - time->tm_year -= 1900; - - return RTC_24H; -} - -static inline int set_rtc_time(struct rtc_time *time) -{ - unsigned long nowtime; - int ret; - - nowtime = mktime(time->tm_year+1900, time->tm_mon+1, - time->tm_mday, time->tm_hour, time->tm_min, - time->tm_sec); - ret = rtc_mips_set_time(nowtime); - - return ret; -} - -static inline unsigned int get_rtc_ss(void) -{ - struct rtc_time h; - - get_rtc_time(&h); - return h.tm_sec; -} - -static inline int get_rtc_pll(struct rtc_pll_info *pll) -{ - return -EINVAL; -} - -static inline int set_rtc_pll(struct rtc_pll_info *pll) -{ - return -EINVAL; -} -#endif -#endif diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h index ce51213d84f..c07ebd8eb9e 100644 --- a/include/asm-mips/serial.h +++ b/include/asm-mips/serial.h @@ -19,159 +19,4 @@ */ #define BASE_BAUD (1843200 / 16) -/* Standard COM flags (except for COM4, because of the 8514 problem) */ -#ifdef CONFIG_SERIAL_DETECT_IRQ -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) -#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ) -#else -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) -#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF -#endif - -#ifdef CONFIG_MACH_JAZZ -#include <asm/jazz.h> - -#ifndef CONFIG_OLIVETTI_M700 - /* Some Jazz machines seem to have an 8MHz crystal clock but I don't know - exactly which ones ... XXX */ -#define JAZZ_BASE_BAUD ( 8000000 / 16 ) /* ( 3072000 / 16) */ -#else -/* but the M700 isn't such a strange beast */ -#define JAZZ_BASE_BAUD BASE_BAUD -#endif - -#define _JAZZ_SERIAL_INIT(int, base) \ - { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \ - .iomem_base = (u8 *) base, .iomem_reg_shift = 0, \ - .io_type = SERIAL_IO_MEM } -#define JAZZ_SERIAL_PORT_DEFNS \ - _JAZZ_SERIAL_INIT(JAZZ_SERIAL1_IRQ, JAZZ_SERIAL1_BASE), \ - _JAZZ_SERIAL_INIT(JAZZ_SERIAL2_IRQ, JAZZ_SERIAL2_BASE), -#else -#define JAZZ_SERIAL_PORT_DEFNS -#endif - -/* - * Galileo EV64120 evaluation board - */ -#ifdef CONFIG_MIPS_EV64120 -#include <mach-gt64120.h> -#define EV64120_SERIAL_PORT_DEFNS \ - { .baud_base = EV64120_BASE_BAUD, .irq = EV64120_UART_IRQ, \ - .flags = STD_COM_FLAGS, \ - .iomem_base = EV64120_UART0_REGS_BASE, .iomem_reg_shift = 2, \ - .io_type = SERIAL_IO_MEM }, \ - { .baud_base = EV64120_BASE_BAUD, .irq = EV64120_UART_IRQ, \ - .flags = STD_COM_FLAGS, \ - .iomem_base = EV64120_UART1_REGS_BASE, .iomem_reg_shift = 2, \ - .io_type = SERIAL_IO_MEM }, -#else -#define EV64120_SERIAL_PORT_DEFNS -#endif - -#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT -#define STD_SERIAL_PORT_DEFNS \ - /* UART CLK PORT IRQ FLAGS */ \ - { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ - { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ - { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ - { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ - -#else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */ -#define STD_SERIAL_PORT_DEFNS -#endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */ - -#ifdef CONFIG_MOMENCO_OCELOT_3 -#define OCELOT_3_BASE_BAUD ( 20000000 / 16 ) -#define OCELOT_3_SERIAL_IRQ 6 -#define OCELOT_3_SERIAL_BASE (signed)0xfd000020 - -#define _OCELOT_3_SERIAL_INIT(int, base) \ - { .baud_base = OCELOT_3_BASE_BAUD, irq: int, \ - .flags = STD_COM_FLAGS, \ - .iomem_base = (u8 *) base, iomem_reg_shift: 2, \ - io_type: SERIAL_IO_MEM } - -#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \ - _OCELOT_3_SERIAL_INIT(OCELOT_3_SERIAL_IRQ, OCELOT_3_SERIAL_BASE) -#else -#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS -#endif - -#ifdef CONFIG_MOMENCO_OCELOT -/* Ordinary NS16552 duart with a 20MHz crystal. */ -#define OCELOT_BASE_BAUD ( 20000000 / 16 ) - -#define OCELOT_SERIAL1_IRQ 4 -#define OCELOT_SERIAL1_BASE 0xe0001020 - -#define _OCELOT_SERIAL_INIT(int, base) \ - { .baud_base = OCELOT_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \ - .iomem_base = (u8 *) base, .iomem_reg_shift = 2, \ - .io_type = SERIAL_IO_MEM } -#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS \ - _OCELOT_SERIAL_INIT(OCELOT_SERIAL1_IRQ, OCELOT_SERIAL1_BASE) -#else -#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS -#endif - -#ifdef CONFIG_MOMENCO_OCELOT_C -/* Ordinary NS16552 duart with a 20MHz crystal. */ -#define OCELOT_C_BASE_BAUD ( 20000000 / 16 ) - -#define OCELOT_C_SERIAL1_IRQ 80 -#define OCELOT_C_SERIAL1_BASE 0xfd000020 - -#define OCELOT_C_SERIAL2_IRQ 81 -#define OCELOT_C_SERIAL2_BASE 0xfd000000 - -#define _OCELOT_C_SERIAL_INIT(int, base) \ - { .baud_base = OCELOT_C_BASE_BAUD, \ - .irq = (int), \ - .flags = STD_COM_FLAGS, \ - .iomem_base = (u8 *) base, \ - .iomem_reg_shift = 2, \ - .io_type = SERIAL_IO_MEM \ - } -#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ - _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL1_IRQ, OCELOT_C_SERIAL1_BASE), \ - _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL2_IRQ, OCELOT_C_SERIAL2_BASE) -#else -#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS -#endif - -#ifdef CONFIG_DDB5477 -#include <asm/ddb5xxx/ddb5477.h> -#define DDB5477_SERIAL_PORT_DEFNS \ - { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART0, \ - .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04200, \ - .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM}, \ - { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART1, \ - .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04240, \ - .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM}, -#else -#define DDB5477_SERIAL_PORT_DEFNS -#endif - -#ifdef CONFIG_SGI_IP32 -/* - * The IP32 (SGI O2) has standard serial ports (UART 16550A) mapped in memory - * They are initialized in ip32_setup - */ -#define IP32_SERIAL_PORT_DEFNS \ - {},{}, -#else -#define IP32_SERIAL_PORT_DEFNS -#endif /* CONFIG_SGI_IP32 */ - -#define SERIAL_PORT_DFNS \ - DDB5477_SERIAL_PORT_DEFNS \ - EV64120_SERIAL_PORT_DEFNS \ - IP32_SERIAL_PORT_DEFNS \ - JAZZ_SERIAL_PORT_DEFNS \ - STD_SERIAL_PORT_DEFNS \ - MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ - MOMENCO_OCELOT_SERIAL_PORT_DEFNS \ - MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS - #endif /* _ASM_SERIAL_H */ diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h index 1608fd71d6f..13aef6af422 100644 --- a/include/asm-mips/smp.h +++ b/include/asm-mips/smp.h @@ -49,13 +49,6 @@ extern struct call_data_struct *call_data; extern cpumask_t phys_cpu_present_map; #define cpu_possible_map phys_cpu_present_map -extern cpumask_t cpu_callout_map; -/* We don't mark CPUs online until __cpu_up(), so we need another measure */ -static inline int num_booting_cpus(void) -{ - return cpus_weight(cpu_callout_map); -} - /* * These are defined by the board-specific code. */ diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h index f257509b914..ddaf36a1e38 100644 --- a/include/asm-mips/sni.h +++ b/include/asm-mips/sni.h @@ -146,9 +146,6 @@ extern unsigned int sni_brd_type; #define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE #define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5) -#define SNI_DS1216_A20R_BASE 0xbc081ffc -#define SNI_DS1216_RM200_BASE 0xbcd41ffc - #define SNI_PCIT_INT_REG 0xbfff000c #define SNI_PCIT_INT_START 24 diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h index 7afa1fdf70c..ed33366b85b 100644 --- a/include/asm-mips/stackframe.h +++ b/include/asm-mips/stackframe.h @@ -17,6 +17,18 @@ #include <asm/mipsregs.h> #include <asm/asm-offsets.h> +/* + * For SMTC kernel, global IE should be left set, and interrupts + * controlled exclusively via IXMT. + */ +#ifdef CONFIG_MIPS_MT_SMTC +#define STATMASK 0x1e +#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) +#define STATMASK 0x3f +#else +#define STATMASK 0x1f +#endif + #ifdef CONFIG_MIPS_MT_SMTC #include <asm/mipsmtregs.h> #endif /* CONFIG_MIPS_MT_SMTC */ @@ -236,10 +248,10 @@ .set reorder .set noat mfc0 a0, CP0_STATUS - ori a0, 0x1f - xori a0, 0x1f - mtc0 a0, CP0_STATUS li v1, 0xff00 + ori a0, STATMASK + xori a0, STATMASK + mtc0 a0, CP0_STATUS and a0, v1 LONG_L v0, PT_STATUS(sp) nor v1, $0, v1 @@ -249,10 +261,6 @@ LONG_L $31, PT_R31(sp) LONG_L $28, PT_R28(sp) LONG_L $25, PT_R25(sp) -#ifdef CONFIG_64BIT - LONG_L $8, PT_R8(sp) - LONG_L $9, PT_R9(sp) -#endif LONG_L $7, PT_R7(sp) LONG_L $6, PT_R6(sp) LONG_L $5, PT_R5(sp) @@ -273,16 +281,6 @@ .endm #else -/* - * For SMTC kernel, global IE should be left set, and interrupts - * controlled exclusively via IXMT. - */ - -#ifdef CONFIG_MIPS_MT_SMTC -#define STATMASK 0x1e -#else -#define STATMASK 0x1f -#endif .macro RESTORE_SOME .set push .set reorder @@ -385,9 +383,9 @@ .macro CLI #if !defined(CONFIG_MIPS_MT_SMTC) mfc0 t0, CP0_STATUS - li t1, ST0_CU0 | 0x1f + li t1, ST0_CU0 | STATMASK or t0, t1 - xori t0, 0x1f + xori t0, STATMASK mtc0 t0, CP0_STATUS #else /* CONFIG_MIPS_MT_SMTC */ /* @@ -420,9 +418,9 @@ .macro STI #if !defined(CONFIG_MIPS_MT_SMTC) mfc0 t0, CP0_STATUS - li t1, ST0_CU0 | 0x1f + li t1, ST0_CU0 | STATMASK or t0, t1 - xori t0, 0x1e + xori t0, STATMASK & ~1 mtc0 t0, CP0_STATUS #else /* CONFIG_MIPS_MT_SMTC */ /* @@ -451,7 +449,8 @@ .endm /* - * Just move to kernel mode and leave interrupts as they are. + * Just move to kernel mode and leave interrupts as they are. Note + * for the R3000 this means copying the previous enable from IEp. * Set cp0 enable bit as sign that we're running on the kernel stack */ .macro KMODE @@ -482,9 +481,14 @@ move ra, t0 #endif /* CONFIG_MIPS_MT_SMTC */ mfc0 t0, CP0_STATUS - li t1, ST0_CU0 | 0x1e + li t1, ST0_CU0 | (STATMASK & ~1) +#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) + andi t2, t0, ST0_IEP + srl t2, 2 + or t0, t2 +#endif or t0, t1 - xori t0, 0x1e + xori t0, STATMASK & ~1 mtc0 t0, CP0_STATUS #ifdef CONFIG_MIPS_MT_SMTC _ehb diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h index bb0b289dbc9..46bdb3f566f 100644 --- a/include/asm-mips/system.h +++ b/include/asm-mips/system.h @@ -44,7 +44,7 @@ struct task_struct; * different thread. */ -#define switch_to(prev,next,last) \ +#define __mips_mt_fpaff_switch_to(prev) \ do { \ if (cpu_has_fpu && \ (prev->thread.mflags & MF_FPUBOUND) && \ @@ -52,24 +52,24 @@ do { \ prev->thread.mflags &= ~MF_FPUBOUND; \ prev->cpus_allowed = prev->thread.user_cpus_allowed; \ } \ - if (cpu_has_dsp) \ - __save_dsp(prev); \ next->thread.emulated_fp = 0; \ - (last) = resume(prev, next, task_thread_info(next)); \ - if (cpu_has_dsp) \ - __restore_dsp(current); \ } while(0) #else +#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0) +#endif + #define switch_to(prev,next,last) \ do { \ + __mips_mt_fpaff_switch_to(prev); \ if (cpu_has_dsp) \ __save_dsp(prev); \ (last) = resume(prev, next, task_thread_info(next)); \ if (cpu_has_dsp) \ __restore_dsp(current); \ + if (cpu_has_userlocal) \ + write_c0_userlocal(task_thread_info(current)->tp_value);\ } while(0) -#endif /* * On SMP systems, when the scheduler does migration-cost autodetection, diff --git a/include/asm-mips/termbits.h b/include/asm-mips/termbits.h index 0bbe07b42a0..5bfdc3b6451 100644 --- a/include/asm-mips/termbits.h +++ b/include/asm-mips/termbits.h @@ -30,6 +30,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ diff --git a/include/asm-mips/tlbdebug.h b/include/asm-mips/tlbdebug.h index fff7a73e22d..bb8f5c29c3d 100644 --- a/include/asm-mips/tlbdebug.h +++ b/include/asm-mips/tlbdebug.h @@ -11,10 +11,6 @@ /* * TLB debugging functions: */ -extern void dump_tlb(int first, int last); extern void dump_tlb_all(void); -extern void dump_tlb_wired(void); -extern void dump_tlb_addr(unsigned long addr); -extern void dump_tlb_nonwired(void); #endif /* __ASM_TLBDEBUG_H */ diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h index 0fbedafdcea..74e7d8061e5 100644 --- a/include/asm-mips/tx4938/rbtx4938.h +++ b/include/asm-mips/tx4938/rbtx4938.h @@ -105,12 +105,6 @@ #define rbtx4938_pcireset_ptr \ ((volatile unsigned char *)RBTX4938_PCIRESET_ADDR) -/* SPI */ -#define RBTX4938_SEEPROM1_CHIPID 0 -#define RBTX4938_SEEPROM2_CHIPID 1 -#define RBTX4938_SEEPROM3_CHIPID 2 -#define RBTX4938_SRTC_CHIPID 3 - /* * IRQ mappings */ diff --git a/include/asm-mips/tx4938/spi.h b/include/asm-mips/tx4938/spi.h index 0dbbab820a5..6a60c83e152 100644 --- a/include/asm-mips/tx4938/spi.h +++ b/include/asm-mips/tx4938/spi.h @@ -14,61 +14,7 @@ #ifndef __ASM_TX_BOARDS_TX4938_SPI_H #define __ASM_TX_BOARDS_TX4938_SPI_H -/* SPI */ -struct spi_dev_desc { - unsigned int baud; - unsigned short tcss, tcsh, tcsr; /* CS setup/hold/recovery time */ - unsigned int byteorder:1; /* 0:LSB-First, 1:MSB-First */ - unsigned int polarity:1; /* 0:High-Active */ - unsigned int phase:1; /* 0:Sample-Then-Shift */ -}; - -extern void txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on)) __init; -extern void txx9_spi_irqinit(int irc_irq) __init; -extern int txx9_spi_io(int chipid, struct spi_dev_desc *desc, - unsigned char **inbufs, unsigned int *incounts, - unsigned char **outbufs, unsigned int *outcounts, - int cansleep); -extern int spi_eeprom_write_enable(int chipid, int enable); -extern int spi_eeprom_read_status(int chipid); +extern int spi_eeprom_register(int chipid); extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len); -extern int spi_eeprom_write(int chipid, int address, unsigned char *buf, int len); -extern void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid) __init; - -#define TXX9_IMCLK (txx9_gbus_clock / 2) - -/* -* SPI -*/ - -/* SPMCR : SPI Master Control */ -#define TXx9_SPMCR_OPMODE 0xc0 -#define TXx9_SPMCR_CONFIG 0x40 -#define TXx9_SPMCR_ACTIVE 0x80 -#define TXx9_SPMCR_SPSTP 0x02 -#define TXx9_SPMCR_BCLR 0x01 - -/* SPCR0 : SPI Status */ -#define TXx9_SPCR0_TXIFL_MASK 0xc000 -#define TXx9_SPCR0_RXIFL_MASK 0x3000 -#define TXx9_SPCR0_SIDIE 0x0800 -#define TXx9_SPCR0_SOEIE 0x0400 -#define TXx9_SPCR0_RBSIE 0x0200 -#define TXx9_SPCR0_TBSIE 0x0100 -#define TXx9_SPCR0_IFSPSE 0x0010 -#define TXx9_SPCR0_SBOS 0x0004 -#define TXx9_SPCR0_SPHA 0x0002 -#define TXx9_SPCR0_SPOL 0x0001 - -/* SPSR : SPI Status */ -#define TXx9_SPSR_TBSI 0x8000 -#define TXx9_SPSR_RBSI 0x4000 -#define TXx9_SPSR_TBS_MASK 0x3800 -#define TXx9_SPSR_RBS_MASK 0x0700 -#define TXx9_SPSR_SPOE 0x0080 -#define TXx9_SPSR_IFSD 0x0008 -#define TXx9_SPSR_SIDLE 0x0004 -#define TXx9_SPSR_STRDY 0x0002 -#define TXx9_SPSR_SRRDY 0x0001 #endif /* __ASM_TX_BOARDS_TX4938_SPI_H */ diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h index 2f1087b3a20..ed16de0a639 100644 --- a/include/asm-mips/unistd.h +++ b/include/asm-mips/unistd.h @@ -336,16 +336,20 @@ #define __NR_epoll_pwait (__NR_Linux + 313) #define __NR_ioprio_set (__NR_Linux + 314) #define __NR_ioprio_get (__NR_Linux + 315) +#define __NR_utimensat (__NR_Linux + 316) +#define __NR_signalfd (__NR_Linux + 317) +#define __NR_timerfd (__NR_Linux + 318) +#define __NR_eventfd (__NR_Linux + 319) /* * Offset of the last Linux o32 flavoured syscall */ -#define __NR_Linux_syscalls 315 +#define __NR_Linux_syscalls 319 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ #define __NR_O32_Linux 4000 -#define __NR_O32_Linux_syscalls 315 +#define __NR_O32_Linux_syscalls 319 #if _MIPS_SIM == _MIPS_SIM_ABI64 @@ -628,16 +632,20 @@ #define __NR_epoll_pwait (__NR_Linux + 272) #define __NR_ioprio_set (__NR_Linux + 273) #define __NR_ioprio_get (__NR_Linux + 274) +#define __NR_utimensat (__NR_Linux + 275) +#define __NR_signalfd (__NR_Linux + 276) +#define __NR_timerfd (__NR_Linux + 277) +#define __NR_eventfd (__NR_Linux + 278) /* * Offset of the last Linux 64-bit flavoured syscall */ -#define __NR_Linux_syscalls 274 +#define __NR_Linux_syscalls 278 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ #define __NR_64_Linux 5000 -#define __NR_64_Linux_syscalls 274 +#define __NR_64_Linux_syscalls 278 #if _MIPS_SIM == _MIPS_SIM_NABI32 @@ -924,16 +932,20 @@ #define __NR_epoll_pwait (__NR_Linux + 276) #define __NR_ioprio_set (__NR_Linux + 277) #define __NR_ioprio_get (__NR_Linux + 278) +#define __NR_utimensat (__NR_Linux + 279) +#define __NR_signalfd (__NR_Linux + 280) +#define __NR_timerfd (__NR_Linux + 281) +#define __NR_eventfd (__NR_Linux + 282) /* * Offset of the last N32 flavoured syscall */ -#define __NR_Linux_syscalls 278 +#define __NR_Linux_syscalls 282 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ #define __NR_N32_Linux 6000 -#define __NR_N32_Linux_syscalls 278 +#define __NR_N32_Linux_syscalls 282 #ifdef __KERNEL__ @@ -949,7 +961,6 @@ #define __ARCH_WANT_SYS_UTIME #define __ARCH_WANT_SYS_WAITPID #define __ARCH_WANT_SYS_SOCKETCALL -#define __ARCH_WANT_SYS_FADVISE64 #define __ARCH_WANT_SYS_GETPGRP #define __ARCH_WANT_SYS_LLSEEK #define __ARCH_WANT_SYS_NICE @@ -966,6 +977,22 @@ # define __ARCH_WANT_COMPAT_SYS_TIME # endif +/* whitelists for checksyscalls */ +#define __IGNORE_select +#define __IGNORE_vfork +#define __IGNORE_time +#define __IGNORE_uselib +#define __IGNORE_fadvise64_64 +#define __IGNORE_getdents64 +#if _MIPS_SIM == _MIPS_SIM_NABI32 +#define __IGNORE_truncate64 +#define __IGNORE_ftruncate64 +#define __IGNORE_stat64 +#define __IGNORE_lstat64 +#define __IGNORE_fstat64 +#define __IGNORE_fstatat64 +#endif + #endif /* !__ASSEMBLY__ */ /* diff --git a/include/asm-mips/vr41xx/giu.h b/include/asm-mips/vr41xx/giu.h index 8109cda557d..0bcdd3a5c25 100644 --- a/include/asm-mips/vr41xx/giu.h +++ b/include/asm-mips/vr41xx/giu.h @@ -20,6 +20,15 @@ #ifndef __NEC_VR41XX_GIU_H #define __NEC_VR41XX_GIU_H +/* + * NEC VR4100 series GIU platform device IDs. + */ +enum { + GPIO_50PINS_PULLUPDOWN, + GPIO_36PINS, + GPIO_48PINS_EDGE_SELECT, +}; + typedef enum { IRQ_TRIGGER_LEVEL, IRQ_TRIGGER_EDGE, diff --git a/include/asm-mips/vr41xx/siu.h b/include/asm-mips/vr41xx/siu.h index 1fcf6e8082b..98cdb409648 100644 --- a/include/asm-mips/vr41xx/siu.h +++ b/include/asm-mips/vr41xx/siu.h @@ -20,6 +20,8 @@ #ifndef __NEC_VR41XX_SIU_H #define __NEC_VR41XX_SIU_H +#define SIU_PORTS_MAX 2 + typedef enum { SIU_INTERFACE_RS232C, SIU_INTERFACE_IRDA, diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index 13a3502eef4..9de52a5b0f3 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h @@ -169,26 +169,28 @@ /* * On the RM9000 there is a problem which makes the CreateDirtyExclusive - * cache operation unusable on SMP systems. + * eache operation unusable on SMP systems. */ -#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE) || \ - defined(CONFIG_BASLER_EXCITE) +#if defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE) #define RM9000_CDEX_SMP_WAR 1 #endif /* - * The RM9000 has a bug (though PMC-Sierra opposes it being called that) - * where invalid instructions in the same I-cache line worth of instructions - * being fetched may case spurious exceptions. + * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra + * opposes it being called that) where invalid instructions in the same + * I-cache line worth of instructions being fetched may case spurious + * exceptions. */ -#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \ - defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE) +#if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MIPS_ATLAS) || \ + defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MOMENCO_OCELOT) || \ + defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_SGI_IP32) || \ + defined(CONFIG_WR_PPMC) #define ICACHE_REFILLS_WORKAROUND_WAR 1 #endif /* - * ON the R10000 upto version 2.6 (not sure about 2.7) there is a bug that + * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that * may cause ll / sc and lld / scd sequences to execute non-atomically. */ #ifdef CONFIG_SGI_IP27 @@ -196,6 +198,14 @@ #endif /* + * 34K core erratum: "Problems Executing the TLBR Instruction" + */ +#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \ + defined(CONFIG_PMC_MSP7120_FPGA) +#define MIPS34K_MISSED_ITLB_WAR 1 +#endif + +/* * Workarounds default to off */ #ifndef ICACHE_REFILLS_WORKAROUND_WAR @@ -234,5 +244,8 @@ #ifndef R10000_LLSC_WAR #define R10000_LLSC_WAR 0 #endif +#ifndef MIPS34K_MISSED_ITLB_WAR +#define MIPS34K_MISSED_ITLB_WAR 0 +#endif #endif /* _ASM_WAR_H */ diff --git a/include/asm-mips/watch.h b/include/asm-mips/watch.h deleted file mode 100644 index 6aa90cae111..00000000000 --- a/include/asm-mips/watch.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996, 1997, 1998, 2000, 2001 by Ralf Baechle - */ -#ifndef _ASM_WATCH_H -#define _ASM_WATCH_H - -#include <linux/linkage.h> - -/* - * Types of reference for watch_set() - */ -enum wref_type { - wr_save = 1, - wr_load = 2 -}; - -extern asmlinkage void __watch_set(unsigned long addr, enum wref_type ref); -extern asmlinkage void __watch_clear(void); -extern asmlinkage void __watch_reenable(void); - -#define watch_set(addr, ref) \ - if (cpu_has_watch) \ - __watch_set(addr, ref) -#define watch_clear() \ - if (cpu_has_watch) \ - __watch_clear() -#define watch_reenable() \ - if (cpu_has_watch) \ - __watch_reenable() - -#endif /* _ASM_WATCH_H */ diff --git a/include/asm-parisc/hardware.h b/include/asm-parisc/hardware.h index 76d880dc4ba..4e9626836ba 100644 --- a/include/asm-parisc/hardware.h +++ b/include/asm-parisc/hardware.h @@ -31,10 +31,11 @@ enum cpu_type { pcxw = 8, /* pa8500 pa 2.0 */ pcxw_ = 9, /* pa8600 (w+) pa 2.0 */ pcxw2 = 10, /* pa8700 pa 2.0 */ - mako = 11 /* pa8800 pa 2.0 */ + mako = 11, /* pa8800 pa 2.0 */ + mako2 = 12 /* pa8900 pa 2.0 */ }; -extern char *cpu_name_version[][2]; /* mapping from enum cpu_type to strings */ +extern const char * const cpu_name_version[][2]; /* mapping from enum cpu_type to strings */ struct parisc_driver; diff --git a/include/asm-parisc/linkage.h b/include/asm-parisc/linkage.h index 7a09d911b53..ad8cd0d069e 100644 --- a/include/asm-parisc/linkage.h +++ b/include/asm-parisc/linkage.h @@ -8,8 +8,10 @@ /* * In parisc assembly a semicolon marks a comment while a - * exclamation mark is used to seperate independend lines. + * exclamation mark is used to seperate independent lines. */ +#ifdef __ASSEMBLY__ + #define ENTRY(name) \ .export name !\ ALIGN !\ @@ -24,5 +26,6 @@ name: END(name) #endif +#endif /* __ASSEMBLY__ */ #endif /* __ASM_PARISC_LINKAGE_H */ diff --git a/include/asm-parisc/pci.h b/include/asm-parisc/pci.h index 7b3be9ac0dd..61fbd57a832 100644 --- a/include/asm-parisc/pci.h +++ b/include/asm-parisc/pci.h @@ -238,9 +238,6 @@ extern inline void pcibios_register_hba(struct pci_hba_data *x) #define PCIBIOS_MIN_IO 0x10 #define PCIBIOS_MIN_MEM 0x1000 /* NBPG - but pci/setup-res.c dies */ -/* Don't support DAC yet. */ -#define pci_dac_dma_supported(pci_dev, mask) (0) - /* export the pci_ DMA API in terms of the dma_ one */ #include <asm-generic/pci-dma-compat.h> @@ -284,10 +281,6 @@ pcibios_select_root(struct pci_dev *pdev, struct resource *res) return root; } -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - static inline void pcibios_penalize_isa_irq(int irq, int active) { /* We don't need to penalize isa irq's */ diff --git a/include/asm-parisc/processor.h b/include/asm-parisc/processor.h index d2f396721d3..6b294fb07a2 100644 --- a/include/asm-parisc/processor.h +++ b/include/asm-parisc/processor.h @@ -69,8 +69,8 @@ struct system_cpuinfo_parisc { char sys_model_name[81]; /* PDC-ROM returnes this model name */ } pdc; - char *cpu_name; /* e.g. "PA7300LC (PCX-L2)" */ - char *family_name; /* e.g. "1.1e" */ + const char *cpu_name; /* e.g. "PA7300LC (PCX-L2)" */ + const char *family_name; /* e.g. "1.1e" */ }; @@ -334,8 +334,8 @@ extern unsigned long get_wchan(struct task_struct *p); static inline int parisc_requires_coherency(void) { #ifdef CONFIG_PA8X00 - /* FIXME: also pa8900 - when we see one */ - return boot_cpu_data.cpu_type == mako; + return (boot_cpu_data.cpu_type == mako) || + (boot_cpu_data.cpu_type == mako2); #else return 0; #endif diff --git a/include/asm-parisc/system.h b/include/asm-parisc/system.h index 7e9afa720d4..21fbfc5afd0 100644 --- a/include/asm-parisc/system.h +++ b/include/asm-parisc/system.h @@ -188,7 +188,6 @@ static inline void set_eiem(unsigned long val) # define __lock_aligned __attribute__((__section__(".data.lock_aligned"))) #endif -#define KERNEL_START (0x10100000 - 0x1000) #define arch_align_stack(x) (x) #endif diff --git a/include/asm-parisc/termbits.h b/include/asm-parisc/termbits.h index a46e299a939..e847fe97968 100644 --- a/include/asm-parisc/termbits.h +++ b/include/asm-parisc/termbits.h @@ -17,6 +17,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ diff --git a/include/asm-parisc/unistd.h b/include/asm-parisc/unistd.h index 2f7c40861c9..f74099bdca3 100644 --- a/include/asm-parisc/unistd.h +++ b/include/asm-parisc/unistd.h @@ -792,8 +792,19 @@ #define __NR_epoll_pwait (__NR_Linux + 297) #define __NR_statfs64 (__NR_Linux + 298) #define __NR_fstatfs64 (__NR_Linux + 299) +#define __NR_kexec_load (__NR_Linux + 300) +#define __NR_utimensat (__NR_Linux + 301) +#define __NR_signalfd (__NR_Linux + 302) +#define __NR_timerfd (__NR_Linux + 303) +#define __NR_eventfd (__NR_Linux + 304) + +#define __NR_Linux_syscalls (__NR_eventfd + 1) + + +#define __IGNORE_select /* newselect */ +#define __IGNORE_fadvise64 /* fadvise64_64 */ +#define __IGNORE_utimes /* utime */ -#define __NR_Linux_syscalls (__NR_fstatfs64 + 1) #define HPUX_GATEWAY_ADDR 0xC0000004 #define LINUX_GATEWAY_ADDR 0x100 diff --git a/include/asm-powerpc/dma-mapping.h b/include/asm-powerpc/dma-mapping.h index a19a6f1a1cf..f6bd804d909 100644 --- a/include/asm-powerpc/dma-mapping.h +++ b/include/asm-powerpc/dma-mapping.h @@ -61,7 +61,6 @@ struct dma_mapping_ops { void (*unmap_sg)(struct device *dev, struct scatterlist *sg, int nents, enum dma_data_direction direction); int (*dma_supported)(struct device *dev, u64 mask); - int (*dac_dma_supported)(struct device *dev, u64 mask); int (*set_dma_mask)(struct device *dev, u64 dma_mask); }; diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h index 4734cc178db..05dd5a3eb3a 100644 --- a/include/asm-powerpc/irq.h +++ b/include/asm-powerpc/irq.h @@ -138,10 +138,7 @@ struct irq_map_entry { extern struct irq_map_entry irq_map[NR_IRQS]; -static inline irq_hw_number_t virq_to_hw(unsigned int virq) -{ - return irq_map[virq].hwirq; -} +extern irq_hw_number_t virq_to_hw(unsigned int virq); /** * irq_alloc_host - Allocate a new irq_host data structure diff --git a/include/asm-powerpc/pci.h b/include/asm-powerpc/pci.h index ce0f13e8eb1..e16e7bc9ab5 100644 --- a/include/asm-powerpc/pci.h +++ b/include/asm-powerpc/pci.h @@ -74,18 +74,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) extern void set_pci_dma_ops(struct dma_mapping_ops *dma_ops); extern struct dma_mapping_ops *get_pci_dma_ops(void); -/* For DAC DMA, we currently don't support it by default, but - * we let 64-bit platforms override this. - */ -static inline int pci_dac_dma_supported(struct pci_dev *hwdev,u64 mask) -{ - struct dma_mapping_ops *d = get_pci_dma_ops(); - - if (d && d->dac_dma_supported) - return d->dac_dma_supported(&hwdev->dev, mask); - return 0; -} - static inline void pci_dma_burst_advice(struct pci_dev *pdev, enum pci_dma_burst_strategy *strat, unsigned long *strategy_parameter) @@ -124,12 +112,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, } #endif -/* - * At present there are very few 32-bit PPC machines that can have - * memory above the 4GB point, and we don't support that. - */ -#define pci_dac_dma_supported(pci_dev, mask) (0) - /* Return the index of the PCI controller for device PDEV. */ #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index @@ -243,8 +225,6 @@ extern void of_scan_bus(struct device_node *node, struct pci_bus *bus); extern int pci_read_irq_line(struct pci_dev *dev); -extern void pcibios_add_platform_entries(struct pci_dev *dev); - struct file; extern pgprot_t pci_phys_mem_access_prot(struct file *file, unsigned long pfn, diff --git a/include/asm-powerpc/pgalloc-64.h b/include/asm-powerpc/pgalloc-64.h index d9a3a8ca58a..94d0294341d 100644 --- a/include/asm-powerpc/pgalloc-64.h +++ b/include/asm-powerpc/pgalloc-64.h @@ -90,7 +90,8 @@ static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, static inline struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address) { - return virt_to_page(pte_alloc_one_kernel(mm, address)); + pte_t *pte = pte_alloc_one_kernel(mm, address); + return pte ? virt_to_page(pte) : NULL; } static inline void pte_free_kernel(pte_t *pte) diff --git a/include/asm-powerpc/pgtable-ppc32.h b/include/asm-powerpc/pgtable-ppc32.h index c863bdb2889..7fb730c62f8 100644 --- a/include/asm-powerpc/pgtable-ppc32.h +++ b/include/asm-powerpc/pgtable-ppc32.h @@ -673,10 +673,14 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty) } #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \ - do { \ - __ptep_set_access_flags(__ptep, __entry, __dirty); \ - flush_tlb_page_nohash(__vma, __address); \ - } while(0) +({ \ + int __changed = !pte_same(*(__ptep), __entry); \ + if (__changed) { \ + __ptep_set_access_flags(__ptep, __entry, __dirty); \ + flush_tlb_page_nohash(__vma, __address); \ + } \ + __changed; \ +}) /* * Macro to mark a page protection value as "uncacheable". diff --git a/include/asm-powerpc/pgtable-ppc64.h b/include/asm-powerpc/pgtable-ppc64.h index 704c4e669fe..3cfd98f44bf 100644 --- a/include/asm-powerpc/pgtable-ppc64.h +++ b/include/asm-powerpc/pgtable-ppc64.h @@ -413,10 +413,14 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty) :"cc"); } #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \ - do { \ - __ptep_set_access_flags(__ptep, __entry, __dirty); \ - flush_tlb_page_nohash(__vma, __address); \ - } while(0) +({ \ + int __changed = !pte_same(*(__ptep), __entry); \ + if (__changed) { \ + __ptep_set_access_flags(__ptep, __entry, __dirty); \ + flush_tlb_page_nohash(__vma, __address); \ + } \ + __changed; \ +}) /* * Macro to mark a page protection value as "uncacheable". diff --git a/include/asm-powerpc/systbl.h b/include/asm-powerpc/systbl.h index 700ca592874..1cc3f9cb6f4 100644 --- a/include/asm-powerpc/systbl.h +++ b/include/asm-powerpc/systbl.h @@ -311,3 +311,4 @@ COMPAT_SYS_SPU(utimensat) COMPAT_SYS_SPU(signalfd) COMPAT_SYS_SPU(timerfd) SYSCALL_SPU(eventfd) +COMPAT_SYS_SPU(sync_file_range2) diff --git a/include/asm-powerpc/tlb.h b/include/asm-powerpc/tlb.h index 0a17682663d..66714042e43 100644 --- a/include/asm-powerpc/tlb.h +++ b/include/asm-powerpc/tlb.h @@ -38,6 +38,15 @@ extern void pte_free_finish(void); static inline void tlb_flush(struct mmu_gather *tlb) { + struct ppc64_tlb_batch *tlbbatch = &__get_cpu_var(ppc64_tlb_batch); + + /* If there's a TLB batch pending, then we must flush it because the + * pages are going to be freed and we really don't want to have a CPU + * access a freed page because it has a stale TLB + */ + if (tlbbatch->index) + __flush_tlb_pending(tlbbatch); + pte_free_finish(); } diff --git a/include/asm-powerpc/unistd.h b/include/asm-powerpc/unistd.h index e3c28dc31ab..f71c6061f1e 100644 --- a/include/asm-powerpc/unistd.h +++ b/include/asm-powerpc/unistd.h @@ -330,10 +330,11 @@ #define __NR_signalfd 305 #define __NR_timerfd 306 #define __NR_eventfd 307 +#define __NR_sync_file_range2 308 #ifdef __KERNEL__ -#define __NR_syscalls 308 +#define __NR_syscalls 309 #define __NR__exit __NR_exit #define NR_syscalls __NR_syscalls diff --git a/include/asm-ppc/pci.h b/include/asm-ppc/pci.h index 9d162028dab..d2442cd72a5 100644 --- a/include/asm-ppc/pci.h +++ b/include/asm-ppc/pci.h @@ -102,12 +102,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, } #endif -/* - * At present there are very few 32-bit PPC machines that can have - * memory above the 4GB point, and we don't support that. - */ -#define pci_dac_dma_supported(pci_dev, mask) (0) - /* Return the index of the PCI controller for device PDEV. */ #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index @@ -145,8 +139,6 @@ pcibios_select_root(struct pci_dev *pdev, struct resource *res) return root; } -extern void pcibios_add_platform_entries(struct pci_dev *dev); - struct file; extern pgprot_t pci_phys_mem_access_prot(struct file *file, unsigned long pfn, diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h index bed452d4a5f..9d0ce9ff584 100644 --- a/include/asm-ppc/pgtable.h +++ b/include/asm-ppc/pgtable.h @@ -694,10 +694,14 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty) } #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \ - do { \ - __ptep_set_access_flags(__ptep, __entry, __dirty); \ - flush_tlb_page_nohash(__vma, __address); \ - } while(0) +({ \ + int __changed = !pte_same(*(__ptep), __entry); \ + if (__changed) { \ + __ptep_set_access_flags(__ptep, __entry, __dirty); \ + flush_tlb_page_nohash(__vma, __address); \ + } \ + __changed; \ +}) /* * Macro to mark a page protection value as "uncacheable". diff --git a/include/asm-s390/atomic.h b/include/asm-s390/atomic.h index c17bdbf2206..ea486952f77 100644 --- a/include/asm-s390/atomic.h +++ b/include/asm-s390/atomic.h @@ -24,7 +24,7 @@ */ typedef struct { - volatile int counter; + int counter; } __attribute__ ((aligned (4))) atomic_t; #define ATOMIC_INIT(i) { (i) } @@ -141,7 +141,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) #ifdef __s390x__ typedef struct { - volatile long long counter; + long long counter; } __attribute__ ((aligned (8))) atomic64_t; #define ATOMIC64_INIT(i) { (i) } diff --git a/include/asm-s390/cmb.h b/include/asm-s390/cmb.h index 241756f80df..021e7c3223e 100644 --- a/include/asm-s390/cmb.h +++ b/include/asm-s390/cmb.h @@ -88,7 +88,6 @@ extern u64 cmf_read(struct ccw_device *cdev, int index); * any **/ extern int cmf_readall(struct ccw_device *cdev, struct cmbdata*data); -extern void cmf_reset(struct ccw_device *cdev); #endif /* __KERNEL__ */ #endif /* S390_CMB_H */ diff --git a/include/asm-s390/pgtable.h b/include/asm-s390/pgtable.h index 8fe8d42e64c..0a307bb2f35 100644 --- a/include/asm-s390/pgtable.h +++ b/include/asm-s390/pgtable.h @@ -744,7 +744,12 @@ ptep_establish(struct vm_area_struct *vma, } #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \ - ptep_establish(__vma, __address, __ptep, __entry) +({ \ + int __changed = !pte_same(*(__ptep), __entry); \ + if (__changed) \ + ptep_establish(__vma, __address, __ptep, __entry); \ + __changed; \ +}) /* * Test and clear dirty bit in storage key. diff --git a/include/asm-s390/processor.h b/include/asm-s390/processor.h index e0fcea8c64c..3b972d4c6b2 100644 --- a/include/asm-s390/processor.h +++ b/include/asm-s390/processor.h @@ -216,6 +216,11 @@ static inline void cpu_relax(void) barrier(); } +static inline void psw_set_key(unsigned int key) +{ + asm volatile("spka 0(%0)" : : "d" (key)); +} + /* * Set PSW to specified value. */ @@ -352,8 +357,8 @@ extern void (*s390_base_ext_handler_fn)(void); /* * CPU idle notifier chain. */ -#define CPU_IDLE 0 -#define CPU_NOT_IDLE 1 +#define S390_CPU_IDLE 0 +#define S390_CPU_NOT_IDLE 1 struct notifier_block; int register_idle_notifier(struct notifier_block *nb); diff --git a/include/asm-s390/ptrace.h b/include/asm-s390/ptrace.h index fa6ca87080e..332ee73688f 100644 --- a/include/asm-s390/ptrace.h +++ b/include/asm-s390/ptrace.h @@ -470,14 +470,7 @@ struct user_regs_struct #define regs_return_value(regs)((regs)->gprs[2]) #define profile_pc(regs) instruction_pointer(regs) extern void show_regs(struct pt_regs * regs); -#endif - -static inline void -psw_set_key(unsigned int key) -{ - asm volatile("spka 0(%0)" : : "d" (key)); -} - +#endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ #endif /* _S390_PTRACE_H */ diff --git a/include/asm-s390/sclp.h b/include/asm-s390/sclp.h index 21ed6477321..cb9faf1ea5c 100644 --- a/include/asm-s390/sclp.h +++ b/include/asm-s390/sclp.h @@ -11,29 +11,6 @@ #include <linux/types.h> #include <asm/chpid.h> -struct sccb_header { - u16 length; - u8 function_code; - u8 control_mask[3]; - u16 response_code; -} __attribute__((packed)); - -#define LOADPARM_LEN 8 - -struct sclp_readinfo_sccb { - struct sccb_header header; /* 0-7 */ - u16 rnmax; /* 8-9 */ - u8 rnsize; /* 10 */ - u8 _reserved0[24 - 11]; /* 11-23 */ - u8 loadparm[LOADPARM_LEN]; /* 24-31 */ - u8 _reserved1[91 - 32]; /* 32-90 */ - u8 flags; /* 91 */ - u8 _reserved2[100 - 92]; /* 92-99 */ - u32 rnsize2; /* 100-103 */ - u64 rnmax2; /* 104-111 */ - u8 _reserved3[4096 - 112]; /* 112-4095 */ -} __attribute__((packed, aligned(4096))); - #define SCLP_CHP_INFO_MASK_SIZE 32 struct sclp_chp_info { @@ -42,12 +19,22 @@ struct sclp_chp_info { u8 configured[SCLP_CHP_INFO_MASK_SIZE]; }; -extern struct sclp_readinfo_sccb s390_readinfo_sccb; -extern void sclp_readinfo_early(void); -extern int sclp_sdias_blk_count(void); -extern int sclp_sdias_copy(void *dest, int blk_num, int nr_blks); -extern int sclp_chp_configure(struct chp_id chpid); -extern int sclp_chp_deconfigure(struct chp_id chpid); -extern int sclp_chp_read_info(struct sclp_chp_info *info); +#define LOADPARM_LEN 8 + +struct sclp_ipl_info { + int is_valid; + int has_dump; + char loadparm[LOADPARM_LEN]; +}; + +void sclp_readinfo_early(void); +void sclp_facilities_detect(void); +unsigned long long sclp_memory_detect(void); +int sclp_sdias_blk_count(void); +int sclp_sdias_copy(void *dest, int blk_num, int nr_blks); +int sclp_chp_configure(struct chp_id chpid); +int sclp_chp_deconfigure(struct chp_id chpid); +int sclp_chp_read_info(struct sclp_chp_info *info); +void sclp_get_ipl_info(struct sclp_ipl_info *info); #endif /* _ASM_S390_SCLP_H */ diff --git a/include/asm-s390/sfp-machine.h b/include/asm-s390/sfp-machine.h index 8ca8c77b2d0..4e16aede4b0 100644 --- a/include/asm-s390/sfp-machine.h +++ b/include/asm-s390/sfp-machine.h @@ -27,9 +27,9 @@ #define _FP_W_TYPE_SIZE 32 -#define _FP_W_TYPE unsigned long -#define _FP_WS_TYPE signed long -#define _FP_I_TYPE long +#define _FP_W_TYPE unsigned int +#define _FP_WS_TYPE signed int +#define _FP_I_TYPE int #define _FP_MUL_MEAT_S(R,X,Y) \ _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm) diff --git a/include/asm-s390/sfp-util.h b/include/asm-s390/sfp-util.h index 8cabcd23d97..0addc6466d9 100644 --- a/include/asm-s390/sfp-util.h +++ b/include/asm-s390/sfp-util.h @@ -51,6 +51,16 @@ wl = __wl; \ }) +#ifdef __s390x__ +#define udiv_qrnnd(q, r, n1, n0, d) \ + do { unsigned long __n; \ + unsigned int __r, __d; \ + __n = ((unsigned long)(n1) << 32) + n0; \ + __d = (d); \ + (q) = __n / __d; \ + (r) = __n % __d; \ + } while (0) +#else #define udiv_qrnnd(q, r, n1, n0, d) \ do { unsigned int __r; \ (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \ @@ -58,6 +68,7 @@ } while (0) extern unsigned long __udiv_qrnnd (unsigned int *, unsigned int, unsigned int , unsigned int); +#endif #define UDIV_NEEDS_NORMALIZATION 0 diff --git a/include/asm-s390/termbits.h b/include/asm-s390/termbits.h index 585c78a6e40..811b9a9cdc0 100644 --- a/include/asm-s390/termbits.h +++ b/include/asm-s390/termbits.h @@ -25,6 +25,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ diff --git a/include/asm-sh/cpu-sh4/freq.h b/include/asm-sh/cpu-sh4/freq.h index 86564e7a26a..39f41fcd509 100644 --- a/include/asm-sh/cpu-sh4/freq.h +++ b/include/asm-sh/cpu-sh4/freq.h @@ -24,6 +24,9 @@ #define FRQMR1 0xffc80014 #else #define FRQCR 0xffc00000 +#define FRQCR_PSTBY 0x0200 +#define FRQCR_PLLEN 0x0400 +#define FRQCR_CKOEN 0x0800 #endif #define MIN_DIVISOR_NR 0 #define MAX_DIVISOR_NR 3 diff --git a/include/asm-sh/dma.h b/include/asm-sh/dma.h index faf3051cd42..6034d4a29e7 100644 --- a/include/asm-sh/dma.h +++ b/include/asm-sh/dma.h @@ -13,6 +13,7 @@ #include <linux/spinlock.h> #include <linux/wait.h> +#include <linux/sched.h> #include <linux/sysdev.h> #include <asm/cpu/dma.h> diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h index a0e55b09e4f..aa80930ce8e 100644 --- a/include/asm-sh/io.h +++ b/include/asm-sh/io.h @@ -116,13 +116,13 @@ void __raw_readsl(unsigned long addr, void *data, int longlen); * redefined by userlevel programs. */ #ifdef __readb -# define readb(a) ({ unsigned long r_ = __raw_readb(a); mb(); r_; }) +# define readb(a) ({ unsigned int r_ = __raw_readb(a); mb(); r_; }) #endif #ifdef __raw_readw -# define readw(a) ({ unsigned long r_ = __raw_readw(a); mb(); r_; }) +# define readw(a) ({ unsigned int r_ = __raw_readw(a); mb(); r_; }) #endif #ifdef __raw_readl -# define readl(a) ({ unsigned long r_ = __raw_readl(a); mb(); r_; }) +# define readl(a) ({ unsigned int r_ = __raw_readl(a); mb(); r_; }) #endif #ifdef __raw_writeb diff --git a/include/asm-sh/pci.h b/include/asm-sh/pci.h index b1f9a9e0231..2757ce096ff 100644 --- a/include/asm-sh/pci.h +++ b/include/asm-sh/pci.h @@ -110,11 +110,6 @@ static inline void pcibios_penalize_isa_irq(int irq, int active) #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) #endif -/* Not supporting more than 32-bit PCI bus addresses now, but - * must satisfy references to this function. Change if needed. - */ -#define pci_dac_dma_supported(pci_dev, mask) (0) - #ifdef CONFIG_PCI static inline void pci_dma_burst_advice(struct pci_dev *pdev, enum pci_dma_burst_strategy *strat, @@ -134,10 +129,6 @@ int pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin); int pciauto_assign_resources(int busno, struct pci_channel *hose); #endif -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - #endif /* __KERNEL__ */ /* generic pci stuff */ diff --git a/include/asm-sh/se73180.h b/include/asm-sh/se73180.h index 3a4acb3e38a..907c062b4c9 100644 --- a/include/asm-sh/se73180.h +++ b/include/asm-sh/se73180.h @@ -1,9 +1,7 @@ -#ifndef __ASM_SH_HITACHI_SE73180_H -#define __ASM_SH_HITACHI_SE73180_H +#ifndef __ASM_SH_SE73180_H +#define __ASM_SH_SE73180_H /* - * include/asm-sh/se/se73180.h - * * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp> * * SH-Mobile SolutionEngine 73180 support @@ -62,4 +60,7 @@ #define __IO_PREFIX sh73180se #include <asm/io_generic.h> -#endif /* __ASM_SH_HITACHI_SE73180_H */ +/* arch/sh/boards/se/73180/irq.c */ +int shmse_irq_demux(int irq); + +#endif /* __ASM_SH_SE73180_H */ diff --git a/include/asm-sh/smp.h b/include/asm-sh/smp.h index 71ecddf70db..caa7b93f1bc 100644 --- a/include/asm-sh/smp.h +++ b/include/asm-sh/smp.h @@ -15,7 +15,7 @@ #ifdef CONFIG_SMP -#include <asm/spinlock.h> +#include <linux/spinlock.h> #include <asm/atomic.h> #include <asm/current.h> diff --git a/include/asm-sh/spinlock.h b/include/asm-sh/spinlock.h index 2586eef07d5..92f6e2008b2 100644 --- a/include/asm-sh/spinlock.h +++ b/include/asm-sh/spinlock.h @@ -11,6 +11,7 @@ #define __ASM_SH_SPINLOCK_H #include <asm/atomic.h> +#include <asm/spinlock_types.h> /* * Your basic SMP spinlocks, allowing only a single CPU anywhere @@ -42,7 +43,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock) static inline void __raw_spin_unlock(raw_spinlock_t *lock) { - assert_spin_locked(lock); + //assert_spin_locked(lock); lock->lock = 0; } @@ -88,6 +89,11 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw) __raw_spin_unlock(&rw->lock); } +static inline int __raw_write_can_lock(raw_rwlock_t *rw) +{ + return (atomic_read(&rw->counter) == RW_LOCK_BIAS); +} + static inline int __raw_read_trylock(raw_rwlock_t *lock) { atomic_t *count = (atomic_t*)lock; diff --git a/include/asm-sh/spinlock_types.h b/include/asm-sh/spinlock_types.h index 8c41b6c3aac..5c58134f2c4 100644 --- a/include/asm-sh/spinlock_types.h +++ b/include/asm-sh/spinlock_types.h @@ -9,7 +9,9 @@ typedef struct { volatile unsigned long lock; } raw_spinlock_t; -#define __SPIN_LOCK_UNLOCKED { 0 } +#define __RAW_SPIN_LOCK_UNLOCKED { 1 } + +#include <asm/atomic.h> typedef struct { raw_spinlock_t lock; diff --git a/include/asm-sh/termbits.h b/include/asm-sh/termbits.h index f1b7b46f4e9..7ee1b42eeab 100644 --- a/include/asm-sh/termbits.h +++ b/include/asm-sh/termbits.h @@ -17,6 +17,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ diff --git a/include/asm-sh64/pci.h b/include/asm-sh64/pci.h index aa8043089bb..57a67cf7a5c 100644 --- a/include/asm-sh64/pci.h +++ b/include/asm-sh64/pci.h @@ -72,11 +72,6 @@ static inline void pcibios_penalize_isa_irq(int irq, int active) #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) #endif -/* Not supporting more than 32-bit PCI bus addresses now, but - * must satisfy references to this function. Change if needed. - */ -#define pci_dac_dma_supported(pci_dev, mask) (0) - /* These macros should be used after a pci_map_sg call has been done * to get bus addresses of each of the SG entries and their lengths. * You should only work with the number of sg entries pci_map_sg @@ -104,10 +99,6 @@ extern void pcibios_fixup_irqs(void); extern int pciauto_assign_resources(int busno, struct pci_channel *hose); #endif -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - #endif /* __KERNEL__ */ /* generic pci stuff */ diff --git a/include/asm-sparc/pci.h b/include/asm-sparc/pci.h index a750c688408..b93b6c79e08 100644 --- a/include/asm-sparc/pci.h +++ b/include/asm-sparc/pci.h @@ -142,8 +142,6 @@ static inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask) return 1; } -#define pci_dac_dma_supported(dev, mask) (0) - #ifdef CONFIG_PCI static inline void pci_dma_burst_advice(struct pci_dev *pdev, enum pci_dma_burst_strategy *strat, @@ -154,10 +152,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, } #endif -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - #define PCI_DMA_ERROR_CODE (~(dma_addr_t)0x0) static inline int pci_dma_mapping_error(dma_addr_t dma_addr) diff --git a/include/asm-sparc/pgtable.h b/include/asm-sparc/pgtable.h index 4f0a5ba0d6a..59229aeba27 100644 --- a/include/asm-sparc/pgtable.h +++ b/include/asm-sparc/pgtable.h @@ -446,6 +446,17 @@ extern int io_remap_pfn_range(struct vm_area_struct *vma, #define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4)) #define GET_PFN(pfn) (pfn & 0x0fffffffUL) +#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS +#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \ +({ \ + int __changed = !pte_same(*(__ptep), __entry); \ + if (__changed) { \ + set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \ + flush_tlb_page(__vma, __address); \ + } \ + (sparc_cpu_model == sun4c) || __changed; \ +}) + #include <asm-generic/pgtable.h> #endif /* !(__ASSEMBLY__) */ diff --git a/include/asm-sparc64/cpudata.h b/include/asm-sparc64/cpudata.h index 03c385de761..445026fbec3 100644 --- a/include/asm-sparc64/cpudata.h +++ b/include/asm-sparc64/cpudata.h @@ -31,7 +31,7 @@ typedef struct { unsigned int ecache_size; unsigned int ecache_line_size; int core_id; - unsigned int __pad3; + int proc_id; } cpuinfo_sparc; DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data); diff --git a/include/asm-sparc64/dma-mapping.h b/include/asm-sparc64/dma-mapping.h index 9329429fb7f..c58ec1661df 100644 --- a/include/asm-sparc64/dma-mapping.h +++ b/include/asm-sparc64/dma-mapping.h @@ -15,8 +15,7 @@ static inline int dma_supported(struct device *dev, u64 mask) { - BUG_ON(dev->bus != &pci_bus_type && - dev->bus != &ebus_bus_type); + BUG_ON(dev->bus != &pci_bus_type); return pci_dma_supported(to_pci_dev(dev), mask); } @@ -24,8 +23,7 @@ dma_supported(struct device *dev, u64 mask) static inline int dma_set_mask(struct device *dev, u64 dma_mask) { - BUG_ON(dev->bus != &pci_bus_type && - dev->bus != &ebus_bus_type); + BUG_ON(dev->bus != &pci_bus_type); return pci_set_dma_mask(to_pci_dev(dev), dma_mask); } @@ -34,8 +32,7 @@ static inline void * dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t flag) { - BUG_ON(dev->bus != &pci_bus_type && - dev->bus != &ebus_bus_type); + BUG_ON(dev->bus != &pci_bus_type); return pci_iommu_ops->alloc_consistent(to_pci_dev(dev), size, dma_handle, flag); } @@ -44,8 +41,7 @@ static inline void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr_t dma_handle) { - BUG_ON(dev->bus != &pci_bus_type && - dev->bus != &ebus_bus_type); + BUG_ON(dev->bus != &pci_bus_type); pci_free_consistent(to_pci_dev(dev), size, cpu_addr, dma_handle); } @@ -54,8 +50,7 @@ static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr, size_t size, enum dma_data_direction direction) { - BUG_ON(dev->bus != &pci_bus_type && - dev->bus != &ebus_bus_type); + BUG_ON(dev->bus != &pci_bus_type); return pci_map_single(to_pci_dev(dev), cpu_addr, size, (int)direction); } @@ -64,8 +59,7 @@ static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, enum dma_data_direction direction) { - BUG_ON(dev->bus != &pci_bus_type && - dev->bus != &ebus_bus_type); + BUG_ON(dev->bus != &pci_bus_type); pci_unmap_single(to_pci_dev(dev), dma_addr, size, (int)direction); } @@ -75,8 +69,7 @@ dma_map_page(struct device *dev, struct page *page, unsigned long offset, size_t size, enum dma_data_direction direction) { - BUG_ON(dev->bus != &pci_bus_type && - dev->bus != &ebus_bus_type); + BUG_ON(dev->bus != &pci_bus_type); return pci_map_page(to_pci_dev(dev), page, offset, size, (int)direction); } @@ -85,8 +78,7 @@ static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, enum dma_data_direction direction) { - BUG_ON(dev->bus != &pci_bus_type && - dev->bus != &ebus_bus_type); + BUG_ON(dev->bus != &pci_bus_type); pci_unmap_page(to_pci_dev(dev), dma_address, size, (int)direction); } @@ -95,8 +87,7 @@ static inline int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, enum dma_data_direction direction) { - BUG_ON(dev->bus != &pci_bus_type && - dev->bus != &ebus_bus_type); + BUG_ON(dev->bus != &pci_bus_type); return pci_map_sg(to_pci_dev(dev), sg, nents, (int)direction); } @@ -105,8 +96,7 @@ static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, enum dma_data_direction direction) { - BUG_ON(dev->bus != &pci_bus_type && - dev->bus != &ebus_bus_type); + BUG_ON(dev->bus != &pci_bus_type); pci_unmap_sg(to_pci_dev(dev), sg, nhwentries, (int)direction); } @@ -115,8 +105,7 @@ static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) { - BUG_ON(dev->bus != &pci_bus_type && - dev->bus != &ebus_bus_type); + BUG_ON(dev->bus != &pci_bus_type); pci_dma_sync_single_for_cpu(to_pci_dev(dev), dma_handle, size, (int)direction); @@ -126,8 +115,7 @@ static inline void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) { - BUG_ON(dev->bus != &pci_bus_type && - dev->bus != &ebus_bus_type); + BUG_ON(dev->bus != &pci_bus_type); pci_dma_sync_single_for_device(to_pci_dev(dev), dma_handle, size, (int)direction); @@ -137,8 +125,7 @@ static inline void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, enum dma_data_direction direction) { - BUG_ON(dev->bus != &pci_bus_type && - dev->bus != &ebus_bus_type); + BUG_ON(dev->bus != &pci_bus_type); pci_dma_sync_sg_for_cpu(to_pci_dev(dev), sg, nelems, (int)direction); } @@ -147,8 +134,7 @@ static inline void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems, enum dma_data_direction direction) { - BUG_ON(dev->bus != &pci_bus_type && - dev->bus != &ebus_bus_type); + BUG_ON(dev->bus != &pci_bus_type); pci_dma_sync_sg_for_device(to_pci_dev(dev), sg, nelems, (int)direction); } @@ -162,6 +148,22 @@ dma_mapping_error(dma_addr_t dma_addr) #else struct device; +struct page; +struct scatterlist; + +static inline int +dma_supported(struct device *dev, u64 mask) +{ + BUG(); + return 0; +} + +static inline int +dma_set_mask(struct device *dev, u64 dma_mask) +{ + BUG(); + return 0; +} static inline void *dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t flag) @@ -176,6 +178,52 @@ static inline void dma_free_coherent(struct device *dev, size_t size, BUG(); } +static inline dma_addr_t +dma_map_single(struct device *dev, void *cpu_addr, size_t size, + enum dma_data_direction direction) +{ + BUG(); + return 0; +} + +static inline void +dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, + enum dma_data_direction direction) +{ + BUG(); +} + +static inline dma_addr_t +dma_map_page(struct device *dev, struct page *page, + unsigned long offset, size_t size, + enum dma_data_direction direction) +{ + BUG(); + return 0; +} + +static inline void +dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, + enum dma_data_direction direction) +{ + BUG(); +} + +static inline int +dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, + enum dma_data_direction direction) +{ + BUG(); + return 0; +} + +static inline void +dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, + enum dma_data_direction direction) +{ + BUG(); +} + static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) @@ -190,6 +238,27 @@ dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t siz BUG(); } +static inline void +dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, + enum dma_data_direction direction) +{ + BUG(); +} + +static inline void +dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems, + enum dma_data_direction direction) +{ + BUG(); +} + +static inline int +dma_mapping_error(dma_addr_t dma_addr) +{ + BUG(); + return 0; +} + #endif /* PCI */ diff --git a/include/asm-sparc64/hypervisor.h b/include/asm-sparc64/hypervisor.h index 5cdb1ff0483..db2130a95d6 100644 --- a/include/asm-sparc64/hypervisor.h +++ b/include/asm-sparc64/hypervisor.h @@ -1097,6 +1097,80 @@ extern unsigned long sun4v_mach_set_soft_state(unsigned long soft_state, */ #define HV_FAST_MACH_GET_SOFT_STATE 0x71 +/* svc_send() + * TRAP: HV_FAST_TRAP + * FUNCTION: HV_FAST_SVC_SEND + * ARG0: service ID + * ARG1: buffer real address + * ARG2: buffer size + * RET0: STATUS + * RET1: sent_bytes + * + * Be careful, all output registers are clobbered by this operation, + * so for example it is not possible to save away a value in %o4 + * across the trap. + */ +#define HV_FAST_SVC_SEND 0x80 + +/* svc_recv() + * TRAP: HV_FAST_TRAP + * FUNCTION: HV_FAST_SVC_RECV + * ARG0: service ID + * ARG1: buffer real address + * ARG2: buffer size + * RET0: STATUS + * RET1: recv_bytes + * + * Be careful, all output registers are clobbered by this operation, + * so for example it is not possible to save away a value in %o4 + * across the trap. + */ +#define HV_FAST_SVC_RECV 0x81 + +/* svc_getstatus() + * TRAP: HV_FAST_TRAP + * FUNCTION: HV_FAST_SVC_GETSTATUS + * ARG0: service ID + * RET0: STATUS + * RET1: status bits + */ +#define HV_FAST_SVC_GETSTATUS 0x82 + +/* svc_setstatus() + * TRAP: HV_FAST_TRAP + * FUNCTION: HV_FAST_SVC_SETSTATUS + * ARG0: service ID + * ARG1: bits to set + * RET0: STATUS + */ +#define HV_FAST_SVC_SETSTATUS 0x83 + +/* svc_clrstatus() + * TRAP: HV_FAST_TRAP + * FUNCTION: HV_FAST_SVC_CLRSTATUS + * ARG0: service ID + * ARG1: bits to clear + * RET0: STATUS + */ +#define HV_FAST_SVC_CLRSTATUS 0x84 + +#ifndef __ASSEMBLY__ +extern unsigned long sun4v_svc_send(unsigned long svc_id, + unsigned long buffer, + unsigned long buffer_size, + unsigned long *sent_bytes); +extern unsigned long sun4v_svc_recv(unsigned long svc_id, + unsigned long buffer, + unsigned long buffer_size, + unsigned long *recv_bytes); +extern unsigned long sun4v_svc_getstatus(unsigned long svc_id, + unsigned long *status_bits); +extern unsigned long sun4v_svc_setstatus(unsigned long svc_id, + unsigned long status_bits); +extern unsigned long sun4v_svc_clrstatus(unsigned long svc_id, + unsigned long status_bits); +#endif + /* Trap trace services. * * The hypervisor provides a trap tracing capability for privileged @@ -2541,8 +2615,9 @@ struct ldc_mtable_entry { /* ldc_revoke() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_LDC_REVOKE - * ARG0: cookie - * ARG1: ldc_mtable_entry cookie + * ARG0: channel ID + * ARG1: cookie + * ARG2: ldc_mtable_entry cookie * RET0: status */ #define HV_FAST_LDC_REVOKE 0xef @@ -2589,7 +2664,8 @@ extern unsigned long sun4v_ldc_mapin(unsigned long channel, unsigned long *ra, unsigned long *perm); extern unsigned long sun4v_ldc_unmap(unsigned long ra); -extern unsigned long sun4v_ldc_revoke(unsigned long cookie, +extern unsigned long sun4v_ldc_revoke(unsigned long channel, + unsigned long cookie, unsigned long mte_cookie); #endif @@ -2724,6 +2800,105 @@ struct hv_mmu_statistics { */ #define HV_FAST_MMUSTAT_INFO 0x103 +#ifndef __ASSEMBLY__ +extern unsigned long sun4v_mmustat_conf(unsigned long ra, unsigned long *orig_ra); +extern unsigned long sun4v_mmustat_info(unsigned long *ra); +#endif + +/* NCS crypto services */ + +/* ncs_request() sub-function numbers */ +#define HV_NCS_QCONF 0x01 +#define HV_NCS_QTAIL_UPDATE 0x02 + +#ifndef __ASSEMBLY__ +struct hv_ncs_queue_entry { + /* MAU Control Register */ + unsigned long mau_control; +#define MAU_CONTROL_INV_PARITY 0x0000000000002000 +#define MAU_CONTROL_STRAND 0x0000000000001800 +#define MAU_CONTROL_BUSY 0x0000000000000400 +#define MAU_CONTROL_INT 0x0000000000000200 +#define MAU_CONTROL_OP 0x00000000000001c0 +#define MAU_CONTROL_OP_SHIFT 6 +#define MAU_OP_LOAD_MA_MEMORY 0x0 +#define MAU_OP_STORE_MA_MEMORY 0x1 +#define MAU_OP_MODULAR_MULT 0x2 +#define MAU_OP_MODULAR_REDUCE 0x3 +#define MAU_OP_MODULAR_EXP_LOOP 0x4 +#define MAU_CONTROL_LEN 0x000000000000003f +#define MAU_CONTROL_LEN_SHIFT 0 + + /* Real address of bytes to load or store bytes + * into/out-of the MAU. + */ + unsigned long mau_mpa; + + /* Modular Arithmetic MA Offset Register. */ + unsigned long mau_ma; + + /* Modular Arithmetic N Prime Register. */ + unsigned long mau_np; +}; + +struct hv_ncs_qconf_arg { + unsigned long mid; /* MAU ID, 1 per core on Niagara */ + unsigned long base; /* Real address base of queue */ + unsigned long end; /* Real address end of queue */ + unsigned long num_ents; /* Number of entries in queue */ +}; + +struct hv_ncs_qtail_update_arg { + unsigned long mid; /* MAU ID, 1 per core on Niagara */ + unsigned long tail; /* New tail index to use */ + unsigned long syncflag; /* only SYNCFLAG_SYNC is implemented */ +#define HV_NCS_SYNCFLAG_SYNC 0x00 +#define HV_NCS_SYNCFLAG_ASYNC 0x01 +}; +#endif + +/* ncs_request() + * TRAP: HV_FAST_TRAP + * FUNCTION: HV_FAST_NCS_REQUEST + * ARG0: NCS sub-function + * ARG1: sub-function argument real address + * ARG2: size in bytes of sub-function argument + * RET0: status + * + * The MAU chip of the Niagara processor is not directly accessible + * to privileged code, instead it is programmed indirectly via this + * hypervisor API. + * + * The interfaces defines a queue of MAU operations to perform. + * Privileged code registers a queue with the hypervisor by invoking + * this HVAPI with the HV_NCS_QCONF sub-function, which defines the + * base, end, and number of entries of the queue. Each queue entry + * contains a MAU register struct block. + * + * The privileged code then proceeds to add entries to the queue and + * then invoke the HV_NCS_QTAIL_UPDATE sub-function. Since only + * synchronous operations are supported by the current hypervisor, + * HV_NCS_QTAIL_UPDATE will run all the pending queue entries to + * completion and return HV_EOK, or return an error code. + * + * The real address of the sub-function argument must be aligned on at + * least an 8-byte boundary. + * + * The tail argument of HV_NCS_QTAIL_UPDATE is an index, not a byte + * offset, into the queue and must be less than or equal the 'num_ents' + * argument given in the HV_NCS_QCONF call. + */ +#define HV_FAST_NCS_REQUEST 0x110 + +#ifndef __ASSEMBLY__ +extern unsigned long sun4v_ncs_request(unsigned long request, + unsigned long arg_ra, + unsigned long arg_size); +#endif + +#define HV_FAST_FIRE_GET_PERFREG 0x120 +#define HV_FAST_FIRE_SET_PERFREG 0x121 + /* Function numbers for HV_CORE_TRAP. */ #define HV_CORE_SET_VER 0x00 #define HV_CORE_PUTCHAR 0x01 diff --git a/include/asm-sparc64/irq.h b/include/asm-sparc64/irq.h index 5d233b42fe1..90781e34a95 100644 --- a/include/asm-sparc64/irq.h +++ b/include/asm-sparc64/irq.h @@ -46,6 +46,7 @@ extern void irq_install_pre_handler(int virt_irq, #define irq_canonicalize(irq) (irq) extern unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap); extern unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino); +extern unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino); extern unsigned int sun4v_build_msi(u32 devhandle, unsigned int *virt_irq_p, unsigned int msi_devino_start, unsigned int msi_devino_end); diff --git a/include/asm-sparc64/mdesc.h b/include/asm-sparc64/mdesc.h index 124eb8ca237..c6383982b53 100644 --- a/include/asm-sparc64/mdesc.h +++ b/include/asm-sparc64/mdesc.h @@ -15,6 +15,7 @@ struct mdesc_node { u64 node; unsigned int unique_id; unsigned int num_arcs; + unsigned int irqs[2]; struct property *properties; struct mdesc_node *hash_next; struct mdesc_node *allnodes_next; diff --git a/include/asm-sparc64/parport.h b/include/asm-sparc64/parport.h index 6340a5253a3..23cc63f049a 100644 --- a/include/asm-sparc64/parport.h +++ b/include/asm-sparc64/parport.h @@ -145,7 +145,7 @@ static int parport_isa_probe(int count) */ if (parport_pc_probe_port(base, base + 0x400, child->irq, PARPORT_DMA_NOFIFO, - child->bus->self)) + &child->bus->self->dev)) count++; } } @@ -199,7 +199,8 @@ static int parport_pc_find_nonpci_ports (int autoirq, int autodma) if (parport_pc_probe_port(base, base + 0x400, edev->irqs[0], - count, ebus->self)) + count, + &ebus->self->dev)) count++; } } diff --git a/include/asm-sparc64/pci.h b/include/asm-sparc64/pci.h index 47cea16e1ba..e11ac100f04 100644 --- a/include/asm-sparc64/pci.h +++ b/include/asm-sparc64/pci.h @@ -206,49 +206,6 @@ extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask); #define PCI64_REQUIRED_MASK (~(dma64_addr_t)0) #define PCI64_ADDR_BASE 0xfffc000000000000UL -/* Usage of the pci_dac_foo interfaces is only valid if this - * test passes. - */ -#define pci_dac_dma_supported(pci_dev, mask) \ - ((((mask) & PCI64_REQUIRED_MASK) == PCI64_REQUIRED_MASK) ? 1 : 0) - -static inline dma64_addr_t -pci_dac_page_to_dma(struct pci_dev *pdev, struct page *page, unsigned long offset, int direction) -{ - return (PCI64_ADDR_BASE + - __pa(page_address(page)) + offset); -} - -static inline struct page * -pci_dac_dma_to_page(struct pci_dev *pdev, dma64_addr_t dma_addr) -{ - unsigned long paddr = (dma_addr & PAGE_MASK) - PCI64_ADDR_BASE; - - return virt_to_page(__va(paddr)); -} - -static inline unsigned long -pci_dac_dma_to_offset(struct pci_dev *pdev, dma64_addr_t dma_addr) -{ - return (dma_addr & ~PAGE_MASK); -} - -static inline void -pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction) -{ - /* DAC cycle addressing does not make use of the - * PCI controller's streaming cache, so nothing to do. - */ -} - -static inline void -pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction) -{ - /* DAC cycle addressing does not make use of the - * PCI controller's streaming cache, so nothing to do. - */ -} - #define PCI_DMA_ERROR_CODE (~(dma_addr_t)0x0) static inline int pci_dma_mapping_error(dma_addr_t dma_addr) @@ -303,10 +260,6 @@ pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, extern struct resource *pcibios_select_root(struct pci_dev *, struct resource *); -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) { return PCI_IRQ_NONE; diff --git a/include/asm-sparc64/smp.h b/include/asm-sparc64/smp.h index f76e1492add..4fb8c4bfb84 100644 --- a/include/asm-sparc64/smp.h +++ b/include/asm-sparc64/smp.h @@ -33,6 +33,8 @@ extern cpumask_t phys_cpu_present_map; #define cpu_possible_map phys_cpu_present_map extern cpumask_t cpu_sibling_map[NR_CPUS]; +extern cpumask_t cpu_core_map[NR_CPUS]; +extern int sparc64_multi_core; /* * General functions that each host system must provide. diff --git a/include/asm-sparc64/tlb.h b/include/asm-sparc64/tlb.h index 7af1e1109c4..349d1d3e9c2 100644 --- a/include/asm-sparc64/tlb.h +++ b/include/asm-sparc64/tlb.h @@ -2,6 +2,7 @@ #define _SPARC64_TLB_H #include <linux/swap.h> +#include <linux/pagemap.h> #include <asm/pgalloc.h> #include <asm/tlbflush.h> #include <asm/mmu_context.h> diff --git a/include/asm-sparc64/topology.h b/include/asm-sparc64/topology.h index e0d450d600e..290ac75f385 100644 --- a/include/asm-sparc64/topology.h +++ b/include/asm-sparc64/topology.h @@ -1,12 +1,17 @@ #ifndef _ASM_SPARC64_TOPOLOGY_H #define _ASM_SPARC64_TOPOLOGY_H -#include <asm/spitfire.h> -#define smt_capable() (tlb_type == hypervisor) +#ifdef CONFIG_SMP +#define topology_physical_package_id(cpu) (cpu_data(cpu).proc_id) +#define topology_core_id(cpu) (cpu_data(cpu).core_id) +#define topology_core_siblings(cpu) (cpu_core_map[cpu]) +#define topology_thread_siblings(cpu) (cpu_sibling_map[cpu]) +#define mc_capable() (sparc64_multi_core) +#define smt_capable() (sparc64_multi_core) +#endif /* CONFIG_SMP */ #include <asm-generic/topology.h> -#define topology_core_id(cpu) (cpu_data(cpu).core_id) -#define topology_thread_siblings(cpu) (cpu_sibling_map[cpu]) +#define cpu_coregroup_map(cpu) (cpu_core_map[cpu]) #endif /* _ASM_SPARC64_TOPOLOGY_H */ diff --git a/include/asm-um/a.out.h b/include/asm-um/a.out.h index 50cee7b296f..7016b893ac9 100644 --- a/include/asm-um/a.out.h +++ b/include/asm-um/a.out.h @@ -5,6 +5,7 @@ #include "choose-mode.h" #undef STACK_TOP +#undef STACK_TOP_MAX extern unsigned long stacksizelim; diff --git a/include/asm-um/bug.h b/include/asm-um/bug.h index 3357c5e2468..9e33b864c35 100644 --- a/include/asm-um/bug.h +++ b/include/asm-um/bug.h @@ -1,6 +1,6 @@ #ifndef __UM_BUG_H #define __UM_BUG_H -#include <asm/arch/bug.h> +#include <asm-generic/bug.h> #endif diff --git a/include/asm-um/common.lds.S b/include/asm-um/common.lds.S index f5de80c31e8..e3f010bd12b 100644 --- a/include/asm-um/common.lds.S +++ b/include/asm-um/common.lds.S @@ -20,6 +20,8 @@ __ex_table : { *(__ex_table) } __stop___ex_table = .; + BUG_TABLE + __uml_setup_start = .; .uml.setup.init : { *(.uml.setup.init) } __uml_setup_end = .; diff --git a/include/asm-um/paravirt.h b/include/asm-um/paravirt.h new file mode 100644 index 00000000000..9d6aaad80b5 --- /dev/null +++ b/include/asm-um/paravirt.h @@ -0,0 +1,6 @@ +#ifndef __UM_PARAVIRT_H +#define __UM_PARAVIRT_H + +#include "asm/arch/paravirt.h" + +#endif diff --git a/include/asm-v850/pci.h b/include/asm-v850/pci.h index 4581826e1ca..de2a7d0a81c 100644 --- a/include/asm-v850/pci.h +++ b/include/asm-v850/pci.h @@ -116,8 +116,4 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); extern void pci_iounmap (struct pci_dev *dev, void __iomem *addr); -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - #endif /* __V850_PCI_H__ */ diff --git a/include/asm-v850/rte_cb.h b/include/asm-v850/rte_cb.h index 9f7f02cb039..e85d261b79b 100644 --- a/include/asm-v850/rte_cb.h +++ b/include/asm-v850/rte_cb.h @@ -64,7 +64,6 @@ /* As we don't really support PCI DMA to cpu memory, and use bounce-buffers instead, perversely enough, this becomes always true! */ # define pci_dma_supported(dev, mask) 1 -# define pci_dac_dma_supported(dev, mask) 0 # define pcibios_assign_all_busses() 1 #endif /* CONFIG_RTE_MB_A_PCI */ diff --git a/include/asm-v850/termbits.h b/include/asm-v850/termbits.h index f3b43303208..35412f7f3ee 100644 --- a/include/asm-v850/termbits.h +++ b/include/asm-v850/termbits.h @@ -17,6 +17,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ diff --git a/include/asm-x86_64/alternative.h b/include/asm-x86_64/alternative.h index a0942764076..eea7aecfac7 100644 --- a/include/asm-x86_64/alternative.h +++ b/include/asm-x86_64/alternative.h @@ -5,6 +5,41 @@ #include <linux/types.h> #include <linux/stddef.h> + +/* + * Alternative inline assembly for SMP. + * + * The LOCK_PREFIX macro defined here replaces the LOCK and + * LOCK_PREFIX macros used everywhere in the source tree. + * + * SMP alternatives use the same data structures as the other + * alternatives and the X86_FEATURE_UP flag to indicate the case of a + * UP system running a SMP kernel. The existing apply_alternatives() + * works fine for patching a SMP kernel for UP. + * + * The SMP alternative tables can be kept after boot and contain both + * UP and SMP versions of the instructions to allow switching back to + * SMP at runtime, when hotplugging in a new CPU, which is especially + * useful in virtualized environments. + * + * The very common lock prefix is handled as special case in a + * separate table which is a pure address list without replacement ptr + * and size information. That keeps the table sizes small. + */ + +#ifdef CONFIG_SMP +#define LOCK_PREFIX \ + ".section .smp_locks,\"a\"\n" \ + " .align 8\n" \ + " .quad 661f\n" /* address */ \ + ".previous\n" \ + "661:\n\tlock; " + +#else /* ! CONFIG_SMP */ +#define LOCK_PREFIX "" +#endif + +/* This must be included *after* the definition of LOCK_PREFIX */ #include <asm/cpufeature.h> struct alt_instr { @@ -108,39 +143,6 @@ static inline void alternatives_smp_switch(int smp) {} */ #define ASM_OUTPUT2(a, b) a, b -/* - * Alternative inline assembly for SMP. - * - * The LOCK_PREFIX macro defined here replaces the LOCK and - * LOCK_PREFIX macros used everywhere in the source tree. - * - * SMP alternatives use the same data structures as the other - * alternatives and the X86_FEATURE_UP flag to indicate the case of a - * UP system running a SMP kernel. The existing apply_alternatives() - * works fine for patching a SMP kernel for UP. - * - * The SMP alternative tables can be kept after boot and contain both - * UP and SMP versions of the instructions to allow switching back to - * SMP at runtime, when hotplugging in a new CPU, which is especially - * useful in virtualized environments. - * - * The very common lock prefix is handled as special case in a - * separate table which is a pure address list without replacement ptr - * and size information. That keeps the table sizes small. - */ - -#ifdef CONFIG_SMP -#define LOCK_PREFIX \ - ".section .smp_locks,\"a\"\n" \ - " .align 8\n" \ - " .quad 661f\n" /* address */ \ - ".previous\n" \ - "661:\n\tlock; " - -#else /* ! CONFIG_SMP */ -#define LOCK_PREFIX "" -#endif - struct paravirt_patch; #ifdef CONFIG_PARAVIRT void apply_paravirt(struct paravirt_patch *start, struct paravirt_patch *end); diff --git a/include/asm-x86_64/boot.h b/include/asm-x86_64/boot.h index 96b228e6e79..3c46cea8db7 100644 --- a/include/asm-x86_64/boot.h +++ b/include/asm-x86_64/boot.h @@ -1,15 +1 @@ -#ifndef _LINUX_BOOT_H -#define _LINUX_BOOT_H - -/* Don't touch these, unless you really know what you're doing. */ -#define DEF_INITSEG 0x9000 -#define DEF_SYSSEG 0x1000 -#define DEF_SETUPSEG 0x9020 -#define DEF_SYSSIZE 0x7F00 - -/* Internal svga startup constants */ -#define NORMAL_VGA 0xffff /* 80x25 mode */ -#define EXTENDED_VGA 0xfffe /* 80x50 mode */ -#define ASK_VGA 0xfffd /* ask for it at bootup */ - -#endif +#include <asm-i386/boot.h> diff --git a/include/asm-x86_64/bootparam.h b/include/asm-x86_64/bootparam.h new file mode 100644 index 00000000000..aa82e5238d8 --- /dev/null +++ b/include/asm-x86_64/bootparam.h @@ -0,0 +1 @@ +#include <asm-i386/bootparam.h> diff --git a/include/asm-x86_64/cpufeature.h b/include/asm-x86_64/cpufeature.h index 0b3c686139f..8baefc3beb2 100644 --- a/include/asm-x86_64/cpufeature.h +++ b/include/asm-x86_64/cpufeature.h @@ -7,115 +7,24 @@ #ifndef __ASM_X8664_CPUFEATURE_H #define __ASM_X8664_CPUFEATURE_H -#define NCAPINTS 7 /* N 32-bit words worth of info */ +#include <asm-i386/cpufeature.h> -/* Intel-defined CPU features, CPUID level 0x00000001, word 0 */ -#define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */ -#define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */ -#define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */ -#define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */ -#define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */ -#define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */ -#define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */ -#define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Architecture */ -#define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */ -#define X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */ -#define X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */ -#define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */ -#define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */ -#define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */ -#define X86_FEATURE_CMOV (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */ -#define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */ -#define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */ -#define X86_FEATURE_PN (0*32+18) /* Processor serial number */ -#define X86_FEATURE_CLFLSH (0*32+19) /* Supports the CLFLUSH instruction */ -#define X86_FEATURE_DS (0*32+21) /* Debug Store */ -#define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */ -#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */ -#define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */ - /* of FPU context), and CR4.OSFXSR available */ -#define X86_FEATURE_XMM (0*32+25) /* Streaming SIMD Extensions */ -#define X86_FEATURE_XMM2 (0*32+26) /* Streaming SIMD Extensions-2 */ -#define X86_FEATURE_SELFSNOOP (0*32+27) /* CPU self snoop */ -#define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */ -#define X86_FEATURE_ACC (0*32+29) /* Automatic clock control */ -#define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */ - -/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ -/* Don't duplicate feature flags which are redundant with Intel! */ -#define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */ -#define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */ -#define X86_FEATURE_FXSR_OPT (1*32+25) /* FXSR optimizations */ -#define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */ -#define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */ -#define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */ -#define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */ - -/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ -#define X86_FEATURE_RECOVERY (2*32+ 0) /* CPU in recovery mode */ -#define X86_FEATURE_LONGRUN (2*32+ 1) /* Longrun power control */ -#define X86_FEATURE_LRTI (2*32+ 3) /* LongRun table interface */ - -/* Other features, Linux-defined mapping, word 3 */ -/* This range is used for feature bits which conflict or are synthesized */ -#define X86_FEATURE_CXMMX (3*32+ 0) /* Cyrix MMX extensions */ -#define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */ -#define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */ -#define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */ -#define X86_FEATURE_REP_GOOD (3*32+ 4) /* rep microcode works well on this CPU */ -#define X86_FEATURE_CONSTANT_TSC (3*32+5) /* TSC runs at constant rate */ -#define X86_FEATURE_SYNC_RDTSC (3*32+6) /* RDTSC syncs CPU core */ -#define X86_FEATURE_FXSAVE_LEAK (3*32+7) /* FIP/FOP/FDP leaks through FXSAVE */ -#define X86_FEATURE_UP (3*32+8) /* SMP kernel running on UP */ -#define X86_FEATURE_ARCH_PERFMON (3*32+9) /* Intel Architectural PerfMon */ -#define X86_FEATURE_PEBS (3*32+10) /* Precise-Event Based Sampling */ -#define X86_FEATURE_BTS (3*32+11) /* Branch Trace Store */ - -/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ -#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ -#define X86_FEATURE_MWAIT (4*32+ 3) /* Monitor/Mwait support */ -#define X86_FEATURE_DSCPL (4*32+ 4) /* CPL Qualified Debug Store */ -#define X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */ -#define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */ -#define X86_FEATURE_CID (4*32+10) /* Context ID */ -#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */ -#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */ - -/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ -#define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */ -#define X86_FEATURE_XSTORE_EN (5*32+ 3) /* on-CPU RNG enabled */ -#define X86_FEATURE_XCRYPT (5*32+ 6) /* on-CPU crypto (xcrypt insn) */ -#define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* on-CPU crypto enabled */ - -/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ -#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ -#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ - -#define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) -#define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability) - -#define cpu_has_fpu 1 +#undef cpu_has_vme #define cpu_has_vme 0 -#define cpu_has_de 1 -#define cpu_has_pse 1 -#define cpu_has_tsc 1 + +#undef cpu_has_pae #define cpu_has_pae ___BUG___ -#define cpu_has_pge 1 -#define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC) -#define cpu_has_mtrr 1 -#define cpu_has_mmx 1 -#define cpu_has_fxsr 1 -#define cpu_has_xmm 1 -#define cpu_has_xmm2 1 -#define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3) -#define cpu_has_ht boot_cpu_has(X86_FEATURE_HT) + +#undef cpu_has_mp #define cpu_has_mp 1 /* XXX */ + +#undef cpu_has_k6_mtrr #define cpu_has_k6_mtrr 0 + +#undef cpu_has_cyrix_arr #define cpu_has_cyrix_arr 0 + +#undef cpu_has_centaur_mcr #define cpu_has_centaur_mcr 0 -#define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH) -#define cpu_has_ds boot_cpu_has(X86_FEATURE_DS) -#define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS) -#define cpu_has_bts boot_cpu_has(X86_FEATURE_BTS) #endif /* __ASM_X8664_CPUFEATURE_H */ diff --git a/include/asm-x86_64/e820.h b/include/asm-x86_64/e820.h index 6216fa3f280..3486e701bd8 100644 --- a/include/asm-x86_64/e820.h +++ b/include/asm-x86_64/e820.h @@ -11,8 +11,6 @@ #ifndef __E820_HEADER #define __E820_HEADER -#include <linux/mmzone.h> - #define E820MAP 0x2d0 /* our map */ #define E820MAX 128 /* number of entries in E820MAP */ #define E820NR 0x1e8 /* # entries in E820MAP */ @@ -30,7 +28,7 @@ struct e820entry { } __attribute__((packed)); struct e820map { - int nr_map; + u32 nr_map; struct e820entry map[E820MAX]; }; diff --git a/include/asm-x86_64/pci.h b/include/asm-x86_64/pci.h index 49c5e928059..bda94fd5176 100644 --- a/include/asm-x86_64/pci.h +++ b/include/asm-x86_64/pci.h @@ -54,14 +54,6 @@ extern int iommu_setup(char *opt); #if defined(CONFIG_IOMMU) || defined(CONFIG_CALGARY_IOMMU) -/* - * x86-64 always supports DAC, but sometimes it is useful to force - * devices through the IOMMU to get automatic sg list merging. - * Optional right now. - */ -extern int iommu_sac_force; -#define pci_dac_dma_supported(pci_dev, mask) (!iommu_sac_force) - #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ dma_addr_t ADDR_NAME; #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \ @@ -78,8 +70,6 @@ extern int iommu_sac_force; #else /* No IOMMU */ -#define pci_dac_dma_supported(pci_dev, mask) 1 - #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) #define pci_unmap_addr(PTR, ADDR_NAME) (0) @@ -91,36 +81,6 @@ extern int iommu_sac_force; #include <asm-generic/pci-dma-compat.h> -static inline dma64_addr_t -pci_dac_page_to_dma(struct pci_dev *pdev, struct page *page, unsigned long offset, int direction) -{ - return ((dma64_addr_t) page_to_phys(page) + - (dma64_addr_t) offset); -} - -static inline struct page * -pci_dac_dma_to_page(struct pci_dev *pdev, dma64_addr_t dma_addr) -{ - return virt_to_page(__va(dma_addr)); -} - -static inline unsigned long -pci_dac_dma_to_offset(struct pci_dev *pdev, dma64_addr_t dma_addr) -{ - return (dma_addr & ~PAGE_MASK); -} - -static inline void -pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction) -{ -} - -static inline void -pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction) -{ - flush_write_buffers(); -} - #ifdef CONFIG_PCI static inline void pci_dma_burst_advice(struct pci_dev *pdev, enum pci_dma_burst_strategy *strat, @@ -135,10 +95,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, enum pci_mmap_state mmap_state, int write_combine); -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - #endif /* __KERNEL__ */ /* generic pci stuff */ diff --git a/include/asm-x86_64/pgtable.h b/include/asm-x86_64/pgtable.h index 08b9831f2e1..0a71e0b9a61 100644 --- a/include/asm-x86_64/pgtable.h +++ b/include/asm-x86_64/pgtable.h @@ -395,12 +395,14 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) * bit at the same time. */ #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \ - do { \ - if (__dirty) { \ - set_pte(__ptep, __entry); \ - flush_tlb_page(__vma, __address); \ - } \ - } while (0) +({ \ + int __changed = !pte_same(*(__ptep), __entry); \ + if (__changed && __dirty) { \ + set_pte(__ptep, __entry); \ + flush_tlb_page(__vma, __address); \ + } \ + __changed; \ +}) /* Encode and de-code a swap entry */ #define __swp_type(x) (((x).val >> 1) & 0x3f) diff --git a/include/asm-x86_64/processor.h b/include/asm-x86_64/processor.h index 461ffe4c1fc..efc87a5aff7 100644 --- a/include/asm-x86_64/processor.h +++ b/include/asm-x86_64/processor.h @@ -100,6 +100,7 @@ extern char ignore_irq13; extern void identify_cpu(struct cpuinfo_x86 *); extern void print_cpu_info(struct cpuinfo_x86 *); +extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); extern unsigned short num_cache_leaves; @@ -368,8 +369,6 @@ static inline void sync_core(void) asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory"); } -#define cpu_has_fpu 1 - #define ARCH_HAS_PREFETCH static inline void prefetch(void *x) { diff --git a/include/asm-x86_64/required-features.h b/include/asm-x86_64/required-features.h new file mode 100644 index 00000000000..e80d5761b00 --- /dev/null +++ b/include/asm-x86_64/required-features.h @@ -0,0 +1,46 @@ +#ifndef _ASM_REQUIRED_FEATURES_H +#define _ASM_REQUIRED_FEATURES_H 1 + +/* Define minimum CPUID feature set for kernel These bits are checked + really early to actually display a visible error message before the + kernel dies. Make sure to assign features to the proper mask! + + The real information is in arch/x86_64/Kconfig.cpu, this just converts + the CONFIGs into a bitmask */ + +/* x86-64 baseline features */ +#define NEED_FPU (1<<(X86_FEATURE_FPU & 31)) +#define NEED_PSE (1<<(X86_FEATURE_PSE & 31)) +#define NEED_MSR (1<<(X86_FEATURE_MSR & 31)) +#define NEED_PAE (1<<(X86_FEATURE_PAE & 31)) +#define NEED_CX8 (1<<(X86_FEATURE_CX8 & 31)) +#define NEED_PGE (1<<(X86_FEATURE_PGE & 31)) +#define NEED_FXSR (1<<(X86_FEATURE_FXSR & 31)) +#define NEED_CMOV (1<<(X86_FEATURE_CMOV & 31)) +#define NEED_XMM (1<<(X86_FEATURE_XMM & 31)) +#define NEED_XMM2 (1<<(X86_FEATURE_XMM2 & 31)) + +#define REQUIRED_MASK0 (NEED_FPU|NEED_PSE|NEED_MSR|NEED_PAE|\ + NEED_CX8|NEED_PGE|NEED_FXSR|NEED_CMOV|\ + NEED_XMM|NEED_XMM2) +#define SSE_MASK (NEED_XMM|NEED_XMM2) + +/* x86-64 baseline features */ +#define NEED_LM (1<<(X86_FEATURE_LM & 31)) + +#ifdef CONFIG_X86_USE_3DNOW +# define NEED_3DNOW (1<<(X86_FEATURE_3DNOW & 31)) +#else +# define NEED_3DNOW 0 +#endif + +#define REQUIRED_MASK1 (NEED_LM|NEED_3DNOW) + +#define REQUIRED_MASK2 0 +#define REQUIRED_MASK3 0 +#define REQUIRED_MASK4 0 +#define REQUIRED_MASK5 0 +#define REQUIRED_MASK6 0 +#define REQUIRED_MASK7 0 + +#endif diff --git a/include/asm-x86_64/segment.h b/include/asm-x86_64/segment.h index adf2bf1e187..04b8ab21328 100644 --- a/include/asm-x86_64/segment.h +++ b/include/asm-x86_64/segment.h @@ -3,6 +3,14 @@ #include <asm/cache.h> +/* Simple and small GDT entries for booting only */ + +#define GDT_ENTRY_BOOT_CS 2 +#define __BOOT_CS (GDT_ENTRY_BOOT_CS * 8) + +#define GDT_ENTRY_BOOT_DS (GDT_ENTRY_BOOT_CS + 1) +#define __BOOT_DS (GDT_ENTRY_BOOT_DS * 8) + #define __KERNEL_CS 0x10 #define __KERNEL_DS 0x18 diff --git a/include/asm-x86_64/unistd.h b/include/asm-x86_64/unistd.h index ae1ed05f281..8696f8ad401 100644 --- a/include/asm-x86_64/unistd.h +++ b/include/asm-x86_64/unistd.h @@ -626,9 +626,9 @@ __SYSCALL(__NR_utimensat, sys_utimensat) __SYSCALL(__NR_epoll_pwait, sys_epoll_pwait) #define __NR_signalfd 282 __SYSCALL(__NR_signalfd, sys_signalfd) -#define __NR_timerfd 282 +#define __NR_timerfd 283 __SYSCALL(__NR_timerfd, sys_timerfd) -#define __NR_eventfd 283 +#define __NR_eventfd 284 __SYSCALL(__NR_eventfd, sys_eventfd) #ifndef __NO_STUBS diff --git a/include/asm-xtensa/bitops.h b/include/asm-xtensa/bitops.h index d815649617a..1c1e0d933ee 100644 --- a/include/asm-xtensa/bitops.h +++ b/include/asm-xtensa/bitops.h @@ -7,7 +7,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2001 - 2005 Tensilica Inc. + * Copyright (C) 2001 - 2007 Tensilica Inc. */ #ifndef _XTENSA_BITOPS_H @@ -31,53 +31,30 @@ #if XCHAL_HAVE_NSA -static __inline__ int __cntlz (unsigned long x) +static inline unsigned long __cntlz (unsigned long x) { int lz; asm ("nsau %0, %1" : "=r" (lz) : "r" (x)); - return 31 - lz; + return lz; } -#else - -static __inline__ int __cntlz (unsigned long x) -{ - unsigned long sum, x1, x2, x4, x8, x16; - x1 = x & 0xAAAAAAAA; - x2 = x & 0xCCCCCCCC; - x4 = x & 0xF0F0F0F0; - x8 = x & 0xFF00FF00; - x16 = x & 0xFFFF0000; - sum = x2 ? 2 : 0; - sum += (x16 != 0) * 16; - sum += (x8 != 0) * 8; - sum += (x4 != 0) * 4; - sum += (x1 != 0); - - return sum; -} - -#endif - /* * ffz: Find first zero in word. Undefined if no zero exists. * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). */ -static __inline__ int ffz(unsigned long x) +static inline int ffz(unsigned long x) { - if ((x = ~x) == 0) - return 32; - return __cntlz(x & -x); + return 31 - __cntlz(~x & -~x); } /* * __ffs: Find first bit set in word. Return 0 for bit 0 */ -static __inline__ int __ffs(unsigned long x) +static inline int __ffs(unsigned long x) { - return __cntlz(x & -x); + return 31 - __cntlz(x & -x); } /* @@ -86,9 +63,9 @@ static __inline__ int __ffs(unsigned long x) * differs in spirit from the above ffz (man ffs). */ -static __inline__ int ffs(unsigned long x) +static inline int ffs(unsigned long x) { - return __cntlz(x & -x) + 1; + return 32 - __cntlz(x & -x); } /* @@ -96,20 +73,36 @@ static __inline__ int ffs(unsigned long x) * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. */ -static __inline__ int fls (unsigned int x) +static inline int fls (unsigned int x) { - return __cntlz(x); + return 32 - __cntlz(x); } + +#else + +/* Use the generic implementation if we don't have the nsa/nsau instructions. */ + +# include <asm-generic/bitops/ffs.h> +# include <asm-generic/bitops/__ffs.h> +# include <asm-generic/bitops/ffz.h> +# include <asm-generic/bitops/fls.h> + +#endif + #include <asm-generic/bitops/fls64.h> #include <asm-generic/bitops/find.h> #include <asm-generic/bitops/ext2-non-atomic.h> #ifdef __XTENSA_EL__ -# define ext2_set_bit_atomic(lock,nr,addr) test_and_set_bit((nr),(addr)) -# define ext2_clear_bit_atomic(lock,nr,addr) test_and_clear_bit((nr),(addr)) +# define ext2_set_bit_atomic(lock,nr,addr) \ + test_and_set_bit((nr), (unsigned long*)(addr)) +# define ext2_clear_bit_atomic(lock,nr,addr) \ + test_and_clear_bit((nr), (unsigned long*)(addr)) #elif defined(__XTENSA_EB__) -# define ext2_set_bit_atomic(lock,nr,addr) test_and_set_bit((nr) ^ 0x18, (addr)) -# define ext2_clear_bit_atomic(lock,nr,addr) test_and_clear_bit((nr)^0x18,(addr)) +# define ext2_set_bit_atomic(lock,nr,addr) \ + test_and_set_bit((nr) ^ 0x18, (unsigned long*)(addr)) +# define ext2_clear_bit_atomic(lock,nr,addr) \ + test_and_clear_bit((nr) ^ 0x18, (unsigned long*)(addr)) #else # error processor byte order undefined! #endif diff --git a/include/asm-xtensa/byteorder.h b/include/asm-xtensa/byteorder.h index 0f540a5f4c0..765edf17a9a 100644 --- a/include/asm-xtensa/byteorder.h +++ b/include/asm-xtensa/byteorder.h @@ -12,6 +12,7 @@ #define _XTENSA_BYTEORDER_H #include <asm/types.h> +#include <linux/compiler.h> static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) { @@ -78,4 +79,4 @@ static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) # error processor byte order undefined! #endif -#endif /* __ASM_XTENSA_BYTEORDER_H */ +#endif /* _XTENSA_BYTEORDER_H */ diff --git a/include/asm-xtensa/coprocessor.h b/include/asm-xtensa/coprocessor.h index bd09ec02d57..aa212103455 100644 --- a/include/asm-xtensa/coprocessor.h +++ b/include/asm-xtensa/coprocessor.h @@ -64,6 +64,7 @@ typedef struct { # define COPROCESSOR_INFO_SIZE 8 # endif #endif +#endif /* XCHAL_HAVE_CP */ #ifndef __ASSEMBLY__ @@ -74,8 +75,11 @@ extern void save_coprocessor_registers(void*, int); # else # define release_coprocessors(task) # endif -#endif -#endif +typedef unsigned char cp_state_t[XTENSA_CP_EXTRA_SIZE] + __attribute__ ((aligned (XTENSA_CP_EXTRA_ALIGN))); + +#endif /* !__ASSEMBLY__ */ + #endif /* _XTENSA_COPROCESSOR_H */ diff --git a/include/asm-xtensa/div64.h b/include/asm-xtensa/div64.h index 20965e3af1d..f35678cb0a9 100644 --- a/include/asm-xtensa/div64.h +++ b/include/asm-xtensa/div64.h @@ -5,21 +5,12 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2001 - 2005 Tensilica Inc. + * Copyright (C) 2001 - 2007 Tensilica Inc. */ #ifndef _XTENSA_DIV64_H #define _XTENSA_DIV64_H -#include <linux/types.h> +#include <asm-generic/div64.h> -#define do_div(n,base) ({ \ - int __res = n % ((unsigned int) base); \ - n /= (unsigned int) base; \ - __res; }) - -static inline uint64_t div64_64(uint64_t dividend, uint64_t divisor) -{ - return dividend / divisor; -} -#endif +#endif /* _XTENSA_DIV64_H */ diff --git a/include/asm-xtensa/elf.h b/include/asm-xtensa/elf.h index f0f9fd8560a..1569b53cec9 100644 --- a/include/asm-xtensa/elf.h +++ b/include/asm-xtensa/elf.h @@ -13,7 +13,6 @@ #ifndef _XTENSA_ELF_H #define _XTENSA_ELF_H -#include <asm/variant/core.h> #include <asm/ptrace.h> /* Xtensa processor ELF architecture-magic number */ @@ -49,7 +48,7 @@ typedef struct { elf_greg_t lcount; elf_greg_t sar; elf_greg_t syscall; - elf_greg_t ar[XCHAL_NUM_AREGS]; + elf_greg_t ar[64]; } xtensa_gregset_t; #define ELF_NGREG (sizeof(xtensa_gregset_t) / sizeof(elf_greg_t)) diff --git a/include/asm-xtensa/fcntl.h b/include/asm-xtensa/fcntl.h index 0609fc691b7..46ab12db573 100644 --- a/include/asm-xtensa/fcntl.h +++ b/include/asm-xtensa/fcntl.h @@ -1,99 +1 @@ -/* - * include/asm-xtensa/fcntl.h - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle - * Copyright (C) 2001 - 2005 Tensilica Inc. - */ - -#ifndef _XTENSA_FCNTL_H -#define _XTENSA_FCNTL_H - -/* open/fcntl - O_SYNC is only implemented on blocks devices and on files - located on an ext2 file system */ -#define O_ACCMODE 0003 -#define O_RDONLY 00 -#define O_WRONLY 01 -#define O_RDWR 02 -#define O_CREAT 0100 /* not fcntl */ -#define O_EXCL 0200 /* not fcntl */ -#define O_NOCTTY 0400 /* not fcntl */ -#define O_TRUNC 01000 /* not fcntl */ -#define O_APPEND 02000 -#define O_NONBLOCK 04000 -#define O_NDELAY O_NONBLOCK -#define O_SYNC 010000 -#define FASYNC 020000 /* fcntl, for BSD compatibility */ -#define O_DIRECT 040000 /* direct disk access hint */ -#define O_LARGEFILE 0100000 -#define O_DIRECTORY 0200000 /* must be a directory */ -#define O_NOFOLLOW 0400000 /* don't follow links */ -#define O_NOATIME 01000000 - -#define F_DUPFD 0 /* dup */ -#define F_GETFD 1 /* get close_on_exec */ -#define F_SETFD 2 /* set/clear close_on_exec */ -#define F_GETFL 3 /* get file->f_flags */ -#define F_SETFL 4 /* set file->f_flags */ -#define F_GETLK 5 -#define F_SETLK 6 -#define F_SETLKW 7 - -#define F_SETOWN 8 /* for sockets. */ -#define F_GETOWN 9 /* for sockets. */ -#define F_SETSIG 10 /* for sockets. */ -#define F_GETSIG 11 /* for sockets. */ - -#define F_GETLK64 12 /* using 'struct flock64' */ -#define F_SETLK64 13 -#define F_SETLKW64 14 - -/* for F_[GET|SET]FL */ -#define FD_CLOEXEC 1 /* actually anything with low bit set goes */ - -/* for posix fcntl() and lockf() */ -#define F_RDLCK 0 -#define F_WRLCK 1 -#define F_UNLCK 2 - -/* for old implementation of bsd flock () */ -#define F_EXLCK 4 /* or 3 */ -#define F_SHLCK 8 /* or 4 */ - -/* for leases */ -#define F_INPROGRESS 16 - -/* operations for bsd flock(), also used by the kernel implementation */ -#define LOCK_SH 1 /* shared lock */ -#define LOCK_EX 2 /* exclusive lock */ -#define LOCK_NB 4 /* or'd with one of the above to prevent - blocking */ -#define LOCK_UN 8 /* remove lock */ - -#define LOCK_MAND 32 /* This is a mandatory flock */ -#define LOCK_READ 64 /* ... Which allows concurrent read operations */ -#define LOCK_WRITE 128 /* ... Which allows concurrent write operations */ -#define LOCK_RW 192 /* ... Which allows concurrent read & write ops */ - -struct flock { - short l_type; - short l_whence; - off_t l_start; - off_t l_len; - pid_t l_pid; -}; - -struct flock64 { - short l_type; - short l_whence; - loff_t l_start; - loff_t l_len; - pid_t l_pid; -}; - -#define F_LINUX_SPECIFIC_BASE 1024 - -#endif /* _XTENSA_FCNTL_H */ +#include <asm-generic/fcntl.h> diff --git a/include/asm-xtensa/mmu_context.h b/include/asm-xtensa/mmu_context.h index 92f948392eb..c0fd8e5b451 100644 --- a/include/asm-xtensa/mmu_context.h +++ b/include/asm-xtensa/mmu_context.h @@ -14,6 +14,7 @@ #define _XTENSA_MMU_CONTEXT_H #include <linux/stringify.h> +#include <linux/sched.h> #include <asm/pgtable.h> #include <asm/cacheflush.h> diff --git a/include/asm-xtensa/page.h b/include/asm-xtensa/page.h index c631d006194..1213cde7543 100644 --- a/include/asm-xtensa/page.h +++ b/include/asm-xtensa/page.h @@ -131,6 +131,6 @@ void copy_user_page(void *to,void* from,unsigned long vaddr,struct page* page); #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) -#endif /* __KERNEL__ */ #include <asm-generic/memory_model.h> +#endif /* __KERNEL__ */ #endif /* _XTENSA_PAGE_H */ diff --git a/include/asm-xtensa/param.h b/include/asm-xtensa/param.h index 6f281392e3f..ce3a336cad0 100644 --- a/include/asm-xtensa/param.h +++ b/include/asm-xtensa/param.h @@ -11,15 +11,13 @@ #ifndef _XTENSA_PARAM_H #define _XTENSA_PARAM_H -#include <asm/variant/core.h> - #ifdef __KERNEL__ # define HZ 100 /* internal timer frequency */ # define USER_HZ 100 /* for user interfaces in "ticks" */ # define CLOCKS_PER_SEC (USER_HZ) /* frequnzy at which times() counts */ #endif -#define EXEC_PAGESIZE (1 << XCHAL_MMU_MIN_PTE_PAGE_SIZE) +#define EXEC_PAGESIZE 4096 #ifndef NGROUPS #define NGROUPS 32 diff --git a/include/asm-xtensa/pci.h b/include/asm-xtensa/pci.h index 24eb7fc25da..66410acf18b 100644 --- a/include/asm-xtensa/pci.h +++ b/include/asm-xtensa/pci.h @@ -64,9 +64,6 @@ struct pci_dev; #define pci_ubnmap_len(PTR, LEN_NAME) (0) #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) -/* We cannot access memory above 4GB */ -#define pci_dac_dma_supported(pci_dev, mask) (0) - /* Map a range of PCI memory or I/O space for a device into user space */ int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, enum pci_mmap_state mmap_state, int write_combine); @@ -74,10 +71,6 @@ int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, /* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */ #define HAVE_PCI_MMAP 1 -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} - #endif /* __KERNEL__ */ /* Implement the pci_ DMA API in terms of the generic device dma_ one */ diff --git a/include/asm-xtensa/ptrace.h b/include/asm-xtensa/ptrace.h index 1b7fe363fad..77ff02d307b 100644 --- a/include/asm-xtensa/ptrace.h +++ b/include/asm-xtensa/ptrace.h @@ -11,8 +11,6 @@ #ifndef _XTENSA_PTRACE_H #define _XTENSA_PTRACE_H -#include <asm/variant/core.h> - /* * Kernel stack * @@ -101,7 +99,8 @@ struct pt_regs { unsigned long windowbase; /* 48 */ unsigned long windowstart; /* 52 */ unsigned long syscall; /* 56 */ - int reserved[2]; /* 64 */ + unsigned long icountlevel; /* 60 */ + int reserved[1]; /* 64 */ /* Make sure the areg field is 16 bytes aligned. */ int align[0] __attribute__ ((aligned(16))); @@ -113,6 +112,9 @@ struct pt_regs { }; #ifdef __KERNEL__ + +#include <asm/variant/core.h> + # define task_pt_regs(tsk) ((struct pt_regs*) \ (task_stack_page(tsk) + KERNEL_STACK_SIZE - (XCHAL_NUM_AREGS-16)*4) - 1) # define user_mode(regs) (((regs)->ps & 0x00000020)!=0) diff --git a/include/asm-xtensa/shmparam.h b/include/asm-xtensa/shmparam.h index d3b65bfa71c..c8cc16c3da9 100644 --- a/include/asm-xtensa/shmparam.h +++ b/include/asm-xtensa/shmparam.h @@ -9,8 +9,6 @@ #ifndef _XTENSA_SHMPARAM_H #define _XTENSA_SHMPARAM_H -#include <asm/processor.h> - /* * Xtensa can have variable size caches, and if * the size of single way is larger than the page size, diff --git a/include/asm-xtensa/sigcontext.h b/include/asm-xtensa/sigcontext.h index a7517729141..e3381cee505 100644 --- a/include/asm-xtensa/sigcontext.h +++ b/include/asm-xtensa/sigcontext.h @@ -5,21 +5,12 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2001 - 2003 Tensilica Inc. + * Copyright (C) 2001 - 2007 Tensilica Inc. */ #ifndef _XTENSA_SIGCONTEXT_H #define _XTENSA_SIGCONTEXT_H -#define _ASMLANGUAGE -#include <asm/processor.h> -#include <asm/coprocessor.h> - - -struct _cpstate { - unsigned char _cpstate[XTENSA_CP_EXTRA_SIZE]; -} __attribute__ ((aligned (XTENSA_CP_EXTRA_ALIGN))); - struct sigcontext { unsigned long oldmask; @@ -27,18 +18,13 @@ struct sigcontext { /* CPU registers */ unsigned long sc_pc; unsigned long sc_ps; - unsigned long sc_wmask; - unsigned long sc_windowbase; - unsigned long sc_windowstart; unsigned long sc_lbeg; unsigned long sc_lend; unsigned long sc_lcount; unsigned long sc_sar; - unsigned long sc_depc; - unsigned long sc_dareg0; - unsigned long sc_treg[4]; - unsigned long sc_areg[XCHAL_NUM_AREGS]; - struct _cpstate *sc_cpstate; + unsigned long sc_acclo; + unsigned long sc_acchi; + unsigned long sc_a[16]; }; -#endif /* __ASM_XTENSA_SIGCONTEXT_H */ +#endif /* _XTENSA_SIGCONTEXT_H */ diff --git a/include/asm-xtensa/termbits.h b/include/asm-xtensa/termbits.h index 057b9a3d8f8..9972c25ec86 100644 --- a/include/asm-xtensa/termbits.h +++ b/include/asm-xtensa/termbits.h @@ -30,6 +30,17 @@ struct termios { cc_t c_cc[NCCS]; /* control characters */ }; +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + struct ktermios { tcflag_t c_iflag; /* input mode flags */ tcflag_t c_oflag; /* output mode flags */ diff --git a/include/asm-xtensa/thread_info.h b/include/asm-xtensa/thread_info.h index 5ae34ab7159..3fa29799b43 100644 --- a/include/asm-xtensa/thread_info.h +++ b/include/asm-xtensa/thread_info.h @@ -116,6 +116,7 @@ static inline struct thread_info *current_thread_info(void) #define TIF_SINGLESTEP 4 /* restore singlestep on return to user mode */ #define TIF_IRET 5 /* return with iret */ #define TIF_MEMDIE 6 +#define TIF_RESTORE_SIGMASK 7 /* restore signal mask in do_signal() */ #define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */ #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) @@ -125,6 +126,7 @@ static inline struct thread_info *current_thread_info(void) #define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP) #define _TIF_IRET (1<<TIF_IRET) #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) +#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK) #define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */ #define _TIF_ALLWORK_MASK 0x0000FFFF /* work to do on any return to u-space */ diff --git a/include/asm-xtensa/unistd.h b/include/asm-xtensa/unistd.h index 8a7fb6964ce..9bd34024431 100644 --- a/include/asm-xtensa/unistd.h +++ b/include/asm-xtensa/unistd.h @@ -485,8 +485,8 @@ __SYSCALL(217, sys_sched_get_priority_min, 1) __SYSCALL(218, sys_sched_rr_get_interval, 2) #define __NR_sched_yield 219 __SYSCALL(219, sys_sched_yield, 0) -#define __NR_sigreturn 222 -__SYSCALL(222, xtensa_sigreturn, 0) +#define __NR_available222 222 +__SYSCALL(222, sys_ni_syscall, 0) /* Signal Handling */ diff --git a/include/linux/Kbuild b/include/linux/Kbuild index e1013156c25..127d2d192b5 100644 --- a/include/linux/Kbuild +++ b/include/linux/Kbuild @@ -49,6 +49,7 @@ header-y += consolemap.h header-y += const.h header-y += cycx_cfm.h header-y += dlm_device.h +header-y += dlm_netlink.h header-y += dm-ioctl.h header-y += dn.h header-y += dqblk_v1.h @@ -62,6 +63,8 @@ header-y += fadvise.h header-y += fd.h header-y += fdreg.h header-y += fib_rules.h +header-y += firewire-cdev.h +header-y += firewire-constants.h header-y += fuse.h header-y += genetlink.h header-y += gen_stats.h @@ -88,7 +91,6 @@ header-y += in6.h header-y += in_route.h header-y += ioctl.h header-y += ipmi_msgdefs.h -header-y += ip_mp_alg.h header-y += ipsec.h header-y += ipx.h header-y += irda.h @@ -223,6 +225,7 @@ unifdef-y += if_fddi.h unifdef-y += if_frad.h unifdef-y += if_ltalk.h unifdef-y += if_link.h +unifdef-y += if_pppol2tp.h unifdef-y += if_pppox.h unifdef-y += if_shaper.h unifdef-y += if_tr.h diff --git a/include/linux/aer.h b/include/linux/aer.h index 402e178b38e..509656286e5 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -13,11 +13,13 @@ extern int pci_enable_pcie_error_reporting(struct pci_dev *dev); extern int pci_find_aer_capability(struct pci_dev *dev); extern int pci_disable_pcie_error_reporting(struct pci_dev *dev); extern int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev); +extern int pci_cleanup_aer_correct_error_status(struct pci_dev *dev); #else -#define pci_enable_pcie_error_reporting(dev) do { } while (0) -#define pci_find_aer_capability(dev) do { } while (0) -#define pci_disable_pcie_error_reporting(dev) do { } while (0) -#define pci_cleanup_aer_uncorrect_error_status(dev) do { } while (0) +#define pci_enable_pcie_error_reporting(dev) (-EINVAL) +#define pci_find_aer_capability(dev) (0) +#define pci_disable_pcie_error_reporting(dev) (-EINVAL) +#define pci_cleanup_aer_uncorrect_error_status(dev) (-EINVAL) +#define pci_cleanup_aer_correct_error_status(dev) (-EINVAL) #endif #endif //_AER_H_ diff --git a/include/linux/async_tx.h b/include/linux/async_tx.h new file mode 100644 index 00000000000..ff1255079fa --- /dev/null +++ b/include/linux/async_tx.h @@ -0,0 +1,156 @@ +/* + * Copyright © 2006, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + */ +#ifndef _ASYNC_TX_H_ +#define _ASYNC_TX_H_ +#include <linux/dmaengine.h> +#include <linux/spinlock.h> +#include <linux/interrupt.h> + +/** + * dma_chan_ref - object used to manage dma channels received from the + * dmaengine core. + * @chan - the channel being tracked + * @node - node for the channel to be placed on async_tx_master_list + * @rcu - for list_del_rcu + * @count - number of times this channel is listed in the pool + * (for channels with multiple capabiities) + */ +struct dma_chan_ref { + struct dma_chan *chan; + struct list_head node; + struct rcu_head rcu; + atomic_t count; +}; + +/** + * async_tx_flags - modifiers for the async_* calls + * @ASYNC_TX_XOR_ZERO_DST: this flag must be used for xor operations where the + * the destination address is not a source. The asynchronous case handles this + * implicitly, the synchronous case needs to zero the destination block. + * @ASYNC_TX_XOR_DROP_DST: this flag must be used if the destination address is + * also one of the source addresses. In the synchronous case the destination + * address is an implied source, whereas the asynchronous case it must be listed + * as a source. The destination address must be the first address in the source + * array. + * @ASYNC_TX_ASSUME_COHERENT: skip cache maintenance operations + * @ASYNC_TX_ACK: immediately ack the descriptor, precludes setting up a + * dependency chain + * @ASYNC_TX_DEP_ACK: ack the dependency descriptor. Useful for chaining. + * @ASYNC_TX_KMAP_SRC: if the transaction is to be performed synchronously + * take an atomic mapping (KM_USER0) on the source page(s) + * @ASYNC_TX_KMAP_DST: if the transaction is to be performed synchronously + * take an atomic mapping (KM_USER0) on the dest page(s) + */ +enum async_tx_flags { + ASYNC_TX_XOR_ZERO_DST = (1 << 0), + ASYNC_TX_XOR_DROP_DST = (1 << 1), + ASYNC_TX_ASSUME_COHERENT = (1 << 2), + ASYNC_TX_ACK = (1 << 3), + ASYNC_TX_DEP_ACK = (1 << 4), + ASYNC_TX_KMAP_SRC = (1 << 5), + ASYNC_TX_KMAP_DST = (1 << 6), +}; + +#ifdef CONFIG_DMA_ENGINE +void async_tx_issue_pending_all(void); +enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); +void async_tx_run_dependencies(struct dma_async_tx_descriptor *tx); +struct dma_chan * +async_tx_find_channel(struct dma_async_tx_descriptor *depend_tx, + enum dma_transaction_type tx_type); +#else +static inline void async_tx_issue_pending_all(void) +{ + do { } while (0); +} + +static inline enum dma_status +dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) +{ + return DMA_SUCCESS; +} + +static inline void +async_tx_run_dependencies(struct dma_async_tx_descriptor *tx, + struct dma_chan *host_chan) +{ + do { } while (0); +} + +static inline struct dma_chan * +async_tx_find_channel(struct dma_async_tx_descriptor *depend_tx, + enum dma_transaction_type tx_type) +{ + return NULL; +} +#endif + +/** + * async_tx_sync_epilog - actions to take if an operation is run synchronously + * @flags: async_tx flags + * @depend_tx: transaction depends on depend_tx + * @cb_fn: function to call when the transaction completes + * @cb_fn_param: parameter to pass to the callback routine + */ +static inline void +async_tx_sync_epilog(unsigned long flags, + struct dma_async_tx_descriptor *depend_tx, + dma_async_tx_callback cb_fn, void *cb_fn_param) +{ + if (cb_fn) + cb_fn(cb_fn_param); + + if (depend_tx && (flags & ASYNC_TX_DEP_ACK)) + async_tx_ack(depend_tx); +} + +void +async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx, + enum async_tx_flags flags, struct dma_async_tx_descriptor *depend_tx, + dma_async_tx_callback cb_fn, void *cb_fn_param); + +struct dma_async_tx_descriptor * +async_xor(struct page *dest, struct page **src_list, unsigned int offset, + int src_cnt, size_t len, enum async_tx_flags flags, + struct dma_async_tx_descriptor *depend_tx, + dma_async_tx_callback cb_fn, void *cb_fn_param); + +struct dma_async_tx_descriptor * +async_xor_zero_sum(struct page *dest, struct page **src_list, + unsigned int offset, int src_cnt, size_t len, + u32 *result, enum async_tx_flags flags, + struct dma_async_tx_descriptor *depend_tx, + dma_async_tx_callback cb_fn, void *cb_fn_param); + +struct dma_async_tx_descriptor * +async_memcpy(struct page *dest, struct page *src, unsigned int dest_offset, + unsigned int src_offset, size_t len, enum async_tx_flags flags, + struct dma_async_tx_descriptor *depend_tx, + dma_async_tx_callback cb_fn, void *cb_fn_param); + +struct dma_async_tx_descriptor * +async_memset(struct page *dest, int val, unsigned int offset, + size_t len, enum async_tx_flags flags, + struct dma_async_tx_descriptor *depend_tx, + dma_async_tx_callback cb_fn, void *cb_fn_param); + +struct dma_async_tx_descriptor * +async_trigger_callback(enum async_tx_flags flags, + struct dma_async_tx_descriptor *depend_tx, + dma_async_tx_callback cb_fn, void *cb_fn_param); +#endif /* _ASYNC_TX_H_ */ diff --git a/include/linux/ata.h b/include/linux/ata.h index edb31bfff68..b5a20162af3 100644 --- a/include/linux/ata.h +++ b/include/linux/ata.h @@ -126,6 +126,7 @@ enum { ATA_REG_IRQ = ATA_REG_NSECT, /* ATA device commands */ + ATA_CMD_DEV_RESET = 0x08, /* ATAPI device reset */ ATA_CMD_CHK_POWER = 0xE5, /* check power mode */ ATA_CMD_STANDBY = 0xE2, /* place in standby power mode */ ATA_CMD_IDLE = 0xE3, /* place in idle power mode */ @@ -151,6 +152,7 @@ enum { ATA_CMD_WRITE_MULTI_EXT = 0x39, ATA_CMD_WRITE_MULTI_FUA_EXT = 0xCE, ATA_CMD_SET_FEATURES = 0xEF, + ATA_CMD_SET_MULTI = 0xC6, ATA_CMD_PACKET = 0xA0, ATA_CMD_VERIFY = 0x40, ATA_CMD_VERIFY_EXT = 0x42, @@ -162,6 +164,8 @@ enum { ATA_CMD_SET_MAX = 0xF9, ATA_CMD_SET_MAX_EXT = 0x37, ATA_CMD_READ_LOG_EXT = 0x2f, + ATA_CMD_PMP_READ = 0xE4, + ATA_CMD_PMP_WRITE = 0xE8, /* READ_LOG_EXT pages */ ATA_LOG_SATA_NCQ = 0x10, @@ -210,6 +214,28 @@ enum { 0=to device, 1=to host */ ATAPI_CDB_LEN = 16, + /* PMP stuff */ + SATA_PMP_MAX_PORTS = 15, + SATA_PMP_CTRL_PORT = 15, + + SATA_PMP_GSCR_DWORDS = 128, + SATA_PMP_GSCR_PROD_ID = 0, + SATA_PMP_GSCR_REV = 1, + SATA_PMP_GSCR_PORT_INFO = 2, + SATA_PMP_GSCR_ERROR = 32, + SATA_PMP_GSCR_ERROR_EN = 33, + SATA_PMP_GSCR_FEAT = 64, + SATA_PMP_GSCR_FEAT_EN = 96, + + SATA_PMP_PSCR_STATUS = 0, + SATA_PMP_PSCR_ERROR = 1, + SATA_PMP_PSCR_CONTROL = 2, + + SATA_PMP_FEAT_BIST = (1 << 0), + SATA_PMP_FEAT_PMREQ = (1 << 1), + SATA_PMP_FEAT_DYNSSC = (1 << 2), + SATA_PMP_FEAT_NOTIFY = (1 << 3), + /* cable types */ ATA_CBL_NONE = 0, ATA_CBL_PATA40 = 1, @@ -249,7 +275,7 @@ enum ata_tf_protocols { /* ATA taskfile protocols */ ATA_PROT_UNKNOWN, /* unknown/invalid */ ATA_PROT_NODATA, /* no data */ - ATA_PROT_PIO, /* PIO single sector */ + ATA_PROT_PIO, /* PIO data xfer */ ATA_PROT_DMA, /* DMA */ ATA_PROT_NCQ, /* NCQ */ ATA_PROT_ATAPI, /* packet command, PIO data xfer*/ @@ -416,4 +442,9 @@ static inline int lba_48_ok(u64 block, u32 n_block) return ((block + n_block - 1) < ((u64)1 << 48)) && (n_block <= 65536); } +#define sata_pmp_gscr_vendor(gscr) ((gscr)[SATA_PMP_GSCR_PROD_ID] & 0xffff) +#define sata_pmp_gscr_devid(gscr) ((gscr)[SATA_PMP_GSCR_PROD_ID] >> 16) +#define sata_pmp_gscr_rev(gscr) (((gscr)[SATA_PMP_GSCR_REV] >> 8) & 0xff) +#define sata_pmp_gscr_ports(gscr) ((gscr)[SATA_PMP_GSCR_PORT_INFO] & 0xf) + #endif /* __LINUX_ATA_H__ */ diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h index db5b00a792f..fae138bd220 100644 --- a/include/linux/blkdev.h +++ b/include/linux/blkdev.h @@ -868,11 +868,6 @@ void kblockd_flush_work(struct work_struct *work); */ #define buffer_heads_over_limit 0 -static inline long blk_congestion_wait(int rw, long timeout) -{ - return io_schedule_timeout(timeout); -} - static inline long nr_blockdev_pages(void) { return 0; diff --git a/include/linux/bootmem.h b/include/linux/bootmem.h index 0365ec9fc0c..c83534ee1e7 100644 --- a/include/linux/bootmem.h +++ b/include/linux/bootmem.h @@ -59,6 +59,7 @@ extern void *__alloc_bootmem_core(struct bootmem_data *bdata, unsigned long align, unsigned long goal, unsigned long limit); +extern void *alloc_bootmem_high_node(pg_data_t *pgdat, unsigned long size); #ifndef CONFIG_HAVE_ARCH_BOOTMEM_NODE extern void reserve_bootmem(unsigned long addr, unsigned long size); diff --git a/include/linux/console_struct.h b/include/linux/console_struct.h index a461f76fb00..dc77fed7b28 100644 --- a/include/linux/console_struct.h +++ b/include/linux/console_struct.h @@ -9,6 +9,9 @@ * to achieve effects such as fast scrolling by changing the origin. */ +#ifndef _LINUX_CONSOLE_STRUCT_H +#define _LINUX_CONSOLE_STRUCT_H + #include <linux/wait.h> #include <linux/vt.h> #include <linux/workqueue.h> @@ -130,3 +133,5 @@ extern void vc_SAK(struct work_struct *work); #define CUR_DEFAULT CUR_UNDERLINE #define CON_IS_VISIBLE(conp) (*conp->vc_display_fg == conp) + +#endif /* _LINUX_CONSOLE_STRUCT_H */ diff --git a/include/linux/crypto.h b/include/linux/crypto.h index 0de7e2ace82..357e8cfedc3 100644 --- a/include/linux/crypto.h +++ b/include/linux/crypto.h @@ -295,28 +295,8 @@ struct blkcipher_tfm { }; struct cipher_tfm { - void *cit_iv; - unsigned int cit_ivsize; - u32 cit_mode; int (*cit_setkey)(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen); - int (*cit_encrypt)(struct crypto_tfm *tfm, - struct scatterlist *dst, - struct scatterlist *src, - unsigned int nbytes); - int (*cit_encrypt_iv)(struct crypto_tfm *tfm, - struct scatterlist *dst, - struct scatterlist *src, - unsigned int nbytes, u8 *iv); - int (*cit_decrypt)(struct crypto_tfm *tfm, - struct scatterlist *dst, - struct scatterlist *src, - unsigned int nbytes); - int (*cit_decrypt_iv)(struct crypto_tfm *tfm, - struct scatterlist *dst, - struct scatterlist *src, - unsigned int nbytes, u8 *iv); - void (*cit_xor_block)(u8 *dst, const u8 *src); void (*cit_encrypt_one)(struct crypto_tfm *tfm, u8 *dst, const u8 *src); void (*cit_decrypt_one)(struct crypto_tfm *tfm, u8 *dst, const u8 *src); }; diff --git a/include/linux/debugfs.h b/include/linux/debugfs.h index 5a9c49534d0..104e51e20e1 100644 --- a/include/linux/debugfs.h +++ b/include/linux/debugfs.h @@ -38,6 +38,9 @@ struct dentry *debugfs_create_symlink(const char *name, struct dentry *parent, void debugfs_remove(struct dentry *dentry); +struct dentry *debugfs_rename(struct dentry *old_dir, struct dentry *old_dentry, + struct dentry *new_dir, const char *new_name); + struct dentry *debugfs_create_u8(const char *name, mode_t mode, struct dentry *parent, u8 *value); struct dentry *debugfs_create_u16(const char *name, mode_t mode, @@ -85,6 +88,12 @@ static inline struct dentry *debugfs_create_symlink(const char *name, static inline void debugfs_remove(struct dentry *dentry) { } +static inline struct dentry *debugfs_rename(struct dentry *old_dir, struct dentry *old_dentry, + struct dentry *new_dir, char *new_name) +{ + return ERR_PTR(-ENODEV); +} + static inline struct dentry *debugfs_create_u8(const char *name, mode_t mode, struct dentry *parent, u8 *value) diff --git a/include/linux/device.h b/include/linux/device.h index 2e1a2988b7e..be2debed70d 100644 --- a/include/linux/device.h +++ b/include/linux/device.h @@ -238,7 +238,6 @@ extern int __must_check class_device_create_file(struct class_device *, * @devt: for internal use by the driver core only. * @node: for internal use by the driver core only. * @kobj: for internal use by the driver core only. - * @devt_attr: for internal use by the driver core only. * @groups: optional additional groups to be created * @dev: if set, a symlink to the struct device is created in the sysfs * directory for this struct class device. @@ -263,8 +262,6 @@ struct class_device { struct kobject kobj; struct class * class; /* required */ dev_t devt; /* dev_t, creates the sysfs "dev" */ - struct class_device_attribute *devt_attr; - struct class_device_attribute uevent_attr; struct device * dev; /* not necessary, but nice to have */ void * class_data; /* class-specific data */ struct class_device *parent; /* parent of this child device, if there is one */ @@ -419,8 +416,6 @@ struct device { struct device_type *type; unsigned is_registered:1; unsigned uevent_suppress:1; - struct device_attribute uevent_attr; - struct device_attribute *devt_attr; struct semaphore sem; /* semaphore to synchronize calls to * its driver. diff --git a/include/linux/dlm.h b/include/linux/dlm.h index 1b1dcb9a40b..be9d278761e 100644 --- a/include/linux/dlm.h +++ b/include/linux/dlm.h @@ -2,7 +2,7 @@ ******************************************************************************* ** ** Copyright (C) Sistina Software, Inc. 1997-2003 All rights reserved. -** Copyright (C) 2004-2005 Red Hat, Inc. All rights reserved. +** Copyright (C) 2004-2007 Red Hat, Inc. All rights reserved. ** ** This copyrighted material is made available to anyone wishing to use, ** modify, copy, or redistribute it subject to the terms and conditions @@ -85,7 +85,11 @@ * Only relevant to locks originating in userspace. A persistent lock will not * be removed if the process holding the lock exits. * - * DLM_LKF_NODLKWT + * DLM_LKF_NODLCKWT + * + * Do not cancel the lock if it gets into conversion deadlock. + * Exclude this lock from being monitored due to DLM_LSFL_TIMEWARN. + * * DLM_LKF_NODLCKBLK * * net yet implemented @@ -149,6 +153,7 @@ #define DLM_LKF_ALTPR 0x00008000 #define DLM_LKF_ALTCW 0x00010000 #define DLM_LKF_FORCEUNLOCK 0x00020000 +#define DLM_LKF_TIMEOUT 0x00040000 /* * Some return codes that are not in errno.h @@ -199,11 +204,12 @@ struct dlm_lksb { char * sb_lvbptr; }; +#define DLM_LSFL_NODIR 0x00000001 +#define DLM_LSFL_TIMEWARN 0x00000002 +#define DLM_LSFL_FS 0x00000004 #ifdef __KERNEL__ -#define DLM_LSFL_NODIR 0x00000001 - /* * dlm_new_lockspace * diff --git a/include/linux/dlm_device.h b/include/linux/dlm_device.h index c2735cab2eb..9642277a152 100644 --- a/include/linux/dlm_device.h +++ b/include/linux/dlm_device.h @@ -2,7 +2,7 @@ ******************************************************************************* ** ** Copyright (C) Sistina Software, Inc. 1997-2003 All rights reserved. -** Copyright (C) 2004-2005 Red Hat, Inc. All rights reserved. +** Copyright (C) 2004-2007 Red Hat, Inc. All rights reserved. ** ** This copyrighted material is made available to anyone wishing to use, ** modify, copy, or redistribute it subject to the terms and conditions @@ -18,21 +18,24 @@ #define DLM_USER_LVB_LEN 32 /* Version of the device interface */ -#define DLM_DEVICE_VERSION_MAJOR 5 -#define DLM_DEVICE_VERSION_MINOR 1 +#define DLM_DEVICE_VERSION_MAJOR 6 +#define DLM_DEVICE_VERSION_MINOR 0 #define DLM_DEVICE_VERSION_PATCH 0 /* struct passed to the lock write */ struct dlm_lock_params { __u8 mode; __u8 namelen; - __u16 flags; + __u16 unused; + __u32 flags; __u32 lkid; __u32 parent; - void __user *castparam; + __u64 xid; + __u64 timeout; + void __user *castparam; void __user *castaddr; void __user *bastparam; - void __user *bastaddr; + void __user *bastaddr; struct dlm_lksb __user *lksb; char lvb[DLM_USER_LVB_LEN]; char name[0]; @@ -62,9 +65,15 @@ struct dlm_write_request { } i; }; +struct dlm_device_version { + __u32 version[3]; +}; + /* struct read from the "device" fd, consists mainly of userspace pointers for the library to use */ + struct dlm_lock_result { + __u32 version[3]; __u32 length; void __user * user_astaddr; void __user * user_astparam; @@ -83,6 +92,7 @@ struct dlm_lock_result { #define DLM_USER_CREATE_LOCKSPACE 4 #define DLM_USER_REMOVE_LOCKSPACE 5 #define DLM_USER_PURGE 6 +#define DLM_USER_DEADLOCK 7 /* Arbitrary length restriction */ #define MAX_LS_NAME_LEN 64 diff --git a/include/linux/dlm_netlink.h b/include/linux/dlm_netlink.h new file mode 100644 index 00000000000..19276332707 --- /dev/null +++ b/include/linux/dlm_netlink.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2007 Red Hat, Inc. All rights reserved. + * + * This copyrighted material is made available to anyone wishing to use, + * modify, copy, or redistribute it subject to the terms and conditions + * of the GNU General Public License v.2. + */ + +#ifndef _DLM_NETLINK_H +#define _DLM_NETLINK_H + +enum { + DLM_STATUS_WAITING = 1, + DLM_STATUS_GRANTED = 2, + DLM_STATUS_CONVERT = 3, +}; + +#define DLM_LOCK_DATA_VERSION 1 + +struct dlm_lock_data { + uint16_t version; + uint32_t lockspace_id; + int nodeid; + int ownpid; + uint32_t id; + uint32_t remid; + uint64_t xid; + int8_t status; + int8_t grmode; + int8_t rqmode; + unsigned long timestamp; + int resource_namelen; + char resource_name[DLM_RESNAME_MAXLEN]; +}; + +enum { + DLM_CMD_UNSPEC = 0, + DLM_CMD_HELLO, /* user->kernel */ + DLM_CMD_TIMEOUT, /* kernel->user */ + __DLM_CMD_MAX, +}; + +#define DLM_CMD_MAX (__DLM_CMD_MAX - 1) + +enum { + DLM_TYPE_UNSPEC = 0, + DLM_TYPE_LOCK, + __DLM_TYPE_MAX, +}; + +#define DLM_TYPE_MAX (__DLM_TYPE_MAX - 1) + +#define DLM_GENL_VERSION 0x1 +#define DLM_GENL_NAME "DLM" + +#endif /* _DLM_NETLINK_H */ diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index c94d8f1d62e..a3b6035b6c8 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -21,29 +21,40 @@ #ifndef DMAENGINE_H #define DMAENGINE_H -#ifdef CONFIG_DMA_ENGINE - #include <linux/device.h> #include <linux/uio.h> #include <linux/kref.h> #include <linux/completion.h> #include <linux/rcupdate.h> +#include <linux/dma-mapping.h> /** - * enum dma_event - resource PNP/power managment events + * enum dma_state - resource PNP/power managment state * @DMA_RESOURCE_SUSPEND: DMA device going into low power state * @DMA_RESOURCE_RESUME: DMA device returning to full power - * @DMA_RESOURCE_ADDED: DMA device added to the system + * @DMA_RESOURCE_AVAILABLE: DMA device available to the system * @DMA_RESOURCE_REMOVED: DMA device removed from the system */ -enum dma_event { +enum dma_state { DMA_RESOURCE_SUSPEND, DMA_RESOURCE_RESUME, - DMA_RESOURCE_ADDED, + DMA_RESOURCE_AVAILABLE, DMA_RESOURCE_REMOVED, }; /** + * enum dma_state_client - state of the channel in the client + * @DMA_ACK: client would like to use, or was using this channel + * @DMA_DUP: client has already seen this channel, or is not using this channel + * @DMA_NAK: client does not want to see any more channels + */ +enum dma_state_client { + DMA_ACK, + DMA_DUP, + DMA_NAK, +}; + +/** * typedef dma_cookie_t - an opaque DMA cookie * * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code @@ -65,6 +76,31 @@ enum dma_status { }; /** + * enum dma_transaction_type - DMA transaction types/indexes + */ +enum dma_transaction_type { + DMA_MEMCPY, + DMA_XOR, + DMA_PQ_XOR, + DMA_DUAL_XOR, + DMA_PQ_UPDATE, + DMA_ZERO_SUM, + DMA_PQ_ZERO_SUM, + DMA_MEMSET, + DMA_MEMCPY_CRC32C, + DMA_INTERRUPT, +}; + +/* last transaction type for creation of the capabilities mask */ +#define DMA_TX_TYPE_END (DMA_INTERRUPT + 1) + +/** + * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. + * See linux/cpumask.h + */ +typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t; + +/** * struct dma_chan_percpu - the per-CPU part of struct dma_chan * @refcount: local_t used for open-coded "bigref" counting * @memcpy_count: transaction counter @@ -80,7 +116,6 @@ struct dma_chan_percpu { /** * struct dma_chan - devices supply DMA channels, clients use them - * @client: ptr to the client user of this chan, will be %NULL when unused * @device: ptr to the dma device who supplies this channel, always !%NULL * @cookie: last cookie value returned to client * @chan_id: channel ID for sysfs @@ -88,12 +123,10 @@ struct dma_chan_percpu { * @refcount: kref, used in "bigref" slow-mode * @slow_ref: indicates that the DMA channel is free * @rcu: the DMA channel's RCU head - * @client_node: used to add this to the client chan list * @device_node: used to add this to the device chan list * @local: per-cpu pointer to a struct dma_chan_percpu */ struct dma_chan { - struct dma_client *client; struct dma_device *device; dma_cookie_t cookie; @@ -105,11 +138,11 @@ struct dma_chan { int slow_ref; struct rcu_head rcu; - struct list_head client_node; struct list_head device_node; struct dma_chan_percpu *local; }; + void dma_chan_cleanup(struct kref *kref); static inline void dma_chan_get(struct dma_chan *chan) @@ -134,169 +167,206 @@ static inline void dma_chan_put(struct dma_chan *chan) /* * typedef dma_event_callback - function pointer to a DMA event callback + * For each channel added to the system this routine is called for each client. + * If the client would like to use the channel it returns '1' to signal (ack) + * the dmaengine core to take out a reference on the channel and its + * corresponding device. A client must not 'ack' an available channel more + * than once. When a channel is removed all clients are notified. If a client + * is using the channel it must 'ack' the removal. A client must not 'ack' a + * removed channel more than once. + * @client - 'this' pointer for the client context + * @chan - channel to be acted upon + * @state - available or removed */ -typedef void (*dma_event_callback) (struct dma_client *client, - struct dma_chan *chan, enum dma_event event); +struct dma_client; +typedef enum dma_state_client (*dma_event_callback) (struct dma_client *client, + struct dma_chan *chan, enum dma_state state); /** * struct dma_client - info on the entity making use of DMA services * @event_callback: func ptr to call when something happens - * @chan_count: number of chans allocated - * @chans_desired: number of chans requested. Can be +/- chan_count - * @lock: protects access to the channels list - * @channels: the list of DMA channels allocated + * @cap_mask: only return channels that satisfy the requested capabilities + * a value of zero corresponds to any capability * @global_node: list_head for global dma_client_list */ struct dma_client { dma_event_callback event_callback; - unsigned int chan_count; - unsigned int chans_desired; - - spinlock_t lock; - struct list_head channels; + dma_cap_mask_t cap_mask; struct list_head global_node; }; +typedef void (*dma_async_tx_callback)(void *dma_async_param); +/** + * struct dma_async_tx_descriptor - async transaction descriptor + * ---dma generic offload fields--- + * @cookie: tracking cookie for this transaction, set to -EBUSY if + * this tx is sitting on a dependency list + * @ack: the descriptor can not be reused until the client acknowledges + * receipt, i.e. has has a chance to establish any dependency chains + * @phys: physical address of the descriptor + * @tx_list: driver common field for operations that require multiple + * descriptors + * @chan: target channel for this operation + * @tx_submit: set the prepared descriptor(s) to be executed by the engine + * @tx_set_dest: set a destination address in a hardware descriptor + * @tx_set_src: set a source address in a hardware descriptor + * @callback: routine to call after this operation is complete + * @callback_param: general parameter to pass to the callback routine + * ---async_tx api specific fields--- + * @depend_list: at completion this list of transactions are submitted + * @depend_node: allow this transaction to be executed after another + * transaction has completed, possibly on another channel + * @parent: pointer to the next level up in the dependency chain + * @lock: protect the dependency list + */ +struct dma_async_tx_descriptor { + dma_cookie_t cookie; + int ack; + dma_addr_t phys; + struct list_head tx_list; + struct dma_chan *chan; + dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); + void (*tx_set_dest)(dma_addr_t addr, + struct dma_async_tx_descriptor *tx, int index); + void (*tx_set_src)(dma_addr_t addr, + struct dma_async_tx_descriptor *tx, int index); + dma_async_tx_callback callback; + void *callback_param; + struct list_head depend_list; + struct list_head depend_node; + struct dma_async_tx_descriptor *parent; + spinlock_t lock; +}; + /** * struct dma_device - info on the entity supplying DMA services * @chancnt: how many DMA channels are supported * @channels: the list of struct dma_chan * @global_node: list_head for global dma_device_list + * @cap_mask: one or more dma_capability flags + * @max_xor: maximum number of xor sources, 0 if no capability * @refcount: reference count * @done: IO completion struct * @dev_id: unique device ID + * @dev: struct device reference for dma mapping api * @device_alloc_chan_resources: allocate resources and return the * number of allocated descriptors * @device_free_chan_resources: release DMA channel's resources - * @device_memcpy_buf_to_buf: memcpy buf pointer to buf pointer - * @device_memcpy_buf_to_pg: memcpy buf pointer to struct page - * @device_memcpy_pg_to_pg: memcpy struct page/offset to struct page/offset - * @device_memcpy_complete: poll the status of an IOAT DMA transaction - * @device_memcpy_issue_pending: push appended descriptors to hardware + * @device_prep_dma_memcpy: prepares a memcpy operation + * @device_prep_dma_xor: prepares a xor operation + * @device_prep_dma_zero_sum: prepares a zero_sum operation + * @device_prep_dma_memset: prepares a memset operation + * @device_prep_dma_interrupt: prepares an end of chain interrupt operation + * @device_dependency_added: async_tx notifies the channel about new deps + * @device_issue_pending: push pending transactions to hardware */ struct dma_device { unsigned int chancnt; struct list_head channels; struct list_head global_node; + dma_cap_mask_t cap_mask; + int max_xor; struct kref refcount; struct completion done; int dev_id; + struct device *dev; int (*device_alloc_chan_resources)(struct dma_chan *chan); void (*device_free_chan_resources)(struct dma_chan *chan); - dma_cookie_t (*device_memcpy_buf_to_buf)(struct dma_chan *chan, - void *dest, void *src, size_t len); - dma_cookie_t (*device_memcpy_buf_to_pg)(struct dma_chan *chan, - struct page *page, unsigned int offset, void *kdata, - size_t len); - dma_cookie_t (*device_memcpy_pg_to_pg)(struct dma_chan *chan, - struct page *dest_pg, unsigned int dest_off, - struct page *src_pg, unsigned int src_off, size_t len); - enum dma_status (*device_memcpy_complete)(struct dma_chan *chan, + + struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( + struct dma_chan *chan, size_t len, int int_en); + struct dma_async_tx_descriptor *(*device_prep_dma_xor)( + struct dma_chan *chan, unsigned int src_cnt, size_t len, + int int_en); + struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)( + struct dma_chan *chan, unsigned int src_cnt, size_t len, + u32 *result, int int_en); + struct dma_async_tx_descriptor *(*device_prep_dma_memset)( + struct dma_chan *chan, int value, size_t len, int int_en); + struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( + struct dma_chan *chan); + + void (*device_dependency_added)(struct dma_chan *chan); + enum dma_status (*device_is_tx_complete)(struct dma_chan *chan, dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used); - void (*device_memcpy_issue_pending)(struct dma_chan *chan); + void (*device_issue_pending)(struct dma_chan *chan); }; /* --- public DMA engine API --- */ -struct dma_client *dma_async_client_register(dma_event_callback event_callback); +void dma_async_client_register(struct dma_client *client); void dma_async_client_unregister(struct dma_client *client); -void dma_async_client_chan_request(struct dma_client *client, - unsigned int number); +void dma_async_client_chan_request(struct dma_client *client); +dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan, + void *dest, void *src, size_t len); +dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan, + struct page *page, unsigned int offset, void *kdata, size_t len); +dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan, + struct page *dest_pg, unsigned int dest_off, struct page *src_pg, + unsigned int src_off, size_t len); +void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, + struct dma_chan *chan); -/** - * dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses - * @chan: DMA channel to offload copy to - * @dest: destination address (virtual) - * @src: source address (virtual) - * @len: length - * - * Both @dest and @src must be mappable to a bus address according to the - * DMA mapping API rules for streaming mappings. - * Both @dest and @src must stay memory resident (kernel memory or locked - * user space pages). - */ -static inline dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan, - void *dest, void *src, size_t len) +static inline void +async_tx_ack(struct dma_async_tx_descriptor *tx) { - int cpu = get_cpu(); - per_cpu_ptr(chan->local, cpu)->bytes_transferred += len; - per_cpu_ptr(chan->local, cpu)->memcpy_count++; - put_cpu(); - - return chan->device->device_memcpy_buf_to_buf(chan, dest, src, len); + tx->ack = 1; } -/** - * dma_async_memcpy_buf_to_pg - offloaded copy from address to page - * @chan: DMA channel to offload copy to - * @page: destination page - * @offset: offset in page to copy to - * @kdata: source address (virtual) - * @len: length - * - * Both @page/@offset and @kdata must be mappable to a bus address according - * to the DMA mapping API rules for streaming mappings. - * Both @page/@offset and @kdata must stay memory resident (kernel memory or - * locked user space pages) - */ -static inline dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan, - struct page *page, unsigned int offset, void *kdata, size_t len) +#define first_dma_cap(mask) __first_dma_cap(&(mask)) +static inline int __first_dma_cap(const dma_cap_mask_t *srcp) { - int cpu = get_cpu(); - per_cpu_ptr(chan->local, cpu)->bytes_transferred += len; - per_cpu_ptr(chan->local, cpu)->memcpy_count++; - put_cpu(); + return min_t(int, DMA_TX_TYPE_END, + find_first_bit(srcp->bits, DMA_TX_TYPE_END)); +} - return chan->device->device_memcpy_buf_to_pg(chan, page, offset, - kdata, len); +#define next_dma_cap(n, mask) __next_dma_cap((n), &(mask)) +static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp) +{ + return min_t(int, DMA_TX_TYPE_END, + find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1)); } -/** - * dma_async_memcpy_pg_to_pg - offloaded copy from page to page - * @chan: DMA channel to offload copy to - * @dest_pg: destination page - * @dest_off: offset in page to copy to - * @src_pg: source page - * @src_off: offset in page to copy from - * @len: length - * - * Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus - * address according to the DMA mapping API rules for streaming mappings. - * Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident - * (kernel memory or locked user space pages). - */ -static inline dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan, - struct page *dest_pg, unsigned int dest_off, struct page *src_pg, - unsigned int src_off, size_t len) +#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) +static inline void +__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) { - int cpu = get_cpu(); - per_cpu_ptr(chan->local, cpu)->bytes_transferred += len; - per_cpu_ptr(chan->local, cpu)->memcpy_count++; - put_cpu(); + set_bit(tx_type, dstp->bits); +} - return chan->device->device_memcpy_pg_to_pg(chan, dest_pg, dest_off, - src_pg, src_off, len); +#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) +static inline int +__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) +{ + return test_bit(tx_type, srcp->bits); } +#define for_each_dma_cap_mask(cap, mask) \ + for ((cap) = first_dma_cap(mask); \ + (cap) < DMA_TX_TYPE_END; \ + (cap) = next_dma_cap((cap), (mask))) + /** - * dma_async_memcpy_issue_pending - flush pending copies to HW + * dma_async_issue_pending - flush pending transactions to HW * @chan: target DMA channel * * This allows drivers to push copies to HW in batches, * reducing MMIO writes where possible. */ -static inline void dma_async_memcpy_issue_pending(struct dma_chan *chan) +static inline void dma_async_issue_pending(struct dma_chan *chan) { - return chan->device->device_memcpy_issue_pending(chan); + return chan->device->device_issue_pending(chan); } +#define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan) + /** - * dma_async_memcpy_complete - poll for transaction completion + * dma_async_is_tx_complete - poll for transaction completion * @chan: DMA channel * @cookie: transaction identifier to check status of * @last: returns last completed cookie, can be NULL @@ -306,12 +376,15 @@ static inline void dma_async_memcpy_issue_pending(struct dma_chan *chan) * internal state and can be used with dma_async_is_complete() to check * the status of multiple cookies without re-checking hardware state. */ -static inline enum dma_status dma_async_memcpy_complete(struct dma_chan *chan, +static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) { - return chan->device->device_memcpy_complete(chan, cookie, last, used); + return chan->device->device_is_tx_complete(chan, cookie, last, used); } +#define dma_async_memcpy_complete(chan, cookie, last, used)\ + dma_async_is_tx_complete(chan, cookie, last, used) + /** * dma_async_is_complete - test a cookie against chan state * @cookie: transaction identifier to test status of @@ -334,6 +407,7 @@ static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, return DMA_IN_PROGRESS; } +enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); /* --- DMA device --- */ @@ -362,5 +436,4 @@ dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov, struct dma_pinned_list *pinned_list, struct page *page, unsigned int offset, size_t len); -#endif /* CONFIG_DMA_ENGINE */ #endif /* DMAENGINE_H */ diff --git a/include/linux/dmi.h b/include/linux/dmi.h index 904bf3d2d90..b8ac7b01c45 100644 --- a/include/linux/dmi.h +++ b/include/linux/dmi.h @@ -12,9 +12,17 @@ enum dmi_field { DMI_PRODUCT_NAME, DMI_PRODUCT_VERSION, DMI_PRODUCT_SERIAL, + DMI_PRODUCT_UUID, DMI_BOARD_VENDOR, DMI_BOARD_NAME, DMI_BOARD_VERSION, + DMI_BOARD_SERIAL, + DMI_BOARD_ASSET_TAG, + DMI_CHASSIS_VENDOR, + DMI_CHASSIS_TYPE, + DMI_CHASSIS_VERSION, + DMI_CHASSIS_SERIAL, + DMI_CHASSIS_ASSET_TAG, DMI_STRING_MAX, }; diff --git a/include/linux/edd.h b/include/linux/edd.h index b2b3e68aa51..7b647822d6d 100644 --- a/include/linux/edd.h +++ b/include/linux/edd.h @@ -49,10 +49,6 @@ #define EDD_MBR_SIG_MAX 16 /* max number of signatures to store */ #define EDD_MBR_SIG_NR_BUF 0x1ea /* addr of number of MBR signtaures at EDD_MBR_SIG_BUF in boot_params - treat this as 1 byte */ -#define EDD_CL_EQUALS 0x3d646465 /* "edd=" */ -#define EDD_CL_OFF 0x666f /* "of" for off */ -#define EDD_CL_SKIP 0x6b73 /* "sk" for skipmbr */ -#define EDD_CL_ON 0x6e6f /* "on" for on */ #ifndef __ASSEMBLY__ diff --git a/include/linux/eeprom_93cx6.h b/include/linux/eeprom_93cx6.h new file mode 100644 index 00000000000..d774b7778c9 --- /dev/null +++ b/include/linux/eeprom_93cx6.h @@ -0,0 +1,72 @@ +/* + Copyright (C) 2004 - 2006 rt2x00 SourceForge Project + <http://rt2x00.serialmonkey.com> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the + Free Software Foundation, Inc., + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* + Module: eeprom_93cx6 + Abstract: EEPROM reader datastructures for 93cx6 chipsets. + Supported chipsets: 93c46 & 93c66. + */ + +/* + * EEPROM operation defines. + */ +#define PCI_EEPROM_WIDTH_93C46 6 +#define PCI_EEPROM_WIDTH_93C66 8 +#define PCI_EEPROM_WIDTH_OPCODE 3 +#define PCI_EEPROM_WRITE_OPCODE 0x05 +#define PCI_EEPROM_READ_OPCODE 0x06 +#define PCI_EEPROM_EWDS_OPCODE 0x10 +#define PCI_EEPROM_EWEN_OPCODE 0x13 + +/** + * struct eeprom_93cx6 - control structure for setting the commands + * for reading the eeprom data. + * @data: private pointer for the driver. + * @register_read(struct eeprom_93cx6 *eeprom): handler to + * read the eeprom register, this function should set all reg_* fields. + * @register_write(struct eeprom_93cx6 *eeprom): handler to + * write to the eeprom register by using all reg_* fields. + * @width: eeprom width, should be one of the PCI_EEPROM_WIDTH_* defines + * @reg_data_in: register field to indicate data input + * @reg_data_out: register field to indicate data output + * @reg_data_clock: register field to set the data clock + * @reg_chip_select: register field to set the chip select + * + * This structure is used for the communication between the driver + * and the eeprom_93cx6 handlers for reading the eeprom. + */ +struct eeprom_93cx6 { + void *data; + + void (*register_read)(struct eeprom_93cx6 *eeprom); + void (*register_write)(struct eeprom_93cx6 *eeprom); + + int width; + + char reg_data_in; + char reg_data_out; + char reg_data_clock; + char reg_chip_select; +}; + +extern void eeprom_93cx6_read(struct eeprom_93cx6 *eeprom, + const u8 word, u16 *data); +extern void eeprom_93cx6_multiread(struct eeprom_93cx6 *eeprom, + const u8 word, __le16 *data, const u16 words); diff --git a/include/linux/errno.h b/include/linux/errno.h index d90b80f9b28..46685832ed9 100644 --- a/include/linux/errno.h +++ b/include/linux/errno.h @@ -5,7 +5,12 @@ #ifdef __KERNEL__ -/* Should never be seen by user programs */ +/* + * These should never be seen by user programs. To return one of ERESTART* + * codes, signal_pending() MUST be set. Note that ptrace can observe these + * at syscall exit tracing, but they will never be left for the debugged user + * process to see. + */ #define ERESTARTSYS 512 #define ERESTARTNOINTR 513 #define ERESTARTNOHAND 514 /* restart if no handler.. */ diff --git a/include/linux/etherdevice.h b/include/linux/etherdevice.h index 071c67abed8..6cdb97365e4 100644 --- a/include/linux/etherdevice.h +++ b/include/linux/etherdevice.h @@ -39,13 +39,8 @@ extern void eth_header_cache_update(struct hh_cache *hh, struct net_device *dev extern int eth_header_cache(struct neighbour *neigh, struct hh_cache *hh); -extern struct net_device *alloc_etherdev(int sizeof_priv); -static inline void eth_copy_and_sum (struct sk_buff *dest, - const unsigned char *src, - int len, int base) -{ - memcpy (dest->data, src, len); -} +extern struct net_device *alloc_etherdev_mq(int sizeof_priv, unsigned int queue_count); +#define alloc_etherdev(sizeof_priv) alloc_etherdev_mq(sizeof_priv, 1) /** * is_zero_ether_addr - Determine if give Ethernet address is all zeros. diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h index f2d248f8cc9..3a632244f31 100644 --- a/include/linux/ethtool.h +++ b/include/linux/ethtool.h @@ -265,6 +265,7 @@ u32 ethtool_op_get_link(struct net_device *dev); u32 ethtool_op_get_tx_csum(struct net_device *dev); int ethtool_op_set_tx_csum(struct net_device *dev, u32 data); int ethtool_op_set_tx_hw_csum(struct net_device *dev, u32 data); +int ethtool_op_set_tx_ipv6_csum(struct net_device *dev, u32 data); u32 ethtool_op_get_sg(struct net_device *dev); int ethtool_op_set_sg(struct net_device *dev, u32 data); u32 ethtool_op_get_tso(struct net_device *dev); diff --git a/include/linux/eventfd.h b/include/linux/eventfd.h index 0d6ecc60b94..b489fc6d0b6 100644 --- a/include/linux/eventfd.h +++ b/include/linux/eventfd.h @@ -19,7 +19,8 @@ int eventfd_signal(struct file *file, int n); #else /* CONFIG_EVENTFD */ #define eventfd_fget(fd) ERR_PTR(-ENOSYS) -#define eventfd_signal(f, n) 0 +static inline int eventfd_signal(struct file *file, int n) +{ return 0; } #endif /* CONFIG_EVENTFD */ diff --git a/include/linux/ext4_fs.h b/include/linux/ext4_fs.h index 54c576d414c..de1f9f78625 100644 --- a/include/linux/ext4_fs.h +++ b/include/linux/ext4_fs.h @@ -32,9 +32,9 @@ /* * Define EXT4_RESERVATION to reserve data blocks for expanding files */ -#define EXT4_DEFAULT_RESERVE_BLOCKS 8 +#define EXT4_DEFAULT_RESERVE_BLOCKS 8 /*max window size: 1024(direct blocks) + 3([t,d]indirect blocks) */ -#define EXT4_MAX_RESERVE_BLOCKS 1027 +#define EXT4_MAX_RESERVE_BLOCKS 1027 #define EXT4_RESERVE_WINDOW_NOT_ALLOCATED 0 /* * Always enable hashed directories @@ -204,12 +204,12 @@ struct ext4_group_desc /* Used to pass group descriptor data when online resize is done */ struct ext4_new_group_input { - __u32 group; /* Group number for this data */ - __u64 block_bitmap; /* Absolute block number of block bitmap */ - __u64 inode_bitmap; /* Absolute block number of inode bitmap */ - __u64 inode_table; /* Absolute block number of inode table start */ - __u32 blocks_count; /* Total number of blocks in this group */ - __u16 reserved_blocks; /* Number of reserved blocks in this group */ + __u32 group; /* Group number for this data */ + __u64 block_bitmap; /* Absolute block number of block bitmap */ + __u64 inode_bitmap; /* Absolute block number of inode bitmap */ + __u64 inode_table; /* Absolute block number of inode table start */ + __u32 blocks_count; /* Total number of blocks in this group */ + __u16 reserved_blocks; /* Number of reserved blocks in this group */ __u16 unused; }; @@ -310,7 +310,7 @@ struct ext4_inode { __u8 l_i_frag; /* Fragment number */ __u8 l_i_fsize; /* Fragment size */ __le16 l_i_file_acl_high; - __le16 l_i_uid_high; /* these 2 fields */ + __le16 l_i_uid_high; /* these 2 fields */ __le16 l_i_gid_high; /* were reserved2[0] */ __u32 l_i_reserved2; } linux2; @@ -513,7 +513,14 @@ struct ext4_super_block { /*150*/ __le32 s_blocks_count_hi; /* Blocks count */ __le32 s_r_blocks_count_hi; /* Reserved blocks count */ __le32 s_free_blocks_count_hi; /* Free blocks count */ - __u32 s_reserved[169]; /* Padding to the end of the block */ + __u16 s_min_extra_isize; /* All inodes have at least # bytes */ + __u16 s_want_extra_isize; /* New inodes should reserve # bytes */ + __u32 s_flags; /* Miscellaneous flags */ + __u16 s_raid_stride; /* RAID stride */ + __u16 s_mmp_interval; /* # seconds to wait in MMP checking */ + __u64 s_mmp_block; /* Block for multi-mount protection */ + __u32 s_raid_stripe_width; /* blocks on all data disks (N*stride)*/ + __u32 s_reserved[163]; /* Padding to the end of the block */ }; #ifdef __KERNEL__ @@ -780,9 +787,9 @@ void ext4_get_group_no_and_offset(struct super_block *sb, ext4_fsblk_t blocknr, * Ok, these declarations are also in <linux/kernel.h> but none of the * ext4 source programs needs to include it so they are duplicated here. */ -# define NORET_TYPE /**/ -# define ATTRIB_NORET __attribute__((noreturn)) -# define NORET_AND noreturn, +# define NORET_TYPE /**/ +# define ATTRIB_NORET __attribute__((noreturn)) +# define NORET_AND noreturn, /* balloc.c */ extern unsigned int ext4_block_group(struct super_block *sb, diff --git a/include/linux/ext4_fs_extents.h b/include/linux/ext4_fs_extents.h index 7eb1d73fc5d..acfe59740b0 100644 --- a/include/linux/ext4_fs_extents.h +++ b/include/linux/ext4_fs_extents.h @@ -151,8 +151,8 @@ typedef int (*ext_prepare_callback)(struct inode *, struct ext4_ext_path *, ((struct ext4_extent_idx *) (((char *) (__hdr__)) + \ sizeof(struct ext4_extent_header))) #define EXT_HAS_FREE_INDEX(__path__) \ - (le16_to_cpu((__path__)->p_hdr->eh_entries) \ - < le16_to_cpu((__path__)->p_hdr->eh_max)) + (le16_to_cpu((__path__)->p_hdr->eh_entries) \ + < le16_to_cpu((__path__)->p_hdr->eh_max)) #define EXT_LAST_EXTENT(__hdr__) \ (EXT_FIRST_EXTENT((__hdr__)) + le16_to_cpu((__hdr__)->eh_entries) - 1) #define EXT_LAST_INDEX(__hdr__) \ @@ -190,6 +190,7 @@ ext4_ext_invalidate_cache(struct inode *inode) extern int ext4_extent_tree_init(handle_t *, struct inode *); extern int ext4_ext_calc_credits_for_insert(struct inode *, struct ext4_ext_path *); +extern unsigned int ext4_ext_check_overlap(struct inode *, struct ext4_extent *, struct ext4_ext_path *); extern int ext4_ext_insert_extent(handle_t *, struct inode *, struct ext4_ext_path *, struct ext4_extent *); extern int ext4_ext_walk_space(struct inode *, unsigned long, unsigned long, ext_prepare_callback, void *); extern struct ext4_ext_path * ext4_ext_find_extent(struct inode *, int, struct ext4_ext_path *); diff --git a/include/linux/ext4_fs_i.h b/include/linux/ext4_fs_i.h index d5b177e5b39..9de49440699 100644 --- a/include/linux/ext4_fs_i.h +++ b/include/linux/ext4_fs_i.h @@ -41,14 +41,14 @@ struct ext4_reserve_window_node { struct ext4_block_alloc_info { /* information about reservation window */ - struct ext4_reserve_window_node rsv_window_node; + struct ext4_reserve_window_node rsv_window_node; /* * was i_next_alloc_block in ext4_inode_info * is the logical (file-relative) number of the * most-recently-allocated block in this file. * We use this for detecting linearly ascending allocation requests. */ - __u32 last_alloc_logical_block; + __u32 last_alloc_logical_block; /* * Was i_next_alloc_goal in ext4_inode_info * is the *physical* companion to i_next_alloc_block. @@ -56,7 +56,7 @@ struct ext4_block_alloc_info { * allocated to this file. This give us the goal (target) for the next * allocation when we detect linearly ascending requests. */ - ext4_fsblk_t last_alloc_physical_block; + ext4_fsblk_t last_alloc_physical_block; }; #define rsv_start rsv_window._rsv_start diff --git a/include/linux/fb.h b/include/linux/fb.h index c654d0e9ce3..66226824ab6 100644 --- a/include/linux/fb.h +++ b/include/linux/fb.h @@ -942,6 +942,7 @@ extern int fb_new_modelist(struct fb_info *info); extern struct fb_info *registered_fb[FB_MAX]; extern int num_registered_fb; +extern struct class *fb_class; static inline void __fb_pad_aligned_buffer(u8 *dst, u32 d_pitch, u8 *src, u32 s_pitch, u32 height) diff --git a/include/linux/firewire-cdev.h b/include/linux/firewire-cdev.h index d4455eb2ae3..1a45d6f41b0 100644 --- a/include/linux/firewire-cdev.h +++ b/include/linux/firewire-cdev.h @@ -30,16 +30,38 @@ #define FW_CDEV_EVENT_REQUEST 0x02 #define FW_CDEV_EVENT_ISO_INTERRUPT 0x03 -/* The 'closure' fields are for user space to use. Data passed in the - * 'closure' field for a request will be returned in the corresponding - * event. It's a 64-bit type so that it's a fixed size type big - * enough to hold a pointer on all platforms. */ - +/** + * struct fw_cdev_event_common - Common part of all fw_cdev_event_ types + * @closure: For arbitrary use by userspace + * @type: Discriminates the fw_cdev_event_ types + * + * This struct may be used to access generic members of all fw_cdev_event_ + * types regardless of the specific type. + * + * Data passed in the @closure field for a request will be returned in the + * corresponding event. It is big enough to hold a pointer on all platforms. + * The ioctl used to set @closure depends on the @type of event. + */ struct fw_cdev_event_common { __u64 closure; __u32 type; }; +/** + * struct fw_cdev_event_bus_reset - Sent when a bus reset occurred + * @closure: See &fw_cdev_event_common; set by %FW_CDEV_IOC_GET_INFO ioctl + * @type: See &fw_cdev_event_common; always %FW_CDEV_EVENT_BUS_RESET + * @node_id: New node ID of this node + * @local_node_id: Node ID of the local node, i.e. of the controller + * @bm_node_id: Node ID of the bus manager + * @irm_node_id: Node ID of the iso resource manager + * @root_node_id: Node ID of the root node + * @generation: New bus generation + * + * This event is sent when the bus the device belongs to goes through a bus + * reset. It provides information about the new bus configuration, such as + * new node ID for this device, new root ID, and others. + */ struct fw_cdev_event_bus_reset { __u64 closure; __u32 type; @@ -51,6 +73,20 @@ struct fw_cdev_event_bus_reset { __u32 generation; }; +/** + * struct fw_cdev_event_response - Sent when a response packet was received + * @closure: See &fw_cdev_event_common; + * set by %FW_CDEV_IOC_SEND_REQUEST ioctl + * @type: See &fw_cdev_event_common; always %FW_CDEV_EVENT_RESPONSE + * @rcode: Response code returned by the remote node + * @length: Data length, i.e. the response's payload size in bytes + * @data: Payload data, if any + * + * This event is sent when the stack receives a response to an outgoing request + * sent by %FW_CDEV_IOC_SEND_REQUEST ioctl. The payload data for responses + * carrying data (read and lock responses) follows immediately and can be + * accessed through the @data field. + */ struct fw_cdev_event_response { __u64 closure; __u32 type; @@ -59,6 +95,25 @@ struct fw_cdev_event_response { __u32 data[0]; }; +/** + * struct fw_cdev_event_request - Sent on incoming request to an address region + * @closure: See &fw_cdev_event_common; set by %FW_CDEV_IOC_ALLOCATE ioctl + * @type: See &fw_cdev_event_common; always %FW_CDEV_EVENT_REQUEST + * @tcode: Transaction code of the incoming request + * @offset: The offset into the 48-bit per-node address space + * @handle: Reference to the kernel-side pending request + * @length: Data length, i.e. the request's payload size in bytes + * @data: Incoming data, if any + * + * This event is sent when the stack receives an incoming request to an address + * region registered using the %FW_CDEV_IOC_ALLOCATE ioctl. The request is + * guaranteed to be completely contained in the specified region. Userspace is + * responsible for sending the response by %FW_CDEV_IOC_SEND_RESPONSE ioctl, + * using the same @handle. + * + * The payload data for requests carrying data (write and lock requests) + * follows immediately and can be accessed through the @data field. + */ struct fw_cdev_event_request { __u64 closure; __u32 type; @@ -69,14 +124,39 @@ struct fw_cdev_event_request { __u32 data[0]; }; +/** + * struct fw_cdev_event_iso_interrupt - Sent when an iso packet was completed + * @closure: See &fw_cdev_event_common; + * set by %FW_CDEV_CREATE_ISO_CONTEXT ioctl + * @type: See &fw_cdev_event_common; always %FW_CDEV_EVENT_ISO_INTERRUPT + * @cycle: Cycle counter of the interrupt packet + * @header_length: Total length of following headers, in bytes + * @header: Stripped headers, if any + * + * This event is sent when the controller has completed an &fw_cdev_iso_packet + * with the %FW_CDEV_ISO_INTERRUPT bit set. In the receive case, the headers + * stripped of all packets up until and including the interrupt packet are + * returned in the @header field. + */ struct fw_cdev_event_iso_interrupt { __u64 closure; __u32 type; __u32 cycle; - __u32 header_length; /* Length in bytes of following headers. */ + __u32 header_length; __u32 header[0]; }; +/** + * union fw_cdev_event - Convenience union of fw_cdev_event_ types + * @common: Valid for all types + * @bus_reset: Valid if @common.type == %FW_CDEV_EVENT_BUS_RESET + * @response: Valid if @common.type == %FW_CDEV_EVENT_RESPONSE + * @request: Valid if @common.type == %FW_CDEV_EVENT_REQUEST + * @iso_interrupt: Valid if @common.type == %FW_CDEV_EVENT_ISO_INTERRUPT + * + * Convenience union for userspace use. Events could be read(2) into a char + * buffer and then cast to this union for further processing. + */ union fw_cdev_event { struct fw_cdev_event_common common; struct fw_cdev_event_bus_reset bus_reset; @@ -105,35 +185,47 @@ union fw_cdev_event { */ #define FW_CDEV_VERSION 1 +/** + * struct fw_cdev_get_info - General purpose information ioctl + * @version: The version field is just a running serial number. + * We never break backwards compatibility, but may add more + * structs and ioctls in later revisions. + * @rom_length: If @rom is non-zero, at most rom_length bytes of configuration + * ROM will be copied into that user space address. In either + * case, @rom_length is updated with the actual length of the + * configuration ROM. + * @rom: If non-zero, address of a buffer to be filled by a copy of the + * local node's configuration ROM + * @bus_reset: If non-zero, address of a buffer to be filled by a + * &struct fw_cdev_event_bus_reset with the current state + * of the bus. This does not cause a bus reset to happen. + * @bus_reset_closure: Value of &closure in this and subsequent bus reset events + * @card: The index of the card this device belongs to + */ struct fw_cdev_get_info { - /* The version field is just a running serial number. We - * never break backwards compatibility. Userspace passes in - * the version it expects and the kernel passes back the - * highest version it can provide. Even if the structs in - * this interface are extended in a later version, the kernel - * will not copy back more data than what was present in the - * interface version userspace expects. */ __u32 version; - - /* If non-zero, at most rom_length bytes of config rom will be - * copied into that user space address. In either case, - * rom_length is updated with the actual length of the config - * rom. */ __u32 rom_length; __u64 rom; - - /* If non-zero, a fw_cdev_event_bus_reset struct will be - * copied here with the current state of the bus. This does - * not cause a bus reset to happen. The value of closure in - * this and sub-sequent bus reset events is set to - * bus_reset_closure. */ __u64 bus_reset; __u64 bus_reset_closure; - - /* The index of the card this devices belongs to. */ __u32 card; }; +/** + * struct fw_cdev_send_request - Send an asynchronous request packet + * @tcode: Transaction code of the request + * @length: Length of outgoing payload, in bytes + * @offset: 48-bit offset at destination node + * @closure: Passed back to userspace in the response event + * @data: Userspace pointer to payload + * @generation: The bus generation where packet is valid + * + * Send a request to the device. This ioctl implements all outgoing requests. + * Both quadlet and block request specify the payload as a pointer to the data + * in the @data field. Once the transaction completes, the kernel writes an + * &fw_cdev_event_request event back. The @closure field is passed back to + * user space in the response event. + */ struct fw_cdev_send_request { __u32 tcode; __u32 length; @@ -143,6 +235,19 @@ struct fw_cdev_send_request { __u32 generation; }; +/** + * struct fw_cdev_send_response - Send an asynchronous response packet + * @rcode: Response code as determined by the userspace handler + * @length: Length of outgoing payload, in bytes + * @data: Userspace pointer to payload + * @handle: The handle from the &fw_cdev_event_request + * + * Send a response to an incoming request. By setting up an address range using + * the %FW_CDEV_IOC_ALLOCATE ioctl, userspace can listen for incoming requests. An + * incoming request will generate an %FW_CDEV_EVENT_REQUEST, and userspace must + * send a reply using this ioctl. The event has a handle to the kernel-side + * pending transaction, which should be used with this ioctl. + */ struct fw_cdev_send_response { __u32 rcode; __u32 length; @@ -150,6 +255,21 @@ struct fw_cdev_send_response { __u32 handle; }; +/** + * struct fw_cdev_allocate - Allocate a CSR address range + * @offset: Start offset of the address range + * @closure: To be passed back to userspace in request events + * @length: Length of the address range, in bytes + * @handle: Handle to the allocation, written by the kernel + * + * Allocate an address range in the 48-bit address space on the local node + * (the controller). This allows userspace to listen for requests with an + * offset within that address range. When the kernel receives a request + * within the range, an &fw_cdev_event_request event will be written back. + * The @closure field is passed back to userspace in the response event. + * The @handle field is an out parameter, returning a handle to the allocated + * range to be used for later deallocation of the range. + */ struct fw_cdev_allocate { __u64 offset; __u64 closure; @@ -157,6 +277,11 @@ struct fw_cdev_allocate { __u32 handle; }; +/** + * struct fw_cdev_deallocate - Free an address range allocation + * @handle: Handle to the address range, as returned by the kernel when the + * range was allocated + */ struct fw_cdev_deallocate { __u32 handle; }; @@ -164,10 +289,41 @@ struct fw_cdev_deallocate { #define FW_CDEV_LONG_RESET 0 #define FW_CDEV_SHORT_RESET 1 +/** + * struct fw_cdev_initiate_bus_reset - Initiate a bus reset + * @type: %FW_CDEV_SHORT_RESET or %FW_CDEV_LONG_RESET + * + * Initiate a bus reset for the bus this device is on. The bus reset can be + * either the original (long) bus reset or the arbitrated (short) bus reset + * introduced in 1394a-2000. + */ struct fw_cdev_initiate_bus_reset { - __u32 type; + __u32 type; /* FW_CDEV_SHORT_RESET or FW_CDEV_LONG_RESET */ }; +/** + * struct fw_cdev_add_descriptor - Add contents to the local node's config ROM + * @immediate: If non-zero, immediate key to insert before pointer + * @key: Upper 8 bits of root directory pointer + * @data: Userspace pointer to contents of descriptor block + * @length: Length of descriptor block data, in bytes + * @handle: Handle to the descriptor, written by the kernel + * + * Add a descriptor block and optionally a preceding immediate key to the local + * node's configuration ROM. + * + * The @key field specifies the upper 8 bits of the descriptor root directory + * pointer and the @data and @length fields specify the contents. The @key + * should be of the form 0xXX000000. The offset part of the root directory entry + * will be filled in by the kernel. + * + * If not 0, the @immediate field specifies an immediate key which will be + * inserted before the root directory pointer. + * + * If successful, the kernel adds the descriptor and writes back a handle to the + * kernel-side object to be used for later removal of the descriptor block and + * immediate key. + */ struct fw_cdev_add_descriptor { __u32 immediate; __u32 key; @@ -176,6 +332,14 @@ struct fw_cdev_add_descriptor { __u32 handle; }; +/** + * struct fw_cdev_remove_descriptor - Remove contents from the configuration ROM + * @handle: Handle to the descriptor, as returned by the kernel when the + * descriptor was added + * + * Remove a descriptor block and accompanying immediate key from the local + * node's configuration ROM. + */ struct fw_cdev_remove_descriptor { __u32 handle; }; @@ -183,12 +347,24 @@ struct fw_cdev_remove_descriptor { #define FW_CDEV_ISO_CONTEXT_TRANSMIT 0 #define FW_CDEV_ISO_CONTEXT_RECEIVE 1 -#define FW_CDEV_ISO_CONTEXT_MATCH_TAG0 1 -#define FW_CDEV_ISO_CONTEXT_MATCH_TAG1 2 -#define FW_CDEV_ISO_CONTEXT_MATCH_TAG2 4 -#define FW_CDEV_ISO_CONTEXT_MATCH_TAG3 8 -#define FW_CDEV_ISO_CONTEXT_MATCH_ALL_TAGS 15 - +/** + * struct fw_cdev_create_iso_context - Create a context for isochronous IO + * @type: %FW_CDEV_ISO_CONTEXT_TRANSMIT or %FW_CDEV_ISO_CONTEXT_RECEIVE + * @header_size: Header size to strip for receive contexts + * @channel: Channel to bind to + * @speed: Speed to transmit at + * @closure: To be returned in &fw_cdev_event_iso_interrupt + * @handle: Handle to context, written back by kernel + * + * Prior to sending or receiving isochronous I/O, a context must be created. + * The context records information about the transmit or receive configuration + * and typically maps to an underlying hardware resource. A context is set up + * for either sending or receiving. It is bound to a specific isochronous + * channel. + * + * If a context was successfully created, the kernel writes back a handle to the + * context, which must be passed in for subsequent operations on that context. + */ struct fw_cdev_create_iso_context { __u32 type; __u32 header_size; @@ -198,16 +374,52 @@ struct fw_cdev_create_iso_context { __u32 handle; }; +#define FW_CDEV_ISO_PAYLOAD_LENGTH(v) (v) +#define FW_CDEV_ISO_INTERRUPT (1 << 16) +#define FW_CDEV_ISO_SKIP (1 << 17) +#define FW_CDEV_ISO_SYNC (1 << 17) +#define FW_CDEV_ISO_TAG(v) ((v) << 18) +#define FW_CDEV_ISO_SY(v) ((v) << 20) +#define FW_CDEV_ISO_HEADER_LENGTH(v) ((v) << 24) + +/** + * struct fw_cdev_iso_packet - Isochronous packet + * @control: Contains the header length (8 uppermost bits), the sy field + * (4 bits), the tag field (2 bits), a sync flag (1 bit), + * a skip flag (1 bit), an interrupt flag (1 bit), and the + * payload length (16 lowermost bits) + * @header: Header and payload + * + * &struct fw_cdev_iso_packet is used to describe isochronous packet queues. + * + * Use the FW_CDEV_ISO_ macros to fill in @control. The sy and tag fields are + * specified by IEEE 1394a and IEC 61883. + * + * FIXME - finish this documentation + */ struct fw_cdev_iso_packet { - __u16 payload_length; /* Length of indirect payload. */ - __u32 interrupt : 1; /* Generate interrupt on this packet */ - __u32 skip : 1; /* Set to not send packet at all. */ - __u32 tag : 2; - __u32 sy : 4; - __u32 header_length : 8; /* Length of immediate header. */ + __u32 control; __u32 header[0]; }; +/** + * struct fw_cdev_queue_iso - Queue isochronous packets for I/O + * @packets: Userspace pointer to packet data + * @data: Pointer into mmap()'ed payload buffer + * @size: Size of packet data in bytes + * @handle: Isochronous context handle + * + * Queue a number of isochronous packets for reception or transmission. + * This ioctl takes a pointer to an array of &fw_cdev_iso_packet structs, + * which describe how to transmit from or receive into a contiguous region + * of a mmap()'ed payload buffer. As part of the packet descriptors, + * a series of headers can be supplied, which will be prepended to the + * payload during DMA. + * + * The kernel may or may not queue all packets, but will write back updated + * values of the @packets, @data and @size fields, so the ioctl can be + * resubmitted easily. + */ struct fw_cdev_queue_iso { __u64 packets; __u64 data; @@ -215,6 +427,23 @@ struct fw_cdev_queue_iso { __u32 handle; }; +#define FW_CDEV_ISO_CONTEXT_MATCH_TAG0 1 +#define FW_CDEV_ISO_CONTEXT_MATCH_TAG1 2 +#define FW_CDEV_ISO_CONTEXT_MATCH_TAG2 4 +#define FW_CDEV_ISO_CONTEXT_MATCH_TAG3 8 +#define FW_CDEV_ISO_CONTEXT_MATCH_ALL_TAGS 15 + +/** + * struct fw_cdev_start_iso - Start an isochronous transmission or reception + * @cycle: Cycle in which to start I/O. If @cycle is greater than or + * equal to 0, the I/O will start on that cycle. + * @sync: Determines the value to wait for for receive packets that have + * the %FW_CDEV_ISO_SYNC bit set + * @tags: Tag filter bit mask. Only valid for isochronous reception. + * Determines the tag values for which packets will be accepted. + * Use FW_CDEV_ISO_CONTEXT_MATCH_ macros to set @tags. + * @handle: Isochronous context handle within which to transmit or receive + */ struct fw_cdev_start_iso { __s32 cycle; __u32 sync; @@ -222,6 +451,10 @@ struct fw_cdev_start_iso { __u32 handle; }; +/** + * struct fw_cdev_stop_iso - Stop an isochronous transmission or reception + * @handle: Handle of isochronous context to stop + */ struct fw_cdev_stop_iso { __u32 handle; }; diff --git a/include/linux/fs.h b/include/linux/fs.h index 7cf0c54a46a..4f0b3bf5983 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -938,6 +938,7 @@ struct super_block { struct list_head s_files; struct block_device *s_bdev; + struct mtd_info *s_mtd; struct list_head s_instances; struct quota_info s_dquot; /* Diskquota specific options */ @@ -1053,7 +1054,7 @@ struct block_device_operations { }; /* - * "descriptor" for what we're up to with a read for sendfile(). + * "descriptor" for what we're up to with a read. * This allows us to use the same read code yet * have multiple different users of the data that * we read from a file. @@ -1104,7 +1105,6 @@ struct file_operations { int (*aio_fsync) (struct kiocb *, int datasync); int (*fasync) (int, struct file *, int); int (*lock) (struct file *, int, struct file_lock *); - ssize_t (*sendfile) (struct file *, loff_t *, size_t, read_actor_t, void *); ssize_t (*sendpage) (struct file *, struct page *, int, size_t, loff_t *, int); unsigned long (*get_unmapped_area)(struct file *, unsigned long, unsigned long, unsigned long, unsigned long); int (*check_flags)(int); @@ -1210,6 +1210,14 @@ static inline void mark_inode_dirty_sync(struct inode *inode) __mark_inode_dirty(inode, I_DIRTY_SYNC); } +/** + * inc_nlink - directly increment an inode's link count + * @inode: inode + * + * This is a low-level filesystem helper to replace any + * direct filesystem manipulation of i_nlink. Currently, + * it is only here for parity with dec_nlink(). + */ static inline void inc_nlink(struct inode *inode) { inode->i_nlink++; @@ -1221,11 +1229,30 @@ static inline void inode_inc_link_count(struct inode *inode) mark_inode_dirty(inode); } +/** + * drop_nlink - directly drop an inode's link count + * @inode: inode + * + * This is a low-level filesystem helper to replace any + * direct filesystem manipulation of i_nlink. In cases + * where we are attempting to track writes to the + * filesystem, a decrement to zero means an imminent + * write when the file is truncated and actually unlinked + * on the filesystem. + */ static inline void drop_nlink(struct inode *inode) { inode->i_nlink--; } +/** + * clear_nlink - directly zero an inode's link count + * @inode: inode + * + * This is a low-level filesystem helper to replace any + * direct filesystem manipulation of i_nlink. See + * drop_nlink() for why we care about i_nlink hitting zero. + */ static inline void clear_nlink(struct inode *inode) { inode->i_nlink = 0; @@ -1734,7 +1761,6 @@ extern ssize_t generic_file_buffered_write(struct kiocb *, const struct iovec *, unsigned long, loff_t, loff_t *, size_t, ssize_t); extern ssize_t do_sync_read(struct file *filp, char __user *buf, size_t len, loff_t *ppos); extern ssize_t do_sync_write(struct file *filp, const char __user *buf, size_t len, loff_t *ppos); -extern ssize_t generic_file_sendfile(struct file *, loff_t *, size_t, read_actor_t, void *); extern void do_generic_mapping_read(struct address_space *mapping, struct file_ra_state *, struct file *, loff_t *, read_descriptor_t *, read_actor_t); @@ -1764,9 +1790,6 @@ extern int nonseekable_open(struct inode * inode, struct file * filp); #ifdef CONFIG_FS_XIP extern ssize_t xip_file_read(struct file *filp, char __user *buf, size_t len, loff_t *ppos); -extern ssize_t xip_file_sendfile(struct file *in_file, loff_t *ppos, - size_t count, read_actor_t actor, - void *target); extern int xip_file_mmap(struct file * file, struct vm_area_struct * vma); extern ssize_t xip_file_write(struct file *filp, const char __user *buf, size_t len, loff_t *ppos); diff --git a/include/linux/futex.h b/include/linux/futex.h index 899fc7f20ed..99650353adf 100644 --- a/include/linux/futex.h +++ b/include/linux/futex.h @@ -17,7 +17,6 @@ union ktime; #define FUTEX_LOCK_PI 6 #define FUTEX_UNLOCK_PI 7 #define FUTEX_TRYLOCK_PI 8 -#define FUTEX_CMP_REQUEUE_PI 9 #define FUTEX_PRIVATE_FLAG 128 #define FUTEX_CMD_MASK ~FUTEX_PRIVATE_FLAG @@ -98,14 +97,9 @@ struct robust_list_head { #define FUTEX_OWNER_DIED 0x40000000 /* - * Some processes have been requeued on this PI-futex - */ -#define FUTEX_WAITER_REQUEUED 0x20000000 - -/* * The rest of the robust-futex field is for the TID: */ -#define FUTEX_TID_MASK 0x0fffffff +#define FUTEX_TID_MASK 0x3fffffff /* * This limit protects against a deliberately circular list. @@ -139,7 +133,6 @@ handle_futex_death(u32 __user *uaddr, struct task_struct *curr, int pi); #define FUT_OFF_MMSHARED 2 /* We set bit 1 if key has a reference on mm */ union futex_key { - u32 __user *uaddr; struct { unsigned long pgoff; struct inode *inode; diff --git a/include/linux/gfs2_ondisk.h b/include/linux/gfs2_ondisk.h index 8b7e4c1e32a..a44a6a078f0 100644 --- a/include/linux/gfs2_ondisk.h +++ b/include/linux/gfs2_ondisk.h @@ -54,18 +54,6 @@ struct gfs2_inum { __be64 no_addr; }; -struct gfs2_inum_host { - __u64 no_formal_ino; - __u64 no_addr; -}; - -static inline int gfs2_inum_equal(const struct gfs2_inum_host *ino1, - const struct gfs2_inum_host *ino2) -{ - return ino1->no_formal_ino == ino2->no_formal_ino && - ino1->no_addr == ino2->no_addr; -} - /* * Generic metadata head structure * Every inplace buffer logged in the journal must start with this. @@ -94,12 +82,6 @@ struct gfs2_meta_header { __be32 __pad1; /* Was incarnation number in gfs1 */ }; -struct gfs2_meta_header_host { - __u32 mh_magic; - __u32 mh_type; - __u32 mh_format; -}; - /* * super-block structure * @@ -139,23 +121,6 @@ struct gfs2_sb { /* In gfs1, quota and license dinodes followed */ }; -struct gfs2_sb_host { - struct gfs2_meta_header_host sb_header; - - __u32 sb_fs_format; - __u32 sb_multihost_format; - - __u32 sb_bsize; - __u32 sb_bsize_shift; - - struct gfs2_inum_host sb_master_dir; /* Was jindex dinode in gfs1 */ - struct gfs2_inum_host sb_root_dir; - - char sb_lockproto[GFS2_LOCKNAME_LEN]; - char sb_locktable[GFS2_LOCKNAME_LEN]; - /* In gfs1, quota and license dinodes followed */ -}; - /* * resource index structure */ @@ -173,14 +138,6 @@ struct gfs2_rindex { __u8 ri_reserved[64]; }; -struct gfs2_rindex_host { - __u64 ri_addr; /* grp block disk address */ - __u64 ri_data0; /* first data location */ - __u32 ri_length; /* length of rgrp header in fs blocks */ - __u32 ri_data; /* num of data blocks in rgrp */ - __u32 ri_bitbytes; /* number of bytes in data bitmaps */ -}; - /* * resource group header structure */ @@ -212,13 +169,6 @@ struct gfs2_rgrp { __u8 rg_reserved[80]; /* Several fields from gfs1 now reserved */ }; -struct gfs2_rgrp_host { - __u32 rg_flags; - __u32 rg_free; - __u32 rg_dinodes; - __u64 rg_igeneration; -}; - /* * quota structure */ @@ -230,12 +180,6 @@ struct gfs2_quota { __u8 qu_reserved[64]; }; -struct gfs2_quota_host { - __u64 qu_limit; - __u64 qu_warn; - __u64 qu_value; -}; - /* * dinode structure */ @@ -315,29 +259,11 @@ struct gfs2_dinode { struct gfs2_inum __pad4; /* Unused even in current gfs1 */ __be64 di_eattr; /* extended attribute block number */ + __be32 di_atime_nsec; /* nsec portion of atime */ + __be32 di_mtime_nsec; /* nsec portion of mtime */ + __be32 di_ctime_nsec; /* nsec portion of ctime */ - __u8 di_reserved[56]; -}; - -struct gfs2_dinode_host { - __u64 di_size; /* number of bytes in file */ - __u64 di_blocks; /* number of blocks in file */ - - /* This section varies from gfs1. Padding added to align with - * remainder of dinode - */ - __u64 di_goal_meta; /* rgrp to alloc from next */ - __u64 di_goal_data; /* data block goal */ - __u64 di_generation; /* generation number for NFS */ - - __u32 di_flags; /* GFS2_DIF_... */ - __u16 di_height; /* height of metadata */ - - /* These only apply to directories */ - __u16 di_depth; /* Number of bits in the table */ - __u32 di_entries; /* The number of entries in the directory */ - - __u64 di_eattr; /* extended attribute block number */ + __u8 di_reserved[44]; }; /* @@ -414,16 +340,6 @@ struct gfs2_log_header { __be32 lh_hash; }; -struct gfs2_log_header_host { - struct gfs2_meta_header_host lh_header; - - __u64 lh_sequence; /* Sequence number of this transaction */ - __u32 lh_flags; /* GFS2_LOG_HEAD_... */ - __u32 lh_tail; /* Block number of log tail */ - __u32 lh_blkno; - __u32 lh_hash; -}; - /* * Log type descriptor */ @@ -464,11 +380,6 @@ struct gfs2_inum_range { __be64 ir_length; }; -struct gfs2_inum_range_host { - __u64 ir_start; - __u64 ir_length; -}; - /* * Statfs change * Describes an change to the pool of free and allocated @@ -481,12 +392,6 @@ struct gfs2_statfs_change { __be64 sc_dinodes; }; -struct gfs2_statfs_change_host { - __u64 sc_total; - __u64 sc_free; - __u64 sc_dinodes; -}; - /* * Quota change * Describes an allocation change for a particular @@ -501,39 +406,12 @@ struct gfs2_quota_change { __be32 qc_id; }; -struct gfs2_quota_change_host { - __u64 qc_change; - __u32 qc_flags; /* GFS2_QCF_... */ - __u32 qc_id; +struct gfs2_quota_lvb { + __be32 qb_magic; + __u32 __pad; + __be64 qb_limit; /* Hard limit of # blocks to alloc */ + __be64 qb_warn; /* Warn user when alloc is above this # */ + __be64 qb_value; /* Current # blocks allocated */ }; -#ifdef __KERNEL__ -/* Translation functions */ - -extern void gfs2_inum_in(struct gfs2_inum_host *no, const void *buf); -extern void gfs2_inum_out(const struct gfs2_inum_host *no, void *buf); -extern void gfs2_sb_in(struct gfs2_sb_host *sb, const void *buf); -extern void gfs2_rindex_in(struct gfs2_rindex_host *ri, const void *buf); -extern void gfs2_rindex_out(const struct gfs2_rindex_host *ri, void *buf); -extern void gfs2_rgrp_in(struct gfs2_rgrp_host *rg, const void *buf); -extern void gfs2_rgrp_out(const struct gfs2_rgrp_host *rg, void *buf); -extern void gfs2_quota_in(struct gfs2_quota_host *qu, const void *buf); -struct gfs2_inode; -extern void gfs2_dinode_out(const struct gfs2_inode *ip, void *buf); -extern void gfs2_ea_header_in(struct gfs2_ea_header *ea, const void *buf); -extern void gfs2_ea_header_out(const struct gfs2_ea_header *ea, void *buf); -extern void gfs2_log_header_in(struct gfs2_log_header_host *lh, const void *buf); -extern void gfs2_inum_range_in(struct gfs2_inum_range_host *ir, const void *buf); -extern void gfs2_inum_range_out(const struct gfs2_inum_range_host *ir, void *buf); -extern void gfs2_statfs_change_in(struct gfs2_statfs_change_host *sc, const void *buf); -extern void gfs2_statfs_change_out(const struct gfs2_statfs_change_host *sc, void *buf); -extern void gfs2_quota_change_in(struct gfs2_quota_change_host *qc, const void *buf); - -/* Printing functions */ - -extern void gfs2_rindex_print(const struct gfs2_rindex_host *ri); -extern void gfs2_dinode_print(const struct gfs2_inode *ip); - -#endif /* __KERNEL__ */ - #endif /* __GFS2_ONDISK_DOT_H__ */ diff --git a/include/linux/gpio_mouse.h b/include/linux/gpio_mouse.h new file mode 100644 index 00000000000..44ed7aa14d8 --- /dev/null +++ b/include/linux/gpio_mouse.h @@ -0,0 +1,61 @@ +/* + * Driver for simulating a mouse on GPIO lines. + * + * Copyright (C) 2007 Atmel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _GPIO_MOUSE_H +#define _GPIO_MOUSE_H + +#define GPIO_MOUSE_POLARITY_ACT_HIGH 0x00 +#define GPIO_MOUSE_POLARITY_ACT_LOW 0x01 + +#define GPIO_MOUSE_PIN_UP 0 +#define GPIO_MOUSE_PIN_DOWN 1 +#define GPIO_MOUSE_PIN_LEFT 2 +#define GPIO_MOUSE_PIN_RIGHT 3 +#define GPIO_MOUSE_PIN_BLEFT 4 +#define GPIO_MOUSE_PIN_BMIDDLE 5 +#define GPIO_MOUSE_PIN_BRIGHT 6 +#define GPIO_MOUSE_PIN_MAX 7 + +/** + * struct gpio_mouse_platform_data + * @scan_ms: integer in ms specifying the scan periode. + * @polarity: Pin polarity, active high or low. + * @up: GPIO line for up value. + * @down: GPIO line for down value. + * @left: GPIO line for left value. + * @right: GPIO line for right value. + * @bleft: GPIO line for left button. + * @bmiddle: GPIO line for middle button. + * @bright: GPIO line for right button. + * + * This struct must be added to the platform_device in the board code. + * It is used by the gpio_mouse driver to setup GPIO lines and to + * calculate mouse movement. + */ +struct gpio_mouse_platform_data { + int scan_ms; + int polarity; + + union { + struct { + int up; + int down; + int left; + int right; + + int bleft; + int bmiddle; + int bright; + }; + int pins[GPIO_MOUSE_PIN_MAX]; + }; +}; + +#endif /* _GPIO_MOUSE_H */ diff --git a/include/linux/hardirq.h b/include/linux/hardirq.h index 7803014f3a1..8d302298a16 100644 --- a/include/linux/hardirq.h +++ b/include/linux/hardirq.h @@ -79,6 +79,19 @@ #endif #ifdef CONFIG_PREEMPT +# define PREEMPT_CHECK_OFFSET 1 +#else +# define PREEMPT_CHECK_OFFSET 0 +#endif + +/* + * Check whether we were atomic before we did preempt_disable(): + * (used by the scheduler) + */ +#define in_atomic_preempt_off() \ + ((preempt_count() & ~PREEMPT_ACTIVE) != PREEMPT_CHECK_OFFSET) + +#ifdef CONFIG_PREEMPT # define preemptible() (preempt_count() == 0 && !irqs_disabled()) # define IRQ_EXIT_OFFSET (HARDIRQ_OFFSET-1) #else diff --git a/include/linux/hid.h b/include/linux/hid.h index 827ee748fd4..898103b401f 100644 --- a/include/linux/hid.h +++ b/include/linux/hid.h @@ -263,19 +263,28 @@ struct hid_item { #define HID_QUIRK_2WHEEL_MOUSE_HACK_5 0x00000100 #define HID_QUIRK_2WHEEL_MOUSE_HACK_ON 0x00000200 #define HID_QUIRK_MIGHTYMOUSE 0x00000400 -#define HID_QUIRK_CYMOTION 0x00000800 -#define HID_QUIRK_POWERBOOK_HAS_FN 0x00001000 -#define HID_QUIRK_POWERBOOK_FN_ON 0x00002000 -#define HID_QUIRK_INVERT_HWHEEL 0x00004000 -#define HID_QUIRK_POWERBOOK_ISO_KEYBOARD 0x00008000 -#define HID_QUIRK_BAD_RELATIVE_KEYS 0x00010000 -#define HID_QUIRK_SKIP_OUTPUT_REPORTS 0x00020000 -#define HID_QUIRK_IGNORE_MOUSE 0x00040000 -#define HID_QUIRK_SONY_PS3_CONTROLLER 0x00080000 -#define HID_QUIRK_LOGITECH_DESCRIPTOR 0x00100000 -#define HID_QUIRK_DUPLICATE_USAGES 0x00200000 -#define HID_QUIRK_RESET_LEDS 0x00400000 -#define HID_QUIRK_SWAPPED_MIN_MAX 0x00800000 +#define HID_QUIRK_POWERBOOK_HAS_FN 0x00000800 +#define HID_QUIRK_POWERBOOK_FN_ON 0x00001000 +#define HID_QUIRK_INVERT_HWHEEL 0x00002000 +#define HID_QUIRK_POWERBOOK_ISO_KEYBOARD 0x00004000 +#define HID_QUIRK_BAD_RELATIVE_KEYS 0x00008000 +#define HID_QUIRK_SKIP_OUTPUT_REPORTS 0x00010000 +#define HID_QUIRK_IGNORE_MOUSE 0x00020000 +#define HID_QUIRK_SONY_PS3_CONTROLLER 0x00040000 +#define HID_QUIRK_DUPLICATE_USAGES 0x00080000 +#define HID_QUIRK_RESET_LEDS 0x00100000 +#define HID_QUIRK_HIDINPUT 0x00200000 +#define HID_QUIRK_LOGITECH_IGNORE_DOUBLED_WHEEL 0x00400000 +#define HID_QUIRK_LOGITECH_EXPANDED_KEYMAP 0x00800000 + +/* + * Separate quirks for runtime report descriptor fixup + */ + +#define HID_QUIRK_RDESC_CYMOTION 0x00000001 +#define HID_QUIRK_RDESC_LOGITECH 0x00000002 +#define HID_QUIRK_RDESC_SWAPPED_MIN_MAX 0x00000004 +#define HID_QUIRK_RDESC_PETALYNX 0x00000008 /* * This is the global environment of the parser. This information is @@ -488,6 +497,11 @@ struct hid_descriptor { #define IS_INPUT_APPLICATION(a) (((a >= 0x00010000) && (a <= 0x00010008)) || (a == 0x00010080) || (a == 0x000c0001)) /* HID core API */ + +#ifdef CONFIG_HID_DEBUG +extern int hid_debug; +#endif + extern void hidinput_hid_event(struct hid_device *, struct hid_field *, struct hid_usage *, __s32); extern void hidinput_report_event(struct hid_device *hid, struct hid_report *report); extern int hidinput_connect(struct hid_device *); @@ -506,6 +520,7 @@ u32 usbhid_lookup_quirk(const u16 idVendor, const u16 idProduct); int usbhid_modify_dquirk(const u16 idVendor, const u16 idProduct, const u32 quirks); int usbhid_quirks_init(char **quirks_param); void usbhid_quirks_exit(void); +void usbhid_fixup_report_descriptor(const u16, const u16, char *, unsigned, char **); #ifdef CONFIG_HID_FF int hid_ff_init(struct hid_device *hid); @@ -523,14 +538,19 @@ static inline int hid_pidff_init(struct hid_device *hid) { return -ENODEV; } #else static inline int hid_ff_init(struct hid_device *hid) { return -1; } #endif -#ifdef DEBUG -#define dbg(format, arg...) printk(KERN_DEBUG "%s: " format "\n" , \ - __FILE__ , ## arg) + +#ifdef CONFIG_HID_DEBUG +#define dbg_hid(format, arg...) if (hid_debug) \ + printk(KERN_DEBUG "%s: " format ,\ + __FILE__ , ## arg) +#define dbg_hid_line(format, arg...) if (hid_debug) \ + printk(format, ## arg) #else -#define dbg(format, arg...) do {} while (0) +#define dbg_hid(format, arg...) do {} while (0) +#define dbg_hid_line dbg_hid #endif -#define err(format, arg...) printk(KERN_ERR "%s: " format "\n" , \ +#define err_hid(format, arg...) printk(KERN_ERR "%s: " format "\n" , \ __FILE__ , ## arg) #endif diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h index b4570b62ab8..2c13715e9dd 100644 --- a/include/linux/hugetlb.h +++ b/include/linux/hugetlb.h @@ -163,7 +163,7 @@ static inline struct hugetlbfs_sb_info *HUGETLBFS_SB(struct super_block *sb) extern const struct file_operations hugetlbfs_file_operations; extern struct vm_operations_struct hugetlb_vm_ops; -struct file *hugetlb_zero_setup(size_t); +struct file *hugetlb_file_setup(const char *name, size_t); int hugetlb_get_quota(struct address_space *mapping); void hugetlb_put_quota(struct address_space *mapping); @@ -185,7 +185,7 @@ static inline void set_file_hugepages(struct file *file) #define is_file_hugepages(file) 0 #define set_file_hugepages(file) BUG() -#define hugetlb_zero_setup(size) ERR_PTR(-ENOSYS) +#define hugetlb_file_setup(name,size) ERR_PTR(-ENOSYS) #endif /* !CONFIG_HUGETLBFS */ diff --git a/include/linux/i2c.h b/include/linux/i2c.h index cae7d618030..2eaba21b9b1 100644 --- a/include/linux/i2c.h +++ b/include/linux/i2c.h @@ -90,7 +90,7 @@ extern s32 i2c_smbus_write_block_data(struct i2c_client * client, const u8 *values); /* Returns the number of read bytes */ extern s32 i2c_smbus_read_i2c_block_data(struct i2c_client * client, - u8 command, u8 *values); + u8 command, u8 length, u8 *values); extern s32 i2c_smbus_write_i2c_block_data(struct i2c_client * client, u8 command, u8 length, const u8 *values); @@ -150,15 +150,20 @@ struct i2c_driver { /** * struct i2c_client - represent an I2C slave device + * @flags: I2C_CLIENT_TEN indicates the device uses a ten bit chip address; + * I2C_CLIENT_PEC indicates it uses SMBus Packet Error Checking * @addr: Address used on the I2C bus connected to the parent adapter. * @name: Indicates the type of the device, usually a chip name that's * generic enough to hide second-sourcing and compatible revisions. + * @adapter: manages the bus segment hosting this I2C device * @dev: Driver model device node for the slave. + * @irq: indicates the IRQ generated by this device (if any) * @driver_name: Identifies new-style driver used with this device; also * used as the module name for hotplug/coldplug modprobe support. * * An i2c_client identifies a single device (i.e. chip) connected to an - * i2c bus. The behaviour is defined by the routines of the driver. + * i2c bus. The behaviour exposed to Linux is defined by the driver + * managing the device. */ struct i2c_client { unsigned short flags; /* div., see below */ @@ -180,7 +185,8 @@ struct i2c_client { static inline struct i2c_client *kobj_to_i2c_client(struct kobject *kobj) { - return to_i2c_client(container_of(kobj, struct device, kobj)); + struct device * const dev = container_of(kobj, struct device, kobj); + return to_i2c_client(dev); } static inline void *i2c_get_clientdata (struct i2c_client *dev) @@ -201,7 +207,7 @@ static inline void i2c_set_clientdata (struct i2c_client *dev, void *data) * @addr: stored in i2c_client.addr * @platform_data: stored in i2c_client.dev.platform_data * @irq: stored in i2c_client.irq - + * * I2C doesn't actually support hardware probing, although controllers and * devices may be able to use I2C_SMBUS_QUICK to tell whether or not there's * a device at a given address. Drivers commonly need more information than @@ -210,7 +216,7 @@ static inline void i2c_set_clientdata (struct i2c_client *dev, void *data) * i2c_board_info is used to build tables of information listing I2C devices * that are present. This information is used to grow the driver model tree * for "new style" I2C drivers. For mainboards this is done statically using - * i2c_register_board_info(), where @bus_num represents an adapter that isn't + * i2c_register_board_info(); bus numbers identify adapters that aren't * yet available. For add-on boards, i2c_new_device() does this dynamically * with the adapter already known. */ @@ -518,8 +524,9 @@ union i2c_smbus_data { #define I2C_SMBUS_WORD_DATA 3 #define I2C_SMBUS_PROC_CALL 4 #define I2C_SMBUS_BLOCK_DATA 5 -#define I2C_SMBUS_I2C_BLOCK_DATA 6 +#define I2C_SMBUS_I2C_BLOCK_BROKEN 6 #define I2C_SMBUS_BLOCK_PROC_CALL 7 /* SMBus 2.0 */ +#define I2C_SMBUS_I2C_BLOCK_DATA 8 /* ----- commands for the ioctl like i2c_command call: diff --git a/include/linux/ide.h b/include/linux/ide.h index 07aba87d369..19ab2580405 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -25,6 +25,7 @@ #include <asm/system.h> #include <asm/io.h> #include <asm/semaphore.h> +#include <asm/mutex.h> /****************************************************************************** * IDE driver configuration options (play with these as desired): @@ -685,6 +686,8 @@ typedef struct hwif_s { u8 mwdma_mask; u8 swdma_mask; + u8 cbl; /* cable type */ + hwif_chipset_t chipset; /* sub-module for tuning.. */ struct pci_dev *pci_dev; /* for pci chipsets */ @@ -735,8 +738,8 @@ typedef struct hwif_s { void (*ide_dma_clear_irq)(ide_drive_t *drive); void (*dma_host_on)(ide_drive_t *drive); void (*dma_host_off)(ide_drive_t *drive); - int (*ide_dma_lostirq)(ide_drive_t *drive); - int (*ide_dma_timeout)(ide_drive_t *drive); + void (*dma_lost_irq)(ide_drive_t *drive); + void (*dma_timeout)(ide_drive_t *drive); void (*OUTB)(u8 addr, unsigned long port); void (*OUTBSYNC)(ide_drive_t *drive, u8 addr, unsigned long port); @@ -791,7 +794,6 @@ typedef struct hwif_s { unsigned sharing_irq: 1; /* 1 = sharing irq with another hwif */ unsigned reset : 1; /* reset after probe */ unsigned autodma : 1; /* auto-attempt using DMA at boot */ - unsigned udma_four : 1; /* 1=ATA-66 capable, 0=default */ unsigned no_lba48 : 1; /* 1 = cannot do LBA48 */ unsigned no_lba48_dma : 1; /* 1 = cannot do LBA48 DMA */ unsigned auto_poll : 1; /* supports nop auto-poll */ @@ -863,7 +865,7 @@ typedef struct hwgroup_s { typedef struct ide_driver_s ide_driver_t; -extern struct semaphore ide_setting_sem; +extern struct mutex ide_setting_mtx; int set_io_32bit(ide_drive_t *, int); int set_pio_mode(ide_drive_t *, int); @@ -1001,6 +1003,7 @@ struct ide_driver_s { struct device_driver gen_driver; int (*probe)(ide_drive_t *); void (*remove)(ide_drive_t *); + void (*resume)(ide_drive_t *); void (*shutdown)(ide_drive_t *); #ifdef CONFIG_IDE_PROC_FS ide_proc_entry_t *proc; @@ -1303,8 +1306,8 @@ extern int __ide_dma_check(ide_drive_t *); extern int ide_dma_setup(ide_drive_t *); extern void ide_dma_start(ide_drive_t *); extern int __ide_dma_end(ide_drive_t *); -extern int __ide_dma_lostirq(ide_drive_t *); -extern int __ide_dma_timeout(ide_drive_t *); +extern void ide_dma_lost_irq(ide_drive_t *); +extern void ide_dma_timeout(ide_drive_t *); #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ #else @@ -1381,11 +1384,11 @@ extern const ide_pio_timings_t ide_pio_timings[6]; extern spinlock_t ide_lock; -extern struct semaphore ide_cfg_sem; +extern struct mutex ide_cfg_mtx; /* * Structure locking: * - * ide_cfg_sem and ide_lock together protect changes to + * ide_cfg_mtx and ide_lock together protect changes to * ide_hwif_t->{next,hwgroup} * ide_drive_t->next * diff --git a/include/linux/idr.h b/include/linux/idr.h index 826803449db..915572fa030 100644 --- a/include/linux/idr.h +++ b/include/linux/idr.h @@ -83,4 +83,33 @@ void idr_remove(struct idr *idp, int id); void idr_destroy(struct idr *idp); void idr_init(struct idr *idp); + +/* + * IDA - IDR based id allocator, use when translation from id to + * pointer isn't necessary. + */ +#define IDA_CHUNK_SIZE 128 /* 128 bytes per chunk */ +#define IDA_BITMAP_LONGS (128 / sizeof(long) - 1) +#define IDA_BITMAP_BITS (IDA_BITMAP_LONGS * sizeof(long) * 8) + +struct ida_bitmap { + long nr_busy; + unsigned long bitmap[IDA_BITMAP_LONGS]; +}; + +struct ida { + struct idr idr; + struct ida_bitmap *free_bitmap; +}; + +#define IDA_INIT(name) { .idr = IDR_INIT(name), .free_bitmap = NULL, } +#define DEFINE_IDA(name) struct ida name = IDA_INIT(name) + +int ida_pre_get(struct ida *ida, gfp_t gfp_mask); +int ida_get_new_above(struct ida *ida, int starting_id, int *p_id); +int ida_get_new(struct ida *ida, int *p_id); +void ida_remove(struct ida *ida, int id); +void ida_destroy(struct ida *ida); +void ida_init(struct ida *ida); + #endif /* __IDR_H__ */ diff --git a/include/linux/ieee80211.h b/include/linux/ieee80211.h index ecd61e8438a..272f8c8c90d 100644 --- a/include/linux/ieee80211.h +++ b/include/linux/ieee80211.h @@ -227,6 +227,17 @@ struct ieee80211_cts { #define WLAN_CAPABILITY_SHORT_SLOT_TIME (1<<10) #define WLAN_CAPABILITY_DSSS_OFDM (1<<13) +/* 802.11g ERP information element */ +#define WLAN_ERP_NON_ERP_PRESENT (1<<0) +#define WLAN_ERP_USE_PROTECTION (1<<1) +#define WLAN_ERP_BARKER_PREAMBLE (1<<2) + +/* WLAN_ERP_BARKER_PREAMBLE values */ +enum { + WLAN_ERP_PREAMBLE_SHORT = 0, + WLAN_ERP_PREAMBLE_LONG = 1, +}; + /* Status codes */ enum ieee80211_statuscode { WLAN_STATUS_SUCCESS = 0, diff --git a/include/linux/if_link.h b/include/linux/if_link.h index 604c2434f71..422084d18ce 100644 --- a/include/linux/if_link.h +++ b/include/linux/if_link.h @@ -76,6 +76,8 @@ enum #define IFLA_WEIGHT IFLA_WEIGHT IFLA_OPERSTATE, IFLA_LINKMODE, + IFLA_LINKINFO, +#define IFLA_LINKINFO IFLA_LINKINFO __IFLA_MAX }; @@ -140,4 +142,49 @@ struct ifla_cacheinfo __u32 retrans_time; }; +enum +{ + IFLA_INFO_UNSPEC, + IFLA_INFO_KIND, + IFLA_INFO_DATA, + IFLA_INFO_XSTATS, + __IFLA_INFO_MAX, +}; + +#define IFLA_INFO_MAX (__IFLA_INFO_MAX - 1) + +/* VLAN section */ + +enum +{ + IFLA_VLAN_UNSPEC, + IFLA_VLAN_ID, + IFLA_VLAN_FLAGS, + IFLA_VLAN_EGRESS_QOS, + IFLA_VLAN_INGRESS_QOS, + __IFLA_VLAN_MAX, +}; + +#define IFLA_VLAN_MAX (__IFLA_VLAN_MAX - 1) + +struct ifla_vlan_flags { + __u32 flags; + __u32 mask; +}; + +enum +{ + IFLA_VLAN_QOS_UNSPEC, + IFLA_VLAN_QOS_MAPPING, + __IFLA_VLAN_QOS_MAX +}; + +#define IFLA_VLAN_QOS_MAX (__IFLA_VLAN_QOS_MAX - 1) + +struct ifla_vlan_qos_mapping +{ + __u32 from; + __u32 to; +}; + #endif /* _LINUX_IF_LINK_H */ diff --git a/include/linux/if_macvlan.h b/include/linux/if_macvlan.h new file mode 100644 index 00000000000..0d9d7ea2c1c --- /dev/null +++ b/include/linux/if_macvlan.h @@ -0,0 +1,9 @@ +#ifndef _LINUX_IF_MACVLAN_H +#define _LINUX_IF_MACVLAN_H + +#ifdef __KERNEL__ + +extern struct sk_buff *(*macvlan_handle_frame_hook)(struct sk_buff *); + +#endif /* __KERNEL__ */ +#endif /* _LINUX_IF_MACVLAN_H */ diff --git a/include/linux/if_ppp.h b/include/linux/if_ppp.h index 768372f07ca..0f2f70d4e48 100644 --- a/include/linux/if_ppp.h +++ b/include/linux/if_ppp.h @@ -110,6 +110,21 @@ struct ifpppcstatsreq { struct ppp_comp_stats stats; }; +/* For PPPIOCGL2TPSTATS */ +struct pppol2tp_ioc_stats { + __u16 tunnel_id; /* redundant */ + __u16 session_id; /* if zero, get tunnel stats */ + __u32 using_ipsec:1; /* valid only for session_id == 0 */ + aligned_u64 tx_packets; + aligned_u64 tx_bytes; + aligned_u64 tx_errors; + aligned_u64 rx_packets; + aligned_u64 rx_bytes; + aligned_u64 rx_seq_discards; + aligned_u64 rx_oos_packets; + aligned_u64 rx_errors; +}; + #define ifr__name b.ifr_ifrn.ifrn_name #define stats_ptr b.ifr_ifru.ifru_data @@ -146,6 +161,7 @@ struct ifpppcstatsreq { #define PPPIOCDISCONN _IO('t', 57) /* disconnect channel */ #define PPPIOCATTCHAN _IOW('t', 56, int) /* attach to ppp channel */ #define PPPIOCGCHAN _IOR('t', 55, int) /* get ppp channel number */ +#define PPPIOCGL2TPSTATS _IOR('t', 54, struct pppol2tp_ioc_stats) #define SIOCGPPPSTATS (SIOCDEVPRIVATE + 0) #define SIOCGPPPVER (SIOCDEVPRIVATE + 1) /* NEVER change this!! */ diff --git a/include/linux/if_pppol2tp.h b/include/linux/if_pppol2tp.h new file mode 100644 index 00000000000..516203b6fde --- /dev/null +++ b/include/linux/if_pppol2tp.h @@ -0,0 +1,69 @@ +/*************************************************************************** + * Linux PPP over L2TP (PPPoL2TP) Socket Implementation (RFC 2661) + * + * This file supplies definitions required by the PPP over L2TP driver + * (pppol2tp.c). All version information wrt this file is located in pppol2tp.c + * + * License: + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#ifndef __LINUX_IF_PPPOL2TP_H +#define __LINUX_IF_PPPOL2TP_H + +#include <asm/types.h> + +#ifdef __KERNEL__ +#include <linux/in.h> +#endif + +/* Structure used to connect() the socket to a particular tunnel UDP + * socket. + */ +struct pppol2tp_addr +{ + pid_t pid; /* pid that owns the fd. + * 0 => current */ + int fd; /* FD of UDP socket to use */ + + struct sockaddr_in addr; /* IP address and port to send to */ + + __be16 s_tunnel, s_session; /* For matching incoming packets */ + __be16 d_tunnel, d_session; /* For sending outgoing packets */ +}; + +/* Socket options: + * DEBUG - bitmask of debug message categories + * SENDSEQ - 0 => don't send packets with sequence numbers + * 1 => send packets with sequence numbers + * RECVSEQ - 0 => receive packet sequence numbers are optional + * 1 => drop receive packets without sequence numbers + * LNSMODE - 0 => act as LAC. + * 1 => act as LNS. + * REORDERTO - reorder timeout (in millisecs). If 0, don't try to reorder. + */ +enum { + PPPOL2TP_SO_DEBUG = 1, + PPPOL2TP_SO_RECVSEQ = 2, + PPPOL2TP_SO_SENDSEQ = 3, + PPPOL2TP_SO_LNSMODE = 4, + PPPOL2TP_SO_REORDERTO = 5, +}; + +/* Debug message categories for the DEBUG socket option */ +enum { + PPPOL2TP_MSG_DEBUG = (1 << 0), /* verbose debug (if + * compiled in) */ + PPPOL2TP_MSG_CONTROL = (1 << 1), /* userspace - kernel + * interface */ + PPPOL2TP_MSG_SEQ = (1 << 2), /* sequence numbers */ + PPPOL2TP_MSG_DATA = (1 << 3), /* data packets */ +}; + + + +#endif diff --git a/include/linux/if_pppox.h b/include/linux/if_pppox.h index 6f987be60fe..25652545ba6 100644 --- a/include/linux/if_pppox.h +++ b/include/linux/if_pppox.h @@ -27,6 +27,7 @@ #include <asm/semaphore.h> #include <linux/ppp_channel.h> #endif /* __KERNEL__ */ +#include <linux/if_pppol2tp.h> /* For user-space programs to pick up these definitions * which they wouldn't get otherwise without defining __KERNEL__ @@ -50,8 +51,9 @@ struct pppoe_addr{ * Protocols supported by AF_PPPOX */ #define PX_PROTO_OE 0 /* Currently just PPPoE */ -#define PX_MAX_PROTO 1 - +#define PX_PROTO_OL2TP 1 /* Now L2TP also */ +#define PX_MAX_PROTO 2 + struct sockaddr_pppox { sa_family_t sa_family; /* address family, AF_PPPOX */ unsigned int sa_protocol; /* protocol identifier */ @@ -60,6 +62,16 @@ struct sockaddr_pppox { }sa_addr; }__attribute__ ((packed)); +/* The use of the above union isn't viable because the size of this + * struct must stay fixed over time -- applications use sizeof(struct + * sockaddr_pppox) to fill it. We use a protocol specific sockaddr + * type instead. + */ +struct sockaddr_pppol2tp { + sa_family_t sa_family; /* address family, AF_PPPOX */ + unsigned int sa_protocol; /* protocol identifier */ + struct pppol2tp_addr pppol2tp; +}__attribute__ ((packed)); /********************************************************************* * diff --git a/include/linux/if_tun.h b/include/linux/if_tun.h index 88aef7b86ef..42eb6945b93 100644 --- a/include/linux/if_tun.h +++ b/include/linux/if_tun.h @@ -36,6 +36,7 @@ struct tun_struct { unsigned long flags; int attached; uid_t owner; + gid_t group; wait_queue_head_t read_wait; struct sk_buff_head readq; @@ -78,6 +79,7 @@ struct tun_struct { #define TUNSETPERSIST _IOW('T', 203, int) #define TUNSETOWNER _IOW('T', 204, int) #define TUNSETLINK _IOW('T', 205, int) +#define TUNSETGROUP _IOW('T', 206, int) /* TUNSETIFF ifr flags */ #define IFF_TUN 0x0001 diff --git a/include/linux/if_vlan.h b/include/linux/if_vlan.h index 81e9bc93569..f8443fdb124 100644 --- a/include/linux/if_vlan.h +++ b/include/linux/if_vlan.h @@ -99,7 +99,7 @@ static inline void vlan_group_set_device(struct vlan_group *vg, int vlan_id, } struct vlan_priority_tci_mapping { - unsigned long priority; + u32 priority; unsigned short vlan_qos; /* This should be shifted when first set, so we only do it * at provisioning time. * ((skb->priority << 13) & 0xE000) @@ -112,7 +112,10 @@ struct vlan_dev_info { /** This will be the mapping that correlates skb->priority to * 3 bits of VLAN QOS tags... */ - unsigned long ingress_priority_map[8]; + unsigned int nr_ingress_mappings; + u32 ingress_priority_map[8]; + + unsigned int nr_egress_mappings; struct vlan_priority_tci_mapping *egress_priority_map[16]; /* hash table */ unsigned short vlan_id; /* The VLAN Identifier for this interface. */ @@ -124,14 +127,8 @@ struct vlan_dev_info { * like DHCP that use packet-filtering and don't understand * 802.1Q */ - struct dev_mc_list *old_mc_list; /* old multi-cast list for the VLAN interface.. - * we save this so we can tell what changes were - * made, in order to feed the right changes down - * to the real hardware... - */ - int old_allmulti; /* similar to above. */ - int old_promiscuity; /* similar to above. */ struct net_device *real_dev; /* the underlying device/interface */ + unsigned char real_dev_addr[ETH_ALEN]; struct proc_dir_entry *dent; /* Holds the proc data */ unsigned long cnt_inc_headroom_on_tx; /* How many times did we have to grow the skb on TX. */ unsigned long cnt_encap_on_xmit; /* How many times did we have to encapsulate the skb on TX. */ @@ -395,6 +392,10 @@ enum vlan_ioctl_cmds { GET_VLAN_VID_CMD /* Get the VID of this VLAN (specified by name) */ }; +enum vlan_flags { + VLAN_FLAG_REORDER_HDR = 0x1, +}; + enum vlan_name_types { VLAN_NAME_TYPE_PLUS_VID, /* Name will look like: vlan0005 */ VLAN_NAME_TYPE_RAW_PLUS_VID, /* name will look like: eth1.0005 */ diff --git a/include/linux/inetdevice.h b/include/linux/inetdevice.h index c0f7aec331c..d83fee2dc64 100644 --- a/include/linux/inetdevice.h +++ b/include/linux/inetdevice.h @@ -3,35 +3,18 @@ #ifdef __KERNEL__ +#include <linux/bitmap.h> #include <linux/if.h> #include <linux/netdevice.h> #include <linux/rcupdate.h> #include <linux/timer.h> +#include <linux/sysctl.h> struct ipv4_devconf { - int accept_redirects; - int send_redirects; - int secure_redirects; - int shared_media; - int accept_source_route; - int rp_filter; - int proxy_arp; - int bootp_relay; - int log_martians; - int forwarding; - int mc_forwarding; - int tag; - int arp_filter; - int arp_announce; - int arp_ignore; - int arp_accept; - int medium_id; - int no_xfrm; - int no_policy; - int force_igmp_version; - int promote_secondaries; void *sysctl; + int data[__NET_IPV4_CONF_MAX - 1]; + DECLARE_BITMAP(state, __NET_IPV4_CONF_MAX - 1); }; extern struct ipv4_devconf ipv4_devconf; @@ -60,30 +43,70 @@ struct in_device struct rcu_head rcu_head; }; -#define IN_DEV_FORWARD(in_dev) ((in_dev)->cnf.forwarding) -#define IN_DEV_MFORWARD(in_dev) (ipv4_devconf.mc_forwarding && (in_dev)->cnf.mc_forwarding) -#define IN_DEV_RPFILTER(in_dev) (ipv4_devconf.rp_filter && (in_dev)->cnf.rp_filter) -#define IN_DEV_SOURCE_ROUTE(in_dev) (ipv4_devconf.accept_source_route && (in_dev)->cnf.accept_source_route) -#define IN_DEV_BOOTP_RELAY(in_dev) (ipv4_devconf.bootp_relay && (in_dev)->cnf.bootp_relay) - -#define IN_DEV_LOG_MARTIANS(in_dev) (ipv4_devconf.log_martians || (in_dev)->cnf.log_martians) -#define IN_DEV_PROXY_ARP(in_dev) (ipv4_devconf.proxy_arp || (in_dev)->cnf.proxy_arp) -#define IN_DEV_SHARED_MEDIA(in_dev) (ipv4_devconf.shared_media || (in_dev)->cnf.shared_media) -#define IN_DEV_TX_REDIRECTS(in_dev) (ipv4_devconf.send_redirects || (in_dev)->cnf.send_redirects) -#define IN_DEV_SEC_REDIRECTS(in_dev) (ipv4_devconf.secure_redirects || (in_dev)->cnf.secure_redirects) -#define IN_DEV_IDTAG(in_dev) ((in_dev)->cnf.tag) -#define IN_DEV_MEDIUM_ID(in_dev) ((in_dev)->cnf.medium_id) -#define IN_DEV_PROMOTE_SECONDARIES(in_dev) (ipv4_devconf.promote_secondaries || (in_dev)->cnf.promote_secondaries) +#define IPV4_DEVCONF(cnf, attr) ((cnf).data[NET_IPV4_CONF_ ## attr - 1]) +#define IPV4_DEVCONF_ALL(attr) IPV4_DEVCONF(ipv4_devconf, attr) + +static inline int ipv4_devconf_get(struct in_device *in_dev, int index) +{ + index--; + return in_dev->cnf.data[index]; +} + +static inline void ipv4_devconf_set(struct in_device *in_dev, int index, + int val) +{ + index--; + set_bit(index, in_dev->cnf.state); + in_dev->cnf.data[index] = val; +} + +static inline void ipv4_devconf_setall(struct in_device *in_dev) +{ + bitmap_fill(in_dev->cnf.state, __NET_IPV4_CONF_MAX - 1); +} + +#define IN_DEV_CONF_GET(in_dev, attr) \ + ipv4_devconf_get((in_dev), NET_IPV4_CONF_ ## attr) +#define IN_DEV_CONF_SET(in_dev, attr, val) \ + ipv4_devconf_set((in_dev), NET_IPV4_CONF_ ## attr, (val)) + +#define IN_DEV_ANDCONF(in_dev, attr) \ + (IPV4_DEVCONF_ALL(attr) && IN_DEV_CONF_GET((in_dev), attr)) +#define IN_DEV_ORCONF(in_dev, attr) \ + (IPV4_DEVCONF_ALL(attr) || IN_DEV_CONF_GET((in_dev), attr)) +#define IN_DEV_MAXCONF(in_dev, attr) \ + (max(IPV4_DEVCONF_ALL(attr), IN_DEV_CONF_GET((in_dev), attr))) + +#define IN_DEV_FORWARD(in_dev) IN_DEV_CONF_GET((in_dev), FORWARDING) +#define IN_DEV_MFORWARD(in_dev) (IPV4_DEVCONF_ALL(MC_FORWARDING) && \ + IPV4_DEVCONF((in_dev)->cnf, \ + MC_FORWARDING)) +#define IN_DEV_RPFILTER(in_dev) IN_DEV_ANDCONF((in_dev), RP_FILTER) +#define IN_DEV_SOURCE_ROUTE(in_dev) IN_DEV_ANDCONF((in_dev), \ + ACCEPT_SOURCE_ROUTE) +#define IN_DEV_BOOTP_RELAY(in_dev) IN_DEV_ANDCONF((in_dev), BOOTP_RELAY) + +#define IN_DEV_LOG_MARTIANS(in_dev) IN_DEV_ORCONF((in_dev), LOG_MARTIANS) +#define IN_DEV_PROXY_ARP(in_dev) IN_DEV_ORCONF((in_dev), PROXY_ARP) +#define IN_DEV_SHARED_MEDIA(in_dev) IN_DEV_ORCONF((in_dev), SHARED_MEDIA) +#define IN_DEV_TX_REDIRECTS(in_dev) IN_DEV_ORCONF((in_dev), SEND_REDIRECTS) +#define IN_DEV_SEC_REDIRECTS(in_dev) IN_DEV_ORCONF((in_dev), \ + SECURE_REDIRECTS) +#define IN_DEV_IDTAG(in_dev) IN_DEV_CONF_GET(in_dev, TAG) +#define IN_DEV_MEDIUM_ID(in_dev) IN_DEV_CONF_GET(in_dev, MEDIUM_ID) +#define IN_DEV_PROMOTE_SECONDARIES(in_dev) \ + IN_DEV_ORCONF((in_dev), \ + PROMOTE_SECONDARIES) #define IN_DEV_RX_REDIRECTS(in_dev) \ ((IN_DEV_FORWARD(in_dev) && \ - (ipv4_devconf.accept_redirects && (in_dev)->cnf.accept_redirects)) \ + IN_DEV_ANDCONF((in_dev), ACCEPT_REDIRECTS)) \ || (!IN_DEV_FORWARD(in_dev) && \ - (ipv4_devconf.accept_redirects || (in_dev)->cnf.accept_redirects))) + IN_DEV_ORCONF((in_dev), ACCEPT_REDIRECTS))) -#define IN_DEV_ARPFILTER(in_dev) (ipv4_devconf.arp_filter || (in_dev)->cnf.arp_filter) -#define IN_DEV_ARP_ANNOUNCE(in_dev) (max(ipv4_devconf.arp_announce, (in_dev)->cnf.arp_announce)) -#define IN_DEV_ARP_IGNORE(in_dev) (max(ipv4_devconf.arp_ignore, (in_dev)->cnf.arp_ignore)) +#define IN_DEV_ARPFILTER(in_dev) IN_DEV_ORCONF((in_dev), ARPFILTER) +#define IN_DEV_ARP_ANNOUNCE(in_dev) IN_DEV_MAXCONF((in_dev), ARP_ANNOUNCE) +#define IN_DEV_ARP_IGNORE(in_dev) IN_DEV_MAXCONF((in_dev), ARP_IGNORE) struct in_ifaddr { @@ -108,7 +131,6 @@ extern struct net_device *ip_dev_find(__be32 addr); extern int inet_addr_onlink(struct in_device *in_dev, __be32 a, __be32 b); extern int devinet_ioctl(unsigned int cmd, void __user *); extern void devinet_init(void); -extern struct in_device *inetdev_init(struct net_device *dev); extern struct in_device *inetdev_by_index(int); extern __be32 inet_select_addr(const struct net_device *dev, __be32 dst, int scope); extern __be32 inet_confirm_addr(const struct net_device *dev, __be32 dst, __be32 local, int scope); diff --git a/include/linux/input.h b/include/linux/input.h index be2bf3a2b03..18c98b54303 100644 --- a/include/linux/input.h +++ b/include/linux/input.h @@ -108,6 +108,13 @@ struct input_absinfo { /* * Keys and buttons + * + * Most of the keys/buttons are modeled after USB HUT 1.12 + * (see http://www.usb.org/developers/hidpage). + * Abbreviations in the comments: + * AC - Application Control + * AL - Application Launch Button + * SC - System Control */ #define KEY_RESERVED 0 @@ -226,7 +233,7 @@ struct input_absinfo { #define KEY_MUTE 113 #define KEY_VOLUMEDOWN 114 #define KEY_VOLUMEUP 115 -#define KEY_POWER 116 +#define KEY_POWER 116 /* SC System Power Down */ #define KEY_KPEQUAL 117 #define KEY_KPPLUSMINUS 118 #define KEY_PAUSE 119 @@ -240,38 +247,39 @@ struct input_absinfo { #define KEY_RIGHTMETA 126 #define KEY_COMPOSE 127 -#define KEY_STOP 128 +#define KEY_STOP 128 /* AC Stop */ #define KEY_AGAIN 129 -#define KEY_PROPS 130 -#define KEY_UNDO 131 +#define KEY_PROPS 130 /* AC Properties */ +#define KEY_UNDO 131 /* AC Undo */ #define KEY_FRONT 132 -#define KEY_COPY 133 -#define KEY_OPEN 134 -#define KEY_PASTE 135 -#define KEY_FIND 136 -#define KEY_CUT 137 -#define KEY_HELP 138 -#define KEY_MENU 139 -#define KEY_CALC 140 +#define KEY_COPY 133 /* AC Copy */ +#define KEY_OPEN 134 /* AC Open */ +#define KEY_PASTE 135 /* AC Paste */ +#define KEY_FIND 136 /* AC Search */ +#define KEY_CUT 137 /* AC Cut */ +#define KEY_HELP 138 /* AL Integrated Help Center */ +#define KEY_MENU 139 /* Menu (show menu) */ +#define KEY_CALC 140 /* AL Calculator */ #define KEY_SETUP 141 -#define KEY_SLEEP 142 -#define KEY_WAKEUP 143 -#define KEY_FILE 144 +#define KEY_SLEEP 142 /* SC System Sleep */ +#define KEY_WAKEUP 143 /* System Wake Up */ +#define KEY_FILE 144 /* AL Local Machine Browser */ #define KEY_SENDFILE 145 #define KEY_DELETEFILE 146 #define KEY_XFER 147 #define KEY_PROG1 148 #define KEY_PROG2 149 -#define KEY_WWW 150 +#define KEY_WWW 150 /* AL Internet Browser */ #define KEY_MSDOS 151 -#define KEY_COFFEE 152 +#define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */ +#define KEY_SCREENLOCK KEY_COFFEE #define KEY_DIRECTION 153 #define KEY_CYCLEWINDOWS 154 #define KEY_MAIL 155 -#define KEY_BOOKMARKS 156 +#define KEY_BOOKMARKS 156 /* AC Bookmarks */ #define KEY_COMPUTER 157 -#define KEY_BACK 158 -#define KEY_FORWARD 159 +#define KEY_BACK 158 /* AC Back */ +#define KEY_FORWARD 159 /* AC Forward */ #define KEY_CLOSECD 160 #define KEY_EJECTCD 161 #define KEY_EJECTCLOSECD 162 @@ -281,20 +289,20 @@ struct input_absinfo { #define KEY_STOPCD 166 #define KEY_RECORD 167 #define KEY_REWIND 168 -#define KEY_PHONE 169 +#define KEY_PHONE 169 /* Media Select Telephone */ #define KEY_ISO 170 -#define KEY_CONFIG 171 -#define KEY_HOMEPAGE 172 -#define KEY_REFRESH 173 -#define KEY_EXIT 174 +#define KEY_CONFIG 171 /* AL Consumer Control Configuration */ +#define KEY_HOMEPAGE 172 /* AC Home */ +#define KEY_REFRESH 173 /* AC Refresh */ +#define KEY_EXIT 174 /* AC Exit */ #define KEY_MOVE 175 #define KEY_EDIT 176 #define KEY_SCROLLUP 177 #define KEY_SCROLLDOWN 178 #define KEY_KPLEFTPAREN 179 #define KEY_KPRIGHTPAREN 180 -#define KEY_NEW 181 -#define KEY_REDO 182 +#define KEY_NEW 181 /* AC New */ +#define KEY_REDO 182 /* AC Redo/Repeat */ #define KEY_F13 183 #define KEY_F14 184 @@ -314,11 +322,11 @@ struct input_absinfo { #define KEY_PROG3 202 #define KEY_PROG4 203 #define KEY_SUSPEND 205 -#define KEY_CLOSE 206 +#define KEY_CLOSE 206 /* AC Close */ #define KEY_PLAY 207 #define KEY_FASTFORWARD 208 #define KEY_BASSBOOST 209 -#define KEY_PRINT 210 +#define KEY_PRINT 210 /* AC Print */ #define KEY_HP 211 #define KEY_CAMERA 212 #define KEY_SOUND 213 @@ -327,11 +335,11 @@ struct input_absinfo { #define KEY_CHAT 216 #define KEY_SEARCH 217 #define KEY_CONNECT 218 -#define KEY_FINANCE 219 +#define KEY_FINANCE 219 /* AL Checkbook/Finance */ #define KEY_SPORT 220 #define KEY_SHOP 221 #define KEY_ALTERASE 222 -#define KEY_CANCEL 223 +#define KEY_CANCEL 223 /* AC Cancel */ #define KEY_BRIGHTNESSDOWN 224 #define KEY_BRIGHTNESSUP 225 #define KEY_MEDIA 226 @@ -341,10 +349,10 @@ struct input_absinfo { #define KEY_KBDILLUMDOWN 229 #define KEY_KBDILLUMUP 230 -#define KEY_SEND 231 -#define KEY_REPLY 232 -#define KEY_FORWARDMAIL 233 -#define KEY_SAVE 234 +#define KEY_SEND 231 /* AC Send */ +#define KEY_REPLY 232 /* AC Reply */ +#define KEY_FORWARDMAIL 233 /* AC Forward Msg */ +#define KEY_SAVE 234 /* AC Save */ #define KEY_DOCUMENTS 235 #define KEY_BATTERY 236 @@ -433,15 +441,15 @@ struct input_absinfo { #define KEY_CLEAR 0x163 #define KEY_POWER2 0x164 #define KEY_OPTION 0x165 -#define KEY_INFO 0x166 +#define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */ #define KEY_TIME 0x167 #define KEY_VENDOR 0x168 #define KEY_ARCHIVE 0x169 -#define KEY_PROGRAM 0x16a +#define KEY_PROGRAM 0x16a /* Media Select Program Guide */ #define KEY_CHANNEL 0x16b #define KEY_FAVORITES 0x16c #define KEY_EPG 0x16d -#define KEY_PVR 0x16e +#define KEY_PVR 0x16e /* Media Select Home */ #define KEY_MHP 0x16f #define KEY_LANGUAGE 0x170 #define KEY_TITLE 0x171 @@ -451,36 +459,36 @@ struct input_absinfo { #define KEY_MODE 0x175 #define KEY_KEYBOARD 0x176 #define KEY_SCREEN 0x177 -#define KEY_PC 0x178 -#define KEY_TV 0x179 -#define KEY_TV2 0x17a -#define KEY_VCR 0x17b -#define KEY_VCR2 0x17c -#define KEY_SAT 0x17d +#define KEY_PC 0x178 /* Media Select Computer */ +#define KEY_TV 0x179 /* Media Select TV */ +#define KEY_TV2 0x17a /* Media Select Cable */ +#define KEY_VCR 0x17b /* Media Select VCR */ +#define KEY_VCR2 0x17c /* VCR Plus */ +#define KEY_SAT 0x17d /* Media Select Satellite */ #define KEY_SAT2 0x17e -#define KEY_CD 0x17f -#define KEY_TAPE 0x180 +#define KEY_CD 0x17f /* Media Select CD */ +#define KEY_TAPE 0x180 /* Media Select Tape */ #define KEY_RADIO 0x181 -#define KEY_TUNER 0x182 +#define KEY_TUNER 0x182 /* Media Select Tuner */ #define KEY_PLAYER 0x183 #define KEY_TEXT 0x184 -#define KEY_DVD 0x185 +#define KEY_DVD 0x185 /* Media Select DVD */ #define KEY_AUX 0x186 #define KEY_MP3 0x187 #define KEY_AUDIO 0x188 #define KEY_VIDEO 0x189 #define KEY_DIRECTORY 0x18a #define KEY_LIST 0x18b -#define KEY_MEMO 0x18c +#define KEY_MEMO 0x18c /* Media Select Messages */ #define KEY_CALENDAR 0x18d #define KEY_RED 0x18e #define KEY_GREEN 0x18f #define KEY_YELLOW 0x190 #define KEY_BLUE 0x191 -#define KEY_CHANNELUP 0x192 -#define KEY_CHANNELDOWN 0x193 +#define KEY_CHANNELUP 0x192 /* Channel Increment */ +#define KEY_CHANNELDOWN 0x193 /* Channel Decrement */ #define KEY_FIRST 0x194 -#define KEY_LAST 0x195 +#define KEY_LAST 0x195 /* Recall Last */ #define KEY_AB 0x196 #define KEY_NEXT 0x197 #define KEY_RESTART 0x198 @@ -491,21 +499,21 @@ struct input_absinfo { #define KEY_DIGITS 0x19d #define KEY_TEEN 0x19e #define KEY_TWEN 0x19f -#define KEY_VIDEOPHONE 0x1a0 -#define KEY_GAMES 0x1a1 -#define KEY_ZOOMIN 0x1a2 -#define KEY_ZOOMOUT 0x1a3 -#define KEY_ZOOMRESET 0x1a4 -#define KEY_WORDPROCESSOR 0x1a5 -#define KEY_EDITOR 0x1a6 -#define KEY_SPREADSHEET 0x1a7 -#define KEY_GRAPHICSEDITOR 0x1a8 -#define KEY_PRESENTATION 0x1a9 -#define KEY_DATABASE 0x1aa -#define KEY_NEWS 0x1ab -#define KEY_VOICEMAIL 0x1ac -#define KEY_ADDRESSBOOK 0x1ad -#define KEY_MESSENGER 0x1ae +#define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */ +#define KEY_GAMES 0x1a1 /* Media Select Games */ +#define KEY_ZOOMIN 0x1a2 /* AC Zoom In */ +#define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */ +#define KEY_ZOOMRESET 0x1a4 /* AC Zoom */ +#define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */ +#define KEY_EDITOR 0x1a6 /* AL Text Editor */ +#define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */ +#define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */ +#define KEY_PRESENTATION 0x1a9 /* AL Presentation App */ +#define KEY_DATABASE 0x1aa /* AL Database App */ +#define KEY_NEWS 0x1ab /* AL Newsreader */ +#define KEY_VOICEMAIL 0x1ac /* AL Voicemail */ +#define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */ +#define KEY_MESSENGER 0x1ae /* AL Instant Messaging */ #define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */ #define KEY_DEL_EOL 0x1c0 @@ -603,6 +611,7 @@ struct input_absinfo { #define SW_LID 0x00 /* set = lid shut */ #define SW_TABLET_MODE 0x01 /* set = tablet mode */ #define SW_HEADPHONE_INSERT 0x02 /* set = inserted */ +#define SW_RADIO 0x03 /* set = radio enabled */ #define SW_MAX 0x0f /* @@ -972,15 +981,15 @@ struct input_dev { struct mutex mutex; /* serializes open and close operations */ unsigned int users; - struct class_device cdev; + struct device dev; union { /* temporarily so while we switching to struct device */ - struct device *parent; - } dev; + struct device *dev; + } cdev; struct list_head h_list; struct list_head node; }; -#define to_input_dev(d) container_of(d, struct input_dev, cdev) +#define to_input_dev(d) container_of(d, struct input_dev, dev) /* * Verify that we are in sync with input_device_id mod_devicetable.h #defines @@ -1087,22 +1096,22 @@ struct input_handle { struct list_head h_node; }; -#define to_dev(n) container_of(n,struct input_dev,node) -#define to_handler(n) container_of(n,struct input_handler,node) -#define to_handle(n) container_of(n,struct input_handle,d_node) -#define to_handle_h(n) container_of(n,struct input_handle,h_node) +#define to_dev(n) container_of(n, struct input_dev, node) +#define to_handler(n) container_of(n, struct input_handler, node) +#define to_handle(n) container_of(n, struct input_handle, d_node) +#define to_handle_h(n) container_of(n, struct input_handle, h_node) struct input_dev *input_allocate_device(void); void input_free_device(struct input_dev *dev); static inline struct input_dev *input_get_device(struct input_dev *dev) { - return to_input_dev(class_device_get(&dev->cdev)); + return to_input_dev(get_device(&dev->dev)); } static inline void input_put_device(struct input_dev *dev) { - class_device_put(&dev->cdev); + put_device(&dev->dev); } static inline void *input_get_drvdata(struct input_dev *dev) diff --git a/include/linux/ioprio.h b/include/linux/ioprio.h index 8e2042b9d47..2eaa142cd06 100644 --- a/include/linux/ioprio.h +++ b/include/linux/ioprio.h @@ -47,8 +47,10 @@ enum { #define IOPRIO_NORM (4) static inline int task_ioprio(struct task_struct *task) { - WARN_ON(!ioprio_valid(task->ioprio)); - return IOPRIO_PRIO_DATA(task->ioprio); + if (ioprio_valid(task->ioprio)) + return IOPRIO_PRIO_DATA(task->ioprio); + + return IOPRIO_NORM; } static inline int task_nice_ioprio(struct task_struct *task) diff --git a/include/linux/ip_mp_alg.h b/include/linux/ip_mp_alg.h deleted file mode 100644 index e234e2008f5..00000000000 --- a/include/linux/ip_mp_alg.h +++ /dev/null @@ -1,22 +0,0 @@ -/* ip_mp_alg.h: IPV4 multipath algorithm support, user-visible values. - * - * Copyright (C) 2004, 2005 Einar Lueck <elueck@de.ibm.com> - * Copyright (C) 2005 David S. Miller <davem@davemloft.net> - */ - -#ifndef _LINUX_IP_MP_ALG_H -#define _LINUX_IP_MP_ALG_H - -enum ip_mp_alg { - IP_MP_ALG_NONE, - IP_MP_ALG_RR, - IP_MP_ALG_DRR, - IP_MP_ALG_RANDOM, - IP_MP_ALG_WRANDOM, - __IP_MP_ALG_MAX -}; - -#define IP_MP_ALG_MAX (__IP_MP_ALG_MAX - 1) - -#endif /* _LINUX_IP_MP_ALG_H */ - diff --git a/include/linux/ipv6.h b/include/linux/ipv6.h index 09ea01a8a99..97983dc9df1 100644 --- a/include/linux/ipv6.h +++ b/include/linux/ipv6.h @@ -27,8 +27,8 @@ struct in6_ifreq { int ifr6_ifindex; }; -#define IPV6_SRCRT_STRICT 0x01 /* this hop must be a neighbor */ -#define IPV6_SRCRT_TYPE_0 0 /* IPv6 type 0 Routing Header */ +#define IPV6_SRCRT_STRICT 0x01 /* Deprecated; will be removed */ +#define IPV6_SRCRT_TYPE_0 0 /* Deprecated; will be removed */ #define IPV6_SRCRT_TYPE_2 2 /* IPv6 type 2 Routing Header */ /* @@ -209,9 +209,8 @@ enum { DEVCONF_RTR_PROBE_INTERVAL, DEVCONF_ACCEPT_RA_RT_INFO_MAX_PLEN, DEVCONF_PROXY_NDP, - __DEVCONF_OPTIMISTIC_DAD, - DEVCONF_ACCEPT_SOURCE_ROUTE, DEVCONF_OPTIMISTIC_DAD, + DEVCONF_ACCEPT_SOURCE_ROUTE, DEVCONF_MAX }; @@ -248,7 +247,7 @@ struct inet6_skb_parm { __u16 lastopt; __u32 nhoff; __u16 flags; -#ifdef CONFIG_IPV6_MIP6 +#if defined(CONFIG_IPV6_MIP6) || defined(CONFIG_IPV6_MIP6_MODULE) __u16 dsthao; #endif @@ -300,8 +299,8 @@ struct ipv6_pinfo { /* pktoption flags */ union { struct { - __u16 srcrt:2, - osrcrt:2, + __u16 srcrt:1, + osrcrt:1, rxinfo:1, rxoinfo:1, rxhlim:1, diff --git a/include/linux/irda.h b/include/linux/irda.h index 945ba311087..8e3735714c1 100644 --- a/include/linux/irda.h +++ b/include/linux/irda.h @@ -216,6 +216,34 @@ struct if_irda_req { #define ifr_dtr ifr_ifru.ifru_line.dtr #define ifr_rts ifr_ifru.ifru_line.rts + +/* IrDA netlink definitions */ +#define IRDA_NL_NAME "irda" +#define IRDA_NL_VERSION 1 + +enum irda_nl_commands { + IRDA_NL_CMD_UNSPEC, + IRDA_NL_CMD_SET_MODE, + IRDA_NL_CMD_GET_MODE, + + __IRDA_NL_CMD_AFTER_LAST +}; +#define IRDA_NL_CMD_MAX (__IRDA_NL_CMD_AFTER_LAST - 1) + +enum nl80211_attrs { + IRDA_NL_ATTR_UNSPEC, + IRDA_NL_ATTR_IFNAME, + IRDA_NL_ATTR_MODE, + + __IRDA_NL_ATTR_AFTER_LAST +}; +#define IRDA_NL_ATTR_MAX (__IRDA_NL_ATTR_AFTER_LAST - 1) + +/* IrDA modes */ +#define IRDA_MODE_PRIMARY 0x1 +#define IRDA_MODE_SECONDARY 0x2 +#define IRDA_MODE_MONITOR 0x4 + #endif /* KERNEL_IRDA_H */ diff --git a/include/linux/kallsyms.h b/include/linux/kallsyms.h index 12178d2c882..5f06527dca2 100644 --- a/include/linux/kallsyms.h +++ b/include/linux/kallsyms.h @@ -5,6 +5,7 @@ #ifndef _LINUX_KALLSYMS_H #define _LINUX_KALLSYMS_H +#include <linux/errno.h> #define KSYM_NAME_LEN 127 #define KSYM_SYMBOL_LEN (sizeof("%s+%#lx/%#lx [%s]") + KSYM_NAME_LEN + \ diff --git a/include/linux/kernel.h b/include/linux/kernel.h index 45353d757cd..7a485250591 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -218,10 +218,14 @@ enum { DUMP_PREFIX_ADDRESS, DUMP_PREFIX_OFFSET }; -extern void hex_dump_to_buffer(const void *buf, size_t len, char *linebuf, - size_t linebuflen); -extern void print_hex_dump(const char *level, int prefix_type, - void *buf, size_t len); +extern void hex_dump_to_buffer(const void *buf, size_t len, + int rowsize, int groupsize, + char *linebuf, size_t linebuflen, bool ascii); +extern void print_hex_dump(const char *level, const char *prefix_str, + int prefix_type, int rowsize, int groupsize, + void *buf, size_t len, bool ascii); +extern void print_hex_dump_bytes(const char *prefix_str, int prefix_type, + void *buf, size_t len); #define hex_asc(x) "0123456789abcdef"[x] #ifdef DEBUG diff --git a/include/linux/kobject.h b/include/linux/kobject.h index c288e41ba33..06cbf41d32d 100644 --- a/include/linux/kobject.h +++ b/include/linux/kobject.h @@ -55,7 +55,7 @@ struct kobject { struct kobject * parent; struct kset * kset; struct kobj_type * ktype; - struct dentry * dentry; + struct sysfs_dirent * sd; wait_queue_head_t poll; }; @@ -71,13 +71,14 @@ extern void kobject_init(struct kobject *); extern void kobject_cleanup(struct kobject *); extern int __must_check kobject_add(struct kobject *); -extern int __must_check kobject_shadow_add(struct kobject *, struct dentry *); +extern int __must_check kobject_shadow_add(struct kobject *kobj, + struct sysfs_dirent *shadow_parent); extern void kobject_del(struct kobject *); extern int __must_check kobject_rename(struct kobject *, const char *new_name); extern int __must_check kobject_shadow_rename(struct kobject *kobj, - struct dentry *new_parent, - const char *new_name); + struct sysfs_dirent *new_parent, + const char *new_name); extern int __must_check kobject_move(struct kobject *, struct kobject *); extern int __must_check kobject_register(struct kobject *); diff --git a/include/linux/ktime.h b/include/linux/ktime.h index c762954bda1..dae7143644f 100644 --- a/include/linux/ktime.h +++ b/include/linux/ktime.h @@ -261,12 +261,34 @@ static inline s64 ktime_to_ns(const ktime_t kt) #endif +/** + * ktime_equal - Compares two ktime_t variables to see if they are equal + * @cmp1: comparable1 + * @cmp2: comparable2 + * + * Compare two ktime_t variables, returns 1 if equal + */ +static inline int ktime_equal(const ktime_t cmp1, const ktime_t cmp2) +{ + return cmp1.tv64 == cmp2.tv64; +} + static inline s64 ktime_to_us(const ktime_t kt) { struct timeval tv = ktime_to_timeval(kt); return (s64) tv.tv_sec * USEC_PER_SEC + tv.tv_usec; } +static inline s64 ktime_us_delta(const ktime_t later, const ktime_t earlier) +{ + return ktime_to_us(ktime_sub(later, earlier)); +} + +static inline ktime_t ktime_add_us(const ktime_t kt, const u64 usec) +{ + return ktime_add_ns(kt, usec * 1000); +} + /* * The resolution of the clocks. The resolution value is returned in * the clock_getres() system call to give application programmers an diff --git a/include/linux/libata.h b/include/linux/libata.h index 85f7b1bd148..47cd2a1c554 100644 --- a/include/linux/libata.h +++ b/include/linux/libata.h @@ -116,6 +116,7 @@ static inline struct device *pci_dev_to_dev(struct pci_dev *pdev) enum { /* various global constants */ LIBATA_MAX_PRD = ATA_MAX_PRD / 2, + LIBATA_DUMB_MAX_PRD = ATA_MAX_PRD / 4, /* Worst case */ ATA_MAX_PORTS = 8, ATA_DEF_QUEUE = 1, /* tag ATA_MAX_QUEUE - 1 is reserved for internal commands */ @@ -136,6 +137,8 @@ enum { ATA_DFLAG_CDB_INTR = (1 << 2), /* device asserts INTRQ when ready for CDB */ ATA_DFLAG_NCQ = (1 << 3), /* device supports NCQ */ ATA_DFLAG_FLUSH_EXT = (1 << 4), /* do FLUSH_EXT instead of FLUSH */ + ATA_DFLAG_ACPI_PENDING = (1 << 5), /* ACPI resume action pending */ + ATA_DFLAG_ACPI_FAILED = (1 << 6), /* ACPI on devcfg has failed */ ATA_DFLAG_CFG_MASK = (1 << 8) - 1, ATA_DFLAG_PIO = (1 << 8), /* device limited to PIO mode */ @@ -171,7 +174,6 @@ enum { ATA_FLAG_SKIP_D2H_BSY = (1 << 12), /* can't wait for the first D2H * Register FIS clearing BSY */ ATA_FLAG_DEBUGMSG = (1 << 13), - ATA_FLAG_SETXFER_POLLING= (1 << 14), /* use polling for SETXFER */ ATA_FLAG_IGN_SIMPLEX = (1 << 15), /* ignore SIMPLEX */ ATA_FLAG_NO_IORDY = (1 << 16), /* controller lacks iordy */ ATA_FLAG_ACPI_SATA = (1 << 17), /* need native SATA ACPI layout */ @@ -194,9 +196,9 @@ enum { ATA_PFLAG_SCSI_HOTPLUG = (1 << 6), /* SCSI hotplug scheduled */ ATA_PFLAG_INITIALIZING = (1 << 7), /* being initialized, don't touch */ - ATA_PFLAG_FLUSH_PORT_TASK = (1 << 16), /* flush port task */ ATA_PFLAG_SUSPENDED = (1 << 17), /* port is suspended (power) */ ATA_PFLAG_PM_PENDING = (1 << 18), /* PM operation pending */ + ATA_PFLAG_GTM_VALID = (1 << 19), /* acpi_gtm data valid */ /* struct ata_queued_cmd flags */ ATA_QCFLAG_ACTIVE = (1 << 0), /* cmd not yet ack'd to scsi lyer */ @@ -299,7 +301,6 @@ enum { ATA_HORKAGE_NODMA = (1 << 1), /* DMA problems */ ATA_HORKAGE_NONCQ = (1 << 2), /* Don't use NCQ */ ATA_HORKAGE_MAX_SEC_128 = (1 << 3), /* Limit max sects to 128 */ - ATA_HORKAGE_DMA_RW_ONLY = (1 << 4), /* ATAPI DMA for RW only */ }; enum hsm_task_states { @@ -365,6 +366,9 @@ struct ata_host { void *private_data; const struct ata_port_operations *ops; unsigned long flags; +#ifdef CONFIG_ATA_ACPI + acpi_handle acpi_handle; +#endif struct ata_port *simplex_claimed; /* channel owning the DMA */ struct ata_port *ports[0]; }; @@ -430,7 +434,11 @@ struct ata_device { struct ata_port *ap; unsigned int devno; /* 0 or 1 */ unsigned long flags; /* ATA_DFLAG_xxx */ + unsigned int horkage; /* List of broken features */ struct scsi_device *sdev; /* attached SCSI device */ +#ifdef CONFIG_ATA_ACPI + acpi_handle acpi_handle; +#endif /* n_sector is used as CLEAR_OFFSET, read comment above CLEAR_OFFSET */ u64 n_sectors; /* size of device, if ATA */ unsigned int class; /* ATA_DEV_xxx */ @@ -458,11 +466,6 @@ struct ata_device { /* error history */ struct ata_ering ering; int spdn_cnt; - unsigned int horkage; /* List of broken features */ -#ifdef CONFIG_ATA_ACPI - /* ACPI objects info */ - acpi_handle obj_handle; -#endif }; /* Offset into struct ata_device. Fields above it are maintained @@ -491,6 +494,17 @@ struct ata_eh_context { unsigned int did_probe_mask; }; +struct ata_acpi_drive +{ + u32 pio; + u32 dma; +} __packed; + +struct ata_acpi_gtm { + struct ata_acpi_drive drive[2]; + u32 flags; +} __packed; + struct ata_port { struct Scsi_Host *scsi_host; /* our co-allocated scsi host */ const struct ata_port_operations *ops; @@ -551,6 +565,10 @@ struct ata_port { void *private_data; +#ifdef CONFIG_ATA_ACPI + acpi_handle acpi_handle; + struct ata_acpi_gtm acpi_gtm; +#endif u8 sector_buf[ATA_SECT_SIZE]; /* owned by EH */ }; @@ -754,11 +772,13 @@ extern u8 ata_check_status(struct ata_port *ap); extern u8 ata_altstatus(struct ata_port *ap); extern void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf); extern int ata_port_start (struct ata_port *ap); +extern int ata_sff_port_start (struct ata_port *ap); extern irqreturn_t ata_interrupt (int irq, void *dev_instance); extern void ata_data_xfer(struct ata_device *adev, unsigned char *buf, unsigned int buflen, int write_data); extern void ata_data_xfer_noirq(struct ata_device *adev, unsigned char *buf, unsigned int buflen, int write_data); +extern void ata_dumb_qc_prep(struct ata_queued_cmd *qc); extern void ata_qc_prep(struct ata_queued_cmd *qc); extern void ata_noop_qc_prep(struct ata_queued_cmd *qc); extern unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc); @@ -773,7 +793,6 @@ extern void ata_id_string(const u16 *id, unsigned char *s, extern void ata_id_c_string(const u16 *id, unsigned char *s, unsigned int ofs, unsigned int len); extern void ata_id_to_dma_mode(struct ata_device *dev, u8 unknown); -extern unsigned long ata_device_blacklisted(const struct ata_device *dev); extern void ata_bmdma_setup (struct ata_queued_cmd *qc); extern void ata_bmdma_start (struct ata_queued_cmd *qc); extern void ata_bmdma_stop(struct ata_queued_cmd *qc); @@ -850,11 +869,11 @@ struct pci_bits { unsigned long val; }; -extern int ata_pci_init_native_host(struct ata_host *host); +extern int ata_pci_init_sff_host(struct ata_host *host); extern int ata_pci_init_bmdma(struct ata_host *host); -extern int ata_pci_prepare_native_host(struct pci_dev *pdev, - const struct ata_port_info * const * ppi, - struct ata_host **r_host); +extern int ata_pci_prepare_sff_host(struct pci_dev *pdev, + const struct ata_port_info * const * ppi, + struct ata_host **r_host); extern int pci_test_config_bits(struct pci_dev *pdev, const struct pci_bits *bits); extern unsigned long ata_pci_default_filter(struct ata_device *, unsigned long); #endif /* CONFIG_PCI */ @@ -1088,11 +1107,9 @@ static inline u8 ata_wait_idle(struct ata_port *ap) { u8 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000); - if (status != 0xff && (status & (ATA_BUSY | ATA_DRQ))) { - if (ata_msg_warn(ap)) - printk(KERN_WARNING "ATA: abnormal status 0x%X on port 0x%p\n", - status, ap->ioaddr.status_addr); - } + if (status != 0xff && (status & (ATA_BUSY | ATA_DRQ))) + DPRINTK("ATA: abnormal status 0x%X on port 0x%p\n", + status, ap->ioaddr.status_addr); return status; } diff --git a/include/linux/lockd/lockd.h b/include/linux/lockd/lockd.h index 05707e2fcca..e2d1ce36b36 100644 --- a/include/linux/lockd/lockd.h +++ b/include/linux/lockd/lockd.h @@ -39,6 +39,7 @@ struct nlm_host { struct hlist_node h_hash; /* doubly linked list */ struct sockaddr_in h_addr; /* peer address */ + struct sockaddr_in h_saddr; /* our address (optional) */ struct rpc_clnt * h_rpcclnt; /* RPC client to talk to peer */ char * h_name; /* remote hostname */ u32 h_version; /* interface version */ diff --git a/include/linux/lzo.h b/include/linux/lzo.h new file mode 100644 index 00000000000..582d8b711a1 --- /dev/null +++ b/include/linux/lzo.h @@ -0,0 +1,44 @@ +#ifndef __LZO_H__ +#define __LZO_H__ +/* + * LZO Public Kernel Interface + * A mini subset of the LZO real-time data compression library + * + * Copyright (C) 1996-2005 Markus F.X.J. Oberhumer <markus@oberhumer.com> + * + * The full LZO package can be found at: + * http://www.oberhumer.com/opensource/lzo/ + * + * Changed for kernel use by: + * Nitin Gupta <nitingupta910@gmail.com> + * Richard Purdie <rpurdie@openedhand.com> + */ + +#define LZO1X_MEM_COMPRESS (16384 * sizeof(unsigned char *)) +#define LZO1X_1_MEM_COMPRESS LZO1X_MEM_COMPRESS + +#define lzo1x_worst_compress(x) (x + (x / 64) + 16 + 3) + +/* This requires 'workmem' of size LZO1X_1_MEM_COMPRESS */ +int lzo1x_1_compress(const unsigned char *src, size_t src_len, + unsigned char *dst, size_t *dst_len, void *wrkmem); + +/* safe decompression with overrun testing */ +int lzo1x_decompress_safe(const unsigned char *src, size_t src_len, + unsigned char *dst, size_t *dst_len); + +/* + * Return values (< 0 = Error) + */ +#define LZO_E_OK 0 +#define LZO_E_ERROR (-1) +#define LZO_E_OUT_OF_MEMORY (-2) +#define LZO_E_NOT_COMPRESSIBLE (-3) +#define LZO_E_INPUT_OVERRUN (-4) +#define LZO_E_OUTPUT_OVERRUN (-5) +#define LZO_E_LOOKBEHIND_OVERRUN (-6) +#define LZO_E_EOF_NOT_FOUND (-7) +#define LZO_E_INPUT_NOT_CONSUMED (-8) +#define LZO_E_NOT_YET_IMPLEMENTED (-9) + +#endif diff --git a/include/linux/mlx4/cmd.h b/include/linux/mlx4/cmd.h index 4fb552d12f7..7d1eaa97de1 100644 --- a/include/linux/mlx4/cmd.h +++ b/include/linux/mlx4/cmd.h @@ -54,6 +54,7 @@ enum { MLX4_CMD_INIT_PORT = 0x9, MLX4_CMD_CLOSE_PORT = 0xa, MLX4_CMD_QUERY_HCA = 0xb, + MLX4_CMD_QUERY_PORT = 0x43, MLX4_CMD_SET_PORT = 0xc, MLX4_CMD_ACCESS_DDR = 0x2e, MLX4_CMD_MAP_ICM = 0xffa, diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h index 8c5f8fd8684..cfb78fb2c04 100644 --- a/include/linux/mlx4/device.h +++ b/include/linux/mlx4/device.h @@ -41,6 +41,7 @@ enum { MLX4_FLAG_MSI_X = 1 << 0, + MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, }; enum { @@ -131,10 +132,10 @@ enum { struct mlx4_caps { u64 fw_ver; int num_ports; - int vl_cap; - int mtu_cap; - int gid_table_len; - int pkey_table_len; + int vl_cap[MLX4_MAX_PORTS + 1]; + int mtu_cap[MLX4_MAX_PORTS + 1]; + int gid_table_len[MLX4_MAX_PORTS + 1]; + int pkey_table_len[MLX4_MAX_PORTS + 1]; int local_ca_ack_delay; int num_uars; int bf_reg_size; @@ -171,10 +172,11 @@ struct mlx4_caps { int num_pds; int reserved_pds; int mtt_entry_sz; + u32 max_msg_sz; u32 page_size_cap; u32 flags; u16 stat_rate_support; - u8 port_width_cap; + u8 port_width_cap[MLX4_MAX_PORTS + 1]; }; struct mlx4_buf_list { @@ -321,8 +323,9 @@ int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); +int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); -int mlx4_INIT_PORT(struct mlx4_dev *dev, struct mlx4_init_port_param *param, int port); +int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]); diff --git a/include/linux/mlx4/qp.h b/include/linux/mlx4/qp.h index 9eeb61adf6a..3968b943259 100644 --- a/include/linux/mlx4/qp.h +++ b/include/linux/mlx4/qp.h @@ -269,6 +269,10 @@ struct mlx4_wqe_data_seg { __be64 addr; }; +enum { + MLX4_INLINE_ALIGN = 64, +}; + struct mlx4_wqe_inline_seg { __be32 byte_count; }; @@ -278,6 +282,9 @@ int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt, struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar, int sqd_event, struct mlx4_qp *qp); +int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp, + struct mlx4_qp_context *context); + static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn) { return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1)); diff --git a/include/linux/mm.h b/include/linux/mm.h index e4183c6c7de..1c1207472bb 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -603,6 +603,10 @@ static inline struct address_space *page_mapping(struct page *page) if (unlikely(PageSwapCache(page))) mapping = &swapper_space; +#ifdef CONFIG_SLUB + else if (unlikely(PageSlab(page))) + mapping = NULL; +#endif else if (unlikely((unsigned long)mapping & PAGE_MAPPING_ANON)) mapping = NULL; return mapping; diff --git a/include/linux/mtd/super.h b/include/linux/mtd/super.h new file mode 100644 index 00000000000..4016dd6fe33 --- /dev/null +++ b/include/linux/mtd/super.h @@ -0,0 +1,30 @@ +/* MTD-based superblock handling + * + * Copyright © 2006 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#ifndef __MTD_SUPER_H__ +#define __MTD_SUPER_H__ + +#ifdef __KERNEL__ + +#include <linux/mtd/mtd.h> +#include <linux/fs.h> +#include <linux/mount.h> + +extern int get_sb_mtd(struct file_system_type *fs_type, int flags, + const char *dev_name, void *data, + int (*fill_super)(struct super_block *, void *, int), + struct vfsmount *mnt); +extern void kill_mtd_super(struct super_block *sb); + + +#endif /* __KERNEL__ */ + +#endif /* __MTD_SUPER_H__ */ diff --git a/include/linux/mv643xx.h b/include/linux/mv643xx.h index c6d4ab86b83..b021b3a2b65 100644 --- a/include/linux/mv643xx.h +++ b/include/linux/mv643xx.h @@ -13,10 +13,6 @@ #ifndef __ASM_MV643XX_H #define __ASM_MV643XX_H -#ifdef __mips__ -#include <asm/addrspace.h> -#include <asm/marvell.h> -#endif #include <asm/types.h> /****************************************/ diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index f671cd2f133..322b5eae57d 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -108,6 +108,14 @@ struct wireless_dev; #define MAX_HEADER (LL_MAX_HEADER + 48) #endif +struct net_device_subqueue +{ + /* Give a control state for each queue. This struct may contain + * per-queue locks in the future. + */ + unsigned long state; +}; + /* * Network device statistics. Akin to the 2.0 ether stats but * with byte counters. @@ -177,19 +185,25 @@ struct netif_rx_stats DECLARE_PER_CPU(struct netif_rx_stats, netdev_rx_stat); +struct dev_addr_list +{ + struct dev_addr_list *next; + u8 da_addr[MAX_ADDR_LEN]; + u8 da_addrlen; + u8 da_synced; + int da_users; + int da_gusers; +}; /* * We tag multicasts with these structures. */ - -struct dev_mc_list -{ - struct dev_mc_list *next; - __u8 dmi_addr[MAX_ADDR_LEN]; - unsigned char dmi_addrlen; - int dmi_users; - int dmi_gusers; -}; + +#define dev_mc_list dev_addr_list +#define dmi_addr da_addr +#define dmi_addrlen da_addrlen +#define dmi_users da_users +#define dmi_gusers da_gusers struct hh_cache { @@ -248,6 +262,8 @@ enum netdev_state_t __LINK_STATE_LINKWATCH_PENDING, __LINK_STATE_DORMANT, __LINK_STATE_QDISC_RUNNING, + /* Set by the netpoll NAPI code */ + __LINK_STATE_POLL_LIST_FROZEN, }; @@ -314,9 +330,10 @@ struct net_device /* Net device features */ unsigned long features; #define NETIF_F_SG 1 /* Scatter/gather IO. */ -#define NETIF_F_IP_CSUM 2 /* Can checksum only TCP/UDP over IPv4. */ +#define NETIF_F_IP_CSUM 2 /* Can checksum TCP/UDP over IPv4. */ #define NETIF_F_NO_CSUM 4 /* Does not require checksum. F.e. loopack. */ #define NETIF_F_HW_CSUM 8 /* Can checksum all the packets. */ +#define NETIF_F_IPV6_CSUM 16 /* Can checksum TCP/UDP over IPV6 */ #define NETIF_F_HIGHDMA 32 /* Can DMA to high memory. */ #define NETIF_F_FRAGLIST 64 /* Scatter/gather IO. */ #define NETIF_F_HW_VLAN_TX 128 /* Transmit VLAN hw acceleration */ @@ -325,6 +342,7 @@ struct net_device #define NETIF_F_VLAN_CHALLENGED 1024 /* Device cannot handle VLAN packets */ #define NETIF_F_GSO 2048 /* Enable software GSO. */ #define NETIF_F_LLTX 4096 /* LockLess TX */ +#define NETIF_F_MULTI_QUEUE 16384 /* Has multiple TX/RX queues */ /* Segmentation offload features */ #define NETIF_F_GSO_SHIFT 16 @@ -338,8 +356,11 @@ struct net_device /* List of features with software fallbacks. */ #define NETIF_F_GSO_SOFTWARE (NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6) + #define NETIF_F_GEN_CSUM (NETIF_F_NO_CSUM | NETIF_F_HW_CSUM) -#define NETIF_F_ALL_CSUM (NETIF_F_IP_CSUM | NETIF_F_GEN_CSUM) +#define NETIF_F_V4_CSUM (NETIF_F_GEN_CSUM | NETIF_F_IP_CSUM) +#define NETIF_F_V6_CSUM (NETIF_F_GEN_CSUM | NETIF_F_IPV6_CSUM) +#define NETIF_F_ALL_CSUM (NETIF_F_V4_CSUM | NETIF_F_V6_CSUM) struct net_device *next_sched; @@ -388,7 +409,10 @@ struct net_device unsigned char addr_len; /* hardware address length */ unsigned short dev_id; /* for shared network cards */ - struct dev_mc_list *mc_list; /* Multicast mac addresses */ + struct dev_addr_list *uc_list; /* Secondary unicast mac addresses */ + int uc_count; /* Number of installed ucasts */ + int uc_promisc; + struct dev_addr_list *mc_list; /* Multicast mac addresses */ int mc_count; /* Number of installed mcasts */ int promiscuity; int allmulti; @@ -493,6 +517,11 @@ struct net_device void *saddr, unsigned len); int (*rebuild_header)(struct sk_buff *skb); +#define HAVE_CHANGE_RX_FLAGS + void (*change_rx_flags)(struct net_device *dev, + int flags); +#define HAVE_SET_RX_MODE + void (*set_rx_mode)(struct net_device *dev); #define HAVE_MULTICAST void (*set_multicast_list)(struct net_device *dev); #define HAVE_SET_MAC_ADDR @@ -535,22 +564,29 @@ struct net_device /* bridge stuff */ struct net_bridge_port *br_port; + /* macvlan */ + struct macvlan_port *macvlan_port; /* class/net/name entry */ struct device dev; /* space for optional statistics and wireless sysfs groups */ struct attribute_group *sysfs_groups[3]; + + /* rtnetlink link ops */ + const struct rtnl_link_ops *rtnl_link_ops; + + /* The TX queue control structures */ + unsigned int egress_subqueue_count; + struct net_device_subqueue egress_subqueue[0]; }; #define to_net_dev(d) container_of(d, struct net_device, dev) #define NETDEV_ALIGN 32 #define NETDEV_ALIGN_CONST (NETDEV_ALIGN - 1) -static inline void *netdev_priv(struct net_device *dev) +static inline void *netdev_priv(const struct net_device *dev) { - return (char *)dev + ((sizeof(struct net_device) - + NETDEV_ALIGN_CONST) - & ~NETDEV_ALIGN_CONST); + return dev->priv; } #define SET_MODULE_OWNER(dev) do { } while (0) @@ -702,6 +738,62 @@ static inline int netif_running(const struct net_device *dev) return test_bit(__LINK_STATE_START, &dev->state); } +/* + * Routines to manage the subqueues on a device. We only need start + * stop, and a check if it's stopped. All other device management is + * done at the overall netdevice level. + * Also test the device if we're multiqueue. + */ +static inline void netif_start_subqueue(struct net_device *dev, u16 queue_index) +{ +#ifdef CONFIG_NETDEVICES_MULTIQUEUE + clear_bit(__LINK_STATE_XOFF, &dev->egress_subqueue[queue_index].state); +#endif +} + +static inline void netif_stop_subqueue(struct net_device *dev, u16 queue_index) +{ +#ifdef CONFIG_NETDEVICES_MULTIQUEUE +#ifdef CONFIG_NETPOLL_TRAP + if (netpoll_trap()) + return; +#endif + set_bit(__LINK_STATE_XOFF, &dev->egress_subqueue[queue_index].state); +#endif +} + +static inline int netif_subqueue_stopped(const struct net_device *dev, + u16 queue_index) +{ +#ifdef CONFIG_NETDEVICES_MULTIQUEUE + return test_bit(__LINK_STATE_XOFF, + &dev->egress_subqueue[queue_index].state); +#else + return 0; +#endif +} + +static inline void netif_wake_subqueue(struct net_device *dev, u16 queue_index) +{ +#ifdef CONFIG_NETDEVICES_MULTIQUEUE +#ifdef CONFIG_NETPOLL_TRAP + if (netpoll_trap()) + return; +#endif + if (test_and_clear_bit(__LINK_STATE_XOFF, + &dev->egress_subqueue[queue_index].state)) + __netif_schedule(dev); +#endif +} + +static inline int netif_is_multiqueue(const struct net_device *dev) +{ +#ifdef CONFIG_NETDEVICES_MULTIQUEUE + return (!!(NETIF_F_MULTI_QUEUE & dev->features)); +#else + return 0; +#endif +} /* Use this variant when it is known for sure that it * is executing from interrupt context. @@ -910,6 +1002,17 @@ static inline int netif_rx_reschedule(struct net_device *dev, int undo) return 0; } +/* same as netif_rx_complete, except that local_irq_save(flags) + * has already been issued + */ +static inline void __netif_rx_complete(struct net_device *dev) +{ + BUG_ON(!test_bit(__LINK_STATE_RX_SCHED, &dev->state)); + list_del(&dev->poll_list); + smp_mb__before_clear_bit(); + clear_bit(__LINK_STATE_RX_SCHED, &dev->state); +} + /* Remove interface from poll list: it must be in the poll list * on current cpu. This primitive is called by dev->poll(), when * it completes the work. The device cannot be out of poll list at this @@ -919,11 +1022,16 @@ static inline void netif_rx_complete(struct net_device *dev) { unsigned long flags; +#ifdef CONFIG_NETPOLL + /* Prevent race with netpoll - yes, this is a kludge. + * But at least it doesn't penalize the non-netpoll + * code path. */ + if (test_bit(__LINK_STATE_POLL_LIST_FROZEN, &dev->state)) + return; +#endif + local_irq_save(flags); - BUG_ON(!test_bit(__LINK_STATE_RX_SCHED, &dev->state)); - list_del(&dev->poll_list); - smp_mb__before_clear_bit(); - clear_bit(__LINK_STATE_RX_SCHED, &dev->state); + __netif_rx_complete(dev); local_irq_restore(flags); } @@ -940,17 +1048,6 @@ static inline void netif_poll_enable(struct net_device *dev) clear_bit(__LINK_STATE_RX_SCHED, &dev->state); } -/* same as netif_rx_complete, except that local_irq_save(flags) - * has already been issued - */ -static inline void __netif_rx_complete(struct net_device *dev) -{ - BUG_ON(!test_bit(__LINK_STATE_RX_SCHED, &dev->state)); - list_del(&dev->poll_list); - smp_mb__before_clear_bit(); - clear_bit(__LINK_STATE_RX_SCHED, &dev->state); -} - static inline void netif_tx_lock(struct net_device *dev) { spin_lock(&dev->_xmit_lock); @@ -995,15 +1092,26 @@ static inline void netif_tx_disable(struct net_device *dev) extern void ether_setup(struct net_device *dev); /* Support for loadable net-drivers */ -extern struct net_device *alloc_netdev(int sizeof_priv, const char *name, - void (*setup)(struct net_device *)); +extern struct net_device *alloc_netdev_mq(int sizeof_priv, const char *name, + void (*setup)(struct net_device *), + unsigned int queue_count); +#define alloc_netdev(sizeof_priv, name, setup) \ + alloc_netdev_mq(sizeof_priv, name, setup, 1) extern int register_netdev(struct net_device *dev); extern void unregister_netdev(struct net_device *dev); -/* Functions used for multicast support */ -extern void dev_mc_upload(struct net_device *dev); +/* Functions used for secondary unicast and multicast support */ +extern void dev_set_rx_mode(struct net_device *dev); +extern void __dev_set_rx_mode(struct net_device *dev); +extern int dev_unicast_delete(struct net_device *dev, void *addr, int alen); +extern int dev_unicast_add(struct net_device *dev, void *addr, int alen); extern int dev_mc_delete(struct net_device *dev, void *addr, int alen, int all); extern int dev_mc_add(struct net_device *dev, void *addr, int alen, int newonly); +extern int dev_mc_sync(struct net_device *to, struct net_device *from); +extern void dev_mc_unsync(struct net_device *to, struct net_device *from); extern void dev_mc_discard(struct net_device *dev); +extern int __dev_addr_delete(struct dev_addr_list **list, int *count, void *addr, int alen, int all); +extern int __dev_addr_add(struct dev_addr_list **list, int *count, void *addr, int alen, int newonly); +extern void __dev_addr_discard(struct dev_addr_list **list); extern void dev_set_promiscuity(struct net_device *dev, int inc); extern void dev_set_allmulti(struct net_device *dev, int inc); extern void netdev_state_change(struct net_device *dev); diff --git a/include/linux/netfilter.h b/include/linux/netfilter.h index 10b5c627570..0eed0b7ab2d 100644 --- a/include/linux/netfilter.h +++ b/include/linux/netfilter.h @@ -275,7 +275,8 @@ struct nf_queue_handler { }; extern int nf_register_queue_handler(int pf, struct nf_queue_handler *qh); -extern int nf_unregister_queue_handler(int pf); +extern int nf_unregister_queue_handler(int pf, + struct nf_queue_handler *qh); extern void nf_unregister_queue_handlers(struct nf_queue_handler *qh); extern void nf_reinject(struct sk_buff *skb, struct nf_info *info, diff --git a/include/linux/netfilter/nf_conntrack_pptp.h b/include/linux/netfilter/nf_conntrack_pptp.h index 9d8144a488c..c93061f3314 100644 --- a/include/linux/netfilter/nf_conntrack_pptp.h +++ b/include/linux/netfilter/nf_conntrack_pptp.h @@ -4,6 +4,8 @@ #include <linux/netfilter/nf_conntrack_common.h> +extern const char *pptp_msg_name[]; + /* state of the control session */ enum pptp_ctrlsess_state { PPTP_SESSION_NONE, /* no session present */ diff --git a/include/linux/netfilter/x_tables.h b/include/linux/netfilter/x_tables.h index 7e733a6ba4f..64f425a855b 100644 --- a/include/linux/netfilter/x_tables.h +++ b/include/linux/netfilter/x_tables.h @@ -141,22 +141,22 @@ struct xt_match /* Arguments changed since 2.6.9, as this must now handle non-linear skb, using skb_header_pointer and skb_ip_make_writable. */ - int (*match)(const struct sk_buff *skb, - const struct net_device *in, - const struct net_device *out, - const struct xt_match *match, - const void *matchinfo, - int offset, - unsigned int protoff, - int *hotdrop); + bool (*match)(const struct sk_buff *skb, + const struct net_device *in, + const struct net_device *out, + const struct xt_match *match, + const void *matchinfo, + int offset, + unsigned int protoff, + bool *hotdrop); /* Called when user tries to insert an entry of this type. */ /* Should return true or false. */ - int (*checkentry)(const char *tablename, - const void *ip, - const struct xt_match *match, - void *matchinfo, - unsigned int hook_mask); + bool (*checkentry)(const char *tablename, + const void *ip, + const struct xt_match *match, + void *matchinfo, + unsigned int hook_mask); /* Called when entry of this type deleted. */ void (*destroy)(const struct xt_match *match, void *matchinfo); @@ -202,11 +202,11 @@ struct xt_target hook_mask is a bitmask of hooks from which it can be called. */ /* Should return true or false. */ - int (*checkentry)(const char *tablename, - const void *entry, - const struct xt_target *target, - void *targinfo, - unsigned int hook_mask); + bool (*checkentry)(const char *tablename, + const void *entry, + const struct xt_target *target, + void *targinfo, + unsigned int hook_mask); /* Called when entry of this type deleted. */ void (*destroy)(const struct xt_target *target, void *targinfo); diff --git a/include/linux/netfilter/xt_connlimit.h b/include/linux/netfilter/xt_connlimit.h new file mode 100644 index 00000000000..90ae8b474cb --- /dev/null +++ b/include/linux/netfilter/xt_connlimit.h @@ -0,0 +1,17 @@ +#ifndef _XT_CONNLIMIT_H +#define _XT_CONNLIMIT_H + +struct xt_connlimit_data; + +struct xt_connlimit_info { + union { + u_int32_t v4_mask; + u_int32_t v6_mask[4]; + }; + unsigned int limit, inverse; + + /* this needs to be at the end */ + struct xt_connlimit_data *data __attribute__((aligned(8))); +}; + +#endif /* _XT_CONNLIMIT_H */ diff --git a/include/linux/netfilter/xt_u32.h b/include/linux/netfilter/xt_u32.h new file mode 100644 index 00000000000..9947f56cdbd --- /dev/null +++ b/include/linux/netfilter/xt_u32.h @@ -0,0 +1,40 @@ +#ifndef _XT_U32_H +#define _XT_U32_H 1 + +enum xt_u32_ops { + XT_U32_AND, + XT_U32_LEFTSH, + XT_U32_RIGHTSH, + XT_U32_AT, +}; + +struct xt_u32_location_element { + u_int32_t number; + u_int8_t nextop; +}; + +struct xt_u32_value_element { + u_int32_t min; + u_int32_t max; +}; + +/* + * Any way to allow for an arbitrary number of elements? + * For now, I settle with a limit of 10 each. + */ +#define XT_U32_MAXSIZE 10 + +struct xt_u32_test { + struct xt_u32_location_element location[XT_U32_MAXSIZE+1]; + struct xt_u32_value_element value[XT_U32_MAXSIZE+1]; + u_int8_t nnums; + u_int8_t nvalues; +}; + +struct xt_u32 { + struct xt_u32_test tests[XT_U32_MAXSIZE+1]; + u_int8_t ntests; + u_int8_t invert; +}; + +#endif /* _XT_U32_H */ diff --git a/include/linux/netfilter_ipv4/ip_tables.h b/include/linux/netfilter_ipv4/ip_tables.h index 2f46dd728ee..e992cd6b28f 100644 --- a/include/linux/netfilter_ipv4/ip_tables.h +++ b/include/linux/netfilter_ipv4/ip_tables.h @@ -264,6 +264,26 @@ ipt_get_target(struct ipt_entry *e) __ret; \ }) +/* fn returns 0 to continue iteration */ +#define IPT_ENTRY_ITERATE_CONTINUE(entries, size, n, fn, args...) \ +({ \ + unsigned int __i, __n; \ + int __ret = 0; \ + struct ipt_entry *__entry; \ + \ + for (__i = 0, __n = 0; __i < (size); \ + __i += __entry->next_offset, __n++) { \ + __entry = (void *)(entries) + __i; \ + if (__n < n) \ + continue; \ + \ + __ret = fn(__entry , ## args); \ + if (__ret != 0) \ + break; \ + } \ + __ret; \ +}) + /* * Main firewall chains definitions and global var's definitions. */ diff --git a/include/linux/netfilter_ipv4/ipt_CLUSTERIP.h b/include/linux/netfilter_ipv4/ipt_CLUSTERIP.h index d9bceedfb3d..daf50be22c9 100644 --- a/include/linux/netfilter_ipv4/ipt_CLUSTERIP.h +++ b/include/linux/netfilter_ipv4/ipt_CLUSTERIP.h @@ -18,13 +18,13 @@ struct clusterip_config; struct ipt_clusterip_tgt_info { u_int32_t flags; - + /* only relevant for new ones */ u_int8_t clustermac[6]; u_int16_t num_total_nodes; u_int16_t num_local_nodes; u_int16_t local_nodes[CLUSTERIP_MAX_NODES]; - enum clusterip_hashmode hash_mode; + u_int32_t hash_mode; u_int32_t hash_initval; struct clusterip_config *config; diff --git a/include/linux/netfilter_ipv6/ip6_tables.h b/include/linux/netfilter_ipv6/ip6_tables.h index 4686f8342cb..9a720f05888 100644 --- a/include/linux/netfilter_ipv6/ip6_tables.h +++ b/include/linux/netfilter_ipv6/ip6_tables.h @@ -44,8 +44,14 @@ struct ip6t_ip6 { char iniface[IFNAMSIZ], outiface[IFNAMSIZ]; unsigned char iniface_mask[IFNAMSIZ], outiface_mask[IFNAMSIZ]; - /* ARGH, HopByHop uses 0, so can't do 0 = ANY, - instead IP6T_F_NOPROTO must be set */ + /* Upper protocol number + * - The allowed value is 0 (any) or protocol number of last parsable + * header, which is 50 (ESP), 59 (No Next Header), 135 (MH), or + * the non IPv6 extension headers. + * - The protocol numbers of IPv6 extension headers except of ESP and + * MH do not match any packets. + * - You also need to set IP6T_FLAGS_PROTO to "flags" to check protocol. + */ u_int16_t proto; /* TOS to match iff flags & IP6T_F_TOS */ u_int8_t tos; diff --git a/include/linux/nfs4.h b/include/linux/nfs4.h index 7e7f33a38fc..8726491de15 100644 --- a/include/linux/nfs4.h +++ b/include/linux/nfs4.h @@ -15,6 +15,7 @@ #include <linux/types.h> +#define NFS4_BITMAP_SIZE 2 #define NFS4_VERIFIER_SIZE 8 #define NFS4_STATEID_SIZE 16 #define NFS4_FHSIZE 128 diff --git a/include/linux/nfs4_mount.h b/include/linux/nfs4_mount.h index 26b4c83f831..a0dcf665565 100644 --- a/include/linux/nfs4_mount.h +++ b/include/linux/nfs4_mount.h @@ -65,6 +65,7 @@ struct nfs4_mount_data { #define NFS4_MOUNT_NOCTO 0x0010 /* 1 */ #define NFS4_MOUNT_NOAC 0x0020 /* 1 */ #define NFS4_MOUNT_STRICTLOCK 0x1000 /* 1 */ -#define NFS4_MOUNT_FLAGMASK 0xFFFF +#define NFS4_MOUNT_UNSHARED 0x8000 /* 1 */ +#define NFS4_MOUNT_FLAGMASK 0x9033 #endif diff --git a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h index 0543439a97a..c098ae194f7 100644 --- a/include/linux/nfs_fs.h +++ b/include/linux/nfs_fs.h @@ -30,7 +30,9 @@ #ifdef __KERNEL__ #include <linux/in.h> +#include <linux/kref.h> #include <linux/mm.h> +#include <linux/namei.h> #include <linux/pagemap.h> #include <linux/rbtree.h> #include <linux/rwsem.h> @@ -69,9 +71,8 @@ struct nfs_access_entry { struct nfs4_state; struct nfs_open_context { - atomic_t count; - struct vfsmount *vfsmnt; - struct dentry *dentry; + struct kref kref; + struct path path; struct rpc_cred *cred; struct nfs4_state *state; fl_owner_t lockowner; @@ -155,13 +156,9 @@ struct nfs_inode { /* * This is the list of dirty unwritten pages. */ - spinlock_t req_lock; - struct list_head dirty; - struct list_head commit; struct radix_tree_root nfs_page_tree; - unsigned int ndirty, - ncommit, + unsigned long ncommit, npages; /* Open contexts for shared mmap writes */ @@ -187,6 +184,7 @@ struct nfs_inode { #define NFS_INO_INVALID_ACCESS 0x0008 /* cached access cred invalid */ #define NFS_INO_INVALID_ACL 0x0010 /* cached acls are invalid */ #define NFS_INO_REVAL_PAGECACHE 0x0020 /* must revalidate pagecache */ +#define NFS_INO_REVAL_FORCED 0x0040 /* force revalidation ignoring a delegation */ /* * Bit offsets in flags field @@ -496,21 +494,18 @@ static inline void nfs3_forget_cached_acls(struct inode *inode) /* * linux/fs/mount_clnt.c - * (Used only by nfsroot module) */ -extern int nfsroot_mount(struct sockaddr_in *, char *, struct nfs_fh *, - int, int); +extern int nfs_mount(struct sockaddr *, size_t, char *, char *, + int, int, struct nfs_fh *); /* * inline functions */ -static inline loff_t -nfs_size_to_loff_t(__u64 size) +static inline loff_t nfs_size_to_loff_t(__u64 size) { - loff_t maxsz = (((loff_t) ULONG_MAX) << PAGE_CACHE_SHIFT) + PAGE_CACHE_SIZE - 1; - if (size > maxsz) - return maxsz; + if (size > (__u64) OFFSET_MAX - 1) + return OFFSET_MAX - 1; return (loff_t) size; } @@ -557,6 +552,7 @@ extern void * nfs_root_data(void); #define NFSDBG_ROOT 0x0080 #define NFSDBG_CALLBACK 0x0100 #define NFSDBG_CLIENT 0x0200 +#define NFSDBG_MOUNT 0x0400 #define NFSDBG_ALL 0xFFFF #ifdef __KERNEL__ diff --git a/include/linux/nfs_fs_sb.h b/include/linux/nfs_fs_sb.h index 52b4378311c..0cac49bc095 100644 --- a/include/linux/nfs_fs_sb.h +++ b/include/linux/nfs_fs_sb.h @@ -16,7 +16,6 @@ struct nfs_client { #define NFS_CS_INITING 1 /* busy initialising */ int cl_nfsversion; /* NFS protocol version */ unsigned long cl_res_state; /* NFS resources state */ -#define NFS_CS_RPCIOD 0 /* - rpciod started */ #define NFS_CS_CALLBACK 1 /* - callback started */ #define NFS_CS_IDMAP 2 /* - idmap started */ #define NFS_CS_RENEWD 3 /* - renewd started */ @@ -35,7 +34,8 @@ struct nfs_client { nfs4_verifier cl_confirm; unsigned long cl_state; - u32 cl_lockowner_id; + struct rb_root cl_openowner_id; + struct rb_root cl_lockowner_id; /* * The following rwsem ensures exclusive access to the server @@ -44,9 +44,7 @@ struct nfs_client { struct rw_semaphore cl_sem; struct list_head cl_delegations; - struct list_head cl_state_owners; - struct list_head cl_unused; - int cl_nunused; + struct rb_root cl_state_owners; spinlock_t cl_lock; unsigned long cl_lease_time; diff --git a/include/linux/nfs_mount.h b/include/linux/nfs_mount.h index cc8b9c59acb..a3ade89a64d 100644 --- a/include/linux/nfs_mount.h +++ b/include/linux/nfs_mount.h @@ -37,7 +37,7 @@ struct nfs_mount_data { int acdirmin; /* 1 */ int acdirmax; /* 1 */ struct sockaddr_in addr; /* 1 */ - char hostname[256]; /* 1 */ + char hostname[NFS_MAXNAMLEN + 1]; /* 1 */ int namlen; /* 2 */ unsigned int bsize; /* 3 */ struct nfs3_fh root; /* 4 */ @@ -62,6 +62,7 @@ struct nfs_mount_data { #define NFS_MOUNT_STRICTLOCK 0x1000 /* reserved for NFSv4 */ #define NFS_MOUNT_SECFLAVOUR 0x2000 /* 5 */ #define NFS_MOUNT_NORDIRPLUS 0x4000 /* 5 */ +#define NFS_MOUNT_UNSHARED 0x8000 /* 5 */ #define NFS_MOUNT_FLAGMASK 0xFFFF #endif diff --git a/include/linux/nfs_page.h b/include/linux/nfs_page.h index bd193af8016..78e60798d10 100644 --- a/include/linux/nfs_page.h +++ b/include/linux/nfs_page.h @@ -16,12 +16,13 @@ #include <linux/sunrpc/auth.h> #include <linux/nfs_xdr.h> -#include <asm/atomic.h> +#include <linux/kref.h> /* * Valid flags for the radix tree */ -#define NFS_PAGE_TAG_WRITEBACK 0 +#define NFS_PAGE_TAG_LOCKED 0 +#define NFS_PAGE_TAG_COMMIT 1 /* * Valid flags for a dirty buffer @@ -33,8 +34,7 @@ struct nfs_inode; struct nfs_page { - struct list_head wb_list, /* Defines state of page: */ - *wb_list_head; /* read/write/commit */ + struct list_head wb_list; /* Defines state of page: */ struct page *wb_page; /* page to read in/write out */ struct nfs_open_context *wb_context; /* File state context info */ atomic_t wb_complete; /* i/os we're waiting for */ @@ -42,7 +42,7 @@ struct nfs_page { unsigned int wb_offset, /* Offset & ~PAGE_CACHE_MASK */ wb_pgbase, /* Start of page data */ wb_bytes; /* Length of request */ - atomic_t wb_count; /* reference count */ + struct kref wb_kref; /* reference count */ unsigned long wb_flags; struct nfs_writeverf wb_verf; /* Commit cookie */ }; @@ -71,8 +71,8 @@ extern void nfs_clear_request(struct nfs_page *req); extern void nfs_release_request(struct nfs_page *req); -extern int nfs_scan_list(struct nfs_inode *nfsi, struct list_head *head, struct list_head *dst, - pgoff_t idx_start, unsigned int npages); +extern int nfs_scan_list(struct nfs_inode *nfsi, struct list_head *dst, + pgoff_t idx_start, unsigned int npages, int tag); extern void nfs_pageio_init(struct nfs_pageio_descriptor *desc, struct inode *inode, int (*doio)(struct inode *, struct list_head *, unsigned int, size_t, int), @@ -84,12 +84,11 @@ extern void nfs_pageio_complete(struct nfs_pageio_descriptor *desc); extern void nfs_pageio_cond_complete(struct nfs_pageio_descriptor *, pgoff_t); extern int nfs_wait_on_request(struct nfs_page *); extern void nfs_unlock_request(struct nfs_page *req); -extern int nfs_set_page_writeback_locked(struct nfs_page *req); -extern void nfs_clear_page_writeback(struct nfs_page *req); +extern void nfs_clear_page_tag_locked(struct nfs_page *req); /* - * Lock the page of an asynchronous request without incrementing the wb_count + * Lock the page of an asynchronous request without getting a new reference */ static inline int nfs_lock_request_dontget(struct nfs_page *req) @@ -98,14 +97,14 @@ nfs_lock_request_dontget(struct nfs_page *req) } /* - * Lock the page of an asynchronous request + * Lock the page of an asynchronous request and take a reference */ static inline int nfs_lock_request(struct nfs_page *req) { if (test_and_set_bit(PG_BUSY, &req->wb_flags)) return 0; - atomic_inc(&req->wb_count); + kref_get(&req->wb_kref); return 1; } @@ -118,7 +117,6 @@ static inline void nfs_list_add_request(struct nfs_page *req, struct list_head *head) { list_add_tail(&req->wb_list, head); - req->wb_list_head = head; } @@ -132,7 +130,6 @@ nfs_list_remove_request(struct nfs_page *req) if (list_empty(&req->wb_list)) return; list_del_init(&req->wb_list); - req->wb_list_head = NULL; } static inline struct nfs_page * diff --git a/include/linux/nfs_xdr.h b/include/linux/nfs_xdr.h index 10c26ed0db7..38d77681cf2 100644 --- a/include/linux/nfs_xdr.h +++ b/include/linux/nfs_xdr.h @@ -119,7 +119,7 @@ struct nfs_openargs { struct nfs_seqid * seqid; int open_flags; __u64 clientid; - __u32 id; + __u64 id; union { struct iattr * attrs; /* UNCHECKED, GUARDED */ nfs4_verifier verifier; /* EXCLUSIVE */ @@ -144,6 +144,7 @@ struct nfs_openres { nfs4_stateid delegation; __u32 do_recall; __u64 maxsize; + __u32 attrset[NFS4_BITMAP_SIZE]; }; /* @@ -180,7 +181,7 @@ struct nfs_closeres { * */ struct nfs_lowner { __u64 clientid; - u32 id; + __u64 id; }; struct nfs_lock_args { diff --git a/include/linux/pata_platform.h b/include/linux/pata_platform.h index 2d5fd647e0e..5799e8d5062 100644 --- a/include/linux/pata_platform.h +++ b/include/linux/pata_platform.h @@ -8,6 +8,11 @@ struct pata_platform_info { * spacing used by ata_std_ports(). */ unsigned int ioport_shift; + /* + * Indicate platform specific irq types and initial + * IRQ flags when call request_irq() + */ + unsigned int irq_flags; }; #endif /* __LINUX_PATA_PLATFORM_H */ diff --git a/include/linux/pci.h b/include/linux/pci.h index fbf3766dac1..37a71580ad8 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -111,7 +111,8 @@ enum pcie_reset_state { typedef unsigned short __bitwise pci_bus_flags_t; enum pci_bus_flags { - PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, + PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, + PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, }; struct pci_cap_saved_state { @@ -138,6 +139,7 @@ struct pci_dev { unsigned short subsystem_vendor; unsigned short subsystem_device; unsigned int class; /* 3 bytes: (base,sub,prog-if) */ + u8 revision; /* PCI revision, low byte of class word */ u8 hdr_type; /* PCI header type (`multi' flag masked out) */ u8 rom_base_reg; /* which config register controls the ROM */ u8 pin; /* which interrupt pin this device uses */ @@ -313,7 +315,7 @@ struct pci_dynids { /* ---------------------------------------------------------------- */ /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides - * a set fof callbacks in struct pci_error_handlers, then that device driver + * a set of callbacks in struct pci_error_handlers, then that device driver * will be notified of PCI bus errors, and will be driven to recovery * when an error occurs. */ @@ -370,7 +372,6 @@ struct pci_driver { int (*suspend_late) (struct pci_dev *dev, pm_message_t state); int (*resume_early) (struct pci_dev *dev); int (*resume) (struct pci_dev *dev); /* Device woken up */ - int (*enable_wake) (struct pci_dev *dev, pci_power_t state, int enable); /* Enable wake event */ void (*shutdown) (struct pci_dev *dev); struct pci_error_handlers *err_handler; @@ -475,7 +476,7 @@ extern void pci_sort_breadthfirst(void); /* Generic PCI functions exported to card drivers */ struct pci_dev __deprecated *pci_find_device (unsigned int vendor, unsigned int device, const struct pci_dev *from); -struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn); +struct pci_dev __deprecated *pci_find_slot (unsigned int bus, unsigned int devfn); int pci_find_capability (struct pci_dev *dev, int cap); int pci_find_next_capability (struct pci_dev *dev, u8 pos, int cap); int pci_find_ext_capability (struct pci_dev *dev, int cap); @@ -544,11 +545,16 @@ void pci_set_master(struct pci_dev *dev); int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); #define HAVE_PCI_SET_MWI int __must_check pci_set_mwi(struct pci_dev *dev); +int pci_try_set_mwi(struct pci_dev *dev); void pci_clear_mwi(struct pci_dev *dev); void pci_intx(struct pci_dev *dev, int enable); void pci_msi_off(struct pci_dev *dev); int pci_set_dma_mask(struct pci_dev *dev, u64 mask); int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask); +int pcix_get_max_mmrbc(struct pci_dev *dev); +int pcix_get_mmrbc(struct pci_dev *dev); +int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); +int pcie_set_readrq(struct pci_dev *dev, int rq); void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno); int __must_check pci_assign_resource(struct pci_dev *dev, int i); int __must_check pci_assign_resource_fixed(struct pci_dev *dev, int i); @@ -560,6 +566,7 @@ void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); void __iomem __must_check *pci_map_rom_copy(struct pci_dev *pdev, size_t *size); void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); void pci_remove_rom(struct pci_dev *pdev); +size_t pci_get_rom_size(void __iomem *rom, size_t size); /* Power management related routines */ int pci_save_state(struct pci_dev *dev); @@ -748,6 +755,17 @@ static inline void pci_release_regions(struct pci_dev *dev) { } static inline void pci_block_user_cfg_access(struct pci_dev *dev) { } static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) { } +static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) +{ return NULL; } + +static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, + unsigned int devfn) +{ return NULL; } + +static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, + unsigned int devfn) +{ return NULL; } + #endif /* CONFIG_PCI */ /* Include architecture-dependent settings and functions */ @@ -865,5 +883,7 @@ extern int pci_pci_problems; extern unsigned long pci_cardbus_io_size; extern unsigned long pci_cardbus_mem_size; +extern int pcibios_add_platform_entries(struct pci_dev *dev); + #endif /* __KERNEL__ */ #endif /* LINUX_PCI_H */ diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 4712e269d8d..2c7add16953 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -133,6 +133,9 @@ /* Vendors and devices. Sort key: vendor first, device next. */ +#define PCI_VENDOR_ID_TTTECH 0x0357 +#define PCI_DEVICE_ID_TTTECH_MC322 0x000a + #define PCI_VENDOR_ID_DYNALINK 0x0675 #define PCI_DEVICE_ID_DYNALINK_IS64PH 0x1702 @@ -371,6 +374,7 @@ #define PCI_DEVICE_ID_ATI_IXP600_SMBUS 0x4385 #define PCI_DEVICE_ID_ATI_IXP600_IDE 0x438c #define PCI_DEVICE_ID_ATI_IXP700_SATA 0x4390 +#define PCI_DEVICE_ID_ATI_IXP700_SMBUS 0x4395 #define PCI_DEVICE_ID_ATI_IXP700_IDE 0x439c #define PCI_VENDOR_ID_VLSI 0x1004 @@ -475,6 +479,9 @@ #define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM_PCIE 0x0361 #define PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL 0x252 +#define PCI_VENDOR_ID_UNISYS 0x1018 +#define PCI_DEVICE_ID_UNISYS_DMA_DIRECTOR 0x001C + #define PCI_VENDOR_ID_COMPEX2 0x101a /* pci.ids says "AT&T GIS (NCR)" */ #define PCI_DEVICE_ID_COMPEX2_100VG 0x0005 @@ -661,6 +668,7 @@ #define PCI_DEVICE_ID_SI_965 0x0965 #define PCI_DEVICE_ID_SI_966 0x0966 #define PCI_DEVICE_ID_SI_968 0x0968 +#define PCI_DEVICE_ID_SI_1180 0x1180 #define PCI_DEVICE_ID_SI_5511 0x5511 #define PCI_DEVICE_ID_SI_5513 0x5513 #define PCI_DEVICE_ID_SI_5517 0x5517 @@ -731,7 +739,6 @@ #define PCI_DEVICE_ID_ELSA_MICROLINK 0x1000 #define PCI_DEVICE_ID_ELSA_QS3000 0x3000 - #define PCI_VENDOR_ID_BUSLOGIC 0x104B #define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140 #define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER 0x1040 @@ -777,7 +784,6 @@ #define PCI_VENDOR_ID_SONY 0x104d - /* Winbond have two vendor IDs! See 0x10ad as well */ #define PCI_VENDOR_ID_WINBOND2 0x1050 #define PCI_DEVICE_ID_WINBOND2_89C940F 0x5a5a @@ -815,7 +821,6 @@ #define PCI_DEVICE_ID_PROMISE_20276 0x5275 #define PCI_DEVICE_ID_PROMISE_20277 0x7275 - #define PCI_VENDOR_ID_UMC 0x1060 #define PCI_DEVICE_ID_UMC_UM8673F 0x0101 #define PCI_DEVICE_ID_UMC_UM8886BF 0x673a @@ -831,7 +836,6 @@ #define PCI_DEVICE_ID_MYLEX_DAC960_BA 0xBA56 #define PCI_DEVICE_ID_MYLEX_DAC960_GEM 0xB166 - #define PCI_VENDOR_ID_APPLE 0x106b #define PCI_DEVICE_ID_APPLE_BANDIT 0x0001 #define PCI_DEVICE_ID_APPLE_HYDRA 0x000e @@ -867,7 +871,6 @@ #define PCI_DEVICE_ID_YAMAHA_744 0x0010 #define PCI_DEVICE_ID_YAMAHA_754 0x0012 - #define PCI_VENDOR_ID_QLOGIC 0x1077 #define PCI_DEVICE_ID_QLOGIC_ISP10160 0x1016 #define PCI_DEVICE_ID_QLOGIC_ISP1020 0x1020 @@ -898,12 +901,9 @@ #define PCI_DEVICE_ID_CYRIX_5530_AUDIO 0x0103 #define PCI_DEVICE_ID_CYRIX_5530_VIDEO 0x0104 - - #define PCI_VENDOR_ID_CONTAQ 0x1080 #define PCI_DEVICE_ID_CONTAQ_82C693 0xc693 - #define PCI_VENDOR_ID_OLICOM 0x108d #define PCI_DEVICE_ID_OLICOM_OC2325 0x0012 #define PCI_DEVICE_ID_OLICOM_OC2183 0x0013 @@ -935,23 +935,19 @@ #define PCI_DEVICE_ID_SII_3112 0x3112 #define PCI_DEVICE_ID_SII_1210SA 0x0240 - #define PCI_VENDOR_ID_BROOKTREE 0x109e #define PCI_DEVICE_ID_BROOKTREE_878 0x0878 #define PCI_DEVICE_ID_BROOKTREE_879 0x0879 - #define PCI_VENDOR_ID_SGI 0x10a9 #define PCI_DEVICE_ID_SGI_IOC3 0x0003 +#define PCI_DEVICE_ID_SGI_LITHIUM 0x1002 #define PCI_DEVICE_ID_SGI_IOC4 0x100a -#define PCI_VENDOR_ID_SGI_LITHIUM 0x1002 - #define PCI_VENDOR_ID_WINBOND 0x10ad #define PCI_DEVICE_ID_WINBOND_82C105 0x0105 #define PCI_DEVICE_ID_WINBOND_83C553 0x0565 - #define PCI_VENDOR_ID_PLX 0x10b5 #define PCI_DEVICE_ID_PLX_R685 0x1030 #define PCI_DEVICE_ID_PLX_ROMULUS 0x106a @@ -985,7 +981,6 @@ #define PCI_DEVICE_ID_3COM_3CR990SVR97 0x9909 #define PCI_DEVICE_ID_3COM_3CR990SVR 0x990a - #define PCI_VENDOR_ID_AL 0x10b9 #define PCI_DEVICE_ID_AL_M1533 0x1533 #define PCI_DEVICE_ID_AL_M1535 0x1535 @@ -1008,18 +1003,14 @@ #define PCI_DEVICE_ID_AL_M5451 0x5451 #define PCI_DEVICE_ID_AL_M7101 0x7101 - - #define PCI_VENDOR_ID_NEOMAGIC 0x10c8 #define PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO 0x8005 #define PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO 0x8006 #define PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO 0x8016 - #define PCI_VENDOR_ID_TCONRAD 0x10da #define PCI_DEVICE_ID_TCONRAD_TOKENRING 0x0508 - #define PCI_VENDOR_ID_NVIDIA 0x10de #define PCI_DEVICE_ID_NVIDIA_TNT 0x0020 #define PCI_DEVICE_ID_NVIDIA_TNT2 0x0028 @@ -1233,14 +1224,13 @@ #define PCI_DEVICE_ID_NVIDIA_NVENET_26 0x054E #define PCI_DEVICE_ID_NVIDIA_NVENET_27 0x054F #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE 0x0560 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE 0x056C +#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE 0x0759 #define PCI_VENDOR_ID_IMS 0x10e0 #define PCI_DEVICE_ID_IMS_TT128 0x9128 #define PCI_DEVICE_ID_IMS_TT3D 0x9135 - - - #define PCI_VENDOR_ID_INTERG 0x10ea #define PCI_DEVICE_ID_INTERG_1682 0x1682 #define PCI_DEVICE_ID_INTERG_2000 0x2000 @@ -1259,7 +1249,6 @@ #define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5 #define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI 0x3fc6 - #define PCI_VENDOR_ID_INIT 0x1101 #define PCI_VENDOR_ID_CREATIVE 0x1102 /* duplicate: ECTIVA */ @@ -1292,6 +1281,7 @@ #define PCI_DEVICE_ID_VIA_P4M890 0x0327 #define PCI_DEVICE_ID_VIA_VT3324 0x0324 #define PCI_DEVICE_ID_VIA_VT3336 0x0336 +#define PCI_DEVICE_ID_VIA_VT3351 0x0351 #define PCI_DEVICE_ID_VIA_8371_0 0x0391 #define PCI_DEVICE_ID_VIA_8501_0 0x0501 #define PCI_DEVICE_ID_VIA_82C561 0x0561 @@ -1353,7 +1343,6 @@ #define PCI_VENDOR_ID_SIEMENS 0x110A #define PCI_DEVICE_ID_SIEMENS_DSCC4 0x2102 - #define PCI_VENDOR_ID_VORTEX 0x1119 #define PCI_DEVICE_ID_VORTEX_GDT60x0 0x0000 #define PCI_DEVICE_ID_VORTEX_GDT6000B 0x0001 @@ -1379,8 +1368,8 @@ #define PCI_VENDOR_ID_EF 0x111a #define PCI_DEVICE_ID_EF_ATM_FPGA 0x0000 #define PCI_DEVICE_ID_EF_ATM_ASIC 0x0002 -#define PCI_VENDOR_ID_EF_ATM_LANAI2 0x0003 -#define PCI_VENDOR_ID_EF_ATM_LANAIHB 0x0005 +#define PCI_DEVICE_ID_EF_ATM_LANAI2 0x0003 +#define PCI_DEVICE_ID_EF_ATM_LANAIHB 0x0005 #define PCI_VENDOR_ID_IDT 0x111d #define PCI_DEVICE_ID_IDT_IDT77201 0x0001 @@ -1388,7 +1377,6 @@ #define PCI_VENDOR_ID_FORE 0x1127 #define PCI_DEVICE_ID_FORE_PCA200E 0x0300 - #define PCI_VENDOR_ID_PHILIPS 0x1131 #define PCI_DEVICE_ID_PHILIPS_SAA7146 0x7146 #define PCI_DEVICE_ID_PHILIPS_SAA9730 0x9730 @@ -1407,7 +1395,6 @@ #define PCI_DEVICE_ID_ZIATECH_5550_HC 0x5550 - #define PCI_VENDOR_ID_SYSKONNECT 0x1148 #define PCI_DEVICE_ID_SYSKONNECT_TR 0x4200 #define PCI_DEVICE_ID_SYSKONNECT_GE 0x4300 @@ -1415,7 +1402,6 @@ #define PCI_DEVICE_ID_SYSKONNECT_9DXX 0x4400 #define PCI_DEVICE_ID_SYSKONNECT_9MXX 0x4500 - #define PCI_VENDOR_ID_DIGI 0x114f #define PCI_DEVICE_ID_DIGI_DF_M_IOM2_E 0x0070 #define PCI_DEVICE_ID_DIGI_DF_M_E 0x0071 @@ -1426,17 +1412,16 @@ #define PCI_DEVICE_ID_NEO_2RJ45 0x00CA #define PCI_DEVICE_ID_NEO_2RJ45PRI 0x00CB - #define PCI_VENDOR_ID_XIRCOM 0x115d #define PCI_DEVICE_ID_XIRCOM_RBM56G 0x0101 #define PCI_DEVICE_ID_XIRCOM_X3201_MDM 0x0103 - #define PCI_VENDOR_ID_SERVERWORKS 0x1166 #define PCI_DEVICE_ID_SERVERWORKS_HE 0x0008 #define PCI_DEVICE_ID_SERVERWORKS_LE 0x0009 #define PCI_DEVICE_ID_SERVERWORKS_GCNB_LE 0x0017 #define PCI_DEVICE_ID_SERVERWORKS_EPB 0x0103 +#define PCI_DEVICE_ID_SERVERWORKS_HT1000_PCIX 0x0104 #define PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE 0x0132 #define PCI_DEVICE_ID_SERVERWORKS_OSB4 0x0200 #define PCI_DEVICE_ID_SERVERWORKS_CSB5 0x0201 @@ -1499,7 +1484,6 @@ #define PCI_DEVICE_ID_ZEITNET_1221 0x0001 #define PCI_DEVICE_ID_ZEITNET_1225 0x0002 - #define PCI_VENDOR_ID_FUJITSU_ME 0x119e #define PCI_DEVICE_ID_FUJITSU_FS155 0x0001 #define PCI_DEVICE_ID_FUJITSU_FS50 0x0003 @@ -1517,28 +1501,23 @@ #define PCI_DEVICE_ID_V3_V960 0x0001 #define PCI_DEVICE_ID_V3_V351 0x0002 - #define PCI_VENDOR_ID_ATT 0x11c1 #define PCI_DEVICE_ID_ATT_VENUS_MODEM 0x480 - #define PCI_VENDOR_ID_SPECIALIX 0x11cb #define PCI_DEVICE_ID_SPECIALIX_IO8 0x2000 #define PCI_DEVICE_ID_SPECIALIX_RIO 0x8000 #define PCI_SUBDEVICE_ID_SPECIALIX_SPEED4 0xa004 - #define PCI_VENDOR_ID_ANALOG_DEVICES 0x11d4 #define PCI_DEVICE_ID_AD1889JS 0x1889 - #define PCI_DEVICE_ID_SEGA_BBA 0x1234 #define PCI_VENDOR_ID_ZORAN 0x11de #define PCI_DEVICE_ID_ZORAN_36057 0x6057 #define PCI_DEVICE_ID_ZORAN_36120 0x6120 - #define PCI_VENDOR_ID_COMPEX 0x11f6 #define PCI_DEVICE_ID_COMPEX_ENET100VG4 0x0112 @@ -1597,8 +1576,6 @@ #define PCI_DEVICE_ID_3DFX_VOODOO3 0x0005 #define PCI_DEVICE_ID_3DFX_VOODOO5 0x0009 - - #define PCI_VENDOR_ID_AVM 0x1244 #define PCI_DEVICE_ID_AVM_B1 0x0700 #define PCI_DEVICE_ID_AVM_C4 0x0800 @@ -1607,7 +1584,6 @@ #define PCI_DEVICE_ID_AVM_C2 0x1100 #define PCI_DEVICE_ID_AVM_T1 0x1200 - #define PCI_VENDOR_ID_STALLION 0x124d /* Allied Telesyn */ @@ -1630,7 +1606,6 @@ #define PCI_VENDOR_ID_SATSAGEM 0x1267 #define PCI_DEVICE_ID_SATSAGEM_NICCY 0x1016 - #define PCI_VENDOR_ID_ENSONIQ 0x1274 #define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880 #define PCI_DEVICE_ID_ENSONIQ_ES1370 0x5000 @@ -1653,7 +1628,6 @@ #define PCI_VENDOR_ID_ALTEON 0x12ae - #define PCI_SUBVENDOR_ID_CONNECT_TECH 0x12c4 #define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232 0x0001 #define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232 0x0002 @@ -1684,7 +1658,6 @@ #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485 0x0331 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485 0x0332 - #define PCI_VENDOR_ID_NVIDIA_SGS 0x12d2 #define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018 @@ -1794,7 +1767,6 @@ #define PCI_DEVICE_ID_LMC_SSI 0x0005 #define PCI_DEVICE_ID_LMC_T1 0x0006 - #define PCI_VENDOR_ID_NETGEAR 0x1385 #define PCI_DEVICE_ID_NETGEAR_GA620 0x620a @@ -1897,6 +1869,8 @@ #define PCI_DEVICE_ID_OXSEMI_16PCI952 0x9521 #define PCI_DEVICE_ID_OXSEMI_16PCI952PP 0x9523 +#define PCI_VENDOR_ID_CHELSIO 0x1425 + #define PCI_VENDOR_ID_SAMSUNG 0x144d #define PCI_VENDOR_ID_MYRICOM 0x14c1 @@ -1995,6 +1969,7 @@ #define PCI_VENDOR_ID_ENE 0x1524 #define PCI_DEVICE_ID_ENE_CB712_SD 0x0550 +#define PCI_DEVICE_ID_ENE_CB712_SD_2 0x0551 #define PCI_DEVICE_ID_ENE_1211 0x1211 #define PCI_DEVICE_ID_ENE_1225 0x1225 #define PCI_DEVICE_ID_ENE_1410 0x1410 @@ -2004,13 +1979,10 @@ #define PCI_DEVICE_ID_ENE_720 0x1421 #define PCI_DEVICE_ID_ENE_722 0x1422 -#define PCI_VENDOR_ID_CHELSIO 0x1425 - #define PCI_SUBVENDOR_ID_PERLE 0x155f #define PCI_SUBDEVICE_ID_PCI_RAS4 0xf001 #define PCI_SUBDEVICE_ID_PCI_RAS8 0xf010 - #define PCI_VENDOR_ID_SYBA 0x1592 #define PCI_DEVICE_ID_SYBA_2P_EPP 0x0782 #define PCI_DEVICE_ID_SYBA_1P_ECP 0x0783 @@ -2029,8 +2001,10 @@ #define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c #define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 -#define PCI_VENDOR_ID_PDC 0x15e9 +#define PCI_VENDOR_ID_QUICKNET 0x15e2 +#define PCI_DEVICE_ID_QUICKNET_XJ 0x0500 +#define PCI_VENDOR_ID_PDC 0x15e9 #define PCI_VENDOR_ID_FARSITE 0x1619 #define PCI_DEVICE_ID_FARSITE_T2P 0x0400 @@ -2047,6 +2021,8 @@ #define PCI_DEVICE_ID_BCM1250_PCI 0x0001 #define PCI_DEVICE_ID_BCM1250_HT 0x0002 +#define PCI_VENDOR_ID_ATHEROS 0x168c + #define PCI_VENDOR_ID_NETCELL 0x169c #define PCI_DEVICE_ID_REVOLUTION 0x0044 @@ -2085,7 +2061,6 @@ #define PCI_DEVICE_ID_HERC_WIN 0x5732 #define PCI_DEVICE_ID_HERC_UNI 0x5832 - #define PCI_VENDOR_ID_SITECOM 0x182d #define PCI_DEVICE_ID_SITECOM_DC105V2 0x3069 @@ -2121,12 +2096,9 @@ #define PCI_DEVICE_ID_3DLABS_PERMEDIA2 0x0007 #define PCI_DEVICE_ID_3DLABS_PERMEDIA2V 0x0009 - #define PCI_VENDOR_ID_AKS 0x416c #define PCI_DEVICE_ID_AKS_ALADDINCARD 0x0100 - - #define PCI_VENDOR_ID_S3 0x5333 #define PCI_DEVICE_ID_S3_TRIO 0x8811 #define PCI_DEVICE_ID_S3_868 0x8880 @@ -2138,7 +2110,6 @@ #define PCI_VENDOR_ID_DUNORD 0x5544 #define PCI_DEVICE_ID_DUNORD_I3000 0x0001 - #define PCI_VENDOR_ID_DCI 0x6666 #define PCI_DEVICE_ID_DCI_PCCOM4 0x0001 #define PCI_DEVICE_ID_DCI_PCCOM8 0x0002 @@ -2267,11 +2238,11 @@ #define PCI_DEVICE_ID_INTEL_ICH8_5 0x283e #define PCI_DEVICE_ID_INTEL_ICH8_6 0x2850 #define PCI_DEVICE_ID_INTEL_ICH9_0 0x2910 -#define PCI_DEVICE_ID_INTEL_ICH9_1 0x2911 +#define PCI_DEVICE_ID_INTEL_ICH9_1 0x2917 #define PCI_DEVICE_ID_INTEL_ICH9_2 0x2912 #define PCI_DEVICE_ID_INTEL_ICH9_3 0x2913 #define PCI_DEVICE_ID_INTEL_ICH9_4 0x2914 -#define PCI_DEVICE_ID_INTEL_ICH9_5 0x2915 +#define PCI_DEVICE_ID_INTEL_ICH9_5 0x2919 #define PCI_DEVICE_ID_INTEL_ICH9_6 0x2930 #define PCI_DEVICE_ID_INTEL_82855PM_HB 0x3340 #define PCI_DEVICE_ID_INTEL_82830_HB 0x3575 @@ -2382,7 +2353,6 @@ #define PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN 0x0500 #define PCI_DEVICE_ID_ADAPTEC2_SCAMP 0x0503 - #define PCI_VENDOR_ID_HOLTEK 0x9412 #define PCI_DEVICE_ID_HOLTEK_6565 0x6565 @@ -2398,6 +2368,8 @@ #define PCI_DEVICE_ID_NETMOS_9845 0x9845 #define PCI_DEVICE_ID_NETMOS_9855 0x9855 +#define PCI_VENDOR_ID_3COM_2 0xa727 + #define PCI_SUBVENDOR_ID_EXSYS 0xd84d #define PCI_SUBDEVICE_ID_EXSYS_4014 0x4014 #define PCI_SUBDEVICE_ID_EXSYS_4055 0x4055 @@ -2406,13 +2378,7 @@ #define PCI_DEVICE_ID_TIGERJET_300 0x0001 #define PCI_DEVICE_ID_TIGERJET_100 0x0002 -#define PCI_VENDOR_ID_TTTECH 0x0357 -#define PCI_DEVICE_ID_TTTECH_MC322 0x000A - #define PCI_VENDOR_ID_XILINX_RME 0xea60 #define PCI_DEVICE_ID_RME_DIGI32 0x9896 #define PCI_DEVICE_ID_RME_DIGI32_PRO 0x9897 #define PCI_DEVICE_ID_RME_DIGI32_8 0x9898 - -#define PCI_VENDOR_ID_QUICKNET 0x15E2 -#define PCI_DEVICE_ID_QUICKNET_XJ 0x0500 diff --git a/include/linux/pda_power.h b/include/linux/pda_power.h new file mode 100644 index 00000000000..1375f15797e --- /dev/null +++ b/include/linux/pda_power.h @@ -0,0 +1,31 @@ +/* + * Common power driver for PDAs and phones with one or two external + * power supplies (AC/USB) connected to main and backup batteries, + * and optional builtin charger. + * + * Copyright © 2007 Anton Vorontsov <cbou@mail.ru> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __PDA_POWER_H__ +#define __PDA_POWER_H__ + +#define PDA_POWER_CHARGE_AC (1 << 0) +#define PDA_POWER_CHARGE_USB (1 << 1) + +struct pda_power_pdata { + int (*is_ac_online)(void); + int (*is_usb_online)(void); + void (*set_charge)(int flags); + + char **supplied_to; + size_t num_supplicants; + + unsigned int wait_for_status; /* msecs, default is 500 */ + unsigned int wait_for_charger; /* msecs, default is 500 */ +}; + +#endif /* __PDA_POWER_H__ */ diff --git a/include/linux/pipe_fs_i.h b/include/linux/pipe_fs_i.h index 8bcbc54e1b4..8e4120285f7 100644 --- a/include/linux/pipe_fs_i.h +++ b/include/linux/pipe_fs_i.h @@ -9,48 +9,125 @@ #define PIPE_BUF_FLAG_ATOMIC 0x02 /* was atomically mapped */ #define PIPE_BUF_FLAG_GIFT 0x04 /* page is a gift */ +/** + * struct pipe_buffer - a linux kernel pipe buffer + * @page: the page containing the data for the pipe buffer + * @offset: offset of data inside the @page + * @len: length of data inside the @page + * @ops: operations associated with this buffer. See @pipe_buf_operations. + * @flags: pipe buffer flags. See above. + * @private: private data owned by the ops. + **/ struct pipe_buffer { struct page *page; unsigned int offset, len; const struct pipe_buf_operations *ops; unsigned int flags; + unsigned long private; +}; + +/** + * struct pipe_inode_info - a linux kernel pipe + * @wait: reader/writer wait point in case of empty/full pipe + * @nrbufs: the number of non-empty pipe buffers in this pipe + * @curbuf: the current pipe buffer entry + * @tmp_page: cached released page + * @readers: number of current readers of this pipe + * @writers: number of current writers of this pipe + * @waiting_writers: number of writers blocked waiting for room + * @r_counter: reader counter + * @w_counter: writer counter + * @fasync_readers: reader side fasync + * @fasync_writers: writer side fasync + * @inode: inode this pipe is attached to + * @bufs: the circular array of pipe buffers + **/ +struct pipe_inode_info { + wait_queue_head_t wait; + unsigned int nrbufs, curbuf; + struct page *tmp_page; + unsigned int readers; + unsigned int writers; + unsigned int waiting_writers; + unsigned int r_counter; + unsigned int w_counter; + struct fasync_struct *fasync_readers; + struct fasync_struct *fasync_writers; + struct inode *inode; + struct pipe_buffer bufs[PIPE_BUFFERS]; }; /* * Note on the nesting of these functions: * - * ->pin() + * ->confirm() * ->steal() * ... * ->map() * ... * ->unmap() * - * That is, ->map() must be called on a pinned buffer, same goes for ->steal(). + * That is, ->map() must be called on a confirmed buffer, + * same goes for ->steal(). See below for the meaning of each + * operation. Also see kerneldoc in fs/pipe.c for the pipe + * and generic variants of these hooks. */ struct pipe_buf_operations { + /* + * This is set to 1, if the generic pipe read/write may coalesce + * data into an existing buffer. If this is set to 0, a new pipe + * page segment is always used for new data. + */ int can_merge; + + /* + * ->map() returns a virtual address mapping of the pipe buffer. + * The last integer flag reflects whether this should be an atomic + * mapping or not. The atomic map is faster, however you can't take + * page faults before calling ->unmap() again. So if you need to eg + * access user data through copy_to/from_user(), then you must get + * a non-atomic map. ->map() uses the KM_USER0 atomic slot for + * atomic maps, so you can't map more than one pipe_buffer at once + * and you have to be careful if mapping another page as source + * or destination for a copy (IOW, it has to use something else + * than KM_USER0). + */ void * (*map)(struct pipe_inode_info *, struct pipe_buffer *, int); + + /* + * Undoes ->map(), finishes the virtual mapping of the pipe buffer. + */ void (*unmap)(struct pipe_inode_info *, struct pipe_buffer *, void *); - int (*pin)(struct pipe_inode_info *, struct pipe_buffer *); + + /* + * ->confirm() verifies that the data in the pipe buffer is there + * and that the contents are good. If the pages in the pipe belong + * to a file system, we may need to wait for IO completion in this + * hook. Returns 0 for good, or a negative error value in case of + * error. + */ + int (*confirm)(struct pipe_inode_info *, struct pipe_buffer *); + + /* + * When the contents of this pipe buffer has been completely + * consumed by a reader, ->release() is called. + */ void (*release)(struct pipe_inode_info *, struct pipe_buffer *); + + /* + * Attempt to take ownership of the pipe buffer and its contents. + * ->steal() returns 0 for success, in which case the contents + * of the pipe (the buf->page) is locked and now completely owned + * by the caller. The page may then be transferred to a different + * mapping, the most often used case is insertion into different + * file address space cache. + */ int (*steal)(struct pipe_inode_info *, struct pipe_buffer *); - void (*get)(struct pipe_inode_info *, struct pipe_buffer *); -}; -struct pipe_inode_info { - wait_queue_head_t wait; - unsigned int nrbufs, curbuf; - struct page *tmp_page; - unsigned int readers; - unsigned int writers; - unsigned int waiting_writers; - unsigned int r_counter; - unsigned int w_counter; - struct fasync_struct *fasync_readers; - struct fasync_struct *fasync_writers; - struct inode *inode; - struct pipe_buffer bufs[PIPE_BUFFERS]; + /* + * Get a reference to the pipe buffer. + */ + void (*get)(struct pipe_inode_info *, struct pipe_buffer *); }; /* Differs from PIPE_BUF in that PIPE_SIZE is the length of the actual @@ -68,39 +145,7 @@ void __free_pipe_info(struct pipe_inode_info *); void *generic_pipe_buf_map(struct pipe_inode_info *, struct pipe_buffer *, int); void generic_pipe_buf_unmap(struct pipe_inode_info *, struct pipe_buffer *, void *); void generic_pipe_buf_get(struct pipe_inode_info *, struct pipe_buffer *); -int generic_pipe_buf_pin(struct pipe_inode_info *, struct pipe_buffer *); +int generic_pipe_buf_confirm(struct pipe_inode_info *, struct pipe_buffer *); int generic_pipe_buf_steal(struct pipe_inode_info *, struct pipe_buffer *); -/* - * splice is tied to pipes as a transport (at least for now), so we'll just - * add the splice flags here. - */ -#define SPLICE_F_MOVE (0x01) /* move pages instead of copying */ -#define SPLICE_F_NONBLOCK (0x02) /* don't block on the pipe splicing (but */ - /* we may still block on the fd we splice */ - /* from/to, of course */ -#define SPLICE_F_MORE (0x04) /* expect more data */ -#define SPLICE_F_GIFT (0x08) /* pages passed in are a gift */ - -/* - * Passed to the actors - */ -struct splice_desc { - unsigned int len, total_len; /* current and remaining length */ - unsigned int flags; /* splice flags */ - struct file *file; /* file to read/write */ - loff_t pos; /* file position */ -}; - -typedef int (splice_actor)(struct pipe_inode_info *, struct pipe_buffer *, - struct splice_desc *); - -extern ssize_t splice_from_pipe(struct pipe_inode_info *, struct file *, - loff_t *, size_t, unsigned int, - splice_actor *); - -extern ssize_t __splice_from_pipe(struct pipe_inode_info *, struct file *, - loff_t *, size_t, unsigned int, - splice_actor *); - #endif diff --git a/include/linux/pkt_cls.h b/include/linux/pkt_cls.h index c3f01b3085a..30b8571e6b3 100644 --- a/include/linux/pkt_cls.h +++ b/include/linux/pkt_cls.h @@ -403,16 +403,13 @@ enum * 1..32767 Reserved for ematches inside kernel tree * 32768..65535 Free to use, not reliable */ -enum -{ - TCF_EM_CONTAINER, - TCF_EM_CMP, - TCF_EM_NBYTE, - TCF_EM_U32, - TCF_EM_META, - TCF_EM_TEXT, - __TCF_EM_MAX -}; +#define TCF_EM_CONTAINER 0 +#define TCF_EM_CMP 1 +#define TCF_EM_NBYTE 2 +#define TCF_EM_U32 3 +#define TCF_EM_META 4 +#define TCF_EM_TEXT 5 +#define TCF_EM_MAX 5 enum { diff --git a/include/linux/pkt_sched.h b/include/linux/pkt_sched.h index d10f3533850..268c51599eb 100644 --- a/include/linux/pkt_sched.h +++ b/include/linux/pkt_sched.h @@ -101,6 +101,15 @@ struct tc_prio_qopt __u8 priomap[TC_PRIO_MAX+1]; /* Map: logical priority -> PRIO band */ }; +enum +{ + TCA_PRIO_UNSPEC, + TCA_PRIO_MQ, + __TCA_PRIO_MAX +}; + +#define TCA_PRIO_MAX (__TCA_PRIO_MAX - 1) + /* TBF section */ struct tc_tbf_qopt diff --git a/include/linux/pm.h b/include/linux/pm.h index 87545e0f0b5..273781c82e4 100644 --- a/include/linux/pm.h +++ b/include/linux/pm.h @@ -110,37 +110,67 @@ typedef int __bitwise suspend_state_t; #define PM_SUSPEND_MAX ((__force suspend_state_t) 4) /** - * struct pm_ops - Callbacks for managing platform dependent suspend states. - * @valid: Callback to determine whether the given state can be entered. - * Valid states are advertised in /sys/power/state but can still - * be rejected by prepare or enter if the conditions aren't right. - * There is a %pm_valid_only_mem function available that can be assigned - * to this if you only implement mem sleep. + * struct pm_ops - Callbacks for managing platform dependent system sleep + * states. * - * @prepare: Prepare the platform for the given suspend state. Can return a - * negative error code if necessary. + * @valid: Callback to determine if given system sleep state is supported by + * the platform. + * Valid (ie. supported) states are advertised in /sys/power/state. Note + * that it still may be impossible to enter given system sleep state if the + * conditions aren't right. + * There is the %pm_valid_only_mem function available that can be assigned + * to this if the platform only supports mem sleep. * - * @enter: Enter the given suspend state, must be assigned. Can return a - * negative error code if necessary. + * @set_target: Tell the platform which system sleep state is going to be + * entered. + * @set_target() is executed right prior to suspending devices. The + * information conveyed to the platform code by @set_target() should be + * disregarded by the platform as soon as @finish() is executed and if + * @prepare() fails. If @set_target() fails (ie. returns nonzero), + * @prepare(), @enter() and @finish() will not be called by the PM core. + * This callback is optional. However, if it is implemented, the argument + * passed to @prepare(), @enter() and @finish() is meaningless and should + * be ignored. * - * @finish: Called when the system has left the given state and all devices - * are resumed. The return value is ignored. + * @prepare: Prepare the platform for entering the system sleep state indicated + * by @set_target() or represented by the argument if @set_target() is not + * implemented. + * @prepare() is called right after devices have been suspended (ie. the + * appropriate .suspend() method has been executed for each device) and + * before the nonboot CPUs are disabled (it is executed with IRQs enabled). + * This callback is optional. It returns 0 on success or a negative + * error code otherwise, in which case the system cannot enter the desired + * sleep state (@enter() and @finish() will not be called in that case). + * + * @enter: Enter the system sleep state indicated by @set_target() or + * represented by the argument if @set_target() is not implemented. + * This callback is mandatory. It returns 0 on success or a negative + * error code otherwise, in which case the system cannot enter the desired + * sleep state. + * + * @finish: Called when the system has just left a sleep state, right after + * the nonboot CPUs have been enabled and before devices are resumed (it is + * executed with IRQs enabled). If @set_target() is not implemented, the + * argument represents the sleep state being left. + * This callback is optional, but should be implemented by the platforms + * that implement @prepare(). If implemented, it is always called after + * @enter() (even if @enter() fails). */ struct pm_ops { int (*valid)(suspend_state_t state); + int (*set_target)(suspend_state_t state); int (*prepare)(suspend_state_t state); int (*enter)(suspend_state_t state); int (*finish)(suspend_state_t state); }; +extern struct pm_ops *pm_ops; + /** * pm_set_ops - set platform dependent power management ops * @pm_ops: The new power management operations to set. */ extern void pm_set_ops(struct pm_ops *pm_ops); -extern struct pm_ops *pm_ops; -extern int pm_suspend(suspend_state_t state); - extern int pm_valid_only_mem(suspend_state_t state); /** @@ -161,6 +191,8 @@ extern void arch_suspend_disable_irqs(void); */ extern void arch_suspend_enable_irqs(void); +extern int pm_suspend(suspend_state_t state); + /* * Device power management */ @@ -235,15 +267,10 @@ struct dev_pm_info { unsigned can_wakeup:1; #ifdef CONFIG_PM unsigned should_wakeup:1; - pm_message_t prev_state; - void * saved_state; - struct device * pm_parent; struct list_head entry; #endif }; -extern void device_pm_set_parent(struct device * dev, struct device * parent); - extern int device_power_down(pm_message_t state); extern void device_power_up(void); extern void device_resume(void); diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h new file mode 100644 index 00000000000..606c0957997 --- /dev/null +++ b/include/linux/power_supply.h @@ -0,0 +1,180 @@ +/* + * Universal power supply monitor class + * + * Copyright © 2007 Anton Vorontsov <cbou@mail.ru> + * Copyright © 2004 Szabolcs Gyurko + * Copyright © 2003 Ian Molton <spyro@f2s.com> + * + * Modified: 2004, Oct Szabolcs Gyurko + * + * You may use this code as per GPL version 2 + */ + +#ifndef __LINUX_POWER_SUPPLY_H__ +#define __LINUX_POWER_SUPPLY_H__ + +#include <linux/device.h> +#include <linux/workqueue.h> +#include <linux/leds.h> + +/* + * All voltages, currents, charges, energies, time and temperatures in uV, + * µA, µAh, µWh, seconds and tenths of degree Celsius unless otherwise + * stated. It's driver's job to convert its raw values to units in which + * this class operates. + */ + +/* + * For systems where the charger determines the maximum battery capacity + * the min and max fields should be used to present these values to user + * space. Unused/unknown fields will not appear in sysfs. + */ + +enum { + POWER_SUPPLY_STATUS_UNKNOWN = 0, + POWER_SUPPLY_STATUS_CHARGING, + POWER_SUPPLY_STATUS_DISCHARGING, + POWER_SUPPLY_STATUS_NOT_CHARGING, + POWER_SUPPLY_STATUS_FULL, +}; + +enum { + POWER_SUPPLY_HEALTH_UNKNOWN = 0, + POWER_SUPPLY_HEALTH_GOOD, + POWER_SUPPLY_HEALTH_OVERHEAT, + POWER_SUPPLY_HEALTH_DEAD, + POWER_SUPPLY_HEALTH_OVERVOLTAGE, + POWER_SUPPLY_HEALTH_UNSPEC_FAILURE, +}; + +enum { + POWER_SUPPLY_TECHNOLOGY_UNKNOWN = 0, + POWER_SUPPLY_TECHNOLOGY_NiMH, + POWER_SUPPLY_TECHNOLOGY_LION, + POWER_SUPPLY_TECHNOLOGY_LIPO, + POWER_SUPPLY_TECHNOLOGY_LiFe, + POWER_SUPPLY_TECHNOLOGY_NiCd, +}; + +enum { + POWER_SUPPLY_CAPACITY_LEVEL_UNKNOWN = 0, + POWER_SUPPLY_CAPACITY_LEVEL_CRITICAL, + POWER_SUPPLY_CAPACITY_LEVEL_LOW, + POWER_SUPPLY_CAPACITY_LEVEL_NORMAL, + POWER_SUPPLY_CAPACITY_LEVEL_HIGH, + POWER_SUPPLY_CAPACITY_LEVEL_FULL, +}; + +enum power_supply_property { + /* Properties of type `int' */ + POWER_SUPPLY_PROP_STATUS = 0, + POWER_SUPPLY_PROP_HEALTH, + POWER_SUPPLY_PROP_PRESENT, + POWER_SUPPLY_PROP_ONLINE, + POWER_SUPPLY_PROP_TECHNOLOGY, + POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN, + POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN, + POWER_SUPPLY_PROP_VOLTAGE_NOW, + POWER_SUPPLY_PROP_VOLTAGE_AVG, + POWER_SUPPLY_PROP_CURRENT_NOW, + POWER_SUPPLY_PROP_CURRENT_AVG, + POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN, + POWER_SUPPLY_PROP_CHARGE_EMPTY_DESIGN, + POWER_SUPPLY_PROP_CHARGE_FULL, + POWER_SUPPLY_PROP_CHARGE_EMPTY, + POWER_SUPPLY_PROP_CHARGE_NOW, + POWER_SUPPLY_PROP_CHARGE_AVG, + POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN, + POWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN, + POWER_SUPPLY_PROP_ENERGY_FULL, + POWER_SUPPLY_PROP_ENERGY_EMPTY, + POWER_SUPPLY_PROP_ENERGY_NOW, + POWER_SUPPLY_PROP_ENERGY_AVG, + POWER_SUPPLY_PROP_CAPACITY, /* in percents! */ + POWER_SUPPLY_PROP_CAPACITY_LEVEL, + POWER_SUPPLY_PROP_TEMP, + POWER_SUPPLY_PROP_TEMP_AMBIENT, + POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW, + POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG, + POWER_SUPPLY_PROP_TIME_TO_FULL_NOW, + POWER_SUPPLY_PROP_TIME_TO_FULL_AVG, + /* Properties of type `const char *' */ + POWER_SUPPLY_PROP_MODEL_NAME, + POWER_SUPPLY_PROP_MANUFACTURER, +}; + +enum power_supply_type { + POWER_SUPPLY_TYPE_BATTERY = 0, + POWER_SUPPLY_TYPE_UPS, + POWER_SUPPLY_TYPE_MAINS, + POWER_SUPPLY_TYPE_USB, +}; + +union power_supply_propval { + int intval; + const char *strval; +}; + +struct power_supply { + const char *name; + enum power_supply_type type; + enum power_supply_property *properties; + size_t num_properties; + + char **supplied_to; + size_t num_supplicants; + + int (*get_property)(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val); + void (*external_power_changed)(struct power_supply *psy); + + /* For APM emulation, think legacy userspace. */ + int use_for_apm; + + /* private */ + struct device *dev; + struct work_struct changed_work; + +#ifdef CONFIG_LEDS_TRIGGERS + struct led_trigger *charging_full_trig; + char *charging_full_trig_name; + struct led_trigger *charging_trig; + char *charging_trig_name; + struct led_trigger *full_trig; + char *full_trig_name; + struct led_trigger *online_trig; + char *online_trig_name; +#endif +}; + +/* + * This is recommended structure to specify static power supply parameters. + * Generic one, parametrizable for different power supplies. Power supply + * class itself does not use it, but that's what implementing most platform + * drivers, should try reuse for consistency. + */ + +struct power_supply_info { + const char *name; + int technology; + int voltage_max_design; + int voltage_min_design; + int charge_full_design; + int charge_empty_design; + int energy_full_design; + int energy_empty_design; + int use_for_apm; +}; + +extern void power_supply_changed(struct power_supply *psy); +extern int power_supply_am_i_supplied(struct power_supply *psy); + +extern int power_supply_register(struct device *parent, + struct power_supply *psy); +extern void power_supply_unregister(struct power_supply *psy); + +/* For APM emulation, think legacy userspace. */ +extern struct class *power_supply_class; + +#endif /* __LINUX_POWER_SUPPLY_H__ */ diff --git a/include/linux/raid/raid5.h b/include/linux/raid/raid5.h index d8286db60b9..93678f57ccb 100644 --- a/include/linux/raid/raid5.h +++ b/include/linux/raid/raid5.h @@ -116,13 +116,46 @@ * attach a request to an active stripe (add_stripe_bh()) * lockdev attach-buffer unlockdev * handle a stripe (handle_stripe()) - * lockstripe clrSTRIPE_HANDLE ... (lockdev check-buffers unlockdev) .. change-state .. record io needed unlockstripe schedule io + * lockstripe clrSTRIPE_HANDLE ... + * (lockdev check-buffers unlockdev) .. + * change-state .. + * record io/ops needed unlockstripe schedule io/ops * release an active stripe (release_stripe()) * lockdev if (!--cnt) { if STRIPE_HANDLE, add to handle_list else add to inactive-list } unlockdev * * The refcount counts each thread that have activated the stripe, * plus raid5d if it is handling it, plus one for each active request - * on a cached buffer. + * on a cached buffer, and plus one if the stripe is undergoing stripe + * operations. + * + * Stripe operations are performed outside the stripe lock, + * the stripe operations are: + * -copying data between the stripe cache and user application buffers + * -computing blocks to save a disk access, or to recover a missing block + * -updating the parity on a write operation (reconstruct write and + * read-modify-write) + * -checking parity correctness + * -running i/o to disk + * These operations are carried out by raid5_run_ops which uses the async_tx + * api to (optionally) offload operations to dedicated hardware engines. + * When requesting an operation handle_stripe sets the pending bit for the + * operation and increments the count. raid5_run_ops is then run whenever + * the count is non-zero. + * There are some critical dependencies between the operations that prevent some + * from being requested while another is in flight. + * 1/ Parity check operations destroy the in cache version of the parity block, + * so we prevent parity dependent operations like writes and compute_blocks + * from starting while a check is in progress. Some dma engines can perform + * the check without damaging the parity block, in these cases the parity + * block is re-marked up to date (assuming the check was successful) and is + * not re-read from disk. + * 2/ When a write operation is requested we immediately lock the affected + * blocks, and mark them as not up to date. This causes new read requests + * to be held off, as well as parity checks and compute block operations. + * 3/ Once a compute block operation has been requested handle_stripe treats + * that block as if it is up to date. raid5_run_ops guaruntees that any + * operation that is dependent on the compute block result is initiated after + * the compute block completes. */ struct stripe_head { @@ -136,15 +169,46 @@ struct stripe_head { spinlock_t lock; int bm_seq; /* sequence number for bitmap flushes */ int disks; /* disks in stripe */ + /* stripe_operations + * @pending - pending ops flags (set for request->issue->complete) + * @ack - submitted ops flags (set for issue->complete) + * @complete - completed ops flags (set for complete) + * @target - STRIPE_OP_COMPUTE_BLK target + * @count - raid5_runs_ops is set to run when this is non-zero + */ + struct stripe_operations { + unsigned long pending; + unsigned long ack; + unsigned long complete; + int target; + int count; + u32 zero_sum_result; + } ops; struct r5dev { struct bio req; struct bio_vec vec; struct page *page; - struct bio *toread, *towrite, *written; + struct bio *toread, *read, *towrite, *written; sector_t sector; /* sector of this page */ unsigned long flags; } dev[1]; /* allocated with extra space depending of RAID geometry */ }; + +/* stripe_head_state - collects and tracks the dynamic state of a stripe_head + * for handle_stripe. It is only valid under spin_lock(sh->lock); + */ +struct stripe_head_state { + int syncing, expanding, expanded; + int locked, uptodate, to_read, to_write, failed, written; + int to_fill, compute, req_compute, non_overwrite; + int failed_num; +}; + +/* r6_state - extra state data only relevant to r6 */ +struct r6_state { + int p_failed, q_failed, qd_idx, failed_num[2]; +}; + /* Flags */ #define R5_UPTODATE 0 /* page contains current data */ #define R5_LOCKED 1 /* IO has been submitted on "req" */ @@ -158,6 +222,15 @@ struct stripe_head { #define R5_ReWrite 9 /* have tried to over-write the readerror */ #define R5_Expanded 10 /* This block now has post-expand data */ +#define R5_Wantcompute 11 /* compute_block in progress treat as + * uptodate + */ +#define R5_Wantfill 12 /* dev->toread contains a bio that needs + * filling + */ +#define R5_Wantprexor 13 /* distinguish blocks ready for rmw from + * other "towrites" + */ /* * Write method */ @@ -180,6 +253,24 @@ struct stripe_head { #define STRIPE_EXPAND_SOURCE 10 #define STRIPE_EXPAND_READY 11 /* + * Operations flags (in issue order) + */ +#define STRIPE_OP_BIOFILL 0 +#define STRIPE_OP_COMPUTE_BLK 1 +#define STRIPE_OP_PREXOR 2 +#define STRIPE_OP_BIODRAIN 3 +#define STRIPE_OP_POSTXOR 4 +#define STRIPE_OP_CHECK 5 +#define STRIPE_OP_IO 6 + +/* modifiers to the base operations + * STRIPE_OP_MOD_REPAIR_PD - compute the parity block and write it back + * STRIPE_OP_MOD_DMA_CHECK - parity is not corrupted by the check + */ +#define STRIPE_OP_MOD_REPAIR_PD 7 +#define STRIPE_OP_MOD_DMA_CHECK 8 + +/* * Plugging: * * To improve write throughput, we need to delay the handling of some diff --git a/include/linux/raid/xor.h b/include/linux/raid/xor.h index f0d67cbdea4..3e120587ead 100644 --- a/include/linux/raid/xor.h +++ b/include/linux/raid/xor.h @@ -3,9 +3,10 @@ #include <linux/raid/md.h> -#define MAX_XOR_BLOCKS 5 +#define MAX_XOR_BLOCKS 4 -extern void xor_block(unsigned int count, unsigned int bytes, void **ptr); +extern void xor_blocks(unsigned int count, unsigned int bytes, + void *dest, void **srcs); struct xor_block_template { struct xor_block_template *next; diff --git a/include/linux/rfkill.h b/include/linux/rfkill.h index 7c1ffbab786..a8a6ea809da 100644 --- a/include/linux/rfkill.h +++ b/include/linux/rfkill.h @@ -63,7 +63,7 @@ enum rfkill_state { * This structure represents a RF switch located on a network device. */ struct rfkill { - char *name; + const char *name; enum rfkill_type type; enum rfkill_state state; diff --git a/include/linux/rtnetlink.h b/include/linux/rtnetlink.h index 1fae30af91f..c91476ce314 100644 --- a/include/linux/rtnetlink.h +++ b/include/linux/rtnetlink.h @@ -261,7 +261,7 @@ enum rtattr_type_t RTA_FLOW, RTA_CACHEINFO, RTA_SESSION, - RTA_MP_ALGO, + RTA_MP_ALGO, /* no longer used */ RTA_TABLE, __RTA_MAX }; @@ -570,10 +570,16 @@ static __inline__ int rtattr_strcmp(const struct rtattr *rta, const char *str) } extern int rtattr_parse(struct rtattr *tb[], int maxattr, struct rtattr *rta, int len); +extern int __rtattr_parse_nested_compat(struct rtattr *tb[], int maxattr, + struct rtattr *rta, int len); #define rtattr_parse_nested(tb, max, rta) \ rtattr_parse((tb), (max), RTA_DATA((rta)), RTA_PAYLOAD((rta))) +#define rtattr_parse_nested_compat(tb, max, rta, data, len) \ +({ data = RTA_PAYLOAD(rta) >= len ? RTA_DATA(rta) : NULL; \ + __rtattr_parse_nested_compat(tb, max, rta, len); }) + extern int rtnetlink_send(struct sk_buff *skb, u32 pid, u32 group, int echo); extern int rtnl_unicast(struct sk_buff *skb, u32 pid); extern int rtnl_notify(struct sk_buff *skb, u32 pid, u32 group, @@ -638,6 +644,18 @@ extern void __rta_fill(struct sk_buff *skb, int attrtype, int attrlen, const voi ({ (start)->rta_len = skb_tail_pointer(skb) - (unsigned char *)(start); \ (skb)->len; }) +#define RTA_NEST_COMPAT(skb, type, attrlen, data) \ +({ struct rtattr *__start = (struct rtattr *)skb_tail_pointer(skb); \ + RTA_PUT(skb, type, attrlen, data); \ + RTA_NEST(skb, type); \ + __start; }) + +#define RTA_NEST_COMPAT_END(skb, start) \ +({ struct rtattr *__nest = (void *)(start) + NLMSG_ALIGN((start)->rta_len); \ + (start)->rta_len = skb_tail_pointer(skb) - (unsigned char *)(start); \ + RTA_NEST_END(skb, __nest); \ + (skb)->len; }) + #define RTA_NEST_CANCEL(skb, start) \ ({ if (start) \ skb_trim(skb, (unsigned char *) (start) - (skb)->data); \ diff --git a/include/linux/sched.h b/include/linux/sched.h index d58e74b9836..cfb680585ab 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -34,6 +34,8 @@ #define SCHED_FIFO 1 #define SCHED_RR 2 #define SCHED_BATCH 3 +/* SCHED_ISO: reserved but not implemented yet */ +#define SCHED_IDLE 5 #ifdef __KERNEL__ @@ -130,6 +132,26 @@ extern unsigned long nr_active(void); extern unsigned long nr_iowait(void); extern unsigned long weighted_cpuload(const int cpu); +struct seq_file; +struct cfs_rq; +#ifdef CONFIG_SCHED_DEBUG +extern void proc_sched_show_task(struct task_struct *p, struct seq_file *m); +extern void proc_sched_set_task(struct task_struct *p); +extern void +print_cfs_rq(struct seq_file *m, int cpu, struct cfs_rq *cfs_rq, u64 now); +#else +static inline void +proc_sched_show_task(struct task_struct *p, struct seq_file *m) +{ +} +static inline void proc_sched_set_task(struct task_struct *p) +{ +} +static inline void +print_cfs_rq(struct seq_file *m, int cpu, struct cfs_rq *cfs_rq, u64 now) +{ +} +#endif /* * Task state bitmask. NOTE! These bits are also @@ -193,6 +215,7 @@ struct task_struct; extern void sched_init(void); extern void sched_init_smp(void); extern void init_idle(struct task_struct *idle, int cpu); +extern void init_idle_bootup_task(struct task_struct *idle); extern cpumask_t nohz_cpu_mask; #if defined(CONFIG_SMP) && defined(CONFIG_NO_HZ) @@ -479,7 +502,7 @@ struct signal_struct { * from jiffies_to_ns(utime + stime) if sched_clock uses something * other than jiffies.) */ - unsigned long long sched_time; + unsigned long long sum_sched_runtime; /* * We don't bother to synchronize most readers of this at all, @@ -521,31 +544,6 @@ struct signal_struct { #define SIGNAL_STOP_CONTINUED 0x00000004 /* SIGCONT since WCONTINUED reap */ #define SIGNAL_GROUP_EXIT 0x00000008 /* group exit in progress */ - -/* - * Priority of a process goes from 0..MAX_PRIO-1, valid RT - * priority is 0..MAX_RT_PRIO-1, and SCHED_NORMAL/SCHED_BATCH - * tasks are in the range MAX_RT_PRIO..MAX_PRIO-1. Priority - * values are inverted: lower p->prio value means higher priority. - * - * The MAX_USER_RT_PRIO value allows the actual maximum - * RT priority to be separate from the value exported to - * user-space. This allows kernel threads to set their - * priority to a value higher than any user task. Note: - * MAX_RT_PRIO must not be smaller than MAX_USER_RT_PRIO. - */ - -#define MAX_USER_RT_PRIO 100 -#define MAX_RT_PRIO MAX_USER_RT_PRIO - -#define MAX_PRIO (MAX_RT_PRIO + 40) - -#define rt_prio(prio) unlikely((prio) < MAX_RT_PRIO) -#define rt_task(p) rt_prio((p)->prio) -#define batch_task(p) (unlikely((p)->policy == SCHED_BATCH)) -#define is_rt_policy(p) ((p) != SCHED_NORMAL && (p) != SCHED_BATCH) -#define has_rt_policy(p) unlikely(is_rt_policy((p)->policy)) - /* * Some day this will be a full-fledged user tracking system.. */ @@ -583,13 +581,13 @@ struct reclaim_state; #if defined(CONFIG_SCHEDSTATS) || defined(CONFIG_TASK_DELAY_ACCT) struct sched_info { /* cumulative counters */ - unsigned long cpu_time, /* time spent on the cpu */ - run_delay, /* time spent waiting on a runqueue */ - pcnt; /* # of timeslices run on this cpu */ + unsigned long pcnt; /* # of times run on this cpu */ + unsigned long long cpu_time, /* time spent on the cpu */ + run_delay; /* time spent waiting on a runqueue */ /* timestamps */ - unsigned long last_arrival, /* when we last ran on a cpu */ - last_queued; /* when we were last queued to run */ + unsigned long long last_arrival,/* when we last ran on a cpu */ + last_queued; /* when we were last queued to run */ }; #endif /* defined(CONFIG_SCHEDSTATS) || defined(CONFIG_TASK_DELAY_ACCT) */ @@ -639,18 +637,24 @@ static inline int sched_info_on(void) #endif } -enum idle_type -{ - SCHED_IDLE, - NOT_IDLE, - NEWLY_IDLE, - MAX_IDLE_TYPES +enum cpu_idle_type { + CPU_IDLE, + CPU_NOT_IDLE, + CPU_NEWLY_IDLE, + CPU_MAX_IDLE_TYPES }; /* * sched-domains (multiprocessor balancing) declarations: */ -#define SCHED_LOAD_SCALE 128UL /* increase resolution of load */ + +/* + * Increase resolution of nice-level calculations: + */ +#define SCHED_LOAD_SHIFT 10 +#define SCHED_LOAD_SCALE (1L << SCHED_LOAD_SHIFT) + +#define SCHED_LOAD_SCALE_FUZZ (SCHED_LOAD_SCALE >> 5) #ifdef CONFIG_SMP #define SD_LOAD_BALANCE 1 /* Do load balancing on this domain. */ @@ -719,14 +723,14 @@ struct sched_domain { #ifdef CONFIG_SCHEDSTATS /* load_balance() stats */ - unsigned long lb_cnt[MAX_IDLE_TYPES]; - unsigned long lb_failed[MAX_IDLE_TYPES]; - unsigned long lb_balanced[MAX_IDLE_TYPES]; - unsigned long lb_imbalance[MAX_IDLE_TYPES]; - unsigned long lb_gained[MAX_IDLE_TYPES]; - unsigned long lb_hot_gained[MAX_IDLE_TYPES]; - unsigned long lb_nobusyg[MAX_IDLE_TYPES]; - unsigned long lb_nobusyq[MAX_IDLE_TYPES]; + unsigned long lb_cnt[CPU_MAX_IDLE_TYPES]; + unsigned long lb_failed[CPU_MAX_IDLE_TYPES]; + unsigned long lb_balanced[CPU_MAX_IDLE_TYPES]; + unsigned long lb_imbalance[CPU_MAX_IDLE_TYPES]; + unsigned long lb_gained[CPU_MAX_IDLE_TYPES]; + unsigned long lb_hot_gained[CPU_MAX_IDLE_TYPES]; + unsigned long lb_nobusyg[CPU_MAX_IDLE_TYPES]; + unsigned long lb_nobusyq[CPU_MAX_IDLE_TYPES]; /* Active load balancing */ unsigned long alb_cnt; @@ -753,12 +757,6 @@ struct sched_domain { extern int partition_sched_domains(cpumask_t *partition1, cpumask_t *partition2); -/* - * Maximum cache size the migration-costs auto-tuning code will - * search from: - */ -extern unsigned int max_cache_size; - #endif /* CONFIG_SMP */ @@ -809,14 +807,86 @@ struct mempolicy; struct pipe_inode_info; struct uts_namespace; -enum sleep_type { - SLEEP_NORMAL, - SLEEP_NONINTERACTIVE, - SLEEP_INTERACTIVE, - SLEEP_INTERRUPTED, +struct rq; +struct sched_domain; + +struct sched_class { + struct sched_class *next; + + void (*enqueue_task) (struct rq *rq, struct task_struct *p, + int wakeup, u64 now); + void (*dequeue_task) (struct rq *rq, struct task_struct *p, + int sleep, u64 now); + void (*yield_task) (struct rq *rq, struct task_struct *p); + + void (*check_preempt_curr) (struct rq *rq, struct task_struct *p); + + struct task_struct * (*pick_next_task) (struct rq *rq, u64 now); + void (*put_prev_task) (struct rq *rq, struct task_struct *p, u64 now); + + int (*load_balance) (struct rq *this_rq, int this_cpu, + struct rq *busiest, + unsigned long max_nr_move, unsigned long max_load_move, + struct sched_domain *sd, enum cpu_idle_type idle, + int *all_pinned, unsigned long *total_load_moved); + + void (*set_curr_task) (struct rq *rq); + void (*task_tick) (struct rq *rq, struct task_struct *p); + void (*task_new) (struct rq *rq, struct task_struct *p); }; -struct prio_array; +struct load_weight { + unsigned long weight, inv_weight; +}; + +/* + * CFS stats for a schedulable entity (task, task-group etc) + * + * Current field usage histogram: + * + * 4 se->block_start + * 4 se->run_node + * 4 se->sleep_start + * 4 se->sleep_start_fair + * 6 se->load.weight + * 7 se->delta_fair + * 15 se->wait_runtime + */ +struct sched_entity { + long wait_runtime; + unsigned long delta_fair_run; + unsigned long delta_fair_sleep; + unsigned long delta_exec; + s64 fair_key; + struct load_weight load; /* for load-balancing */ + struct rb_node run_node; + unsigned int on_rq; + + u64 wait_start_fair; + u64 wait_start; + u64 exec_start; + u64 sleep_start; + u64 sleep_start_fair; + u64 block_start; + u64 sleep_max; + u64 block_max; + u64 exec_max; + u64 wait_max; + u64 last_ran; + + u64 sum_exec_runtime; + s64 sum_wait_runtime; + s64 sum_sleep_runtime; + unsigned long wait_runtime_overruns; + unsigned long wait_runtime_underruns; +#ifdef CONFIG_FAIR_GROUP_SCHED + struct sched_entity *parent; + /* rq on which this entity is (to be) queued: */ + struct cfs_rq *cfs_rq; + /* rq "owned" by this entity/group: */ + struct cfs_rq *my_q; +#endif +}; struct task_struct { volatile long state; /* -1 unrunnable, 0 runnable, >0 stopped */ @@ -832,23 +902,20 @@ struct task_struct { int oncpu; #endif #endif - int load_weight; /* for niceness load balancing purposes */ + int prio, static_prio, normal_prio; struct list_head run_list; - struct prio_array *array; + struct sched_class *sched_class; + struct sched_entity se; unsigned short ioprio; #ifdef CONFIG_BLK_DEV_IO_TRACE unsigned int btrace_seq; #endif - unsigned long sleep_avg; - unsigned long long timestamp, last_ran; - unsigned long long sched_time; /* sched_clock time spent running */ - enum sleep_type sleep_type; unsigned int policy; cpumask_t cpus_allowed; - unsigned int time_slice, first_time_slice; + unsigned int time_slice; #if defined(CONFIG_SCHEDSTATS) || defined(CONFIG_TASK_DELAY_ACCT) struct sched_info sched_info; @@ -1078,6 +1145,37 @@ struct task_struct { #endif }; +/* + * Priority of a process goes from 0..MAX_PRIO-1, valid RT + * priority is 0..MAX_RT_PRIO-1, and SCHED_NORMAL/SCHED_BATCH + * tasks are in the range MAX_RT_PRIO..MAX_PRIO-1. Priority + * values are inverted: lower p->prio value means higher priority. + * + * The MAX_USER_RT_PRIO value allows the actual maximum + * RT priority to be separate from the value exported to + * user-space. This allows kernel threads to set their + * priority to a value higher than any user task. Note: + * MAX_RT_PRIO must not be smaller than MAX_USER_RT_PRIO. + */ + +#define MAX_USER_RT_PRIO 100 +#define MAX_RT_PRIO MAX_USER_RT_PRIO + +#define MAX_PRIO (MAX_RT_PRIO + 40) +#define DEFAULT_PRIO (MAX_RT_PRIO + 20) + +static inline int rt_prio(int prio) +{ + if (unlikely(prio < MAX_RT_PRIO)) + return 1; + return 0; +} + +static inline int rt_task(struct task_struct *p) +{ + return rt_prio(p->prio); +} + static inline pid_t process_group(struct task_struct *tsk) { return tsk->signal->pgrp; @@ -1162,6 +1260,7 @@ static inline void put_task_struct(struct task_struct *t) /* Not implemented yet, only for 486*/ #define PF_STARTING 0x00000002 /* being created */ #define PF_EXITING 0x00000004 /* getting shut down */ +#define PF_EXITPIDONE 0x00000008 /* pi exit done on shut down */ #define PF_FORKNOEXEC 0x00000040 /* forked but didn't exec */ #define PF_SUPERPRIV 0x00000100 /* used super-user privileges */ #define PF_DUMPCORE 0x00000200 /* dumped core */ @@ -1222,7 +1321,7 @@ static inline int set_cpus_allowed(struct task_struct *p, cpumask_t new_mask) extern unsigned long long sched_clock(void); extern unsigned long long -current_sched_time(const struct task_struct *current_task); +task_sched_runtime(struct task_struct *task); /* sched_exec is called by processes performing an exec */ #ifdef CONFIG_SMP @@ -1231,6 +1330,8 @@ extern void sched_exec(void); #define sched_exec() {} #endif +extern void sched_clock_unstable_event(void); + #ifdef CONFIG_HOTPLUG_CPU extern void idle_task_exit(void); #else @@ -1239,6 +1340,14 @@ static inline void idle_task_exit(void) {} extern void sched_idle_next(void); +extern unsigned int sysctl_sched_granularity; +extern unsigned int sysctl_sched_wakeup_granularity; +extern unsigned int sysctl_sched_batch_wakeup_granularity; +extern unsigned int sysctl_sched_stat_granularity; +extern unsigned int sysctl_sched_runtime_limit; +extern unsigned int sysctl_sched_child_runs_first; +extern unsigned int sysctl_sched_features; + #ifdef CONFIG_RT_MUTEXES extern int rt_mutex_getprio(struct task_struct *p); extern void rt_mutex_setprio(struct task_struct *p, int prio); @@ -1316,8 +1425,8 @@ extern void FASTCALL(wake_up_new_task(struct task_struct * tsk, #else static inline void kick_process(struct task_struct *tsk) { } #endif -extern void FASTCALL(sched_fork(struct task_struct * p, int clone_flags)); -extern void FASTCALL(sched_exit(struct task_struct * p)); +extern void sched_fork(struct task_struct *p, int clone_flags); +extern void sched_dead(struct task_struct *p); extern int in_group_p(gid_t); extern int in_egroup_p(gid_t); @@ -1405,7 +1514,7 @@ extern struct mm_struct * mm_alloc(void); extern void FASTCALL(__mmdrop(struct mm_struct *)); static inline void mmdrop(struct mm_struct * mm) { - if (atomic_dec_and_test(&mm->mm_count)) + if (unlikely(atomic_dec_and_test(&mm->mm_count))) __mmdrop(mm); } @@ -1637,10 +1746,7 @@ static inline unsigned int task_cpu(const struct task_struct *p) return task_thread_info(p)->cpu; } -static inline void set_task_cpu(struct task_struct *p, unsigned int cpu) -{ - task_thread_info(p)->cpu = cpu; -} +extern void set_task_cpu(struct task_struct *p, unsigned int cpu); #else diff --git a/include/linux/screen_info.h b/include/linux/screen_info.h index b02308ee766..3ee412bc00e 100644 --- a/include/linux/screen_info.h +++ b/include/linux/screen_info.h @@ -10,7 +10,7 @@ struct screen_info { u8 orig_x; /* 0x00 */ u8 orig_y; /* 0x01 */ - u16 dontuse1; /* 0x02 -- EXT_MEM_K sits here */ + u16 ext_mem_k; /* 0x02 */ u16 orig_video_page; /* 0x04 */ u8 orig_video_mode; /* 0x06 */ u8 orig_video_cols; /* 0x07 */ @@ -27,7 +27,7 @@ struct screen_info { u16 lfb_depth; /* 0x16 */ u32 lfb_base; /* 0x18 */ u32 lfb_size; /* 0x1c */ - u16 dontuse2, dontuse3; /* 0x20 -- CL_MAGIC and CL_OFFSET here */ + u16 cl_magic, cl_offset; /* 0x20 */ u16 lfb_linelength; /* 0x24 */ u8 red_size; /* 0x26 */ u8 red_pos; /* 0x27 */ @@ -42,9 +42,8 @@ struct screen_info { u16 pages; /* 0x32 */ u16 vesa_attributes; /* 0x34 */ u32 capabilities; /* 0x36 */ - /* 0x3a -- 0x3b reserved for future expansion */ - /* 0x3c -- 0x3f micro stack for relocatable kernels */ -}; + u8 _reserved[6]; /* 0x3a */ +} __attribute__((packed)); extern struct screen_info screen_info; diff --git a/include/linux/security.h b/include/linux/security.h index 9eb9e0fe033..c11dc8aa035 100644 --- a/include/linux/security.h +++ b/include/linux/security.h @@ -71,6 +71,7 @@ struct xfrm_user_sec_ctx; extern int cap_netlink_send(struct sock *sk, struct sk_buff *skb); extern int cap_netlink_recv(struct sk_buff *skb, int cap); +extern unsigned long mmap_min_addr; /* * Values used in the task_security_ops calls */ @@ -1241,8 +1242,9 @@ struct security_operations { int (*file_ioctl) (struct file * file, unsigned int cmd, unsigned long arg); int (*file_mmap) (struct file * file, - unsigned long reqprot, - unsigned long prot, unsigned long flags); + unsigned long reqprot, unsigned long prot, + unsigned long flags, unsigned long addr, + unsigned long addr_only); int (*file_mprotect) (struct vm_area_struct * vma, unsigned long reqprot, unsigned long prot); @@ -1814,9 +1816,12 @@ static inline int security_file_ioctl (struct file *file, unsigned int cmd, static inline int security_file_mmap (struct file *file, unsigned long reqprot, unsigned long prot, - unsigned long flags) + unsigned long flags, + unsigned long addr, + unsigned long addr_only) { - return security_ops->file_mmap (file, reqprot, prot, flags); + return security_ops->file_mmap (file, reqprot, prot, flags, addr, + addr_only); } static inline int security_file_mprotect (struct vm_area_struct *vma, @@ -2489,7 +2494,9 @@ static inline int security_file_ioctl (struct file *file, unsigned int cmd, static inline int security_file_mmap (struct file *file, unsigned long reqprot, unsigned long prot, - unsigned long flags) + unsigned long flags, + unsigned long addr, + unsigned long addr_only) { return 0; } diff --git a/include/linux/seq_file.h b/include/linux/seq_file.h index 3e3cccbb1ca..83783ab0f55 100644 --- a/include/linux/seq_file.h +++ b/include/linux/seq_file.h @@ -50,5 +50,16 @@ int seq_release_private(struct inode *, struct file *); #define SEQ_START_TOKEN ((void *)1) +/* + * Helpers for iteration over list_head-s in seq_files + */ + +extern struct list_head *seq_list_start(struct list_head *head, + loff_t pos); +extern struct list_head *seq_list_start_head(struct list_head *head, + loff_t pos); +extern struct list_head *seq_list_next(void *v, struct list_head *head, + loff_t *ppos); + #endif #endif diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h index a3ac4c89683..7f2c99d66e9 100644 --- a/include/linux/serial_core.h +++ b/include/linux/serial_core.h @@ -152,6 +152,7 @@ #include <linux/sched.h> #include <linux/tty.h> #include <linux/mutex.h> +#include <linux/sysrq.h> struct uart_port; struct uart_info; diff --git a/include/linux/serio.h b/include/linux/serio.h index 1ebf0455e22..d9377ce9ffd 100644 --- a/include/linux/serio.h +++ b/include/linux/serio.h @@ -209,5 +209,6 @@ static inline void serio_unpin_driver(struct serio *serio) #define SERIO_PENMOUNT 0x31 #define SERIO_TOUCHRIGHT 0x32 #define SERIO_TOUCHWIN 0x33 +#define SERIO_TAOSEVM 0x34 #endif diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h index e7367c74e1b..ce256438e61 100644 --- a/include/linux/skbuff.h +++ b/include/linux/skbuff.h @@ -65,13 +65,20 @@ * is able to produce some skb->csum, it MUST use COMPLETE, * not UNNECESSARY. * + * PARTIAL: identical to the case for output below. This may occur + * on a packet received directly from another Linux OS, e.g., + * a virtualised Linux kernel on the same host. The packet can + * be treated in the same way as UNNECESSARY except that on + * output (i.e., forwarding) the checksum must be filled in + * by the OS or the hardware. + * * B. Checksumming on output. * * NONE: skb is checksummed by protocol or csum is not required. * * PARTIAL: device is required to csum packet as seen by hard_start_xmit - * from skb->transport_header to the end and to record the checksum - * at skb->transport_header + skb->csum. + * from skb->csum_start to the end and to record the checksum + * at skb->csum_start + skb->csum_offset. * * Device must show its capabilities in dev->features, set * at device setup time. @@ -82,6 +89,7 @@ * TCP/UDP over IPv4. Sigh. Vendors like this * way by an unknown reason. Though, see comment above * about CHECKSUM_UNNECESSARY. 8) + * NETIF_F_IPV6_CSUM about as dumb as the last one but does IPv6 instead. * * Any questions? No questions, good. --ANK */ @@ -147,8 +155,8 @@ struct skb_shared_info { /* We divide dataref into two halves. The higher 16 bits hold references * to the payload part of skb->data. The lower 16 bits hold references to - * the entire skb->data. It is up to the users of the skb to agree on - * where the payload starts. + * the entire skb->data. A clone of a headerless skb holds the length of + * the header in skb->hdr_len. * * All users must obey the rule that the skb->data reference count must be * greater than or equal to the payload reference count. @@ -196,7 +204,6 @@ typedef unsigned char *sk_buff_data_t; * @sk: Socket we are owned by * @tstamp: Time we arrived * @dev: Device we arrived on/are leaving by - * @iif: ifindex of device we arrived on * @transport_header: Transport layer header * @network_header: Network layer header * @mac_header: Link layer header @@ -206,6 +213,7 @@ typedef unsigned char *sk_buff_data_t; * @len: Length of actual data * @data_len: Data length * @mac_len: Length of link layer header + * @hdr_len: writable header length of cloned skb * @csum: Checksum (must include start/offset pair) * @csum_start: Offset from skb->head where checksumming should start * @csum_offset: Offset from csum_start where checksum should be stored @@ -227,9 +235,12 @@ typedef unsigned char *sk_buff_data_t; * @mark: Generic packet mark * @nfct: Associated connection, if any * @ipvs_property: skbuff is owned by ipvs + * @nf_trace: netfilter packet trace flag * @nfctinfo: Relationship of this skb to the connection * @nfct_reasm: netfilter conntrack re-assembly pointer * @nf_bridge: Saved data about a bridged frame - see br_netfilter.c + * @iif: ifindex of device we arrived on + * @queue_mapping: Queue mapping for multiqueue devices * @tc_index: Traffic control index * @tc_verd: traffic control verdict * @dma_cookie: a cookie to one of several possible DMA operations @@ -245,8 +256,6 @@ struct sk_buff { struct sock *sk; ktime_t tstamp; struct net_device *dev; - int iif; - /* 4 byte hole on 64 bit*/ struct dst_entry *dst; struct sec_path *sp; @@ -260,8 +269,9 @@ struct sk_buff { char cb[48]; unsigned int len, - data_len, - mac_len; + data_len; + __u16 mac_len, + hdr_len; union { __wsum csum; struct { @@ -277,7 +287,8 @@ struct sk_buff { nfctinfo:3; __u8 pkt_type:3, fclone:2, - ipvs_property:1; + ipvs_property:1, + nf_trace:1; __be16 protocol; void (*destructor)(struct sk_buff *skb); @@ -288,12 +299,18 @@ struct sk_buff { #ifdef CONFIG_BRIDGE_NETFILTER struct nf_bridge_info *nf_bridge; #endif + + int iif; + __u16 queue_mapping; + #ifdef CONFIG_NET_SCHED __u16 tc_index; /* traffic control index */ #ifdef CONFIG_NET_CLS_ACT __u16 tc_verd; /* traffic control verdict */ #endif #endif + /* 2 byte hole */ + #ifdef CONFIG_NET_DMA dma_cookie_t dma_cookie; #endif @@ -1322,6 +1339,20 @@ static inline struct sk_buff *netdev_alloc_skb(struct net_device *dev, } /** + * skb_clone_writable - is the header of a clone writable + * @skb: buffer to check + * @len: length up to which to write + * + * Returns true if modifying the header part of the cloned buffer + * does not requires the data to be copied. + */ +static inline int skb_clone_writable(struct sk_buff *skb, int len) +{ + return !skb_header_cloned(skb) && + skb_headroom(skb) + len <= skb->hdr_len; +} + +/** * skb_cow - copy header of skb when it is required * @skb: buffer to cow * @headroom: needed headroom @@ -1579,6 +1610,10 @@ static inline ktime_t net_timedelta(ktime_t t) return ktime_sub(ktime_get_real(), t); } +static inline ktime_t net_invalid_timestamp(void) +{ + return ktime_set(0, 0); +} extern __sum16 __skb_checksum_complete_head(struct sk_buff *skb, int len); extern __sum16 __skb_checksum_complete(struct sk_buff *skb); @@ -1604,7 +1639,7 @@ static inline int skb_csum_unnecessary(const struct sk_buff *skb) * if skb->ip_summed is CHECKSUM_UNNECESSARY which indicates that the * hardware has already verified the correctness of the checksum. */ -static inline unsigned int skb_checksum_complete(struct sk_buff *skb) +static inline __sum16 skb_checksum_complete(struct sk_buff *skb) { return skb_csum_unnecessary(skb) ? 0 : __skb_checksum_complete(skb); @@ -1705,6 +1740,20 @@ static inline void skb_init_secmark(struct sk_buff *skb) { } #endif +static inline void skb_set_queue_mapping(struct sk_buff *skb, u16 queue_mapping) +{ +#ifdef CONFIG_NETDEVICES_MULTIQUEUE + skb->queue_mapping = queue_mapping; +#endif +} + +static inline void skb_copy_queue_mapping(struct sk_buff *to, const struct sk_buff *from) +{ +#ifdef CONFIG_NETDEVICES_MULTIQUEUE + to->queue_mapping = from->queue_mapping; +#endif +} + static inline int skb_is_gso(const struct sk_buff *skb) { return skb_shinfo(skb)->gso_size; diff --git a/include/linux/slab.h b/include/linux/slab.h index a015236cc57..cebcd3833c7 100644 --- a/include/linux/slab.h +++ b/include/linux/slab.h @@ -82,8 +82,8 @@ static inline void *kmem_cache_alloc_node(struct kmem_cache *cachep, * to do various tricks to work around compiler limitations in order to * ensure proper constant folding. */ -#define KMALLOC_SHIFT_HIGH ((MAX_ORDER + PAGE_SHIFT) <= 25 ? \ - (MAX_ORDER + PAGE_SHIFT) : 25) +#define KMALLOC_SHIFT_HIGH ((MAX_ORDER + PAGE_SHIFT - 1) <= 25 ? \ + (MAX_ORDER + PAGE_SHIFT - 1) : 25) #define KMALLOC_MAX_SIZE (1UL << KMALLOC_SHIFT_HIGH) #define KMALLOC_MAX_ORDER (KMALLOC_SHIFT_HIGH - PAGE_SHIFT) diff --git a/include/linux/slub_def.h b/include/linux/slub_def.h index 0764c829d96..6207a3d8da7 100644 --- a/include/linux/slub_def.h +++ b/include/linux/slub_def.h @@ -28,7 +28,7 @@ struct kmem_cache { int size; /* The size of an object including meta data */ int objsize; /* The size of an object without meta data */ int offset; /* Free pointer offset. */ - unsigned int order; + int order; /* * Avoid an extra cache line for UP, SMP and for the node local to @@ -56,7 +56,13 @@ struct kmem_cache { /* * Kmalloc subsystem. */ -#define KMALLOC_SHIFT_LOW 3 +#if defined(ARCH_KMALLOC_MINALIGN) && ARCH_KMALLOC_MINALIGN > 8 +#define KMALLOC_MIN_SIZE ARCH_KMALLOC_MINALIGN +#else +#define KMALLOC_MIN_SIZE 8 +#endif + +#define KMALLOC_SHIFT_LOW ilog2(KMALLOC_MIN_SIZE) /* * We keep the general caches in an array of slab caches that are used for @@ -70,15 +76,15 @@ extern struct kmem_cache kmalloc_caches[KMALLOC_SHIFT_HIGH + 1]; */ static inline int kmalloc_index(size_t size) { - /* - * We should return 0 if size == 0 but we use the smallest object - * here for SLAB legacy reasons. - */ - WARN_ON_ONCE(size == 0); + if (!size) + return 0; if (size > KMALLOC_MAX_SIZE) return -1; + if (size <= KMALLOC_MIN_SIZE) + return KMALLOC_SHIFT_LOW; + if (size > 64 && size <= 96) return 1; if (size > 128 && size <= 192) @@ -153,13 +159,25 @@ static inline struct kmem_cache *kmalloc_slab(size_t size) #define SLUB_DMA 0 #endif + +/* + * ZERO_SIZE_PTR will be returned for zero sized kmalloc requests. + * + * Dereferencing ZERO_SIZE_PTR will lead to a distinct access fault. + * + * ZERO_SIZE_PTR can be passed to kfree though in the same way that NULL can. + * Both make kfree a no-op. + */ +#define ZERO_SIZE_PTR ((void *)16) + + static inline void *kmalloc(size_t size, gfp_t flags) { if (__builtin_constant_p(size) && !(flags & SLUB_DMA)) { struct kmem_cache *s = kmalloc_slab(size); if (!s) - return NULL; + return ZERO_SIZE_PTR; return kmem_cache_alloc(s, flags); } else @@ -172,7 +190,7 @@ static inline void *kzalloc(size_t size, gfp_t flags) struct kmem_cache *s = kmalloc_slab(size); if (!s) - return NULL; + return ZERO_SIZE_PTR; return kmem_cache_zalloc(s, flags); } else @@ -188,7 +206,7 @@ static inline void *kmalloc_node(size_t size, gfp_t flags, int node) struct kmem_cache *s = kmalloc_slab(size); if (!s) - return NULL; + return ZERO_SIZE_PTR; return kmem_cache_alloc_node(s, flags, node); } else diff --git a/include/linux/sm501-regs.h b/include/linux/sm501-regs.h index cc9be4a1186..014e73b31fc 100644 --- a/include/linux/sm501-regs.h +++ b/include/linux/sm501-regs.h @@ -64,6 +64,11 @@ #define SM501_DEBUG_CONTROL (0x000034) /* power management */ +#define SM501_POWERMODE_P2X_SRC (1<<29) +#define SM501_POWERMODE_V2X_SRC (1<<20) +#define SM501_POWERMODE_M_SRC (1<<12) +#define SM501_POWERMODE_M1_SRC (1<<4) + #define SM501_CURRENT_GATE (0x000038) #define SM501_CURRENT_CLOCK (0x00003C) #define SM501_POWER_MODE_0_GATE (0x000040) @@ -104,6 +109,9 @@ #define SM501_DEVICEID (0x000060) /* 0x050100A0 */ +#define SM501_DEVICEID_SM501 (0x05010000) +#define SM501_DEVICEID_IDMASK (0xffff0000) + #define SM501_PLLCLOCK_COUNT (0x000064) #define SM501_MISC_TIMING (0x000068) #define SM501_CURRENT_SDRAM_CLOCK (0x00006C) diff --git a/include/linux/socket.h b/include/linux/socket.h index 6e7c9483a6a..fe195c97a89 100644 --- a/include/linux/socket.h +++ b/include/linux/socket.h @@ -287,6 +287,7 @@ struct ucred { #define SOL_NETLINK 270 #define SOL_TIPC 271 #define SOL_RXRPC 272 +#define SOL_PPPOL2TP 273 /* IPX options */ #define IPX_TYPE 1 diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index b6bedc3ee95..1be5ea05947 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -341,9 +341,14 @@ extern struct spi_master *spi_busnum_to_master(u16 busnum); * chip transactions together. * * (ii) When the transfer is the last one in the message, the chip may - * stay selected until the next transfer. This is purely a performance - * hint; the controller driver may need to select a different device - * for the next message. + * stay selected until the next transfer. On multi-device SPI busses + * with nothing blocking messages going to other devices, this is just + * a performance hint; starting a message to another device deselects + * this one. But in other cases, this can be used to ensure correctness. + * Some devices need protocol transactions to be built from a series of + * spi_message submissions, where the content of one message is determined + * by the results of previous messages and where the whole transaction + * ends when the chipselect goes intactive. * * The code that submits an spi_message (and its spi_transfers) * to the lower layers is responsible for managing its memory. @@ -480,14 +485,15 @@ static inline void spi_message_free(struct spi_message *m) /** * spi_setup - setup SPI mode and clock rate * @spi: the device whose settings are being modified - * Context: can sleep + * Context: can sleep, and no requests are queued to the device * * SPI protocol drivers may need to update the transfer mode if the - * device doesn't work with the mode 0 default. They may likewise need + * device doesn't work with its default. They may likewise need * to update clock rates or word sizes from initial values. This function * changes those settings, and must be called from a context that can sleep. - * The changes take effect the next time the device is selected and data - * is transferred to or from it. + * Except for SPI_CS_HIGH, which takes effect immediately, the changes take + * effect the next time the device is selected and data is transferred to + * or from it. When this function returns, the spi device is deselected. * * Note that this call will fail if the protocol driver specifies an option * that the underlying controller or its driver does not support. For diff --git a/include/linux/splice.h b/include/linux/splice.h new file mode 100644 index 00000000000..33e447f98a5 --- /dev/null +++ b/include/linux/splice.h @@ -0,0 +1,73 @@ +/* + * Function declerations and data structures related to the splice + * implementation. + * + * Copyright (C) 2007 Jens Axboe <jens.axboe@oracle.com> + * + */ +#ifndef SPLICE_H +#define SPLICE_H + +#include <linux/pipe_fs_i.h> + +/* + * splice is tied to pipes as a transport (at least for now), so we'll just + * add the splice flags here. + */ +#define SPLICE_F_MOVE (0x01) /* move pages instead of copying */ +#define SPLICE_F_NONBLOCK (0x02) /* don't block on the pipe splicing (but */ + /* we may still block on the fd we splice */ + /* from/to, of course */ +#define SPLICE_F_MORE (0x04) /* expect more data */ +#define SPLICE_F_GIFT (0x08) /* pages passed in are a gift */ + +/* + * Passed to the actors + */ +struct splice_desc { + unsigned int len, total_len; /* current and remaining length */ + unsigned int flags; /* splice flags */ + /* + * actor() private data + */ + union { + void __user *userptr; /* memory to write to */ + struct file *file; /* file to read/write */ + void *data; /* cookie */ + } u; + loff_t pos; /* file position */ +}; + +struct partial_page { + unsigned int offset; + unsigned int len; + unsigned long private; +}; + +/* + * Passed to splice_to_pipe + */ +struct splice_pipe_desc { + struct page **pages; /* page map */ + struct partial_page *partial; /* pages[] may not be contig */ + int nr_pages; /* number of pages in map */ + unsigned int flags; /* splice flags */ + const struct pipe_buf_operations *ops;/* ops associated with output pipe */ +}; + +typedef int (splice_actor)(struct pipe_inode_info *, struct pipe_buffer *, + struct splice_desc *); +typedef int (splice_direct_actor)(struct pipe_inode_info *, + struct splice_desc *); + +extern ssize_t splice_from_pipe(struct pipe_inode_info *, struct file *, + loff_t *, size_t, unsigned int, + splice_actor *); +extern ssize_t __splice_from_pipe(struct pipe_inode_info *, + struct splice_desc *, splice_actor *); +extern ssize_t splice_to_pipe(struct pipe_inode_info *, + struct splice_pipe_desc *); +extern ssize_t splice_direct_to_actor(struct file *, struct splice_desc *, + splice_direct_actor *); + +#endif diff --git a/include/linux/sunrpc/auth.h b/include/linux/sunrpc/auth.h index 534cdc7be58..7a69ca3beba 100644 --- a/include/linux/sunrpc/auth.h +++ b/include/linux/sunrpc/auth.h @@ -16,6 +16,7 @@ #include <linux/sunrpc/xdr.h> #include <asm/atomic.h> +#include <linux/rcupdate.h> /* size of the nodename buffer */ #define UNX_MAXNODENAME 32 @@ -30,22 +31,28 @@ struct auth_cred { /* * Client user credentials */ +struct rpc_auth; +struct rpc_credops; struct rpc_cred { struct hlist_node cr_hash; /* hash chain */ - struct rpc_credops * cr_ops; - unsigned long cr_expire; /* when to gc */ - atomic_t cr_count; /* ref count */ - unsigned short cr_flags; /* various flags */ + struct list_head cr_lru; /* lru garbage collection */ + struct rcu_head cr_rcu; + struct rpc_auth * cr_auth; + const struct rpc_credops *cr_ops; #ifdef RPC_DEBUG unsigned long cr_magic; /* 0x0f4aa4f0 */ #endif + unsigned long cr_expire; /* when to gc */ + unsigned long cr_flags; /* various flags */ + atomic_t cr_count; /* ref count */ uid_t cr_uid; /* per-flavor data */ }; -#define RPCAUTH_CRED_NEW 0x0001 -#define RPCAUTH_CRED_UPTODATE 0x0002 +#define RPCAUTH_CRED_NEW 0 +#define RPCAUTH_CRED_UPTODATE 1 +#define RPCAUTH_CRED_HASHED 2 #define RPCAUTH_CRED_MAGIC 0x0f4aa4f0 @@ -56,10 +63,10 @@ struct rpc_cred { #define RPC_CREDCACHE_MASK (RPC_CREDCACHE_NR - 1) struct rpc_cred_cache { struct hlist_head hashtable[RPC_CREDCACHE_NR]; - unsigned long nextgc; /* next garbage collection */ - unsigned long expire; /* cache expiry interval */ + spinlock_t lock; }; +struct rpc_authops; struct rpc_auth { unsigned int au_cslack; /* call cred size estimate */ /* guess at number of u32's auth adds before @@ -69,7 +76,7 @@ struct rpc_auth { unsigned int au_verfsize; unsigned int au_flags; /* various flags */ - struct rpc_authops * au_ops; /* operations */ + const struct rpc_authops *au_ops; /* operations */ rpc_authflavor_t au_flavor; /* pseudoflavor (note may * differ from the flavor in * au_ops->au_flavor in gss @@ -115,17 +122,19 @@ struct rpc_credops { void *, __be32 *, void *); }; -extern struct rpc_authops authunix_ops; -extern struct rpc_authops authnull_ops; -#ifdef CONFIG_SUNRPC_SECURE -extern struct rpc_authops authdes_ops; -#endif +extern const struct rpc_authops authunix_ops; +extern const struct rpc_authops authnull_ops; + +void __init rpc_init_authunix(void); +void __init rpcauth_init_module(void); +void __exit rpcauth_remove_module(void); -int rpcauth_register(struct rpc_authops *); -int rpcauth_unregister(struct rpc_authops *); +int rpcauth_register(const struct rpc_authops *); +int rpcauth_unregister(const struct rpc_authops *); struct rpc_auth * rpcauth_create(rpc_authflavor_t, struct rpc_clnt *); -void rpcauth_destroy(struct rpc_auth *); +void rpcauth_release(struct rpc_auth *); struct rpc_cred * rpcauth_lookup_credcache(struct rpc_auth *, struct auth_cred *, int); +void rpcauth_init_cred(struct rpc_cred *, const struct auth_cred *, struct rpc_auth *, const struct rpc_credops *); struct rpc_cred * rpcauth_lookupcred(struct rpc_auth *, int); struct rpc_cred * rpcauth_bindcred(struct rpc_task *); void rpcauth_holdcred(struct rpc_task *); @@ -138,8 +147,9 @@ int rpcauth_unwrap_resp(struct rpc_task *task, kxdrproc_t decode, void *rqstp, int rpcauth_refreshcred(struct rpc_task *); void rpcauth_invalcred(struct rpc_task *); int rpcauth_uptodatecred(struct rpc_task *); -int rpcauth_init_credcache(struct rpc_auth *, unsigned long); -void rpcauth_free_credcache(struct rpc_auth *); +int rpcauth_init_credcache(struct rpc_auth *); +void rpcauth_destroy_credcache(struct rpc_auth *); +void rpcauth_clear_credcache(struct rpc_cred_cache *); static inline struct rpc_cred * get_rpccred(struct rpc_cred *cred) diff --git a/include/linux/sunrpc/auth_gss.h b/include/linux/sunrpc/auth_gss.h index 2db2fbf3494..67658e17a37 100644 --- a/include/linux/sunrpc/auth_gss.h +++ b/include/linux/sunrpc/auth_gss.h @@ -75,6 +75,7 @@ struct gss_cl_ctx { struct xdr_netobj gc_wire_ctx; u32 gc_win; unsigned long gc_expiry; + struct rcu_head gc_rcu; }; struct gss_upcall_msg; @@ -85,11 +86,6 @@ struct gss_cred { struct gss_upcall_msg *gc_upcall; }; -#define gc_uid gc_base.cr_uid -#define gc_count gc_base.cr_count -#define gc_flags gc_base.cr_flags -#define gc_expire gc_base.cr_expire - #endif /* __KERNEL__ */ #endif /* _LINUX_SUNRPC_AUTH_GSS_H */ diff --git a/include/linux/sunrpc/clnt.h b/include/linux/sunrpc/clnt.h index 66611423c8e..c0d9d14983b 100644 --- a/include/linux/sunrpc/clnt.h +++ b/include/linux/sunrpc/clnt.h @@ -24,8 +24,10 @@ struct rpc_inode; * The high-level client handle */ struct rpc_clnt { - atomic_t cl_count; /* Number of clones */ - atomic_t cl_users; /* number of references */ + struct kref cl_kref; /* Number of references */ + struct list_head cl_clients; /* Global list of clients */ + struct list_head cl_tasks; /* List of tasks */ + spinlock_t cl_lock; /* spinlock */ struct rpc_xprt * cl_xprt; /* transport */ struct rpc_procinfo * cl_procinfo; /* procedure info */ u32 cl_prog, /* RPC program number */ @@ -41,9 +43,7 @@ struct rpc_clnt { unsigned int cl_softrtry : 1,/* soft timeouts */ cl_intr : 1,/* interruptible */ cl_discrtry : 1,/* disconnect before retry */ - cl_autobind : 1,/* use getport() */ - cl_oneshot : 1,/* dispose after use */ - cl_dead : 1;/* abandoned */ + cl_autobind : 1;/* use getport() */ struct rpc_rtt * cl_rtt; /* RTO estimator data */ @@ -98,6 +98,7 @@ struct rpc_create_args { int protocol; struct sockaddr *address; size_t addrsize; + struct sockaddr *saddress; struct rpc_timeout *timeout; char *servername; struct rpc_program *program; @@ -110,20 +111,20 @@ struct rpc_create_args { #define RPC_CLNT_CREATE_HARDRTRY (1UL << 0) #define RPC_CLNT_CREATE_INTR (1UL << 1) #define RPC_CLNT_CREATE_AUTOBIND (1UL << 2) -#define RPC_CLNT_CREATE_ONESHOT (1UL << 3) -#define RPC_CLNT_CREATE_NONPRIVPORT (1UL << 4) -#define RPC_CLNT_CREATE_NOPING (1UL << 5) -#define RPC_CLNT_CREATE_DISCRTRY (1UL << 6) +#define RPC_CLNT_CREATE_NONPRIVPORT (1UL << 3) +#define RPC_CLNT_CREATE_NOPING (1UL << 4) +#define RPC_CLNT_CREATE_DISCRTRY (1UL << 5) struct rpc_clnt *rpc_create(struct rpc_create_args *args); struct rpc_clnt *rpc_bind_new_program(struct rpc_clnt *, struct rpc_program *, int); struct rpc_clnt *rpc_clone_client(struct rpc_clnt *); -int rpc_shutdown_client(struct rpc_clnt *); -int rpc_destroy_client(struct rpc_clnt *); +void rpc_shutdown_client(struct rpc_clnt *); void rpc_release_client(struct rpc_clnt *); + int rpcb_register(u32, u32, int, unsigned short, int *); -void rpcb_getport(struct rpc_task *); +int rpcb_getport_sync(struct sockaddr_in *, __u32, __u32, int); +void rpcb_getport_async(struct rpc_task *); void rpc_call_setup(struct rpc_task *, struct rpc_message *, int); @@ -132,20 +133,16 @@ int rpc_call_async(struct rpc_clnt *clnt, struct rpc_message *msg, void *calldata); int rpc_call_sync(struct rpc_clnt *clnt, struct rpc_message *msg, int flags); +struct rpc_task *rpc_call_null(struct rpc_clnt *clnt, struct rpc_cred *cred, + int flags); void rpc_restart_call(struct rpc_task *); void rpc_clnt_sigmask(struct rpc_clnt *clnt, sigset_t *oldset); void rpc_clnt_sigunmask(struct rpc_clnt *clnt, sigset_t *oldset); void rpc_setbufsize(struct rpc_clnt *, unsigned int, unsigned int); size_t rpc_max_payload(struct rpc_clnt *); void rpc_force_rebind(struct rpc_clnt *); -int rpc_ping(struct rpc_clnt *clnt, int flags); size_t rpc_peeraddr(struct rpc_clnt *, struct sockaddr *, size_t); char * rpc_peeraddr2str(struct rpc_clnt *, enum rpc_display_format_t); -/* - * Helper function for NFSroot support - */ -int rpcb_getport_external(struct sockaddr_in *, __u32, __u32, int); - #endif /* __KERNEL__ */ #endif /* _LINUX_SUNRPC_CLNT_H */ diff --git a/include/linux/sunrpc/gss_api.h b/include/linux/sunrpc/gss_api.h index 5eca9e44205..bbac101ac37 100644 --- a/include/linux/sunrpc/gss_api.h +++ b/include/linux/sunrpc/gss_api.h @@ -77,7 +77,7 @@ struct gss_api_mech { struct module *gm_owner; struct xdr_netobj gm_oid; char *gm_name; - struct gss_api_ops *gm_ops; + const struct gss_api_ops *gm_ops; /* pseudoflavors supported by this mechanism: */ int gm_pf_num; struct pf_desc * gm_pfs; diff --git a/include/linux/sunrpc/rpc_pipe_fs.h b/include/linux/sunrpc/rpc_pipe_fs.h index ad293760f6e..51b977a4ca2 100644 --- a/include/linux/sunrpc/rpc_pipe_fs.h +++ b/include/linux/sunrpc/rpc_pipe_fs.h @@ -23,9 +23,11 @@ struct rpc_inode { void *private; struct list_head pipe; struct list_head in_upcall; + struct list_head in_downcall; int pipelen; int nreaders; int nwriters; + int nkern_readwriters; wait_queue_head_t waitq; #define RPC_PIPE_WAIT_FOR_OPEN 1 int flags; diff --git a/include/linux/sunrpc/sched.h b/include/linux/sunrpc/sched.h index 2047fb202a1..8ea077db009 100644 --- a/include/linux/sunrpc/sched.h +++ b/include/linux/sunrpc/sched.h @@ -98,7 +98,6 @@ struct rpc_task { unsigned short tk_pid; /* debugging aid */ #endif }; -#define tk_auth tk_client->cl_auth #define tk_xprt tk_client->cl_xprt /* support walking a list of tasks on a wait queue */ @@ -110,11 +109,6 @@ struct rpc_task { if (!list_empty(head) && \ ((task=list_entry((head)->next, struct rpc_task, u.tk_wait.list)),1)) -/* .. and walking list of all tasks */ -#define alltask_for_each(task, pos, head) \ - list_for_each(pos, head) \ - if ((task=list_entry(pos, struct rpc_task, tk_task)),1) - typedef void (*rpc_action)(struct rpc_task *); struct rpc_call_ops { diff --git a/include/linux/sunrpc/svc.h b/include/linux/sunrpc/svc.h index 4a7ae8ab6eb..129d50f2225 100644 --- a/include/linux/sunrpc/svc.h +++ b/include/linux/sunrpc/svc.h @@ -253,7 +253,7 @@ struct svc_rqst { * determine what device number * to report (real or virtual) */ - int rq_sendfile_ok; /* turned off in gss privacy + int rq_splice_ok; /* turned off in gss privacy * to prevent encrypting page * cache pages */ wait_queue_head_t rq_wait; /* synchronization */ diff --git a/include/linux/sunrpc/svcsock.h b/include/linux/sunrpc/svcsock.h index e21dd93ac4b..a53e0fa855d 100644 --- a/include/linux/sunrpc/svcsock.h +++ b/include/linux/sunrpc/svcsock.h @@ -59,6 +59,7 @@ struct svc_sock { /* cache of various info for TCP sockets */ void *sk_info_authunix; + struct sockaddr_storage sk_local; /* local address */ struct sockaddr_storage sk_remote; /* remote peer's address */ int sk_remotelen; /* length of address */ }; diff --git a/include/linux/sunrpc/xprt.h b/include/linux/sunrpc/xprt.h index 34f7590506f..d11cedd14f0 100644 --- a/include/linux/sunrpc/xprt.h +++ b/include/linux/sunrpc/xprt.h @@ -17,6 +17,8 @@ #include <linux/sunrpc/xdr.h> #include <linux/sunrpc/msg_prot.h> +#ifdef __KERNEL__ + extern unsigned int xprt_udp_slot_table_entries; extern unsigned int xprt_tcp_slot_table_entries; @@ -194,7 +196,13 @@ struct rpc_xprt { char * address_strings[RPC_DISPLAY_MAX]; }; -#ifdef __KERNEL__ +struct rpc_xprtsock_create { + int proto; /* IPPROTO_UDP or IPPROTO_TCP */ + struct sockaddr * srcaddr; /* optional local address */ + struct sockaddr * dstaddr; /* remote peer address */ + size_t addrlen; + struct rpc_timeout * timeout; /* optional timeout parameters */ +}; /* * Transport operations used by ULPs @@ -204,7 +212,7 @@ void xprt_set_timeout(struct rpc_timeout *to, unsigned int retr, unsigned long /* * Generic internal transport functions */ -struct rpc_xprt * xprt_create_transport(int proto, struct sockaddr *addr, size_t size, struct rpc_timeout *toparms); +struct rpc_xprt * xprt_create_transport(struct rpc_xprtsock_create *args); void xprt_connect(struct rpc_task *task); void xprt_reserve(struct rpc_task *task); int xprt_reserve_xprt(struct rpc_task *task); @@ -242,8 +250,8 @@ void xprt_disconnect(struct rpc_xprt *xprt); /* * Socket transport setup operations */ -struct rpc_xprt * xs_setup_udp(struct sockaddr *addr, size_t addrlen, struct rpc_timeout *to); -struct rpc_xprt * xs_setup_tcp(struct sockaddr *addr, size_t addrlen, struct rpc_timeout *to); +struct rpc_xprt * xs_setup_udp(struct rpc_xprtsock_create *args); +struct rpc_xprt * xs_setup_tcp(struct rpc_xprtsock_create *args); int init_socket_xprt(void); void cleanup_socket_xprt(void); diff --git a/include/linux/syscalls.h b/include/linux/syscalls.h index b02070eac42..83d0ec11235 100644 --- a/include/linux/syscalls.h +++ b/include/linux/syscalls.h @@ -598,6 +598,8 @@ asmlinkage long sys_tee(int fdin, int fdout, size_t len, unsigned int flags); asmlinkage long sys_sync_file_range(int fd, loff_t offset, loff_t nbytes, unsigned int flags); +asmlinkage long sys_sync_file_range2(int fd, unsigned int flags, + loff_t offset, loff_t nbytes); asmlinkage long sys_get_robust_list(int pid, struct robust_list_head __user * __user *head_ptr, size_t __user *len_ptr); diff --git a/include/linux/sysdev.h b/include/linux/sysdev.h index e699ab279c2..e285746588d 100644 --- a/include/linux/sysdev.h +++ b/include/linux/sysdev.h @@ -101,8 +101,7 @@ struct sysdev_attribute { #define _SYSDEV_ATTR(_name,_mode,_show,_store) \ { \ - .attr = { .name = __stringify(_name), .mode = _mode, \ - .owner = THIS_MODULE }, \ + .attr = { .name = __stringify(_name), .mode = _mode }, \ .show = _show, \ .store = _store, \ } diff --git a/include/linux/sysfs.h b/include/linux/sysfs.h index 7d5d1ec95c2..be8228e50a2 100644 --- a/include/linux/sysfs.h +++ b/include/linux/sysfs.h @@ -19,10 +19,15 @@ struct kobject; struct module; struct nameidata; struct dentry; +struct sysfs_dirent; +/* FIXME + * The *owner field is no longer used, but leave around + * until the tree gets cleaned up fully. + */ struct attribute { const char * name; - struct module * owner; + struct module * owner; mode_t mode; }; @@ -39,14 +44,14 @@ struct attribute_group { */ #define __ATTR(_name,_mode,_show,_store) { \ - .attr = {.name = __stringify(_name), .mode = _mode, .owner = THIS_MODULE }, \ + .attr = {.name = __stringify(_name), .mode = _mode }, \ .show = _show, \ .store = _store, \ } #define __ATTR_RO(_name) { \ - .attr = { .name = __stringify(_name), .mode = 0444, .owner = THIS_MODULE }, \ - .show = _name##_show, \ + .attr = { .name = __stringify(_name), .mode = 0444 }, \ + .show = _name##_show, \ } #define __ATTR_NULL { .attr = { .name = NULL } } @@ -59,8 +64,10 @@ struct bin_attribute { struct attribute attr; size_t size; void *private; - ssize_t (*read)(struct kobject *, char *, loff_t, size_t); - ssize_t (*write)(struct kobject *, char *, loff_t, size_t); + ssize_t (*read)(struct kobject *, struct bin_attribute *, + char *, loff_t, size_t); + ssize_t (*write)(struct kobject *, struct bin_attribute *, + char *, loff_t, size_t); int (*mmap)(struct kobject *, struct bin_attribute *attr, struct vm_area_struct *vma); }; @@ -70,12 +77,16 @@ struct sysfs_ops { ssize_t (*store)(struct kobject *,struct attribute *,const char *, size_t); }; +#define SYSFS_TYPE_MASK 0x00ff #define SYSFS_ROOT 0x0001 #define SYSFS_DIR 0x0002 #define SYSFS_KOBJ_ATTR 0x0004 #define SYSFS_KOBJ_BIN_ATTR 0x0008 #define SYSFS_KOBJ_LINK 0x0020 -#define SYSFS_NOT_PINNED (SYSFS_KOBJ_ATTR | SYSFS_KOBJ_BIN_ATTR | SYSFS_KOBJ_LINK) +#define SYSFS_COPY_NAME (SYSFS_DIR | SYSFS_KOBJ_LINK) + +#define SYSFS_FLAG_MASK ~SYSFS_TYPE_MASK +#define SYSFS_FLAG_REMOVED 0x0100 #ifdef CONFIG_SYSFS @@ -83,13 +94,14 @@ extern int sysfs_schedule_callback(struct kobject *kobj, void (*func)(void *), void *data, struct module *owner); extern int __must_check -sysfs_create_dir(struct kobject *, struct dentry *); +sysfs_create_dir(struct kobject *kobj, struct sysfs_dirent *shadow_parent_sd); extern void sysfs_remove_dir(struct kobject *); extern int __must_check -sysfs_rename_dir(struct kobject *, struct dentry *, const char *new_name); +sysfs_rename_dir(struct kobject *kobj, struct sysfs_dirent *new_parent_sd, + const char *new_name); extern int __must_check sysfs_move_dir(struct kobject *, struct kobject *); @@ -129,8 +141,8 @@ void sysfs_notify(struct kobject * k, char *dir, char *attr); extern int sysfs_make_shadowed_dir(struct kobject *kobj, void * (*follow_link)(struct dentry *, struct nameidata *)); -extern struct dentry *sysfs_create_shadow_dir(struct kobject *kobj); -extern void sysfs_remove_shadow_dir(struct dentry *dir); +extern struct sysfs_dirent *sysfs_create_shadow_dir(struct kobject *kobj); +extern void sysfs_remove_shadow_dir(struct sysfs_dirent *shadow_sd); extern int __must_check sysfs_init(void); @@ -142,7 +154,8 @@ static inline int sysfs_schedule_callback(struct kobject *kobj, return -ENOSYS; } -static inline int sysfs_create_dir(struct kobject * k, struct dentry *shadow) +static inline int sysfs_create_dir(struct kobject *kobj, + struct sysfs_dirent *shadow_parent_sd) { return 0; } @@ -152,9 +165,9 @@ static inline void sysfs_remove_dir(struct kobject * k) ; } -static inline int sysfs_rename_dir(struct kobject * k, - struct dentry *new_parent, - const char *new_name) +static inline int sysfs_rename_dir(struct kobject *kobj, + struct sysfs_dirent *new_parent_sd, + const char *new_name) { return 0; } diff --git a/include/linux/topology.h b/include/linux/topology.h index a9d1f049cc1..d0890a7e5ba 100644 --- a/include/linux/topology.h +++ b/include/linux/topology.h @@ -50,10 +50,10 @@ for_each_online_node(node) \ if (nr_cpus_node(node)) -#ifndef node_distance /* Conform to ACPI 2.0 SLIT distance definitions */ #define LOCAL_DISTANCE 10 #define REMOTE_DISTANCE 20 +#ifndef node_distance #define node_distance(from,to) ((from) == (to) ? LOCAL_DISTANCE : REMOTE_DISTANCE) #endif #ifndef RECLAIM_DISTANCE @@ -98,7 +98,7 @@ .cache_nice_tries = 0, \ .busy_idx = 0, \ .idle_idx = 0, \ - .newidle_idx = 1, \ + .newidle_idx = 0, \ .wake_idx = 0, \ .forkexec_idx = 0, \ .flags = SD_LOAD_BALANCE \ @@ -128,14 +128,15 @@ .imbalance_pct = 125, \ .cache_nice_tries = 1, \ .busy_idx = 2, \ - .idle_idx = 1, \ - .newidle_idx = 2, \ + .idle_idx = 0, \ + .newidle_idx = 0, \ .wake_idx = 1, \ .forkexec_idx = 1, \ .flags = SD_LOAD_BALANCE \ | SD_BALANCE_NEWIDLE \ | SD_BALANCE_EXEC \ | SD_WAKE_AFFINE \ + | SD_WAKE_IDLE \ | SD_SHARE_PKG_RESOURCES\ | BALANCE_FOR_MC_POWER, \ .last_balance = jiffies, \ @@ -158,14 +159,15 @@ .imbalance_pct = 125, \ .cache_nice_tries = 1, \ .busy_idx = 2, \ - .idle_idx = 1, \ - .newidle_idx = 2, \ + .idle_idx = 0, \ + .newidle_idx = 0, \ .wake_idx = 1, \ .forkexec_idx = 1, \ .flags = SD_LOAD_BALANCE \ | SD_BALANCE_NEWIDLE \ | SD_BALANCE_EXEC \ | SD_WAKE_AFFINE \ + | SD_WAKE_IDLE \ | BALANCE_FOR_PKG_POWER,\ .last_balance = jiffies, \ .balance_interval = 1, \ diff --git a/include/linux/udp.h b/include/linux/udp.h index 6de445c31a6..8ec703f462d 100644 --- a/include/linux/udp.h +++ b/include/linux/udp.h @@ -42,6 +42,7 @@ static inline struct udphdr *udp_hdr(const struct sk_buff *skb) /* UDP encapsulation types */ #define UDP_ENCAP_ESPINUDP_NON_IKE 1 /* draft-ietf-ipsec-nat-t-ike-00/01 */ #define UDP_ENCAP_ESPINUDP 2 /* draft-ietf-ipsec-udp-encaps-06 */ +#define UDP_ENCAP_L2TPINUDP 3 /* rfc2661 */ #ifdef __KERNEL__ #include <linux/types.h> @@ -70,6 +71,11 @@ struct udp_sock { #define UDPLITE_SEND_CC 0x2 /* set via udplite setsockopt */ #define UDPLITE_RECV_CC 0x4 /* set via udplite setsocktopt */ __u8 pcflag; /* marks socket as UDP-Lite if > 0 */ + __u8 unused[3]; + /* + * For encapsulation sockets. + */ + int (*encap_rcv)(struct sock *sk, struct sk_buff *skb); }; static inline struct udp_sock *udp_sk(const struct sock *sk) diff --git a/include/linux/usb.h b/include/linux/usb.h index 94bd38a6d94..7a60946df3b 100644 --- a/include/linux/usb.h +++ b/include/linux/usb.h @@ -146,6 +146,10 @@ struct usb_interface { * active alternate setting */ unsigned num_altsetting; /* number of alternate settings */ + /* If there is an interface association descriptor then it will list + * the associated interfaces */ + struct usb_interface_assoc_descriptor *intf_assoc; + int minor; /* minor number this interface is * bound to */ enum usb_interface_condition condition; /* state of binding */ @@ -175,6 +179,7 @@ void usb_put_intf(struct usb_interface *intf); /* this maximum is arbitrary */ #define USB_MAXINTERFACES 32 +#define USB_MAXIADS USB_MAXINTERFACES/2 /** * struct usb_interface_cache - long-term representation of a device interface @@ -245,6 +250,11 @@ struct usb_host_config { struct usb_config_descriptor desc; char *string; /* iConfiguration string, if present */ + + /* List of any Interface Association Descriptors in this + * configuration. */ + struct usb_interface_assoc_descriptor *intf_assoc[USB_MAXIADS]; + /* the interfaces associated with this configuration, * stored in no particular order */ struct usb_interface *interface[USB_MAXINTERFACES]; @@ -403,6 +413,8 @@ struct usb_device { unsigned auto_pm:1; /* autosuspend/resume in progress */ unsigned do_remote_wakeup:1; /* remote wakeup should be enabled */ + unsigned reset_resume:1; /* needs reset instead of resume */ + unsigned persist_enabled:1; /* USB_PERSIST enabled for this dev */ unsigned autosuspend_disabled:1; /* autosuspend and autoresume */ unsigned autoresume_disabled:1; /* disabled by the user */ #endif @@ -729,6 +741,22 @@ static inline int usb_endpoint_is_isoc_out(const struct usb_endpoint_descriptor .bcdDevice_lo = (lo), .bcdDevice_hi = (hi) /** + * USB_DEVICE_INTERFACE_PROTOCOL - macro used to describe a usb + * device with a specific interface protocol + * @vend: the 16 bit USB Vendor ID + * @prod: the 16 bit USB Product ID + * @pr: bInterfaceProtocol value + * + * This macro is used to create a struct usb_device_id that matches a + * specific interface protocol of devices. + */ +#define USB_DEVICE_INTERFACE_PROTOCOL(vend,prod,pr) \ + .match_flags = USB_DEVICE_ID_MATCH_DEVICE | USB_DEVICE_ID_MATCH_INT_PROTOCOL, \ + .idVendor = (vend), \ + .idProduct = (prod), \ + .bInterfaceProtocol = (pr) + +/** * USB_DEVICE_INFO - macro used to describe a class of usb devices * @cl: bDeviceClass value * @sc: bDeviceSubClass value @@ -754,6 +782,28 @@ static inline int usb_endpoint_is_isoc_out(const struct usb_endpoint_descriptor .match_flags = USB_DEVICE_ID_MATCH_INT_INFO, .bInterfaceClass = (cl), \ .bInterfaceSubClass = (sc), .bInterfaceProtocol = (pr) +/** + * USB_DEVICE_AND_INTERFACE_INFO - macro used to describe a specific usb device + * with a class of usb interfaces + * @vend: the 16 bit USB Vendor ID + * @prod: the 16 bit USB Product ID + * @cl: bInterfaceClass value + * @sc: bInterfaceSubClass value + * @pr: bInterfaceProtocol value + * + * This macro is used to create a struct usb_device_id that matches a + * specific device with a specific class of interfaces. + * + * This is especially useful when explicitly matching devices that have + * vendor specific bDeviceClass values, but standards-compliant interfaces. + */ +#define USB_DEVICE_AND_INTERFACE_INFO(vend,prod,cl,sc,pr) \ + .match_flags = USB_DEVICE_ID_MATCH_INT_INFO \ + | USB_DEVICE_ID_MATCH_DEVICE, \ + .idVendor = (vend), .idProduct = (prod), \ + .bInterfaceClass = (cl), \ + .bInterfaceSubClass = (sc), .bInterfaceProtocol = (pr) + /* ----------------------------------------------------------------------- */ /* Stuff for dynamic usb ids */ @@ -800,10 +850,15 @@ struct usbdrv_wrap { * do (or don't) show up otherwise in the filesystem. * @suspend: Called when the device is going to be suspended by the system. * @resume: Called when the device is being resumed by the system. + * @reset_resume: Called when the suspended device has been reset instead + * of being resumed. * @pre_reset: Called by usb_reset_composite_device() when the device * is about to be reset. * @post_reset: Called by usb_reset_composite_device() after the device - * has been reset. + * has been reset, or in lieu of @resume following a reset-resume + * (i.e., the device is reset instead of being resumed, as might + * happen if power was lost). The second argument tells which is + * the reason. * @id_table: USB drivers use ID table to support hotplugging. * Export this with MODULE_DEVICE_TABLE(usb,...). This must be set * or your driver's probe function will never get called. @@ -843,9 +898,10 @@ struct usb_driver { int (*suspend) (struct usb_interface *intf, pm_message_t message); int (*resume) (struct usb_interface *intf); + int (*reset_resume)(struct usb_interface *intf); - void (*pre_reset) (struct usb_interface *intf); - void (*post_reset) (struct usb_interface *intf); + int (*pre_reset)(struct usb_interface *intf); + int (*post_reset)(struct usb_interface *intf); const struct usb_device_id *id_table; @@ -948,6 +1004,7 @@ extern int usb_disabled(void); #define URB_ZERO_PACKET 0x0040 /* Finish bulk OUT with short packet */ #define URB_NO_INTERRUPT 0x0080 /* HINT: no non-error interrupt * needed */ +#define URB_FREE_BUFFER 0x0100 /* Free transfer buffer with the URB */ struct usb_iso_packet_descriptor { unsigned int offset; @@ -958,11 +1015,26 @@ struct usb_iso_packet_descriptor { struct urb; +struct usb_anchor { + struct list_head urb_list; + wait_queue_head_t wait; + spinlock_t lock; +}; + +static inline void init_usb_anchor(struct usb_anchor *anchor) +{ + INIT_LIST_HEAD(&anchor->urb_list); + init_waitqueue_head(&anchor->wait); + spin_lock_init(&anchor->lock); +} + typedef void (*usb_complete_t)(struct urb *); /** * struct urb - USB Request Block * @urb_list: For use by current owner of the URB. + * @anchor_list: membership in the list of an anchor + * @anchor: to anchor URBs to a common mooring * @pipe: Holds endpoint number, direction, type, and more. * Create these values with the eight macros available; * usb_{snd,rcv}TYPEpipe(dev,endpoint), where the TYPE is "ctrl" @@ -1135,6 +1207,8 @@ struct urb /* public: documented fields in the urb that can be used by drivers */ struct list_head urb_list; /* list head for use by the urb's * current owner */ + struct list_head anchor_list; /* the URB may be anchored by the driver */ + struct usb_anchor *anchor; struct usb_device *dev; /* (in) pointer to associated device */ unsigned int pipe; /* (in) pipe information */ int status; /* (return) non-ISO status */ @@ -1270,6 +1344,11 @@ extern struct urb *usb_get_urb(struct urb *urb); extern int usb_submit_urb(struct urb *urb, gfp_t mem_flags); extern int usb_unlink_urb(struct urb *urb); extern void usb_kill_urb(struct urb *urb); +extern void usb_kill_anchored_urbs(struct usb_anchor *anchor); +extern void usb_anchor_urb(struct urb *urb, struct usb_anchor *anchor); +extern void usb_unanchor_urb(struct urb *urb); +extern int usb_wait_anchor_empty_timeout(struct usb_anchor *anchor, + unsigned int timeout); void *usb_buffer_alloc (struct usb_device *dev, size_t size, gfp_t mem_flags, dma_addr_t *dma); diff --git a/include/linux/usb/Kbuild b/include/linux/usb/Kbuild index 43f160cfe00..6ce42bf9f74 100644 --- a/include/linux/usb/Kbuild +++ b/include/linux/usb/Kbuild @@ -1,5 +1,6 @@ unifdef-y += audio.h unifdef-y += cdc.h unifdef-y += ch9.h +unifdef-y += gadgetfs.h unifdef-y += midi.h diff --git a/include/linux/usb_gadgetfs.h b/include/linux/usb/gadgetfs.h index 8086d5a9b94..e8654c33872 100644 --- a/include/linux/usb_gadgetfs.h +++ b/include/linux/usb/gadgetfs.h @@ -1,3 +1,5 @@ +#ifndef __LINUX_USB_GADGETFS_H +#define __LINUX_USB_GADGETFS_H #include <asm/types.h> #include <asm/ioctl.h> @@ -7,11 +9,12 @@ /* * Filesystem based user-mode API to USB Gadget controller hardware * - * Almost everything can be done with only read and write operations, + * Other than ep0 operations, most things are done by read() and write() * on endpoint files found in one directory. They are configured by * writing descriptors, and then may be used for normal stream style * i/o requests. When ep0 is configured, the device can enumerate; - * when it's closed, the device disconnects from usb. + * when it's closed, the device disconnects from usb. Operations on + * ep0 require ioctl() operations. * * Configuration and device descriptors get written to /dev/gadget/$CHIP, * which may then be used to read usb_gadgetfs_event structs. The driver @@ -21,9 +24,9 @@ */ /* - * Events are delivered on the ep0 file descriptor, if the user mode driver + * Events are delivered on the ep0 file descriptor, when the user mode driver * reads from this file descriptor after writing the descriptors. Don't - * stop polling this descriptor, if you write that kind of driver. + * stop polling this descriptor. */ enum usb_gadgetfs_event_type { @@ -36,8 +39,10 @@ enum usb_gadgetfs_event_type { // and likely more ! }; +/* NOTE: this structure must stay the same size and layout on + * both 32-bit and 64-bit kernels. + */ struct usb_gadgetfs_event { - enum usb_gadgetfs_event_type type; union { // NOP, DISCONNECT, SUSPEND: nothing // ... some hardware can't report disconnection @@ -46,19 +51,20 @@ struct usb_gadgetfs_event { enum usb_device_speed speed; // SETUP: packet; DATA phase i/o precedes next event - // (setup.bmRequestType & USB_DIR_IN) flags direction + // (setup.bmRequestType & USB_DIR_IN) flags direction // ... includes SET_CONFIGURATION, SET_INTERFACE struct usb_ctrlrequest setup; } u; + enum usb_gadgetfs_event_type type; }; /* endpoint ioctls */ /* IN transfers may be reported to the gadget driver as complete - * when the fifo is loaded, before the host reads the data; + * when the fifo is loaded, before the host reads the data; * OUT transfers may be reported to the host's "client" driver as - * complete when they're sitting in the FIFO unread. + * complete when they're sitting in the FIFO unread. * THIS returns how many bytes are "unclaimed" in the endpoint fifo * (needed for precise fault handling, when the hardware allows it) */ @@ -72,4 +78,4 @@ struct usb_gadgetfs_event { */ #define GADGETFS_CLEAR_HALT _IO('g',3) - +#endif /* __LINUX_USB_GADGETFS_H */ diff --git a/include/linux/usb/quirks.h b/include/linux/usb/quirks.h index 6bac8faacbc..8da374caf58 100644 --- a/include/linux/usb/quirks.h +++ b/include/linux/usb/quirks.h @@ -9,3 +9,6 @@ /* string descriptors must not be fetched using a 255-byte read */ #define USB_QUIRK_STRING_FETCH_255 0x00000002 + +/* device can't resume correctly so reset it instead */ +#define USB_QUIRK_RESET_RESUME 0x00000004 diff --git a/include/linux/usb/serial.h b/include/linux/usb/serial.h index 32acbae28d2..e8b8928232c 100644 --- a/include/linux/usb/serial.h +++ b/include/linux/usb/serial.h @@ -221,6 +221,9 @@ struct usb_serial_driver { int (*port_probe) (struct usb_serial_port *port); int (*port_remove) (struct usb_serial_port *port); + int (*suspend) (struct usb_serial *serial, pm_message_t message); + int (*resume) (struct usb_serial *serial); + /* serial function calls */ int (*open) (struct usb_serial_port *port, struct file * filp); void (*close) (struct usb_serial_port *port, struct file * filp); @@ -249,6 +252,9 @@ extern void usb_serial_port_softint(struct usb_serial_port *port); extern int usb_serial_probe(struct usb_interface *iface, const struct usb_device_id *id); extern void usb_serial_disconnect(struct usb_interface *iface); +extern int usb_serial_suspend(struct usb_interface *intf, pm_message_t message); +extern int usb_serial_resume(struct usb_interface *intf); + extern int ezusb_writememory (struct usb_serial *serial, int address, unsigned char *data, int length, __u8 bRequest); extern int ezusb_set_reset (struct usb_serial *serial, unsigned char reset_bit); @@ -269,6 +275,7 @@ extern void usb_serial_put(struct usb_serial *serial); extern int usb_serial_generic_open (struct usb_serial_port *port, struct file *filp); extern int usb_serial_generic_write (struct usb_serial_port *port, const unsigned char *buf, int count); extern void usb_serial_generic_close (struct usb_serial_port *port, struct file *filp); +extern int usb_serial_generic_resume (struct usb_serial *serial); extern int usb_serial_generic_write_room (struct usb_serial_port *port); extern int usb_serial_generic_chars_in_buffer (struct usb_serial_port *port); extern void usb_serial_generic_read_bulk_callback (struct urb *urb); diff --git a/include/linux/usb_gadget.h b/include/linux/usb_gadget.h index e17186dbcdc..4f59b2aa8a9 100644 --- a/include/linux/usb_gadget.h +++ b/include/linux/usb_gadget.h @@ -110,13 +110,6 @@ struct usb_ep_ops { gfp_t gfp_flags); void (*free_request) (struct usb_ep *ep, struct usb_request *req); - void *(*alloc_buffer) (struct usb_ep *ep, unsigned bytes, - dma_addr_t *dma, gfp_t gfp_flags); - void (*free_buffer) (struct usb_ep *ep, void *buf, dma_addr_t dma, - unsigned bytes); - // NOTE: on 2.6, drivers may also use dma_map() and - // dma_sync_single_*() to directly manage dma overhead. - int (*queue) (struct usb_ep *ep, struct usb_request *req, gfp_t gfp_flags); int (*dequeue) (struct usb_ep *ep, struct usb_request *req); @@ -235,47 +228,6 @@ usb_ep_free_request (struct usb_ep *ep, struct usb_request *req) } /** - * usb_ep_alloc_buffer - allocate an I/O buffer - * @ep:the endpoint associated with the buffer - * @len:length of the desired buffer - * @dma:pointer to the buffer's DMA address; must be valid - * @gfp_flags:GFP_* flags to use - * - * Returns a new buffer, or null if one could not be allocated. - * The buffer is suitably aligned for dma, if that endpoint uses DMA, - * and the caller won't have to care about dma-inconsistency - * or any hidden "bounce buffer" mechanism. No additional per-request - * DMA mapping will be required for such buffers. - * Free it later with usb_ep_free_buffer(). - * - * You don't need to use this call to allocate I/O buffers unless you - * want to make sure drivers don't incur costs for such "bounce buffer" - * copies or per-request DMA mappings. - */ -static inline void * -usb_ep_alloc_buffer (struct usb_ep *ep, unsigned len, dma_addr_t *dma, - gfp_t gfp_flags) -{ - return ep->ops->alloc_buffer (ep, len, dma, gfp_flags); -} - -/** - * usb_ep_free_buffer - frees an i/o buffer - * @ep:the endpoint associated with the buffer - * @buf:CPU view address of the buffer - * @dma:the buffer's DMA address - * @len:length of the buffer - * - * reverses the effect of usb_ep_alloc_buffer(). - * caller guarantees the buffer will no longer be accessed - */ -static inline void -usb_ep_free_buffer (struct usb_ep *ep, void *buf, dma_addr_t dma, unsigned len) -{ - ep->ops->free_buffer (ep, buf, dma, len); -} - -/** * usb_ep_queue - queues (submits) an I/O request to an endpoint. * @ep:the endpoint associated with the request * @req:the request being submitted diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h index e7560389079..d16a2b57dc8 100644 --- a/include/linux/videodev2.h +++ b/include/linux/videodev2.h @@ -243,8 +243,7 @@ struct v4l2_capability #define V4L2_CAP_SLICED_VBI_CAPTURE 0x00000040 /* Is a sliced VBI capture device */ #define V4L2_CAP_SLICED_VBI_OUTPUT 0x00000080 /* Is a sliced VBI output device */ #define V4L2_CAP_RDS_CAPTURE 0x00000100 /* RDS data capture */ -#define V4L2_CAP_VIDEO_OUTPUT_POS 0x00000200 /* Video output can have x,y coords */ -#define V4L2_CAP_VIDEO_OUTPUT_OVERLAY 0x00000400 /* Can do video output overlay */ +#define V4L2_CAP_VIDEO_OUTPUT_OVERLAY 0x00000200 /* Can do video output overlay */ #define V4L2_CAP_TUNER 0x00010000 /* has a tuner */ #define V4L2_CAP_AUDIO 0x00020000 /* has audio support */ @@ -616,12 +615,16 @@ struct v4l2_framebuffer #define V4L2_FBUF_CAP_BITMAP_CLIPPING 0x0008 #define V4L2_FBUF_CAP_LOCAL_ALPHA 0x0010 #define V4L2_FBUF_CAP_GLOBAL_ALPHA 0x0020 +#define V4L2_FBUF_CAP_LOCAL_INV_ALPHA 0x0040 +#define V4L2_FBUF_CAP_GLOBAL_INV_ALPHA 0x0080 /* Flags for the 'flags' field. */ #define V4L2_FBUF_FLAG_PRIMARY 0x0001 #define V4L2_FBUF_FLAG_OVERLAY 0x0002 #define V4L2_FBUF_FLAG_CHROMAKEY 0x0004 #define V4L2_FBUF_FLAG_LOCAL_ALPHA 0x0008 #define V4L2_FBUF_FLAG_GLOBAL_ALPHA 0x0010 +#define V4L2_FBUF_FLAG_LOCAL_INV_ALPHA 0x0020 +#define V4L2_FBUF_FLAG_GLOBAL_INV_ALPHA 0x0040 struct v4l2_clip { diff --git a/include/linux/wait.h b/include/linux/wait.h index e820d00e138..0e686280450 100644 --- a/include/linux/wait.h +++ b/include/linux/wait.h @@ -366,15 +366,15 @@ static inline void remove_wait_queue_locked(wait_queue_head_t *q, /* * These are the old interfaces to sleep waiting for an event. - * They are racy. DO NOT use them, use the wait_event* interfaces above. - * We plan to remove these interfaces during 2.7. + * They are racy. DO NOT use them, use the wait_event* interfaces above. + * We plan to remove these interfaces. */ -extern void FASTCALL(sleep_on(wait_queue_head_t *q)); -extern long FASTCALL(sleep_on_timeout(wait_queue_head_t *q, - signed long timeout)); -extern void FASTCALL(interruptible_sleep_on(wait_queue_head_t *q)); -extern long FASTCALL(interruptible_sleep_on_timeout(wait_queue_head_t *q, - signed long timeout)); +extern void sleep_on(wait_queue_head_t *q); +extern long sleep_on_timeout(wait_queue_head_t *q, + signed long timeout); +extern void interruptible_sleep_on(wait_queue_head_t *q); +extern long interruptible_sleep_on_timeout(wait_queue_head_t *q, + signed long timeout); /* * Waitqueues which are removed from the waitqueue_head at wakeup time diff --git a/include/net/9p/9p.h b/include/net/9p/9p.h new file mode 100644 index 00000000000..88884d39f28 --- /dev/null +++ b/include/net/9p/9p.h @@ -0,0 +1,417 @@ +/* + * include/net/9p/9p.h + * + * 9P protocol definitions. + * + * Copyright (C) 2005 by Latchesar Ionkov <lucho@ionkov.net> + * Copyright (C) 2004 by Eric Van Hensbergen <ericvh@gmail.com> + * Copyright (C) 2002 by Ron Minnich <rminnich@lanl.gov> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to: + * Free Software Foundation + * 51 Franklin Street, Fifth Floor + * Boston, MA 02111-1301 USA + * + */ + +#ifndef NET_9P_H +#define NET_9P_H + +#ifdef CONFIG_NET_9P_DEBUG + +#define P9_DEBUG_ERROR (1<<0) +#define P9_DEBUG_9P (1<<2) +#define P9_DEBUG_VFS (1<<3) +#define P9_DEBUG_CONV (1<<4) +#define P9_DEBUG_MUX (1<<5) +#define P9_DEBUG_TRANS (1<<6) +#define P9_DEBUG_SLABS (1<<7) +#define P9_DEBUG_FCALL (1<<8) + +extern unsigned int p9_debug_level; + +#define P9_DPRINTK(level, format, arg...) \ +do { \ + if ((p9_debug_level & level) == level) \ + printk(KERN_NOTICE "-- %s (%d): " \ + format , __FUNCTION__, current->pid , ## arg); \ +} while (0) + +#define PRINT_FCALL_ERROR(s, fcall) P9_DPRINTK(P9_DEBUG_ERROR, \ + "%s: %.*s\n", s, fcall?fcall->params.rerror.error.len:0, \ + fcall?fcall->params.rerror.error.str:""); + +#else +#define P9_DPRINTK(level, format, arg...) do { } while (0) +#define PRINT_FCALL_ERROR(s, fcall) do { } while (0) +#endif + +#define P9_EPRINTK(level, format, arg...) \ +do { \ + printk(level "9p: %s (%d): " \ + format , __FUNCTION__, current->pid , ## arg); \ +} while (0) + + +/* Message Types */ +enum { + P9_TVERSION = 100, + P9_RVERSION, + P9_TAUTH = 102, + P9_RAUTH, + P9_TATTACH = 104, + P9_RATTACH, + P9_TERROR = 106, + P9_RERROR, + P9_TFLUSH = 108, + P9_RFLUSH, + P9_TWALK = 110, + P9_RWALK, + P9_TOPEN = 112, + P9_ROPEN, + P9_TCREATE = 114, + P9_RCREATE, + P9_TREAD = 116, + P9_RREAD, + P9_TWRITE = 118, + P9_RWRITE, + P9_TCLUNK = 120, + P9_RCLUNK, + P9_TREMOVE = 122, + P9_RREMOVE, + P9_TSTAT = 124, + P9_RSTAT, + P9_TWSTAT = 126, + P9_RWSTAT, +}; + +/* open modes */ +enum { + P9_OREAD = 0x00, + P9_OWRITE = 0x01, + P9_ORDWR = 0x02, + P9_OEXEC = 0x03, + P9_OEXCL = 0x04, + P9_OTRUNC = 0x10, + P9_OREXEC = 0x20, + P9_ORCLOSE = 0x40, + P9_OAPPEND = 0x80, +}; + +/* permissions */ +enum { + P9_DMDIR = 0x80000000, + P9_DMAPPEND = 0x40000000, + P9_DMEXCL = 0x20000000, + P9_DMMOUNT = 0x10000000, + P9_DMAUTH = 0x08000000, + P9_DMTMP = 0x04000000, + P9_DMSYMLINK = 0x02000000, + P9_DMLINK = 0x01000000, + /* 9P2000.u extensions */ + P9_DMDEVICE = 0x00800000, + P9_DMNAMEDPIPE = 0x00200000, + P9_DMSOCKET = 0x00100000, + P9_DMSETUID = 0x00080000, + P9_DMSETGID = 0x00040000, +}; + +/* qid.types */ +enum { + P9_QTDIR = 0x80, + P9_QTAPPEND = 0x40, + P9_QTEXCL = 0x20, + P9_QTMOUNT = 0x10, + P9_QTAUTH = 0x08, + P9_QTTMP = 0x04, + P9_QTSYMLINK = 0x02, + P9_QTLINK = 0x01, + P9_QTFILE = 0x00, +}; + +#define P9_NOTAG (u16)(~0) +#define P9_NOFID (u32)(~0) +#define P9_MAXWELEM 16 + +/* ample room for Twrite/Rread header */ +#define P9_IOHDRSZ 24 + +struct p9_str { + u16 len; + char *str; +}; + +/* qids are the unique ID for a file (like an inode */ +struct p9_qid { + u8 type; + u32 version; + u64 path; +}; + +/* Plan 9 file metadata (stat) structure */ +struct p9_stat { + u16 size; + u16 type; + u32 dev; + struct p9_qid qid; + u32 mode; + u32 atime; + u32 mtime; + u64 length; + struct p9_str name; + struct p9_str uid; + struct p9_str gid; + struct p9_str muid; + struct p9_str extension; /* 9p2000.u extensions */ + u32 n_uid; /* 9p2000.u extensions */ + u32 n_gid; /* 9p2000.u extensions */ + u32 n_muid; /* 9p2000.u extensions */ +}; + +/* file metadata (stat) structure used to create Twstat message + The is similar to p9_stat, but the strings don't point to + the same memory block and should be freed separately +*/ +struct p9_wstat { + u16 size; + u16 type; + u32 dev; + struct p9_qid qid; + u32 mode; + u32 atime; + u32 mtime; + u64 length; + char *name; + char *uid; + char *gid; + char *muid; + char *extension; /* 9p2000.u extensions */ + u32 n_uid; /* 9p2000.u extensions */ + u32 n_gid; /* 9p2000.u extensions */ + u32 n_muid; /* 9p2000.u extensions */ +}; + +/* Structures for Protocol Operations */ +struct p9_tversion { + u32 msize; + struct p9_str version; +}; + +struct p9_rversion { + u32 msize; + struct p9_str version; +}; + +struct p9_tauth { + u32 afid; + struct p9_str uname; + struct p9_str aname; +}; + +struct p9_rauth { + struct p9_qid qid; +}; + +struct p9_rerror { + struct p9_str error; + u32 errno; /* 9p2000.u extension */ +}; + +struct p9_tflush { + u16 oldtag; +}; + +struct p9_rflush { +}; + +struct p9_tattach { + u32 fid; + u32 afid; + struct p9_str uname; + struct p9_str aname; +}; + +struct p9_rattach { + struct p9_qid qid; +}; + +struct p9_twalk { + u32 fid; + u32 newfid; + u16 nwname; + struct p9_str wnames[16]; +}; + +struct p9_rwalk { + u16 nwqid; + struct p9_qid wqids[16]; +}; + +struct p9_topen { + u32 fid; + u8 mode; +}; + +struct p9_ropen { + struct p9_qid qid; + u32 iounit; +}; + +struct p9_tcreate { + u32 fid; + struct p9_str name; + u32 perm; + u8 mode; + struct p9_str extension; +}; + +struct p9_rcreate { + struct p9_qid qid; + u32 iounit; +}; + +struct p9_tread { + u32 fid; + u64 offset; + u32 count; +}; + +struct p9_rread { + u32 count; + u8 *data; +}; + +struct p9_twrite { + u32 fid; + u64 offset; + u32 count; + u8 *data; +}; + +struct p9_rwrite { + u32 count; +}; + +struct p9_tclunk { + u32 fid; +}; + +struct p9_rclunk { +}; + +struct p9_tremove { + u32 fid; +}; + +struct p9_rremove { +}; + +struct p9_tstat { + u32 fid; +}; + +struct p9_rstat { + struct p9_stat stat; +}; + +struct p9_twstat { + u32 fid; + struct p9_stat stat; +}; + +struct p9_rwstat { +}; + +/* + * fcall is the primary packet structure + * + */ + +struct p9_fcall { + u32 size; + u8 id; + u16 tag; + void *sdata; + + union { + struct p9_tversion tversion; + struct p9_rversion rversion; + struct p9_tauth tauth; + struct p9_rauth rauth; + struct p9_rerror rerror; + struct p9_tflush tflush; + struct p9_rflush rflush; + struct p9_tattach tattach; + struct p9_rattach rattach; + struct p9_twalk twalk; + struct p9_rwalk rwalk; + struct p9_topen topen; + struct p9_ropen ropen; + struct p9_tcreate tcreate; + struct p9_rcreate rcreate; + struct p9_tread tread; + struct p9_rread rread; + struct p9_twrite twrite; + struct p9_rwrite rwrite; + struct p9_tclunk tclunk; + struct p9_rclunk rclunk; + struct p9_tremove tremove; + struct p9_rremove rremove; + struct p9_tstat tstat; + struct p9_rstat rstat; + struct p9_twstat twstat; + struct p9_rwstat rwstat; + } params; +}; + +struct p9_idpool; + +int p9_deserialize_stat(void *buf, u32 buflen, struct p9_stat *stat, + int dotu); +int p9_deserialize_fcall(void *buf, u32 buflen, struct p9_fcall *fc, int dotu); +void p9_set_tag(struct p9_fcall *fc, u16 tag); +struct p9_fcall *p9_create_tversion(u32 msize, char *version); +struct p9_fcall *p9_create_tattach(u32 fid, u32 afid, char *uname, + char *aname); +struct p9_fcall *p9_create_tauth(u32 afid, char *uname, char *aname); +struct p9_fcall *p9_create_tflush(u16 oldtag); +struct p9_fcall *p9_create_twalk(u32 fid, u32 newfid, u16 nwname, + char **wnames); +struct p9_fcall *p9_create_topen(u32 fid, u8 mode); +struct p9_fcall *p9_create_tcreate(u32 fid, char *name, u32 perm, u8 mode, + char *extension, int dotu); +struct p9_fcall *p9_create_tread(u32 fid, u64 offset, u32 count); +struct p9_fcall *p9_create_twrite(u32 fid, u64 offset, u32 count, + const char *data); +struct p9_fcall *p9_create_twrite_u(u32 fid, u64 offset, u32 count, + const char __user *data); +struct p9_fcall *p9_create_tclunk(u32 fid); +struct p9_fcall *p9_create_tremove(u32 fid); +struct p9_fcall *p9_create_tstat(u32 fid); +struct p9_fcall *p9_create_twstat(u32 fid, struct p9_wstat *wstat, + int dotu); + +int p9_printfcall(char *buf, int buflen, struct p9_fcall *fc, int dotu); +int p9_errstr2errno(char *errstr, int len); + +struct p9_idpool *p9_idpool_create(void); +void p9_idpool_destroy(struct p9_idpool *); +int p9_idpool_get(struct p9_idpool *p); +void p9_idpool_put(int id, struct p9_idpool *p); +int p9_idpool_check(int id, struct p9_idpool *p); + +int p9_error_init(void); +int p9_errstr2errno(char *, int); +int __init p9_sysctl_register(void); +void __exit p9_sysctl_unregister(void); +#endif /* NET_9P_H */ diff --git a/include/net/9p/client.h b/include/net/9p/client.h new file mode 100644 index 00000000000..d65ed7c6906 --- /dev/null +++ b/include/net/9p/client.h @@ -0,0 +1,80 @@ +/* + * include/net/9p/client.h + * + * 9P Client Definitions + * + * Copyright (C) 2007 by Latchesar Ionkov <lucho@ionkov.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to: + * Free Software Foundation + * 51 Franklin Street, Fifth Floor + * Boston, MA 02111-1301 USA + * + */ + +#ifndef NET_9P_CLIENT_H +#define NET_9P_CLIENT_H + +struct p9_client { + spinlock_t lock; /* protect client structure */ + int msize; + unsigned char dotu; + struct p9_transport *trans; + struct p9_conn *conn; + + struct p9_idpool *fidpool; + struct list_head fidlist; +}; + +struct p9_fid { + struct p9_client *clnt; + u32 fid; + int mode; + struct p9_qid qid; + u32 iounit; + uid_t uid; + void *aux; + + int rdir_fpos; + int rdir_pos; + struct p9_fcall *rdir_fcall; + struct list_head flist; + struct list_head dlist; /* list of all fids attached to a dentry */ +}; + +struct p9_client *p9_client_create(struct p9_transport *trans, int msize, + int dotu); +void p9_client_destroy(struct p9_client *clnt); +void p9_client_disconnect(struct p9_client *clnt); +struct p9_fid *p9_client_attach(struct p9_client *clnt, struct p9_fid *afid, + char *uname, char *aname); +struct p9_fid *p9_client_auth(struct p9_client *clnt, char *uname, char *aname); +struct p9_fid *p9_client_walk(struct p9_fid *oldfid, int nwname, char **wnames, + int clone); +int p9_client_open(struct p9_fid *fid, int mode); +int p9_client_fcreate(struct p9_fid *fid, char *name, u32 perm, int mode, + char *extension); +int p9_client_clunk(struct p9_fid *fid); +int p9_client_remove(struct p9_fid *fid); +int p9_client_read(struct p9_fid *fid, char *data, u64 offset, u32 count); +int p9_client_readn(struct p9_fid *fid, char *data, u64 offset, u32 count); +int p9_client_write(struct p9_fid *fid, char *data, u64 offset, u32 count); +int p9_client_uread(struct p9_fid *fid, char __user *data, u64 offset, + u32 count); +int p9_client_uwrite(struct p9_fid *fid, const char __user *data, u64 offset, + u32 count); +struct p9_stat *p9_client_stat(struct p9_fid *fid); +int p9_client_wstat(struct p9_fid *fid, struct p9_wstat *wst); +struct p9_stat *p9_client_dirread(struct p9_fid *fid, u64 offset); + +#endif /* NET_9P_CLIENT_H */ diff --git a/include/net/9p/conn.h b/include/net/9p/conn.h new file mode 100644 index 00000000000..583b6a2cb3d --- /dev/null +++ b/include/net/9p/conn.h @@ -0,0 +1,57 @@ +/* + * include/net/9p/conn.h + * + * Connection Definitions + * + * Copyright (C) 2005 by Latchesar Ionkov <lucho@ionkov.net> + * Copyright (C) 2004 by Eric Van Hensbergen <ericvh@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to: + * Free Software Foundation + * 51 Franklin Street, Fifth Floor + * Boston, MA 02111-1301 USA + * + */ + +#ifndef NET_9P_CONN_H +#define NET_9P_CONN_H + +#undef P9_NONBLOCK + +struct p9_conn; +struct p9_req; + +/** + * p9_mux_req_callback - callback function that is called when the + * response of a request is received. The callback is called from + * a workqueue and shouldn't block. + * + * @req - request + * @a - the pointer that was specified when the request was send to be + * passed to the callback + */ +typedef void (*p9_conn_req_callback)(struct p9_req *req, void *a); + +struct p9_conn *p9_conn_create(struct p9_transport *trans, int msize, + unsigned char *dotu); +void p9_conn_destroy(struct p9_conn *); +int p9_conn_rpc(struct p9_conn *m, struct p9_fcall *tc, struct p9_fcall **rc); + +#ifdef P9_NONBLOCK +int p9_conn_rpcnb(struct p9_conn *m, struct p9_fcall *tc, + p9_conn_req_callback cb, void *a); +#endif /* P9_NONBLOCK */ + +void p9_conn_cancel(struct p9_conn *m, int err); + +#endif /* NET_9P_CONN_H */ diff --git a/include/net/9p/transport.h b/include/net/9p/transport.h new file mode 100644 index 00000000000..462d42279fb --- /dev/null +++ b/include/net/9p/transport.h @@ -0,0 +1,49 @@ +/* + * include/net/9p/transport.h + * + * Transport Definition + * + * Copyright (C) 2005 by Latchesar Ionkov <lucho@ionkov.net> + * Copyright (C) 2004 by Eric Van Hensbergen <ericvh@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to: + * Free Software Foundation + * 51 Franklin Street, Fifth Floor + * Boston, MA 02111-1301 USA + * + */ + +#ifndef NET_9P_TRANSPORT_H +#define NET_9P_TRANSPORT_H + +enum p9_transport_status { + Connected, + Disconnected, + Hung, +}; + +struct p9_transport { + enum p9_transport_status status; + void *priv; + + int (*write) (struct p9_transport *, void *, int); + int (*read) (struct p9_transport *, void *, int); + void (*close) (struct p9_transport *); + unsigned int (*poll)(struct p9_transport *, struct poll_table_struct *); +}; + +struct p9_transport *p9_trans_create_tcp(const char *addr, int port); +struct p9_transport *p9_trans_create_unix(const char *addr); +struct p9_transport *p9_trans_create_fd(int rfd, int wfd); + +#endif /* NET_9P_TRANSPORT_H */ diff --git a/include/net/act_api.h b/include/net/act_api.h index 8b06c2f3657..68b4eaf7719 100644 --- a/include/net/act_api.h +++ b/include/net/act_api.h @@ -19,7 +19,6 @@ struct tcf_common { struct gnet_stats_basic tcfc_bstats; struct gnet_stats_queue tcfc_qstats; struct gnet_stats_rate_est tcfc_rate_est; - spinlock_t *tcfc_stats_lock; spinlock_t tcfc_lock; }; #define tcf_next common.tcfc_next @@ -32,7 +31,6 @@ struct tcf_common { #define tcf_bstats common.tcfc_bstats #define tcf_qstats common.tcfc_qstats #define tcf_rate_est common.tcfc_rate_est -#define tcf_stats_lock common.tcfc_stats_lock #define tcf_lock common.tcfc_lock struct tcf_police { @@ -123,34 +121,4 @@ extern int tcf_action_dump_old(struct sk_buff *skb, struct tc_action *a, int, in extern int tcf_action_dump_1(struct sk_buff *skb, struct tc_action *a, int, int); extern int tcf_action_copy_stats (struct sk_buff *,struct tc_action *, int); #endif /* CONFIG_NET_CLS_ACT */ - -extern int tcf_police(struct sk_buff *skb, struct tcf_police *p); -extern void tcf_police_destroy(struct tcf_police *p); -extern struct tcf_police * tcf_police_locate(struct rtattr *rta, struct rtattr *est); -extern int tcf_police_dump(struct sk_buff *skb, struct tcf_police *p); -extern int tcf_police_dump_stats(struct sk_buff *skb, struct tcf_police *p); - -static inline int -tcf_police_release(struct tcf_police *p, int bind) -{ - int ret = 0; -#ifdef CONFIG_NET_CLS_ACT - if (p) { - if (bind) - p->tcf_bindcnt--; - - p->tcf_refcnt--; - if (p->tcf_refcnt <= 0 && !p->tcf_bindcnt) { - tcf_police_destroy(p); - ret = 1; - } - } -#else - if (p && --p->tcf_refcnt == 0) - tcf_police_destroy(p); - -#endif /* CONFIG_NET_CLS_ACT */ - return ret; -} - #endif diff --git a/include/net/addrconf.h b/include/net/addrconf.h index f3531d0bcd0..33b593e1744 100644 --- a/include/net/addrconf.h +++ b/include/net/addrconf.h @@ -61,7 +61,7 @@ extern int addrconf_set_dstaddr(void __user *arg); extern int ipv6_chk_addr(struct in6_addr *addr, struct net_device *dev, int strict); -#ifdef CONFIG_IPV6_MIP6 +#if defined(CONFIG_IPV6_MIP6) || defined(CONFIG_IPV6_MIP6_MODULE) extern int ipv6_chk_home_addr(struct in6_addr *addr); #endif extern struct inet6_ifaddr * ipv6_get_ifaddr(struct in6_addr *addr, diff --git a/include/net/af_unix.h b/include/net/af_unix.h index c0398f5a8cb..6de1e9e35c7 100644 --- a/include/net/af_unix.h +++ b/include/net/af_unix.h @@ -62,13 +62,11 @@ struct unix_skb_parms { #define UNIXCREDS(skb) (&UNIXCB((skb)).creds) #define UNIXSID(skb) (&UNIXCB((skb)).secid) -#define unix_state_rlock(s) spin_lock(&unix_sk(s)->lock) -#define unix_state_runlock(s) spin_unlock(&unix_sk(s)->lock) -#define unix_state_wlock(s) spin_lock(&unix_sk(s)->lock) -#define unix_state_wlock_nested(s) \ +#define unix_state_lock(s) spin_lock(&unix_sk(s)->lock) +#define unix_state_unlock(s) spin_unlock(&unix_sk(s)->lock) +#define unix_state_lock_nested(s) \ spin_lock_nested(&unix_sk(s)->lock, \ SINGLE_DEPTH_NESTING) -#define unix_state_wunlock(s) spin_unlock(&unix_sk(s)->lock) #ifdef __KERNEL__ /* The AF_UNIX socket */ @@ -81,9 +79,10 @@ struct unix_sock { struct mutex readlock; struct sock *peer; struct sock *other; - struct sock *gc_tree; + struct list_head link; atomic_t inflight; spinlock_t lock; + unsigned int gc_candidate : 1; wait_queue_head_t peer_wait; }; #define unix_sk(__sk) ((struct unix_sock *)__sk) diff --git a/include/net/ax88796.h b/include/net/ax88796.h new file mode 100644 index 00000000000..ee786a043b3 --- /dev/null +++ b/include/net/ax88796.h @@ -0,0 +1,27 @@ +/* include/net/ax88796.h + * + * Copyright 2005 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + +#ifndef __NET_AX88796_PLAT_H +#define __NET_AX88796_PLAT_H + +#define AXFLG_HAS_EEPROM (1<<0) +#define AXFLG_MAC_FROMDEV (1<<1) /* device already has MAC */ + +struct ax_plat_data { + unsigned int flags; + unsigned char wordlength; /* 1 or 2 */ + unsigned char dcr_val; /* default value for DCR */ + unsigned char rcr_val; /* default value for RCR */ + unsigned char gpoc_val; /* default value for GPOC */ + u32 *reg_offsets; /* register offsets */ +}; + +#endif /* __NET_AX88796_PLAT_H */ diff --git a/include/net/bluetooth/hci.h b/include/net/bluetooth/hci.h index 93ce272a5d2..ebfb96b4110 100644 --- a/include/net/bluetooth/hci.h +++ b/include/net/bluetooth/hci.h @@ -107,14 +107,14 @@ enum { #define HCI_IDLE_TIMEOUT (6000) /* 6 seconds */ #define HCI_INIT_TIMEOUT (10000) /* 10 seconds */ -/* HCI Packet types */ +/* HCI data types */ #define HCI_COMMAND_PKT 0x01 #define HCI_ACLDATA_PKT 0x02 #define HCI_SCODATA_PKT 0x03 #define HCI_EVENT_PKT 0x04 #define HCI_VENDOR_PKT 0xff -/* HCI Packet types */ +/* HCI packet types */ #define HCI_DM1 0x0008 #define HCI_DM3 0x0400 #define HCI_DM5 0x4000 @@ -129,6 +129,14 @@ enum { #define SCO_PTYPE_MASK (HCI_HV1 | HCI_HV2 | HCI_HV3) #define ACL_PTYPE_MASK (~SCO_PTYPE_MASK) +/* eSCO packet types */ +#define ESCO_HV1 0x0001 +#define ESCO_HV2 0x0002 +#define ESCO_HV3 0x0004 +#define ESCO_EV3 0x0008 +#define ESCO_EV4 0x0010 +#define ESCO_EV5 0x0020 + /* ACL flags */ #define ACL_CONT 0x01 #define ACL_START 0x02 @@ -138,6 +146,7 @@ enum { /* Baseband links */ #define SCO_LINK 0x00 #define ACL_LINK 0x01 +#define ESCO_LINK 0x02 /* LMP features */ #define LMP_3SLOT 0x01 @@ -162,6 +171,11 @@ enum { #define LMP_PSCHEME 0x02 #define LMP_PCONTROL 0x04 +#define LMP_ESCO 0x80 + +#define LMP_EV4 0x01 +#define LMP_EV5 0x02 + #define LMP_SNIFF_SUBR 0x02 /* Connection modes */ diff --git a/include/net/bluetooth/hci_core.h b/include/net/bluetooth/hci_core.h index c0fc39620f3..8f67c8a7169 100644 --- a/include/net/bluetooth/hci_core.h +++ b/include/net/bluetooth/hci_core.h @@ -78,6 +78,7 @@ struct hci_dev { __u16 voice_setting; __u16 pkt_type; + __u16 esco_type; __u16 link_policy; __u16 link_mode; @@ -109,6 +110,7 @@ struct hci_dev { struct sk_buff_head cmd_q; struct sk_buff *sent_cmd; + struct sk_buff *reassembly[3]; struct semaphore req_lock; wait_queue_head_t req_wait_q; @@ -437,6 +439,8 @@ static inline int hci_recv_frame(struct sk_buff *skb) return 0; } +int hci_recv_fragment(struct hci_dev *hdev, int type, void *data, int count); + int hci_register_sysfs(struct hci_dev *hdev); void hci_unregister_sysfs(struct hci_dev *hdev); void hci_conn_add_sysfs(struct hci_conn *conn); @@ -449,6 +453,7 @@ void hci_conn_del_sysfs(struct hci_conn *conn); #define lmp_encrypt_capable(dev) ((dev)->features[0] & LMP_ENCRYPT) #define lmp_sniff_capable(dev) ((dev)->features[0] & LMP_SNIFF) #define lmp_sniffsubr_capable(dev) ((dev)->features[5] & LMP_SNIFF_SUBR) +#define lmp_esco_capable(dev) ((dev)->features[3] & LMP_ESCO) /* ----- HCI protocols ----- */ struct hci_proto { diff --git a/include/net/bluetooth/rfcomm.h b/include/net/bluetooth/rfcomm.h index 3c563f02907..25aa575db80 100644 --- a/include/net/bluetooth/rfcomm.h +++ b/include/net/bluetooth/rfcomm.h @@ -323,6 +323,7 @@ int rfcomm_connect_ind(struct rfcomm_session *s, u8 channel, struct rfcomm_dlc #define RFCOMM_RELEASE_ONHUP 1 #define RFCOMM_HANGUP_NOW 2 #define RFCOMM_TTY_ATTACHED 3 +#define RFCOMM_TTY_RELEASED 4 struct rfcomm_dev_req { s16 dev_id; diff --git a/include/net/cfg80211.h b/include/net/cfg80211.h index 88171f8ce58..7edaef6b29d 100644 --- a/include/net/cfg80211.h +++ b/include/net/cfg80211.h @@ -11,6 +11,44 @@ * Copyright 2006 Johannes Berg <johannes@sipsolutions.net> */ + +/* Radiotap header iteration + * implemented in net/wireless/radiotap.c + * docs in Documentation/networking/radiotap-headers.txt + */ +/** + * struct ieee80211_radiotap_iterator - tracks walk thru present radiotap args + * @rtheader: pointer to the radiotap header we are walking through + * @max_length: length of radiotap header in cpu byte ordering + * @this_arg_index: IEEE80211_RADIOTAP_... index of current arg + * @this_arg: pointer to current radiotap arg + * @arg_index: internal next argument index + * @arg: internal next argument pointer + * @next_bitmap: internal pointer to next present u32 + * @bitmap_shifter: internal shifter for curr u32 bitmap, b0 set == arg present + */ + +struct ieee80211_radiotap_iterator { + struct ieee80211_radiotap_header *rtheader; + int max_length; + int this_arg_index; + u8 *this_arg; + + int arg_index; + u8 *arg; + __le32 *next_bitmap; + u32 bitmap_shifter; +}; + +extern int ieee80211_radiotap_iterator_init( + struct ieee80211_radiotap_iterator *iterator, + struct ieee80211_radiotap_header *radiotap_header, + int max_length); + +extern int ieee80211_radiotap_iterator_next( + struct ieee80211_radiotap_iterator *iterator); + + /* from net/wireless.h */ struct wiphy; diff --git a/include/net/cipso_ipv4.h b/include/net/cipso_ipv4.h index 4f90f5554fa..a6bb94530cf 100644 --- a/include/net/cipso_ipv4.h +++ b/include/net/cipso_ipv4.h @@ -203,12 +203,10 @@ static inline int cipso_v4_cache_add(const struct sk_buff *skb, #ifdef CONFIG_NETLABEL void cipso_v4_error(struct sk_buff *skb, int error, u32 gateway); -int cipso_v4_socket_setattr(const struct socket *sock, - const struct cipso_v4_doi *doi_def, - const struct netlbl_lsm_secattr *secattr); +int cipso_v4_sock_setattr(struct sock *sk, + const struct cipso_v4_doi *doi_def, + const struct netlbl_lsm_secattr *secattr); int cipso_v4_sock_getattr(struct sock *sk, struct netlbl_lsm_secattr *secattr); -int cipso_v4_socket_getattr(const struct socket *sock, - struct netlbl_lsm_secattr *secattr); int cipso_v4_skbuff_getattr(const struct sk_buff *skb, struct netlbl_lsm_secattr *secattr); int cipso_v4_validate(unsigned char **option); @@ -220,9 +218,9 @@ static inline void cipso_v4_error(struct sk_buff *skb, return; } -static inline int cipso_v4_socket_setattr(const struct socket *sock, - const struct cipso_v4_doi *doi_def, - const struct netlbl_lsm_secattr *secattr) +static inline int cipso_v4_sock_setattr(struct sock *sk, + const struct cipso_v4_doi *doi_def, + const struct netlbl_lsm_secattr *secattr) { return -ENOSYS; } @@ -233,12 +231,6 @@ static inline int cipso_v4_sock_getattr(struct sock *sk, return -ENOSYS; } -static inline int cipso_v4_socket_getattr(const struct socket *sock, - struct netlbl_lsm_secattr *secattr) -{ - return -ENOSYS; -} - static inline int cipso_v4_skbuff_getattr(const struct sk_buff *skb, struct netlbl_lsm_secattr *secattr) { diff --git a/include/net/dn.h b/include/net/dn.h index ac4ce909174..627778384c8 100644 --- a/include/net/dn.h +++ b/include/net/dn.h @@ -3,7 +3,6 @@ #include <linux/dn.h> #include <net/sock.h> -#include <net/tcp.h> #include <asm/byteorder.h> #define dn_ntohs(x) le16_to_cpu(x) diff --git a/include/net/dst.h b/include/net/dst.h index 82270f9332d..e9ff4a4caef 100644 --- a/include/net/dst.h +++ b/include/net/dst.h @@ -47,7 +47,6 @@ struct dst_entry #define DST_NOXFRM 2 #define DST_NOPOLICY 4 #define DST_NOHASH 8 -#define DST_BALANCED 0x10 unsigned long expires; unsigned short header_len; /* more space at head required */ diff --git a/include/net/fib_rules.h b/include/net/fib_rules.h index ed3a8872c6c..83e41dd15cc 100644 --- a/include/net/fib_rules.h +++ b/include/net/fib_rules.h @@ -64,7 +64,7 @@ struct fib_rules_ops void (*flush_cache)(void); int nlgroup; - struct nla_policy *policy; + const struct nla_policy *policy; struct list_head *rules_list; struct module *owner; }; diff --git a/include/net/flow.h b/include/net/flow.h index f3cc1f81261..af59fa5cc1f 100644 --- a/include/net/flow.h +++ b/include/net/flow.h @@ -67,20 +67,16 @@ struct flowi { __be32 spi; -#ifdef CONFIG_IPV6_MIP6 struct { __u8 type; } mht; -#endif } uli_u; #define fl_ip_sport uli_u.ports.sport #define fl_ip_dport uli_u.ports.dport #define fl_icmp_type uli_u.icmpt.type #define fl_icmp_code uli_u.icmpt.code #define fl_ipsec_spi uli_u.spi -#ifdef CONFIG_IPV6_MIP6 #define fl_mh_type uli_u.mht.type -#endif __u32 secid; /* used by xfrm; see secid.txt */ } __attribute__((__aligned__(BITS_PER_LONG/8))); diff --git a/include/net/genetlink.h b/include/net/genetlink.h index adff4c898d5..b6eaca122db 100644 --- a/include/net/genetlink.h +++ b/include/net/genetlink.h @@ -60,7 +60,7 @@ struct genl_ops { u8 cmd; unsigned int flags; - struct nla_policy *policy; + const struct nla_policy *policy; int (*doit)(struct sk_buff *skb, struct genl_info *info); int (*dumpit)(struct sk_buff *skb, diff --git a/include/net/inet_timewait_sock.h b/include/net/inet_timewait_sock.h index 09a2532699b..47d52b2414d 100644 --- a/include/net/inet_timewait_sock.h +++ b/include/net/inet_timewait_sock.h @@ -209,9 +209,6 @@ static inline void inet_twsk_put(struct inet_timewait_sock *tw) extern struct inet_timewait_sock *inet_twsk_alloc(const struct sock *sk, const int state); -extern void __inet_twsk_kill(struct inet_timewait_sock *tw, - struct inet_hashinfo *hashinfo); - extern void __inet_twsk_hashdance(struct inet_timewait_sock *tw, struct sock *sk, struct inet_hashinfo *hashinfo); diff --git a/include/net/ip.h b/include/net/ip.h index bb207db0367..abf2820a112 100644 --- a/include/net/ip.h +++ b/include/net/ip.h @@ -143,6 +143,7 @@ struct ip_reply_arg { __wsum csum; int csumoffset; /* u16 offset of csum in iov[0].iov_base */ /* -1 if not needed */ + int bound_dev_if; }; void ip_send_reply(struct sock *sk, struct sk_buff *skb, struct ip_reply_arg *arg, diff --git a/include/net/ip_fib.h b/include/net/ip_fib.h index 5a4a0366c24..8cadc77c7df 100644 --- a/include/net/ip_fib.h +++ b/include/net/ip_fib.h @@ -39,7 +39,6 @@ struct fib_config { int fc_mx_len; int fc_mp_len; u32 fc_flow; - u32 fc_mp_alg; u32 fc_nlflags; struct nl_info fc_nlinfo; }; @@ -86,9 +85,6 @@ struct fib_info { #ifdef CONFIG_IP_ROUTE_MULTIPATH int fib_power; #endif -#ifdef CONFIG_IP_ROUTE_MULTIPATH_CACHED - u32 fib_mp_alg; -#endif struct fib_nh fib_nh[0]; #define fib_dev fib_nh[0].nh_dev }; @@ -103,10 +99,6 @@ struct fib_result { unsigned char nh_sel; unsigned char type; unsigned char scope; -#ifdef CONFIG_IP_ROUTE_MULTIPATH_CACHED - __be32 network; - __be32 netmask; -#endif struct fib_info *fi; #ifdef CONFIG_IP_MULTIPLE_TABLES struct fib_rule *r; @@ -145,14 +137,6 @@ struct fib_result_nl { #define FIB_RES_DEV(res) (FIB_RES_NH(res).nh_dev) #define FIB_RES_OIF(res) (FIB_RES_NH(res).nh_oif) -#ifdef CONFIG_IP_ROUTE_MULTIPATH_CACHED -#define FIB_RES_NETWORK(res) ((res).network) -#define FIB_RES_NETMASK(res) ((res).netmask) -#else /* CONFIG_IP_ROUTE_MULTIPATH_CACHED */ -#define FIB_RES_NETWORK(res) (0) -#define FIB_RES_NETMASK(res) (0) -#endif /* CONFIG_IP_ROUTE_MULTIPATH_WRANDOM */ - struct fib_table { struct hlist_node tb_hlist; u32 tb_id; @@ -213,7 +197,7 @@ extern void fib_select_default(const struct flowi *flp, struct fib_result *res); #endif /* CONFIG_IP_MULTIPLE_TABLES */ /* Exported by fib_frontend.c */ -extern struct nla_policy rtm_ipv4_policy[]; +extern const struct nla_policy rtm_ipv4_policy[]; extern void ip_fib_init(void); extern int fib_validate_source(__be32 src, __be32 dst, u8 tos, int oif, struct net_device *dev, __be32 *spec_dst, u32 *itag); diff --git a/include/net/ip_mp_alg.h b/include/net/ip_mp_alg.h deleted file mode 100644 index 25b56571e54..00000000000 --- a/include/net/ip_mp_alg.h +++ /dev/null @@ -1,96 +0,0 @@ -/* ip_mp_alg.h: IPV4 multipath algorithm support. - * - * Copyright (C) 2004, 2005 Einar Lueck <elueck@de.ibm.com> - * Copyright (C) 2005 David S. Miller <davem@davemloft.net> - */ - -#ifndef _NET_IP_MP_ALG_H -#define _NET_IP_MP_ALG_H - -#include <linux/ip_mp_alg.h> -#include <net/flow.h> -#include <net/route.h> - -struct fib_nh; - -struct ip_mp_alg_ops { - void (*mp_alg_select_route)(const struct flowi *flp, - struct rtable *rth, struct rtable **rp); - void (*mp_alg_flush)(void); - void (*mp_alg_set_nhinfo)(__be32 network, __be32 netmask, - unsigned char prefixlen, - const struct fib_nh *nh); - void (*mp_alg_remove)(struct rtable *rth); -}; - -extern int multipath_alg_register(struct ip_mp_alg_ops *, enum ip_mp_alg); -extern void multipath_alg_unregister(struct ip_mp_alg_ops *, enum ip_mp_alg); - -extern struct ip_mp_alg_ops *ip_mp_alg_table[]; - -static inline int multipath_select_route(const struct flowi *flp, - struct rtable *rth, - struct rtable **rp) -{ -#ifdef CONFIG_IP_ROUTE_MULTIPATH_CACHED - struct ip_mp_alg_ops *ops = ip_mp_alg_table[rth->rt_multipath_alg]; - - /* mp_alg_select_route _MUST_ be implemented */ - if (ops && (rth->u.dst.flags & DST_BALANCED)) { - ops->mp_alg_select_route(flp, rth, rp); - return 1; - } -#endif - return 0; -} - -static inline void multipath_flush(void) -{ -#ifdef CONFIG_IP_ROUTE_MULTIPATH_CACHED - int i; - - for (i = IP_MP_ALG_NONE; i <= IP_MP_ALG_MAX; i++) { - struct ip_mp_alg_ops *ops = ip_mp_alg_table[i]; - - if (ops && ops->mp_alg_flush) - ops->mp_alg_flush(); - } -#endif -} - -static inline void multipath_set_nhinfo(struct rtable *rth, - __be32 network, __be32 netmask, - unsigned char prefixlen, - const struct fib_nh *nh) -{ -#ifdef CONFIG_IP_ROUTE_MULTIPATH_CACHED - struct ip_mp_alg_ops *ops = ip_mp_alg_table[rth->rt_multipath_alg]; - - if (ops && ops->mp_alg_set_nhinfo) - ops->mp_alg_set_nhinfo(network, netmask, prefixlen, nh); -#endif -} - -static inline void multipath_remove(struct rtable *rth) -{ -#ifdef CONFIG_IP_ROUTE_MULTIPATH_CACHED - struct ip_mp_alg_ops *ops = ip_mp_alg_table[rth->rt_multipath_alg]; - - if (ops && ops->mp_alg_remove && - (rth->u.dst.flags & DST_BALANCED)) - ops->mp_alg_remove(rth); -#endif -} - -static inline int multipath_comparekeys(const struct flowi *flp1, - const struct flowi *flp2) -{ - return flp1->fl4_dst == flp2->fl4_dst && - flp1->fl4_src == flp2->fl4_src && - flp1->oif == flp2->oif && - flp1->mark == flp2->mark && - !((flp1->fl4_tos ^ flp2->fl4_tos) & - (IPTOS_RT_MASK | RTO_ONLINK)); -} - -#endif /* _NET_IP_MP_ALG_H */ diff --git a/include/net/ipv6.h b/include/net/ipv6.h index 78a0d06d98d..46b9dce82f6 100644 --- a/include/net/ipv6.h +++ b/include/net/ipv6.h @@ -512,10 +512,6 @@ extern int ipv6_ext_hdr(u8 nexthdr); extern int ipv6_find_tlv(struct sk_buff *skb, int offset, int type); -extern struct ipv6_txoptions * ipv6_invert_rthdr(struct sock *sk, - struct ipv6_rt_hdr *hdr); - - /* * socket options (ipv6_sockglue.c) */ diff --git a/include/net/irda/irda.h b/include/net/irda/irda.h index 36bee441aa5..08387553b57 100644 --- a/include/net/irda/irda.h +++ b/include/net/irda/irda.h @@ -125,6 +125,9 @@ extern void irda_sysctl_unregister(void); extern int irsock_init(void); extern void irsock_cleanup(void); +extern int irda_nl_register(void); +extern void irda_nl_unregister(void); + extern int irlap_driver_rcv(struct sk_buff *skb, struct net_device *dev, struct packet_type *ptype, struct net_device *orig_dev); diff --git a/include/net/irda/irlap.h b/include/net/irda/irlap.h index f0248fb8e19..9d0c78ea92f 100644 --- a/include/net/irda/irlap.h +++ b/include/net/irda/irlap.h @@ -208,6 +208,8 @@ struct irlap_cb { int xbofs_delay; /* Nr of XBOF's used to MTT */ int bofs_count; /* Negotiated extra BOFs */ int next_bofs; /* Negotiated extra BOFs after next frame */ + + int mode; /* IrLAP mode (primary, secondary or monitor) */ }; /* @@ -289,4 +291,21 @@ static inline void irlap_clear_disconnect(struct irlap_cb *self) self->disconnect_pending = FALSE; } +/* + * Function irlap_next_state (self, state) + * + * Switches state and provides debug information + * + */ +static inline void irlap_next_state(struct irlap_cb *self, IRLAP_STATE state) +{ + /* + if (!self || self->magic != LAP_MAGIC) + return; + + IRDA_DEBUG(4, "next LAP state = %s\n", irlap_state[state]); + */ + self->state = state; +} + #endif diff --git a/include/net/iucv/af_iucv.h b/include/net/iucv/af_iucv.h index f9bd11be189..b6c468cd7f5 100644 --- a/include/net/iucv/af_iucv.h +++ b/include/net/iucv/af_iucv.h @@ -60,6 +60,7 @@ struct iucv_sock { char dst_user_id[8]; char dst_name[8]; struct list_head accept_q; + spinlock_t accept_q_lock; struct sock *parent; struct iucv_path *path; struct sk_buff_head send_skb_q; diff --git a/include/net/mac80211.h b/include/net/mac80211.h index a7f122b7994..c34fd9a6160 100644 --- a/include/net/mac80211.h +++ b/include/net/mac80211.h @@ -347,9 +347,16 @@ enum ieee80211_if_types { * @mac_addr: pointer to MAC address of the interface. This pointer is valid * until the interface is removed (i.e. it cannot be used after * remove_interface() callback was called for this interface). + * This pointer will be %NULL for monitor interfaces, be careful. * * This structure is used in add_interface() and remove_interface() * callbacks of &struct ieee80211_hw. + * + * When you allow multiple interfaces to be added to your PHY, take care + * that the hardware can actually handle multiple MAC addresses. However, + * also take care that when there's no interface left with mac_addr != %NULL + * you remove the MAC address from the device to avoid acknowledging packets + * in pure monitor mode. */ struct ieee80211_if_init_conf { int if_id; @@ -574,10 +581,11 @@ struct ieee80211_ops { * to returning zero. By returning non-zero addition of the interface * is inhibited. Unless monitor_during_oper is set, it is guaranteed * that monitor interfaces and normal interfaces are mutually - * exclusive. The open() handler is called after add_interface() - * if this is the first device added. At least one of the open() - * open() and add_interface() callbacks has to be assigned. If - * add_interface() is NULL, one STA interface is permitted only. */ + * exclusive. If assigned, the open() handler is called after + * add_interface() if this is the first device added. The + * add_interface() callback has to be assigned because it is the only + * way to obtain the requested MAC address for any interface. + */ int (*add_interface)(struct ieee80211_hw *hw, struct ieee80211_if_init_conf *conf); @@ -921,12 +929,6 @@ struct sk_buff * ieee80211_get_buffered_bc(struct ieee80211_hw *hw, int if_id, struct ieee80211_tx_control *control); -/* Low level drivers that have their own MLME and MAC indicate - * the aid for an associating station with this call */ -int ieee80211_set_aid_for_sta(struct ieee80211_hw *hw, - u8 *peer_address, u16 aid); - - /* Given an sk_buff with a raw 802.11 header at the data pointer this function * returns the 802.11 header length in bytes (not including encryption * headers). If the data in the sk_buff is too short to contain a valid 802.11 diff --git a/include/net/mip6.h b/include/net/mip6.h index 68263c6d999..63272610a24 100644 --- a/include/net/mip6.h +++ b/include/net/mip6.h @@ -54,8 +54,4 @@ struct ip6_mh { #define IP6_MH_TYPE_BERROR 7 /* Binding Error */ #define IP6_MH_TYPE_MAX IP6_MH_TYPE_BERROR -extern int mip6_init(void); -extern void mip6_fini(void); -extern int mip6_mh_filter(struct sock *sk, struct sk_buff *skb); - #endif diff --git a/include/net/netfilter/ipv4/nf_conntrack_ipv4.h b/include/net/netfilter/ipv4/nf_conntrack_ipv4.h index 1401ccc051c..7a671603fca 100644 --- a/include/net/netfilter/ipv4/nf_conntrack_ipv4.h +++ b/include/net/netfilter/ipv4/nf_conntrack_ipv4.h @@ -9,29 +9,10 @@ #ifndef _NF_CONNTRACK_IPV4_H #define _NF_CONNTRACK_IPV4_H -#ifdef CONFIG_NF_NAT_NEEDED -#include <net/netfilter/nf_nat.h> -#include <linux/netfilter/nf_conntrack_pptp.h> - -/* per conntrack: nat application helper private data */ -union nf_conntrack_nat_help { - /* insert nat helper private data here */ - struct nf_nat_pptp nat_pptp_info; -}; - -struct nf_conn_nat { - struct nf_nat_info info; - union nf_conntrack_nat_help help; -#if defined(CONFIG_IP_NF_TARGET_MASQUERADE) || \ - defined(CONFIG_IP_NF_TARGET_MASQUERADE_MODULE) - int masq_index; -#endif -}; -#endif /* CONFIG_NF_NAT_NEEDED */ - /* Returns new sk_buff, or NULL */ -struct sk_buff * -nf_ct_ipv4_ct_gather_frags(struct sk_buff *skb); +struct sk_buff *nf_ct_ipv4_ct_gather_frags(struct sk_buff *skb); + +extern struct nf_conntrack_l3proto nf_conntrack_l3proto_ipv4; extern struct nf_conntrack_l4proto nf_conntrack_l4proto_tcp4; extern struct nf_conntrack_l4proto nf_conntrack_l4proto_udp4; diff --git a/include/net/netfilter/ipv6/nf_conntrack_ipv6.h b/include/net/netfilter/ipv6/nf_conntrack_ipv6.h index b4b6049e01f..5a896590437 100644 --- a/include/net/netfilter/ipv6/nf_conntrack_ipv6.h +++ b/include/net/netfilter/ipv6/nf_conntrack_ipv6.h @@ -7,7 +7,7 @@ extern struct nf_conntrack_l4proto nf_conntrack_l4proto_tcp6; extern struct nf_conntrack_l4proto nf_conntrack_l4proto_udp6; extern struct nf_conntrack_l4proto nf_conntrack_l4proto_icmpv6; -extern int nf_ct_ipv6_skip_exthdr(struct sk_buff *skb, int start, +extern int nf_ct_ipv6_skip_exthdr(const struct sk_buff *skb, int start, u8 *nexthdrp, int len); extern int nf_ct_frag6_init(void); diff --git a/include/net/netfilter/nf_conntrack.h b/include/net/netfilter/nf_conntrack.h index 4732432f8eb..810020ec345 100644 --- a/include/net/netfilter/nf_conntrack.h +++ b/include/net/netfilter/nf_conntrack.h @@ -82,6 +82,8 @@ struct nf_conn_help { union nf_conntrack_help help; + struct hlist_head expectations; + /* Current number of expected connections */ unsigned int expecting; }; @@ -117,9 +119,6 @@ struct nf_conn /* Unique ID that identifies this conntrack*/ unsigned int id; - /* features - nat, helper, ... used by allocating system */ - u_int32_t features; - #if defined(CONFIG_NF_CONNTRACK_MARK) u_int32_t mark; #endif @@ -131,8 +130,8 @@ struct nf_conn /* Storage reserved for other modules: */ union nf_conntrack_proto proto; - /* features dynamically at the end: helper, nat (both optional) */ - char data[0]; + /* Extensions */ + struct nf_ct_ext *ext; }; static inline struct nf_conn * @@ -175,6 +174,10 @@ static inline void nf_ct_put(struct nf_conn *ct) extern int nf_ct_l3proto_try_module_get(unsigned short l3proto); extern void nf_ct_l3proto_module_put(unsigned short l3proto); +extern struct hlist_head *nf_ct_alloc_hashtable(int *sizep, int *vmalloced); +extern void nf_ct_free_hashtable(struct hlist_head *hash, int vmalloced, + int size); + extern struct nf_conntrack_tuple_hash * __nf_conntrack_find(const struct nf_conntrack_tuple *tuple, const struct nf_conn *ignored_conntrack); @@ -183,6 +186,10 @@ extern void nf_conntrack_hash_insert(struct nf_conn *ct); extern void nf_conntrack_flush(void); +extern int nf_ct_get_tuplepr(const struct sk_buff *skb, + unsigned int nhoff, + u_int16_t l3num, + struct nf_conntrack_tuple *tuple); extern int nf_ct_invert_tuplepr(struct nf_conntrack_tuple *inverse, const struct nf_conntrack_tuple *orig); @@ -216,9 +223,6 @@ extern void nf_conntrack_tcp_update(struct sk_buff *skb, struct nf_conn *conntrack, int dir); -/* Call me when a conntrack is destroyed. */ -extern void (*nf_conntrack_destroyed)(struct nf_conn *conntrack); - /* Fake conntrack entry for untracked connections */ extern struct nf_conn nf_conntrack_untracked; @@ -262,60 +266,10 @@ do { \ local_bh_enable(); \ } while (0) -/* no helper, no nat */ -#define NF_CT_F_BASIC 0 -/* for helper */ -#define NF_CT_F_HELP 1 -/* for nat. */ -#define NF_CT_F_NAT 2 -#define NF_CT_F_NUM 4 - extern int nf_conntrack_register_cache(u_int32_t features, const char *name, size_t size); extern void nf_conntrack_unregister_cache(u_int32_t features); -/* valid combinations: - * basic: nf_conn, nf_conn .. nf_conn_help - * nat: nf_conn .. nf_conn_nat, nf_conn .. nf_conn_nat .. nf_conn help - */ -#ifdef CONFIG_NF_NAT_NEEDED -static inline struct nf_conn_nat *nfct_nat(const struct nf_conn *ct) -{ - unsigned int offset = sizeof(struct nf_conn); - - if (!(ct->features & NF_CT_F_NAT)) - return NULL; - - offset = ALIGN(offset, __alignof__(struct nf_conn_nat)); - return (struct nf_conn_nat *) ((void *)ct + offset); -} - -static inline struct nf_conn_help *nfct_help(const struct nf_conn *ct) -{ - unsigned int offset = sizeof(struct nf_conn); - - if (!(ct->features & NF_CT_F_HELP)) - return NULL; - if (ct->features & NF_CT_F_NAT) { - offset = ALIGN(offset, __alignof__(struct nf_conn_nat)); - offset += sizeof(struct nf_conn_nat); - } - - offset = ALIGN(offset, __alignof__(struct nf_conn_help)); - return (struct nf_conn_help *) ((void *)ct + offset); -} -#else /* No NAT */ -static inline struct nf_conn_help *nfct_help(const struct nf_conn *ct) -{ - unsigned int offset = sizeof(struct nf_conn); - - if (!(ct->features & NF_CT_F_HELP)) - return NULL; - - offset = ALIGN(offset, __alignof__(struct nf_conn_help)); - return (struct nf_conn_help *) ((void *)ct + offset); -} -#endif /* CONFIG_NF_NAT_NEEDED */ #endif /* __KERNEL__ */ #endif /* _NF_CONNTRACK_H */ diff --git a/include/net/netfilter/nf_conntrack_core.h b/include/net/netfilter/nf_conntrack_core.h index 9fb906688ff..4056f5f08da 100644 --- a/include/net/netfilter/nf_conntrack_core.h +++ b/include/net/netfilter/nf_conntrack_core.h @@ -30,6 +30,9 @@ extern void nf_conntrack_cleanup(void); extern int nf_conntrack_proto_init(void); extern void nf_conntrack_proto_fini(void); +extern int nf_conntrack_helper_init(void); +extern void nf_conntrack_helper_fini(void); + struct nf_conntrack_l3proto; extern struct nf_conntrack_l3proto *nf_ct_find_l3proto(u_int16_t pf); /* Like above, but you already have conntrack read lock. */ @@ -55,8 +58,7 @@ nf_ct_invert_tuple(struct nf_conntrack_tuple *inverse, /* Find a connection corresponding to a tuple. */ extern struct nf_conntrack_tuple_hash * -nf_conntrack_find_get(const struct nf_conntrack_tuple *tuple, - const struct nf_conn *ignored_conntrack); +nf_conntrack_find_get(const struct nf_conntrack_tuple *tuple); extern int __nf_conntrack_confirm(struct sk_buff **pskb); @@ -81,9 +83,8 @@ print_tuple(struct seq_file *s, const struct nf_conntrack_tuple *tuple, struct nf_conntrack_l3proto *l3proto, struct nf_conntrack_l4proto *proto); -extern struct list_head *nf_conntrack_hash; -extern struct list_head nf_conntrack_expect_list; +extern struct hlist_head *nf_conntrack_hash; extern rwlock_t nf_conntrack_lock ; -extern struct list_head unconfirmed; +extern struct hlist_head unconfirmed; #endif /* _NF_CONNTRACK_CORE_H */ diff --git a/include/net/netfilter/nf_conntrack_ecache.h b/include/net/netfilter/nf_conntrack_ecache.h index 811c9073c53..f0b9078235c 100644 --- a/include/net/netfilter/nf_conntrack_ecache.h +++ b/include/net/netfilter/nf_conntrack_ecache.h @@ -49,15 +49,15 @@ static inline void nf_conntrack_event(enum ip_conntrack_events event, atomic_notifier_call_chain(&nf_conntrack_chain, event, ct); } -extern struct atomic_notifier_head nf_conntrack_expect_chain; -extern int nf_conntrack_expect_register_notifier(struct notifier_block *nb); -extern int nf_conntrack_expect_unregister_notifier(struct notifier_block *nb); +extern struct atomic_notifier_head nf_ct_expect_chain; +extern int nf_ct_expect_register_notifier(struct notifier_block *nb); +extern int nf_ct_expect_unregister_notifier(struct notifier_block *nb); static inline void -nf_conntrack_expect_event(enum ip_conntrack_expect_events event, - struct nf_conntrack_expect *exp) +nf_ct_expect_event(enum ip_conntrack_expect_events event, + struct nf_conntrack_expect *exp) { - atomic_notifier_call_chain(&nf_conntrack_expect_chain, event, exp); + atomic_notifier_call_chain(&nf_ct_expect_chain, event, exp); } #else /* CONFIG_NF_CONNTRACK_EVENTS */ @@ -67,9 +67,8 @@ static inline void nf_conntrack_event_cache(enum ip_conntrack_events event, static inline void nf_conntrack_event(enum ip_conntrack_events event, struct nf_conn *ct) {} static inline void nf_ct_deliver_cached_events(const struct nf_conn *ct) {} -static inline void -nf_conntrack_expect_event(enum ip_conntrack_expect_events event, - struct nf_conntrack_expect *exp) {} +static inline void nf_ct_expect_event(enum ip_conntrack_expect_events event, + struct nf_conntrack_expect *exp) {} static inline void nf_ct_event_cache_flush(void) {} #endif /* CONFIG_NF_CONNTRACK_EVENTS */ diff --git a/include/net/netfilter/nf_conntrack_expect.h b/include/net/netfilter/nf_conntrack_expect.h index 173c7c1eff2..cae1a0dce36 100644 --- a/include/net/netfilter/nf_conntrack_expect.h +++ b/include/net/netfilter/nf_conntrack_expect.h @@ -6,17 +6,21 @@ #define _NF_CONNTRACK_EXPECT_H #include <net/netfilter/nf_conntrack.h> -extern struct list_head nf_conntrack_expect_list; -extern struct kmem_cache *nf_conntrack_expect_cachep; -extern const struct file_operations exp_file_ops; +extern struct hlist_head *nf_ct_expect_hash; +extern unsigned int nf_ct_expect_hsize; +extern unsigned int nf_ct_expect_max; struct nf_conntrack_expect { - /* Internal linked list (global expectation list) */ - struct list_head list; + /* Conntrack expectation list member */ + struct hlist_node lnode; + + /* Hash member */ + struct hlist_node hnode; /* We expect this tuple, with the following mask */ - struct nf_conntrack_tuple tuple, mask; + struct nf_conntrack_tuple tuple; + struct nf_conntrack_tuple_mask mask; /* Function to call after setup and insertion */ void (*expectfn)(struct nf_conn *new, @@ -52,29 +56,31 @@ struct nf_conntrack_expect #define NF_CT_EXPECT_PERMANENT 0x1 +int nf_conntrack_expect_init(void); +void nf_conntrack_expect_fini(void); struct nf_conntrack_expect * -__nf_conntrack_expect_find(const struct nf_conntrack_tuple *tuple); +__nf_ct_expect_find(const struct nf_conntrack_tuple *tuple); struct nf_conntrack_expect * -nf_conntrack_expect_find_get(const struct nf_conntrack_tuple *tuple); +nf_ct_expect_find_get(const struct nf_conntrack_tuple *tuple); struct nf_conntrack_expect * -find_expectation(const struct nf_conntrack_tuple *tuple); +nf_ct_find_expectation(const struct nf_conntrack_tuple *tuple); void nf_ct_unlink_expect(struct nf_conntrack_expect *exp); void nf_ct_remove_expectations(struct nf_conn *ct); -void nf_conntrack_unexpect_related(struct nf_conntrack_expect *exp); +void nf_ct_unexpect_related(struct nf_conntrack_expect *exp); /* Allocate space for an expectation: this is mandatory before calling - nf_conntrack_expect_related. You will have to call put afterwards. */ -struct nf_conntrack_expect *nf_conntrack_expect_alloc(struct nf_conn *me); -void nf_conntrack_expect_init(struct nf_conntrack_expect *, int, - union nf_conntrack_address *, - union nf_conntrack_address *, - u_int8_t, __be16 *, __be16 *); -void nf_conntrack_expect_put(struct nf_conntrack_expect *exp); -int nf_conntrack_expect_related(struct nf_conntrack_expect *expect); + nf_ct_expect_related. You will have to call put afterwards. */ +struct nf_conntrack_expect *nf_ct_expect_alloc(struct nf_conn *me); +void nf_ct_expect_init(struct nf_conntrack_expect *, int, + union nf_conntrack_address *, + union nf_conntrack_address *, + u_int8_t, __be16 *, __be16 *); +void nf_ct_expect_put(struct nf_conntrack_expect *exp); +int nf_ct_expect_related(struct nf_conntrack_expect *expect); #endif /*_NF_CONNTRACK_EXPECT_H*/ diff --git a/include/net/netfilter/nf_conntrack_extend.h b/include/net/netfilter/nf_conntrack_extend.h new file mode 100644 index 00000000000..73b5711faf3 --- /dev/null +++ b/include/net/netfilter/nf_conntrack_extend.h @@ -0,0 +1,85 @@ +#ifndef _NF_CONNTRACK_EXTEND_H +#define _NF_CONNTRACK_EXTEND_H + +#include <net/netfilter/nf_conntrack.h> + +enum nf_ct_ext_id +{ + NF_CT_EXT_HELPER, + NF_CT_EXT_NAT, + NF_CT_EXT_NUM, +}; + +#define NF_CT_EXT_HELPER_TYPE struct nf_conn_help +#define NF_CT_EXT_NAT_TYPE struct nf_conn_nat + +/* Extensions: optional stuff which isn't permanently in struct. */ +struct nf_ct_ext { + u8 offset[NF_CT_EXT_NUM]; + u8 len; + u8 real_len; + char data[0]; +}; + +static inline int nf_ct_ext_exist(const struct nf_conn *ct, u8 id) +{ + return (ct->ext && ct->ext->offset[id]); +} + +static inline void *__nf_ct_ext_find(const struct nf_conn *ct, u8 id) +{ + if (!nf_ct_ext_exist(ct, id)) + return NULL; + + return (void *)ct->ext + ct->ext->offset[id]; +} +#define nf_ct_ext_find(ext, id) \ + ((id##_TYPE *)__nf_ct_ext_find((ext), (id))) + +/* Destroy all relationships */ +extern void __nf_ct_ext_destroy(struct nf_conn *ct); +static inline void nf_ct_ext_destroy(struct nf_conn *ct) +{ + if (ct->ext) + __nf_ct_ext_destroy(ct); +} + +/* Free operation. If you want to free a object referred from private area, + * please implement __nf_ct_ext_free() and call it. + */ +static inline void nf_ct_ext_free(struct nf_conn *ct) +{ + if (ct->ext) + kfree(ct->ext); +} + +/* Add this type, returns pointer to data or NULL. */ +void * +__nf_ct_ext_add(struct nf_conn *ct, enum nf_ct_ext_id id, gfp_t gfp); +#define nf_ct_ext_add(ct, id, gfp) \ + ((id##_TYPE *)__nf_ct_ext_add((ct), (id), (gfp))) + +#define NF_CT_EXT_F_PREALLOC 0x0001 + +struct nf_ct_ext_type +{ + /* Destroys relationships (can be NULL). */ + void (*destroy)(struct nf_conn *ct); + /* Called when realloacted (can be NULL). + Contents has already been moved. */ + void (*move)(struct nf_conn *ct, void *old); + + enum nf_ct_ext_id id; + + unsigned int flags; + + /* Length and min alignment. */ + u8 len; + u8 align; + /* initial size of nf_ct_ext. */ + u8 alloc_size; +}; + +int nf_ct_extend_register(struct nf_ct_ext_type *type); +void nf_ct_extend_unregister(struct nf_ct_ext_type *type); +#endif /* _NF_CONNTRACK_EXTEND_H */ diff --git a/include/net/netfilter/nf_conntrack_helper.h b/include/net/netfilter/nf_conntrack_helper.h index 8c72ac9f0ab..d04f99964d9 100644 --- a/include/net/netfilter/nf_conntrack_helper.h +++ b/include/net/netfilter/nf_conntrack_helper.h @@ -10,12 +10,13 @@ #ifndef _NF_CONNTRACK_HELPER_H #define _NF_CONNTRACK_HELPER_H #include <net/netfilter/nf_conntrack.h> +#include <net/netfilter/nf_conntrack_extend.h> struct module; struct nf_conntrack_helper -{ - struct list_head list; /* Internal use. */ +{ + struct hlist_node hnode; /* Internal use. */ const char *name; /* name of the module */ struct module *me; /* pointer to self */ @@ -23,10 +24,9 @@ struct nf_conntrack_helper * expected connections */ unsigned int timeout; /* timeout for expecteds */ - /* Mask of things we will help (compared against server response) */ + /* Tuple of things we will help (compared against server response) */ struct nf_conntrack_tuple tuple; - struct nf_conntrack_tuple mask; - + /* Function to call when data passes; return verdict, or -1 to invalidate. */ int (*help)(struct sk_buff **pskb, @@ -52,4 +52,10 @@ extern void nf_ct_helper_put(struct nf_conntrack_helper *helper); extern int nf_conntrack_helper_register(struct nf_conntrack_helper *); extern void nf_conntrack_helper_unregister(struct nf_conntrack_helper *); +extern struct nf_conn_help *nf_ct_helper_ext_add(struct nf_conn *ct, gfp_t gfp); + +static inline struct nf_conn_help *nfct_help(const struct nf_conn *ct) +{ + return nf_ct_ext_find(ct, NF_CT_EXT_HELPER); +} #endif /*_NF_CONNTRACK_HELPER_H*/ diff --git a/include/net/netfilter/nf_conntrack_l3proto.h b/include/net/netfilter/nf_conntrack_l3proto.h index 96a58d8e1d3..3c58a2c4df2 100644 --- a/include/net/netfilter/nf_conntrack_l3proto.h +++ b/include/net/netfilter/nf_conntrack_l3proto.h @@ -58,13 +58,11 @@ struct nf_conntrack_l3proto /* * Called before tracking. - * *dataoff: offset of protocol header (TCP, UDP,...) in *pskb + * *dataoff: offset of protocol header (TCP, UDP,...) in skb * *protonum: protocol number */ - int (*prepare)(struct sk_buff **pskb, unsigned int hooknum, - unsigned int *dataoff, u_int8_t *protonum); - - u_int32_t (*get_features)(const struct nf_conntrack_tuple *tuple); + int (*get_l4proto)(const struct sk_buff *skb, unsigned int nhoff, + unsigned int *dataoff, u_int8_t *protonum); int (*tuple_to_nfattr)(struct sk_buff *skb, const struct nf_conntrack_tuple *t); @@ -91,8 +89,6 @@ extern struct nf_conntrack_l3proto *nf_ct_l3proto_find_get(u_int16_t l3proto); extern void nf_ct_l3proto_put(struct nf_conntrack_l3proto *p); /* Existing built-in protocols */ -extern struct nf_conntrack_l3proto nf_conntrack_l3proto_ipv4; -extern struct nf_conntrack_l3proto nf_conntrack_l3proto_ipv6; extern struct nf_conntrack_l3proto nf_conntrack_l3proto_generic; static inline struct nf_conntrack_l3proto * diff --git a/include/net/netfilter/nf_conntrack_tuple.h b/include/net/netfilter/nf_conntrack_tuple.h index 5d72b16e876..040dae5f0c9 100644 --- a/include/net/netfilter/nf_conntrack_tuple.h +++ b/include/net/netfilter/nf_conntrack_tuple.h @@ -100,6 +100,14 @@ struct nf_conntrack_tuple } dst; }; +struct nf_conntrack_tuple_mask +{ + struct { + union nf_conntrack_address u3; + union nf_conntrack_man_proto u; + } src; +}; + /* This is optimized opposed to a memset of the whole structure. Everything we * really care about is the source/destination unions */ #define NF_CT_TUPLE_U_BLANK(tuple) \ @@ -112,11 +120,11 @@ struct nf_conntrack_tuple #ifdef __KERNEL__ -#define NF_CT_DUMP_TUPLE(tp) \ -DEBUGP("tuple %p: %u %u " NIP6_FMT " %hu -> " NIP6_FMT " %hu\n", \ - (tp), (tp)->src.l3num, (tp)->dst.protonum, \ - NIP6(*(struct in6_addr *)(tp)->src.u3.all), ntohs((tp)->src.u.all), \ - NIP6(*(struct in6_addr *)(tp)->dst.u3.all), ntohs((tp)->dst.u.all)) +#define NF_CT_DUMP_TUPLE(tp) \ +pr_debug("tuple %p: %u %u " NIP6_FMT " %hu -> " NIP6_FMT " %hu\n", \ + (tp), (tp)->src.l3num, (tp)->dst.protonum, \ + NIP6(*(struct in6_addr *)(tp)->src.u3.all), ntohs((tp)->src.u.all), \ + NIP6(*(struct in6_addr *)(tp)->dst.u3.all), ntohs((tp)->dst.u.all)) /* If we're the first tuple, it's the original dir. */ #define NF_CT_DIRECTION(h) \ @@ -125,8 +133,7 @@ DEBUGP("tuple %p: %u %u " NIP6_FMT " %hu -> " NIP6_FMT " %hu\n", \ /* Connections have two entries in the hash table: one for each way */ struct nf_conntrack_tuple_hash { - struct list_head list; - + struct hlist_node hnode; struct nf_conntrack_tuple tuple; }; @@ -162,31 +169,44 @@ static inline int nf_ct_tuple_equal(const struct nf_conntrack_tuple *t1, return nf_ct_tuple_src_equal(t1, t2) && nf_ct_tuple_dst_equal(t1, t2); } +static inline int nf_ct_tuple_mask_equal(const struct nf_conntrack_tuple_mask *m1, + const struct nf_conntrack_tuple_mask *m2) +{ + return (m1->src.u3.all[0] == m2->src.u3.all[0] && + m1->src.u3.all[1] == m2->src.u3.all[1] && + m1->src.u3.all[2] == m2->src.u3.all[2] && + m1->src.u3.all[3] == m2->src.u3.all[3] && + m1->src.u.all == m2->src.u.all); +} + +static inline int nf_ct_tuple_src_mask_cmp(const struct nf_conntrack_tuple *t1, + const struct nf_conntrack_tuple *t2, + const struct nf_conntrack_tuple_mask *mask) +{ + int count; + + for (count = 0; count < NF_CT_TUPLE_L3SIZE; count++) { + if ((t1->src.u3.all[count] ^ t2->src.u3.all[count]) & + mask->src.u3.all[count]) + return 0; + } + + if ((t1->src.u.all ^ t2->src.u.all) & mask->src.u.all) + return 0; + + if (t1->src.l3num != t2->src.l3num || + t1->dst.protonum != t2->dst.protonum) + return 0; + + return 1; +} + static inline int nf_ct_tuple_mask_cmp(const struct nf_conntrack_tuple *t, const struct nf_conntrack_tuple *tuple, - const struct nf_conntrack_tuple *mask) + const struct nf_conntrack_tuple_mask *mask) { - int count = 0; - - for (count = 0; count < NF_CT_TUPLE_L3SIZE; count++){ - if ((t->src.u3.all[count] ^ tuple->src.u3.all[count]) & - mask->src.u3.all[count]) - return 0; - } - - for (count = 0; count < NF_CT_TUPLE_L3SIZE; count++){ - if ((t->dst.u3.all[count] ^ tuple->dst.u3.all[count]) & - mask->dst.u3.all[count]) - return 0; - } - - if ((t->src.u.all ^ tuple->src.u.all) & mask->src.u.all || - (t->dst.u.all ^ tuple->dst.u.all) & mask->dst.u.all || - (t->src.l3num ^ tuple->src.l3num) & mask->src.l3num || - (t->dst.protonum ^ tuple->dst.protonum) & mask->dst.protonum) - return 0; - - return 1; + return nf_ct_tuple_src_mask_cmp(t, tuple, mask) && + nf_ct_tuple_dst_equal(t, tuple); } #endif /* _NF_CONNTRACK_TUPLE_H */ diff --git a/include/net/netfilter/nf_nat.h b/include/net/netfilter/nf_nat.h index bc57dd7b9b5..6ae52f7c9f5 100644 --- a/include/net/netfilter/nf_nat.h +++ b/include/net/netfilter/nf_nat.h @@ -51,16 +51,31 @@ struct nf_nat_multi_range_compat #ifdef __KERNEL__ #include <linux/list.h> +#include <linux/netfilter/nf_conntrack_pptp.h> +#include <net/netfilter/nf_conntrack_extend.h> -/* The structure embedded in the conntrack structure. */ -struct nf_nat_info +/* per conntrack: nat application helper private data */ +union nf_conntrack_nat_help { - struct list_head bysource; - struct nf_nat_seq seq[IP_CT_DIR_MAX]; + /* insert nat helper private data here */ + struct nf_nat_pptp nat_pptp_info; }; struct nf_conn; +/* The structure embedded in the conntrack structure. */ +struct nf_conn_nat +{ + struct hlist_node bysource; + struct nf_nat_seq seq[IP_CT_DIR_MAX]; + struct nf_conn *ct; + union nf_conntrack_nat_help help; +#if defined(CONFIG_IP_NF_TARGET_MASQUERADE) || \ + defined(CONFIG_IP_NF_TARGET_MASQUERADE_MODULE) + int masq_index; +#endif +}; + /* Set up the info structure to map into this range. */ extern unsigned int nf_nat_setup_info(struct nf_conn *ct, const struct nf_nat_range *range, @@ -70,7 +85,10 @@ extern unsigned int nf_nat_setup_info(struct nf_conn *ct, extern int nf_nat_used_tuple(const struct nf_conntrack_tuple *tuple, const struct nf_conn *ignored_conntrack); -extern int nf_nat_module_is_loaded; +static inline struct nf_conn_nat *nfct_nat(const struct nf_conn *ct) +{ + return nf_ct_ext_find(ct, NF_CT_EXT_NAT); +} #else /* !__KERNEL__: iptables wants this to compile. */ #define nf_nat_multi_range nf_nat_multi_range_compat diff --git a/include/net/netfilter/nf_nat_core.h b/include/net/netfilter/nf_nat_core.h index 9778ffa9344..c3cd127ba4b 100644 --- a/include/net/netfilter/nf_nat_core.h +++ b/include/net/netfilter/nf_nat_core.h @@ -2,6 +2,7 @@ #define _NF_NAT_CORE_H #include <linux/list.h> #include <net/netfilter/nf_conntrack.h> +#include <net/netfilter/nf_nat.h> /* This header used to share core functionality between the standalone NAT module, and the compatibility layer's use of NAT for masquerading. */ diff --git a/include/net/netlabel.h b/include/net/netlabel.h index 83da7e1f0d3..9b7d6f2ac9a 100644 --- a/include/net/netlabel.h +++ b/include/net/netlabel.h @@ -332,17 +332,15 @@ static inline int netlbl_secattr_catmap_setrng( */ #ifdef CONFIG_NETLABEL -int netlbl_socket_setattr(const struct socket *sock, - const struct netlbl_lsm_secattr *secattr); +int netlbl_sock_setattr(struct sock *sk, + const struct netlbl_lsm_secattr *secattr); int netlbl_sock_getattr(struct sock *sk, struct netlbl_lsm_secattr *secattr); -int netlbl_socket_getattr(const struct socket *sock, - struct netlbl_lsm_secattr *secattr); int netlbl_skbuff_getattr(const struct sk_buff *skb, struct netlbl_lsm_secattr *secattr); void netlbl_skbuff_err(struct sk_buff *skb, int error); #else -static inline int netlbl_socket_setattr(const struct socket *sock, +static inline int netlbl_sock_setattr(struct sock *sk, const struct netlbl_lsm_secattr *secattr) { return -ENOSYS; @@ -354,12 +352,6 @@ static inline int netlbl_sock_getattr(struct sock *sk, return -ENOSYS; } -static inline int netlbl_socket_getattr(const struct socket *sock, - struct netlbl_lsm_secattr *secattr) -{ - return -ENOSYS; -} - static inline int netlbl_skbuff_getattr(const struct sk_buff *skb, struct netlbl_lsm_secattr *secattr) { diff --git a/include/net/netlink.h b/include/net/netlink.h index 0bf325c29af..d7b824be542 100644 --- a/include/net/netlink.h +++ b/include/net/netlink.h @@ -118,6 +118,9 @@ * Nested Attributes Construction: * nla_nest_start(skb, type) start a nested attribute * nla_nest_end(skb, nla) finalize a nested attribute + * nla_nest_compat_start(skb, type, start a nested compat attribute + * len, data) + * nla_nest_compat_end(skb, type) finalize a nested compat attribute * nla_nest_cancel(skb, nla) cancel nested attribute construction * * Attribute Length Calculations: @@ -152,6 +155,7 @@ * nla_find_nested() find attribute in nested attributes * nla_parse() parse and validate stream of attrs * nla_parse_nested() parse nested attribuets + * nla_parse_nested_compat() parse nested compat attributes * nla_for_each_attr() loop over all attributes * nla_for_each_nested() loop over the nested attributes *========================================================================= @@ -170,6 +174,7 @@ enum { NLA_FLAG, NLA_MSECS, NLA_NESTED, + NLA_NESTED_COMPAT, NLA_NUL_STRING, NLA_BINARY, __NLA_TYPE_MAX, @@ -190,6 +195,7 @@ enum { * NLA_NUL_STRING Maximum length of string (excluding NUL) * NLA_FLAG Unused * NLA_BINARY Maximum length of attribute payload + * NLA_NESTED_COMPAT Exact length of structure payload * All other Exact length of attribute payload * * Example: @@ -222,10 +228,10 @@ extern int nlmsg_notify(struct sock *sk, struct sk_buff *skb, gfp_t flags); extern int nla_validate(struct nlattr *head, int len, int maxtype, - struct nla_policy *policy); + const struct nla_policy *policy); extern int nla_parse(struct nlattr *tb[], int maxtype, struct nlattr *head, int len, - struct nla_policy *policy); + const struct nla_policy *policy); extern struct nlattr * nla_find(struct nlattr *head, int len, int attrtype); extern size_t nla_strlcpy(char *dst, const struct nlattr *nla, size_t dstsize); @@ -360,7 +366,7 @@ static inline struct nlmsghdr *nlmsg_next(struct nlmsghdr *nlh, int *remaining) */ static inline int nlmsg_parse(struct nlmsghdr *nlh, int hdrlen, struct nlattr *tb[], int maxtype, - struct nla_policy *policy) + const struct nla_policy *policy) { if (nlh->nlmsg_len < nlmsg_msg_size(hdrlen)) return -EINVAL; @@ -392,7 +398,7 @@ static inline struct nlattr *nlmsg_find_attr(struct nlmsghdr *nlh, * @policy: validation policy */ static inline int nlmsg_validate(struct nlmsghdr *nlh, int hdrlen, int maxtype, - struct nla_policy *policy) + const struct nla_policy *policy) { if (nlh->nlmsg_len < nlmsg_msg_size(hdrlen)) return -EINVAL; @@ -729,10 +735,43 @@ static inline struct nlattr *nla_find_nested(struct nlattr *nla, int attrtype) */ static inline int nla_parse_nested(struct nlattr *tb[], int maxtype, struct nlattr *nla, - struct nla_policy *policy) + const struct nla_policy *policy) { return nla_parse(tb, maxtype, nla_data(nla), nla_len(nla), policy); } + +/** + * nla_parse_nested_compat - parse nested compat attributes + * @tb: destination array with maxtype+1 elements + * @maxtype: maximum attribute type to be expected + * @nla: attribute containing the nested attributes + * @data: pointer to point to contained structure + * @len: length of contained structure + * @policy: validation policy + * + * Parse a nested compat attribute. The compat attribute contains a structure + * and optionally a set of nested attributes. On success the data pointer + * points to the nested data and tb contains the parsed attributes + * (see nla_parse). + */ +static inline int __nla_parse_nested_compat(struct nlattr *tb[], int maxtype, + struct nlattr *nla, + const struct nla_policy *policy, + int len) +{ + if (nla_len(nla) < len) + return -1; + if (nla_len(nla) >= NLA_ALIGN(len) + sizeof(struct nlattr)) + return nla_parse_nested(tb, maxtype, + nla_data(nla) + NLA_ALIGN(len), + policy); + memset(tb, 0, sizeof(struct nlattr *) * (maxtype + 1)); + return 0; +} + +#define nla_parse_nested_compat(tb, maxtype, nla, policy, data, len) \ +({ data = nla_len(nla) >= len ? nla_data(nla) : NULL; \ + __nla_parse_nested_compat(tb, maxtype, nla, policy, len); }) /** * nla_put_u8 - Add a u16 netlink attribute to a socket buffer * @skb: socket buffer to add attribute to @@ -965,6 +1004,51 @@ static inline int nla_nest_end(struct sk_buff *skb, struct nlattr *start) } /** + * nla_nest_compat_start - Start a new level of nested compat attributes + * @skb: socket buffer to add attributes to + * @attrtype: attribute type of container + * @attrlen: length of structure + * @data: pointer to structure + * + * Start a nested compat attribute that contains both a structure and + * a set of nested attributes. + * + * Returns the container attribute + */ +static inline struct nlattr *nla_nest_compat_start(struct sk_buff *skb, + int attrtype, int attrlen, + const void *data) +{ + struct nlattr *start = (struct nlattr *)skb_tail_pointer(skb); + + if (nla_put(skb, attrtype, attrlen, data) < 0) + return NULL; + if (nla_nest_start(skb, attrtype) == NULL) { + nlmsg_trim(skb, start); + return NULL; + } + return start; +} + +/** + * nla_nest_compat_end - Finalize nesting of compat attributes + * @skb: socket buffer the attribtues are stored in + * @start: container attribute + * + * Corrects the container attribute header to include the all + * appeneded attributes. + * + * Returns the total data length of the skb. + */ +static inline int nla_nest_compat_end(struct sk_buff *skb, struct nlattr *start) +{ + struct nlattr *nest = (void *)start + NLMSG_ALIGN(start->nla_len); + + start->nla_len = skb_tail_pointer(skb) - (unsigned char *)start; + return nla_nest_end(skb, nest); +} + +/** * nla_nest_cancel - Cancel nesting of attributes * @skb: socket buffer the message is stored in * @start: container attribute @@ -990,7 +1074,7 @@ static inline int nla_nest_cancel(struct sk_buff *skb, struct nlattr *start) * Returns 0 on success or a negative error code. */ static inline int nla_validate_nested(struct nlattr *start, int maxtype, - struct nla_policy *policy) + const struct nla_policy *policy) { return nla_validate(nla_data(start), nla_len(start), maxtype, policy); } diff --git a/include/net/pkt_cls.h b/include/net/pkt_cls.h index 4129df70807..7968b1d6636 100644 --- a/include/net/pkt_cls.h +++ b/include/net/pkt_cls.h @@ -65,8 +65,6 @@ struct tcf_exts { #ifdef CONFIG_NET_CLS_ACT struct tc_action *action; -#elif defined CONFIG_NET_CLS_POLICE - struct tcf_police *police; #endif }; @@ -91,8 +89,6 @@ tcf_exts_is_predicative(struct tcf_exts *exts) { #ifdef CONFIG_NET_CLS_ACT return !!exts->action; -#elif defined CONFIG_NET_CLS_POLICE - return !!exts->police; #else return 0; #endif @@ -129,11 +125,7 @@ tcf_exts_exec(struct sk_buff *skb, struct tcf_exts *exts, #ifdef CONFIG_NET_CLS_ACT if (exts->action) return tcf_action_exec(skb, exts->action, res); -#elif defined CONFIG_NET_CLS_POLICE - if (exts->police) - return tcf_police(skb, exts->police); #endif - return 0; } @@ -306,6 +298,8 @@ static inline int tcf_em_tree_match(struct sk_buff *skb, return 1; } +#define MODULE_ALIAS_TCF_EMATCH(kind) MODULE_ALIAS("ematch-kind-" __stringify(kind)) + #else /* CONFIG_NET_EMATCH */ struct tcf_ematch_tree diff --git a/include/net/pkt_sched.h b/include/net/pkt_sched.h index 5754d53d9ef..9e22526e80e 100644 --- a/include/net/pkt_sched.h +++ b/include/net/pkt_sched.h @@ -89,8 +89,10 @@ static inline void qdisc_run(struct net_device *dev) __qdisc_run(dev); } +extern int tc_classify_compat(struct sk_buff *skb, struct tcf_proto *tp, + struct tcf_result *res); extern int tc_classify(struct sk_buff *skb, struct tcf_proto *tp, - struct tcf_result *res); + struct tcf_result *res); /* Calculate maximal size of packet seen by hard_start_xmit routine of this device. diff --git a/include/net/rawv6.h b/include/net/rawv6.h index af8960878ef..a5819891d52 100644 --- a/include/net/rawv6.h +++ b/include/net/rawv6.h @@ -3,6 +3,8 @@ #ifdef __KERNEL__ +#include <net/protocol.h> + #define RAWV6_HTABLE_SIZE MAX_INET_PROTOS extern struct hlist_head raw_v6_htable[RAWV6_HTABLE_SIZE]; extern rwlock_t raw_v6_lock; @@ -23,6 +25,13 @@ extern void rawv6_err(struct sock *sk, int type, int code, int offset, __be32 info); +#if defined(CONFIG_IPV6_MIP6) || defined(CONFIG_IPV6_MIP6_MODULE) +int rawv6_mh_filter_register(int (*filter)(struct sock *sock, + struct sk_buff *skb)); +int rawv6_mh_filter_unregister(int (*filter)(struct sock *sock, + struct sk_buff *skb)); +#endif + #endif #endif diff --git a/include/net/route.h b/include/net/route.h index 749e4dfe5ff..f7ce6259f86 100644 --- a/include/net/route.h +++ b/include/net/route.h @@ -62,7 +62,6 @@ struct rtable unsigned rt_flags; __u16 rt_type; - __u16 rt_multipath_alg; __be32 rt_dst; /* Path destination */ __be32 rt_src; /* Path source */ @@ -136,7 +135,7 @@ static inline void ip_rt_put(struct rtable * rt) #define IPTOS_RT_MASK (IPTOS_TOS_MASK & ~3) -extern __u8 ip_tos2prio[16]; +extern const __u8 ip_tos2prio[16]; static inline char rt_tos2priority(u8 tos) { diff --git a/include/net/rtnetlink.h b/include/net/rtnetlink.h index 3b3d4745618..3861c05cdf0 100644 --- a/include/net/rtnetlink.h +++ b/include/net/rtnetlink.h @@ -22,4 +22,62 @@ static inline int rtnl_msg_family(struct nlmsghdr *nlh) return AF_UNSPEC; } +/** + * struct rtnl_link_ops - rtnetlink link operations + * + * @list: Used internally + * @kind: Identifier + * @maxtype: Highest device specific netlink attribute number + * @policy: Netlink policy for device specific attribute validation + * @validate: Optional validation function for netlink/changelink parameters + * @priv_size: sizeof net_device private space + * @setup: net_device setup function + * @newlink: Function for configuring and registering a new device + * @changelink: Function for changing parameters of an existing device + * @dellink: Function to remove a device + * @get_size: Function to calculate required room for dumping device + * specific netlink attributes + * @fill_info: Function to dump device specific netlink attributes + * @get_xstats_size: Function to calculate required room for dumping devic + * specific statistics + * @fill_xstats: Function to dump device specific statistics + */ +struct rtnl_link_ops { + struct list_head list; + + const char *kind; + + size_t priv_size; + void (*setup)(struct net_device *dev); + + int maxtype; + const struct nla_policy *policy; + int (*validate)(struct nlattr *tb[], + struct nlattr *data[]); + + int (*newlink)(struct net_device *dev, + struct nlattr *tb[], + struct nlattr *data[]); + int (*changelink)(struct net_device *dev, + struct nlattr *tb[], + struct nlattr *data[]); + void (*dellink)(struct net_device *dev); + + size_t (*get_size)(const struct net_device *dev); + int (*fill_info)(struct sk_buff *skb, + const struct net_device *dev); + + size_t (*get_xstats_size)(const struct net_device *dev); + int (*fill_xstats)(struct sk_buff *skb, + const struct net_device *dev); +}; + +extern int __rtnl_link_register(struct rtnl_link_ops *ops); +extern void __rtnl_link_unregister(struct rtnl_link_ops *ops); + +extern int rtnl_link_register(struct rtnl_link_ops *ops); +extern void rtnl_link_unregister(struct rtnl_link_ops *ops); + +#define MODULE_ALIAS_RTNL_LINK(kind) MODULE_ALIAS("rtnl-link-" kind) + #endif diff --git a/include/net/sch_generic.h b/include/net/sch_generic.h index 1b8e35197eb..8a67f24cbe0 100644 --- a/include/net/sch_generic.h +++ b/include/net/sch_generic.h @@ -290,7 +290,7 @@ static inline int qdisc_reshape_fail(struct sk_buff *skb, struct Qdisc *sch) { sch->qstats.drops++; -#ifdef CONFIG_NET_CLS_POLICE +#ifdef CONFIG_NET_CLS_ACT if (sch->reshape_fail == NULL || sch->reshape_fail(skb, sch)) goto drop; diff --git a/include/net/sctp/sctp.h b/include/net/sctp/sctp.h index dda72bf5b9b..16baef4dab7 100644 --- a/include/net/sctp/sctp.h +++ b/include/net/sctp/sctp.h @@ -503,6 +503,13 @@ static inline int sctp_frag_point(const struct sctp_sock *sp, int pmtu) return frag; } +static inline void sctp_assoc_pending_pmtu(struct sctp_association *asoc) +{ + + sctp_assoc_sync_pmtu(asoc); + asoc->pmtu_pending = 0; +} + /* Walk through a list of TLV parameters. Don't trust the * individual parameter lengths and instead depend on * the chunk length to indicate when to stop. Make sure diff --git a/include/net/sctp/structs.h b/include/net/sctp/structs.h index 5e81984b847..ee4559b1130 100644 --- a/include/net/sctp/structs.h +++ b/include/net/sctp/structs.h @@ -912,6 +912,9 @@ struct sctp_transport { */ __u16 pathmaxrxt; + /* is the Path MTU update pending on this tranport */ + __u8 pmtu_pending; + /* PMTU : The current known path MTU. */ __u32 pathmtu; @@ -1006,6 +1009,7 @@ void sctp_transport_raise_cwnd(struct sctp_transport *, __u32, __u32); void sctp_transport_lower_cwnd(struct sctp_transport *, sctp_lower_cwnd_t); unsigned long sctp_transport_timeout(struct sctp_transport *); void sctp_transport_reset(struct sctp_transport *); +void sctp_transport_update_pmtu(struct sctp_transport *, u32); /* This is the structure we use to queue packets as they come into @@ -1565,6 +1569,9 @@ struct sctp_association { */ __u16 pathmaxrxt; + /* Flag that path mtu update is pending */ + __u8 pmtu_pending; + /* Association : The smallest PMTU discovered for all of the * PMTU : peer's transport addresses. */ diff --git a/include/net/sock.h b/include/net/sock.h index 689b886038d..dfeb8b13024 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -218,13 +218,13 @@ struct sock { atomic_t sk_rmem_alloc; atomic_t sk_wmem_alloc; atomic_t sk_omem_alloc; + int sk_sndbuf; struct sk_buff_head sk_receive_queue; struct sk_buff_head sk_write_queue; struct sk_buff_head sk_async_wait_queue; int sk_wmem_queued; int sk_forward_alloc; gfp_t sk_allocation; - int sk_sndbuf; int sk_route_caps; int sk_gso_type; int sk_rcvlowat; diff --git a/include/net/tcp.h b/include/net/tcp.h index e22b4f0305a..a8af9ae0017 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -254,6 +254,12 @@ static inline int between(__u32 seq1, __u32 seq2, __u32 seq3) return seq3 - seq2 >= seq1 - seq2; } +static inline int tcp_too_many_orphans(struct sock *sk, int num) +{ + return (num > sysctl_tcp_max_orphans) || + (sk->sk_wmem_queued > SOCK_MIN_SNDBUF && + atomic_read(&tcp_memory_allocated) > sysctl_tcp_mem[2]); +} extern struct proto tcp_prot; diff --git a/include/net/tipc/tipc_port.h b/include/net/tipc/tipc_port.h index 333bba6dc52..cfc4ba46de8 100644 --- a/include/net/tipc/tipc_port.h +++ b/include/net/tipc/tipc_port.h @@ -1,8 +1,8 @@ /* * include/net/tipc/tipc_port.h: Include file for privileged access to TIPC ports * - * Copyright (c) 1994-2006, Ericsson AB - * Copyright (c) 2005, Wind River Systems + * Copyright (c) 1994-2007, Ericsson AB + * Copyright (c) 2005-2007, Wind River Systems * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -55,6 +55,7 @@ * @conn_unacked: number of unacknowledged messages received from peer port * @published: non-zero if port has one or more associated names * @congested: non-zero if cannot send because of link or port congestion + * @max_pkt: maximum packet size "hint" used when building messages sent by port * @ref: unique reference to port in TIPC object registry * @phdr: preformatted message header used when sending messages */ @@ -68,6 +69,7 @@ struct tipc_port { u32 conn_unacked; int published; u32 congested; + u32 max_pkt; u32 ref; struct tipc_msg phdr; }; diff --git a/include/net/udp.h b/include/net/udp.h index 496f89d45c8..98755ebaf16 100644 --- a/include/net/udp.h +++ b/include/net/udp.h @@ -119,16 +119,9 @@ static inline void udp_lib_close(struct sock *sk, long timeout) } -struct udp_get_port_ops { - int (*saddr_cmp)(const struct sock *sk1, const struct sock *sk2); - int (*saddr_any)(const struct sock *sk); - unsigned int (*hash_port_and_rcv_saddr)(__u16 port, - const struct sock *sk); -}; - /* net/ipv4/udp.c */ extern int udp_get_port(struct sock *sk, unsigned short snum, - const struct udp_get_port_ops *ops); + int (*saddr_cmp)(const struct sock *, const struct sock *)); extern void udp_err(struct sk_buff *, u32); extern int udp_sendmsg(struct kiocb *iocb, struct sock *sk, diff --git a/include/net/udplite.h b/include/net/udplite.h index 50b4b424d1c..635b0eafca9 100644 --- a/include/net/udplite.h +++ b/include/net/udplite.h @@ -120,5 +120,5 @@ static inline __wsum udplite_csum_outgoing(struct sock *sk, struct sk_buff *skb) extern void udplite4_register(void); extern int udplite_get_port(struct sock *sk, unsigned short snum, - const struct udp_get_port_ops *ops); + int (*scmp)(const struct sock *, const struct sock *)); #endif /* _UDPLITE_H */ diff --git a/include/net/xfrm.h b/include/net/xfrm.h index 39ef925d39d..ae959e95017 100644 --- a/include/net/xfrm.h +++ b/include/net/xfrm.h @@ -19,9 +19,19 @@ #include <net/ipv6.h> #include <net/ip6_fib.h> +#define XFRM_PROTO_ESP 50 +#define XFRM_PROTO_AH 51 +#define XFRM_PROTO_COMP 108 +#define XFRM_PROTO_IPIP 4 +#define XFRM_PROTO_IPV6 41 +#define XFRM_PROTO_ROUTING IPPROTO_ROUTING +#define XFRM_PROTO_DSTOPTS IPPROTO_DSTOPTS + #define XFRM_ALIGN8(len) (((len) + 7) & ~7) #define MODULE_ALIAS_XFRM_MODE(family, encap) \ MODULE_ALIAS("xfrm-mode-" __stringify(family) "-" __stringify(encap)) +#define MODULE_ALIAS_XFRM_TYPE(family, proto) \ + MODULE_ALIAS("xfrm-type-" __stringify(family) "-" __stringify(proto)) extern struct sock *xfrm_nl; extern u32 sysctl_xfrm_aevent_etime; @@ -237,7 +247,6 @@ extern int xfrm_policy_register_afinfo(struct xfrm_policy_afinfo *afinfo); extern int xfrm_policy_unregister_afinfo(struct xfrm_policy_afinfo *afinfo); extern void km_policy_notify(struct xfrm_policy *xp, int dir, struct km_event *c); extern void km_state_notify(struct xfrm_state *x, struct km_event *c); -#define XFRM_ACQ_EXPIRES 30 struct xfrm_tmpl; extern int km_query(struct xfrm_state *x, struct xfrm_tmpl *t, struct xfrm_policy *pol); @@ -510,11 +519,9 @@ __be16 xfrm_flowi_sport(struct flowi *fl) case IPPROTO_ICMPV6: port = htons(fl->fl_icmp_type); break; -#ifdef CONFIG_IPV6_MIP6 case IPPROTO_MH: port = htons(fl->fl_mh_type); break; -#endif default: port = 0; /*XXX*/ } @@ -921,6 +928,10 @@ extern struct xfrm_state *xfrm_state_find(xfrm_address_t *daddr, xfrm_address_t struct flowi *fl, struct xfrm_tmpl *tmpl, struct xfrm_policy *pol, int *err, unsigned short family); +extern struct xfrm_state * xfrm_stateonly_find(xfrm_address_t *daddr, + xfrm_address_t *saddr, + unsigned short family, + u8 mode, u8 proto, u32 reqid); extern int xfrm_state_check_expire(struct xfrm_state *x); extern void xfrm_state_insert(struct xfrm_state *x); extern int xfrm_state_add(struct xfrm_state *x); @@ -965,7 +976,7 @@ struct xfrmk_spdinfo { extern struct xfrm_state *xfrm_find_acq_byseq(u32 seq); extern int xfrm_state_delete(struct xfrm_state *x); -extern void xfrm_state_flush(u8 proto, struct xfrm_audit *audit_info); +extern int xfrm_state_flush(u8 proto, struct xfrm_audit *audit_info); extern void xfrm_sad_getinfo(struct xfrmk_sadinfo *si); extern void xfrm_spd_getinfo(struct xfrmk_spdinfo *si); extern int xfrm_replay_check(struct xfrm_state *x, __be32 seq); @@ -992,7 +1003,7 @@ extern int xfrm6_find_1stfragopt(struct xfrm_state *x, struct sk_buff *skb, u8 **prevhdr); #ifdef CONFIG_XFRM -extern int xfrm4_rcv_encap(struct sk_buff *skb, __u16 encap_type); +extern int xfrm4_udp_encap_rcv(struct sock *sk, struct sk_buff *skb); extern int xfrm_user_policy(struct sock *sk, int optname, u8 __user *optval, int optlen); extern int xfrm_dst_lookup(struct xfrm_dst **dst, struct flowi *fl, unsigned short family); #else @@ -1001,12 +1012,13 @@ static inline int xfrm_user_policy(struct sock *sk, int optname, u8 __user *optv return -ENOPROTOOPT; } -static inline int xfrm4_rcv_encap(struct sk_buff *skb, __u16 encap_type) +static inline int xfrm4_udp_encap_rcv(struct sock *sk, struct sk_buff *skb) { /* should not happen */ kfree_skb(skb); return 0; } + static inline int xfrm_dst_lookup(struct xfrm_dst **dst, struct flowi *fl, unsigned short family) { return -EINVAL; @@ -1021,13 +1033,13 @@ struct xfrm_policy *xfrm_policy_bysel_ctx(u8 type, int dir, struct xfrm_sec_ctx *ctx, int delete, int *err); struct xfrm_policy *xfrm_policy_byid(u8, int dir, u32 id, int delete, int *err); -void xfrm_policy_flush(u8 type, struct xfrm_audit *audit_info); +int xfrm_policy_flush(u8 type, struct xfrm_audit *audit_info); u32 xfrm_get_acqseq(void); void xfrm_alloc_spi(struct xfrm_state *x, __be32 minspi, __be32 maxspi); struct xfrm_state * xfrm_find_acq(u8 mode, u32 reqid, u8 proto, xfrm_address_t *daddr, xfrm_address_t *saddr, int create, unsigned short family); -extern void xfrm_policy_flush(u8 type, struct xfrm_audit *audit_info); +extern int xfrm_policy_flush(u8 type, struct xfrm_audit *audit_info); extern int xfrm_sk_policy_insert(struct sock *sk, int dir, struct xfrm_policy *pol); extern int xfrm_bundle_ok(struct xfrm_policy *pol, struct xfrm_dst *xdst, struct flowi *fl, int family, int strict); diff --git a/include/pcmcia/ciscode.h b/include/pcmcia/ciscode.h index eae7e2e8449..ad6e278ba7f 100644 --- a/include/pcmcia/ciscode.h +++ b/include/pcmcia/ciscode.h @@ -126,4 +126,6 @@ #define MANFID_POSSIO 0x030c #define PRODID_POSSIO_GCC 0x0003 +#define MANFID_NEC 0x0010 + #endif /* _LINUX_CISCODE_H */ diff --git a/include/rdma/ib_cm.h b/include/rdma/ib_cm.h index 5c070176d9a..12243e80c70 100644 --- a/include/rdma/ib_cm.h +++ b/include/rdma/ib_cm.h @@ -385,7 +385,6 @@ struct ib_cm_rep_param { u8 private_data_len; u8 responder_resources; u8 initiator_depth; - u8 target_ack_delay; u8 failover_accepted; u8 flow_control; u8 rnr_retry_count; diff --git a/include/rdma/ib_mad.h b/include/rdma/ib_mad.h index 739fa4d0e53..30712ddd8a5 100644 --- a/include/rdma/ib_mad.h +++ b/include/rdma/ib_mad.h @@ -111,6 +111,9 @@ #define IB_QP1_QKEY 0x80010000 #define IB_QP_SET_QKEY 0x80000000 +#define IB_DEFAULT_PKEY_PARTIAL 0x7FFF +#define IB_DEFAULT_PKEY_FULL 0xFFFF + enum { IB_MGMT_MAD_HDR = 24, IB_MGMT_MAD_DATA = 232, diff --git a/include/sound/version.h b/include/sound/version.h index 50ee4fd420f..8e5b2f0f594 100644 --- a/include/sound/version.h +++ b/include/sound/version.h @@ -1,3 +1,3 @@ /* include/version.h. Generated by alsa/ksync script. */ -#define CONFIG_SND_VERSION "1.0.14rc4" -#define CONFIG_SND_DATE " (Wed May 16 09:45:46 2007 UTC)" +#define CONFIG_SND_VERSION "1.0.14" +#define CONFIG_SND_DATE " (Thu May 31 09:03:25 2007 UTC)" |