diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-arm/arch-orion/irqs.h | 62 | ||||
| -rw-r--r-- | include/asm-arm/arch-orion/orion.h | 159 | ||||
| -rw-r--r-- | include/asm-arm/arch-orion5x/debug-macro.S (renamed from include/asm-arm/arch-orion/debug-macro.S) | 8 | ||||
| -rw-r--r-- | include/asm-arm/arch-orion5x/dma.h (renamed from include/asm-arm/arch-orion/dma.h) | 0 | ||||
| -rw-r--r-- | include/asm-arm/arch-orion5x/entry-macro.S (renamed from include/asm-arm/arch-orion/entry-macro.S) | 4 | ||||
| -rw-r--r-- | include/asm-arm/arch-orion5x/gpio.h (renamed from include/asm-arm/arch-orion/gpio.h) | 8 | ||||
| -rw-r--r-- | include/asm-arm/arch-orion5x/hardware.h (renamed from include/asm-arm/arch-orion/hardware.h) | 6 | ||||
| -rw-r--r-- | include/asm-arm/arch-orion5x/io.h (renamed from include/asm-arm/arch-orion/io.h) | 26 | ||||
| -rw-r--r-- | include/asm-arm/arch-orion5x/irqs.h | 62 | ||||
| -rw-r--r-- | include/asm-arm/arch-orion5x/memory.h (renamed from include/asm-arm/arch-orion/memory.h) | 2 | ||||
| -rw-r--r-- | include/asm-arm/arch-orion5x/orion5x.h | 159 | ||||
| -rw-r--r-- | include/asm-arm/arch-orion5x/system.h (renamed from include/asm-arm/arch-orion/system.h) | 8 | ||||
| -rw-r--r-- | include/asm-arm/arch-orion5x/timex.h (renamed from include/asm-arm/arch-orion/timex.h) | 4 | ||||
| -rw-r--r-- | include/asm-arm/arch-orion5x/uncompress.h (renamed from include/asm-arm/arch-orion/uncompress.h) | 4 | ||||
| -rw-r--r-- | include/asm-arm/arch-orion5x/vmalloc.h (renamed from include/asm-arm/arch-orion/vmalloc.h) | 2 |
15 files changed, 257 insertions, 257 deletions
diff --git a/include/asm-arm/arch-orion/irqs.h b/include/asm-arm/arch-orion/irqs.h deleted file mode 100644 index 70a2420456a..00000000000 --- a/include/asm-arm/arch-orion/irqs.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * include/asm-arm/arch-orion/irqs.h - * - * IRQ definitions for Orion SoC - * - * Maintainer: Tzachi Perelstein <tzachi@marvell.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -#include "orion.h" /* need GPIO_MAX */ - -/* - * Orion Main Interrupt Controller - */ -#define IRQ_ORION_BRIDGE 0 -#define IRQ_ORION_DOORBELL_H2C 1 -#define IRQ_ORION_DOORBELL_C2H 2 -#define IRQ_ORION_UART0 3 -#define IRQ_ORION_UART1 4 -#define IRQ_ORION_I2C 5 -#define IRQ_ORION_GPIO_0_7 6 -#define IRQ_ORION_GPIO_8_15 7 -#define IRQ_ORION_GPIO_16_23 8 -#define IRQ_ORION_GPIO_24_31 9 -#define IRQ_ORION_PCIE0_ERR 10 -#define IRQ_ORION_PCIE0_INT 11 -#define IRQ_ORION_USB1_CTRL 12 -#define IRQ_ORION_DEV_BUS_ERR 14 -#define IRQ_ORION_PCI_ERR 15 -#define IRQ_ORION_USB_BR_ERR 16 -#define IRQ_ORION_USB0_CTRL 17 -#define IRQ_ORION_ETH_RX 18 -#define IRQ_ORION_ETH_TX 19 -#define IRQ_ORION_ETH_MISC 20 -#define IRQ_ORION_ETH_SUM 21 -#define IRQ_ORION_ETH_ERR 22 -#define IRQ_ORION_IDMA_ERR 23 -#define IRQ_ORION_IDMA_0 24 -#define IRQ_ORION_IDMA_1 25 -#define IRQ_ORION_IDMA_2 26 -#define IRQ_ORION_IDMA_3 27 -#define IRQ_ORION_CESA 28 -#define IRQ_ORION_SATA 29 -#define IRQ_ORION_XOR0 30 -#define IRQ_ORION_XOR1 31 - -/* - * Orion General Purpose Pins - */ -#define IRQ_ORION_GPIO_START 32 -#define NR_GPIO_IRQS GPIO_MAX - -#define NR_IRQS (IRQ_ORION_GPIO_START + NR_GPIO_IRQS) - - -#endif diff --git a/include/asm-arm/arch-orion/orion.h b/include/asm-arm/arch-orion/orion.h deleted file mode 100644 index 01f1299472d..00000000000 --- a/include/asm-arm/arch-orion/orion.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * include/asm-arm/arch-orion/orion.h - * - * Generic definitions of Orion SoC flavors: - * Orion-1, Orion-NAS, Orion-VoIP, and Orion-2. - * - * Maintainer: Tzachi Perelstein <tzachi@marvell.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_ORION_H -#define __ASM_ARCH_ORION_H - -/***************************************************************************** - * Orion Address Maps - * - * phys - * e0000000 PCIe MEM space - * e8000000 PCI MEM space - * f0000000 PCIe WA space (Orion-1/Orion-NAS only) - * f1000000 on-chip peripheral registers - * f2000000 PCIe I/O space - * f2100000 PCI I/O space - * f4000000 device bus mappings (boot) - * fa000000 device bus mappings (cs0) - * fa800000 device bus mappings (cs2) - * fc000000 device bus mappings (cs0/cs1) - * - * virt phys size - * fdd00000 f1000000 1M on-chip peripheral registers - * fde00000 f2000000 1M PCIe I/O space - * fdf00000 f2100000 1M PCI I/O space - * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) - ****************************************************************************/ -#define ORION_REGS_PHYS_BASE 0xf1000000 -#define ORION_REGS_VIRT_BASE 0xfdd00000 -#define ORION_REGS_SIZE SZ_1M - -#define ORION_PCIE_IO_PHYS_BASE 0xf2000000 -#define ORION_PCIE_IO_VIRT_BASE 0xfde00000 -#define ORION_PCIE_IO_BUS_BASE 0x00000000 -#define ORION_PCIE_IO_SIZE SZ_1M - -#define ORION_PCI_IO_PHYS_BASE 0xf2100000 -#define ORION_PCI_IO_VIRT_BASE 0xfdf00000 -#define ORION_PCI_IO_BUS_BASE 0x00100000 -#define ORION_PCI_IO_SIZE SZ_1M - -/* Relevant only for Orion-1/Orion-NAS */ -#define ORION_PCIE_WA_PHYS_BASE 0xf0000000 -#define ORION_PCIE_WA_VIRT_BASE 0xfe000000 -#define ORION_PCIE_WA_SIZE SZ_16M - -#define ORION_PCIE_MEM_PHYS_BASE 0xe0000000 -#define ORION_PCIE_MEM_SIZE SZ_128M - -#define ORION_PCI_MEM_PHYS_BASE 0xe8000000 -#define ORION_PCI_MEM_SIZE SZ_128M - -/******************************************************************************* - * Supported Devices & Revisions - ******************************************************************************/ -/* Orion-1 (88F5181) */ -#define MV88F5181_DEV_ID 0x5181 -#define MV88F5181_REV_B1 3 -/* Orion-NAS (88F5182) */ -#define MV88F5182_DEV_ID 0x5182 -#define MV88F5182_REV_A2 2 -/* Orion-2 (88F5281) */ -#define MV88F5281_DEV_ID 0x5281 -#define MV88F5281_REV_D1 5 -#define MV88F5281_REV_D2 6 - -/******************************************************************************* - * Orion Registers Map - ******************************************************************************/ -#define ORION_DDR_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x00000) -#define ORION_DDR_REG(x) (ORION_DDR_VIRT_BASE | (x)) - -#define ORION_DEV_BUS_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x10000) -#define ORION_DEV_BUS_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x10000) -#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_VIRT_BASE | (x)) -#define I2C_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x1000) -#define UART0_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2000) -#define UART0_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2000) -#define UART1_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2100) -#define UART1_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2100) - -#define ORION_BRIDGE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x20000) -#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_VIRT_BASE | (x)) -#define TIMER_VIRT_BASE (ORION_BRIDGE_VIRT_BASE | 0x300) - -#define ORION_PCI_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x30000) -#define ORION_PCI_REG(x) (ORION_PCI_VIRT_BASE | (x)) - -#define ORION_PCIE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x40000) -#define ORION_PCIE_REG(x) (ORION_PCIE_VIRT_BASE | (x)) - -#define ORION_USB0_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x50000) -#define ORION_USB0_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x50000) -#define ORION_USB0_REG(x) (ORION_USB0_VIRT_BASE | (x)) - -#define ORION_ETH_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x70000) -#define ORION_ETH_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x70000) -#define ORION_ETH_REG(x) (ORION_ETH_VIRT_BASE | (x)) - -#define ORION_SATA_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x80000) -#define ORION_SATA_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x80000) -#define ORION_SATA_REG(x) (ORION_SATA_VIRT_BASE | (x)) - -#define ORION_USB1_PHYS_BASE (ORION_REGS_PHYS_BASE | 0xa0000) -#define ORION_USB1_VIRT_BASE (ORION_REGS_VIRT_BASE | 0xa0000) -#define ORION_USB1_REG(x) (ORION_USB1_VIRT_BASE | (x)) - -/******************************************************************************* - * Device Bus Registers - ******************************************************************************/ -#define MPP_0_7_CTRL ORION_DEV_BUS_REG(0x000) -#define MPP_8_15_CTRL ORION_DEV_BUS_REG(0x004) -#define MPP_16_19_CTRL ORION_DEV_BUS_REG(0x050) -#define MPP_DEV_CTRL ORION_DEV_BUS_REG(0x008) -#define MPP_RESET_SAMPLE ORION_DEV_BUS_REG(0x010) -#define GPIO_OUT ORION_DEV_BUS_REG(0x100) -#define GPIO_IO_CONF ORION_DEV_BUS_REG(0x104) -#define GPIO_BLINK_EN ORION_DEV_BUS_REG(0x108) -#define GPIO_IN_POL ORION_DEV_BUS_REG(0x10c) -#define GPIO_DATA_IN ORION_DEV_BUS_REG(0x110) -#define GPIO_EDGE_CAUSE ORION_DEV_BUS_REG(0x114) -#define GPIO_EDGE_MASK ORION_DEV_BUS_REG(0x118) -#define GPIO_LEVEL_MASK ORION_DEV_BUS_REG(0x11c) -#define DEV_BANK_0_PARAM ORION_DEV_BUS_REG(0x45c) -#define DEV_BANK_1_PARAM ORION_DEV_BUS_REG(0x460) -#define DEV_BANK_2_PARAM ORION_DEV_BUS_REG(0x464) -#define DEV_BANK_BOOT_PARAM ORION_DEV_BUS_REG(0x46c) -#define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0) -#define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0) -#define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4) -#define GPIO_MAX 32 - -/*************************************************************************** - * Orion CPU Bridge Registers - **************************************************************************/ -#define CPU_CONF ORION_BRIDGE_REG(0x100) -#define CPU_CTRL ORION_BRIDGE_REG(0x104) -#define CPU_RESET_MASK ORION_BRIDGE_REG(0x108) -#define CPU_SOFT_RESET ORION_BRIDGE_REG(0x10c) -#define POWER_MNG_CTRL_REG ORION_BRIDGE_REG(0x11C) -#define BRIDGE_CAUSE ORION_BRIDGE_REG(0x110) -#define BRIDGE_MASK ORION_BRIDGE_REG(0x114) -#define BRIDGE_INT_TIMER0 0x0002 -#define BRIDGE_INT_TIMER1 0x0004 -#define MAIN_IRQ_CAUSE ORION_BRIDGE_REG(0x200) -#define MAIN_IRQ_MASK ORION_BRIDGE_REG(0x204) - - -#endif diff --git a/include/asm-arm/arch-orion/debug-macro.S b/include/asm-arm/arch-orion5x/debug-macro.S index c847f8c9250..4f98f3ba292 100644 --- a/include/asm-arm/arch-orion/debug-macro.S +++ b/include/asm-arm/arch-orion5x/debug-macro.S @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/debug-macro.S + * include/asm-arm/arch-orion5x/debug-macro.S * * Debugging macro include header * @@ -8,13 +8,13 @@ * published by the Free Software Foundation. */ -#include <asm/arch/orion.h> +#include <asm/arch/orion5x.h> .macro addruart,rx mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? - ldreq \rx, =ORION_REGS_PHYS_BASE - ldrne \rx, =ORION_REGS_VIRT_BASE + ldreq \rx, =ORION5X_REGS_PHYS_BASE + ldrne \rx, =ORION5X_REGS_VIRT_BASE orr \rx, \rx, #0x00012000 .endm diff --git a/include/asm-arm/arch-orion/dma.h b/include/asm-arm/arch-orion5x/dma.h index 40a8c178f10..40a8c178f10 100644 --- a/include/asm-arm/arch-orion/dma.h +++ b/include/asm-arm/arch-orion5x/dma.h diff --git a/include/asm-arm/arch-orion/entry-macro.S b/include/asm-arm/arch-orion5x/entry-macro.S index cda096b2acf..d8ef54c0ee9 100644 --- a/include/asm-arm/arch-orion/entry-macro.S +++ b/include/asm-arm/arch-orion5x/entry-macro.S @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/entry-macro.S + * include/asm-arm/arch-orion5x/entry-macro.S * * Low-level IRQ helper macros for Orion platforms * @@ -8,7 +8,7 @@ * warranty of any kind, whether express or implied. */ -#include <asm/arch/orion.h> +#include <asm/arch/orion5x.h> .macro disable_fiq .endm diff --git a/include/asm-arm/arch-orion/gpio.h b/include/asm-arm/arch-orion5x/gpio.h index d66284f9a14..c85e498388b 100644 --- a/include/asm-arm/arch-orion/gpio.h +++ b/include/asm-arm/arch-orion5x/gpio.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/gpio.h + * include/asm-arm/arch-orion5x/gpio.h * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any @@ -12,17 +12,17 @@ extern int gpio_direction_input(unsigned pin); extern int gpio_direction_output(unsigned pin, int value); extern int gpio_get_value(unsigned pin); extern void gpio_set_value(unsigned pin, int value); -extern void orion_gpio_set_blink(unsigned pin, int blink); +extern void orion5x_gpio_set_blink(unsigned pin, int blink); extern void gpio_display(void); /* debug */ static inline int gpio_to_irq(int pin) { - return pin + IRQ_ORION_GPIO_START; + return pin + IRQ_ORION5X_GPIO_START; } static inline int irq_to_gpio(int irq) { - return irq - IRQ_ORION_GPIO_START; + return irq - IRQ_ORION5X_GPIO_START; } #include <asm-generic/gpio.h> /* cansleep wrappers */ diff --git a/include/asm-arm/arch-orion/hardware.h b/include/asm-arm/arch-orion5x/hardware.h index 998af6029c7..5d2d8e0b563 100644 --- a/include/asm-arm/arch-orion/hardware.h +++ b/include/asm-arm/arch-orion5x/hardware.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/hardware.h + * include/asm-arm/arch-orion5x/hardware.h * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -9,13 +9,13 @@ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H -#include "orion.h" +#include "orion5x.h" #define pcibios_assign_all_busses() 1 #define PCIBIOS_MIN_IO 0x00001000 #define PCIBIOS_MIN_MEM 0x01000000 -#define PCIMEM_BASE ORION_PCIE_MEM_PHYS_BASE +#define PCIMEM_BASE ORION5X_PCIE_MEM_PHYS_BASE #endif diff --git a/include/asm-arm/arch-orion/io.h b/include/asm-arm/arch-orion5x/io.h index 23820153b61..5148ab7ad1f 100644 --- a/include/asm-arm/arch-orion/io.h +++ b/include/asm-arm/arch-orion5x/io.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/io.h + * include/asm-arm/arch-orion5x/io.h * * Tzachi Perelstein <tzachi@marvell.com> * @@ -11,20 +11,20 @@ #ifndef __ASM_ARCH_IO_H #define __ASM_ARCH_IO_H -#include "orion.h" +#include "orion5x.h" #define IO_SPACE_LIMIT 0xffffffff -#define IO_SPACE_REMAP ORION_PCI_SYS_IO_BASE +#define IO_SPACE_REMAP ORION5X_PCI_SYS_IO_BASE static inline void __iomem * __arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype) { void __iomem *retval; - if (mtype == MT_DEVICE && size && paddr >= ORION_REGS_PHYS_BASE && - paddr + size <= ORION_REGS_PHYS_BASE + ORION_REGS_SIZE) { - retval = (void __iomem *)ORION_REGS_VIRT_BASE + - (paddr - ORION_REGS_PHYS_BASE); + if (mtype == MT_DEVICE && size && paddr >= ORION5X_REGS_PHYS_BASE && + paddr + size <= ORION5X_REGS_PHYS_BASE + ORION5X_REGS_SIZE) { + retval = (void __iomem *)ORION5X_REGS_VIRT_BASE + + (paddr - ORION5X_REGS_PHYS_BASE); } else { retval = __arm_ioremap(paddr, size, mtype); } @@ -35,8 +35,8 @@ __arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype) static inline void __arch_iounmap(void __iomem *addr) { - if (addr < (void __iomem *)ORION_REGS_VIRT_BASE || - addr >= (void __iomem *)(ORION_REGS_VIRT_BASE + ORION_REGS_SIZE)) + if (addr < (void __iomem *)ORION5X_REGS_VIRT_BASE || + addr >= (void __iomem *)(ORION5X_REGS_VIRT_BASE + ORION5X_REGS_SIZE)) __iounmap(addr); } @@ -54,15 +54,15 @@ static inline void __iomem *__io(unsigned long addr) /***************************************************************************** * Helpers to access Orion registers ****************************************************************************/ -#define orion_read(r) __raw_readl(r) -#define orion_write(r, val) __raw_writel(val, r) +#define orion5x_read(r) __raw_readl(r) +#define orion5x_write(r, val) __raw_writel(val, r) /* * These are not preempt-safe. Locks, if needed, must be taken * care of by the caller. */ -#define orion_setbits(r, mask) orion_write((r), orion_read(r) | (mask)) -#define orion_clrbits(r, mask) orion_write((r), orion_read(r) & ~(mask)) +#define orion5x_setbits(r, mask) orion5x_write((r), orion5x_read(r) | (mask)) +#define orion5x_clrbits(r, mask) orion5x_write((r), orion5x_read(r) & ~(mask)) #endif diff --git a/include/asm-arm/arch-orion5x/irqs.h b/include/asm-arm/arch-orion5x/irqs.h new file mode 100644 index 00000000000..abdd61a4833 --- /dev/null +++ b/include/asm-arm/arch-orion5x/irqs.h @@ -0,0 +1,62 @@ +/* + * include/asm-arm/arch-orion5x/irqs.h + * + * IRQ definitions for Orion SoC + * + * Maintainer: Tzachi Perelstein <tzachi@marvell.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +#include "orion5x.h" /* need GPIO_MAX */ + +/* + * Orion Main Interrupt Controller + */ +#define IRQ_ORION5X_BRIDGE 0 +#define IRQ_ORION5X_DOORBELL_H2C 1 +#define IRQ_ORION5X_DOORBELL_C2H 2 +#define IRQ_ORION5X_UART0 3 +#define IRQ_ORION5X_UART1 4 +#define IRQ_ORION5X_I2C 5 +#define IRQ_ORION5X_GPIO_0_7 6 +#define IRQ_ORION5X_GPIO_8_15 7 +#define IRQ_ORION5X_GPIO_16_23 8 +#define IRQ_ORION5X_GPIO_24_31 9 +#define IRQ_ORION5X_PCIE0_ERR 10 +#define IRQ_ORION5X_PCIE0_INT 11 +#define IRQ_ORION5X_USB1_CTRL 12 +#define IRQ_ORION5X_DEV_BUS_ERR 14 +#define IRQ_ORION5X_PCI_ERR 15 +#define IRQ_ORION5X_USB_BR_ERR 16 +#define IRQ_ORION5X_USB0_CTRL 17 +#define IRQ_ORION5X_ETH_RX 18 +#define IRQ_ORION5X_ETH_TX 19 +#define IRQ_ORION5X_ETH_MISC 20 +#define IRQ_ORION5X_ETH_SUM 21 +#define IRQ_ORION5X_ETH_ERR 22 +#define IRQ_ORION5X_IDMA_ERR 23 +#define IRQ_ORION5X_IDMA_0 24 +#define IRQ_ORION5X_IDMA_1 25 +#define IRQ_ORION5X_IDMA_2 26 +#define IRQ_ORION5X_IDMA_3 27 +#define IRQ_ORION5X_CESA 28 +#define IRQ_ORION5X_SATA 29 +#define IRQ_ORION5X_XOR0 30 +#define IRQ_ORION5X_XOR1 31 + +/* + * Orion General Purpose Pins + */ +#define IRQ_ORION5X_GPIO_START 32 +#define NR_GPIO_IRQS GPIO_MAX + +#define NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS) + + +#endif diff --git a/include/asm-arm/arch-orion/memory.h b/include/asm-arm/arch-orion5x/memory.h index d9300d62a53..80053a7afc7 100644 --- a/include/asm-arm/arch-orion/memory.h +++ b/include/asm-arm/arch-orion5x/memory.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/memory.h + * include/asm-arm/arch-orion5x/memory.h * * Marvell Orion memory definitions */ diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h new file mode 100644 index 00000000000..206ddd71e19 --- /dev/null +++ b/include/asm-arm/arch-orion5x/orion5x.h @@ -0,0 +1,159 @@ +/* + * include/asm-arm/arch-orion5x/orion5x.h + * + * Generic definitions of Orion SoC flavors: + * Orion-1, Orion-NAS, Orion-VoIP, and Orion-2. + * + * Maintainer: Tzachi Perelstein <tzachi@marvell.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_ORION5X_H +#define __ASM_ARCH_ORION5X_H + +/***************************************************************************** + * Orion Address Maps + * + * phys + * e0000000 PCIe MEM space + * e8000000 PCI MEM space + * f0000000 PCIe WA space (Orion-1/Orion-NAS only) + * f1000000 on-chip peripheral registers + * f2000000 PCIe I/O space + * f2100000 PCI I/O space + * f4000000 device bus mappings (boot) + * fa000000 device bus mappings (cs0) + * fa800000 device bus mappings (cs2) + * fc000000 device bus mappings (cs0/cs1) + * + * virt phys size + * fdd00000 f1000000 1M on-chip peripheral registers + * fde00000 f2000000 1M PCIe I/O space + * fdf00000 f2100000 1M PCI I/O space + * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) + ****************************************************************************/ +#define ORION5X_REGS_PHYS_BASE 0xf1000000 +#define ORION5X_REGS_VIRT_BASE 0xfdd00000 +#define ORION5X_REGS_SIZE SZ_1M + +#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 +#define ORION5X_PCIE_IO_VIRT_BASE 0xfde00000 +#define ORION5X_PCIE_IO_BUS_BASE 0x00000000 +#define ORION5X_PCIE_IO_SIZE SZ_1M + +#define ORION5X_PCI_IO_PHYS_BASE 0xf2100000 +#define ORION5X_PCI_IO_VIRT_BASE 0xfdf00000 +#define ORION5X_PCI_IO_BUS_BASE 0x00100000 +#define ORION5X_PCI_IO_SIZE SZ_1M + +/* Relevant only for Orion-1/Orion-NAS */ +#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 +#define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000 +#define ORION5X_PCIE_WA_SIZE SZ_16M + +#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000 +#define ORION5X_PCIE_MEM_SIZE SZ_128M + +#define ORION5X_PCI_MEM_PHYS_BASE 0xe8000000 +#define ORION5X_PCI_MEM_SIZE SZ_128M + +/******************************************************************************* + * Supported Devices & Revisions + ******************************************************************************/ +/* Orion-1 (88F5181) */ +#define MV88F5181_DEV_ID 0x5181 +#define MV88F5181_REV_B1 3 +/* Orion-NAS (88F5182) */ +#define MV88F5182_DEV_ID 0x5182 +#define MV88F5182_REV_A2 2 +/* Orion-2 (88F5281) */ +#define MV88F5281_DEV_ID 0x5281 +#define MV88F5281_REV_D1 5 +#define MV88F5281_REV_D2 6 + +/******************************************************************************* + * Orion Registers Map + ******************************************************************************/ +#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000) +#define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x)) + +#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) +#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) +#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x)) +#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000) +#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000) +#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2000) +#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2100) +#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100) + +#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000) +#define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x)) +#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300) + +#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000) +#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x)) + +#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000) +#define ORION5X_PCIE_REG(x) (ORION5X_PCIE_VIRT_BASE | (x)) + +#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000) +#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000) +#define ORION5X_USB0_REG(x) (ORION5X_USB0_VIRT_BASE | (x)) + +#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000) +#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000) +#define ORION5X_ETH_REG(x) (ORION5X_ETH_VIRT_BASE | (x)) + +#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000) +#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000) +#define ORION5X_SATA_REG(x) (ORION5X_SATA_VIRT_BASE | (x)) + +#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000) +#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000) +#define ORION5X_USB1_REG(x) (ORION5X_USB1_VIRT_BASE | (x)) + +/******************************************************************************* + * Device Bus Registers + ******************************************************************************/ +#define MPP_0_7_CTRL ORION5X_DEV_BUS_REG(0x000) +#define MPP_8_15_CTRL ORION5X_DEV_BUS_REG(0x004) +#define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050) +#define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008) +#define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010) +#define GPIO_OUT ORION5X_DEV_BUS_REG(0x100) +#define GPIO_IO_CONF ORION5X_DEV_BUS_REG(0x104) +#define GPIO_BLINK_EN ORION5X_DEV_BUS_REG(0x108) +#define GPIO_IN_POL ORION5X_DEV_BUS_REG(0x10c) +#define GPIO_DATA_IN ORION5X_DEV_BUS_REG(0x110) +#define GPIO_EDGE_CAUSE ORION5X_DEV_BUS_REG(0x114) +#define GPIO_EDGE_MASK ORION5X_DEV_BUS_REG(0x118) +#define GPIO_LEVEL_MASK ORION5X_DEV_BUS_REG(0x11c) +#define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c) +#define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460) +#define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464) +#define DEV_BANK_BOOT_PARAM ORION5X_DEV_BUS_REG(0x46c) +#define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0) +#define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0) +#define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4) +#define GPIO_MAX 32 + +/*************************************************************************** + * Orion CPU Bridge Registers + **************************************************************************/ +#define CPU_CONF ORION5X_BRIDGE_REG(0x100) +#define CPU_CTRL ORION5X_BRIDGE_REG(0x104) +#define CPU_RESET_MASK ORION5X_BRIDGE_REG(0x108) +#define CPU_SOFT_RESET ORION5X_BRIDGE_REG(0x10c) +#define POWER_MNG_CTRL_REG ORION5X_BRIDGE_REG(0x11C) +#define BRIDGE_CAUSE ORION5X_BRIDGE_REG(0x110) +#define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114) +#define BRIDGE_INT_TIMER0 0x0002 +#define BRIDGE_INT_TIMER1 0x0004 +#define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200) +#define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204) + + +#endif diff --git a/include/asm-arm/arch-orion/system.h b/include/asm-arm/arch-orion5x/system.h index 653f992bbe6..3f1d1e2d38f 100644 --- a/include/asm-arm/arch-orion/system.h +++ b/include/asm-arm/arch-orion5x/system.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/system.h + * include/asm-arm/arch-orion5x/system.h * * Tzachi Perelstein <tzachi@marvell.com> * @@ -12,7 +12,7 @@ #define __ASM_ARCH_SYSTEM_H #include <asm/arch/hardware.h> -#include <asm/arch/orion.h> +#include <asm/arch/orion5x.h> static inline void arch_idle(void) { @@ -24,8 +24,8 @@ static inline void arch_reset(char mode) /* * Enable and issue soft reset */ - orion_setbits(CPU_RESET_MASK, (1 << 2)); - orion_setbits(CPU_SOFT_RESET, 1); + orion5x_setbits(CPU_RESET_MASK, (1 << 2)); + orion5x_setbits(CPU_SOFT_RESET, 1); } diff --git a/include/asm-arm/arch-orion/timex.h b/include/asm-arm/arch-orion5x/timex.h index 85588d9c22e..31c568e28cc 100644 --- a/include/asm-arm/arch-orion/timex.h +++ b/include/asm-arm/arch-orion5x/timex.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/timex.h + * include/asm-arm/arch-orion5x/timex.h * * Tzachi Perelstein <tzachi@marvell.com> * @@ -10,4 +10,4 @@ #define CLOCK_TICK_RATE (100 * HZ) -#define ORION_TCLK 166666667 +#define ORION5X_TCLK 166666667 diff --git a/include/asm-arm/arch-orion/uncompress.h b/include/asm-arm/arch-orion5x/uncompress.h index 03306cdd51b..5c13d4fafb4 100644 --- a/include/asm-arm/arch-orion/uncompress.h +++ b/include/asm-arm/arch-orion5x/uncompress.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/uncompress.h + * include/asm-arm/arch-orion5x/uncompress.h * * Tzachi Perelstein <tzachi@marvell.com> * @@ -8,7 +8,7 @@ * warranty of any kind, whether express or implied. */ -#include <asm/arch/orion.h> +#include <asm/arch/orion5x.h> #define MV_UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0)) #define MV_UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14)) diff --git a/include/asm-arm/arch-orion/vmalloc.h b/include/asm-arm/arch-orion5x/vmalloc.h index 9d580278d2b..2b3061e90dc 100644 --- a/include/asm-arm/arch-orion/vmalloc.h +++ b/include/asm-arm/arch-orion5x/vmalloc.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion/vmalloc.h + * include/asm-arm/arch-orion5x/vmalloc.h */ #define VMALLOC_END 0xfd800000 |