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path: root/arch/arm/mach-omap2/clock24xx.h
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2008-08-19ARM: OMAP2: Clockdomain: Associate clocks with clockdomainsPaul Walmsley
Associate each OMAP24xx clock in arch/arm/mach-omap2/clock24xx.h with a clockdomain. Also move the L4 clock up higher in the file in preparation to define the SSI L4 iclk. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithmPaul Walmsley
This patch adds a new rate rounding algorithm for DPLL clocks on the OMAP2/3 architecture. For a desired DPLL target rate, there may be several multiplier/divider (M, N) values which will generate a sufficiently close rate. Lower N values result in greater power economy. However, lower N values can cause the difference between the rounded rate and the target rate ("rate error") to be larger than it would be with a higher N. This can cause downstream devices to run more slowly than they otherwise would. This DPLL rate rounding algorithm: - attempts to find the lowest possible N (DPLL divider) to reach the target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>, lower N values save more power than higher N values). - allows developers to set an upper bound on the error between the rounded rate and the desired target rate ("rate tolerance"), so an appropriate balance between rate fidelity and power savings can be set. This maximum rate error tolerance is set via omap2_set_dpll_rate_tolerance(). - never returns a rounded rate higher than the target rate. The rate rounding algorithm caches the last rounded M, N, and rate computation to avoid rounding the rate twice for each clk_set_rate() call. (This patch does not yet implement set_rate for DPLLs; that follows in a future patch.) The algorithm trades execution speed for rate accuracy. It will find the (M, N) set that results in the least rate error, within a specified rate tolerance. It does this by evaluating each divider setting - on OMAP3, this involves 128 steps. Another approach to DPLL rate rounding would be to bail out as soon as a valid rate is found within the rate tolerance, which would trade rate accuracy for execution speed. Alternate implementations welcome. This code is not yet used by the OMAP24XX DPLL clock, since it is currently defined as a composite clock, fusing the DPLL M,N and the M2 output divider. This patch also renames the existing OMAP24xx DPLL programming functions to highlight that they program both the DPLL and the DPLL's output multiplier. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03ARM: OMAP: McBSP: Add support for mcbsp on mach-omap1Eduardo Valentin
This patch adds support for mach-omap1 based on current mcbsp platform driver. Signed-off-by: Eduardo Valentin <eduardo.valentin@indt.org.br> Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-04-14ARM: OMAP2: Clean up 24xx clock codeTony Lindgren
Clean up 24xx clock code to sync it with linux-omap tree. Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-04-14ARM: OMAP: Add rest of 24xx clocksPaul Walmsley
This patch adds the rest of clocks for 24xx. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-04-14ARM: OMAP2: Change 24xx to use shared clock code and new reg accessPaul Walmsley
This patch changes 24xx to use shared clock code and new register access. Note that patch adds some temporary OLD_CK defines to keep patch more readable. These temporary defines will be removed in the next patch. Also not all clocks are changed in this patch to limit the size. Also, the patch fixes few incorrect clock defines in clock24xx.h. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-04-14ARM: OMAP2: Move clock.h to clock24xx.hPaul Walmsley
This patch moves clock.h to clock24xx.h to make room for adding common clock code for 24xx and 34xx. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>