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From: Bruce Ashfield <bruce.ashfield@windriver.com>
To fully support the armv7-a instruction set/optimizations, support
for the R_ARM_MOVW_ABS_NC and R_ARM_MOVT_ABS relocation types is
required.
The MOVW and MOVT are both load-immediate instructions, MOVW loads 16
bits into the bottom half of a register, and MOVT loads 16 bits into the
top half of a register.
The relocation information for these instructions has a full 32 bit
value, plus an addend which is stored in the 16 immediate bits in the
instruction itself. The immediate bits in the instruction are not
contiguous (the register # splits it into a 4 bit and 12 bit value),
so the addend has to be extracted accordingly and added to the value.
The value is then split and put into the instruction; a MOVW uses the
bottom 16 bits of the value, and a MOVT uses the top 16 bits.
Signed-off-by: David Borman <david.borman@windriver.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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As per commit 284901a90a9e0b812ca3f5f852cbbfb60d10249d, use
DMA_BIT_MASK(n)
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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The i.MX31 ARM11 core is not a v6K core. Disable this option as it
is incompatible with non v6K cores.
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Before this patch I got the following line in my dmesg:
[ 0.000000] BUG: mapping for 0xd4000000 at 0xeb000000 overlaps vmalloc space
VMALLOC_END is 0xf4000000 and there are the following other mappings
defined for mx27ads:
(0xa0500000,+0x00001000) maps to 0xffff0000
(0x10000000,+0x00100000) maps to 0xf4000000
(0x80000000,+0x00100000) maps to 0xf4100000
(0xd8000000,+0x00100000) maps to 0xf4200000
So map PBC to 0xf4300000.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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On i.MX31 I sometimes get spurious interrupts. There is no need
to crash the whole system when this happens. Instead, silently
ignore it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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We want to have a mx31_defconfig file that builds a kernel that is able
to boot on all support mx31 systems and thus also can be better tested
by automatic build scripts. For these reasons, this config file is not
needed anymore.
Signed-off-by: Valentin Longchamp <valentin.longchamp@epfl.ch>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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All i.MX platforms support <linux/clk.h> calls and should select HAVE_CLK.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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On MX2 platforms imx_dma_request() calls request_irq() which may sleep
with interrupts disabled.
Signed-off-by: Martin Fuzzey <mfuzzey@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The sequence
imx_dma_request()
imx_dma_enable()
imx_dma_free()
left the dma channel in_use mode and did not release the timer.
Signed-off-by: Martin Fuzzey <mfuzzey@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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* master.kernel.org:/home/rmk/linux-2.6-arm: (45 commits)
[ARM] 5489/1: ARM errata: Data written to the L2 cache can be overwritten with stale data
[ARM] 5490/1: ARM errata: Processor deadlock when a false hazard is created
[ARM] 5487/1: ARM errata: Stale prediction on replaced interworking branch
[ARM] 5488/1: ARM errata: Invalidation of the Instruction Cache operation can fail
davinci: DM644x: NAND: update partitioning
davinci: update DM644x support in preparation for more SoCs
davinci: DM644x: rename board file
davinci: update pin-multiplexing support
davinci: serial: generalize for more SoCs
davinci: DM355 IRQ Definitions
davinci: DM646x: add interrupt number and priorities
davinci: PSC: Clear bits in MDCTL reg before setting new bits
davinci: gpio bugfixes
davinci: add EDMA driver
davinci: timers: use clk_get_rate()
[ARM] pxa/littleton: add missing da9034 touchscreen support
[ARM] pxa/zylonite: configure GPIO18/19 correctly, used by 2 GPIO expanders
[ARM] pxa/zylonite: fix the issue of unused SDATA_IN_1 pin get AC97 not working
[ARM] pxa: make ads7846 on corgi and spitz to sync on HSYNC
[ARM] pxa: remove unused CPU_FREQ_PXA Kconfig symbol
...
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The alterations to the suspend code missed adding a
call to the cache flushing routines during the suspend
path of the S3C2412.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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Add the physical address of the two I2S channel register blocks.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
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with stale data
This patch is a workaround for the 460075 Cortex-A8 (r2p0) erratum. It
configures the L2 cache auxiliary control register so that the Write
Allocate mode for the L2 cache is disabled.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This patch adds a workaround for the 458693 Cortex-A8 (r2p0)
erratum. It sets the corresponding bits in the auxiliary control
register so that the PLD instruction becomes a NOP.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This patch adds the workaround for the 430973 Cortex-A8 (r1p0..r1p2)
erratum. The BTAC/BTB is now flushed at every context switch.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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can fail
This patch implements the recommended workaround for erratum 411920
(ARM1136, ARM1156, ARM1176).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6
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arm is placing some code in the .text.init section, but it does not
reference that section in its linker scripts.
This change moves this code from the .text.init section to the
.init.text section, which is presumably where it belongs.
Signed-off-by: Tim Abbott <tabbott@mit.edu>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci
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Update NAND partitioning for the dm6446 evm, unmasking the hidden
data at the beginning and letting the kernel be updated from Linux.
- This is boot-compatible with TI's software (U-Boot 1.20 and both
the 2.6.10 and 2.6.18 kernels), in terms of startup and loading
kernels from flash.
- In the same way, it's also boot-compatible with mainline U-Boot,
which stores U-Boot params in block 0 not block 16.
- It's not quite compatible with systems that previously used NAND
partitions to hold (filesystem) data. The compatibilities are a
bit different based on which kernel was used previously
+ Users of TI/MV kernels no longer see mtd2 "params"
(mainline u-boot env is in a different place)
* Filesystem is now mtd2 ... vs mtd3
+ Users of GIT kernels now see mtd0 and mtd1 partitions
* Filesystem partition starts 640 KBytes earlier
* Filesystem is now mtd2 ... vs mtd0
* Linux now *uses* the flash-resident BBT
* Removes annoying slowdown/hiccup during boot
* Potentially ~64KB less space available with TI/MV kernels
If you *used* NAND partitions from Linux, there is no solution that's
fully compatible with all previous kernels in those respects ... ergo
this "best compromise". It'd be good to back back up the filesystem
data; or, carry your own backwards-compatibility patch for awhile.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Rework DM644x code into SoC specific and board specific parts.
This is also to generalize the structure a bit so it's easier to add
support for new SoCs in the DaVinci family.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Rename DM6446 EVM board file, no functional changes. Code is updated
and reworked in following patch.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Update MUX support to be more general and useful across multiple
SoCs in the DaVinci family.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Adding IRQ defintions for DaVinci DM355 and default interrupt
priorities for DM355
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Clear any set bits in the 'NEXT' field of the MDCTL register in the
Power and Sleep Controller (PSC) before setting any new bits.
This also allows some minor cleanup by removing some no longer
needed lines of code.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Update the DaVinci GPIO code to work better on non-dm6446 parts,
notably the dm355:
- Only handle the number of GPIOs the chip actually has. So
for example on dm6467, GPIO-42 is the last GPIO, and trying
to use GPIO-43 now fails cleanly; or GPIO-72 on dm6446.
- Enable GPIO interrupts on each 16-bit GPIO-irq bank ...
previously, only the first five were enabled, so GPIO-80
and above (on dm355) wouldn't trigger IRQs.
- Use the right IRQ for each GPIO bank. The wrong values were
used for dm355 chips, so GPIO IRQs got routed incorrectly.
- Handle up to four pairs of 16-bit GPIO banks ... previously
only three were handled, so accessing GPIO-96 and up (e.g. on
dm355) would oops.
- Update several comments that were dm6446-specific.
Verified by receiving GPIO-1 (dm9000) and GPIO-5 (msp430) IRQs
on the DM355 EVM.
One thing this doesn't do is handle the way some of the GPIO
numbers on dm6467 are reserved but aren't valid as GPIOs. Some
bitmap logic could fix that if needed.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Original code for 2.6.10 and 2.6.28 series done by Texas Instruments
and MontaVista, but major updates and rework done by Troy Kisky and
David Brownell.
Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Use clock framework instead of hard-coded CLOCK_TICK_RATE for
determining timer tick frequencies.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Signed-off-by: Eric Miao <eric.miao@marvell.com>
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Signed-off-by: Eric Miao <eric.miao@marvell.com>
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GPIO17_SDATA_IN_1 and GPIO36_SDATA_IN_1 are originally designed for the 2nd
codec but unused on the board, yet they are initialized incorrectly by the
bootloader as the SDATA_IN_1 alternate function, thus causing AC97 fail to
work. Fix this issue by configuring these pins as normal GPIO to avoid the
noise from these pins being treated as signals from the 2nd codec.
Signed-off-by: Eric Miao <eric.miao@marvell.com>
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Signed-off-by: Eric Miao <eric.miao@marvell.com>
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cpufreq drivers for pxa2xx/3xx are now built-in automatically as soon as
CPU_FREQ is enabled.
Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: Eric Miao <eric.miao@marvell.com>
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ARCH_PXA selects HAVE_CLK and COMMON_CLKDEV twice in arch/arm/Kconfig.
Remove the second entry.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Eric Miao <eric.miao@marvell.com>
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pxa_gpio_irq_type() and pxa_unmask_muxed_gpio() will touch non-muxed GPIOs
(0 and 1 on PXA2xx/PXA3xx) bits in GRERx and GFERx, which is incorrect.
Actually, only those bits should get updated if the corresponding bits are
set in c->irq_mask as well. Fix this by updating only those relevant bits.
Reported-and-tested-by: Daniel Ribeiro <drwyrm@gmail.com>
Signed-off-by: Eric Miao <eric.miao@marvell.com>
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arch/arm/mach-sa1100/lart.c:36: error: 'PAGE_SHIFT' undeclared here (not in a function)
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6
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* master.kernel.org:/home/rmk/linux-2.6-arm:
[ARM] 5460/1: Orion: reduce namespace pollution
[ARM] 5458/1: pcmcia: pxa2xx-sharpsl: check if we do have Scoop config
[ARM] 5457/1: mach-imx gpio buildfix
[ARM] 5456/1: add sys_preadv and sys_pwritev
[ARM] pxa/pcm990: start external GPIOs immediately after built-in ones
[ARM] pxa/palm27x: General fix for Palm27x aSoC driver
[ARM] pxa/mioa701: use GPIO95 as AC97 reset line
[ARM] pxa: merge AC97 platform data structures
[ARM] pxa/magician: remove un-necessary #include of pxa-regs.h and hardware.h
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Add a function omap2_gp_clockevent_set_gptimer() for board-*.c files
to use in .init_irq functions to configure the system tick GPTIMER.
Practical choices at this point are GPTIMER1 or GPTIMER12. Both of
these timers are in the WKUP powerdomain, and so are unaffected by
chip power management. GPTIMER1 can use sys_clk as a source, for
applications where a high-resolution timer is more important than
power management. GPTIMER12 has the special property that it has the
secure 32kHz oscillator as its source clock, which may be less prone
to glitches than the off-chip 32kHz oscillator. But on HS devices, it
may not be available for Linux use.
It appears that most boards are fine with GPTIMER1, but BeagleBoard
should use GPTIMER12 when using a 32KiHz timer source, due to hardware bugs
in revisions B4 and below. Modify board-omap3beagle.c to use GPTIMER12.
This patch originally used a Kbuild config option to select the GPTIMER,
but was changed to allow this to be specified in board-*.c files, per
Tony's request.
Kalle Vallo <kalle.valo@nokia.com> found a bug in an earlier version of
this patch - thanks Kalle.
Tested on Beagle rev B4 ES2.1, with and without CONFIG_OMAP_32K_TIMER, and
3430SDP.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Cc: Kalle Valo <kalle.valo@nokia.com>
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All GP timers on OMAP2/3 can generate wakeup events. The wakeup status is
cleared in the PRCM interrupt handler.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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