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2009-01-16avr32: Fix out-of-range rcalls in large kernelsBen Nizette
Replace handcoded rcall instructions with the call pseudo-instruction. For kernels too far over 1MB the rcall instruction can't reach and linking will fail. We already call the final linker with --relax which converts call pseudo-instructions to the right things anyway. This fixes arch/avr32/kernel/built-in.o: In function `syscall_exit_work': (.ex.text+0x198): relocation truncated to fit: R_AVR32_22H_PCREL against symbol `schedule' defined in .sched.text section in kernel/built-in.o arch/avr32/kernel/built-in.o: In function `fault_exit_work': (.ex.text+0x3b6): relocation truncated to fit: R_AVR32_22H_PCREL against symbol `schedule' defined in .sched.text section in kernel/built-in.o But I'm still left with arch/avr32/kernel/built-in.o:(.fixup+0x2): relocation truncated to fit: R_AVR32_22H_PCREL against `.text'+45a arch/avr32/kernel/built-in.o:(.fixup+0x8): relocation truncated to fit: R_AVR32_22H_PCREL against `.text'+8ea arch/avr32/kernel/built-in.o:(.fixup+0xe): relocation truncated to fit: R_AVR32_22H_PCREL against `.text'+abe arch/avr32/kernel/built-in.o:(.fixup+0x14): relocation truncated to fit: R_AVR32_22H_PCREL against `.text'+ac8 arch/avr32/kernel/built-in.o:(.fixup+0x1a): relocation truncated to fit: R_AVR32_22H_PCREL against `.text'+ad2 arch/avr32/kernel/built-in.o:(.fixup+0x20): relocation truncated to fit: R_AVR32_22H_PCREL against `.text'+adc arch/avr32/kernel/built-in.o:(.fixup+0x26): relocation truncated to fit: R_AVR32_22H_PCREL against `.text'+ae6 arch/avr32/kernel/built-in.o:(.fixup+0x2c): relocation truncated to fit: R_AVR32_22H_PCREL against `.text'+af0 arch/avr32/kernel/built-in.o:(.fixup+0x32): additional relocation overflows omitted from the output These are caused by a similar problem with 'rjmp' instructions. Unfortunately, there's no easy fix for these at the moment since we don't have a arbitrary-range 'jmp' instruction similar to 'call'. Signed-off-by: Ben Nizette <bn@niasdigital.com> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-01avr32: Fix lockup after Java stack underflow in user modeHaavard Skinnemoen
When using the Java Extension Module hardware, a Java stack underflow or overflow trap may cause the system to enter an infinite exception loop. Although there's no kernel support for the Java hardware yet, we need to be able to recover from this situation and keep the system running. This patch adds code to detect and fixup this situation in the critical exception handler and terminate the faulting process. We may have to rethink how to handle this more gracefully when the necessary kernel support for hardware-accelerated Java is added. Reported-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-07-02avr32: Cover the kernel page tables in the user PGDsHaavard Skinnemoen
Expand the per-process PGDs so that they cover the kernel virtual memory area as well. This simplifies the TLB miss handler fastpath since it doesn't have to check for kernel addresses anymore. If a TLB miss happens on a kernel address and a second-level page table can't be found, we check swapper_pg_dir and copy the PGD entry into the user PGD if it can be found there. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-07-02avr32: Store virtual addresses in the PGDHaavard Skinnemoen
Instead of storing physical addresses along with page flags in the PGD, store virtual addresses and use NULL to indicate a not present second-level page table. A non-page-aligned page table indicates a bad PMD. This simplifies the TLB miss handler since it no longer has to check the Present bit and no longer has to convert the PGD entry from physical to virtual address. Instead, it has to check for a NULL entry, which is slightly cheaper than either. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-06-27avr32: Kill special exception handler sectionsHaavard Skinnemoen
Kill the special exception handler sections .tlbx.ex.text, .tlbr.ex.text, tlbw.ex.text and .scall.text. Use .org instead to place the handlers at the required offsets from EVBA. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-04-19avr32: Move sleep code into mach-at32apHaavard Skinnemoen
Create a new file, pm-at32ap700x.S, in mach-at32ap and move the CPU idle sleep code there. Make it possible to disable the sleep code. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
2007-12-07[AVR32] Fix wrong pt_regs in critical exception handlerHaavard Skinnemoen
It's not like it really matters at this point since the system is dying anyway, but handle_critical pushes too few registers on the stack so the register dump, which makes the register dump look a bit strange. This patch fixes it. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
2007-12-07[AVR32] Follow the rules when dealing with the OCD systemHaavard Skinnemoen
The current debug trap handling code does a number of things that are illegal according to the AVR32 Architecture manual. Most importantly, it may try to schedule from Debug Mode, thus clearing the D bit, which can lead to "undefined behaviour". It seems like this works in most cases, but several people have observed somewhat unstable behaviour when debugging programs, including soft lockups. So there's definitely something which is not right with the existing code. The new code will never schedule from Debug mode, it will always exit Debug mode with a "retd" instruction, and if something not running in Debug mode needs to do something debug-related (like doing a single step), it will enter debug mode through a "breakpoint" instruction. The monitor code will then return directly to user space, bypassing its own saved registers if necessary (since we don't actually care about the trapped context, only the one that came before.) This adds three instructions to the common exception handling code, including one branch. It does not touch super-hot paths like the TLB miss handler. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
2007-12-07[AVR32] Clean up OCD register usageHaavard Skinnemoen
Generate a new set of OCD register definitions in asm/ocd.h and rename __mfdr() and __mtdr() to ocd_read() and ocd_write() respectively. The bitfield definitions are a lot more complete now, and they are entirely based on bit numbers, not masks. This is because OCD registers are frequently accessed from assembly code, where bit numbers are a lot more useful (can be fed directly to sbr, bfins, etc.) Bitfields that consist of more than one bit have two definitions: _START, which indicates the number of the first bit, and _SIZE, which indicates the number of bits. These directly correspond to the parameters taken by the bfextu, bfexts and bfins instructions. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
2007-12-07[AVR32] Implement irqflags trace and lockdep supportHaavard Skinnemoen
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
2007-10-11[AVR32] Fix random segfault with preemptionPhilippe Rétornaz
As explained on: http://www.avrfreaks.net/index.php?nameÿphpBB2&fileÿewtopic&tS307 If the current process is preempted before it can copy RAR_SUP and RSR_SUP both register are lost and the process will segfault as soon as it return from the syscall since the return adress will be corrupted. This patch disable IRQ as soon as we enter the syscall path and reenable them when the copy is done. In the interrupt handlers, check if we are interrupting the srrf instruction, if so disable interrupts and return. The interrupt handler will be re-called immediatly when the interrupts are reenabled. After some stressing workload: - find / > /dev/null in loop - top (in ssh) - ping -f avr32 The segfaults are not seen anymore. Signed-off-by: Philippe Rétornaz <philippe.retornaz@epfl.ch> Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
2007-04-27[AVR32] Optimize the TLB miss handlerHaavard Skinnemoen
Reorder some instructions and change the register usage to reduce the number of pipeline stalls. Also use the bfextu and bfins instructions for bitfield manipulations instead of shifting and masking. This makes gzipping a 80MB file approximately 2% faster. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
2007-04-27[AVR32] Fix NMI handlerHaavard Skinnemoen
Fix a problem with the NMI handler entry code related to the NMI handler sharing some code with the exception handlers. This is not a good idea because the RSR and RAR registers are not the same, and the NMI handler runs with interrupts masked the whole time so there's no need to check for pending work. Open-code the low-level NMI handling logic instead so that the pt_regs layout is actually correct when the higher-level handler is called. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
2007-04-27[AVR32] Put cpu in sleep 0 when idle.Hans-Christian Egtvedt
This patch puts the CPU in sleep 0 when doing nothing, idle. This will turn of the CPU clock and thus save power. The CPU is waken again when an interrupt occurs. Signed-off-by: Hans-Christian Egtvedt <hcegtvedt@atmel.com> Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
2006-09-26[PATCH] avr32 architectureHaavard Skinnemoen
This adds support for the Atmel AVR32 architecture as well as the AT32AP7000 CPU and the AT32STK1000 development board. AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption and high code density. The AVR32 architecture is not binary compatible with earlier 8-bit AVR architectures. The AVR32 architecture, including the instruction set, is described by the AVR32 Architecture Manual, available from http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf The Atmel AT32AP7000 is the first CPU implementing the AVR32 architecture. It features a 7-stage pipeline, 16KB instruction and data caches and a full Memory Management Unit. It also comes with a large set of integrated peripherals, many of which are shared with the AT91 ARM-based controllers from Atmel. Full data sheet is available from http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf while the CPU core implementation including caches and MMU is documented by the AVR32 AP Technical Reference, available from http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf Information about the AT32STK1000 development board can be found at http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3918 including a BSP CD image with an earlier version of this patch, development tools (binaries and source/patches) and a root filesystem image suitable for booting from SD card. Alternatively, there's a preliminary "getting started" guide available at http://avr32linux.org/twiki/bin/view/Main/GettingStarted which provides links to the sources and patches you will need in order to set up a cross-compiling environment for avr32-linux. This patch, as well as the other patches included with the BSP and the toolchain patches, is actively supported by Atmel Corporation. [dmccr@us.ibm.com: Fix more pxx_page macro locations] [bunk@stusta.de: fix `make defconfig'] Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Dave McCracken <dmccr@us.ibm.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>