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2007-12-06Fix oprofile configuration breakageRalf Baechle
The cleanup 09cadedbdc01f1a4bea1f427d4fb4642eaa19da9 broke the oprofile configuration for MIPS by allowing oprofile support to be built for kernel models where oprofile doesn't have a chance in hell to work. Just a dependecy list on a number of architectures is - surprise - broken and should as per past discussions probably in most considered to be broken in most cases. So I introduce a dependency for the oprofile configuration on ARCH_SUPPORTS_OPROFILE. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-11-26[MIPS] IP22: Fix broken EISA interrupt setup by switching to generic i8259Thomas Bogendoerfer
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-26[MIPS] 64-bit Sibyte kernels need DMA32.Ralf Baechle
Sibyte SOCs only have 32-bit PCI. Due to the sparse use of the address space only the first 1GB of memory is mapped at physical addresses below 1GB. If a system has more than 1GB of memory 32-bit DMA will not be able to reach all of it. For now this patch is good enough to keep Sibyte users happy but it seems eventually something like swiotlb will be needed for Sibyte. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-26[MIPS] Only build r4k clocksource for systems that work ok with it.Ralf Baechle
In particular as-is it's not suited for multicore and mutiprocessors systems where there is on guarantee that the counter are synchronized or running from the same clock at all. This broke Sibyte and probably others since the "[MIPS] Handle R4000/R4400 mfc0 from count register." commit. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15[MIPS] Fix shadow register support.Ralf Baechle
Shadow register support would not possibly have worked on multicore systems. The support code for it was also depending not on MIPS R2 but VSMP or SMTC kernels even though it makes perfect sense with UP kernels. SR sets are a scarce resource and the expected usage pattern is that users actually hardcode the register set numbers in their code. So fix the allocator by ditching it. Move the remaining CPU probe bits into the generic CPU probe. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15[MIPS] Qemu: Add early printk, your friend in a cold night.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02[MIPS] Bigsur supports highmem.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02[MIPS] Sibyte: Split and move clock code.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29[MIPS] txx9tmr clockevent/clocksource driverAtsushi Nemoto
Convert jmr3927_clock_event_device to more generic txx9tmr_clock_event_device which supports one-shot mode. The txx9tmr_clock_event_device can be used for TX49 too if the cp0 timer interrupt was not available. Convert jmr3927_hpt_read to txx9_clocksource driver which does not depends jiffies anymore. The txx9_clocksource itself can be used for TX49, but normally TX49 uses higher precision clocksource_mips. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-22[MIPS] time: Add GT641xx timer0 clockevent driverYoichi Yuasa
And make use of it for Cobalt. A few others such as the Malta could make use of it as well. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-20typo fixesMatt LaPlante
Most of these fixes were already submitted for old kernel versions, and were approved, but for some reason they never made it into the releases. Because this is a consolidation of a couple old missed patches, it touches both Kconfigs and documentation texts. Signed-off-by: Matt LaPlante <kernel1@cyberdogtech.com> Acked-by: Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by: Adrian Bunk <bunk@kernel.org>
2007-10-19Combine instrumentation menus in kernel/Kconfig.instrumentationMathieu Desnoyers
Quoting Randy: "It seems sad that this patch sources Kconfig.marker, a 7-line file, 20-something times. Yes, you (we) don't want to put those 7 lines into 20-something different files, so sourcing is the right thing. However, what you did for avr32 seems more on the right track to me: make _one_ Instrumentation support menu that includes PROFILING, OPROFILE, KPROBES, and MARKERS and then use (source) that in all of the arches." Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca> Acked-by: Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-18[MIPS] time: Move R4000 clockevent device code to separate configurable fileRalf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-16[MIPS] Lasat: Fix build by conversion to irq_cpu.c.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-16[MIPS] IP32: Fix build by conversion to irq_cpu.c.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] i8253 PIT clocksource and clockevent driversRalf Baechle
Derived from the i386 variant with a few x86 complexities chopped off. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Dyntick support for SMTC:Ralf Baechle
The kernel currently only supports broadcasting of the timer interrupt from a single timer, not multicasting into two multicast groups of processors. So the implemented mechanism for SMTC works by broadcasting the cp0 compare interrupt on VPE 0 and ignoring it on any additional VPEs. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Implement clockevents for R4000-style cp0 count/compare interruptRalf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Switch from to_tm to rtc_time_to_tmRalf Baechle
This replaces the MIPS-specific to_tm function with the generic rtc_time_to_tm function. The big difference between the two functions is that rtc_time_to_tm uses epoch 70 while to_tm uses 1970, so the result of rtc_time_to_tm needs to be fixed up. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Use generic NTP code for all MIPS platformsRalf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Add CFE support to BCM47XXAurelien Jarno
Add CFE support to the BCM47XX code. That includes querying CFE environment variables as well as using CFE to print messages before the serial port is initialized (early printk). Signed-off-by: Aurelien Jarno <aurel32@farad.aurel32.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Move CFE code into arch/mips/fw/cfeAurelien Jarno
Move the platform independent part of the CFE code to arch/mips/fw/cfe from arch/mips/sibyte/cfe. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Add GT641xx IRQ routines.Yoichi Yuasa
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] PCI: Always enable CONFIG_PCI_DOMAINSRalf Baechle
The cost is just too low. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Add support for BCM47XX CPUs.Aurelien Jarno
Note that the BCM4710 does not support the wait instruction, this is not a mistake in the code. It originally comes from the OpenWrt patches. Cc: Michael Buesch <mb@bu3sch.de> Cc: Felix Fietkau <nbd@openwrt.org> Cc: Florian Schirmer <jolt@tuxbox.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] JAZZ fixesThomas Bogendoerfer
- restructured irq handling - switched vdma to use memory allocated via get_free_pages - setup platform devices for serial, jazz_esp and jazzsonic - fixed cmos rtc access Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Add back support for LASAT platformsBrian Murphy
Signed-off-by: Brian Murphy <brian@murphy.dk> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Automatically set CONFIG_BUILD_ELF64Franck Bui-Huu
We do not rely on user anymore to setup this config correctly. Instead we make our choice depending on the load address. If we want to force Kbuild to use ELF64 format whatever the load address we can still do: $ make BUILD_ELF32=no Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] IRQ Affinity Support for SMTC on Malta PlatformKevin D. Kissell
Signed-off-by: Kevin D. Kissell <kevink@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-09-10[MIPS] Ocelot: remove remaining bitsYoichi Yuasa
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-09-10[MIPS] Kconfig: whitespace cleanup.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-08-27[MIPS] Fulong doesn't need ISA DMA.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-08-27[MIPS] Sort out handling of ISA-less PCI systems.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-08-27[MIPS] Excite: disable 64-bit kernel support.Ralf Baechle
CC arch/mips/basler/excite/excite_prom.o arch/mips/basler/excite/excite_prom.c:136:3: #error 64 bit support not implemented Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-08-27[MIPS] Kconfig: Fix configuration warning by hardwiring HOTPLUG_CPU to n.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-08-27[MIPS] SEAD: Don't mark as experimental.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-08-27[MIPS] Drop unneeded config options for RBTX4938Atsushi Nemoto
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-08-27[MIPS] Cleanup TX39/TX49 irq codeAtsushi Nemoto
Cleanup jmr3927, tx4927 and tx4938 irq codes, using common IRQ_CPU, I8259 and IRQ_TXX9 irq routines. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-08-27[MIPS] The irq_chip for TX39/TX49 SoCsAtsushi Nemoto
Add generic irq_chip for TX39/TX49 SoCs. This can be replace jmr3927_irq_irc, tx4927_irq_pic_type and tx4938_irq_pic_type. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-08-27[MIPS] Remove unused pnx8550 KconfigYoichi Yuasa
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-08-27[MIPS] Kconfig: Enable 64BIT_PHYS_ADDR only through select.Ralf Baechle
The user should not have to have any clue about this setting. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-31[MIPS] DDB5477: Remove supportYoichi Yuasa
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-31[MIPS] Remove Momentum Ocelot support.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-31[MIPS] MT: Enable coexistence of AP/SP with VSMP and SMTC.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-31[MIPS] Sort system types alphabeticallyYoichi Yuasa
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-31[MIPS] Fix RBTX49x7 board nameYoichi Yuasa
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-31[MIPS] Fixup secure computing stuff.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-20[MIPS] Make support for weakly ordered LL/SC a config option.Ralf Baechle
None of weakly ordered processor supported in tree need this but it seems like this could change ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-12[MIPS] Rename PC speaker codeRalf Baechle
While the PC speaker is wired up to the i8254 there is more to the i8254 than just the PC speaker so this code was getting in the way under its current name. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-12[MIPS] SMTC: Interrupt mask backstop hackKevin D. Kissell
To support multiple TC microthreads acting as "CPUs" within a VPE, VPE-wide interrupt mask bits must be specially manipulated during interrupt handling. To support legacy drivers and interrupt controller management code, SMTC has a "backstop" to track and if necessary restore the interrupt mask. This has some performance impact on interrupt service overhead. Disable it only if you know what you are doing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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