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path: root/arch/mips/gt64120/wrppmc/irq.c
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2007-10-11[MIPS] cleanup WRPPMC include filesYoichi Yuasa
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-03-19[MIPS] Misc fixes for plat_irq_dispatch functionsThiemo Seufer
o adds missing ST0_IM masks, which caused the logging of valid interrupts as spurious o stops pnx8550 to log every interrupt as spurious o adds cause register masks for ip22/ip32, which caused handling of masked interrupts o removes some superfluous parentheses in the SNI interrupt code Signed-Off-By: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-02-06[MIPS] Define MIPS_CPU_IRQ_BASE in generic headerAtsushi Nemoto
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all platforms and are same value on most platforms (0 or 16, depends on CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make them customizable. This will save a few cycle on each CPU interrupt. A good side effect is removing some dependencies to MALTA in generic SMTC code. Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing them might cause some header dependency problem and there seems no good reason to customize it. So currently only VR41XX is using custom MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259. Testing this patch on those platforms is greatly appreciated. Thank you. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-10-08[MIPS] Complete fixes after removal of pt_regs argument to int handlers.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-29[MIPS] Remove set_c0_status(ST0_IM) from wrppmc's irq.c.Yoichi Yuasa
mips_cpu_irq_init() does clear_c0_status(ST0_IM) first, so set_c0_status(ST0_IM) isn't necessary. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-29[MIPS] Fix the build error of Wind River PPMC board, rewrite irq code to CMark.Zhan
o Fix the build error Wind River PPMC board caused by the change of plat_setup hook interface. o Rewrite first level interrupt dispatch code to C. Signed-off-by: Rongkai.Zhan <rongkai.zhan@windriver.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-19[MIPS] Wind River 4KC PPMC Eval Board SupportMark.Zhan
Support for the GT-64120-based Wind River 4KC PPMC Evaluation board. Signed-off-by: Rongkai.Zhan <Rongkai.zhan@windriver.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>