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2006-02-07[MIPS] Support /proc/kcore for MIPSDaniel Jacobowitz
I'm pretty sure that the CKSEG0 bits are wrong, but I did need to cover that region - because the SB-1 kernel links at 0xffffffff80100000 or so, disassembly and printing static variables don't work unless the debugger can read that region. Signed-off-by: Daniel Jacobowitz <dan@codesourcery.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-07[MIPS] Remove wrong __user tags.Atsushi Nemoto
This fixes sparse warnings 'dereference of noderef expression'. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-01-10MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-12-12[PATCH] mips: setup_zero_pages count 1Hugh Dickins
Page count should be initialized to 1 on each of the MIPS empty zero pages, to avoid a bad_page warning whenever one of them is freed from all mappings. Signed-off-by: Hugh Dickins <hugh@veritas.com> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-12-01[MIPS] Use reset_page_mapcount to initialize empty_zero_page usage counter.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29[PATCH] mm: init_mm without ptlockHugh Dickins
First step in pushing down the page_table_lock. init_mm.page_table_lock has been used throughout the architectures (usually for ioremap): not to serialize kernel address space allocation (that's usually vmlist_lock), but because pud_alloc,pmd_alloc,pte_alloc_kernel expect caller holds it. Reverse that: don't lock or unlock init_mm.page_table_lock in any of the architectures; instead rely on pud_alloc,pmd_alloc,pte_alloc_kernel to take and drop it when allocating a new one, to check lest a racing task already did. Similarly no page_table_lock in vmalloc's map_vm_area. Some temporary ugliness in __pud_alloc and __pmd_alloc: since they also handle user mms, which are converted only by a later patch, for now they have to lock differently according to whether or not it's init_mm. If sources get muddled, there's a danger that an arch source taking init_mm.page_table_lock will be mixed with common source also taking it (or neither take it). So break the rules and make another change, which should break the build for such a mismatch: remove the redundant mm arg from pte_alloc_kernel (ppc64 scrapped its distinct ioremap_mm in 2.6.13). Exceptions: arm26 used pte_alloc_kernel on user mm, now pte_alloc_map; ia64 used pte_alloc_map on init_mm, now pte_alloc_kernel; parisc had bad args to pmd_alloc and pte_alloc_kernel in unused USE_HPPA_IOREMAP code; ppc64 map_io_page forgot to unlock on failure; ppc mmu_mapin_ram and ppc64 im_free took page_table_lock for no good reason. Signed-off-by: Hugh Dickins <hugh@veritas.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-10-29SB1 cache exception handling.Andrew Isaacson
Expand SB1 cache error handling by adding SB1_CEX_ALWAYS_FATAL and SB1_CEX_STALL, allowing configurable behavior on cache errors. Signed-Off-By: Andy Isaacson <adi@broadcom.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Add support for SB1A CPU.Andrew Isaacson
Signed-Off-By: Andy Isaacson <adi@broadcom.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Fix zero length sys_cacheflushAtsushi Nemoto
Cacheflush(0, 0, 0) was crashing the system. This is because flush_icache_range(start, end) tries to flushing whole address space (0 - ~0UL) if both start and end are zero. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Rename page argument of flush_cache_page to something more descriptive.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Fix wrong comment.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Fixup a few lose ends in explicit support for MIPS R1/R2.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Don't copy SB1 cache error handler to uncached memory.Ralf Baechle
This may have made sense on a paranoid day with pass 1 BCM1250 processors that were throwing cache error exception left and right for no good reason. On modern silicion that hardly makes sense and the code had gotten just an obscurity ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Fix stale comment in c-sb1.c.Andrew Isaacson
Signed-Off-By: Andrew Isaacson <adi@broadcom.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Cleanup the mess in cpu_cache_init.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Use R4000 TLB routines for SB1 also.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Sync c-tx39.c with c-r4k.c.Atsushi Nemoto
tx39_flush_cache_range() does nothing if !cpu_has_dc_aliases. It should flush d-cache and invalidate i-cache since the TX39(H2) has separate I/D cache. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Add/Fix missing bit of R4600 hit cacheop workaround.Thiemo Seufer
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Minor code cleanup.Thiemo Seufer
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29R4600 v2.0 needs a nop before tlbp.Thiemo Seufer
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Don't set up a sg dma address if we have no page address for some reason.Thiemo Seufer
Code cleanup. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29More .set push/pop.Thiemo Seufer
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Let r4600 PRID detection match only legacy CPUs, cleanups.Thiemo Seufer
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Handle mtc0 - tlb write hazard for VR5432.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Avoid SMP cacheflushes. This is a minor optimization of startup butRalf Baechle
will also avoid smp_call_function from doing stupid things when called from a CPU that is not yet marked online. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it.Pete Popov
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29More AP / SP bits for the 34K, the Malta bits and things. Still wantsRalf Baechle
a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Mark a few variables __read_mostly.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29MIPS R2 instruction hazard handling.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Detect the 34K.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Define kmap_atomic_pfn() for MIPS.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Date: Fri Jul 8 20:10:17 2005 +0000Ralf Baechle
Those literals are long. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Rename CONFIG_CPU_MIPS{32,64} to CONFIG_CPU_MIPS{32|64}_R1.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Avoid tlbw* hazards for the R4600/R4700/R5000.Maciej W. Rozycki
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Inline ioremap() calls for constant addresses that map to KSEG1.Maciej W. Rozycki
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Fix the diagnostic dump for the XTLB refill handler.Maciej W. Rozycki
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Fix a diagnostic message.Maciej W. Rozycki
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Use macros for the RM7k cp0.config bits instead of magic numbers.Maciej W. Rozycki
Minor clean-ups. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Optimize R3k TLB Load/Store/Modified handlers, by schedulingMaciej W. Rozycki
delay slots properly and avoiding an unnecessary jump to a jump. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Fill R3k load delay slots properly.Maciej W. Rozycki
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Only dump instructions actually emitted.Maciej W. Rozycki
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Handle _PAGE_DIRTY correctly for CONFIG_64BIT_PHYS_ADDR on 32bit CPUs.Thiemo Seufer
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Better interface to run uncached cache setup code.Thiemo Seufer
Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Arrested for multiple offences of header file inclusion.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Fix race conditions for read_c0_entryhi. Remove broken ASID masks inThiemo Seufer
tlb-sb1.c. Make tlb-r4k.c and tlb-sb1.c more similiar and more efficient. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Remove useless casts. Fix formatting.Maciej W. Rozycki
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Fix 64bit SMP TLB handler and stack frame handling, optimize 32bit SMPThiemo Seufer
TLB handlers a bit, match definitions in pgtable-{32,64}.h better. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29R4300 delay slot.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Reformat; cosmetic cleanups.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29Export shm_align_mask and flush_data_cache_page.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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