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2009-01-27Merge branch 'linus' into core/percpuIngo Molnar
Conflicts: arch/x86/kernel/setup_percpu.c
2009-01-26eeprom: More consistent symbol namesJean Delvare
Now that all EEPROM drivers live in the same place, let's harmonize their symbol names. Also fix eeprom's dependencies, it definitely needs sysfs, and is no longer experimental after many years in the kernel tree. Signed-off-by: Jean Delvare <khali@linux-fr.org> Acked-by: Wolfram Sang <w.sang@pengutronix.de> Cc: David Brownell <dbrownell@users.sourceforge.net>
2009-01-21Merge branch 'x86/mm' into core/percpuIngo Molnar
Conflicts: arch/x86/mm/fault.c
2009-01-15Merge branches 'cpus4096', 'x86/cleanups' and 'x86/urgent' into x86/percpuIngo Molnar
2009-01-15irq: update all arches for new irq_desc, fixMike Travis
Impact: fix build errors Since the SPARSE IRQS changes redefined how the kstat irqs are organized, arch's must use the new accessor function: kstat_incr_irqs_this_cpu(irq, DESC); If CONFIG_SPARSE_IRQS is set, then DESC is a pointer to the irq_desc which has a pointer to the kstat_irqs. If not, then the .irqs field of struct kernel_stat is used instead. Signed-off-by: Mike Travis <travis@sgi.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-01-14Merge branch 'syscalls' of git://git390.osdl.marist.edu/pub/scm/linux-2.6Linus Torvalds
* 'syscalls' of git://git390.osdl.marist.edu/pub/scm/linux-2.6: (44 commits) [CVE-2009-0029] s390 specific system call wrappers [CVE-2009-0029] System call wrappers part 33 [CVE-2009-0029] System call wrappers part 32 [CVE-2009-0029] System call wrappers part 31 [CVE-2009-0029] System call wrappers part 30 [CVE-2009-0029] System call wrappers part 29 [CVE-2009-0029] System call wrappers part 28 [CVE-2009-0029] System call wrappers part 27 [CVE-2009-0029] System call wrappers part 26 [CVE-2009-0029] System call wrappers part 25 [CVE-2009-0029] System call wrappers part 24 [CVE-2009-0029] System call wrappers part 23 [CVE-2009-0029] System call wrappers part 22 [CVE-2009-0029] System call wrappers part 21 [CVE-2009-0029] System call wrappers part 20 [CVE-2009-0029] System call wrappers part 19 [CVE-2009-0029] System call wrappers part 18 [CVE-2009-0029] System call wrappers part 17 [CVE-2009-0029] System call wrappers part 16 [CVE-2009-0029] System call wrappers part 15 ...
2009-01-14byteorder: make swab.h include asm/swab.h like a regular headerHarvey Harrison
Add swab.h to kbuild.asm and remove the individual entries from each arch, mark as unifdef as some arches have some kernel-only bits inside. Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-01-14[CVE-2009-0029] Rename old_readdir to sys_old_readdirHeiko Carstens
This way it matches the generic system call name convention. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
2009-01-12irq: update all arches for new irq_descMike Travis
Impact: cleanup, update to new cpumask API Irq_desc.affinity and irq_desc.pending_mask are now cpumask_var_t's so access to them should be using the new cpumask API. Signed-off-by: Mike Travis <travis@sgi.com>
2009-01-11MIPS: Only write c0_framemask on CPUs which have this register.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Alchemy: new userspace suspend interface for development boards.Manuel Lauss
Replace the current sysctl-based suspend interface with a new sysfs- based one which also uses the Linux-2.6 suspend model. To configure wakeup sources, a subtree for the demoboards is created under /sys/power/db1x: sys/ `-- power `-- db1x |-- gpio0 |-- gpio1 |-- gpio2 |-- gpio3 |-- gpio4 |-- gpio5 |-- gpio6 |-- gpio7 |-- timer |-- timer_timeout |-- wakemsk `-- wakesrc The nodes 'gpio[0-7]' and 'timer' configure the GPIO0..7 and M2 bits of the SYS_WAKEMSK (wakeup source enable) register. Writing '1' enables a wakesource, 0 disables it. The 'timer_timeout' node holds the timeout in seconds after which the TOYMATCH2 event should wake the system. The 'wakesrc' node holds the SYS_WAKESRC register after wakeup (in hex), the 'wakemsk' node can be used to get/set the wakeup mask directly. For example, to have the timer wake the system after 10 seconds of sleep, the following must be done in userspace: echo 10 > /sys/power/db1x/timer_timeout echo 1 > /sys/power/db1x/timer echo mem > /sys/power/sleep This patch also removes the homebrew CPU frequency switching code. I don't understand how it could have ever worked reliably; it does not communicate the clock changes to peripheral devices other than uarts. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 arch/mips/alchemy/devboards/pm.c
2009-01-11MIPS: Alchemy: dbdma suspend/resume support.Manuel Lauss
Implement suspend/resume for DBDMA controller and its channels. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Alchemy: Fix up PM code on Au1550/Au1200Manuel Lauss
Au1550/Au1200 have a different memory controller which requires additi- onal code to properly put memory to sleep (code taken from AMD/RMI's Linux-2.6.11 source package). Also fix up the remaining pm-related paths to compile on Au1200/Au1550 platforms. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Alchemy: move calc_clock function.Manuel Lauss
Now that nothing in time.c depends on calc_clock, it can be moved to clocks.c where it belongs. While at it, give it a better non-generic name and call it as soon as possible in plat_mem_init. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Alchemy: RTC counter clocksource / clockevent support.Manuel Lauss
Add support for the 32 kHz counter1 (RTC) as clocksource / clockevent device. As a nice side effect, this also enables use of the 'wait' instruction for runtime idle power savings. If the counters aren't enabled/working properly, fall back on the cp0 counter clock code. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: make cp0 counter clocksource/event usable as fallback.Manuel Lauss
The current mips clock build infrastructure lets a system only use either the MIPS cp0 counter or a SoC specific timer as a clocksource / clockevent device. This patch renames the core cp0 counter clocksource / clockevent functions from mips_* to r4k_* and updates the wrappers in asm-mips/time.h to call these renamed functions instead. Chips which can detect whether it is safe to use a chip-specific timer can now fall back on the cp0 counter if necessary and possible (e.g. Alchemy with a follow-on patch). Existing behaviour is not changed in any way. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Alchemy: remove cpu_table.Manuel Lauss
Remove the cpu_table: - move detection of whether c0_config[OD] is read-only and should be set to fix various chip errata to au1000 headers. - move detection of write-only sys_cpupll to au1000 headers. - remove the BCLK switching code: Activation of this features should be left to the boards using the chips since it also affects external devices tied to BCLK, and only the board designers know whether it is safe to enable. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> delete mode 100644 arch/mips/alchemy/common/cputable.c
2009-01-11MIPS: Alchemy: remove get/set_au1x00_lcd_clock().Manuel Lauss
There are no in-tree users, so remove them. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Print irq handler descriptionManuel Lauss
Add the name set by set_irq_chip_and_handler_name() to the output of /proc/interrupts, like so: db1200 ~ # cat /proc/interrupts CPU0 8: 52 Alchemy-IC0-hilevel serial 10: 171 Alchemy-IC0-hilevel au1xxx-mmc 11: 47 Alchemy-IC0-hilevel Au1xxx dbdma 18: 1 Alchemy-IC0-hilevel au1550-spi 29: 1250997 Alchemy-IC0-riseedge timer 37: 211 Alchemy-IC0-hilevel ehci_hcd:usb1, ohci_hcd:usb2 38: 0 Alchemy-IC0-hilevel lcd 72: 2623 DB1200 CPLD-level ide0 73: 257 DB1200 CPLD-level eth0 84: 1 DB1200 CPLD-level sd_insert 85: 0 DB1200 CPLD-level sd_eject ERR: 0 Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Alchemy: pb1200: update CPLD cascade irq handler.Manuel Lauss
Tested on Db1200. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Alchemy: update core interrupt code.Manuel Lauss
This patch attempts to modernize core Alchemy interrupt handling code. - add irq_chips for irq controllers instead of irq type, - add a set_type() hook to change irq trigger type during runtime, - add a set_wake() hook to control GPIO0..7 based wakeup, - use linux' IRQF_TRIGGER_ constants instead of homebrew ones, - enable GENERIC_HARDIRQS_NO__DO_IRQ. - simplify plat_irq_dispatch - merge au1xxx_irqmap into irq.c file, the only place where its contents are referenced. - board_init_irq() is now mandatory for every board; use it to register the remaining (gpio-based) interrupt sources; update all boards accordingly. Run-tested on Db1200 and other Au1200 based platforms. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> delete mode 100644 arch/mips/alchemy/common/au1xxx_irqmap.c
2009-01-11MIPS: Alchemy: move commandline mangling out of common codeManuel Lauss
Not every alchemy-based board might want these options forced on it, and most of this stuff seems to be intended for devboard code anyway. Remove commandline mangling code out of common chip code and instead add relevant sections to all in-tree boards to not change existing behaviour. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Alchemy: devboards: consolidate filesManuel Lauss
Share some code and merge small files: - Extract the prom init code from all devboard files (they only differ in memory configuration). - Merge the irq configuration into board setup code. - Merge smaller files into board setup code. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> delete mode 100644 arch/mips/alchemy/devboards/db1x00/init.c delete mode 100644 arch/mips/alchemy/devboards/pb1000/init.c delete mode 100644 arch/mips/alchemy/devboards/pb1000/irqmap.c delete mode 100644 arch/mips/alchemy/devboards/pb1100/init.c delete mode 100644 arch/mips/alchemy/devboards/pb1100/irqmap.c delete mode 100644 arch/mips/alchemy/devboards/pb1200/init.c delete mode 100644 arch/mips/alchemy/devboards/pb1500/init.c delete mode 100644 arch/mips/alchemy/devboards/pb1500/irqmap.c delete mode 100644 arch/mips/alchemy/devboards/pb1550/init.c delete mode 100644 arch/mips/alchemy/devboards/pb1550/irqmap.c create mode 100644 arch/mips/alchemy/devboards/prom.c
2009-01-11MIPS: Alchemy: Move development board code to common subdirectoryManuel Lauss
This should ease sharing of common devboard code. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Add Cavium OCTEON to arch/mips/KconfigDavid Daney
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Add defconfig for Cavium OCTEON.David Daney
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Adjust the dma-common.c platform hooks.David Daney
We add a dev parameter to plat_unmap_dma_mem(), and hooks for plat_dma_supported() and plat_extra_sync_for_device() which should be nop changes for all existing targets. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Add Cavium OCTEON slot into proper tlb category.David Daney
Expand the case statement for build_tlb_write_entry so that it does the right thing on Cavium CPU variants. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Compute branch returns for Cavium OCTEON specific branch instructions.David Daney
For Cavium OCTEON, compute the return epc value for OCTEON specific branch instructions. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Cavium OCTEON multiplier state preservation.David Daney
For OCTEON, implement a save and restore of the multiplier state across context switches. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Add SMP_ICACHE_FLUSH for the Cavium CPU family.David Daney
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Add Cavium OCTEON specific registers to ptrace.h and asm-offsets.cDavid Daney
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Add Cavium OCTEON cop2/cvmseg state entries to processor.h.David Daney
Add in the cop2 and cvmseg state info to the known proc reg data for Cavium so that it can be tracked, saved, restored. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Modify core io.h macros to account for the Octeon Errata Core-301.David Daney
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Hook up Cavium OCTEON in arch/mips.David Daney
Take all the OCTEON specific files that were added, and hook them into the build system for the arch/mips. For versions of GCC that lack OCTEON support, override gas target architecture. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Hook Cavium OCTEON cache init into cache.cDavid Daney
Follow precedent of other boards, and hook-up the CPU specific cache init. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Add Cavium OCTEON processor constants and CPU probe.David Daney
Add OCTEON constants to asm/cpu.h and asm/module.h. Add probe function for Cavium OCTEON CPUs and hook it up. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Override assembler target architecture for octeon.David Daney
Gas from binutils 2.19 fails to compile some cop1 instructions with -march=octeon. Since the cop1 instructions are present in mips1, use that arch instead. This will be fixed in binutils 2.20. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Add Cavium OCTEON specific register definitions to mipsregs.hDavid Daney
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: For Cavium OCTEON set hwrena and lazily restore CP2 state.David Daney
If on Cavium, be aware of cop2 and hwrena during do_cpu(). Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: For Cavium OCTEON handle hazards as per the R10000 handling.David Daney
For Cavium CPU, we treat the same as R10000, in that all hazards are dealt with in hardware. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon.David Daney
These are the rest of the new files needed to add OCTEON processor support to the Linux kernel. Other than Makefile and Kconfig which should be obvious, we have: csrc-octeon.c -- Clock source driver for OCTEON. dma-octeon.c -- Helper functions for mapping DMA memory. flash_setup.c -- Register on-board flash with the MTD subsystem. octeon-irq.c -- OCTEON interrupt controller managment. octeon-memcpy.S -- Optimized memcpy() implementation. serial.c -- Register 8250 platform driver and early console. setup.c -- Early architecture initialization. smp.c -- OCTEON SMP support. octeon_switch.S -- Scheduler context switch for OCTEON. c-octeon.c -- OCTEON cache controller support. cex-oct.S -- OCTEON cache exception handler. asm/mach-cavium-octeon/*.h -- Architecture include files. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 arch/mips/cavium-octeon/Kconfig create mode 100644 arch/mips/cavium-octeon/Makefile create mode 100644 arch/mips/cavium-octeon/csrc-octeon.c create mode 100644 arch/mips/cavium-octeon/dma-octeon.c create mode 100644 arch/mips/cavium-octeon/flash_setup.c create mode 100644 arch/mips/cavium-octeon/octeon-irq.c create mode 100644 arch/mips/cavium-octeon/octeon-memcpy.S create mode 100644 arch/mips/cavium-octeon/serial.c create mode 100644 arch/mips/cavium-octeon/setup.c create mode 100644 arch/mips/cavium-octeon/smp.c create mode 100644 arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/irq.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/war.h create mode 100644 arch/mips/include/asm/octeon/octeon.h create mode 100644 arch/mips/kernel/octeon_switch.S create mode 100644 arch/mips/mm/c-octeon.c create mode 100644 arch/mips/mm/cex-oct.S
2009-01-11MIPS: Add Cavium OCTEON processor support files to ↵David Daney
arch/mips/cavium-octeon/executive and asm/octeon. These files are used to coordinate resource sharing between all of the programs running on the OCTEON SOC. The OCTEON processor has many CPU cores (current parts have up to 16, but more are possible). It also has a variety of on-chip hardware blocks for things like network acceleration, encryption and RAID. One typical configuration is to run Linux on several of the CPU cores, and other dedicated applications on the other cores. Resource allocation between the various programs running on the system (Linux kernel and other dedicated applications) needs to be coordinated. The code we use to do this we call the 'executive'. All of this resource allocation and sharing code is gathered together in the executive directory. Included in the patch set are the following files: cvmx-bootmem.c and cvmx-sysinfo.c -- Coordinate memory allocation. All memory used by the Linux kernel is obtained here at boot time. cvmx-l2c.c -- Coordinates operations on the shared level 2 cache. octeon-model.c -- Probes chip capabilities and version. The corresponding headers are in asm/octeon. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 arch/mips/cavium-octeon/executive/Makefile create mode 100644 arch/mips/cavium-octeon/executive/cvmx-bootmem.c create mode 100644 arch/mips/cavium-octeon/executive/cvmx-l2c.c create mode 100644 arch/mips/cavium-octeon/executive/cvmx-sysinfo.c create mode 100644 arch/mips/cavium-octeon/executive/octeon-model.c create mode 100644 arch/mips/include/asm/octeon/cvmx-asm.h create mode 100644 arch/mips/include/asm/octeon/cvmx-bootinfo.h create mode 100644 arch/mips/include/asm/octeon/cvmx-bootmem.h create mode 100644 arch/mips/include/asm/octeon/cvmx-l2c.h create mode 100644 arch/mips/include/asm/octeon/cvmx-packet.h create mode 100644 arch/mips/include/asm/octeon/cvmx-spinlock.h create mode 100644 arch/mips/include/asm/octeon/cvmx-sysinfo.h create mode 100644 arch/mips/include/asm/octeon/cvmx.h create mode 100644 arch/mips/include/asm/octeon/octeon-feature.h create mode 100644 arch/mips/include/asm/octeon/octeon-model.h
2009-01-11MIPS: Add Cavium OCTEON processor CSR definitionsDavid Daney
Here we define the addresses and bit-fields of the Configuration and Status Registers (CSRs) for some of the hardware functional units on the OCTEON SOC. Definitions are needed for: CIU -- Central Interrupt Unit. GPIO -- General Purpose Input Output. IOB -- Input / Output {Busing,Bridge}. IPD -- Input Packet Data unit. L2C -- Level-2 Cache controller. L2D -- Level-2 Data cache. L2T -- Level-2 cache Tag. LED -- Light Emitting Diode controller. MIO -- Miscellaneous Input / Output. POW -- Packet Order / Work unit. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Alchemy: Change strict_strtol to strict_strtoulJulia Lawall
Since memsize is unsigned, it would seem better to use strict_strtoul that strict_strtol. A simplified version of the semantic patch that makes this change is as follows: (http://www.emn.fr/x-info/coccinelle/) // <smpl> @s2@ long e; position p; @@ strict_strtol@p(...,&e) @@ position p != s2.p; type T; T e; @@ - strict_strtol@p + strict_strtoul (...,&e) // </smpl> Signed-off-by: Julia Lawall <julia@diku.dk> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: 64-bit: Use generic 32-bit ptrace compat code.Anirban Sinha
Signed-off-by: Anirban Sinha <asinha@zeugmasystems.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-07Merge branch 'linux-next' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6 * 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (98 commits) PCI PM: Put PM callbacks in the order of execution PCI PM: Run default PM callbacks for all devices using new framework PCI PM: Register power state of devices during initialization PCI PM: Call pci_fixup_device from legacy routines PCI PM: Rearrange code in pci-driver.c PCI PM: Avoid touching devices behind bridges in unknown state PCI PM: Move pci_has_legacy_pm_support PCI PM: Power-manage devices without drivers during suspend-resume PCI PM: Add suspend counterpart of pci_reenable_device PCI PM: Fix poweroff and restore callbacks PCI: Use msleep instead of cpu_relax during ASPM link retraining PCI: PCIe portdrv: Add kerneldoc comments to remining core funtions PCI: PCIe portdrv: Rearrange code so that related things are together PCI: PCIe portdrv: Fix suspend and resume of PCI Express port services PCI: PCIe portdrv: Add kerneldoc comments to some core functions x86/PCI: Do not use interrupt links for devices using MSI-X net: sfc: Use pci_clear_master() to disable bus mastering PCI: Add pci_clear_master() as opposite of pci_set_master() PCI hotplug: remove redundant test in cpq hotplug PCI: pciehp: cleanup register and field definitions ...
2009-01-07Merge branch 'proc-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/adobriyan/proc * 'proc-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/adobriyan/proc: proc: remove write-only variable in proc_pident_lookup() proc: fix sparse warning proc: add /proc/*/stack proc: remove '##' usage proc: remove useless WARN_ONs proc: stop using BKL
2009-01-07Merge branch 'for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (24 commits) trivial: chack -> check typo fix in main Makefile trivial: Add a space (and a comma) to a printk in 8250 driver trivial: Fix misspelling of "firmware" in docs for ncr53c8xx/sym53c8xx trivial: Fix misspelling of "firmware" in powerpc Makefile trivial: Fix misspelling of "firmware" in usb.c trivial: Fix misspelling of "firmware" in qla1280.c trivial: Fix misspelling of "firmware" in a100u2w.c trivial: Fix misspelling of "firmware" in megaraid.c trivial: Fix misspelling of "firmware" in ql4_mbx.c trivial: Fix misspelling of "firmware" in acpi_memhotplug.c trivial: Fix misspelling of "firmware" in ipw2100.c trivial: Fix misspelling of "firmware" in atmel.c trivial: Fix misspelled firmware in Kconfig trivial: fix an -> a typos in documentation and comments trivial: fix then -> than typos in comments and documentation trivial: update Jesper Juhl CREDITS entry with new email trivial: fix singal -> signal typo trivial: Fix incorrect use of "loose" in event.c trivial: printk: fix indentation of new_text_line declaration trivial: rtc-stk17ta8: fix sparse warning ...
2009-01-07PCI: mips: use generic INTx swizzle from PCI coreBjorn Helgaas
Use the generic pci_common_swizzle() instead of arch-specific code. Note that pci_common_swizzle() loops based on dev->bus->self, not dev->bus->parent as the mips common_swizzle() did. I think they are equivalent for this purpose. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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