aboutsummaryrefslogtreecommitdiff
path: root/arch/mips
AgeCommit message (Collapse)Author
2009-01-30MIPS: RC32434: Define io_map_base for PCI controllerPhil Sutter
The code is rather based on trial-and-error than knowledge. Verified Via Rhine functionality in PIO as well as MMIO mode. [Looks sane -- Ralf] Signed-off-by: Phil Sutter <n0-1@freewrt.org> Tested-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-30MIPS: RB532: Fix bit swapping in rb532_set_bit()Phil Sutter
The algorithm works unconditionally. If bitval is one, the first line is a no op and the second line sets the bit at offset position. Vice versa, if bitval is zero, the first line clears the bit at offset position and the second line is a no op. Signed-off-by: Phil Sutter <n0-1@freewrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-30MIPS: Use hardware watchpoints on all R1 and R2 CPUs.David Daney
The previous definition inadvertently omits Octeon which currently is treated as an architecture variant separate from MIPS32 and MIPS64. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-30MIPS: Read watch registers with interrupts disabled.David Daney
If a context switch occurred between the watch exception and reading the watch registers, it would be possible for the new process to corrupt their state. Enabling interrupts only after the watch registers are read avoids this race. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-30MIPS: Fix a typo in watchpoint register structure.David Daney
This fixes the ptrace ABI for watch registers, and should allow 64bit kernels to use the watch register support. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-30MIPS: TXx9: Add support for TX4939 internal RTCAtsushi Nemoto
Add platform support to use rtc-tx4939 driver. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-30MIPS: R2: Fix broken installation of cache error handler.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-30MIPS: IP27: Switch from DMA_IP27 to DMA_COHERENTRalf Baechle
The special IP27 DMA code selected by DMA_IP27 has been removed a while ago turning DMA_IP27 into almost a nop. Also fixup the broken logic of its last users memcpy.S and memcpy-inatomic.s. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-30MIPS: Add return value checks to user_termio_to_kernel_termios()Ralf Baechle
And while at it, convert all functions from macros to inline functions for sanity. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-30MIPS: Octeon: Remove duplicated #includesHuang Weiyi
Signed-off-by: Huang Weiyi <weiyi.huang@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-30MIPS: atomic_*(): Change type of intermediate variables.Ralf Baechle
This shaves of 1912 bytes of an IP27 defconfig kernel and avoids unexpected overflow behaviour in atomic_sub_if_positive. Apply the same changes to the atomic64_* functions for consistency. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-30MIPS: Port "mm: invoke oom-killer from page fault" from UML / x86Ralf Baechle
Original commit 1c0fe6e3bda0464728c23c8d84aa47567e8b716c. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-30MIPS: Avoid destructive invalidation on partial cachelines.Ralf Baechle
See discussion e9c3a7c20901051031y528d0d31r18d44c5096c59e0@mail.gmail.com. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-30MIPS: SMTC: Fix build after recent creditial changes.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-26eeprom: More consistent symbol namesJean Delvare
Now that all EEPROM drivers live in the same place, let's harmonize their symbol names. Also fix eeprom's dependencies, it definitely needs sysfs, and is no longer experimental after many years in the kernel tree. Signed-off-by: Jean Delvare <khali@linux-fr.org> Acked-by: Wolfram Sang <w.sang@pengutronix.de> Cc: David Brownell <dbrownell@users.sourceforge.net>
2009-01-14Merge branch 'syscalls' of git://git390.osdl.marist.edu/pub/scm/linux-2.6Linus Torvalds
* 'syscalls' of git://git390.osdl.marist.edu/pub/scm/linux-2.6: (44 commits) [CVE-2009-0029] s390 specific system call wrappers [CVE-2009-0029] System call wrappers part 33 [CVE-2009-0029] System call wrappers part 32 [CVE-2009-0029] System call wrappers part 31 [CVE-2009-0029] System call wrappers part 30 [CVE-2009-0029] System call wrappers part 29 [CVE-2009-0029] System call wrappers part 28 [CVE-2009-0029] System call wrappers part 27 [CVE-2009-0029] System call wrappers part 26 [CVE-2009-0029] System call wrappers part 25 [CVE-2009-0029] System call wrappers part 24 [CVE-2009-0029] System call wrappers part 23 [CVE-2009-0029] System call wrappers part 22 [CVE-2009-0029] System call wrappers part 21 [CVE-2009-0029] System call wrappers part 20 [CVE-2009-0029] System call wrappers part 19 [CVE-2009-0029] System call wrappers part 18 [CVE-2009-0029] System call wrappers part 17 [CVE-2009-0029] System call wrappers part 16 [CVE-2009-0029] System call wrappers part 15 ...
2009-01-14byteorder: make swab.h include asm/swab.h like a regular headerHarvey Harrison
Add swab.h to kbuild.asm and remove the individual entries from each arch, mark as unifdef as some arches have some kernel-only bits inside. Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-01-14[CVE-2009-0029] Rename old_readdir to sys_old_readdirHeiko Carstens
This way it matches the generic system call name convention. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
2009-01-11MIPS: Only write c0_framemask on CPUs which have this register.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Alchemy: new userspace suspend interface for development boards.Manuel Lauss
Replace the current sysctl-based suspend interface with a new sysfs- based one which also uses the Linux-2.6 suspend model. To configure wakeup sources, a subtree for the demoboards is created under /sys/power/db1x: sys/ `-- power `-- db1x |-- gpio0 |-- gpio1 |-- gpio2 |-- gpio3 |-- gpio4 |-- gpio5 |-- gpio6 |-- gpio7 |-- timer |-- timer_timeout |-- wakemsk `-- wakesrc The nodes 'gpio[0-7]' and 'timer' configure the GPIO0..7 and M2 bits of the SYS_WAKEMSK (wakeup source enable) register. Writing '1' enables a wakesource, 0 disables it. The 'timer_timeout' node holds the timeout in seconds after which the TOYMATCH2 event should wake the system. The 'wakesrc' node holds the SYS_WAKESRC register after wakeup (in hex), the 'wakemsk' node can be used to get/set the wakeup mask directly. For example, to have the timer wake the system after 10 seconds of sleep, the following must be done in userspace: echo 10 > /sys/power/db1x/timer_timeout echo 1 > /sys/power/db1x/timer echo mem > /sys/power/sleep This patch also removes the homebrew CPU frequency switching code. I don't understand how it could have ever worked reliably; it does not communicate the clock changes to peripheral devices other than uarts. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 arch/mips/alchemy/devboards/pm.c
2009-01-11MIPS: Alchemy: dbdma suspend/resume support.Manuel Lauss
Implement suspend/resume for DBDMA controller and its channels. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Alchemy: Fix up PM code on Au1550/Au1200Manuel Lauss
Au1550/Au1200 have a different memory controller which requires additi- onal code to properly put memory to sleep (code taken from AMD/RMI's Linux-2.6.11 source package). Also fix up the remaining pm-related paths to compile on Au1200/Au1550 platforms. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Alchemy: move calc_clock function.Manuel Lauss
Now that nothing in time.c depends on calc_clock, it can be moved to clocks.c where it belongs. While at it, give it a better non-generic name and call it as soon as possible in plat_mem_init. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Alchemy: RTC counter clocksource / clockevent support.Manuel Lauss
Add support for the 32 kHz counter1 (RTC) as clocksource / clockevent device. As a nice side effect, this also enables use of the 'wait' instruction for runtime idle power savings. If the counters aren't enabled/working properly, fall back on the cp0 counter clock code. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: make cp0 counter clocksource/event usable as fallback.Manuel Lauss
The current mips clock build infrastructure lets a system only use either the MIPS cp0 counter or a SoC specific timer as a clocksource / clockevent device. This patch renames the core cp0 counter clocksource / clockevent functions from mips_* to r4k_* and updates the wrappers in asm-mips/time.h to call these renamed functions instead. Chips which can detect whether it is safe to use a chip-specific timer can now fall back on the cp0 counter if necessary and possible (e.g. Alchemy with a follow-on patch). Existing behaviour is not changed in any way. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Alchemy: remove cpu_table.Manuel Lauss
Remove the cpu_table: - move detection of whether c0_config[OD] is read-only and should be set to fix various chip errata to au1000 headers. - move detection of write-only sys_cpupll to au1000 headers. - remove the BCLK switching code: Activation of this features should be left to the boards using the chips since it also affects external devices tied to BCLK, and only the board designers know whether it is safe to enable. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> delete mode 100644 arch/mips/alchemy/common/cputable.c
2009-01-11MIPS: Alchemy: remove get/set_au1x00_lcd_clock().Manuel Lauss
There are no in-tree users, so remove them. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Print irq handler descriptionManuel Lauss
Add the name set by set_irq_chip_and_handler_name() to the output of /proc/interrupts, like so: db1200 ~ # cat /proc/interrupts CPU0 8: 52 Alchemy-IC0-hilevel serial 10: 171 Alchemy-IC0-hilevel au1xxx-mmc 11: 47 Alchemy-IC0-hilevel Au1xxx dbdma 18: 1 Alchemy-IC0-hilevel au1550-spi 29: 1250997 Alchemy-IC0-riseedge timer 37: 211 Alchemy-IC0-hilevel ehci_hcd:usb1, ohci_hcd:usb2 38: 0 Alchemy-IC0-hilevel lcd 72: 2623 DB1200 CPLD-level ide0 73: 257 DB1200 CPLD-level eth0 84: 1 DB1200 CPLD-level sd_insert 85: 0 DB1200 CPLD-level sd_eject ERR: 0 Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Alchemy: pb1200: update CPLD cascade irq handler.Manuel Lauss
Tested on Db1200. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Alchemy: update core interrupt code.Manuel Lauss
This patch attempts to modernize core Alchemy interrupt handling code. - add irq_chips for irq controllers instead of irq type, - add a set_type() hook to change irq trigger type during runtime, - add a set_wake() hook to control GPIO0..7 based wakeup, - use linux' IRQF_TRIGGER_ constants instead of homebrew ones, - enable GENERIC_HARDIRQS_NO__DO_IRQ. - simplify plat_irq_dispatch - merge au1xxx_irqmap into irq.c file, the only place where its contents are referenced. - board_init_irq() is now mandatory for every board; use it to register the remaining (gpio-based) interrupt sources; update all boards accordingly. Run-tested on Db1200 and other Au1200 based platforms. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> delete mode 100644 arch/mips/alchemy/common/au1xxx_irqmap.c
2009-01-11MIPS: Alchemy: move commandline mangling out of common codeManuel Lauss
Not every alchemy-based board might want these options forced on it, and most of this stuff seems to be intended for devboard code anyway. Remove commandline mangling code out of common chip code and instead add relevant sections to all in-tree boards to not change existing behaviour. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Alchemy: devboards: consolidate filesManuel Lauss
Share some code and merge small files: - Extract the prom init code from all devboard files (they only differ in memory configuration). - Merge the irq configuration into board setup code. - Merge smaller files into board setup code. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> delete mode 100644 arch/mips/alchemy/devboards/db1x00/init.c delete mode 100644 arch/mips/alchemy/devboards/pb1000/init.c delete mode 100644 arch/mips/alchemy/devboards/pb1000/irqmap.c delete mode 100644 arch/mips/alchemy/devboards/pb1100/init.c delete mode 100644 arch/mips/alchemy/devboards/pb1100/irqmap.c delete mode 100644 arch/mips/alchemy/devboards/pb1200/init.c delete mode 100644 arch/mips/alchemy/devboards/pb1500/init.c delete mode 100644 arch/mips/alchemy/devboards/pb1500/irqmap.c delete mode 100644 arch/mips/alchemy/devboards/pb1550/init.c delete mode 100644 arch/mips/alchemy/devboards/pb1550/irqmap.c create mode 100644 arch/mips/alchemy/devboards/prom.c
2009-01-11MIPS: Alchemy: Move development board code to common subdirectoryManuel Lauss
This should ease sharing of common devboard code. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Add Cavium OCTEON to arch/mips/KconfigDavid Daney
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Add defconfig for Cavium OCTEON.David Daney
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Adjust the dma-common.c platform hooks.David Daney
We add a dev parameter to plat_unmap_dma_mem(), and hooks for plat_dma_supported() and plat_extra_sync_for_device() which should be nop changes for all existing targets. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Add Cavium OCTEON slot into proper tlb category.David Daney
Expand the case statement for build_tlb_write_entry so that it does the right thing on Cavium CPU variants. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Compute branch returns for Cavium OCTEON specific branch instructions.David Daney
For Cavium OCTEON, compute the return epc value for OCTEON specific branch instructions. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Cavium OCTEON multiplier state preservation.David Daney
For OCTEON, implement a save and restore of the multiplier state across context switches. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Add SMP_ICACHE_FLUSH for the Cavium CPU family.David Daney
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Add Cavium OCTEON specific registers to ptrace.h and asm-offsets.cDavid Daney
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Add Cavium OCTEON cop2/cvmseg state entries to processor.h.David Daney
Add in the cop2 and cvmseg state info to the known proc reg data for Cavium so that it can be tracked, saved, restored. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Modify core io.h macros to account for the Octeon Errata Core-301.David Daney
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Hook up Cavium OCTEON in arch/mips.David Daney
Take all the OCTEON specific files that were added, and hook them into the build system for the arch/mips. For versions of GCC that lack OCTEON support, override gas target architecture. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Hook Cavium OCTEON cache init into cache.cDavid Daney
Follow precedent of other boards, and hook-up the CPU specific cache init. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Add Cavium OCTEON processor constants and CPU probe.David Daney
Add OCTEON constants to asm/cpu.h and asm/module.h. Add probe function for Cavium OCTEON CPUs and hook it up. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Override assembler target architecture for octeon.David Daney
Gas from binutils 2.19 fails to compile some cop1 instructions with -march=octeon. Since the cop1 instructions are present in mips1, use that arch instead. This will be fixed in binutils 2.20. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: Add Cavium OCTEON specific register definitions to mipsregs.hDavid Daney
Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: For Cavium OCTEON set hwrena and lazily restore CP2 state.David Daney
If on Cavium, be aware of cop2 and hwrena during do_cpu(). Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11MIPS: For Cavium OCTEON handle hazards as per the R10000 handling.David Daney
For Cavium CPU, we treat the same as R10000, in that all hazards are dealt with in hardware. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-20 23:53:40 +0000