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We shouldn't directly access sysdata to get the pci_controller. Instead
use pci_bus_to_host() for this purpose. In the future we might have
sysdata be a device_node to match ppc64 and unify the code between ppc32
& ppc64.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Previouslly we just always set the inbound window to 2G. This was
broken for systems with >2G. If a system has >=4G we will need
SWIOTLB support to handle that case.
We now allocate PCICSRBAR/PEXCSRBAR right below the lowest PCI outbound
address for MMIO or the 4G boundary (if the lowest PCI address is above
4G).
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The P2020 is a dual e500v2 core based SOC with:
* 3 PCIe controllers
* 2 General purpose DMA controllers
* 2 sRIO controllers
* 3 eTSECS
* USB 2.0
* SDHC
* SPI, I2C, DUART
* enhanced localbus
* and optional Security (P2020E) security w/XOR acceleration
The p2020 DS reference board is pretty similar to the existing MPC85xx
DS boards and has a ULI 1575 connected on one of the PCIe controllers.
Signed-off-by: Ted Peters <Ted.Peters@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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This patch adds PCI IDs for MPC8569 and MPC8569E processors,
plus adds appropriate quirks for these IDs, and thus makes
PCI-E actually work on MPC8569E-MDS boards.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Also, convert them to resource_size_t (which is unsigned long
on 64-bit, so it's not a change there).
We will be using these on fsl 32b to indicate the start and size
address of memory that the pci controller can actually reach - this
is needed to determine if an address requires bounce buffering. For
now, initialize them to a standard value; in the near future, the
value will be calculated based on how the inbound windows are
programmed.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Ben Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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This patch adds support for PCI-Express controllers as found on the
newer MPC83xx chips.
The work is loosely based on the Tony Li's patch[1], but unlike the
original patch, this patch implements sliding window for the Type 1
transactions using outbound window translations, so we don't have to
ioremap the whole PCI-E configuration space.
[1] http://ozlabs.org/pipermail/linuxppc-dev/2008-January/049028.html
Signed-off-by: Tony Li <tony.li@freescale.com>
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Provides a small speedup when accessing pefetchable ranges. To indicate
that a memory range is prefetchable, mark it in the dts file with 42000000
instead of 02000000.
A powepc pci_controller is allowed three memory ranges, any of which may be
prefetchable. However, the PCI-PCI bridge configuration space only has one
field for "non-prefetchable memory behind bridge", which has a 32 bit
address, and one field for "prefetchable memory behind bridge", which may
have a 64 bit address. These are PCI bus addresses, not CPU physical
addresses.
So really you're only allowed one memory range of each type. And if you
want the range at a PCI address above 32 bits you must make it
prefetchable.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The code that sets up the outbound ATMU windows, which is used to map CPU
physical addresses into PCI bus addresses where BARs will be mapped, didn't
work so well.
For one, it leaked the ioremap() of the ATMU registers. Another small bug
was the high 20 bits of the PCI bus address were left as zero. It's legal
for prefetchable memory regions to be above 32 bits, so the high 20 bits
might not be zero.
Mainly, it couldn't handle ranges that were not a power of two in size or
were not naturally aligned. The ATMU windows have these requirements (size
& alignment), but the code didn't bother to check if the ranges it was
programming met them. If they didn't, the windows would silently be
programmed incorrectly.
This new code can handle ranges which are not power of two sized nor
naturally aligned. It simply splits the ranges into multiple valid ATMU
windows. As there are only four windows, pooly aligned or sized ranges
(which didn't even work before) may run out of windows. In this case an
error is printed and an effort is made to disable the unmapped resources.
An improvement that could be made would be to make use of the default
outbound window. Iff hose->pci_mem_offset is zero, then it's possible that
some or all of the ranges might not need an outbound window and could just
use the default window.
The default ATMU window can support a pci_mem_offset less than zero too,
but pci_mem_offset is unsigned. One could say the abilities allowed a
powerpc pci_controller is neither subset nor a superset of the abilities of
a Freescale PCIe controller. Thankfully, the most useful bits are in the
intersection of the two abilities.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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This patch fixes following sparse warnings:
CHECK fsl_pci.c
fsl_pci.c:32:13: warning: symbol 'setup_pci_atmu' was not declared. Should it be static?
fsl_pci.c:89:13: warning: symbol 'setup_pci_cmd' was not declared. Should it be static?
fsl_pci.c:133:12: warning: symbol 'fsl_pcie_check_link' was not declared. Should it be static?
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Currently there are a number of platforms that open code access to
the ppc_pci_flags global variable. However, that variable is not
present if CONFIG_PCI is not set, which can lead to a build break.
This introduces a number of accessor functions that are defined
to be empty in the case of CONFIG_PCI being disabled. The
various platform files in the kernel are updated to use these.
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
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Uses mpc83xx_add_bridge in fsl_pci.c
Adds second register tuple to pci node register property
as done for 83xx device trees in a previous patch.
Signed-off-by: John Rigby <jrigby@freescale.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Modify mpc83xx_add_bridge to get config space register base address from
the device tree instead of immr + hardcoded offset.
83xx pci nodes have this change:
register properties now contain two address length tuples:
First is the pci bridge register base, this has always been there.
Second is the config base, this is new.
This is documented in dts-bindings/fsl/83xx-512x-pci.txt
The changes accomplish these things:
mpc83xx_add_bridge no longer needs to call get_immrbase
it uses hard coded addresses if the second register value is missing
Signed-off-by: John Rigby <jrigby@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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This allows other platforms with the same pci block like MPC5121 to use it.
Signed-off-by: John Rigby <jrigby@freescale.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Add support for the MPC8536 process and MPC8536DS reference board. The
MPC8536 is an e500v2 based SoC which eTSEC, USB, SATA, PCI, and PCIe.
The USB and SATA IP blocks are similiar to those on the PQ2 Pro SoCs and
thus use the same drivers.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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This patch fixes few cosmetic issues, also removes unused function,
makes some functions static and reduces #ifdef count.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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This MSI driver can be used on 83xx/85xx/86xx board.
In this driver, virtual interrupt host and chip were
setup. There are 256 MSI interrupts in this host, Every 32
MSI interrupts cascaded to one IPIC/MPIC interrupt.
The chip was treated as edge sensitive and some necessary
functions were setup for this chip.
Before using the MSI interrupt, PCI/PCIE device need to
ask for a MSI interrupt in the 256 MSI interrupts. A 256bit
bitmap show which MSI interrupt was used, reserve bit in
the bitmap can be used to force the device use some designate
MSI interrupt in the 256 MSI interrupts. Sometimes this is useful
for testing the all the MSI interrupts. The msi-available-ranges
property in the dts file was used for this purpose.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The current PCI code for Freescale 85xx/86xx was treating the virtual
P2P PCIe bridge as a transparent bridge. Rather than doing that fixup
the virtual P2P bridge by copying the resources from the PHB.
Also, fixup a bit of the code for dealing with resource_size_t being
64-bits and how we set ATMU registers for >4G.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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This adds to the 32 bits PCI code some flags, replacing the old
pci_assign_all_busses global, that allow us to control various
aspects of the PCI probing, such as whether to re-assign all
resources or not, or to not try to assign anything at all.
This also adds the flag x86 already has to avoid ISA alignment
on bridges that don't have ISA forwarding enabled (no legacy
devices on the top level bus) and sets it for PowerMacs.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
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Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
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Signed-off-by: Tony Li <tony.li@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The LTSSM register is actual 32-bits wide so we should be doing a
dword access.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Added basic board port for MPC8572 DS reference platform that is
similiar to the MPC8544/33 DS reference platform in uniprocessor mode.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The initial user manuals for MPC8544/8533 had some issues with properly
documenting the device IDs for MPC8544/8533. These processors are almost
identical and both show up on the reference boards.
Fix up the quirks for PCIe support to handle MPC8533/E.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Fixed the following warnings:
WARNING: vmlinux.o(.text+0x2934): Section mismatch: reference to .init.text:__alloc_bootmem (between 'irq_alloc_host' and 'irq_set_default_host')
WARNING: vmlinux.o(.text+0xb2aa): Section mismatch: reference to .init.data:boot_command_line (between 'register_early_udbg_console' and 'udbg_printf')
WARNING: vmlinux.o(.text+0xb2b2): Section mismatch: reference to .init.data:boot_command_line (between 'register_early_udbg_console' and 'udbg_printf')
WARNING: vmlinux.o(.text+0xe354): Section mismatch: reference to .init.text:__alloc_bootmem (between 'pcibios_alloc_controller' and 'pci_domain_nr')
WARNING: vmlinux.o(.text+0x12768): Section mismatch: reference to .init.text:update_bridge_resource (between 'quirk_fsl_pcie_transparent' and 'indirect_read_config')
WARNING: vmlinux.o(.text+0x127a8): Section mismatch: reference to .init.text:update_bridge_resource (between 'quirk_fsl_pcie_transparent' and 'indirect_read_config')
WARNING: vmlinux.o(.text+0x17566c): Section mismatch: reference to .init.text:pcibios_fixup_bus (between 'pci_scan_child_bus' and 'pci_scan_bus_parented')
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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We didn't actually propogate the flag we pass into setup_indirect_pci()
to set indirect_type and thus were getting the wrong endianness if
PPC_INDIRECT_TYPE_BIG_ENDIAN was set.
Also, we need to or in additional flags rather than just doing a
direct assignment.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Added the MPC85xx PCI device IDs that we need for the quirks we have.
Also, fixed the MPC8567E, MPC8567 device IDs which had the wrong value.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Also add 8641/8641D device IDs as well.
All of which already exist or have been submitted to
The Linux PCI ID Repository at:
http://pci-ids.ucw.cz/
CC-to: pci-ids@ucw.cz
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Some set of 85xx platforms have PCI-X controllers. The old arch/ppc
code setup these controllers and we haven't moved it over to arch/powerpc.
We use the PCI-X Capabilties to know if we are in PCI-X mode instead
of the Global Utilities PORDEVSR.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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For the Freescale PCIe PHBs Not all firmwares setup the virtual P2P
bridge registers properly. Make sure they get setup based on what
the struct pci_controller got from the device tree.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Add basic support for the PCIe PHB and enable the ULI bridge.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Make it so we do a runtime check to know if we need to write cfg_addr
as big or little endian. This is needed if we want to allow 86xx support
to co-exist in the same kernel as other 6xx PPCs.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Added the PCIe device node to the 8568 dts and the needed quirk entries.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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On the 85xx/86xx PCIe controllers if there is no device connected to the
PHB we will still allocate a pci_bus for downstream bus of the virtual
P2P bridge. However the resources allocated to the downstream bus are not
correct and so we just mimic the resources from the upstream pci_bus.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Switch the 85xx platform over to using the FSL generic PCI code. This
gets ups PCIe support in addition to base PCI support.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Use the PCI capabilities to determine if we are PCIe PHB. Also use
PPC_INDIRECT_TYPE_NO_PCIE_LINK since the Freescale PCIe controllers
will lock the system if they don't have link and you try to do a config
access to anything but the PHB.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Rewrite the Freescale PCI code to support PCI on 83xx/85xx/86xx and
PCIe on 85xx/86xx.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Move
arch/powerpc/platforms/86xx/pci.c -> arch/powerpc/sysdev/fsl_pci.c
arch/powerpc/sysdev/fsl_pcie.h -> arch/powerpc/sysdev/fsl_pci.h
as the base to unify 83xx/85xx/86xx pci and pcie.
Add CONFIG_FSL_PCI to build fsl_pci.c for Freescale pci and pcie option.
The code still works for 86xx platforms.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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