| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2007-05-12 | [POWERPC] Add interrupt support for Marvell mv64x60 chips | Dale Farnsworth | |
| There are 3 interrupt groups each with its own status/mask registers. We use a separate struct irq_chip for each interrupt group and handle interrupts in two stages or levels: level 1 selects the appropriate struct irq_chip, and level 2 selects individual interrupts within that irq_chip. Signed-off-by: Dale Farnsworth <dale@farnsworth.org> Signed-off-by: Paul Mackerras <paulus@samba.org> | |||
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