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path: root/arch/sparc64/kernel/tsb.S
AgeCommit message (Expand)Author
2006-03-20[SPARC64]: More TLB/TSB handling fixes.David S. Miller
2006-03-20[SPARC64]: Fix some SUN4V TLB handling bugs.David S. Miller
2006-03-20[SPARC64]: Do not write garbage into %pstate in tsb_context_switch().David S. Miller
2006-03-20[SPARC64]: Deal with PTE layout differences in SUN4V.David S. Miller
2006-03-20[SPARC64]: Simplify sun4v TLB handling using macros.David S. Miller
2006-03-20[SPARC64]: Fix hypervisor call arg passing.David S. Miller
2006-03-20[SPARC64]: Hypervisor TSB context switching.David S. Miller
2006-03-20[SPARC64]: Implement sun4v TSB miss handlers.David S. Miller
2006-03-20[SPARC64]: Rename gl_{1,2}insn_patch --> sun4v_{1,2}insn_patchDavid S. Miller
2006-03-20[SPARC64]: Initial sun4v TLB miss handling infrastructure.David S. Miller
2006-03-20[SPARC64]: Sanitize %pstate writes for sun4v.David S. Miller
2006-03-20[SPARC64]: Refine register window trap handling.David S. Miller
2006-03-20[SPARC64]: Add explicit register args to trap state loading macros.David S. Miller
2006-03-20[SPARC64]: Access TSB with physical addresses when possible.David S. Miller
2006-03-20[SPARC64]: Fix too early reference to %g6David S. Miller
2006-03-20[SPARC64]: Kill PROM locked TLB entry preservation code.David S. Miller
2006-03-20[SPARC64]: Use sparc64_highest_unlocked_tlb_ent in __tsb_context_switch()David S. Miller
2006-03-20[SPARC64]: Preload TSB entries from update_mmu_cache().David S. Miller
2006-03-20[SPARC64]: Add infrastructure for dynamic TSB sizing.David S. Miller
2006-03-20[SPARC64]: TSB refinements.David S. Miller
2006-03-20[SPARC64]: Elminate all usage of hard-coded trap globals.David S. Miller
2006-03-20[SPARC64]: Move away from virtual page tables, part 1.David S. Miller