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2008-07-08x86: remove open-coded save/load segment operationsJeremy Fitzhardinge
This removes a pile of buggy open-coded implementations of savesegment and loadsegment. (They are buggy because they don't have memory barriers to prevent them from being reordered with respect to memory accesses.) Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com> Cc: xen-devel <xen-devel@lists.xensource.com> Cc: Stephen Tweedie <sct@redhat.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Mark McLoughlin <markmc@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-08x86: perfctr-watchdog.c - coding style cleanupCyrill Gorcunov
Just some code beautification. Nothing else. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com> Cc: macro@linux-mips.org Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-08x86: move boot_params declaring to setup.cYinghai Lu
Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-08x86: merge setup64.c into common_64.cYinghai Lu
Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-08x86: change identify_cpu to staticYinghai Lu
Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-08x86: seperate funcs from setup_64 to cpu common_64.cYinghai Lu
Signed-off-by: Yinghai Lu <yhlu.kernel@mail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-08x86: clean up init_amd()Yinghai Lu
1. move out calling of check_enable_amd_mmconf_dmi out of setup_64.c put it into init_amd(), so don't need to make extra dmi check for system with other cpus. 2. 15 --> 0xf Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-08Merge branch 'x86/nmi' into x86/develIngo Molnar
Conflicts: arch/x86/kernel/nmi.c arch/x86/kernel/nmi_32.c Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-08Merge branch 'x86/mpparse' into x86/develIngo Molnar
Conflicts: arch/x86/Kconfig arch/x86/kernel/io_apic_32.c arch/x86/kernel/setup_64.c arch/x86/mm/init_32.c Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-08x86: rename two e820 related functionsYinghai Lu
rename update_memory_range to e820_update_range rename add_memory_region to e820_add_region to make it more clear that they are about e820 map operations. Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-08Merge branch 'linus' into tmp.x86.mpparse.newIngo Molnar
2008-07-08Merge branches 'x86/numa-fixes', 'x86/apic', 'x86/apm', 'x86/bitops', ↵Ingo Molnar
'x86/build', 'x86/cleanups', 'x86/cpa', 'x86/cpu', 'x86/defconfig', 'x86/gart', 'x86/i8259', 'x86/intel', 'x86/irqstats', 'x86/kconfig', 'x86/ldt', 'x86/mce', 'x86/memtest', 'x86/pat', 'x86/ptemask', 'x86/resumetrace', 'x86/threadinfo', 'x86/timers', 'x86/vdso' and 'x86/xen' into x86/devel
2008-07-08x86: make 64-bit identify_cpu use cpu_devYinghai Lu
we may need to move some functions to common.c later Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-08x86: Move PCI IO ECS code to x86/pciRobert Richter
"Form follows function". Code is now where it belongs to. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-08x86, clockevents: add C1E aware idle functionThomas Gleixner
C1E on AMD machines is like C3 but without control from the OS. Up to now we disabled the local apic timer for those machines as it stops when the CPU goes into C1E. This excludes those machines from high resolution timers / dynamic ticks, which hurts especially X2 based laptops. The current boot time C1E detection has another, more serious flaw as well: some BIOSes do not enable C1E until the ACPI processor module is loaded. This causes systems to stop working after that point. To work nicely with C1E enabled machines we use a separate idle function, which checks on idle entry whether C1E was enabled in the Interrupt Pending Message MSR. This allows us to do timer broadcasting for C1E and covers the late enablement of C1E as well. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-03x86, mce_64.c: mce_cpu_quirks being ignoredVenki Pallipadi
Quirks getting ignored was a bug. Below patch fixes the bug, until we have the dynamic banks support. Sysfs choice configuration should not have any issues with the earlier patch as we look for NR_SYSFS_BANKS in do_machine_check(). Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Cc: Andi Kleen <andi@firstfloor.org> Cc: Max Asbock <masbock@us.ibm.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-03Merge commit 'v2.6.26-rc8' into x86/mceIngo Molnar
2008-06-18x86: coding style fixes to x86/kernel/cpu/cpufreq/cpufreq-nforce2.cPaolo Ciarrocchi
Before: total: 22 errors, 8 warnings, 440 lines checked After: total: 0 errors, 8 warnings, 442 lines checked paolo@paolo-desktop:~/linux.trees.git$ md5sum /tmp/cpufreq-nforce2.o.* 3d4330a5d188fe904446e5948a618b48 /tmp/cpufreq-nforce2.o.after 1477e6b0dcd6f59b1fb6b4490042eca6 /tmp/cpufreq-nforce2.o.before ^^^ I guess this is because I fixed a few "do not initialise statics to 0 or NULL" paolo@paolo-desktop:~/linux.trees.git$ size /tmp/cpufreq-nforce2.o.* text data bss dec hex filename 1923 72 16 2011 7db /tmp/cpufreq-nforce2.o.after 1923 72 16 2011 7db /tmp/cpufreq-nforce2.o.before Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-06-18x86: coding style fixes to arch/x86/kernel/cpu/mcheck/k7.cPaolo Ciarrocchi
Before: total: 6 errors, 13 warnings, 105 lines checked After: total: 0 errors, 0 warnings, 105 lines checked paolo@paolo-desktop:~/linux.trees.git$ size /tmp/k7* text data bss dec hex filename 1135 0 0 1135 46f /tmp/k7.o.after 1135 0 0 1135 46f /tmp/k7.o.before paolo@paolo-desktop:~/linux.trees.git$ md5sum /tmp/k7* 87b14954045aa37dbaee6fb7e022ed9a /tmp/k7.o.after 87b14954045aa37dbaee6fb7e022ed9a /tmp/k7.o.before Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-06-18x86: coding style fixes to arch/x86/kernel/cpu/mcheck/p4.cPaolo Ciarrocchi
Before: total: 16 errors, 34 warnings, 257 lines checked After: total: 0 errors, 2 warnings, 257 lines checked No changes in the compiled code: paolo@paolo-desktop:~/linux.trees.git$ size /tmp/p4* text data bss dec hex filename 2644 4 4 2652 a5c /tmp/p4.o.after 2644 4 4 2652 a5c /tmp/p4.o.before paolo@paolo-desktop:~/linux.trees.git$ md5sum /tmp/p4* 13f1b21c4246b31a28aaff38184586ca /tmp/p4.o.after 13f1b21c4246b31a28aaff38184586ca /tmp/p4.o.before Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-06-18x86: correctly report NR_BANKS in mce_64.cDaniel Rahn
attached is a no-brainer that makes kernel correctly report NR_BANKS for MCE. We are right now limited to NR_BANKS==6, but the error message will use the available number of banks instead of the defined maximum. For a Nehalem based system it will print: "MCE: warning: using only 9 banks" while the correct message would be "MCE: warning: using only 6 banks" Signed-off-by: Pavel Machek <pavel@suse.cz> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-06-16Merge branch 'linus' into x86/patIngo Molnar
2008-06-16Merge branch 'linus' into x86/cleanupsIngo Molnar
2008-06-16Merge branch 'linus' into x86/nmiIngo Molnar
Conflicts: arch/x86/kernel/nmi_32.c
2008-06-12x86: PAT: fixed checkpatch errors (and whitespaces)Andreas Herrmann
x86: PAT: fixed checkpatch errors (and whitespaces) Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-06-12x86: PAT: fix ambiguous paranoia check in pat_init()Andreas Herrmann
Starting with commit 8d4a4300854f3971502e81dacd930704cb88f606 (x86: cleanup PAT cpu validation) the PAT CPU feature flag is not cleared anymore. Now the error message "PAT enabled, but CPU feature cleared" in pat_init() is misleading. Furthermore the current code does not check for existence of the PAT CPU feature flag if a CPU is whitelisted in validate_pat_support. This patch clears pat_wc_enabled if boot CPU has no PAT feature flag and adapts the paranoia check. Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-06-12x86: unconditionally enable PAT for AMD CPUsAndreas Herrmann
If PAT support is advertised it should just work. No errata known. Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-06-10x86: use cpuinfo to check for interrupt pending message msrThomas Gleixner
Simplify code: no need to do a cpuid(1) again. The cpuinfo structure has all necessary information already. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-06-10x86: cleanup C1E enabled detectionThomas Gleixner
Rename the "MSR_K8_ENABLE_C1E" MSR to INT_PENDING_MSG, which is the name in the data sheet as well. Move the C1E mask to the header file. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-06-10fix build bug in "x86: add PCI extended config space access for AMD Barcelona"Robert Richter
Also much less code now. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-06-05x86: watchdog - check for CPU is being supportedCyrill Gorcunov
This patch does check if CPU is being recongnized before call the unreserve(). Since enable_lapic_nmi_watchdog() does have such a check the same is make sense here too in a sake of code consistency (but nothing more). Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com> Cc: mingo@redhat.com Cc: hpa@zytor.com Cc: macro@linux-mips.org Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-06-03x86: move bugs_64.c to cpu/bugs_64.cHiroshi Shimamoto
It looks good to move bugs_64.c to cpu/bugs_64.c. Signed-off-by: Hiroshi Shimamoto <h-shimamoto@ct.jp.nec.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2008-06-02fix build bug in "x86: add PCI extended config space access for AMD Barcelona"Ingo Molnar
2008-06-02x86: add PCI extended config space access for AMD BarcelonaRobert Richter
This patch implements PCI extended configuration space access for AMD's Barcelona CPUs. It extends the method using CF8/CFC IO addresses. An x86 capability bit has been introduced that is set for CPUs supporting PCI extended config space accesses. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-05-30x86: fix overlong line in arch/x86/kernel/cpu/amd_64.cH. Peter Anvin
Clean up an overlong line in arch/x86/kernel/cpu/amd_64.c. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2008-05-30x86: Move the 64-bit Centaur specific parts out of setup_64.cDave Jones
Create a separate centaur_64.c file in the cpu/ dir for the useful parts to live in. Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2008-05-30x86: Remove workaround for prescott (32bit P4) from 64-bit code.Dave Jones
Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2008-05-30x86: Move the 64-bit Intel specific parts out of setup_64.cDave Jones
Create a separate intel_64.c file in the cpu/ dir for the useful parts to live in. Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2008-05-30x86: Move the AMD64 specific parts out of setup_64.cDave Jones
Create a separate amd_64.c file in the cpu/ dir for the useful parts to live in. Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2008-05-25x86: mtrr cleanup for converting continuous to discrete layout - fix #2Yinghai Lu
disable the noisy print out. also use the one the less spare mtrr reg. Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-05-25x86: amd opteron TOM2 mask val fixYinghai Lu
there is a typo in the mask value, need to remove that extra 0, to avoid 4bit clearing. Signed-off-by: Yinghal Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-05-25x86: process fam 10h like k8 with fixed mtrr settingYinghai Lu
otherwise fixed MTRR for family 10h may not be changed. Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-05-25x86: mtrr cleanup for converting continuous to discrete - auto detect v4Yinghai Lu
Loop through mtrr chunk_size and gran_size from 1M to 2G to find out the optimal value so user does not need to add mtrr_chunk_size and mtrr_gran_size to the kernel command line. If optimal value is not found, print out all list to help select less optimal value. Add mtrr_spare_reg_nr= so user could set 2 instead of 1, if the card need more entries. v2: find the one with more spare entries v3: fix hole_basek offset v4: tight the compare between range and range_new loop stop with 4g Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Gabriel C <nix.or.die@googlemail.com> Cc: Mika Fischer <mika.fischer@zoopnet.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-05-25x86: mtrr cleanup for converting continuous to discrete layout v8 - fixYinghai Lu
v9: address format change requests by Ingo more case handling in range_to_var_with_hole Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-05-25x86: fix trimming e820 with MTRR holes. - fixYinghai Lu
v2: process hole then end_pfn fix update_memory_range with whole cover comparing Signed-off-by: Yinghai Lu <yinghai.lu@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-05-25x86: fix trimming e820 with MTRR holes.Yinghai Lu
converting MTRR layout from continous to discrete, some time could run out of MTRRs. So add gran_sizek to prevent that by dumpping small RAM piece less than gran_sizek. previous trimming only can handle highest_pfn from mtrr to end_pfn from e820. when have more than 4g RAM installed, there will be holes below 4g. so need to check ram below 4g is coverred well. need to be applied after [PATCH] x86: mtrr cleanup for converting continuous to discrete layout v7 Signed-off-by: Yinghai Lu <yinghai.lu@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-05-25x86: mtrr cleanup for converting continuous to discrete layout, v8Yinghai Lu
some BIOS like to use continus MTRR layout, and X driver can not add WB entries for graphical cards when 4g or more RAM installed. the patch will change MTRR to discrete. mtrr_chunk_size= could be used to have smaller continuous block to hold holes. default is 256m, could be set according to size of graphics card memory. mtrr_gran_size= could be used to send smallest mtrr block to avoid run out of MTRRs v2: fix -1 for UC checking v3: default to disable, and need use enable_mtrr_cleanup to enable this feature skip the var state change warning. remove next_basek in range_to_mtrr() v4: correct warning mask. v5: CONFIG_MTRR_SANITIZER v6: fix 1g, 2g, 512 aligment with extra hole v7: gran_sizek to prevent running out of MTRRs. v8: fix hole_basek caculation caused when removing next_basek gran_sizek using when basek is 0. need to apply [PATCH] x86: fix trimming e820 with MTRR holes. right after this one. Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-05-25x86: fix sparse warning in mtrr/generic.cThomas Gleixner
arch/x86/kernel/cpu/mtrr/generic.c:216:12: warning: symbol 'lo' shadows an earlier one Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-05-25x86: janitor work in bugs.cMiklos Vajna
Just moved trailing statements to the next line, removed space before open/close parenthesis, wrapped long lines. Signed-off-by: Miklos Vajna <vmiklos@frugalware.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-05-22x86: Add Centaur and Transmeta CPUs to PAT whitelistDave Jones
Unconditionally enable PAT support on Centaur and Transmeta CPUs. All known models that advertise PAT have no known errata. Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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