| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2007-08-27 | [XTENSA] Add support for cache-aliasing | Chris Zankel | |
| Add support for processors that have cache-aliasing issues, such as the Stretch S5000 processor. Cache-aliasing means that the size of the cache (for one way) is larger than the page size, thus, a page can end up in several places in cache depending on the virtual to physical translation. The method used here is to map a user page temporarily through the auto-refill way 0 and of of the DTLB. We probably will want to revisit this issue and use a better approach with kmap/kunmap. Signed-off-by: Chris Zankel <chris@zankel.net> | |||
| 2005-06-24 | [PATCH] xtensa: Architecture support for Tensilica Xtensa Part 5 | Chris Zankel | |
| The attached patches provides part 5 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org> | |||
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