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path: root/arch/xtensa/mm/cache.c
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2008-02-13[XTENSA] Flush the page-address in update-mmu instead of user-addressChris Zankel
The TLB entry for the user address doesn't exist at the time we want to flush the caches, so use the page address. Note that processor configurations with cache-aliasing issues are treated separately. Signed-off-by: Chris Zankel <chris@zankel.net>
2008-02-13[XTENSA] Remove duplicate includes.Chris Zankel
Signed-off-by: Lucas Woods <woodzy@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Christian Zankel <chris@zankel.net>
2007-08-27[XTENSA] Add support for cache-aliasingChris Zankel
Add support for processors that have cache-aliasing issues, such as the Stretch S5000 processor. Cache-aliasing means that the size of the cache (for one way) is larger than the page size, thus, a page can end up in several places in cache depending on the virtual to physical translation. The method used here is to map a user page temporarily through the auto-refill way 0 and of of the DTLB. We probably will want to revisit this issue and use a better approach with kmap/kunmap. Signed-off-by: Chris Zankel <chris@zankel.net>