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2006-03-20[SPARC64]: Fix uniprocessor IRQ targetting on SUN4V.David S. Miller
We need to use the real hardware processor ID when targetting interrupts, not the "define to 0" thing the uniprocessor build gives us. Also, fill in the Node-ID and Agent-ID fields properly on sun4u/Safari. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix PCI IRQ probing regression.David S. Miller
If the top-level cnode had multi entries in it's "reg" property, we'd fail. The buffer wasn't large enough in such cases. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Get SUN4V SMP working.David S. Miller
The sibling cpu bringup is extremely fragile. We can only perform the most basic calls until we take over the trap table from the firmware/hypervisor on the new cpu. This means no accesses to %g4, %g5, %g6 since those can't be TLB translated without our trap handlers. In order to achieve this: 1) Change sun4v_init_mondo_queues() so that it can operate in several modes. It can allocate the queues, or install them in the current processor, or both. The boot cpu does both in it's call early on. Later, the boot cpu allocates the sibling cpu queue, starts the sibling cpu, then the sibling cpu loads them in. 2) init_cur_cpu_trap() is changed to take the current_thread_info() as an argument instead of reading %g6 directly on the current cpu. 3) Create a trampoline stack for the sibling cpus. We do our basic kernel calls using this stack, which is locked into the kernel image, then go to our proper thread stack after taking over the trap table. 4) While we are in this delicate startup state, we put 0xdeadbeef into %g4/%g5/%g6 in order to catch accidental accesses. 5) On the final prom_set_trap_table*() call, we put &init_thread_union into %g6. This is a hack to make prom_world(0) work. All that wants to do is restore the %asi register using get_thread_current_ds(). Longer term we should just do the OBP calls to set the trap table by hand just like we do for everything else. This would avoid that silly prom_world(0) issue, then we can remove the init_thread_union hack. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Disable smp_report_regs() for now.David S. Miller
For 32 cpus and a slow console, it just wedges the machine especially with DETECT_SOFTLOCKUP enabled. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Rewrite pci_intmap_match().David S. Miller
The whole algorithm was wrong. What we need to do is: 1) Walk each PCI bus above this device on the path to the PCI controller nexus, and for each: a) If interrupt-map exists, apply it, record IRQ controller node b) Else, swivel interrupt number using PCI_SLOT(), use PCI bus parent OBP node as controller node c) Walk up to "controller node" until we hit the first PCI bus in this domain, or "controller node" is the PCI controller OBP node 2) If we walked to PCI controller OBP node, we're done. 3) Else, apply PCI controller interrupt-map to interrupt. There is some stuff that needs to be checked out for ebus and isa, but the PCI part is good to go. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Don't set interrupt state to IDLE in enable_irq().David S. Miller
We'll lose events that way. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix return from trap on SUN4V.David S. Miller
We need to set the global register set _AND_ disable PSTATE_IE in %pstate. The original patch sequence was leaving PSTATE_IE enabled when returning to kernel mode, oops. This fixes the random register corruption being seen on SUN4V. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Set dummy bucket->{imap,iclr} unique on SUN4V.David S. Miller
So that free_irq() disable's the IRQ correctly. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Add sun4v_cpu_qconf() hypervisor call.David S. Miller
Call it from register_one_mondo(). Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: do_fptrap needs to load the thread reg into %g6.David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix bogus call to sun4v_mna in winfixup code.David S. Miller
The C function is named sun4v_do_mna not sun4v_mna. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix tl1 trap state capture/dump on SUN4V.David S. Miller
No trap levels above 2 in privileged mode on SUN4V. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64] PCI: Size TSB correctly on SUN4V.David S. Miller
Forgot to multiply by 8 * 1024, oops. Correct the size constant when the virtual-dma arena is 2GB in size, it should bet 256 not 128. Finally, log some info about the TSB at probe time. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Don't use ASI_QUAD_LDD_PHYS on SUN4V.David S. Miller
Need to use ASI_QUAD_LDD_PHYS_4V instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Do not write garbage into %pstate in tsb_context_switch().David S. Miller
For SUN4V, we were clobbering %o5 to do the hypervisor call. This clobbers the saved %pstate value and we end up writing garbage into that register as a result. Oops. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix flush_tsb_user() on SUN4V.David S. Miller
Needs to use physical addressing just like cheetah_plus. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix comment typo in __flush_tlb_kernel_range.David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Decode virtual-devices interrupts correctly.David S. Miller
Need to translate through the interrupt-map{,-mask] properties. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Add prom_{start,stop}cpu_cpuid().David S. Miller
Use prom_startcpu_cpuid() on SUN4V instead of prom_startcpu(). We should really test for "SUNW,start-cpu-by-cpuid" presence and use it if present even on SUN4U. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix pci_intmap_match().David S. Miller
When crawling up the PCI bus chain, stop at the first node that has an interrupt-map property before we hit the root. Also, if we use a bus interrupt-{map,mask} do not forget to update the 'intmask' pointer as we do for the 'intmap' pointer. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Two IRQ handling fixes.David S. Miller
On SUN4V, force IRQ state to idle in enable_irq(). However, I'm still not sure this is %100 correct. Call add_interrupt_randomness() on SUN4V too. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Use different cache sizing defaults on SUN4V.David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Make lack of interrupt-map-* a fatal error on SUN4V.David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix sun4v_intr_setenabled() return value check in enable_irq().David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Explicitly init *nregs to 0 in find_device_prom_node().David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Restrict PCI bus scanning on SUN4V.David S. Miller
On the PBM's first bus number, only allow device 0, function 0, to be poked at with PCI config space accesses. For some reason, this single device responds to all device numbers. Also, reduce the verbiage of the debugging log printk's for PCI cfg space accesses in the SUN4V PCI controller driver, so that it doesn't overwhelm the slow SUN4V hypervisor console. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix C-function name called by sun4v_mna trap code.David S. Miller
The trap code was calling itself :-) Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Don't printk() any messaages in sun4v_build_irq().David S. Miller
It just clutters up the log. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: INO is never fully specified already on SUN4V.David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Kill sun4v_register_fault_status() on SMP.David S. Miller
That now gets done as a side effect of taking over the trap table from OBP. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: arch/sparc64/kernel/trampoline.S needs asm/cpudata.hDavid S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Make error codes available from sun4v_intr_get*().David S. Miller
And check for errors at call sites. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Pass correct ino to sun4v_intr_*().David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Use TRAP_LOAD_IRQ_WORK() in sun4v device mondo handler.David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Fix IOMMU mapping on sun4v.David S. Miller
We should dynamically allocate the per-cpu pglist not use an in-kernel-image datum, since __pa() does not work on such addresses. Also, consistently use "u32" for devhandle. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Trim down sun4v IRQ translation kernel log message.David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64] sunhv: Bug fixes.David S. Miller
Add udelay to polling console write loop, and increment the loop limit. Name the device "ttyHV" and pass that to add_preferred_console() when we're using hypervisor console. Kill sunhv_console_setup(), it's empty. Handle the case where we don't want to use hypervisor console. (ie. we have a head attached to a sun4v machine) Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Probe virtual-devices root node on sun4v.David S. Miller
This is where we learn how to get the interrupts for things like the hypervisor console device. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Kill spurious semicolon in sun4v_pci_init().David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Program IRQ registers correctly on sun4v.David S. Miller
Need to use hypervisor calls instead of direct register accesses. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Generic sun4v_build_irq().David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: More SUN4V PCI work.David S. Miller
Get bus range from child of PCI controller root nexus. This is actually a hack, but the PCI-E bridge sitting at the top of the PCI tree responds to PCI config cycles for every device number, so best to just ignore it for now. Preliminary PCI irq routing, needs lots of work. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Log faulting vaddr when bogus kernel PC detected.David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Implement rest of generic interrupt hypervisor calls.David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Move devino_to_sysino out of pci_sun4v_asm.SDavid S. Miller
It is not PCI specific, it is for all system interrupts. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Range check bus number in SUN4V PCI controller driver.David S. Miller
It has to be somewhere in the range from pbm->pci_first_busno to pbm->pci_last_busno, inclusive. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Missing 'return' statement in sun4v_pci_init().David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Implement basic pci_sun4v_scan_bus().David S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: PCI-SUN4V fixes.David S. Miller
Clear top 8-bits of physical addresses in "ranges" property. This gives the actual physical address. Detect PBM-A vs. PBM-B by checking bit 0x40 of the devhandle. Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20[SPARC64]: Use inline patching for critical PTE operations.David S. Miller
This handles the SUN4U vs SUN4V PTE layout differences with near zero performance cost. Signed-off-by: David S. Miller <davem@davemloft.net>