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2010-05-18Merge branch 'gta02-machine-2.6.34' into om-gta02-2.6.34Lars-Peter Clausen
2010-05-18gta02_drm_defconfigMartin Jansa
config used in SHR-U, KMS enabled
2010-05-18gta02_defconfigRadek Polak
config used for qtmoko-v20. It has all freerunner hardware built in - so that you can boot and your phone hardware is working even without /lib/modules. I have (hopefully) all drivers from 2.6.29 as modules (usb keyboards etc).
2010-05-18gta02: add support for platform_batteryPaul Fertser
This adds support for platform_battery driver which allows to specify a set of power supply properties and callbacks to acquire them. It is needed to support dumb batteries where all the information about their status can only be obtained by platform-specific actions such as specific ADC measurements, some guessimation etc. Signed-off-by: Paul Fertser <fercerpav@gmail.com>
2010-05-18gta02: Add battery driverLars-Peter Clausen
2010-05-18gta02: Add fiq handlerLars-Peter Clausen
2010-05-17gta02: Add touchscreen deviceLars-Peter Clausen
2010-05-17gta02: Remove usage of pcf50633 gpio apiLars-Peter Clausen
This is the only user of the pcf50633 gpio api. Since the custom interface is going to be replaced with gpiolib all users need to be remove or replaced. It is safe to be remove it in this case since it is used used to turn a gpio off which is never going to be turned on. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2010-05-17gta02: Add pcf50633 backlight platform dataLars-Peter Clausen
2010-05-17Add jbt device.Lars-Peter Clausen
2010-05-17gta02: Add glamo deviceLars-Peter Clausen
2010-05-17gta02: Add wlan power management deviceLars-Peter Clausen
2010-05-17gta02: Add gsm power management deviceLars-Peter Clausen
2010-05-17gta02: Add gps power management deviceLars-Peter Clausen
2010-05-17gta02: Add bt power management deviceLars-Peter Clausen
2010-05-17gta02: Add notify handler to probe device childrenLars-Peter Clausen
On the gta02 we often have a child parent relationship between different devices. The child devices can only be probed after their parant has been. Instead of adding a probe completed handler to each device we handle this in a generic way with a bus notifier.
2010-05-17gta02: Configure pcf50633 gpios.Lars-Peter Clausen
2010-05-17gta02: Disable hardware ECC unless we get instructed to enable itHolger Freyther
Early verions off uboot used for the gta02 flashed the nand with ecc information incompatible to s3c2440 hardware ecc. Disable hardware error correction by default, unless the bootloader explicitly enables it. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2010-05-17gta02: Include mach/regs-gpioj.hLars-Peter Clausen
2010-05-17gta02: request usb pullup pin before using it.Lars-Peter Clausen
2010-05-17gta02: Fix regulator valid_modes_opsLars-Peter Clausen
2010-05-17gta02: Select missing device symbols.Lars-Peter Clausen
Select usb host and nand device.
2010-05-17ARM: gta02: Add gpio bank B quirk for hardware revision 5 and earlierLars-Peter Clausen
On hardware revision 5 and earlier the leds found on the gta02 are missing a resistor and reading their gpio pin status will always return 0. So we have to shadow the led states in software. This is done by "hijacking" the gpio accessor functions for bank B. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2010-05-17ARM: gta02: Add LED supportLars-Peter Clausen
The gta02 has three leds which are connected though gpio pins and thus can get supported by using the generic leds-gpio driver. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2010-05-17ARM: gta02: Add button supportLars-Peter Clausen
The gta02 has two buttons which are connected to gpio pins and thus can get supported by using the generic gpio-keys driver. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2010-05-17mtd: s3c2410_nand: Add config option to disable hw ecc at runtimeHolger Freyther
This patch adds a flag to the s3c2410_nand platform data, which configures whether hardware ecc is used for that chip. Currently hardware ecc is used if it was compiled into the kernel. But if you want to build a kernel which runs on multiple devices you might have a configuration where you have devices which require hw ecc as well as devices which want software ecc. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2010-05-17s3c24xx: Fix level irqs on external interrupts.Lars-Peter Clausen
Although the external interrupts support level and edge triggered irqs their handler is currently always set to handle_edge_irq(). While being technically wrong for a level triggered irq to be handled by handle_edge_irq() it will cause serious problems in combination with a oneshot irq. handle_edge_irq() will unmask the irq immediately and as a result the irq will be triggered again before the threaded irq handler had a chance to run and clear the irq source. Thus level triggered irqs should be handled by handle_level_irq. According to the specs the irq controller will remember if an irq has been triggered while it had been masked and will issue it when the irq gets unmasked. Thus it is sufficient to use handle_level_irq() for edge triggered irqs as well. Hence handle_level_irq() can always be used for external interrupts. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2010-05-17S3C: Allow to completly disable low-level messagesLars-Peter Clausen
In some cases it is desirable to completly disable low-level messages. For example if you have no uart available for a serial console. With this patch it is possible to disable low-level messages by setting CONFIG_S3C_LOWLEVEL_UART_PORT to less then zero. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2010-05-17s3c: Register gpio bank J with gpiolibLars-Peter Clausen
This is nonportable and wastes a lot of memory and thus should be replaced with a prober solution asap.
2010-05-17s3c24xx: Add number of board irqs for the gta02Lars-Peter Clausen
The gta02 uses the glamo mfd driver which requires 9 board irqs and the pcf50633 mfd driver which requires 40 irqs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2010-05-17s3c24xx: Add support for board IRQsLars-Peter Clausen
Some boards have a need for a set of extra IRQ numbers, for example some multifunction devices which do irq demultiplexing require them. This patch adds S3C2410_BOARD_NR_IRQS which specifies the number of extra board IRQs. Board specific code would use S3C2410_BOARD_IRQ_START to get the number of it's first irq. Since it is possible to support a multiple boards with a single kernel and there is no easy way to set a CONFIG option to multiple values and only use the maximum each board which needs board IRQs has do be explicitly added to irqs.h Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2010-05-17Add c fiq handler.Lars-Peter Clausen
2010-05-15 MIPS: Oprofile: Fix Loongson irq handlerWu Zhangjin
The interrupt enable bit for the performance counters is in the Control Register $24, not in the counter register. loongson2_perfcount_handler(), we need to use Reported-by: Xu Hengyang <hengyang@mail.ustc.edu.cn> Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1198/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2010-05-15 MIPS: N32: Use compat version for sys_ppoll.Chandrakala Chavva
The sys_ppoll() takes struct 'struct timespec'. This is different for the N32 and N64 ABIs. Use the compat version to do the proper conversions. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1210/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2010-05-15 MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1Shane McDonald
In the FPU emulator code of the MIPS, the Cause bits of the FCSR register are not currently writeable by the ctc1 instruction. In odd corner cases, this can cause problems. For example, a case existed where a divide-by-zero exception was generated by the FPU, and the signal handler attempted to restore the FPU registers to their state before the exception occurred. In this particular setup, writing the old value to the FCSR register would cause another divide-by-zero exception to occur immediately. The solution is to change the ctc1 instruction emulator code to allow the Cause bits of the FCSR register to be writeable. This is the behaviour of the hardware that the code is emulating. This problem was found by Shane McDonald, but the credit for the fix goes to Kevin Kissell. In Kevin's words: I submit that the bug is indeed in that ctc_op: case of the emulator. The Cause bits (17:12) are supposed to be writable by that instruction, but the CTC1 emulation won't let them be updated by the instruction. I think that actually if you just completely removed lines 387-388 [...] things would work a good deal better. At least, it would be a more accurate emulation of the architecturally defined FPU. If I wanted to be really, really pedantic (which I sometimes do), I'd also protect the reserved bits that aren't necessarily writable. Signed-off-by: Shane McDonald <mcdonald.shane@gmail.com> To: anemo@mba.ocn.ne.jp To: kevink@paralogos.com To: sshtylyov@mvista.com Patchwork: http://patchwork.linux-mips.org/patch/1205/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2010-05-14Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds
* master.kernel.org:/home/rmk/linux-2.6-arm: ARM: 6126/1: ARM mpcore_wdt: fix build failure and other fixes ARM: 6125/1: ARM TWD: move TWD registers to common header ARM: 6110/1: Fix Thumb-2 kernel builds when UACCESS_WITH_MEMCPY is enabled ARM: 6112/1: Use the Inner Shareable I-cache and BTB ops on ARMv7 SMP ARM: 6111/1: Implement read/write for ownership in the ARMv6 DMA cache ops ARM: 6106/1: Implement copy_to_user_page() for noMMU ARM: 6105/1: Fix the __arm_ioremap_caller() definition in nommu.c
2010-05-14Merge branch 'x86-fixes-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, mrst: Don't blindly access extended config space
2010-05-14x86, mrst: Don't blindly access extended config spaceH. Peter Anvin
Do not blindly access extended configuration space unless we actively know we're on a Moorestown platform. The fixed-size BAR capability lives in the extended configuration space, and thus is not applicable if the configuration space isn't appropriately sized. This fixes booting certain VMware configurations with CONFIG_MRST=y. Moorestown will add a fake PCI-X 266 capability to advertise the presence of extended configuration space. Reported-and-tested-by: Petr Vandrovec <petr@vandrovec.name> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Acked-by: Jacob Pan <jacob.jun.pan@intel.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> LKML-Reference: <AANLkTiltKUa3TrKR1M51eGw8FLNoQJSLT0k0_K5X3-OJ@mail.gmail.com>
2010-05-14Merge branch 'x86-fixes-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, cacheinfo: Turn off L3 cache index disable feature in virtualized environments x86, k8: Fix build error when K8_NB is disabled x86, amd: Check X86_FEATURE_OSVW bit before accessing OSVW MSRs x86: Fix fake apicid to node mapping for numa emulation
2010-05-14x86, cacheinfo: Turn off L3 cache index disable feature in virtualized ↵Frank Arnold
environments When running a quest kernel on xen we get: BUG: unable to handle kernel NULL pointer dereference at 0000000000000038 IP: [<ffffffff8142f2fb>] cpuid4_cache_lookup_regs+0x2ca/0x3df PGD 0 Oops: 0000 [#1] SMP last sysfs file: CPU 0 Modules linked in: Pid: 0, comm: swapper Tainted: G W 2.6.34-rc3 #1 /HVM domU RIP: 0010:[<ffffffff8142f2fb>] [<ffffffff8142f2fb>] cpuid4_cache_lookup_regs+0x 2ca/0x3df RSP: 0018:ffff880002203e08 EFLAGS: 00010046 RAX: 0000000000000000 RBX: 0000000000000003 RCX: 0000000000000060 RDX: 0000000000000000 RSI: 0000000000000040 RDI: 0000000000000000 RBP: ffff880002203ed8 R08: 00000000000017c0 R09: ffff880002203e38 R10: ffff8800023d5d40 R11: ffffffff81a01e28 R12: ffff880187e6f5c0 R13: ffff880002203e34 R14: ffff880002203e58 R15: ffff880002203e68 FS: 0000000000000000(0000) GS:ffff880002200000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 000000008005003b CR2: 0000000000000038 CR3: 0000000001a3c000 CR4: 00000000000006f0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400 Process swapper (pid: 0, threadinfo ffffffff81a00000, task ffffffff81a44020) Stack: ffffffff810d7ecb ffff880002203e20 ffffffff81059140 ffff880002203e30 <0> ffffffff810d7ec9 0000000002203e40 000000000050d140 ffff880002203e70 <0> 0000000002008140 0000000000000086 ffff880040020140 ffffffff81068b8b Call Trace: <IRQ> [<ffffffff810d7ecb>] ? sync_supers_timer_fn+0x0/0x1c [<ffffffff81059140>] ? mod_timer+0x23/0x25 [<ffffffff810d7ec9>] ? arm_supers_timer+0x34/0x36 [<ffffffff81068b8b>] ? hrtimer_get_next_event+0xa7/0xc3 [<ffffffff81058e85>] ? get_next_timer_interrupt+0x19a/0x20d [<ffffffff8142fa23>] get_cpu_leaves+0x5c/0x232 [<ffffffff8106a7b1>] ? sched_clock_local+0x1c/0x82 [<ffffffff8106a9a0>] ? sched_clock_tick+0x75/0x7a [<ffffffff8107748c>] generic_smp_call_function_single_interrupt+0xae/0xd0 [<ffffffff8101f6ef>] smp_call_function_single_interrupt+0x18/0x27 [<ffffffff8100a773>] call_function_single_interrupt+0x13/0x20 <EOI> [<ffffffff8143c468>] ? notifier_call_chain+0x14/0x63 [<ffffffff810295c6>] ? native_safe_halt+0xc/0xd [<ffffffff810114eb>] ? default_idle+0x36/0x53 [<ffffffff81008c22>] cpu_idle+0xaa/0xe4 [<ffffffff81423a9a>] rest_init+0x7e/0x80 [<ffffffff81b10dd2>] start_kernel+0x40e/0x419 [<ffffffff81b102c8>] x86_64_start_reservations+0xb3/0xb7 [<ffffffff81b103c4>] x86_64_start_kernel+0xf8/0x107 Code: 14 d5 40 ff ae 81 8b 14 02 31 c0 3b 15 47 1c 8b 00 7d 0e 48 8b 05 36 1c 8b 00 48 63 d2 48 8b 04 d0 c7 85 5c ff ff ff 00 00 00 00 <8b> 70 38 48 8d 8d 5c ff ff ff 48 8b 78 10 ba c4 01 00 00 e8 eb RIP [<ffffffff8142f2fb>] cpuid4_cache_lookup_regs+0x2ca/0x3df RSP <ffff880002203e08> CR2: 0000000000000038 ---[ end trace a7919e7f17c0a726 ]--- The L3 cache index disable feature of AMD CPUs has to be disabled if the kernel is running as guest on top of a hypervisor because northbridge devices are not available to the guest. Currently, this fixes a boot crash on top of Xen. In the future this will become an issue on KVM as well. Check if northbridge devices are present and do not enable the feature if there are none. [ hpa: backported to 2.6.34 ] Signed-off-by: Frank Arnold <frank.arnold@amd.com> LKML-Reference: <1271945222-5283-3-git-send-email-bp@amd64.org> Acked-by: Borislav Petkov <borislav.petkov@amd.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com> Cc: <stable@kernel.org>
2010-05-14x86, k8: Fix build error when K8_NB is disabledBorislav Petkov
K8_NB depends on PCI and when the last is disabled (allnoconfig) we fail at the final linking stage due to missing exported num_k8_northbridges. Add a header stub for that. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> LKML-Reference: <20100503183036.GJ26107@aftab> Signed-off-by: H. Peter Anvin <hpa@zytor.com> Cc: <stable@kernel.org>
2010-05-14Merge branch 'davinci-fixes-for-linus-2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci * 'davinci-fixes-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci: DA830: fix USB 2.0 clock entry
2010-05-14DA830: fix USB 2.0 clock entrySergei Shtylyov
DA8xx OHCI driver fails to load due to failing clk_get() call for the USB 2.0 clock. Arrange matching USB 2.0 clock by the clock name instead of the device. (Adding another CLK() entry for "ohci.0" device won't do -- in the future I'll also have to enable USB 2.0 clock to configure CPPI 4.1 module, in which case I won't have any device at all.) Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2010-05-14Merge branch 'for-linus' of git://git.monstr.eu/linux-2.6-microblazeLinus Torvalds
* 'for-linus' of git://git.monstr.eu/linux-2.6-microblaze: microblaze: Fix module loading on system with WB cache microblaze: export assembly functions used by modules microblaze: Remove powerpc code from Microblaze port microblaze: Remove compilation warnings in cache macro microblaze: export assembly functions used by modules microblaze: fix get_user/put_user side-effects microblaze: re-enable interrupts before calling schedule
2010-05-14microblaze: Fix module loading on system with WB cacheMichal Simek
There is necessary to flush whole dcache. Icache work should be done in kernel/module.c. Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-05-13x86, amd: Check X86_FEATURE_OSVW bit before accessing OSVW MSRsAndreas Herrmann
If host CPU is exposed to a guest the OSVW MSRs are not guaranteed to be present and a GP fault occurs. Thus checking the feature flag is essential. Cc: <stable@kernel.org> # .32.x .33.x Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> LKML-Reference: <20100427101348.GC4489@alberich.amd.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2010-05-13microblaze: export assembly functions used by modulesMichal Simek
Export __strncpy_user, memory_size, ioremap_bot for modules. Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-05-13microblaze: Remove powerpc code from Microblaze portMichal Simek
Remove eeh_add_device_tree_late which is powerpc specific code. Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-05-13microblaze: Remove compilation warnings in cache macroMichal Simek
CC arch/microblaze/kernel/cpu/cache.o arch/microblaze/kernel/cpu/cache.c: In function '__invalidate_dcache_range_wb': arch/microblaze/kernel/cpu/cache.c:398: warning: ISO C90 forbids mixed declarations and code arch/microblaze/kernel/cpu/cache.c: In function '__flush_dcache_range_wb': arch/microblaze/kernel/cpu/cache.c:509: warning: ISO C90 forbids mixed declara Signed-off-by: Michal Simek <monstr@monstr.eu>
2010-05-13microblaze: export assembly functions used by modulesSteven J. Magnani
Modules that use copy_{to,from}_user(), memcpy(), and memset() fail to build in certain circumstances. Signed-off-by: Steven J. Magnani <steve@digidescorp.com> Signed-off-by: Michal Simek <monstr@monstr.eu>