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parameters
Use a consistent crystal value of 28.636360 MHz for computing all PLL
parameters so clocks don't have relative error due to assumed crystal
value mismatches. Also aimed to have all PLLs run their VOCs at close to
400 MHz to minimze the error of these PLLs as frequency synthesizers. Also
set the VDCLK and AIMCLK PLLs to sane values before the APU and CPU firmware
are loaded. Also fixed I2S Master clock dividers.
Many thanks to Mike Bradley and Jeff Campbell for reporting this problem and
suggesting the solution, researching and experimenting, and performing
extensive testing to support their suggested solution.
Reported-by: Jeff Campbell <jac1dlists@gmail.com>
Reported-by: Mike Bradley <mike.bradley@incanetworks.com>
Signed-off-by: Andy Walls <awalls@radix.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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Disable AV_LOCK, locking of audio PLL to video PLL in the cx18-av-core for
analog captures. It seems to have adverse effects on captures from
SVideo and CVBS sources with current clock & crystal settings in the driver.
Many thanks to Jeff Campbell and Mike Bradley for reporting this problem,
and suggesting the solution and performing extensive testing to support their
suggestion.
Reported-by: Jeff Campbell <jac1dlists@gmail.com>
Reported-by: Mike Bradley <mike.bradley@incanetworks.com>
Signed-off-by: Andy Walls <awalls@radix.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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Add copyright attribution for files modified by awalls in 2008
Signed-off-by: Andy Walls <awalls@radix.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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part 3.
cx18: Fix write retries for registers that always change - part 3.
Fix the io for the rest of the registers that will often not read back the
value just written. Modified register readback checks to make sure the
intended effect was achieved without constantly rewriting the registers.
The one outstanding register remaining is 0xc72014 CX18_AUDIO_ENABLE, whose
behavior on writes I have yet to determine.
Signed-off-by: Andy Walls <awalls@radix.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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captures
cx18: Lock the aux PLL to the video pixel rate for analog captures. The
datasheet for the CX25840 says this is important for MPEG encoding applications.
To ensure the PLL locking was correct, also fixed the aux PLL's multiplier to
be computed based on a precise crystal freq of 4.5 MHz/286 * 455/2 * 8 =
28636363.6363... instead of the imporperly rounded 28636363.
Signed-off-by: Andy Walls <awalls@radix.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
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SIF input
cx18: Fix 32 kHz audio sample output rate for analog tuner SIF input so it
works. The AUX_PLL VCO was being operated at 196.6 MHz out of the spec'ed
200-600 MHz range. Fixed the multipler and post dividers to operate the VCO
within specification and added comments on how magic numbers are derived.
Thanks to Hans Verkuil for pointing out this interesting problem to solve.
Signed-off-by: Andy Walls <awalls@radix.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
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Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
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Many thanks to Steve Toth from Hauppauge and Nattu Dakshinamurthy from
Conexant for their support. I am in particular thankful to Hauppauge
since without their help this driver would not exist. It should also
be noted that Steve did the work to get the DVB part up and running.
Thank you!
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
Signed-off-by: Steven Toth <stoth@hauppauge.com>
Signed-off-by: Michael Krufky <mkrufky@linuxtv.org>
Signed-off-by: G. Andrew Walls <awalls@radix.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
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