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The platform structure was lacking an oobinfo field.
The NDFC driver had some remains from another tree.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Signed-off-by: David Woodhouse <dwmw2@infradead.org>
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We have a type pointer. Make use of it instead of the error prone nand_ids[i]
reference.
The NAND driver used to set default name settings from the chip ID
string for the device. The feature got lost during the rework. Add it back.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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nCE setting can be done when the first command is issued to the device.
We keep the deselect functionality as it makes sense to deassert nCE
when the device becomes idle.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
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Modularize the write function and reorganaize the internal buffer
management. Remove obsolete chip options and fixup all affected
users.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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PCI is faked on these devices by SMM traps. Don't depend on that --
check for the chipset directly instead.
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
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Bad tglx. No biscuit.
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
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Split the core of the read function out and implement
seperate handling functions for software and hardware
ECC.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Cleanup the code in the oob related functions and
make use of the new NO_READRDY flag.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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The nand driver has a superflous read ready / command
delay in the read functions. This was added to handle
chips which have an automatic read forward. Newer
chips do not have this functionality anymore. Add this
option to avoid the delay / I/O operation. Mark all
large page chips with the new option flag.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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The lock simplifying patch did not move the lock and waitqueue
initialization into the controller allocation patch.
This reinitializes waitqueue and spinlocks also for driver
supplied controller stuctures. Move it into the allocation path.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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The cmd_ctrl rework lacks some state transition flags.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Cleanup the functions which are not going to change in the
next steps.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Move the define out of the middle of the code and add an
appropriate comment.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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The previous change of the command / hardware control allows to
remove the write_byte/word functions completely, as their only
user were nand_command and nand_command_lp.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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The hwcontrol function enforced a step by step state machine
for any kind of hardware chip access. Let the hardware driver
know which control bits are set and inform it about a change
of the control lines. Let the hardware driver write out the
command and address bytes directly. This gives a peformance
advantage for address bus controlled chips and simplifies the
quirks in the hardware drivers.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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The previous _ecc removal / cleanup broke (i)nftl module usage.
Export the missing symbol.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Both drivers can not be fixed and compiled due to missing header files.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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MTD clients are agnostic of FLASH which needs ECC suppport.
Remove the functions and fixup the callers.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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These functions were never implemented and added only bloat to
partition and concat code.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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NAND writev(_ecc) support is not longer necessary. Remove it.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Fix the diskonchip ecc setup.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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First step of modularizing ECC support.
- Move ECC related functionality into a seperate embedded data structure
- Get rid of the hardware dependend constants to simplify new ECC models
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Seperate functionality out of nand_scan so the code is more
readable. No functional change. First step of simplifying
the nand driver.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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The NAND driver used a mix of unsigned char, u_char amd uint8_t
data types. Consolidate to uint8_t usage
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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NDFC NAND Flash controller is embedded in PPC EP44x SoCs.
Add platform driver based support.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Replace the chip lock by a the controller lock. For simple drivers a
dummy controller structure is created by the scan code.
This simplifies the locking algorithm in nand_get/release_chip().
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Unrolling the loops produces denser and much faster code.
Add a config switch which allows to select the byte order of the
resulting ecc code. The current Linux implementation has a byte
swap versus the SmartMedia specification
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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o Add a flag MTD_BIT_WRITEABLE for devices that allow single bits to be
cleared.
o Replace MTD_PROGRAM_REGIONS with a cleared MTD_BIT_WRITEABLE flag for
STMicro and Intel Sibley flashes with internal ECC. Those flashes
disallow clearing of single bits, unlike regular NOR flashes, so the
new flag models their behaviour better.
o Remove MTD_ECC. After the STMicro/Sibley merge, this flag is only set
and never checked.
Signed-off-by: Joern Engel <joern@wh.fh-wedel.de>
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At least two flashes exists that have the concept of a minimum write unit,
similar to NAND pages, but no other NAND characteristics. Therefore, rename
the minimum write unit to "writesize" for all flashes, including NAND.
Signed-off-by: Joern Engel <joern@wh.fh-wedel.de>
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The patch below adds support for the NAND device on the Amstrad Delta.
This is a 32MiB 8bit Toshiba device, with the data bus connected to the
OMAP MPUIO pins and ALE, CLE, NCE, NRE, NWE and NWP all connected to the
Delta's latch2 16bit latch.
Signed-Off-By: Jonathan McDowell <noodles@earth.li>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
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On AMD Au1550 the static bus controller fails to keep -CE asserted during
chip ready delay on read commands and the NAND chip being used requires this.
So, the current driver allows nand_base.c to drive -CE manually during the
entire sector read. When the PCMCIA driver is enabled however, occasionally
the ECC errors occur on NAND reads. This happens because the PCMCIA driver
polls sockets periodically and reads one of the board's control/status regs
(BCSRs) which are on the same static bus as the NAND flash, and just use
another chip select (and the NOR flash also resides on that bus), so as the
NAND driver forces NAND chip select asserted and the -RE signal is shared, a
contention occurs on the static bus when BCSR or NOR flash is read while we're
reading from NAND.
So, we either can't keep interrupts enabled during the whole NAND sector
read (which is hardly acceptable), or have to implement some interlocking
scheme between multiple drivers (which is painful, and makes me shudder :-).
There's a third way which has proven to work: to force -CE asserted only
while we're waiting for a NAND chip to become ready after a read command,
disabling interrupts for a maximum of 25 microseconds (according to Toshiba
TC58DVM92A1FT00 datasheet -- this chip is mentioned in the board schematics);
for Samsung NAND chip which seems to be actually used this delay is even less,
12 us.
Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
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During the last cleanup of the AMD Au1550 NAND driver the old buglet was
reintroduced: as the MEM_STNDCTL register is write-only and seem to always
read as 0x31, read-modify-write to it done in au1xxx_nand_init() will have the
side effect of enabling -RCS0/1 pin override (via bits 4/5 of this reg.), thus
possibly causing a contention on the static bus when the NOR flash (using
-RCS0) or board control status registers (using -RCS2) are read. Luckily, this
goes away with a first NAND access, since au1550_hwcontrol() doesn't try to
read this register before writing anymore.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
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We all inherited the same error from the original NAND board driver which
got copied and changed. Fix them all at once...
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
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Signed-off-by: David Woodhouse <dwmw2@infradead.org>
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Make it work even with compilers which lack the wit to notice that
THIS_MODULE is always non-NULL. Use #ifdef MODULE instead. It's only
a temporary debugging check anyway.
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
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Signed-off-by: David Woodhouse <dwmw2@infradead.org>
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The _board_ driver needs to be mtd->owner, and it in turn pins the
nand.ko module. Fix them all to actually do that, and fix nand.ko not to
overwrite it -- and also to check that the caller sets it, if the caller
is a module.
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
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It was just too painful to deal with.
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
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We were scanning for 0xFF through the entire chip -- which takes a while
when it's a 512MiB device as I have on my current toy. The specs only say
we need to check certain bytes -- so do only that.
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
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- Implement HW ECC support,
- Provide read_buf() and write_buf() routines using memcpy
- Use on-flash bad block table
- Fix module refcounting
- Avoid read/modify/write in hwcontrol()
- Minor cosmetic fixes
Partly based on code and ideas from Tom Sylla <tom.sylla@amd.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
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These new chips have 128KiB blocks. Don't try to kmalloc that.
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
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Signed-off-by: Egry Gábor <gaboregry@t-online.hu>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
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This lacks hardware ECC support and a few optimisations we're going to
want fairly soon, but it works well enough to mount and use JFFS2.
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
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The TS-72xx is a series of embedded single board computers from
Technologic Systems based on the Cirrus ep93xx (arm920t based) CPU.
The TS-7200 uses NOR flash, while all the other models in the series
(TS-7250, TS-7260) use NAND flash -- included is a driver for the NAND
flash on those boards.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
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Correct the MTD NAND partition size for Poodle (Sharp Zaurus SL-5600)
Signed-off-by: Richard Purdie <rpurdie@rpsys.net>
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Cc: Russell King <rmk@arm.linux.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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