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path: root/include/asm-arm/arch-ixp23xx/memory.h
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2006-12-18[ARM] 4057/1: ixp23xx: unconditionally enable hardware coherencyLennert Buytenhek
On ixp23xx, it was thought to be necessary to disable coherency to work around certain silicon errata. This turns out not to be the case -- none of the documented errata workarounds require disabling coherency, and disabling coherency does not work around any existing errata. Furthermore, all ixp23xx models do support coherency, so we should just unconditionally enable coherency for all ixp23xx. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-02[ARM] 3539/1: ixp23xx: fix __arch_ixp23xx_is_coherent() for A1 steppingLennert Buytenhek
Patch from Lennert Buytenhek The current __ixp23xx_arch_is_coherent() check assumes that the lower byte of IXP23XX_PRODUCT_ID is identical to the lower byte of processor_id, but this is not the case, and because of this we were incorrectly enabling coherency on A1 stepping CPUs. Stepping A1 of the ixp2350, which has a PRODUCT_ID of 0x401, has '02' in the lower byte of processor_id, while A2, with a PRODUCT_ID of 0x402, has '04' in the lower byte of processor_id. So, to check for >= A2, we really need to check the lower byte of processor_id against >= 4. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-04-02[ARM] 3439/2: xsc3: add I/O coherency supportLennert Buytenhek
Patch from Lennert Buytenhek This patch adds support for the I/O coherent cache available on the xsc3. The approach is to provide a simple API to determine whether the chipset supports coherency by calling arch_is_coherent() and then setting the appropriate system memory PTE and PMD bits. In addition, we call this API on dma_alloc_coherent() and dma_map_single() calls. A generic version exists that will compile out all the coherency-related code that is not needed on the majority of ARM systems. Note that we do not check for coherency in the dma_alloc_writecombine() function as that still requires a special PTE setting. We also don't touch dma_mmap_coherent() as that is a special ARM-only API that is by definition only used on non-coherent system. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-28[ARM] 3388/1: ixp23xx: add core ixp23xx supportLennert Buytenhek
Patch from Lennert Buytenhek This patch adds support for the Intel ixp23xx series of CPUs. The ixp23xx is an XSC3 based CPU with 512K of L2 cache, a 64bit 66MHz PCI interface, two DDR RAM interfaces, QDR RAM interfaces, two gigabit MACs, two 10/100 MACs, expansion bus, four microengines, a Media and Switch Fabric unit almost identical to the one on the ixp2400, two xscale (8250ish) UARTs and a bunch of other stuff. This patch adds the core ixp23xx support code, and support for the ADI Engineering Roadrunner, Intel IXDP2351, and IP Fabrics Double Espresso platforms. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>