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path: root/include/asm-x86/cpufeature.h
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2008-07-08Merge branches 'x86/mmio', 'x86/delay', 'x86/idle', 'x86/oprofile', ↵Ingo Molnar
'x86/debug', 'x86/ptrace' and 'x86/amd-iommu' into x86/devel
2008-06-24x86: add X86_FEATURE_IBS cpu featureRobert Richter
This adds IBS to the cpu feature flags allowing Perfmon and OProfile to use cpu_has(). Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-05-25x86: setup_force_cpu_cap(): don't do clear_bit(non-unsigned-long)Andrew Morton
Another hack to make proper prototyping of x86 bitops viable. Cc: Andrea Arcangeli <andrea@qumranet.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-04-17x86: PAT infrastructure patchvenkatesh.pallipadi@intel.com
Sets up pat_init() infrastructure. PAT MSR has following setting. PAT |PCD ||PWT ||| 000 WB _PAGE_CACHE_WB 001 WC _PAGE_CACHE_WC 010 UC- _PAGE_CACHE_UC_MINUS 011 UC _PAGE_CACHE_UC We are effectively changing WT from boot time setting to WC. UC_MINUS is used to provide backward compatibility to existing /dev/mem users(X). reserve_memtype and free_memtype are new interfaces for maintaining alias-free mapping. It is currently implemented in a simple way with a linked list and not optimized. reserve and free tracks the effective memory type, as a result of PAT and MTRR setting rather than what is actually requested in PAT. pat_init piggy backs on mtrr_init as the rules for setting both pat and mtrr are same. Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-04-17x86: add cpu_has_arch_perfmonstephane eranian
adds cpu_has_arch_perfmon to test presence of architectural perfmon on Intel x86 processor Signed-off-by: Stephane Eranian <eranian@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-04-17x86: clean up cpu capabilities accessesIngo Molnar
introduce test_cpu_cap() for raw access to the real CPU capabilities as they are present in x86_capability. (cpu_has() will shortcut certain tests during build-time) Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-02-04x86: add feature macros for the gbpages cpuid bitAndi Kleen
Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-02-04x86: unify CPU feature string namesH. Peter Anvin
Move the CPU feature string names to a separate file (common to 32 and 64 bits); additionally, make <asm/cpufeature.h> includable by host code in preparation for including the CPU feature strings in the boot code. Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-01-30x86: convert TSC disabling to generic cpuid disable bitmapAndi Kleen
Fix from: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-01-30x86: add framework to disable CPUID bits on the command lineAndi Kleen
There are already various options to disable specific cpuid bits on the command line. They all use their own variable. Add a generic mask to make this easier in the future. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-01-30x86: 64-bit, remove redundant cpu_has_ definitionsKyle McMartin
PSE, PGE, XMM, XMM2, and FXSR are defined as required features, and will be optimized to a constant at compile time. Remove their redundant definitions. Signed-off-by: Kyle McMartin <kyle@mcmartin.ca> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-01-30x86: remove the now unused X86_FEATURE_SYNC_RDTSCAndi Kleen
we need to know whether RDTSC is synchronous or not. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-01-30x86: Implement support to synchronize RDTSC with LFENCE on Intel CPUsAndi Kleen
According to Intel RDTSC can be always synchronized with LFENCE on all current CPUs. Implement the necessary CPUID bit for that. It is unclear yet if that is true for all future CPUs too, but if there's another way the kernel can be always updated. Cc: asit.k.mallick@intel.com Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-01-30x86: implement support to synchronize RDTSC through MFENCE on AMD CPUsAndi Kleen
According to AMD RDTSC can be synchronized through MFENCE. Implement the necessary CPUID bit for that. Cc: andreas.herrmann3@amd.com Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-01-30x86: x86-64 wired cpu_has macrosRoland McGrath
This adds hard-wired definitions for the remaining cpu_has_* macros that correspond to flags required-features.h demands are set for 64-bit. Using these can efficiently avoid some #ifdef's when merging 32-bit and 64-bit code together. Signed-off-by: Roland McGrath <roland@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-01-30x86: add set/clear_cpu_cap operationsJeremy Fitzhardinge
The patch to suppress bitops-related warnings added a pile of ugly casts. Many of these were related to the management of x86 CPU capabilities. Clean these up by adding specific set/clear_cpu_cap macros, and use them consistently. Signed-off-by: Jeremy Fitzhardinge <jeremy@xensource.com> Cc: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-01-30x86: clean up bitops-related warningsJeremy Fitzhardinge
Add casts to appropriate places to silence spurious bitops warnings. Signed-off-by: Jeremy Fitzhardinge <jeremy@xensource.com> Cc: Andi Kleen <ak@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-01-30x86: cleanup tlbflush.h variantsThomas Gleixner
Bring the tlbflush.h variants into sync to prepare merging and paravirt support. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-01-30x86: unify asm/cpufeature.hH. Peter Anvin
asm/cpufeature.h was already almost unified; this completes the job. Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2007-10-11i386/x86_64: move headers to include/asm-x86Thomas Gleixner
Move the headers to include/asm-x86 and fixup the header install make rules Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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