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2007-10-11[MIPS] Allow hardwiring of the CPU type to a single type for optimization.Ralf Baechle
This saves a few k on systems which only ever ship with a single CPU type. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Cobalt: Move reset port definition to arch/mips/cobalt/reset.cYoichi Yuasa
It's only used in arch/mips/cobalt/reset.c. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Cobalt: Move UART base definition to arch/mips/cobalt/console.cYoichi Yuasa
They're only used in arch/mips/cobalt/console.c. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Cobalt: Move PCI definitions to arch/mips/pci/fixup-cobalt.c.Yoichi Yuasa
These PCI definitions are only used in arch/mips/pci/fixup-cobalt.c. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Optimize __alloc_zeroed_user_highpage implementation.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] i8253 PIT clocksource and clockevent driversRalf Baechle
Derived from the i386 variant with a few x86 complexities chopped off. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Implement clockevents for R4000-style cp0 count/compare interruptRalf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Consolidate all variants of MIPS cp0 timer interrupt handlers.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Switch from to_tm to rtc_time_to_tmRalf Baechle
This replaces the MIPS-specific to_tm function with the generic rtc_time_to_tm function. The big difference between the two functions is that rtc_time_to_tm uses epoch 70 while to_tm uses 1970, so the result of rtc_time_to_tm needs to be fixed up. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Deforest the function pointer jungle in the time code.Ralf Baechle
Hard to follow who is pointing what to where and why so it's simply getting in the way of the time code renovation. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] ARC: Get rid of mips_machgroupRalf Baechle
This has not been any serious user of this ill conceived thing since the original invention in like '95. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Split up war.hRalf Baechle
It was getting a little big, ugly and a primary source for merge conflicts. Also the old method was a bit too forgiving in that the workaround did default to off, so now there is an explicit #error forcing platform maintainers to think if they should enable a workaround for a particular platform. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Add gpio support to the BCM47XX platformAurelien Jarno
Add GPIO support to the BCM47XX platform. It will be used by a GPIO LED driver. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Move ARC code into arch/mips/fw/arcAurelien Jarno
Move the ARC code to arch/mips/fw/arc from arch/mips/arc. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Move CFE code into arch/mips/fw/cfeAurelien Jarno
Move the platform independent part of the CFE code to arch/mips/fw/cfe from arch/mips/sibyte/cfe. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Remove IP27 specific structures from struct cpuinfo_mipsRalf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.Ralf Baechle
It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Add GT641xx IRQ routines.Yoichi Yuasa
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] GT64120: Remove unused definitionsYoichi Yuasa
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] i8295 cleanups.Yoichi Yuasa
o Move i8259 function declarations to include/asm-mips/i8259.h o Make i8259.c functions static where possible. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Define known MIPS ISA overrides for Sibyte and Excite boards.Thiemo Seufer
Signed-Off-By: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] floppy: Rewrite fd_cacheflush() to use dma_cache_sync().Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] PCI: Always enable CONFIG_PCI_DOMAINSRalf Baechle
The cost is just too low. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] tx4927: Cleanup unused macros and non-standard IO accessors.Atsushi Nemoto
This patch removes many unused constants, replaces non-standard IO accessors with standard ones, and kills terrible tx4927_mips.h file. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Add support for BCM47XX CPUs.Aurelien Jarno
Note that the BCM4710 does not support the wait instruction, this is not a mistake in the code. It originally comes from the OpenWrt patches. Cc: Michael Buesch <mb@bu3sch.de> Cc: Felix Fietkau <nbd@openwrt.org> Cc: Florian Schirmer <jolt@tuxbox.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] JAZZ fixesThomas Bogendoerfer
- restructured irq handling - switched vdma to use memory allocated via get_free_pages - setup platform devices for serial, jazz_esp and jazzsonic - fixed cmos rtc access Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Add back support for LASAT platformsBrian Murphy
Signed-off-by: Brian Murphy <brian@murphy.dk> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] fix ABI check in include/asm-mips/arv/hinv.hYoichi Yuasa
Fix ABI check in include/asm-mips/arv/hinv.h Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] remove unused include/asm-mips/ip32/machine.hYoichi Yuasa
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Rename CONFIG_BUILD_ELF64 into KBUILD_64BIT_SYM32Franck Bui-Huu
This patch renames it for 3 reasons: - "CONFIG" pattern is used by Kconfig. Now this macro is no more defined by Kconfig but by Kbuild itself make this clear by translating "CONFIG" into "KBUILD". - "ELF32" word is improper because it is irrelevant to ELF format and it makes confusion with CONFIG_BOOT_ELF32. So translate it with SYM32. - Add "64BIT" part to make clear that this macro implies a 64 bits kernel. Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Automatically set CONFIG_BUILD_ELF64Franck Bui-Huu
We do not rely on user anymore to setup this config correctly. Instead we make our choice depending on the load address. If we want to force Kbuild to use ELF64 format whatever the load address we can still do: $ make BUILD_ELF32=no Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] IRQ Affinity Support for SMTC on Malta PlatformKevin D. Kissell
Signed-off-by: Kevin D. Kissell <kevink@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-08Merge branch 'master' of ↵Linus Torvalds
master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6 * 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6: [IPv6]: Fix ICMPv6 redirect handling with target multicast address [PKT_SCHED] cls_u32: error code isn't been propogated properly [ROSE]: Fix rose.ko oops on unload [TCP]: Fix fastpath_cnt_hint when GSO skb is partially ACKed
2007-10-08mm: set_page_dirty_balance() vs ->page_mkwrite()Peter Zijlstra
All the current page_mkwrite() implementations also set the page dirty. Which results in the set_page_dirty_balance() call to _not_ call balance, because the page is already found dirty. This allows us to dirty a _lot_ of pages without ever hitting balance_dirty_pages(). Not good (tm). Force a balance call if ->page_mkwrite() was successful. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-07[ROSE]: Fix rose.ko oops on unloadAlexey Dobriyan
Commit a3d384029aa304f8f3f5355d35f0ae274454f7cd aka "[AX.25]: Fix unchecked rose_add_loopback_neigh uses" transformed rose_loopback_neigh var into statically allocated one. However, on unload it will be kfree's which can't work. Steps to reproduce: modprobe rose rmmod rose BUG: unable to handle kernel NULL pointer dereference at virtual address 00000008 printing eip: c014c664 *pde = 00000000 Oops: 0000 [#1] PREEMPT DEBUG_PAGEALLOC Modules linked in: rose ax25 fan ufs loop usbhid rtc snd_intel8x0 snd_ac97_codec ehci_hcd ac97_bus uhci_hcd thermal usbcore button processor evdev sr_mod cdrom CPU: 0 EIP: 0060:[<c014c664>] Not tainted VLI EFLAGS: 00210086 (2.6.23-rc9 #3) EIP is at kfree+0x48/0xa1 eax: 00000556 ebx: c1734aa0 ecx: f6a5e000 edx: f7082000 esi: 00000000 edi: f9a55d20 ebp: 00200287 esp: f6a5ef28 ds: 007b es: 007b fs: 0000 gs: 0033 ss: 0068 Process rmmod (pid: 1823, ti=f6a5e000 task=f7082000 task.ti=f6a5e000) Stack: f9a55d20 f9a5200c 00000000 00000000 00000000 f6a5e000 f9a5200c f9a55a00 00000000 bf818cf0 f9a51f3f f9a55a00 00000000 c0132c60 65736f72 00000000 f69f9630 f69f9528 c014244a f6a4e900 00200246 f7082000 c01025e6 00000000 Call Trace: [<f9a5200c>] rose_rt_free+0x1d/0x49 [rose] [<f9a5200c>] rose_rt_free+0x1d/0x49 [rose] [<f9a51f3f>] rose_exit+0x4c/0xd5 [rose] [<c0132c60>] sys_delete_module+0x15e/0x186 [<c014244a>] remove_vma+0x40/0x45 [<c01025e6>] sysenter_past_esp+0x8f/0x99 [<c012bacf>] trace_hardirqs_on+0x118/0x13b [<c01025b6>] sysenter_past_esp+0x5f/0x99 ======================= Code: 05 03 1d 80 db 5b c0 8b 03 25 00 40 02 00 3d 00 40 02 00 75 03 8b 5b 0c 8b 73 10 8b 44 24 18 89 44 24 04 9c 5d fa e8 77 df fd ff <8b> 56 08 89 f8 e8 84 f4 fd ff e8 bd 32 06 00 3b 5c 86 60 75 0f EIP: [<c014c664>] kfree+0x48/0xa1 SS:ESP 0068:f6a5ef28 Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-07Don't do load-average calculations at even 5-second intervalsLinus Torvalds
It turns out that there are a few other five-second timers in the kernel, and if the timers get in sync, the load-average can get artificially inflated by events that just happen to coincide. So just offset the load average calculation it by a timer tick. Noticed by Anders Boström, for whom the coincidence started triggering on one of his machines with the JBD jiffies rounding code (JBD is one of the subsystems that also end up using a 5-second timer by default). Tested-by: Anders Boström <anders@bostrom.dyndns.org> Cc: Chuck Ebbert <cebbert@redhat.com> Cc: Arjan van de Ven <arjan@linux.intel.com> Cc: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-05Remove unnecessary cast in prefetch()Serge Belyshev
It is ok to call prefetch() function with NULL argument, as specifically commented in include/linux/prefetch.h. But in standard C, it is invalid to dereference NULL pointer (see C99 standard 6.5.3.2 paragraph 4 and note #84). prefetch() has a memory reference for its argument. Newer gcc versions (4.3 and above) will use that to conclude that "x" argument is non-null and thus wreaking havok everywhere prefetch() was inlined. Fixed by removing cast and changing asm constraint. [ It seems in theory gcc 4.2 could miscompile this too; although no cases known. In 2.6.24 we should probably switch to __builtin_prefetch() instead, but this is a simpler fix for now. -- AK ] Signed-off-by: Serge Belyshev <belyshev@depni.sinp.msu.ru> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-03Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linusLinus Torvalds
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] Terminally fix local_{dec,sub}_if_positive [MIPS] Type proof reimplementation of cmpxchg. [MIPS] pg-r4k.c: Fix a typo in an R4600 v2 erratum workaround
2007-10-04Blackfin arch: fix PORT_J BUG for BF537/6 EMAC driver reported by Kalle ↵Michael Hennerich
Pokki <kalle.pokki@iki.fi> Cc: Kalle Pokki <kalle.pokki@iki.fi> Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-10-04Blackfin arch: gpio pinmux and resource allocation API required by BF537 on ↵Michael Hennerich
chip ethernet mac driver Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-10-03[MIPS] Terminally fix local_{dec,sub}_if_positiveRalf Baechle
They contain 64-bit instructions so wouldn't work on 32-bit kernels or 32-bit hardware. Since there are no users, blow them away. They probably were only ever created because there are atomic_sub_if_positive and atomic_dec_if_positive which exist only for sake of semaphores. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-03[MIPS] Type proof reimplementation of cmpxchg.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-01Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linusLinus Torvalds
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] vmlinux.lds.S: Handle note sections [MIPS] Fix value of O_TRUNC
2007-10-01[MIPS] Fix value of O_TRUNCRalf Baechle
A "cleanup" almost two years ago deleted the old definition from <asm/fcntl.h>, so asm-generic/fcntl.h defaulted it to the the same value as FASYNC ... which happened to be the wrong thing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-09-29i386: remove bogus comment about memory barrierNick Piggin
The comment being removed by this patch is incorrect and misleading. In the following situation: 1. load ... 2. store 1 -> X 3. wmb 4. rmb 5. load a <- Y 6. store ... 4 will only ensure ordering of 1 with 5. 3 will only ensure ordering of 2 with 6. Further, a CPU with strictly in-order stores will still only provide that 2 and 6 are ordered (effectively, it is the same as a weakly ordered CPU with wmb after every store). In all cases, 5 may still be executed before 2 is visible to other CPUs! The additional piece of the puzzle that mb() provides is the store/load ordering, which fundamentally cannot be achieved with any combination of rmb()s and wmb()s. This can be an unexpected result if one expected any sort of global ordering guarantee to barriers (eg. that the barriers themselves are sequentially consistent with other types of barriers). However sfence or lfence barriers need only provide an ordering partial ordering of memory operations -- Consider that wmb may be implemented as nothing more than inserting a special barrier entry in the store queue, or, in the case of x86, it can be a noop as the store queue is in order. And an rmb may be implemented as a directive to prevent subsequent loads only so long as their are no previous outstanding loads (while there could be stores still in store queues). I can actually see the occasional load/store being reordered around lfence on my core2. That doesn't prove my above assertions, but it does show the comment is wrong (unless my program is -- can send it out by request). So: mb() and smp_mb() always have and always will require a full mfence or lock prefixed instruction on x86. And we should remove this comment. Signed-off-by: Nick Piggin <npiggin@suse.de> Cc: Paul McKenney <paulmck@us.ibm.com> Cc: David Howells <dhowells@redhat.com> Cc: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-09-28Merge branch 'master' of ↵Linus Torvalds
master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6 * 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6: [TCP]: Fix MD5 signature handling on big-endian. [NET]: Zero length write() on socket should not simply return 0.
2007-09-28[TCP]: Fix MD5 signature handling on big-endian.David S. Miller
Based upon a report and initial patch by Peter Lieven. tcp4_md5sig_key and tcp6_md5sig_key need to start with the exact same members as tcp_md5sig_key. Because they are both cast to that type by tcp_v{4,6}_md5_do_lookup(). Unfortunately tcp{4,6}_md5sig_key use a u16 for the key length instead of a u8, which is what tcp_md5sig_key uses. This just so happens to work by accident on little-endian, but on big-endian it doesn't. Instead of casting, just place tcp_md5sig_key as the first member of the address-family specific structures, adjust the access sites, and kill off the ugly casts. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-09-27[MIPS] Fix CONFIG_BUILD_ELF64 kernels with symbols in CKSEG0.Ralf Baechle
The __pa() for those did assume that all symbols have XKPHYS values and the math fails for any other address range. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-09-26Revert "[PATCH] x86-64: fix x86_64-mm-sched-clock-share"Linus Torvalds
This reverts commit 184c44d2049c4db7ef6ec65794546954da2c6a0e. As noted by Dave Jones: "Linus, please revert the above cset. It doesn't seem to be necessary (it was added to fix a miscompile in 'make allnoconfig' which doesn't seem to be repeatable with it reverted) and actively breaks the ARM SA1100 framebuffer driver." Requested-by: Dave Jones <davej@redhat.com> Cc: Russell King <rmk+lkml@arm.linux.org.uk> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-09-26Revert "x86-64: Disable local APIC timer use on AMD systems with C1E"Linus Torvalds
This reverts commit e66485d747505e9d960b864fc6c37f8b2afafaf0, since Rafael Wysocki noticed that the change only works for his in -mm, not in mainline (and that both "noapictimer" _and_ "apicmaintimer" are broken on his hardware, but that's apparently not a regression, just a symptom of the same issue that causes the automatic apic timer disable to not work). It turns out that it really doesn't work correctly on x86-64, since x86-64 doesn't use the generic clock events for timers yet. Thanks to Rafal for testing, and here's the ugly details on x86-64 as per Thomas: "I just looked into the code and the logic vs. noapictimer on SMP is completely broken. On i386 the noapictimer option not only disables the local APIC timer, it also registers the CPUs for broadcasting via IPI on SMP systems. The x86-64 code uses the broadcast only when the local apic timer is active, i.e. "noapictimer" is not on the command line. This defeats the whole purpose of "noapictimer". It should be there to make boxen work, where the local APIC timer actually has a hardware problem, e.g. the nx6325. The current implementation of x86_64 only fixes the ACPI c-states related problem where the APIC timer stops in C3(2), nothing else. On nx6325 and other AMD X2 equipped systems which have the C1E enabled we run into the following: PIT keeps jiffies (and the system) running, but the local APIC timer interrupts can get out of sync due to this C1E effect. I don't think this is a critical problem, but it is wrong nevertheless. I think it's safe to revert the C1E patch and postpone the fix to the clock events conversion." On further reflection, Thomas noted: "It's even worse than I thought on the first check: "noapictimer" on the command line of an SMP box prevents _ONLY_ the boot CPU apic timer from being used. But the secondary CPU is still unconditionally setting up the APIC timer and uses the non calibrated variable calibration_result, which is of course 0, to setup the APIC timer. Wreckage guaranteed." so we'll just have to wait for the x86 merge to hopefully fix this up for x86-64. Tested-and-requested-by: Rafael J. Wysocki <rjw@sisk.pl> Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>