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Kernel
drm-tracking
gdrm-2.6.31
gdrm-2.6.32
gdrm-2.6.34
gdrm-for-merging
om-gta02-2.6.32
om-gta02-2.6.34
My Linux kernel repository
Thomas White
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Author
2006-03-20
[SPARC64]: Add SUN4V Hypervisor Console driver.
David S. Miller
2006-03-20
[SPARC64]: Use ASI_SCRATCHPAD address 0x0 properly.
David S. Miller
2006-03-20
[SPARC64]: Add HV_PCI_TSBID() macro.
David S. Miller
2006-03-20
[SPARC64]: More SUN4V PCI controller work.
David S. Miller
2006-03-20
[SPARC64]: Beginnings of SUN4V PCI controller support.
David S. Miller
2006-03-20
[SPARC]: Clean up idprom header files.
David S. Miller
2006-03-20
[SPARC64]: Hypervisor TSB context switching.
David S. Miller
2006-03-20
[SPARC64]: Implement sun4v TSB miss handlers.
David S. Miller
2006-03-20
[SPARC64]: Detect sun4v early in boot process.
David S. Miller
2006-03-20
[SPARC64]: Sun4v cross-call sending support.
David S. Miller
2006-03-20
[SPARC64]: Sun4v interrupt handling.
David S. Miller
2006-03-20
[SPARC64]: Add sun4v mondo queue bases to struct trap_per_cpu.
David S. Miller
2006-03-20
[SPARC64]: Fix some comment typos in asm/hypervisor.h
David S. Miller
2006-03-20
[SPARC64]: Patch up mmu context register writes for sun4v.
David S. Miller
2006-03-20
[SPARC64]: Register per-cpu fault status area with sun4v hypervisor.
David S. Miller
2006-03-20
[SPARC64]: asm/cpudata.h needs asm/asi.h
David S. Miller
2006-03-20
[SPARC64]: Rename gl_{1,2}insn_patch --> sun4v_{1,2}insn_patch
David S. Miller
2006-03-20
[SPARC64]: Initial sun4v TLB miss handling infrastructure.
David S. Miller
2006-03-20
[SPARC64]: Sanitize %pstate writes for sun4v.
David S. Miller
2006-03-20
[SPARC64]: Kill all %pstate changes in context switch code.
David S. Miller
2006-03-20
[SPARC64]: Add initial code to twiddle %gl on trap entry/exit.
David S. Miller
2006-03-20
[SPARC64]: Add define for "GL" field of sun4v %tstate register.
David S. Miller
2006-03-20
[SPARC64]: Add sun4v case to __GET_CPUID() patch tables.
David S. Miller
2006-03-20
[SPARC64]: Sun4v interrupt queue register definitions.
David S. Miller
2006-03-20
[SPARC64]: Sun4v scratchpad register layout.
David S. Miller
2006-03-20
[SPARC64]: Sun4v specific ASI defines.
David S. Miller
2006-03-20
[SPARC64]: Add Niagara init-store twin-load ASI defines.
David S. Miller
2006-03-20
[SPARC64]: Add 'hypervisor' to ultra_tlb_type enumeration.
David S. Miller
2006-03-20
[SPARC64]: SUN4V hypervisor interface defines.
David S. Miller
2006-03-20
[SPARC64]: Refine register window trap handling.
David S. Miller
2006-03-20
[SPARC64]: Add explicit register args to trap state loading macros.
David S. Miller
2006-03-20
[SPARC64]: Refine code sequences to get the cpu id.
David S. Miller
2006-03-20
[SPARC64]: Correctable ECC errors cannot occur at trap level > 0.
David S. Miller
2006-03-20
[SPARC64]: Access TSB with physical addresses when possible.
David S. Miller
2006-03-20
[SPARC64]: Kill out-of-date commentary in asm-sparc64/tsb.h
David S. Miller
2006-03-20
[SPARC64]: Fix race in LOAD_PER_CPU_BASE()
David S. Miller
2006-03-20
[SPARC64]: Increase swapper_tsb size to 32K.
David S. Miller
2006-03-20
[SPARC64]: Kill sole argument passed to setup_tba().
David S. Miller
2006-03-20
[SPARC64]: Fix incorrect TSB lock bit handling.
David S. Miller
2006-03-20
[SPARC64]: Preload TSB entries from update_mmu_cache().
David S. Miller
2006-03-20
[SPARC64]: Dynamically grow TSB in response to RSS growth.
David S. Miller
2006-03-20
[SPARC64]: Add infrastructure for dynamic TSB sizing.
David S. Miller
2006-03-20
[SPARC64]: TSB refinements.
David S. Miller
2006-03-20
[SPARC64]: Elminate all usage of hard-coded trap globals.
David S. Miller
2006-03-20
[SPARC64]: Kill pgtable quicklists and use SLAB.
David S. Miller
2006-03-20
[SPARC64]: No need to D-cache color page tables any longer.
David S. Miller
2006-03-20
[SPARC64]: Move away from virtual page tables, part 1.
David S. Miller
2006-03-19
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
Linus Torvalds
2006-03-19
[TG3]: 40-bit DMA workaround part 2
Michael Chan
2006-03-19
[AX.25]: Fix potencial memory hole.
Ralf Baechle DL5RB
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