From 3e7b484354c8f60c12119c1c5174ef354696c30d Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 11 Jan 2010 22:28:54 +0000 Subject: powerpc: Fix decrementer setup on 1GHz boards We noticed that recent kernels didn't boot on our 1GHz Canyonlands 460EX boards anymore. As it seems, patch 8d165db1 [powerpc: Improve decrementer accuracy] introduced this problem. The routine div_sc() overflows with shift = 32 resulting in this incorrect setup: time_init: decrementer frequency = 1000.000012 MHz time_init: processor frequency = 1000.000012 MHz clocksource: timebase mult[400000] shift[22] registered clockevent: decrementer mult[33] shift[32] cpu[0] This patch now introduces a local div_dc64() version of this function so that this overflow doesn't happen anymore. Signed-off-by: Stefan Roese Cc: Benjamin Herrenschmidt Cc: Detlev Zundel Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/time.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c index 9ba2cc88591..6c6093d67f3 100644 --- a/arch/powerpc/kernel/time.c +++ b/arch/powerpc/kernel/time.c @@ -903,12 +903,21 @@ static void decrementer_set_mode(enum clock_event_mode mode, decrementer_set_next_event(DECREMENTER_MAX, dev); } +static inline uint64_t div_sc64(unsigned long ticks, unsigned long nsec, + int shift) +{ + uint64_t tmp = ((uint64_t)ticks) << shift; + + do_div(tmp, nsec); + return tmp; +} + static void __init setup_clockevent_multiplier(unsigned long hz) { u64 mult, shift = 32; while (1) { - mult = div_sc(hz, NSEC_PER_SEC, shift); + mult = div_sc64(hz, NSEC_PER_SEC, shift); if (mult && (mult >> 32UL) == 0UL) break; -- cgit v1.2.3