From d782c3f95c9263dc0b98e7115f75f1e18b9600b3 Mon Sep 17 00:00:00 2001
From: Zhao Yakui <yakui.zhao@intel.com>
Date: Mon, 22 Jun 2009 13:17:08 +0800
Subject: drm/mode: add the CVT algorithm in kernel space

Add the CVT algorithm in kernel space. And this function can be called to
generate the required modeline.

I copied it from the file of xserver/hw/xfree86/modes/xf86cvt.c. What I have
done is to translate it by using integer calculation. This is to avoid
the float-point calculation in kernel space.

[airlied:- cleaned up some bits]
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Dave Airlie <airlied@linux.ie>
---
 drivers/gpu/drm/drm_modes.c | 219 ++++++++++++++++++++++++++++++++++++++++++++
 include/drm/drm_crtc.h      |   3 +
 2 files changed, 222 insertions(+)

diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 54f492a488a..0dbc7e4f864 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -8,6 +8,7 @@
  * Copyright © 2007 Dave Airlie
  * Copyright © 2007-2008 Intel Corporation
  *   Jesse Barnes <jesse.barnes@intel.com>
+ * Copyright 2005-2006 Luc Verhaegen
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -61,6 +62,224 @@ void drm_mode_debug_printmodeline(struct drm_display_mode *mode)
 }
 EXPORT_SYMBOL(drm_mode_debug_printmodeline);
 
+/**
+ * drm_cvt_mode -create a modeline based on CVT algorithm
+ * @dev: DRM device
+ * @hdisplay: hdisplay size
+ * @vdisplay: vdisplay size
+ * @vrefresh  : vrefresh rate
+ * @reduced : Whether the GTF calculation is simplified
+ * @interlaced:Whether the interlace is supported
+ *
+ * LOCKING:
+ * none.
+ *
+ * return the modeline based on CVT algorithm
+ *
+ * This function is called to generate the modeline based on CVT algorithm
+ * according to the hdisplay, vdisplay, vrefresh.
+ * It is based from the VESA(TM) Coordinated Video Timing Generator by
+ * Graham Loveridge April 9, 2003 available at
+ * http://www.vesa.org/public/CVT/CVTd6r1.xls
+ *
+ * And it is copied from xf86CVTmode in xserver/hw/xfree86/modes/xf86cvt.c.
+ * What I have done is to translate it by using integer calculation.
+ */
+#define HV_FACTOR			1000
+struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay,
+				      int vdisplay, int vrefresh,
+				      bool reduced, bool interlaced)
+{
+	/* 1) top/bottom margin size (% of height) - default: 1.8, */
+#define	CVT_MARGIN_PERCENTAGE		18
+	/* 2) character cell horizontal granularity (pixels) - default 8 */
+#define	CVT_H_GRANULARITY		8
+	/* 3) Minimum vertical porch (lines) - default 3 */
+#define	CVT_MIN_V_PORCH			3
+	/* 4) Minimum number of vertical back porch lines - default 6 */
+#define	CVT_MIN_V_BPORCH		6
+	/* Pixel Clock step (kHz) */
+#define CVT_CLOCK_STEP			250
+	struct drm_display_mode *drm_mode;
+	bool margins = false;
+	unsigned int vfieldrate, hperiod;
+	int hdisplay_rnd, hmargin, vdisplay_rnd, vmargin, vsync;
+	int interlace;
+
+	/* allocate the drm_display_mode structure. If failure, we will
+	 * return directly
+	 */
+	drm_mode = drm_mode_create(dev);
+	if (!drm_mode)
+		return NULL;
+
+	/* the CVT default refresh rate is 60Hz */
+	if (!vrefresh)
+		vrefresh = 60;
+
+	/* the required field fresh rate */
+	if (interlaced)
+		vfieldrate = vrefresh * 2;
+	else
+		vfieldrate = vrefresh;
+
+	/* horizontal pixels */
+	hdisplay_rnd = hdisplay - (hdisplay % CVT_H_GRANULARITY);
+
+	/* determine the left&right borders */
+	hmargin = 0;
+	if (margins) {
+		hmargin = hdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000;
+		hmargin -= hmargin % CVT_H_GRANULARITY;
+	}
+	/* find the total active pixels */
+	drm_mode->hdisplay = hdisplay_rnd + 2 * hmargin;
+
+	/* find the number of lines per field */
+	if (interlaced)
+		vdisplay_rnd = vdisplay / 2;
+	else
+		vdisplay_rnd = vdisplay;
+
+	/* find the top & bottom borders */
+	vmargin = 0;
+	if (margins)
+		vmargin = vdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000;
+
+	drm_mode->vdisplay = vdisplay_rnd + 2 * vmargin;
+
+	/* Interlaced */
+	if (interlaced)
+		interlace = 1;
+	else
+		interlace = 0;
+
+	/* Determine VSync Width from aspect ratio */
+	if (!(vdisplay % 3) && ((vdisplay * 4 / 3) == hdisplay))
+		vsync = 4;
+	else if (!(vdisplay % 9) && ((vdisplay * 16 / 9) == hdisplay))
+		vsync = 5;
+	else if (!(vdisplay % 10) && ((vdisplay * 16 / 10) == hdisplay))
+		vsync = 6;
+	else if (!(vdisplay % 4) && ((vdisplay * 5 / 4) == hdisplay))
+		vsync = 7;
+	else if (!(vdisplay % 9) && ((vdisplay * 15 / 9) == hdisplay))
+		vsync = 7;
+	else /* custom */
+		vsync = 10;
+
+	if (!reduced) {
+		/* simplify the GTF calculation */
+		/* 4) Minimum time of vertical sync + back porch interval (µs)
+		 * default 550.0
+		 */
+		int tmp1, tmp2;
+#define CVT_MIN_VSYNC_BP	550
+		/* 3) Nominal HSync width (% of line period) - default 8 */
+#define CVT_HSYNC_PERCENTAGE	8
+		unsigned int hblank_percentage;
+		int vsyncandback_porch, vback_porch, hblank;
+
+		/* estimated the horizontal period */
+		tmp1 = HV_FACTOR * 1000000  -
+				CVT_MIN_VSYNC_BP * HV_FACTOR * vfieldrate;
+		tmp2 = (vdisplay_rnd + 2 * vmargin + CVT_MIN_V_PORCH) * 2 +
+				interlace;
+		hperiod = tmp1 * 2 / (tmp2 * vfieldrate);
+
+		tmp1 = CVT_MIN_VSYNC_BP * HV_FACTOR / hperiod + 1;
+		/* 9. Find number of lines in sync + backporch */
+		if (tmp1 < (vsync + CVT_MIN_V_PORCH))
+			vsyncandback_porch = vsync + CVT_MIN_V_PORCH;
+		else
+			vsyncandback_porch = tmp1;
+		/* 10. Find number of lines in back porch */
+		vback_porch = vsyncandback_porch - vsync;
+		drm_mode->vtotal = vdisplay_rnd + 2 * vmargin +
+				vsyncandback_porch + CVT_MIN_V_PORCH;
+		/* 5) Definition of Horizontal blanking time limitation */
+		/* Gradient (%/kHz) - default 600 */
+#define CVT_M_FACTOR	600
+		/* Offset (%) - default 40 */
+#define CVT_C_FACTOR	40
+		/* Blanking time scaling factor - default 128 */
+#define CVT_K_FACTOR	128
+		/* Scaling factor weighting - default 20 */
+#define CVT_J_FACTOR	20
+#define CVT_M_PRIME	(CVT_M_FACTOR * CVT_K_FACTOR / 256)
+#define CVT_C_PRIME	((CVT_C_FACTOR - CVT_J_FACTOR) * CVT_K_FACTOR / 256 + \
+			 CVT_J_FACTOR)
+		/* 12. Find ideal blanking duty cycle from formula */
+		hblank_percentage = CVT_C_PRIME * HV_FACTOR - CVT_M_PRIME *
+					hperiod / 1000;
+		/* 13. Blanking time */
+		if (hblank_percentage < 20 * HV_FACTOR)
+			hblank_percentage = 20 * HV_FACTOR;
+		hblank = drm_mode->hdisplay * hblank_percentage /
+			 (100 * HV_FACTOR - hblank_percentage);
+		hblank -= hblank % (2 * CVT_H_GRANULARITY);
+		/* 14. find the total pixes per line */
+		drm_mode->htotal = drm_mode->hdisplay + hblank;
+		drm_mode->hsync_end = drm_mode->hdisplay + hblank / 2;
+		drm_mode->hsync_start = drm_mode->hsync_end -
+			(drm_mode->htotal * CVT_HSYNC_PERCENTAGE) / 100;
+		drm_mode->hsync_start += CVT_H_GRANULARITY -
+			drm_mode->hsync_start % CVT_H_GRANULARITY;
+		/* fill the Vsync values */
+		drm_mode->vsync_start = drm_mode->vdisplay + CVT_MIN_V_PORCH;
+		drm_mode->vsync_end = drm_mode->vsync_start + vsync;
+	} else {
+		/* Reduced blanking */
+		/* Minimum vertical blanking interval time (µs)- default 460 */
+#define CVT_RB_MIN_VBLANK	460
+		/* Fixed number of clocks for horizontal sync */
+#define CVT_RB_H_SYNC		32
+		/* Fixed number of clocks for horizontal blanking */
+#define CVT_RB_H_BLANK		160
+		/* Fixed number of lines for vertical front porch - default 3*/
+#define CVT_RB_VFPORCH		3
+		int vbilines;
+		int tmp1, tmp2;
+		/* 8. Estimate Horizontal period. */
+		tmp1 = HV_FACTOR * 1000000 -
+			CVT_RB_MIN_VBLANK * HV_FACTOR * vfieldrate;
+		tmp2 = vdisplay_rnd + 2 * vmargin;
+		hperiod = tmp1 / (tmp2 * vfieldrate);
+		/* 9. Find number of lines in vertical blanking */
+		vbilines = CVT_RB_MIN_VBLANK * HV_FACTOR / hperiod + 1;
+		/* 10. Check if vertical blanking is sufficient */
+		if (vbilines < (CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH))
+			vbilines = CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH;
+		/* 11. Find total number of lines in vertical field */
+		drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + vbilines;
+		/* 12. Find total number of pixels in a line */
+		drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK;
+		/* Fill in HSync values */
+		drm_mode->hsync_end = drm_mode->hdisplay + CVT_RB_H_BLANK / 2;
+		drm_mode->hsync_start = drm_mode->hsync_end = CVT_RB_H_SYNC;
+	}
+	/* 15/13. Find pixel clock frequency (kHz for xf86) */
+	drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod;
+	drm_mode->clock -= drm_mode->clock % CVT_CLOCK_STEP;
+	/* 18/16. Find actual vertical frame frequency */
+	/* ignore - just set the mode flag for interlaced */
+	if (interlaced)
+		drm_mode->vtotal *= 2;
+	/* Fill the mode line name */
+	drm_mode_set_name(drm_mode);
+	if (reduced)
+		drm_mode->flags |= (DRM_MODE_FLAG_PHSYNC |
+					DRM_MODE_FLAG_NVSYNC);
+	else
+		drm_mode->flags |= (DRM_MODE_FLAG_PVSYNC |
+					DRM_MODE_FLAG_NHSYNC);
+	if (interlaced)
+		drm_mode->flags |= DRM_MODE_FLAG_INTERLACE;
+
+    return drm_mode;
+}
+EXPORT_SYMBOL(drm_cvt_mode);
+
 /**
  * drm_mode_set_name - set the name on a mode
  * @mode: name will be set in this mode
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 7300fb86676..820bc0977e5 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -736,4 +736,7 @@ extern int drm_mode_gamma_get_ioctl(struct drm_device *dev,
 extern int drm_mode_gamma_set_ioctl(struct drm_device *dev,
 				    void *data, struct drm_file *file_priv);
 extern bool drm_detect_hdmi_monitor(struct edid *edid);
+extern struct drm_display_mode *drm_cvt_mode(struct drm_device *dev,
+				int hdisplay, int vdisplay, int vrefresh,
+				bool reduced, bool interlaced);
 #endif /* __DRM_CRTC_H__ */
-- 
cgit v1.2.3


From 26bbdadad356ec02d33657858d91675f3e9aca94 Mon Sep 17 00:00:00 2001
From: Zhao Yakui <yakui.zhao@intel.com>
Date: Mon, 22 Jun 2009 13:17:09 +0800
Subject: drm/mode: add the GTF algorithm in kernel space

Add the GTF algorithm in kernel space. And this function can be called to
generate the required modeline.

I copied it from the file of xserver/hw/xfree86/modes/xf86gtf.c. What I have
done is to translate it by using integer calculation. This is to avoid
the float-point calculation in kernel space.
At the same tie I also refer to the function of fb_get_mode in
drivers/video/fbmon.c

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Dave Airlie <airlied@linux.ie>
---
 drivers/gpu/drm/drm_modes.c | 197 ++++++++++++++++++++++++++++++++++++++++++++
 include/drm/drm_crtc.h      |   3 +
 2 files changed, 200 insertions(+)

diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 0dbc7e4f864..fd489d76fbb 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -9,6 +9,7 @@
  * Copyright © 2007-2008 Intel Corporation
  *   Jesse Barnes <jesse.barnes@intel.com>
  * Copyright 2005-2006 Luc Verhaegen
+ * Copyright (c) 2001, Andy Ritger  aritger@nvidia.com
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -280,6 +281,202 @@ struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay,
 }
 EXPORT_SYMBOL(drm_cvt_mode);
 
+/**
+ * drm_gtf_mode - create the modeline based on GTF algorithm
+ *
+ * @dev		:drm device
+ * @hdisplay	:hdisplay size
+ * @vdisplay	:vdisplay size
+ * @vrefresh	:vrefresh rate.
+ * @interlaced	:whether the interlace is supported
+ * @margins	:whether the margin is supported
+ *
+ * LOCKING.
+ * none.
+ *
+ * return the modeline based on GTF algorithm
+ *
+ * This function is to create the modeline based on the GTF algorithm.
+ * Generalized Timing Formula is derived from:
+ *	GTF Spreadsheet by Andy Morrish (1/5/97)
+ *	available at http://www.vesa.org
+ *
+ * And it is copied from the file of xserver/hw/xfree86/modes/xf86gtf.c.
+ * What I have done is to translate it by using integer calculation.
+ * I also refer to the function of fb_get_mode in the file of
+ * drivers/video/fbmon.c
+ */
+struct drm_display_mode *drm_gtf_mode(struct drm_device *dev, int hdisplay,
+				      int vdisplay, int vrefresh,
+				      bool interlaced, int margins)
+{
+	/* 1) top/bottom margin size (% of height) - default: 1.8, */
+#define	GTF_MARGIN_PERCENTAGE		18
+	/* 2) character cell horizontal granularity (pixels) - default 8 */
+#define	GTF_CELL_GRAN			8
+	/* 3) Minimum vertical porch (lines) - default 3 */
+#define	GTF_MIN_V_PORCH			1
+	/* width of vsync in lines */
+#define V_SYNC_RQD			3
+	/* width of hsync as % of total line */
+#define H_SYNC_PERCENT			8
+	/* min time of vsync + back porch (microsec) */
+#define MIN_VSYNC_PLUS_BP		550
+	/* blanking formula gradient */
+#define GTF_M				600
+	/* blanking formula offset */
+#define GTF_C				40
+	/* blanking formula scaling factor */
+#define GTF_K				128
+	/* blanking formula scaling factor */
+#define GTF_J				20
+	/* C' and M' are part of the Blanking Duty Cycle computation */
+#define GTF_C_PRIME		(((GTF_C - GTF_J) * GTF_K / 256) + GTF_J)
+#define GTF_M_PRIME		(GTF_K * GTF_M / 256)
+	struct drm_display_mode *drm_mode;
+	unsigned int hdisplay_rnd, vdisplay_rnd, vfieldrate_rqd;
+	int top_margin, bottom_margin;
+	int interlace;
+	unsigned int hfreq_est;
+	int vsync_plus_bp, vback_porch;
+	unsigned int vtotal_lines, vfieldrate_est, hperiod;
+	unsigned int vfield_rate, vframe_rate;
+	int left_margin, right_margin;
+	unsigned int total_active_pixels, ideal_duty_cycle;
+	unsigned int hblank, total_pixels, pixel_freq;
+	int hsync, hfront_porch, vodd_front_porch_lines;
+	unsigned int tmp1, tmp2;
+
+	drm_mode = drm_mode_create(dev);
+	if (!drm_mode)
+		return NULL;
+
+	/* 1. In order to give correct results, the number of horizontal
+	 * pixels requested is first processed to ensure that it is divisible
+	 * by the character size, by rounding it to the nearest character
+	 * cell boundary:
+	 */
+	hdisplay_rnd = (hdisplay + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN;
+	hdisplay_rnd = hdisplay_rnd * GTF_CELL_GRAN;
+
+	/* 2. If interlace is requested, the number of vertical lines assumed
+	 * by the calculation must be halved, as the computation calculates
+	 * the number of vertical lines per field.
+	 */
+	if (interlaced)
+		vdisplay_rnd = vdisplay / 2;
+	else
+		vdisplay_rnd = vdisplay;
+
+	/* 3. Find the frame rate required: */
+	if (interlaced)
+		vfieldrate_rqd = vrefresh * 2;
+	else
+		vfieldrate_rqd = vrefresh;
+
+	/* 4. Find number of lines in Top margin: */
+	top_margin = 0;
+	if (margins)
+		top_margin = (vdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) /
+				1000;
+	/* 5. Find number of lines in bottom margin: */
+	bottom_margin = top_margin;
+
+	/* 6. If interlace is required, then set variable interlace: */
+	if (interlaced)
+		interlace = 1;
+	else
+		interlace = 0;
+
+	/* 7. Estimate the Horizontal frequency */
+	{
+		tmp1 = (1000000  - MIN_VSYNC_PLUS_BP * vfieldrate_rqd) / 500;
+		tmp2 = (vdisplay_rnd + 2 * top_margin + GTF_MIN_V_PORCH) *
+				2 + interlace;
+		hfreq_est = (tmp2 * 1000 * vfieldrate_rqd) / tmp1;
+	}
+
+	/* 8. Find the number of lines in V sync + back porch */
+	/* [V SYNC+BP] = RINT(([MIN VSYNC+BP] * hfreq_est / 1000000)) */
+	vsync_plus_bp = MIN_VSYNC_PLUS_BP * hfreq_est / 1000;
+	vsync_plus_bp = (vsync_plus_bp + 500) / 1000;
+	/*  9. Find the number of lines in V back porch alone: */
+	vback_porch = vsync_plus_bp - V_SYNC_RQD;
+	/*  10. Find the total number of lines in Vertical field period: */
+	vtotal_lines = vdisplay_rnd + top_margin + bottom_margin +
+			vsync_plus_bp + GTF_MIN_V_PORCH;
+	/*  11. Estimate the Vertical field frequency: */
+	vfieldrate_est = hfreq_est / vtotal_lines;
+	/*  12. Find the actual horizontal period: */
+	hperiod = 1000000 / (vfieldrate_rqd * vtotal_lines);
+
+	/*  13. Find the actual Vertical field frequency: */
+	vfield_rate = hfreq_est / vtotal_lines;
+	/*  14. Find the Vertical frame frequency: */
+	if (interlaced)
+		vframe_rate = vfield_rate / 2;
+	else
+		vframe_rate = vfield_rate;
+	/*  15. Find number of pixels in left margin: */
+	if (margins)
+		left_margin = (hdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) /
+				1000;
+	else
+		left_margin = 0;
+
+	/* 16.Find number of pixels in right margin: */
+	right_margin = left_margin;
+	/* 17.Find total number of active pixels in image and left and right */
+	total_active_pixels = hdisplay_rnd + left_margin + right_margin;
+	/* 18.Find the ideal blanking duty cycle from blanking duty cycle */
+	ideal_duty_cycle = GTF_C_PRIME * 1000 -
+				(GTF_M_PRIME * 1000000 / hfreq_est);
+	/* 19.Find the number of pixels in the blanking time to the nearest
+	 * double character cell: */
+	hblank = total_active_pixels * ideal_duty_cycle /
+			(100000 - ideal_duty_cycle);
+	hblank = (hblank + GTF_CELL_GRAN) / (2 * GTF_CELL_GRAN);
+	hblank = hblank * 2 * GTF_CELL_GRAN;
+	/* 20.Find total number of pixels: */
+	total_pixels = total_active_pixels + hblank;
+	/* 21.Find pixel clock frequency: */
+	pixel_freq = total_pixels * hfreq_est / 1000;
+	/* Stage 1 computations are now complete; I should really pass
+	 * the results to another function and do the Stage 2 computations,
+	 * but I only need a few more values so I'll just append the
+	 * computations here for now */
+	/* 17. Find the number of pixels in the horizontal sync period: */
+	hsync = H_SYNC_PERCENT * total_pixels / 100;
+	hsync = (hsync + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN;
+	hsync = hsync * GTF_CELL_GRAN;
+	/* 18. Find the number of pixels in horizontal front porch period */
+	hfront_porch = hblank / 2 - hsync;
+	/*  36. Find the number of lines in the odd front porch period: */
+	vodd_front_porch_lines = GTF_MIN_V_PORCH ;
+
+	/* finally, pack the results in the mode struct */
+	drm_mode->hdisplay = hdisplay_rnd;
+	drm_mode->hsync_start = hdisplay_rnd + hfront_porch;
+	drm_mode->hsync_end = drm_mode->hsync_start + hsync;
+	drm_mode->htotal = total_pixels;
+	drm_mode->vdisplay = vdisplay_rnd;
+	drm_mode->vsync_start = vdisplay_rnd + vodd_front_porch_lines;
+	drm_mode->vsync_end = drm_mode->vsync_start + V_SYNC_RQD;
+	drm_mode->vtotal = vtotal_lines;
+
+	drm_mode->clock = pixel_freq;
+
+	drm_mode_set_name(drm_mode);
+	drm_mode->flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC;
+
+	if (interlaced) {
+		drm_mode->vtotal *= 2;
+		drm_mode->flags |= DRM_MODE_FLAG_INTERLACE;
+	}
+
+	return drm_mode;
+}
+EXPORT_SYMBOL(drm_gtf_mode);
 /**
  * drm_mode_set_name - set the name on a mode
  * @mode: name will be set in this mode
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 820bc0977e5..125994d8ac0 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -739,4 +739,7 @@ extern bool drm_detect_hdmi_monitor(struct edid *edid);
 extern struct drm_display_mode *drm_cvt_mode(struct drm_device *dev,
 				int hdisplay, int vdisplay, int vrefresh,
 				bool reduced, bool interlaced);
+extern struct drm_display_mode *drm_gtf_mode(struct drm_device *dev,
+				int hdisplay, int vdisplay, int vrefresh,
+				bool interlaced, int margins);
 #endif /* __DRM_CRTC_H__ */
-- 
cgit v1.2.3


From 5c61259e6c7290082108e93815f7f72f27da14f4 Mon Sep 17 00:00:00 2001
From: Zhao Yakui <yakui.zhao@intel.com>
Date: Mon, 22 Jun 2009 13:17:10 +0800
Subject: drm/mode: get the modeline for standard timing in EDID by using
 CVT/GTF

Create the standard timing modeline by using CVT/GFT algorithm while
interpreting the EDID.

In course of interpreting the EDID, the timing level will be obtained,
which is used to determine whether the CVT/GTF algorithm is selected to
generate the modeline for the given hdisplay/vdisplay/vrefresh_rate.
In the UMS mode firstly it will check whether it can be found in
the DMT table. If it can be found, then the modeline is returned. Then the
timing_level is used to choose CVT/GTF.
As there is no DMT table, no modeline is returned when timing level
is DMT. For the other two timing levels, the CVT/GTF will be called to
generate the required standard timing modeline.

[airlied: fixed up conflicts since EDID rework]

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Dave Airlie <airlied@linux.ie>
---
 drivers/gpu/drm/drm_edid.c | 70 ++++++++++++++++++++++++++++++++++++++--------
 1 file changed, 58 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 80cc6d06d61..bbcb2e22675 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -61,6 +61,10 @@
 /* use +hsync +vsync for detailed mode */
 #define EDID_QUIRK_DETAILED_SYNC_PP		(1 << 6)
 
+#define LEVEL_DMT	0
+#define LEVEL_GTF	1
+#define LEVEL_CVT	2
+
 static struct edid_quirk {
 	char *vendor;
 	int product_id;
@@ -240,25 +244,31 @@ static void edid_fixup_preferred(struct drm_connector *connector,
 /**
  * drm_mode_std - convert standard mode info (width, height, refresh) into mode
  * @t: standard timing params
+ * @timing_level: standard timing level
  *
  * Take the standard timing params (in this case width, aspect, and refresh)
- * and convert them into a real mode using CVT.
+ * and convert them into a real mode using CVT/GTF/DMT.
  *
  * Punts for now, but should eventually use the FB layer's CVT based mode
  * generation code.
  */
 struct drm_display_mode *drm_mode_std(struct drm_device *dev,
-				      struct std_timing *t)
+				      struct std_timing *t,
+				      int timing_level)
 {
 	struct drm_display_mode *mode;
-	int hsize = t->hsize * 8 + 248, vsize;
+	int hsize, vsize;
+	int vrefresh_rate;
 	unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
 		>> EDID_TIMING_ASPECT_SHIFT;
-
-	mode = drm_mode_create(dev);
-	if (!mode)
-		return NULL;
-
+	unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
+		>> EDID_TIMING_VFREQ_SHIFT;
+
+	/* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
+	hsize = t->hsize * 8 + 248;
+	/* vrefresh_rate = vfreq + 60 */
+	vrefresh_rate = vfreq + 60;
+	/* the vdisplay is calculated based on the aspect ratio */
 	if (aspect_ratio == 0)
 		vsize = (hsize * 10) / 16;
 	else if (aspect_ratio == 1)
@@ -268,8 +278,23 @@ struct drm_display_mode *drm_mode_std(struct drm_device *dev,
 	else
 		vsize = (hsize * 9) / 16;
 
-	drm_mode_set_name(mode);
-
+	mode = NULL;
+	switch (timing_level) {
+	case LEVEL_DMT:
+		mode = drm_mode_create(dev);
+		if (mode) {
+			mode->hdisplay = hsize;
+			mode->vdisplay = vsize;
+			drm_mode_set_name(mode);
+		}
+		break;
+	case LEVEL_GTF:
+		mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
+		break;
+	case LEVEL_CVT:
+		mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
+		break;
+	}
 	return mode;
 }
 
@@ -451,6 +476,19 @@ static int add_established_modes(struct drm_connector *connector, struct edid *e
 
 	return modes;
 }
+/**
+ * stanard_timing_level - get std. timing level(CVT/GTF/DMT)
+ * @edid: EDID block to scan
+ */
+static int standard_timing_level(struct edid *edid)
+{
+	if (edid->revision >= 2) {
+		if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
+			return LEVEL_CVT;
+		return LEVEL_GTF;
+	}
+	return LEVEL_DMT;
+}
 
 /**
  * add_standard_modes - get std. modes from EDID and add them
@@ -463,6 +501,9 @@ static int add_standard_modes(struct drm_connector *connector, struct edid *edid
 {
 	struct drm_device *dev = connector->dev;
 	int i, modes = 0;
+	int timing_level;
+
+	timing_level = standard_timing_level(edid);
 
 	for (i = 0; i < EDID_STD_TIMINGS; i++) {
 		struct std_timing *t = &edid->standard_timings[i];
@@ -472,7 +513,8 @@ static int add_standard_modes(struct drm_connector *connector, struct edid *edid
 		if (t->hsize == 1 && t->vfreq_aspect == 1)
 			continue;
 
-		newmode = drm_mode_std(dev, &edid->standard_timings[i]);
+		newmode = drm_mode_std(dev, &edid->standard_timings[i],
+					timing_level);
 		if (newmode) {
 			drm_mode_probed_add(connector, newmode);
 			modes++;
@@ -496,6 +538,9 @@ static int add_detailed_info(struct drm_connector *connector,
 {
 	struct drm_device *dev = connector->dev;
 	int i, j, modes = 0;
+	int timing_level;
+
+	timing_level = standard_timing_level(edid);
 
 	for (i = 0; i < EDID_DETAILED_TIMINGS; i++) {
 		struct detailed_timing *timing = &edid->detailed_timings[i];
@@ -541,7 +586,8 @@ static int add_detailed_info(struct drm_connector *connector,
 				struct drm_display_mode *newmode;
 
 				std = &data->data.timings[j];
-				newmode = drm_mode_std(dev, std);
+				newmode = drm_mode_std(dev, std,
+							timing_level);
 				if (newmode) {
 					drm_mode_probed_add(connector, newmode);
 					modes++;
-- 
cgit v1.2.3


From 8a4c47f346cc7a12d0897c05eb3cc1add26b487f Mon Sep 17 00:00:00 2001
From: Zhao Yakui <yakui.zhao@intel.com>
Date: Mon, 20 Jul 2009 13:48:04 +0800
Subject: drm: Remove the unused prefix in DRM_DEBUG_KMS/DRIVER/MODE

We will have to add a prefix when using the macro defintion of DRM_DEBUG_KMS
/DRM_DEBUG_DRIVER/MODE. It is not convenient. We should use the DRM_NAME
as default prefix.
So remove the prefix in the macro definition of DRM_DEBUG_KMS/DRIVER/MODE.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_modes.c       |  8 +++-----
 drivers/gpu/drm/i915/i915_dma.c   | 35 +++++++++++++++--------------------
 drivers/gpu/drm/i915/intel_lvds.c | 10 +++-------
 drivers/gpu/drm/i915/intel_sdvo.c | 35 ++++++++++++++++-------------------
 include/drm/drmP.h                | 18 +++++++++---------
 5 files changed, 46 insertions(+), 60 deletions(-)

diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index fd489d76fbb..5eca2d5c5f2 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -40,7 +40,6 @@
 #include "drm.h"
 #include "drm_crtc.h"
 
-#define DRM_MODESET_DEBUG	"drm_mode"
 /**
  * drm_mode_debug_printmodeline - debug print a mode
  * @dev: DRM device
@@ -53,8 +52,8 @@
  */
 void drm_mode_debug_printmodeline(struct drm_display_mode *mode)
 {
-	DRM_DEBUG_MODE(DRM_MODESET_DEBUG,
-		"Modeline %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x\n",
+	DRM_DEBUG_MODE("Modeline %d:\"%s\" %d %d %d %d %d %d %d %d %d %d "
+			"0x%x 0x%x\n",
 		mode->base.id, mode->name, mode->vrefresh, mode->clock,
 		mode->hdisplay, mode->hsync_start,
 		mode->hsync_end, mode->htotal,
@@ -819,8 +818,7 @@ void drm_mode_prune_invalid(struct drm_device *dev,
 			list_del(&mode->head);
 			if (verbose) {
 				drm_mode_debug_printmodeline(mode);
-				DRM_DEBUG_MODE(DRM_MODESET_DEBUG,
-					"Not using %s mode %d\n",
+				DRM_DEBUG_MODE("Not using %s mode %d\n",
 					mode->name, mode->status);
 			}
 			drm_mode_destroy(dev, mode);
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 8c4783180bf..14625e146f1 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -33,8 +33,6 @@
 #include "i915_drm.h"
 #include "i915_drv.h"
 
-#define I915_DRV	"i915_drv"
-
 /* Really want an OS-independent resettable timer.  Would like to have
  * this loop run for (eg) 3 sec, but have the timer reset every time
  * the head pointer changes, so that EBUSY only happens if the ring
@@ -101,7 +99,7 @@ static int i915_init_phys_hws(struct drm_device *dev)
 	memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 
 	I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
-	DRM_DEBUG_DRIVER(I915_DRV, "Enabled hardware status page\n");
+	DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 	return 0;
 }
 
@@ -187,8 +185,7 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 		master_priv->sarea_priv = (drm_i915_sarea_t *)
 			((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 	} else {
-		DRM_DEBUG_DRIVER(I915_DRV,
-				"sarea not found assuming DRI2 userspace\n");
+		DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 	}
 
 	if (init->ring_size != 0) {
@@ -238,7 +235,7 @@ static int i915_dma_resume(struct drm_device * dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 
-	DRM_DEBUG_DRIVER(I915_DRV, "%s\n", __func__);
+	DRM_DEBUG_DRIVER("%s\n", __func__);
 
 	if (dev_priv->ring.map.handle == NULL) {
 		DRM_ERROR("can not ioremap virtual address for"
@@ -251,14 +248,14 @@ static int i915_dma_resume(struct drm_device * dev)
 		DRM_ERROR("Can not find hardware status page\n");
 		return -EINVAL;
 	}
-	DRM_DEBUG_DRIVER(I915_DRV, "hw status page @ %p\n",
+	DRM_DEBUG_DRIVER("hw status page @ %p\n",
 				dev_priv->hw_status_page);
 
 	if (dev_priv->status_gfx_addr != 0)
 		I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
 	else
 		I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
-	DRM_DEBUG_DRIVER(I915_DRV, "Enabled hardware status page\n");
+	DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 
 	return 0;
 }
@@ -552,7 +549,7 @@ static int i915_dispatch_flip(struct drm_device * dev)
 	if (!master_priv->sarea_priv)
 		return -EINVAL;
 
-	DRM_DEBUG_DRIVER(I915_DRV, "%s: page=%d pfCurrentPage=%d\n",
+	DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 			  __func__,
 			 dev_priv->current_page,
 			 master_priv->sarea_priv->pf_current_page);
@@ -633,8 +630,7 @@ static int i915_batchbuffer(struct drm_device *dev, void *data,
 		return -EINVAL;
 	}
 
-	DRM_DEBUG_DRIVER(I915_DRV,
-			"i915 batchbuffer, start %x used %d cliprects %d\n",
+	DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 			batch->start, batch->used, batch->num_cliprects);
 
 	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
@@ -681,8 +677,7 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data,
 	void *batch_data;
 	int ret;
 
-	DRM_DEBUG_DRIVER(I915_DRV,
-			"i915 cmdbuffer, buf %p sz %d cliprects %d\n",
+	DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 			cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 
 	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
@@ -735,7 +730,7 @@ static int i915_flip_bufs(struct drm_device *dev, void *data,
 {
 	int ret;
 
-	DRM_DEBUG_DRIVER(I915_DRV, "%s\n", __func__);
+	DRM_DEBUG_DRIVER("%s\n", __func__);
 
 	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 
@@ -778,7 +773,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
 		value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 		break;
 	default:
-		DRM_DEBUG_DRIVER(I915_DRV, "Unknown parameter %d\n",
+		DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 					param->param);
 		return -EINVAL;
 	}
@@ -819,7 +814,7 @@ static int i915_setparam(struct drm_device *dev, void *data,
 		dev_priv->fence_reg_start = param->value;
 		break;
 	default:
-		DRM_DEBUG_DRIVER(I915_DRV, "unknown parameter %d\n",
+		DRM_DEBUG_DRIVER("unknown parameter %d\n",
 					param->param);
 		return -EINVAL;
 	}
@@ -846,7 +841,7 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
 		return 0;
 	}
 
-	DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
+	DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
 
 	dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
 
@@ -868,9 +863,9 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
 
 	memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 	I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
-	DRM_DEBUG_DRIVER(I915_DRV, "load hws HWS_PGA with gfx mem 0x%x\n",
+	DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
 				dev_priv->status_gfx_addr);
-	DRM_DEBUG_DRIVER(I915_DRV, "load hws at %p\n",
+	DRM_DEBUG_DRIVER("load hws at %p\n",
 				dev_priv->hw_status_page);
 	return 0;
 }
@@ -1310,7 +1305,7 @@ int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
 {
 	struct drm_i915_file_private *i915_file_priv;
 
-	DRM_DEBUG_DRIVER(I915_DRV, "\n");
+	DRM_DEBUG_DRIVER("\n");
 	i915_file_priv = (struct drm_i915_file_private *)
 	    kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
 
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 9ab38efffec..b59c65d19d8 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -38,8 +38,6 @@
 #include "i915_drv.h"
 #include <linux/acpi.h>
 
-#define I915_LVDS "i915_lvds"
-
 /*
  * the following four scaling options are defined.
  * #define DRM_MODE_SCALE_NON_GPU	0
@@ -673,8 +671,7 @@ static int intel_lvds_set_property(struct drm_connector *connector,
 		struct drm_crtc *crtc = connector->encoder->crtc;
 		struct intel_lvds_priv *lvds_priv = intel_output->dev_priv;
 		if (value == DRM_MODE_SCALE_NON_GPU) {
-			DRM_DEBUG_KMS(I915_LVDS,
-					"non_GPU property is unsupported\n");
+			DRM_DEBUG_KMS("non_GPU property is unsupported\n");
 			return 0;
 		}
 		if (lvds_priv->fitting_mode == value) {
@@ -731,8 +728,7 @@ static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
 
 static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
 {
-	DRM_DEBUG_KMS(I915_LVDS,
-		      "Skipping LVDS initialization for %s\n", id->ident);
+	DRM_DEBUG_KMS("Skipping LVDS initialization for %s\n", id->ident);
 	return 1;
 }
 
@@ -1013,7 +1009,7 @@ out:
 	return;
 
 failed:
-	DRM_DEBUG_KMS(I915_LVDS, "No LVDS modes found, disabling.\n");
+	DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
 	if (intel_output->ddc_bus)
 		intel_i2c_destroy(intel_output->ddc_bus);
 	drm_connector_cleanup(connector);
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 4f0c30948bc..abef69c8a49 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -36,7 +36,6 @@
 #include "intel_sdvo_regs.h"
 
 #undef SDVO_DEBUG
-#define I915_SDVO	"i915_sdvo"
 struct intel_sdvo_priv {
 	u8 slave_addr;
 
@@ -178,7 +177,7 @@ static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr,
 		return true;
 	}
 
-	DRM_DEBUG("i2c transfer returned %d\n", ret);
+	DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
 	return false;
 }
 
@@ -288,7 +287,7 @@ static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd,
 	struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
 	int i;
 
-	DRM_DEBUG_KMS(I915_SDVO, "%s: W: %02X ",
+	DRM_DEBUG_KMS("%s: W: %02X ",
 				SDVO_NAME(sdvo_priv), cmd);
 	for (i = 0; i < args_len; i++)
 		DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
@@ -341,7 +340,7 @@ static void intel_sdvo_debug_response(struct intel_output *intel_output,
 	struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
 	int i;
 
-	DRM_DEBUG_KMS(I915_SDVO, "%s: R: ", SDVO_NAME(sdvo_priv));
+	DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(sdvo_priv));
 	for (i = 0; i < response_len; i++)
 		DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
 	for (; i < 8; i++)
@@ -658,10 +657,10 @@ static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output)
 	status = intel_sdvo_read_response(intel_output, &response, 1);
 
 	if (status != SDVO_CMD_STATUS_SUCCESS) {
-		DRM_DEBUG("Couldn't get SDVO clock rate multiplier\n");
+		DRM_DEBUG_KMS("Couldn't get SDVO clock rate multiplier\n");
 		return SDVO_CLOCK_RATE_MULT_1X;
 	} else {
-		DRM_DEBUG("Current clock rate multiplier: %d\n", response);
+		DRM_DEBUG_KMS("Current clock rate multiplier: %d\n", response);
 	}
 
 	return response;
@@ -942,14 +941,14 @@ static void intel_sdvo_set_tv_format(struct intel_output *output)
 	format = &sdvo_priv->tv_format;
 	memset(&unset, 0, sizeof(unset));
 	if (memcmp(format, &unset, sizeof(*format))) {
-		DRM_DEBUG("%s: Choosing default TV format of NTSC-M\n",
+		DRM_DEBUG_KMS("%s: Choosing default TV format of NTSC-M\n",
 				SDVO_NAME(sdvo_priv));
 		format->ntsc_m = 1;
 		intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, format,
 				sizeof(*format));
 		status = intel_sdvo_read_response(output, NULL, 0);
 		if (status != SDVO_CMD_STATUS_SUCCESS)
-			DRM_DEBUG("%s: Failed to set TV format\n",
+			DRM_DEBUG_KMS("%s: Failed to set TV format\n",
 					SDVO_NAME(sdvo_priv));
 	}
 }
@@ -1220,8 +1219,8 @@ static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
 		 * a given it the status is a success, we succeeded.
 		 */
 		if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
-			DRM_DEBUG("First %s output reported failure to sync\n",
-				   SDVO_NAME(sdvo_priv));
+			DRM_DEBUG_KMS("First %s output reported failure to "
+					"sync\n", SDVO_NAME(sdvo_priv));
 		}
 
 		if (0)
@@ -1316,8 +1315,8 @@ static void intel_sdvo_restore(struct drm_connector *connector)
 			intel_wait_for_vblank(dev);
 		status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2);
 		if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
-			DRM_DEBUG("First %s output reported failure to sync\n",
-				   SDVO_NAME(sdvo_priv));
+			DRM_DEBUG_KMS("First %s output reported failure to "
+					"sync\n", SDVO_NAME(sdvo_priv));
 	}
 
 	intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs);
@@ -1395,7 +1394,7 @@ int intel_sdvo_supports_hotplug(struct drm_connector *connector)
 	u8 response[2];
 	u8 status;
 	struct intel_output *intel_output;
-	DRM_DEBUG("\n");
+	DRM_DEBUG_KMS("\n");
 
 	if (!connector)
 		return 0;
@@ -1460,7 +1459,7 @@ static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connect
 	intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
 	status = intel_sdvo_read_response(intel_output, &response, 2);
 
-	DRM_DEBUG("SDVO response %d %d\n", response[0], response[1]);
+	DRM_DEBUG_KMS("SDVO response %d %d\n", response[0], response[1]);
 
 	if (status != SDVO_CMD_STATUS_SUCCESS)
 		return connector_status_unknown;
@@ -1905,8 +1904,7 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
 	/* Read the regs to test if we can talk to the device */
 	for (i = 0; i < 0x40; i++) {
 		if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) {
-			DRM_DEBUG_KMS(I915_SDVO,
-					"No SDVO device found on SDVO%c\n",
+			DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
 					output_device == SDVOB ? 'B' : 'C');
 			goto err_i2c;
 		}
@@ -1989,8 +1987,7 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
 
 		sdvo_priv->controlled_output = 0;
 		memcpy (bytes, &sdvo_priv->caps.output_flags, 2);
-		DRM_DEBUG_KMS(I915_SDVO,
-				"%s: Unknown SDVO output type (0x%02x%02x)\n",
+		DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
 				  SDVO_NAME(sdvo_priv),
 				  bytes[0], bytes[1]);
 		encoder_type = DRM_MODE_ENCODER_NONE;
@@ -2022,7 +2019,7 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
 					       &sdvo_priv->pixel_clock_max);
 
 
-	DRM_DEBUG_KMS(I915_SDVO, "%s device VID/DID: %02X:%02X.%02X, "
+	DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
 			"clock range %dMHz - %dMHz, "
 			"input 1: %c, input 2: %c, "
 			"output 1: %c, output 2: %c\n",
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index 45b67d9c39c..edbdb02a7a3 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -174,19 +174,19 @@ extern void drm_ut_debug_printk(unsigned int request_level,
 					__func__, fmt, ##args);		\
 	} while (0)
 
-#define DRM_DEBUG_DRIVER(prefix, fmt, args...)				\
+#define DRM_DEBUG_DRIVER(fmt, args...)					\
 	do {								\
-		drm_ut_debug_printk(DRM_UT_DRIVER, prefix,		\
+		drm_ut_debug_printk(DRM_UT_DRIVER, DRM_NAME,		\
 					__func__, fmt, ##args);		\
 	} while (0)
-#define DRM_DEBUG_KMS(prefix, fmt, args...)				\
+#define DRM_DEBUG_KMS(fmt, args...)				\
 	do {								\
-		drm_ut_debug_printk(DRM_UT_KMS, prefix, 		\
+		drm_ut_debug_printk(DRM_UT_KMS, DRM_NAME, 		\
 					 __func__, fmt, ##args);	\
 	} while (0)
-#define DRM_DEBUG_MODE(prefix, fmt, args...)				\
+#define DRM_DEBUG_MODE(fmt, args...)				\
 	do {								\
-		drm_ut_debug_printk(DRM_UT_MODE, prefix, 		\
+		drm_ut_debug_printk(DRM_UT_MODE, DRM_NAME, 		\
 					 __func__, fmt, ##args);	\
 	} while (0)
 #define DRM_LOG(fmt, args...)						\
@@ -210,9 +210,9 @@ extern void drm_ut_debug_printk(unsigned int request_level,
 					NULL, fmt, ##args);		\
 	} while (0)
 #else
-#define DRM_DEBUG_DRIVER(prefix, fmt, args...) do { } while (0)
-#define DRM_DEBUG_KMS(prefix, fmt, args...)	do { } while (0)
-#define DRM_DEBUG_MODE(prefix, fmt, args...)	do { } while (0)
+#define DRM_DEBUG_DRIVER(fmt, args...) do { } while (0)
+#define DRM_DEBUG_KMS(fmt, args...)	do { } while (0)
+#define DRM_DEBUG_MODE(fmt, args...)	do { } while (0)
 #define DRM_DEBUG(fmt, arg...)		 do { } while (0)
 #define DRM_LOG(fmt, arg...)		do { } while (0)
 #define DRM_LOG_KMS(fmt, args...) do { } while (0)
-- 
cgit v1.2.3


From f940f37f022f7392ab81a35516222cbd46110b42 Mon Sep 17 00:00:00 2001
From: Zhao Yakui <yakui.zhao@intel.com>
Date: Mon, 20 Jul 2009 13:48:05 +0800
Subject: drm: Remove the macro defintion of DRM_DEBUG_MODE

Two macro definitions of DRM_DEBUG_KMS/MODE can be used to add the debug
info related with KMS. It is confusing.
So remove the macro definition of DRM_DEBUG_MODE. Instead it can be replaced
by the DRM_DEBUG_KMS.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_modes.c | 4 ++--
 include/drm/drmP.h          | 7 -------
 2 files changed, 2 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 5eca2d5c5f2..6b4d2dc3cdd 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -52,7 +52,7 @@
  */
 void drm_mode_debug_printmodeline(struct drm_display_mode *mode)
 {
-	DRM_DEBUG_MODE("Modeline %d:\"%s\" %d %d %d %d %d %d %d %d %d %d "
+	DRM_DEBUG_KMS("Modeline %d:\"%s\" %d %d %d %d %d %d %d %d %d %d "
 			"0x%x 0x%x\n",
 		mode->base.id, mode->name, mode->vrefresh, mode->clock,
 		mode->hdisplay, mode->hsync_start,
@@ -818,7 +818,7 @@ void drm_mode_prune_invalid(struct drm_device *dev,
 			list_del(&mode->head);
 			if (verbose) {
 				drm_mode_debug_printmodeline(mode);
-				DRM_DEBUG_MODE("Not using %s mode %d\n",
+				DRM_DEBUG_KMS("Not using %s mode %d\n",
 					mode->name, mode->status);
 			}
 			drm_mode_destroy(dev, mode);
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index edbdb02a7a3..6513d16cd02 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -88,7 +88,6 @@ struct drm_device;
 #define DRM_UT_CORE 		0x01
 #define DRM_UT_DRIVER		0x02
 #define DRM_UT_KMS		0x04
-#define DRM_UT_MODE		0x08
 
 extern void drm_ut_debug_printk(unsigned int request_level,
 				const char *prefix,
@@ -184,11 +183,6 @@ extern void drm_ut_debug_printk(unsigned int request_level,
 		drm_ut_debug_printk(DRM_UT_KMS, DRM_NAME, 		\
 					 __func__, fmt, ##args);	\
 	} while (0)
-#define DRM_DEBUG_MODE(fmt, args...)				\
-	do {								\
-		drm_ut_debug_printk(DRM_UT_MODE, DRM_NAME, 		\
-					 __func__, fmt, ##args);	\
-	} while (0)
 #define DRM_LOG(fmt, args...)						\
 	do {								\
 		drm_ut_debug_printk(DRM_UT_CORE, NULL,			\
@@ -212,7 +206,6 @@ extern void drm_ut_debug_printk(unsigned int request_level,
 #else
 #define DRM_DEBUG_DRIVER(fmt, args...) do { } while (0)
 #define DRM_DEBUG_KMS(fmt, args...)	do { } while (0)
-#define DRM_DEBUG_MODE(fmt, args...)	do { } while (0)
 #define DRM_DEBUG(fmt, arg...)		 do { } while (0)
 #define DRM_LOG(fmt, arg...)		do { } while (0)
 #define DRM_LOG_KMS(fmt, args...) do { } while (0)
-- 
cgit v1.2.3


From 87fdff81cd2d770f0adc742e21eb5e062ad20def Mon Sep 17 00:00:00 2001
From: Zhao Yakui <yakui.zhao@intel.com>
Date: Mon, 20 Jul 2009 13:48:06 +0800
Subject: DRM: Add the explanation about DRM debug level

Add the explanation about DRM debug level in the drmP header file. This is to
explain how/where to use the different DRM debug level.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 include/drm/drmP.h | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index 6513d16cd02..e0f1c1fee58 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -88,6 +88,37 @@ struct drm_device;
 #define DRM_UT_CORE 		0x01
 #define DRM_UT_DRIVER		0x02
 #define DRM_UT_KMS		0x04
+/*
+ * Three debug levels are defined.
+ * drm_core, drm_driver, drm_kms
+ * drm_core level can be used in the generic drm code. For example:
+ * 	drm_ioctl, drm_mm, drm_memory
+ * The macro definiton of DRM_DEBUG is used.
+ * 	DRM_DEBUG(fmt, args...)
+ * 	The debug info by using the DRM_DEBUG can be obtained by adding
+ * 	the boot option of "drm.debug=1".
+ *
+ * drm_driver level can be used in the specific drm driver. It is used
+ * to add the debug info related with the drm driver. For example:
+ * i915_drv, i915_dma, i915_gem, radeon_drv,
+ * 	The macro definition of DRM_DEBUG_DRIVER can be used.
+ * 	DRM_DEBUG_DRIVER(fmt, args...)
+ * 	The debug info by using the DRM_DEBUG_DRIVER can be obtained by
+ * 	adding the boot option of "drm.debug=0x02"
+ *
+ * drm_kms level can be used in the KMS code related with specific drm driver.
+ * It is used to add the debug info related with KMS mode. For example:
+ * the connector/crtc ,
+ * 	The macro definition of DRM_DEBUG_KMS can be used.
+ * 	DRM_DEBUG_KMS(fmt, args...)
+ * 	The debug info by using the DRM_DEBUG_KMS can be obtained by
+ * 	adding the boot option of "drm.debug=0x04"
+ *
+ * If we add the boot option of "drm.debug=0x06", we can get the debug info by
+ * using the DRM_DEBUG_KMS and DRM_DEBUG_DRIVER.
+ * If we add the boot option of "drm.debug=0x05", we can get the debug info by
+ * using the DRM_DEBUG_KMS and DRM_DEBUG.
+ */
 
 extern void drm_ut_debug_printk(unsigned int request_level,
 				const char *prefix,
-- 
cgit v1.2.3


From 58367ed65f30128d8b763bf4c1fb942da49ade15 Mon Sep 17 00:00:00 2001
From: Zhao Yakui <yakui.zhao@intel.com>
Date: Mon, 20 Jul 2009 13:48:07 +0800
Subject: drm: Add the debug info in generic drm mode by using DRM_DEBUG_KMS

Add the debug info in generic drm mode by using DRM_DEBUG_KMS

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_crtc.c        | 29 ++++++++++++++------------
 drivers/gpu/drm/drm_crtc_helper.c | 44 +++++++++++++++++++++------------------
 2 files changed, 40 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 8fab7890a36..9c758305472 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -1060,7 +1060,7 @@ int drm_mode_getresources(struct drm_device *dev, void *data,
 		if (file_priv->master->minor->type == DRM_MINOR_CONTROL) {
 			list_for_each_entry(crtc, &dev->mode_config.crtc_list,
 					    head) {
-				DRM_DEBUG("CRTC ID is %d\n", crtc->base.id);
+				DRM_DEBUG_KMS("CRTC ID is %d\n", crtc->base.id);
 				if (put_user(crtc->base.id, crtc_id + copied)) {
 					ret = -EFAULT;
 					goto out;
@@ -1088,7 +1088,7 @@ int drm_mode_getresources(struct drm_device *dev, void *data,
 			list_for_each_entry(encoder,
 					    &dev->mode_config.encoder_list,
 					    head) {
-				DRM_DEBUG("ENCODER ID is %d\n",
+				DRM_DEBUG_KMS("ENCODER ID is %d\n",
 					  encoder->base.id);
 				if (put_user(encoder->base.id, encoder_id +
 					     copied)) {
@@ -1119,7 +1119,7 @@ int drm_mode_getresources(struct drm_device *dev, void *data,
 			list_for_each_entry(connector,
 					    &dev->mode_config.connector_list,
 					    head) {
-				DRM_DEBUG("CONNECTOR ID is %d\n",
+				DRM_DEBUG_KMS("CONNECTOR ID is %d\n",
 					  connector->base.id);
 				if (put_user(connector->base.id,
 					     connector_id + copied)) {
@@ -1143,7 +1143,7 @@ int drm_mode_getresources(struct drm_device *dev, void *data,
 	}
 	card_res->count_connectors = connector_count;
 
-	DRM_DEBUG("Counted %d %d %d\n", card_res->count_crtcs,
+	DRM_DEBUG_KMS("Counted %d %d %d\n", card_res->count_crtcs,
 		  card_res->count_connectors, card_res->count_encoders);
 
 out:
@@ -1246,7 +1246,7 @@ int drm_mode_getconnector(struct drm_device *dev, void *data,
 
 	memset(&u_mode, 0, sizeof(struct drm_mode_modeinfo));
 
-	DRM_DEBUG("connector id %d:\n", out_resp->connector_id);
+	DRM_DEBUG_KMS("connector id %d:\n", out_resp->connector_id);
 
 	mutex_lock(&dev->mode_config.mutex);
 
@@ -1422,7 +1422,7 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,
 	obj = drm_mode_object_find(dev, crtc_req->crtc_id,
 				   DRM_MODE_OBJECT_CRTC);
 	if (!obj) {
-		DRM_DEBUG("Unknown CRTC ID %d\n", crtc_req->crtc_id);
+		DRM_DEBUG_KMS("Unknown CRTC ID %d\n", crtc_req->crtc_id);
 		ret = -EINVAL;
 		goto out;
 	}
@@ -1435,7 +1435,8 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,
 			list_for_each_entry(crtcfb,
 					    &dev->mode_config.crtc_list, head) {
 				if (crtcfb == crtc) {
-					DRM_DEBUG("Using current fb for setmode\n");
+					DRM_DEBUG_KMS("Using current fb for "
+							"setmode\n");
 					fb = crtc->fb;
 				}
 			}
@@ -1443,7 +1444,8 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,
 			obj = drm_mode_object_find(dev, crtc_req->fb_id,
 						   DRM_MODE_OBJECT_FB);
 			if (!obj) {
-				DRM_DEBUG("Unknown FB ID%d\n", crtc_req->fb_id);
+				DRM_DEBUG_KMS("Unknown FB ID%d\n",
+						crtc_req->fb_id);
 				ret = -EINVAL;
 				goto out;
 			}
@@ -1456,13 +1458,13 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,
 	}
 
 	if (crtc_req->count_connectors == 0 && mode) {
-		DRM_DEBUG("Count connectors is 0 but mode set\n");
+		DRM_DEBUG_KMS("Count connectors is 0 but mode set\n");
 		ret = -EINVAL;
 		goto out;
 	}
 
 	if (crtc_req->count_connectors > 0 && !mode && !fb) {
-		DRM_DEBUG("Count connectors is %d but no mode or fb set\n",
+		DRM_DEBUG_KMS("Count connectors is %d but no mode or fb set\n",
 			  crtc_req->count_connectors);
 		ret = -EINVAL;
 		goto out;
@@ -1495,7 +1497,8 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,
 			obj = drm_mode_object_find(dev, out_id,
 						   DRM_MODE_OBJECT_CONNECTOR);
 			if (!obj) {
-				DRM_DEBUG("Connector id %d unknown\n", out_id);
+				DRM_DEBUG_KMS("Connector id %d unknown\n",
+						out_id);
 				ret = -EINVAL;
 				goto out;
 			}
@@ -1528,7 +1531,7 @@ int drm_mode_cursor_ioctl(struct drm_device *dev,
 	struct drm_crtc *crtc;
 	int ret = 0;
 
-	DRM_DEBUG("\n");
+	DRM_DEBUG_KMS("\n");
 
 	if (!req->flags) {
 		DRM_ERROR("no operation set\n");
@@ -1538,7 +1541,7 @@ int drm_mode_cursor_ioctl(struct drm_device *dev,
 	mutex_lock(&dev->mode_config.mutex);
 	obj = drm_mode_object_find(dev, req->crtc_id, DRM_MODE_OBJECT_CRTC);
 	if (!obj) {
-		DRM_DEBUG("Unknown CRTC ID %d\n", req->crtc_id);
+		DRM_DEBUG_KMS("Unknown CRTC ID %d\n", req->crtc_id);
 		ret = -EINVAL;
 		goto out;
 	}
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index 3da9cfa3184..9cd84513258 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -94,7 +94,7 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector,
 	int count = 0;
 	int mode_flags = 0;
 
-	DRM_DEBUG("%s\n", drm_get_connector_name(connector));
+	DRM_DEBUG_KMS("%s\n", drm_get_connector_name(connector));
 	/* set all modes to the unverified state */
 	list_for_each_entry_safe(mode, t, &connector->modes, head)
 		mode->status = MODE_UNVERIFIED;
@@ -102,7 +102,7 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector,
 	connector->status = connector->funcs->detect(connector);
 
 	if (connector->status == connector_status_disconnected) {
-		DRM_DEBUG("%s is disconnected\n",
+		DRM_DEBUG_KMS("%s is disconnected\n",
 			  drm_get_connector_name(connector));
 		/* TODO set EDID to NULL */
 		return 0;
@@ -138,7 +138,8 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector,
 
 	drm_mode_sort(&connector->modes);
 
-	DRM_DEBUG("Probed modes for %s\n", drm_get_connector_name(connector));
+	DRM_DEBUG_KMS("Probed modes for %s\n",
+				drm_get_connector_name(connector));
 	list_for_each_entry_safe(mode, t, &connector->modes, head) {
 		mode->vrefresh = drm_mode_vrefresh(mode);
 
@@ -184,12 +185,13 @@ static void drm_helper_add_std_modes(struct drm_device *dev,
 		drm_mode_list_concat(&connector->probed_modes,
 				     &connector->modes);
 
-		DRM_DEBUG("Adding mode %s to %s\n", stdmode->name,
+		DRM_DEBUG_KMS("Adding mode %s to %s\n", stdmode->name,
 			  drm_get_connector_name(connector));
 	}
 	drm_mode_sort(&connector->modes);
 
-	DRM_DEBUG("Added std modes on %s\n", drm_get_connector_name(connector));
+	DRM_DEBUG_KMS("Added std modes on %s\n",
+			drm_get_connector_name(connector));
 	list_for_each_entry_safe(mode, t, &connector->modes, head) {
 		mode->vrefresh = drm_mode_vrefresh(mode);
 
@@ -312,7 +314,7 @@ static void drm_enable_connectors(struct drm_device *dev, bool *enabled)
 
 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 		enabled[i] = drm_connector_enabled(connector, true);
-		DRM_DEBUG("connector %d enabled? %s\n", connector->base.id,
+		DRM_DEBUG_KMS("connector %d enabled? %s\n", connector->base.id,
 			  enabled[i] ? "yes" : "no");
 		any_enabled |= enabled[i];
 		i++;
@@ -342,7 +344,7 @@ static bool drm_target_preferred(struct drm_device *dev,
 			continue;
 		}
 
-		DRM_DEBUG("looking for preferred mode on connector %d\n",
+		DRM_DEBUG_KMS("looking for preferred mode on connector %d\n",
 			  connector->base.id);
 
 		modes[i] = drm_has_preferred_mode(connector, width, height);
@@ -351,7 +353,7 @@ static bool drm_target_preferred(struct drm_device *dev,
 			list_for_each_entry(modes[i], &connector->modes, head)
 				break;
 		}
-		DRM_DEBUG("found mode %s\n", modes[i] ? modes[i]->name :
+		DRM_DEBUG_KMS("found mode %s\n", modes[i] ? modes[i]->name :
 			  "none");
 		i++;
 	}
@@ -452,7 +454,7 @@ static void drm_setup_crtcs(struct drm_device *dev)
 	int width, height;
 	int i, ret;
 
-	DRM_DEBUG("\n");
+	DRM_DEBUG_KMS("\n");
 
 	width = dev->mode_config.max_width;
 	height = dev->mode_config.max_height;
@@ -475,7 +477,7 @@ static void drm_setup_crtcs(struct drm_device *dev)
 	if (!ret)
 		DRM_ERROR("Unable to find initial modes\n");
 
-	DRM_DEBUG("picking CRTCs for %dx%d config\n", width, height);
+	DRM_DEBUG_KMS("picking CRTCs for %dx%d config\n", width, height);
 
 	drm_pick_crtcs(dev, crtcs, modes, 0, width, height);
 
@@ -490,7 +492,7 @@ static void drm_setup_crtcs(struct drm_device *dev)
 		}
 
 		if (mode && crtc) {
-			DRM_DEBUG("desired mode %s set on crtc %d\n",
+			DRM_DEBUG_KMS("desired mode %s set on crtc %d\n",
 				  mode->name, crtc->base.id);
 			crtc->desired_mode = mode;
 			connector->encoder->crtc = crtc;
@@ -713,7 +715,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
 	struct drm_crtc_helper_funcs *crtc_funcs;
 	int ret = 0;
 
-	DRM_DEBUG("\n");
+	DRM_DEBUG_KMS("\n");
 
 	if (!set)
 		return -EINVAL;
@@ -726,7 +728,8 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
 
 	crtc_funcs = set->crtc->helper_private;
 
-	DRM_DEBUG("crtc: %p %d fb: %p connectors: %p num_connectors: %d (x, y) (%i, %i)\n",
+	DRM_DEBUG_KMS("crtc: %p %d fb: %p connectors: %p num_connectors:"
+			" %d (x, y) (%i, %i)\n",
 		  set->crtc, set->crtc->base.id, set->fb, set->connectors,
 		  (int)set->num_connectors, set->x, set->y);
 
@@ -756,7 +759,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
 	if (set->crtc->fb != set->fb) {
 		/* If we have no fb then treat it as a full mode set */
 		if (set->crtc->fb == NULL) {
-			DRM_DEBUG("crtc has no fb, full mode set\n");
+			DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
 			mode_changed = true;
 		} else if ((set->fb->bits_per_pixel !=
 			 set->crtc->fb->bits_per_pixel) ||
@@ -770,7 +773,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
 		fb_changed = true;
 
 	if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
-		DRM_DEBUG("modes are different, full mode set\n");
+		DRM_DEBUG_KMS("modes are different, full mode set\n");
 		drm_mode_debug_printmodeline(&set->crtc->mode);
 		drm_mode_debug_printmodeline(set->mode);
 		mode_changed = true;
@@ -796,7 +799,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
 		}
 
 		if (new_encoder != connector->encoder) {
-			DRM_DEBUG("encoder changed, full mode switch\n");
+			DRM_DEBUG_KMS("encoder changed, full mode switch\n");
 			mode_changed = true;
 			connector->encoder = new_encoder;
 		}
@@ -831,11 +834,11 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
 			goto fail_set_mode;
 		}
 		if (new_crtc != connector->encoder->crtc) {
-			DRM_DEBUG("crtc changed, full mode switch\n");
+			DRM_DEBUG_KMS("crtc changed, full mode switch\n");
 			mode_changed = true;
 			connector->encoder->crtc = new_crtc;
 		}
-		DRM_DEBUG("setting connector %d crtc to %p\n",
+		DRM_DEBUG_KMS("setting connector %d crtc to %p\n",
 			  connector->base.id, new_crtc);
 	}
 
@@ -848,7 +851,8 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
 		set->crtc->fb = set->fb;
 		set->crtc->enabled = (set->mode != NULL);
 		if (set->mode != NULL) {
-			DRM_DEBUG("attempting to set mode from userspace\n");
+			DRM_DEBUG_KMS("attempting to set mode from"
+					" userspace\n");
 			drm_mode_debug_printmodeline(set->mode);
 			if (!drm_crtc_helper_set_mode(set->crtc, set->mode,
 						      set->x, set->y,
@@ -901,7 +905,7 @@ EXPORT_SYMBOL(drm_crtc_helper_set_config);
 
 bool drm_helper_plugged_event(struct drm_device *dev)
 {
-	DRM_DEBUG("\n");
+	DRM_DEBUG_KMS("\n");
 
 	drm_helper_probe_connector_modes(dev, dev->mode_config.max_width,
 					 dev->mode_config.max_height);
-- 
cgit v1.2.3


From 2066facca4c7dfe9f5068ece0200a4dbf10f49e1 Mon Sep 17 00:00:00 2001
From: Francisco Jerez <currojerez@riseup.net>
Date: Sun, 2 Aug 2009 04:19:17 +0200
Subject: drm/kms: slave encoder interface.

Define some helper functions to make easier to detach a KMS encoder
implementation from the drm module of the GPU it's used in. This is
mainly useful for some external I2C encoders known to be present on
cards with GPUs from several different manufacturers.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/Makefile            |   2 +-
 drivers/gpu/drm/drm_encoder_slave.c | 116 ++++++++++++++++++++++++++
 include/drm/drm_encoder_slave.h     | 162 ++++++++++++++++++++++++++++++++++++
 3 files changed, 279 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/drm_encoder_slave.c
 create mode 100644 include/drm/drm_encoder_slave.h

diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index fe23f29f7cb..5f0aec4f082 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -11,7 +11,7 @@ drm-y       :=	drm_auth.o drm_bufs.o drm_cache.o \
 		drm_agpsupport.o drm_scatter.o ati_pcigart.o drm_pci.o \
 		drm_sysfs.o drm_hashtab.o drm_sman.o drm_mm.o \
 		drm_crtc.o drm_crtc_helper.o drm_modes.o drm_edid.o \
-		drm_info.o drm_debugfs.o
+		drm_info.o drm_debugfs.o drm_encoder_slave.o
 
 drm-$(CONFIG_COMPAT) += drm_ioc32.o
 
diff --git a/drivers/gpu/drm/drm_encoder_slave.c b/drivers/gpu/drm/drm_encoder_slave.c
new file mode 100644
index 00000000000..6ffd600ccfa
--- /dev/null
+++ b/drivers/gpu/drm/drm_encoder_slave.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2009 Francisco Jerez.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include <drm/drm_encoder_slave.h>
+
+/**
+ * drm_i2c_encoder_init - Initialize an I2C slave encoder
+ * @dev:	DRM device.
+ * @encoder:    Encoder to be attached to the I2C device. You aren't
+ *		required to have called drm_encoder_init() before.
+ * @adap:	I2C adapter that will be used to communicate with
+ *		the device.
+ * @info:	Information that will be used to create the I2C device.
+ *		Required fields are @addr and @type.
+ *
+ * Create an I2C device on the specified bus (the module containing its
+ * driver is transparently loaded) and attach it to the specified
+ * &drm_encoder_slave. The @slave_funcs field will be initialized with
+ * the hooks provided by the slave driver.
+ *
+ * Returns 0 on success or a negative errno on failure, in particular,
+ * -ENODEV is returned when no matching driver is found.
+ */
+int drm_i2c_encoder_init(struct drm_device *dev,
+			 struct drm_encoder_slave *encoder,
+			 struct i2c_adapter *adap,
+			 const struct i2c_board_info *info)
+{
+	char modalias[sizeof(I2C_MODULE_PREFIX)
+		      + I2C_NAME_SIZE];
+	struct module *module = NULL;
+	struct i2c_client *client;
+	struct drm_i2c_encoder_driver *encoder_drv;
+	int err = 0;
+
+	snprintf(modalias, sizeof(modalias),
+		 "%s%s", I2C_MODULE_PREFIX, info->type);
+	request_module(modalias);
+
+	client = i2c_new_device(adap, info);
+	if (!client) {
+		err = -ENOMEM;
+		goto fail;
+	}
+
+	if (!client->driver) {
+		err = -ENODEV;
+		goto fail_unregister;
+	}
+
+	module = client->driver->driver.owner;
+	if (!try_module_get(module)) {
+		err = -ENODEV;
+		goto fail_unregister;
+	}
+
+	encoder->bus_priv = client;
+
+	encoder_drv = to_drm_i2c_encoder_driver(client->driver);
+
+	err = encoder_drv->encoder_init(client, dev, encoder);
+	if (err)
+		goto fail_unregister;
+
+	return 0;
+
+fail_unregister:
+	i2c_unregister_device(client);
+	module_put(module);
+fail:
+	return err;
+}
+EXPORT_SYMBOL(drm_i2c_encoder_init);
+
+/**
+ * drm_i2c_encoder_destroy - Unregister the I2C device backing an encoder
+ * @drm_encoder:	Encoder to be unregistered.
+ *
+ * This should be called from the @destroy method of an I2C slave
+ * encoder driver once I2C access is no longer needed.
+ */
+void drm_i2c_encoder_destroy(struct drm_encoder *drm_encoder)
+{
+	struct drm_encoder_slave *encoder = to_encoder_slave(drm_encoder);
+	struct i2c_client *client = drm_i2c_encoder_get_client(drm_encoder);
+	struct module *module = client->driver->driver.owner;
+
+	i2c_unregister_device(client);
+	encoder->bus_priv = NULL;
+
+	module_put(module);
+}
+EXPORT_SYMBOL(drm_i2c_encoder_destroy);
diff --git a/include/drm/drm_encoder_slave.h b/include/drm/drm_encoder_slave.h
new file mode 100644
index 00000000000..821ec40c17d
--- /dev/null
+++ b/include/drm/drm_encoder_slave.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2009 Francisco Jerez.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __DRM_ENCODER_SLAVE_H__
+#define __DRM_ENCODER_SLAVE_H__
+
+#include <drm/drmP.h>
+#include <drm/drm_crtc.h>
+
+/**
+ * struct drm_encoder_slave_funcs - Entry points exposed by a slave encoder driver
+ * @set_config:	Initialize any encoder-specific modesetting parameters.
+ *		The meaning of the @params parameter is implementation
+ *		dependent. It will usually be a structure with DVO port
+ *		data format settings or timings. It's not required for
+ *		the new parameters to take effect until the next mode
+ *		is set.
+ *
+ * Most of its members are analogous to the function pointers in
+ * &drm_encoder_helper_funcs and they can optionally be used to
+ * initialize the latter. Connector-like methods (e.g. @get_modes and
+ * @set_property) will typically be wrapped around and only be called
+ * if the encoder is the currently selected one for the connector.
+ */
+struct drm_encoder_slave_funcs {
+	void (*set_config)(struct drm_encoder *encoder,
+			   void *params);
+
+	void (*destroy)(struct drm_encoder *encoder);
+	void (*dpms)(struct drm_encoder *encoder, int mode);
+	void (*save)(struct drm_encoder *encoder);
+	void (*restore)(struct drm_encoder *encoder);
+	bool (*mode_fixup)(struct drm_encoder *encoder,
+			   struct drm_display_mode *mode,
+			   struct drm_display_mode *adjusted_mode);
+	int (*mode_valid)(struct drm_encoder *encoder,
+			  struct drm_display_mode *mode);
+	void (*mode_set)(struct drm_encoder *encoder,
+			 struct drm_display_mode *mode,
+			 struct drm_display_mode *adjusted_mode);
+
+	enum drm_connector_status (*detect)(struct drm_encoder *encoder,
+					    struct drm_connector *connector);
+	int (*get_modes)(struct drm_encoder *encoder,
+			 struct drm_connector *connector);
+	int (*create_resources)(struct drm_encoder *encoder,
+				 struct drm_connector *connector);
+	int (*set_property)(struct drm_encoder *encoder,
+			    struct drm_connector *connector,
+			    struct drm_property *property,
+			    uint64_t val);
+
+};
+
+/**
+ * struct drm_encoder_slave - Slave encoder struct
+ * @base: DRM encoder object.
+ * @slave_funcs: Slave encoder callbacks.
+ * @slave_priv: Slave encoder private data.
+ * @bus_priv: Bus specific data.
+ *
+ * A &drm_encoder_slave has two sets of callbacks, @slave_funcs and the
+ * ones in @base. The former are never actually called by the common
+ * CRTC code, it's just a convenience for splitting the encoder
+ * functions in an upper, GPU-specific layer and a (hopefully)
+ * GPU-agnostic lower layer: It's the GPU driver responsibility to
+ * call the slave methods when appropriate.
+ *
+ * drm_i2c_encoder_init() provides a way to get an implementation of
+ * this.
+ */
+struct drm_encoder_slave {
+	struct drm_encoder base;
+
+	struct drm_encoder_slave_funcs *slave_funcs;
+	void *slave_priv;
+	void *bus_priv;
+};
+#define to_encoder_slave(x) container_of((x), struct drm_encoder_slave, base)
+
+int drm_i2c_encoder_init(struct drm_device *dev,
+			 struct drm_encoder_slave *encoder,
+			 struct i2c_adapter *adap,
+			 const struct i2c_board_info *info);
+
+
+/**
+ * struct drm_i2c_encoder_driver
+ *
+ * Describes a device driver for an encoder connected to the GPU
+ * through an I2C bus. In addition to the entry points in @i2c_driver
+ * an @encoder_init function should be provided. It will be called to
+ * give the driver an opportunity to allocate any per-encoder data
+ * structures and to initialize the @slave_funcs and (optionally)
+ * @slave_priv members of @encoder.
+ */
+struct drm_i2c_encoder_driver {
+	struct i2c_driver i2c_driver;
+
+	int (*encoder_init)(struct i2c_client *client,
+			    struct drm_device *dev,
+			    struct drm_encoder_slave *encoder);
+
+};
+#define to_drm_i2c_encoder_driver(x) container_of((x),			\
+						  struct drm_i2c_encoder_driver, \
+						  i2c_driver)
+
+/**
+ * drm_i2c_encoder_get_client - Get the I2C client corresponding to an encoder
+ */
+static inline struct i2c_client *drm_i2c_encoder_get_client(struct drm_encoder *encoder)
+{
+	return (struct i2c_client *)to_encoder_slave(encoder)->bus_priv;
+}
+
+/**
+ * drm_i2c_encoder_register - Register an I2C encoder driver
+ * @owner:	Module containing the driver.
+ * @driver:	Driver to be registered.
+ */
+static inline int drm_i2c_encoder_register(struct module *owner,
+					   struct drm_i2c_encoder_driver *driver)
+{
+	return i2c_register_driver(owner, &driver->i2c_driver);
+}
+
+/**
+ * drm_i2c_encoder_unregister - Unregister an I2C encoder driver
+ * @driver:	Driver to be unregistered.
+ */
+static inline void drm_i2c_encoder_unregister(struct drm_i2c_encoder_driver *driver)
+{
+	return i2c_del_driver(&driver->i2c_driver);
+}
+
+void drm_i2c_encoder_destroy(struct drm_encoder *encoder);
+
+#endif
-- 
cgit v1.2.3


From 74bd3c26b90f39b9dcc05c471333da8998572b5d Mon Sep 17 00:00:00 2001
From: Francisco Jerez <currojerez@riseup.net>
Date: Sun, 2 Aug 2009 04:19:18 +0200
Subject: drm: Define DRM_MODE_CONNECTOR_TV

The existing TV connector types are often unsuitable either because
there is no way to probe them until they're actually plugged in or
because they can change during run time (e.g. 7-pin DIN connectors
that behave as S-Video, Component, Composite or SCART depending on the
adaptor plugged in).

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_crtc.c  | 1 +
 drivers/gpu/drm/drm_sysfs.c | 3 +++
 include/drm/drm_mode.h      | 1 +
 3 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 9c758305472..c7ab80b45e3 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -146,6 +146,7 @@ static struct drm_conn_prop_enum_list drm_connector_enum_list[] =
 	{ DRM_MODE_CONNECTOR_DisplayPort, "DisplayPort", 0 },
 	{ DRM_MODE_CONNECTOR_HDMIA, "HDMI Type A", 0 },
 	{ DRM_MODE_CONNECTOR_HDMIB, "HDMI Type B", 0 },
+	{ DRM_MODE_CONNECTOR_TV, "TV", 0 },
 };
 
 static struct drm_prop_enum_list drm_encoder_enum_list[] =
diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c
index 85ec31b3ff0..adc179459c2 100644
--- a/drivers/gpu/drm/drm_sysfs.c
+++ b/drivers/gpu/drm/drm_sysfs.c
@@ -247,6 +247,7 @@ static ssize_t subconnector_show(struct device *device,
 		case DRM_MODE_CONNECTOR_Composite:
 		case DRM_MODE_CONNECTOR_SVIDEO:
 		case DRM_MODE_CONNECTOR_Component:
+		case DRM_MODE_CONNECTOR_TV:
 			prop = dev->mode_config.tv_subconnector_property;
 			is_tv = 1;
 			break;
@@ -287,6 +288,7 @@ static ssize_t select_subconnector_show(struct device *device,
 		case DRM_MODE_CONNECTOR_Composite:
 		case DRM_MODE_CONNECTOR_SVIDEO:
 		case DRM_MODE_CONNECTOR_Component:
+		case DRM_MODE_CONNECTOR_TV:
 			prop = dev->mode_config.tv_select_subconnector_property;
 			is_tv = 1;
 			break;
@@ -385,6 +387,7 @@ int drm_sysfs_connector_add(struct drm_connector *connector)
 		case DRM_MODE_CONNECTOR_Composite:
 		case DRM_MODE_CONNECTOR_SVIDEO:
 		case DRM_MODE_CONNECTOR_Component:
+		case DRM_MODE_CONNECTOR_TV:
 			for (i = 0; i < ARRAY_SIZE(connector_attrs_opt1); i++) {
 				ret = device_create_file(&connector->kdev, &connector_attrs_opt1[i]);
 				if (ret)
diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h
index ae304cc73c9..c51e9f528c8 100644
--- a/include/drm/drm_mode.h
+++ b/include/drm/drm_mode.h
@@ -155,6 +155,7 @@ struct drm_mode_get_encoder {
 #define DRM_MODE_CONNECTOR_DisplayPort	10
 #define DRM_MODE_CONNECTOR_HDMIA	11
 #define DRM_MODE_CONNECTOR_HDMIB	12
+#define DRM_MODE_CONNECTOR_TV		13
 
 struct drm_mode_get_connector {
 
-- 
cgit v1.2.3


From aeaa1ad3ff32be833680e484d99ec29d892da1ff Mon Sep 17 00:00:00 2001
From: Francisco Jerez <currojerez@riseup.net>
Date: Sun, 2 Aug 2009 04:19:19 +0200
Subject: drm: Define DRM_MODE_SUBCONNECTOR_SCART

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_crtc.c | 2 ++
 include/drm/drm_mode.h     | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index c7ab80b45e3..ed53c5c37ac 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -108,6 +108,7 @@ static struct drm_prop_enum_list drm_tv_select_enum_list[] =
 	{ DRM_MODE_SUBCONNECTOR_Composite, "Composite" }, /* TV-out */
 	{ DRM_MODE_SUBCONNECTOR_SVIDEO,    "SVIDEO"    }, /* TV-out */
 	{ DRM_MODE_SUBCONNECTOR_Component, "Component" }, /* TV-out */
+	{ DRM_MODE_SUBCONNECTOR_SCART,     "SCART"     }, /* TV-out */
 };
 
 DRM_ENUM_NAME_FN(drm_get_tv_select_name, drm_tv_select_enum_list)
@@ -118,6 +119,7 @@ static struct drm_prop_enum_list drm_tv_subconnector_enum_list[] =
 	{ DRM_MODE_SUBCONNECTOR_Composite, "Composite" }, /* TV-out */
 	{ DRM_MODE_SUBCONNECTOR_SVIDEO,    "SVIDEO"    }, /* TV-out */
 	{ DRM_MODE_SUBCONNECTOR_Component, "Component" }, /* TV-out */
+	{ DRM_MODE_SUBCONNECTOR_SCART,     "SCART"     }, /* TV-out */
 };
 
 DRM_ENUM_NAME_FN(drm_get_tv_subconnector_name,
diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h
index c51e9f528c8..616aeb42b77 100644
--- a/include/drm/drm_mode.h
+++ b/include/drm/drm_mode.h
@@ -141,6 +141,7 @@ struct drm_mode_get_encoder {
 #define DRM_MODE_SUBCONNECTOR_Composite	5
 #define DRM_MODE_SUBCONNECTOR_SVIDEO	6
 #define DRM_MODE_SUBCONNECTOR_Component	8
+#define DRM_MODE_SUBCONNECTOR_SCART	9
 
 #define DRM_MODE_CONNECTOR_Unknown	0
 #define DRM_MODE_CONNECTOR_VGA		1
-- 
cgit v1.2.3


From b6b7902e54c7e8abbc213d8bdc290350c00ccfe5 Mon Sep 17 00:00:00 2001
From: Francisco Jerez <currojerez@riseup.net>
Date: Sun, 2 Aug 2009 04:19:20 +0200
Subject: drm: Define some new standard TV properties.

Namely "brightness", "contrast" and "flicker reduction".

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_crtc.c | 18 ++++++++++++++++++
 include/drm/drm_crtc.h     |  3 +++
 2 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index ed53c5c37ac..a8c831134fc 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -718,6 +718,24 @@ int drm_mode_create_tv_properties(struct drm_device *dev, int num_modes,
 		drm_property_add_enum(dev->mode_config.tv_mode_property, i,
 				      i, modes[i]);
 
+	dev->mode_config.tv_brightness_property =
+		drm_property_create(dev, DRM_MODE_PROP_RANGE,
+				    "brightness", 2);
+	dev->mode_config.tv_brightness_property->values[0] = 0;
+	dev->mode_config.tv_brightness_property->values[1] = 100;
+
+	dev->mode_config.tv_contrast_property =
+		drm_property_create(dev, DRM_MODE_PROP_RANGE,
+				    "contrast", 2);
+	dev->mode_config.tv_contrast_property->values[0] = 0;
+	dev->mode_config.tv_contrast_property->values[1] = 100;
+
+	dev->mode_config.tv_flicker_reduction_property =
+		drm_property_create(dev, DRM_MODE_PROP_RANGE,
+				    "flicker reduction", 2);
+	dev->mode_config.tv_flicker_reduction_property->values[0] = 0;
+	dev->mode_config.tv_flicker_reduction_property->values[1] = 100;
+
 	return 0;
 }
 EXPORT_SYMBOL(drm_mode_create_tv_properties);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 125994d8ac0..5f2cc0ca4c7 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -572,6 +572,9 @@ struct drm_mode_config {
 	struct drm_property *tv_right_margin_property;
 	struct drm_property *tv_top_margin_property;
 	struct drm_property *tv_bottom_margin_property;
+	struct drm_property *tv_brightness_property;
+	struct drm_property *tv_contrast_property;
+	struct drm_property *tv_flicker_reduction_property;
 
 	/* Optional properties */
 	struct drm_property *scaling_mode_property;
-- 
cgit v1.2.3


From 841b4117b30d544690fceb952037b1cddf14783f Mon Sep 17 00:00:00 2001
From: Francisco Jerez <currojerez@riseup.net>
Date: Wed, 12 Aug 2009 02:30:09 +0200
Subject: drm: Fix drm_cvt_mode() for interlaced modes.

The calculated vdisplay was half the right value.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_modes.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 6b4d2dc3cdd..9e54925a760 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -146,7 +146,7 @@ struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay,
 	if (margins)
 		vmargin = vdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000;
 
-	drm_mode->vdisplay = vdisplay_rnd + 2 * vmargin;
+	drm_mode->vdisplay = vdisplay + 2 * vmargin;
 
 	/* Interlaced */
 	if (interlaced)
-- 
cgit v1.2.3


From a75f0236292a5fca65f26efedca48bd07db1834d Mon Sep 17 00:00:00 2001
From: Francisco Jerez <currojerez@riseup.net>
Date: Wed, 12 Aug 2009 02:30:10 +0200
Subject: drm: Add more standard TV properties.

Overscan, saturation, hue. Used in the nouveau driver for GPUs with
integrated TV encoders.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_crtc.c | 18 ++++++++++++++++++
 include/drm/drm_crtc.h     |  3 +++
 2 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index a8c831134fc..362a538cded 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -736,6 +736,24 @@ int drm_mode_create_tv_properties(struct drm_device *dev, int num_modes,
 	dev->mode_config.tv_flicker_reduction_property->values[0] = 0;
 	dev->mode_config.tv_flicker_reduction_property->values[1] = 100;
 
+	dev->mode_config.tv_overscan_property =
+		drm_property_create(dev, DRM_MODE_PROP_RANGE,
+				    "overscan", 2);
+	dev->mode_config.tv_overscan_property->values[0] = 0;
+	dev->mode_config.tv_overscan_property->values[1] = 100;
+
+	dev->mode_config.tv_saturation_property =
+		drm_property_create(dev, DRM_MODE_PROP_RANGE,
+				    "saturation", 2);
+	dev->mode_config.tv_saturation_property->values[0] = 0;
+	dev->mode_config.tv_saturation_property->values[1] = 100;
+
+	dev->mode_config.tv_hue_property =
+		drm_property_create(dev, DRM_MODE_PROP_RANGE,
+				    "hue", 2);
+	dev->mode_config.tv_hue_property->values[0] = 0;
+	dev->mode_config.tv_hue_property->values[1] = 100;
+
 	return 0;
 }
 EXPORT_SYMBOL(drm_mode_create_tv_properties);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 5f2cc0ca4c7..db92a83f8ca 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -575,6 +575,9 @@ struct drm_mode_config {
 	struct drm_property *tv_brightness_property;
 	struct drm_property *tv_contrast_property;
 	struct drm_property *tv_flicker_reduction_property;
+	struct drm_property *tv_overscan_property;
+	struct drm_property *tv_saturation_property;
+	struct drm_property *tv_hue_property;
 
 	/* Optional properties */
 	struct drm_property *scaling_mode_property;
-- 
cgit v1.2.3


From cfcf4738cd6b5d7bed1473acad76d6430cf1fb0a Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 13 Aug 2009 13:31:54 +1000
Subject: drm: fixup include file in drm_encoder_slave

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_encoder_slave.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_encoder_slave.c b/drivers/gpu/drm/drm_encoder_slave.c
index 6ffd600ccfa..f0184696edf 100644
--- a/drivers/gpu/drm/drm_encoder_slave.c
+++ b/drivers/gpu/drm/drm_encoder_slave.c
@@ -24,7 +24,7 @@
  *
  */
 
-#include <drm/drm_encoder_slave.h>
+#include "drm_encoder_slave.h"
 
 /**
  * drm_i2c_encoder_init - Initialize an I2C slave encoder
-- 
cgit v1.2.3


From 453a7d46dca88704ed88b364c445ff55680a8557 Mon Sep 17 00:00:00 2001
From: Jesse Barnes <jbarnes@virtuousgeek.org>
Date: Wed, 19 Aug 2009 15:51:55 +1000
Subject: drm: remove root requirement from DRM_IOCTL_SET_VERSION (+
 DRM_IOCTL_AUTH_MAGIC)

Just a DRM_MASTER flag is sufficient here, though maybe this call is
totally deprecated anyway (xf86-video-intel still calls it though).

(airlied: drop ioctl auth_magic as discussed on mailing list also)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_drv.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index b39d7bfc0c9..a75ca63deea 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -63,12 +63,12 @@ static struct drm_ioctl_desc drm_ioctls[] = {
 	DRM_IOCTL_DEF(DRM_IOCTL_GET_MAP, drm_getmap, 0),
 	DRM_IOCTL_DEF(DRM_IOCTL_GET_CLIENT, drm_getclient, 0),
 	DRM_IOCTL_DEF(DRM_IOCTL_GET_STATS, drm_getstats, 0),
-	DRM_IOCTL_DEF(DRM_IOCTL_SET_VERSION, drm_setversion, DRM_MASTER|DRM_ROOT_ONLY),
+	DRM_IOCTL_DEF(DRM_IOCTL_SET_VERSION, drm_setversion, DRM_MASTER),
 
 	DRM_IOCTL_DEF(DRM_IOCTL_SET_UNIQUE, drm_setunique, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 	DRM_IOCTL_DEF(DRM_IOCTL_BLOCK, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 	DRM_IOCTL_DEF(DRM_IOCTL_UNBLOCK, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
-	DRM_IOCTL_DEF(DRM_IOCTL_AUTH_MAGIC, drm_authmagic, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+	DRM_IOCTL_DEF(DRM_IOCTL_AUTH_MAGIC, drm_authmagic, DRM_AUTH|DRM_MASTER),
 
 	DRM_IOCTL_DEF(DRM_IOCTL_ADD_MAP, drm_addmap_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 	DRM_IOCTL_DEF(DRM_IOCTL_RM_MAP, drm_rmmap_ioctl, DRM_AUTH),
-- 
cgit v1.2.3


From 776f3360de6ed246e973577828f725681120fd7a Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Wed, 19 Aug 2009 15:56:37 +1000
Subject: drm: fixup includes in encoder slave header files.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 include/drm/drm_encoder_slave.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/drm/drm_encoder_slave.h b/include/drm/drm_encoder_slave.h
index 821ec40c17d..e5e5c94ca92 100644
--- a/include/drm/drm_encoder_slave.h
+++ b/include/drm/drm_encoder_slave.h
@@ -27,8 +27,8 @@
 #ifndef __DRM_ENCODER_SLAVE_H__
 #define __DRM_ENCODER_SLAVE_H__
 
-#include <drm/drmP.h>
-#include <drm/drm_crtc.h>
+#include "drmP.h"
+#include "drm_crtc.h"
 
 /**
  * struct drm_encoder_slave_funcs - Entry points exposed by a slave encoder driver
-- 
cgit v1.2.3


From 53bd83899f5ba6b0da8f5ef976129273854a72d4 Mon Sep 17 00:00:00 2001
From: Jesse Barnes <jbarnes@virtuousgeek.org>
Date: Wed, 1 Jul 2009 10:04:40 -0700
Subject: drm: clarify scaling property names

Now that we're using the scaling property in the Intel driver I noticed
that the names were a bit confusing.  I've corrected them according to
our discussion on IRC and the mailing list, though I've left out
potential new additions for a new scaling property with an integer (or
two) for the scaling factor.  None of the drivers implement that today,
but if someone wants to do it, I think it could be done with the
addition of a single new type and a new property to describe the
scaling factor in the X and Y directions.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Acked-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_crtc.c        |  8 ++++----
 drivers/gpu/drm/i915/intel_lvds.c | 14 +++-----------
 include/drm/drm_mode.h            |  9 +++++----
 3 files changed, 12 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 362a538cded..39a6bc69d22 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -68,10 +68,10 @@ DRM_ENUM_NAME_FN(drm_get_dpms_name, drm_dpms_enum_list)
  */
 static struct drm_prop_enum_list drm_scaling_mode_enum_list[] =
 {
-	{ DRM_MODE_SCALE_NON_GPU, "Non-GPU" },
-	{ DRM_MODE_SCALE_FULLSCREEN, "Fullscreen" },
-	{ DRM_MODE_SCALE_NO_SCALE, "No scale" },
-	{ DRM_MODE_SCALE_ASPECT, "Aspect" },
+	{ DRM_MODE_SCALE_NONE, "None" },
+	{ DRM_MODE_SCALE_FULLSCREEN, "Full" },
+	{ DRM_MODE_SCALE_CENTER, "Center" },
+	{ DRM_MODE_SCALE_ASPECT, "Full aspect" },
 };
 
 static struct drm_prop_enum_list drm_dithering_mode_enum_list[] =
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index b59c65d19d8..5df486fbe05 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -38,14 +38,6 @@
 #include "i915_drv.h"
 #include <linux/acpi.h>
 
-/*
- * the following four scaling options are defined.
- * #define DRM_MODE_SCALE_NON_GPU	0
- * #define DRM_MODE_SCALE_FULLSCREEN	1
- * #define DRM_MODE_SCALE_NO_SCALE	2
- * #define DRM_MODE_SCALE_ASPECT	3
- */
-
 /* Private structure for the integrated LVDS support */
 struct intel_lvds_priv {
 	int fitting_mode;
@@ -334,7 +326,7 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
 	I915_WRITE(BCLRPAT_B, 0);
 
 	switch (lvds_priv->fitting_mode) {
-	case DRM_MODE_SCALE_NO_SCALE:
+	case DRM_MODE_SCALE_CENTER:
 		/*
 		 * For centered modes, we have to calculate border widths &
 		 * heights and modify the values programmed into the CRTC.
@@ -670,8 +662,8 @@ static int intel_lvds_set_property(struct drm_connector *connector,
 				connector->encoder) {
 		struct drm_crtc *crtc = connector->encoder->crtc;
 		struct intel_lvds_priv *lvds_priv = intel_output->dev_priv;
-		if (value == DRM_MODE_SCALE_NON_GPU) {
-			DRM_DEBUG_KMS("non_GPU property is unsupported\n");
+		if (value == DRM_MODE_SCALE_NONE) {
+			DRM_DEBUG_KMS("no scaling not supported\n");
 			return 0;
 		}
 		if (lvds_priv->fitting_mode == value) {
diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h
index 616aeb42b77..1f908416aed 100644
--- a/include/drm/drm_mode.h
+++ b/include/drm/drm_mode.h
@@ -68,10 +68,11 @@
 #define DRM_MODE_DPMS_OFF	3
 
 /* Scaling mode options */
-#define DRM_MODE_SCALE_NON_GPU		0
-#define DRM_MODE_SCALE_FULLSCREEN	1
-#define DRM_MODE_SCALE_NO_SCALE		2
-#define DRM_MODE_SCALE_ASPECT		3
+#define DRM_MODE_SCALE_NONE		0 /* Unmodified timing (display or
+					     software can still scale) */
+#define DRM_MODE_SCALE_FULLSCREEN	1 /* Full screen, ignore aspect */
+#define DRM_MODE_SCALE_CENTER		2 /* Centered, no scaling */
+#define DRM_MODE_SCALE_ASPECT		3 /* Full screen, preserve aspect */
 
 /* Dithering mode options */
 #define DRM_MODE_DITHERING_OFF	0
-- 
cgit v1.2.3


From 949ef70e2d1a5c12178875f513df34fc85d91a38 Mon Sep 17 00:00:00 2001
From: Pekka Paalanen <pq@iki.fi>
Date: Mon, 17 Aug 2009 19:49:19 +0300
Subject: drm/kms: no need to return void value (encoder)

Cc: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Pekka Paalanen <pq@iki.fi>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 include/drm/drm_encoder_slave.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/drm/drm_encoder_slave.h b/include/drm/drm_encoder_slave.h
index e5e5c94ca92..2f65633d28a 100644
--- a/include/drm/drm_encoder_slave.h
+++ b/include/drm/drm_encoder_slave.h
@@ -154,7 +154,7 @@ static inline int drm_i2c_encoder_register(struct module *owner,
  */
 static inline void drm_i2c_encoder_unregister(struct drm_i2c_encoder_driver *driver)
 {
-	return i2c_del_driver(&driver->i2c_driver);
+	i2c_del_driver(&driver->i2c_driver);
 }
 
 void drm_i2c_encoder_destroy(struct drm_encoder *encoder);
-- 
cgit v1.2.3


From a0724fcf829e5afb66159ef68cb16a805ea11b42 Mon Sep 17 00:00:00 2001
From: Pekka Paalanen <pq@iki.fi>
Date: Mon, 17 Aug 2009 01:18:38 +0300
Subject: drm/ttm: optimize bo_kmap_type values

A micro-optimization on the function ttm_kmap_obj_virtual().

By defining the values of enum ttm_bo_kmap_obj::bo_kmap_type to have a
bit indicating iomem, size of the function ttm_kmap_obj_virtual() will be
reduced by 16 bytes on x86_64 (gcc 4.1.2).

ttm_kmap_obj_virtual() may be heavily used, when buffer objects are
accessed via wrappers, that work for both kinds of memory addresses:
iomem cookies and kernel virtual.

Signed-off-by: Pekka Paalanen <pq@iki.fi>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 include/drm/ttm/ttm_bo_api.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h
index cd22ab4b495..99dc521aa1a 100644
--- a/include/drm/ttm/ttm_bo_api.h
+++ b/include/drm/ttm/ttm_bo_api.h
@@ -245,14 +245,15 @@ struct ttm_buffer_object {
  * premapped region.
  */
 
+#define TTM_BO_MAP_IOMEM_MASK 0x80
 struct ttm_bo_kmap_obj {
 	void *virtual;
 	struct page *page;
 	enum {
-		ttm_bo_map_iomap,
-		ttm_bo_map_vmap,
-		ttm_bo_map_kmap,
-		ttm_bo_map_premapped,
+		ttm_bo_map_iomap        = 1 | TTM_BO_MAP_IOMEM_MASK,
+		ttm_bo_map_vmap         = 2,
+		ttm_bo_map_kmap         = 3,
+		ttm_bo_map_premapped    = 4 | TTM_BO_MAP_IOMEM_MASK,
 	} bo_kmap_type;
 };
 
@@ -522,8 +523,7 @@ extern int ttm_bo_evict_mm(struct ttm_bo_device *bdev, unsigned mem_type);
 static inline void *ttm_kmap_obj_virtual(struct ttm_bo_kmap_obj *map,
 					 bool *is_iomem)
 {
-	*is_iomem = (map->bo_kmap_type == ttm_bo_map_iomap ||
-		     map->bo_kmap_type == ttm_bo_map_premapped);
+	*is_iomem = !!(map->bo_kmap_type & TTM_BO_MAP_IOMEM_MASK);
 	return map->virtual;
 }
 
-- 
cgit v1.2.3


From 327c225bd548bf7871f116a0baa5ebdac884e452 Mon Sep 17 00:00:00 2001
From: Thomas Hellstrom <thellstrom@vmware.com>
Date: Mon, 17 Aug 2009 16:28:37 +0200
Subject: drm: Enable drm drivers to add drm sysfs devices.

Export utility functions for drivers to add specialized devices in the
sysfs drm class subdirectory.

Initially this will be needed form TTM to add a virtual device that
handles power management.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Signed-off-by: Dave Airlie <airlied@linux.ie>
---
 drivers/gpu/drm/drm_sysfs.c | 25 +++++++++++++++++++++++++
 include/drm/drm_sysfs.h     | 12 ++++++++++++
 2 files changed, 37 insertions(+)
 create mode 100644 include/drm/drm_sysfs.h

diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c
index adc179459c2..de154556c40 100644
--- a/drivers/gpu/drm/drm_sysfs.c
+++ b/drivers/gpu/drm/drm_sysfs.c
@@ -16,6 +16,7 @@
 #include <linux/kdev_t.h>
 #include <linux/err.h>
 
+#include "drm_sysfs.h"
 #include "drm_core.h"
 #include "drmP.h"
 
@@ -515,3 +516,27 @@ void drm_sysfs_device_remove(struct drm_minor *minor)
 {
 	device_unregister(&minor->kdev);
 }
+
+
+/**
+ * drm_class_device_register - Register a struct device in the drm class.
+ *
+ * @dev: pointer to struct device to register.
+ *
+ * @dev should have all relevant members pre-filled with the exception
+ * of the class member. In particular, the device_type member must
+ * be set.
+ */
+
+int drm_class_device_register(struct device *dev)
+{
+	dev->class = drm_class;
+	return device_register(dev);
+}
+EXPORT_SYMBOL_GPL(drm_class_device_register);
+
+void drm_class_device_unregister(struct device *dev)
+{
+	return device_unregister(dev);
+}
+EXPORT_SYMBOL_GPL(drm_class_device_unregister);
diff --git a/include/drm/drm_sysfs.h b/include/drm/drm_sysfs.h
new file mode 100644
index 00000000000..1d8e033fde6
--- /dev/null
+++ b/include/drm/drm_sysfs.h
@@ -0,0 +1,12 @@
+#ifndef _DRM_SYSFS_H_
+#define _DRM_SYSFS_H_
+
+/**
+ * This minimalistic include file is intended for users (read TTM) that
+ * don't want to include the full drmP.h file.
+ */
+
+extern int drm_class_device_register(struct device *dev);
+extern void drm_class_device_unregister(struct device *dev);
+
+#endif
-- 
cgit v1.2.3


From e9840be8c23601285a70520b4898818f28ce8c2b Mon Sep 17 00:00:00 2001
From: Thomas Hellstrom <thellstrom@vmware.com>
Date: Tue, 18 Aug 2009 10:27:57 +0200
Subject: drm/ttm: Add a virtual ttm sysfs device.

The device directory will be the base directory of the
sysfs representation of other ttm subsystems.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Signed-off-by: Dave Airlie <airlied@linux.ie>
---
 drivers/gpu/drm/ttm/ttm_module.c | 58 +++++++++++++++++++++++++++++++++++++++-
 1 file changed, 57 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c
index 59ce8191d58..9a6edbfeaa9 100644
--- a/drivers/gpu/drm/ttm/ttm_module.c
+++ b/drivers/gpu/drm/ttm/ttm_module.c
@@ -29,16 +29,72 @@
  * 	    Jerome Glisse
  */
 #include <linux/module.h>
-#include <ttm/ttm_module.h>
+#include <linux/device.h>
+#include <linux/sched.h>
+#include "ttm/ttm_module.h"
+#include "drm_sysfs.h"
+
+static DECLARE_WAIT_QUEUE_HEAD(exit_q);
+atomic_t device_released;
+
+static struct device_type ttm_drm_class_type = {
+	.name = "ttm",
+	/**
+	 * Add pm ops here.
+	 */
+};
+
+static void ttm_drm_class_device_release(struct device *dev)
+{
+	atomic_set(&device_released, 1);
+	wake_up_all(&exit_q);
+}
+
+static struct device ttm_drm_class_device = {
+	.type = &ttm_drm_class_type,
+	.release = &ttm_drm_class_device_release
+};
+
+struct kobject *ttm_get_kobj(void)
+{
+	struct kobject *kobj = &ttm_drm_class_device.kobj;
+	BUG_ON(kobj == NULL);
+	return kobj;
+}
 
 static int __init ttm_init(void)
 {
+	int ret;
+
+	ret = dev_set_name(&ttm_drm_class_device, "ttm");
+	if (unlikely(ret != 0))
+		return ret;
+
 	ttm_global_init();
+
+	atomic_set(&device_released, 0);
+	ret = drm_class_device_register(&ttm_drm_class_device);
+	if (unlikely(ret != 0))
+		goto out_no_dev_reg;
+
 	return 0;
+out_no_dev_reg:
+	atomic_set(&device_released, 1);
+	wake_up_all(&exit_q);
+	ttm_global_release();
+	return ret;
 }
 
 static void __exit ttm_exit(void)
 {
+	drm_class_device_unregister(&ttm_drm_class_device);
+
+	/**
+	 * Refuse to unload until the TTM device is released.
+	 * Not sure this is 100% needed.
+	 */
+
+	wait_event(exit_q, atomic_read(&device_released) == 1);
 	ttm_global_release();
 }
 
-- 
cgit v1.2.3


From 5fd9cbad3a4ae82c83c55b9c621d156c326724ef Mon Sep 17 00:00:00 2001
From: Thomas Hellstrom <thellstrom@vmware.com>
Date: Mon, 17 Aug 2009 16:28:39 +0200
Subject: drm/ttm: Memory accounting rework.

Use inclusive zones to simplify accounting and its sysfs representation.
Use DMA32 accounting where applicable.

Add a sysfs interface to make the heuristically determined limits
readable and configurable.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Signed-off-by: Dave Airlie <airlied@linux.ie>
---
 drivers/gpu/drm/ttm/ttm_bo.c     |   6 +-
 drivers/gpu/drm/ttm/ttm_global.c |   4 +-
 drivers/gpu/drm/ttm/ttm_memory.c | 488 +++++++++++++++++++++++++++++++++------
 drivers/gpu/drm/ttm/ttm_tt.c     |  29 +--
 include/drm/ttm/ttm_memory.h     |  43 ++--
 include/drm/ttm/ttm_module.h     |   2 +
 6 files changed, 453 insertions(+), 119 deletions(-)

diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index c1c407f7cca..f16909ceec9 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -70,7 +70,7 @@ static void ttm_bo_release_list(struct kref *list_kref)
 	if (bo->destroy)
 		bo->destroy(bo);
 	else {
-		ttm_mem_global_free(bdev->mem_glob, bo->acc_size, false);
+		ttm_mem_global_free(bdev->mem_glob, bo->acc_size);
 		kfree(bo);
 	}
 }
@@ -1065,14 +1065,14 @@ int ttm_buffer_object_create(struct ttm_bo_device *bdev,
 
 	size_t acc_size =
 	    ttm_bo_size(bdev, (size + PAGE_SIZE - 1) >> PAGE_SHIFT);
-	ret = ttm_mem_global_alloc(mem_glob, acc_size, false, false, false);
+	ret = ttm_mem_global_alloc(mem_glob, acc_size, false, false);
 	if (unlikely(ret != 0))
 		return ret;
 
 	bo = kzalloc(sizeof(*bo), GFP_KERNEL);
 
 	if (unlikely(bo == NULL)) {
-		ttm_mem_global_free(mem_glob, acc_size, false);
+		ttm_mem_global_free(mem_glob, acc_size);
 		return -ENOMEM;
 	}
 
diff --git a/drivers/gpu/drm/ttm/ttm_global.c b/drivers/gpu/drm/ttm/ttm_global.c
index 0b14eb1972b..541744d00d3 100644
--- a/drivers/gpu/drm/ttm/ttm_global.c
+++ b/drivers/gpu/drm/ttm/ttm_global.c
@@ -71,7 +71,7 @@ int ttm_global_item_ref(struct ttm_global_reference *ref)
 
 	mutex_lock(&item->mutex);
 	if (item->refcount == 0) {
-		item->object = kmalloc(ref->size, GFP_KERNEL);
+		item->object = kzalloc(ref->size, GFP_KERNEL);
 		if (unlikely(item->object == NULL)) {
 			ret = -ENOMEM;
 			goto out_err;
@@ -89,7 +89,6 @@ int ttm_global_item_ref(struct ttm_global_reference *ref)
 	mutex_unlock(&item->mutex);
 	return 0;
 out_err:
-	kfree(item->object);
 	mutex_unlock(&item->mutex);
 	item->object = NULL;
 	return ret;
@@ -105,7 +104,6 @@ void ttm_global_item_unref(struct ttm_global_reference *ref)
 	BUG_ON(ref->object != item->object);
 	if (--item->refcount == 0) {
 		ref->release(ref);
-		kfree(item->object);
 		item->object = NULL;
 	}
 	mutex_unlock(&item->mutex);
diff --git a/drivers/gpu/drm/ttm/ttm_memory.c b/drivers/gpu/drm/ttm/ttm_memory.c
index 87323d4ff68..62fb5cf0899 100644
--- a/drivers/gpu/drm/ttm/ttm_memory.c
+++ b/drivers/gpu/drm/ttm/ttm_memory.c
@@ -26,15 +26,180 @@
  **************************************************************************/
 
 #include "ttm/ttm_memory.h"
+#include "ttm/ttm_module.h"
 #include <linux/spinlock.h>
 #include <linux/sched.h>
 #include <linux/wait.h>
 #include <linux/mm.h>
 #include <linux/module.h>
 
-#define TTM_PFX "[TTM] "
 #define TTM_MEMORY_ALLOC_RETRIES 4
 
+struct ttm_mem_zone {
+	struct kobject kobj;
+	struct ttm_mem_global *glob;
+	const char *name;
+	uint64_t zone_mem;
+	uint64_t emer_mem;
+	uint64_t max_mem;
+	uint64_t swap_limit;
+	uint64_t used_mem;
+};
+
+static struct attribute ttm_mem_sys = {
+	.name = "zone_memory",
+	.mode = S_IRUGO
+};
+static struct attribute ttm_mem_emer = {
+	.name = "emergency_memory",
+	.mode = S_IRUGO | S_IWUSR
+};
+static struct attribute ttm_mem_max = {
+	.name = "available_memory",
+	.mode = S_IRUGO | S_IWUSR
+};
+static struct attribute ttm_mem_swap = {
+	.name = "swap_limit",
+	.mode = S_IRUGO | S_IWUSR
+};
+static struct attribute ttm_mem_used = {
+	.name = "used_memory",
+	.mode = S_IRUGO
+};
+
+static void ttm_mem_zone_kobj_release(struct kobject *kobj)
+{
+	struct ttm_mem_zone *zone =
+		container_of(kobj, struct ttm_mem_zone, kobj);
+
+	printk(KERN_INFO TTM_PFX
+	       "Zone %7s: Used memory at exit: %llu kiB.\n",
+	       zone->name, (unsigned long long) zone->used_mem >> 10);
+	kfree(zone);
+}
+
+static ssize_t ttm_mem_zone_show(struct kobject *kobj,
+				 struct attribute *attr,
+				 char *buffer)
+{
+	struct ttm_mem_zone *zone =
+		container_of(kobj, struct ttm_mem_zone, kobj);
+	uint64_t val = 0;
+
+	spin_lock(&zone->glob->lock);
+	if (attr == &ttm_mem_sys)
+		val = zone->zone_mem;
+	else if (attr == &ttm_mem_emer)
+		val = zone->emer_mem;
+	else if (attr == &ttm_mem_max)
+		val = zone->max_mem;
+	else if (attr == &ttm_mem_swap)
+		val = zone->swap_limit;
+	else if (attr == &ttm_mem_used)
+		val = zone->used_mem;
+	spin_unlock(&zone->glob->lock);
+
+	return snprintf(buffer, PAGE_SIZE, "%llu\n",
+			(unsigned long long) val >> 10);
+}
+
+static void ttm_check_swapping(struct ttm_mem_global *glob);
+
+static ssize_t ttm_mem_zone_store(struct kobject *kobj,
+				  struct attribute *attr,
+				  const char *buffer,
+				  size_t size)
+{
+	struct ttm_mem_zone *zone =
+		container_of(kobj, struct ttm_mem_zone, kobj);
+	int chars;
+	unsigned long val;
+	uint64_t val64;
+
+	chars = sscanf(buffer, "%lu", &val);
+	if (chars == 0)
+		return size;
+
+	val64 = val;
+	val64 <<= 10;
+
+	spin_lock(&zone->glob->lock);
+	if (val64 > zone->zone_mem)
+		val64 = zone->zone_mem;
+	if (attr == &ttm_mem_emer) {
+		zone->emer_mem = val64;
+		if (zone->max_mem > val64)
+			zone->max_mem = val64;
+	} else if (attr == &ttm_mem_max) {
+		zone->max_mem = val64;
+		if (zone->emer_mem < val64)
+			zone->emer_mem = val64;
+	} else if (attr == &ttm_mem_swap)
+		zone->swap_limit = val64;
+	spin_unlock(&zone->glob->lock);
+
+	ttm_check_swapping(zone->glob);
+
+	return size;
+}
+
+static struct attribute *ttm_mem_zone_attrs[] = {
+	&ttm_mem_sys,
+	&ttm_mem_emer,
+	&ttm_mem_max,
+	&ttm_mem_swap,
+	&ttm_mem_used,
+	NULL
+};
+
+static struct sysfs_ops ttm_mem_zone_ops = {
+	.show = &ttm_mem_zone_show,
+	.store = &ttm_mem_zone_store
+};
+
+static struct kobj_type ttm_mem_zone_kobj_type = {
+	.release = &ttm_mem_zone_kobj_release,
+	.sysfs_ops = &ttm_mem_zone_ops,
+	.default_attrs = ttm_mem_zone_attrs,
+};
+
+static void ttm_mem_global_kobj_release(struct kobject *kobj)
+{
+	struct ttm_mem_global *glob =
+		container_of(kobj, struct ttm_mem_global, kobj);
+
+	kfree(glob);
+}
+
+static struct kobj_type ttm_mem_glob_kobj_type = {
+	.release = &ttm_mem_global_kobj_release,
+};
+
+static bool ttm_zones_above_swap_target(struct ttm_mem_global *glob,
+					bool from_wq, uint64_t extra)
+{
+	unsigned int i;
+	struct ttm_mem_zone *zone;
+	uint64_t target;
+
+	for (i = 0; i < glob->num_zones; ++i) {
+		zone = glob->zones[i];
+
+		if (from_wq)
+			target = zone->swap_limit;
+		else if (capable(CAP_SYS_ADMIN))
+			target = zone->emer_mem;
+		else
+			target = zone->max_mem;
+
+		target = (extra > target) ? 0ULL : target;
+
+		if (zone->used_mem > target)
+			return true;
+	}
+	return false;
+}
+
 /**
  * At this point we only support a single shrink callback.
  * Extend this if needed, perhaps using a linked list of callbacks.
@@ -42,34 +207,17 @@
  * many threads may try to swap out at any given time.
  */
 
-static void ttm_shrink(struct ttm_mem_global *glob, bool from_workqueue,
+static void ttm_shrink(struct ttm_mem_global *glob, bool from_wq,
 		       uint64_t extra)
 {
 	int ret;
 	struct ttm_mem_shrink *shrink;
-	uint64_t target;
-	uint64_t total_target;
 
 	spin_lock(&glob->lock);
 	if (glob->shrink == NULL)
 		goto out;
 
-	if (from_workqueue) {
-		target = glob->swap_limit;
-		total_target = glob->total_memory_swap_limit;
-	} else if (capable(CAP_SYS_ADMIN)) {
-		total_target = glob->emer_total_memory;
-		target = glob->emer_memory;
-	} else {
-		total_target = glob->max_total_memory;
-		target = glob->max_memory;
-	}
-
-	total_target = (extra >= total_target) ? 0 : total_target - extra;
-	target = (extra >= target) ? 0 : target - extra;
-
-	while (glob->used_memory > target ||
-	       glob->used_total_memory > total_target) {
+	while (ttm_zones_above_swap_target(glob, from_wq, extra)) {
 		shrink = glob->shrink;
 		spin_unlock(&glob->lock);
 		ret = shrink->do_shrink(shrink);
@@ -81,6 +229,8 @@ out:
 	spin_unlock(&glob->lock);
 }
 
+
+
 static void ttm_shrink_work(struct work_struct *work)
 {
 	struct ttm_mem_global *glob =
@@ -89,63 +239,178 @@ static void ttm_shrink_work(struct work_struct *work)
 	ttm_shrink(glob, true, 0ULL);
 }
 
+static int ttm_mem_init_kernel_zone(struct ttm_mem_global *glob,
+				    const struct sysinfo *si)
+{
+	struct ttm_mem_zone *zone = kzalloc(sizeof(*zone), GFP_KERNEL);
+	uint64_t mem;
+
+	if (unlikely(!zone))
+		return -ENOMEM;
+
+	mem = si->totalram - si->totalhigh;
+	mem *= si->mem_unit;
+
+	zone->name = "kernel";
+	zone->zone_mem = mem;
+	zone->max_mem = mem >> 1;
+	zone->emer_mem = (mem >> 1) + (mem >> 2);
+	zone->swap_limit = zone->max_mem - (mem >> 3);
+	zone->used_mem = 0;
+	zone->glob = glob;
+	glob->zone_kernel = zone;
+	glob->zones[glob->num_zones++] = zone;
+	kobject_init(&zone->kobj, &ttm_mem_zone_kobj_type);
+	return kobject_add(&zone->kobj, &glob->kobj, zone->name);
+}
+
+#ifdef CONFIG_HIGHMEM
+static int ttm_mem_init_highmem_zone(struct ttm_mem_global *glob,
+				     const struct sysinfo *si)
+{
+	struct ttm_mem_zone *zone = kzalloc(sizeof(*zone), GFP_KERNEL);
+	uint64_t mem;
+
+	if (unlikely(!zone))
+		return -ENOMEM;
+
+	if (si->totalhigh == 0)
+		return 0;
+
+	mem = si->totalram;
+	mem *= si->mem_unit;
+
+	zone->name = "highmem";
+	zone->zone_mem = mem;
+	zone->max_mem = mem >> 1;
+	zone->emer_mem = (mem >> 1) + (mem >> 2);
+	zone->swap_limit = zone->max_mem - (mem >> 3);
+	zone->used_mem = 0;
+	zone->glob = glob;
+	glob->zone_highmem = zone;
+	glob->zones[glob->num_zones++] = zone;
+	kobject_init(&zone->kobj, &ttm_mem_zone_kobj_type);
+	return kobject_add(&zone->kobj, &glob->kobj, zone->name);
+}
+#else
+static int ttm_mem_init_dma32_zone(struct ttm_mem_global *glob,
+				   const struct sysinfo *si)
+{
+	struct ttm_mem_zone *zone = kzalloc(sizeof(*zone), GFP_KERNEL);
+	uint64_t mem;
+
+	if (unlikely(!zone))
+		return -ENOMEM;
+
+	mem = si->totalram;
+	mem *= si->mem_unit;
+
+	/**
+	 * No special dma32 zone needed.
+	 */
+
+	if (mem <= ((uint64_t) 1ULL << 32))
+		return 0;
+
+	/*
+	 * Limit max dma32 memory to 4GB for now
+	 * until we can figure out how big this
+	 * zone really is.
+	 */
+
+	mem = ((uint64_t) 1ULL << 32);
+	zone->name = "dma32";
+	zone->zone_mem = mem;
+	zone->max_mem = mem >> 1;
+	zone->emer_mem = (mem >> 1) + (mem >> 2);
+	zone->swap_limit = zone->max_mem - (mem >> 3);
+	zone->used_mem = 0;
+	zone->glob = glob;
+	glob->zone_dma32 = zone;
+	glob->zones[glob->num_zones++] = zone;
+	kobject_init(&zone->kobj, &ttm_mem_zone_kobj_type);
+	return kobject_add(&zone->kobj, &glob->kobj, zone->name);
+}
+#endif
+
 int ttm_mem_global_init(struct ttm_mem_global *glob)
 {
 	struct sysinfo si;
-	uint64_t mem;
+	int ret;
+	int i;
+	struct ttm_mem_zone *zone;
 
 	spin_lock_init(&glob->lock);
 	glob->swap_queue = create_singlethread_workqueue("ttm_swap");
 	INIT_WORK(&glob->work, ttm_shrink_work);
 	init_waitqueue_head(&glob->queue);
+	kobject_init(&glob->kobj, &ttm_mem_glob_kobj_type);
+	ret = kobject_add(&glob->kobj,
+			  ttm_get_kobj(),
+			  "memory_accounting");
+	if (unlikely(ret != 0))
+		goto out_no_zone;
 
 	si_meminfo(&si);
 
-	mem = si.totalram - si.totalhigh;
-	mem *= si.mem_unit;
-
-	glob->max_memory = mem >> 1;
-	glob->emer_memory = (mem >> 1) + (mem >> 2);
-	glob->swap_limit = glob->max_memory - (mem >> 3);
-	glob->used_memory = 0;
-	glob->used_total_memory = 0;
-	glob->shrink = NULL;
-
-	mem = si.totalram;
-	mem *= si.mem_unit;
-
-	glob->max_total_memory = mem >> 1;
-	glob->emer_total_memory = (mem >> 1) + (mem >> 2);
-
-	glob->total_memory_swap_limit = glob->max_total_memory - (mem >> 3);
-
-	printk(KERN_INFO TTM_PFX "TTM available graphics memory: %llu MiB\n",
-	       glob->max_total_memory >> 20);
-	printk(KERN_INFO TTM_PFX "TTM available object memory: %llu MiB\n",
-	       glob->max_memory >> 20);
-
+	ret = ttm_mem_init_kernel_zone(glob, &si);
+	if (unlikely(ret != 0))
+		goto out_no_zone;
+#ifdef CONFIG_HIGHMEM
+	ret = ttm_mem_init_highmem_zone(glob, &si);
+	if (unlikely(ret != 0))
+		goto out_no_zone;
+#else
+	ret = ttm_mem_init_dma32_zone(glob, &si);
+	if (unlikely(ret != 0))
+		goto out_no_zone;
+#endif
+	for (i = 0; i < glob->num_zones; ++i) {
+		zone = glob->zones[i];
+		printk(KERN_INFO TTM_PFX
+		       "Zone %7s: Available graphics memory: %llu kiB.\n",
+		       zone->name, (unsigned long long) zone->max_mem >> 10);
+	}
 	return 0;
+out_no_zone:
+	ttm_mem_global_release(glob);
+	return ret;
 }
 EXPORT_SYMBOL(ttm_mem_global_init);
 
 void ttm_mem_global_release(struct ttm_mem_global *glob)
 {
-	printk(KERN_INFO TTM_PFX "Used total memory is %llu bytes.\n",
-	       (unsigned long long)glob->used_total_memory);
+	unsigned int i;
+	struct ttm_mem_zone *zone;
+
 	flush_workqueue(glob->swap_queue);
 	destroy_workqueue(glob->swap_queue);
 	glob->swap_queue = NULL;
+	for (i = 0; i < glob->num_zones; ++i) {
+		zone = glob->zones[i];
+		kobject_del(&zone->kobj);
+		kobject_put(&zone->kobj);
+	}
+	kobject_del(&glob->kobj);
+	kobject_put(&glob->kobj);
 }
 EXPORT_SYMBOL(ttm_mem_global_release);
 
-static inline void ttm_check_swapping(struct ttm_mem_global *glob)
+static void ttm_check_swapping(struct ttm_mem_global *glob)
 {
-	bool needs_swapping;
+	bool needs_swapping = false;
+	unsigned int i;
+	struct ttm_mem_zone *zone;
 
 	spin_lock(&glob->lock);
-	needs_swapping = (glob->used_memory > glob->swap_limit ||
-			  glob->used_total_memory >
-			  glob->total_memory_swap_limit);
+	for (i = 0; i < glob->num_zones; ++i) {
+		zone = glob->zones[i];
+		if (zone->used_mem > zone->swap_limit) {
+			needs_swapping = true;
+			break;
+		}
+	}
+
 	spin_unlock(&glob->lock);
 
 	if (unlikely(needs_swapping))
@@ -153,44 +418,60 @@ static inline void ttm_check_swapping(struct ttm_mem_global *glob)
 
 }
 
-void ttm_mem_global_free(struct ttm_mem_global *glob,
-			 uint64_t amount, bool himem)
+static void ttm_mem_global_free_zone(struct ttm_mem_global *glob,
+				     struct ttm_mem_zone *single_zone,
+				     uint64_t amount)
 {
+	unsigned int i;
+	struct ttm_mem_zone *zone;
+
 	spin_lock(&glob->lock);
-	glob->used_total_memory -= amount;
-	if (!himem)
-		glob->used_memory -= amount;
-	wake_up_all(&glob->queue);
+	for (i = 0; i < glob->num_zones; ++i) {
+		zone = glob->zones[i];
+		if (single_zone && zone != single_zone)
+			continue;
+		zone->used_mem -= amount;
+	}
 	spin_unlock(&glob->lock);
 }
 
+void ttm_mem_global_free(struct ttm_mem_global *glob,
+			 uint64_t amount)
+{
+	return ttm_mem_global_free_zone(glob, NULL, amount);
+}
+
 static int ttm_mem_global_reserve(struct ttm_mem_global *glob,
-				  uint64_t amount, bool himem, bool reserve)
+				  struct ttm_mem_zone *single_zone,
+				  uint64_t amount, bool reserve)
 {
 	uint64_t limit;
-	uint64_t lomem_limit;
 	int ret = -ENOMEM;
+	unsigned int i;
+	struct ttm_mem_zone *zone;
 
 	spin_lock(&glob->lock);
+	for (i = 0; i < glob->num_zones; ++i) {
+		zone = glob->zones[i];
+		if (single_zone && zone != single_zone)
+			continue;
 
-	if (capable(CAP_SYS_ADMIN)) {
-		limit = glob->emer_total_memory;
-		lomem_limit = glob->emer_memory;
-	} else {
-		limit = glob->max_total_memory;
-		lomem_limit = glob->max_memory;
-	}
+		limit = (capable(CAP_SYS_ADMIN)) ?
+			zone->emer_mem : zone->max_mem;
 
-	if (unlikely(glob->used_total_memory + amount > limit))
-		goto out_unlock;
-	if (unlikely(!himem && glob->used_memory + amount > lomem_limit))
-		goto out_unlock;
+		if (zone->used_mem > limit)
+			goto out_unlock;
+	}
 
 	if (reserve) {
-		glob->used_total_memory += amount;
-		if (!himem)
-			glob->used_memory += amount;
+		for (i = 0; i < glob->num_zones; ++i) {
+			zone = glob->zones[i];
+			if (single_zone && zone != single_zone)
+				continue;
+			zone->used_mem += amount;
+		}
 	}
+
 	ret = 0;
 out_unlock:
 	spin_unlock(&glob->lock);
@@ -199,12 +480,17 @@ out_unlock:
 	return ret;
 }
 
-int ttm_mem_global_alloc(struct ttm_mem_global *glob, uint64_t memory,
-			 bool no_wait, bool interruptible, bool himem)
+
+static int ttm_mem_global_alloc_zone(struct ttm_mem_global *glob,
+				     struct ttm_mem_zone *single_zone,
+				     uint64_t memory,
+				     bool no_wait, bool interruptible)
 {
 	int count = TTM_MEMORY_ALLOC_RETRIES;
 
-	while (unlikely(ttm_mem_global_reserve(glob, memory, himem, true)
+	while (unlikely(ttm_mem_global_reserve(glob,
+					       single_zone,
+					       memory, true)
 			!= 0)) {
 		if (no_wait)
 			return -ENOMEM;
@@ -216,6 +502,56 @@ int ttm_mem_global_alloc(struct ttm_mem_global *glob, uint64_t memory,
 	return 0;
 }
 
+int ttm_mem_global_alloc(struct ttm_mem_global *glob, uint64_t memory,
+			 bool no_wait, bool interruptible)
+{
+	/**
+	 * Normal allocations of kernel memory are registered in
+	 * all zones.
+	 */
+
+	return ttm_mem_global_alloc_zone(glob, NULL, memory, no_wait,
+					 interruptible);
+}
+
+int ttm_mem_global_alloc_page(struct ttm_mem_global *glob,
+			      struct page *page,
+			      bool no_wait, bool interruptible)
+{
+
+	struct ttm_mem_zone *zone = NULL;
+
+	/**
+	 * Page allocations may be registed in a single zone
+	 * only if highmem or !dma32.
+	 */
+
+#ifdef CONFIG_HIGHMEM
+	if (PageHighMem(page) && glob->zone_highmem != NULL)
+		zone = glob->zone_highmem;
+#else
+	if (glob->zone_dma32 && page_to_pfn(page) > 0x00100000UL)
+		zone = glob->zone_kernel;
+#endif
+	return ttm_mem_global_alloc_zone(glob, zone, PAGE_SIZE, no_wait,
+					 interruptible);
+}
+
+void ttm_mem_global_free_page(struct ttm_mem_global *glob, struct page *page)
+{
+	struct ttm_mem_zone *zone = NULL;
+
+#ifdef CONFIG_HIGHMEM
+	if (PageHighMem(page) && glob->zone_highmem != NULL)
+		zone = glob->zone_highmem;
+#else
+	if (glob->zone_dma32 && page_to_pfn(page) > 0x00100000UL)
+		zone = glob->zone_kernel;
+#endif
+	ttm_mem_global_free_zone(glob, zone, PAGE_SIZE);
+}
+
+
 size_t ttm_round_pot(size_t size)
 {
 	if ((size & (size - 1)) == 0)
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 75dc8bd2459..4e1e2566d51 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -166,7 +166,7 @@ static void ttm_tt_free_user_pages(struct ttm_tt *ttm)
 			set_page_dirty_lock(page);
 
 		ttm->pages[i] = NULL;
-		ttm_mem_global_free(ttm->bdev->mem_glob, PAGE_SIZE, false);
+		ttm_mem_global_free(ttm->bdev->mem_glob, PAGE_SIZE);
 		put_page(page);
 	}
 	ttm->state = tt_unpopulated;
@@ -187,21 +187,14 @@ static struct page *__ttm_tt_get_page(struct ttm_tt *ttm, int index)
 		if (!p)
 			return NULL;
 
-		if (PageHighMem(p)) {
-			ret =
-			    ttm_mem_global_alloc(mem_glob, PAGE_SIZE,
-						 false, false, true);
-			if (unlikely(ret != 0))
-				goto out_err;
+		ret = ttm_mem_global_alloc_page(mem_glob, p, false, false);
+		if (unlikely(ret != 0))
+			goto out_err;
+
+		if (PageHighMem(p))
 			ttm->pages[--ttm->first_himem_page] = p;
-		} else {
-			ret =
-			    ttm_mem_global_alloc(mem_glob, PAGE_SIZE,
-						 false, false, false);
-			if (unlikely(ret != 0))
-				goto out_err;
+		else
 			ttm->pages[++ttm->last_lomem_page] = p;
-		}
 	}
 	return p;
 out_err:
@@ -355,8 +348,8 @@ static void ttm_tt_free_alloced_pages(struct ttm_tt *ttm)
 				printk(KERN_ERR TTM_PFX
 				       "Erroneous page count. "
 				       "Leaking pages.\n");
-			ttm_mem_global_free(ttm->bdev->mem_glob, PAGE_SIZE,
-					    PageHighMem(cur_page));
+			ttm_mem_global_free_page(ttm->bdev->mem_glob,
+						 cur_page);
 			__free_page(cur_page);
 		}
 	}
@@ -411,7 +404,7 @@ int ttm_tt_set_user(struct ttm_tt *ttm,
 	 */
 
 	ret = ttm_mem_global_alloc(mem_glob, num_pages * PAGE_SIZE,
-				   false, false, false);
+				   false, false);
 	if (unlikely(ret != 0))
 		return ret;
 
@@ -422,7 +415,7 @@ int ttm_tt_set_user(struct ttm_tt *ttm,
 
 	if (ret != num_pages && write) {
 		ttm_tt_free_user_pages(ttm);
-		ttm_mem_global_free(mem_glob, num_pages * PAGE_SIZE, false);
+		ttm_mem_global_free(mem_glob, num_pages * PAGE_SIZE);
 		return -ENOMEM;
 	}
 
diff --git a/include/drm/ttm/ttm_memory.h b/include/drm/ttm/ttm_memory.h
index d8b8f042c4f..6983a7cf4da 100644
--- a/include/drm/ttm/ttm_memory.h
+++ b/include/drm/ttm/ttm_memory.h
@@ -32,6 +32,7 @@
 #include <linux/spinlock.h>
 #include <linux/wait.h>
 #include <linux/errno.h>
+#include <linux/kobject.h>
 
 /**
  * struct ttm_mem_shrink - callback to shrink TTM memory usage.
@@ -60,34 +61,33 @@ struct ttm_mem_shrink {
  * @queue: Wait queue for processes suspended waiting for memory.
  * @lock: Lock to protect the @shrink - and the memory accounting members,
  * that is, essentially the whole structure with some exceptions.
- * @emer_memory: Lowmem memory limit available for root.
- * @max_memory: Lowmem memory limit available for non-root.
- * @swap_limit: Lowmem memory limit where the shrink workqueue kicks in.
- * @used_memory: Currently used lowmem memory.
- * @used_total_memory: Currently used total (lowmem + highmem) memory.
- * @total_memory_swap_limit: Total memory limit where the shrink workqueue
- * kicks in.
- * @max_total_memory: Total memory available to non-root processes.
- * @emer_total_memory: Total memory available to root processes.
+ * @zones: Array of pointers to accounting zones.
+ * @num_zones: Number of populated entries in the @zones array.
+ * @zone_kernel: Pointer to the kernel zone.
+ * @zone_highmem: Pointer to the highmem zone if there is one.
+ * @zone_dma32: Pointer to the dma32 zone if there is one.
  *
  * Note that this structure is not per device. It should be global for all
  * graphics devices.
  */
 
+#define TTM_MEM_MAX_ZONES 2
+struct ttm_mem_zone;
 struct ttm_mem_global {
+	struct kobject kobj;
 	struct ttm_mem_shrink *shrink;
 	struct workqueue_struct *swap_queue;
 	struct work_struct work;
 	wait_queue_head_t queue;
 	spinlock_t lock;
-	uint64_t emer_memory;
-	uint64_t max_memory;
-	uint64_t swap_limit;
-	uint64_t used_memory;
-	uint64_t used_total_memory;
-	uint64_t total_memory_swap_limit;
-	uint64_t max_total_memory;
-	uint64_t emer_total_memory;
+	struct ttm_mem_zone *zones[TTM_MEM_MAX_ZONES];
+	unsigned int num_zones;
+	struct ttm_mem_zone *zone_kernel;
+#ifdef CONFIG_HIGHMEM
+	struct ttm_mem_zone *zone_highmem;
+#else
+	struct ttm_mem_zone *zone_dma32;
+#endif
 };
 
 /**
@@ -146,8 +146,13 @@ static inline void ttm_mem_unregister_shrink(struct ttm_mem_global *glob,
 extern int ttm_mem_global_init(struct ttm_mem_global *glob);
 extern void ttm_mem_global_release(struct ttm_mem_global *glob);
 extern int ttm_mem_global_alloc(struct ttm_mem_global *glob, uint64_t memory,
-				bool no_wait, bool interruptible, bool himem);
+				bool no_wait, bool interruptible);
 extern void ttm_mem_global_free(struct ttm_mem_global *glob,
-				uint64_t amount, bool himem);
+				uint64_t amount);
+extern int ttm_mem_global_alloc_page(struct ttm_mem_global *glob,
+				     struct page *page,
+				     bool no_wait, bool interruptible);
+extern void ttm_mem_global_free_page(struct ttm_mem_global *glob,
+				     struct page *page);
 extern size_t ttm_round_pot(size_t size);
 #endif
diff --git a/include/drm/ttm/ttm_module.h b/include/drm/ttm/ttm_module.h
index 889a4c7958a..0a72ac7c7e5 100644
--- a/include/drm/ttm/ttm_module.h
+++ b/include/drm/ttm/ttm_module.h
@@ -32,6 +32,7 @@
 #define _TTM_MODULE_H_
 
 #include <linux/kernel.h>
+struct kobject;
 
 #define TTM_PFX "[TTM]"
 
@@ -54,5 +55,6 @@ extern void ttm_global_init(void);
 extern void ttm_global_release(void);
 extern int ttm_global_item_ref(struct ttm_global_reference *ref);
 extern void ttm_global_item_unref(struct ttm_global_reference *ref);
+extern struct kobject *ttm_get_kobj(void);
 
 #endif /* _TTM_MODULE_H_ */
-- 
cgit v1.2.3


From a987fcaa805fcb24ba885c2e29fd4fdb6816f08f Mon Sep 17 00:00:00 2001
From: Thomas Hellstrom <thellstrom@vmware.com>
Date: Tue, 18 Aug 2009 16:51:56 +0200
Subject: ttm: Make parts of a struct ttm_bo_device global.

Common resources, like memory accounting and swap lists should be
global and not per device. Introduce a struct ttm_bo_global to
accomodate this, and register it with sysfs. Add a small sysfs interface
to return the number of active buffer objects.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Signed-off-by: Dave Airlie <airlied@linux.ie>
---
 drivers/gpu/drm/radeon/radeon_object.h |   1 +
 drivers/gpu/drm/radeon/radeon_ttm.c    |  33 +++-
 drivers/gpu/drm/ttm/ttm_bo.c           | 292 ++++++++++++++++++++++-----------
 drivers/gpu/drm/ttm/ttm_bo_util.c      |   4 +-
 drivers/gpu/drm/ttm/ttm_tt.c           |  12 +-
 include/drm/ttm/ttm_bo_api.h           |   1 +
 include/drm/ttm/ttm_bo_driver.h        |  94 ++++++++---
 7 files changed, 296 insertions(+), 141 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_object.h b/drivers/gpu/drm/radeon/radeon_object.h
index 473e4775dc5..10e8af6bb45 100644
--- a/drivers/gpu/drm/radeon/radeon_object.h
+++ b/drivers/gpu/drm/radeon/radeon_object.h
@@ -37,6 +37,7 @@
  * TTM.
  */
 struct radeon_mman {
+	struct ttm_bo_global_ref        bo_global_ref;
 	struct ttm_global_reference	mem_global_ref;
 	bool				mem_global_referenced;
 	struct ttm_bo_device		bdev;
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index 1227a97f516..343b6d6b99c 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -77,9 +77,25 @@ static int radeon_ttm_global_init(struct radeon_device *rdev)
 	global_ref->release = &radeon_ttm_mem_global_release;
 	r = ttm_global_item_ref(global_ref);
 	if (r != 0) {
-		DRM_ERROR("Failed referencing a global TTM memory object.\n");
+		DRM_ERROR("Failed setting up TTM memory accounting "
+			  "subsystem.\n");
 		return r;
 	}
+
+	rdev->mman.bo_global_ref.mem_glob =
+		rdev->mman.mem_global_ref.object;
+	global_ref = &rdev->mman.bo_global_ref.ref;
+	global_ref->global_type = TTM_GLOBAL_TTM_BO;
+	global_ref->size = sizeof(struct ttm_mem_global);
+	global_ref->init = &ttm_bo_global_init;
+	global_ref->release = &ttm_bo_global_release;
+	r = ttm_global_item_ref(global_ref);
+	if (r != 0) {
+		DRM_ERROR("Failed setting up TTM BO subsystem.\n");
+		ttm_global_item_unref(&rdev->mman.mem_global_ref);
+		return r;
+	}
+
 	rdev->mman.mem_global_referenced = true;
 	return 0;
 }
@@ -87,6 +103,7 @@ static int radeon_ttm_global_init(struct radeon_device *rdev)
 static void radeon_ttm_global_fini(struct radeon_device *rdev)
 {
 	if (rdev->mman.mem_global_referenced) {
+		ttm_global_item_unref(&rdev->mman.bo_global_ref.ref);
 		ttm_global_item_unref(&rdev->mman.mem_global_ref);
 		rdev->mman.mem_global_referenced = false;
 	}
@@ -286,9 +303,11 @@ static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
 	r = ttm_bo_move_ttm(bo, true, no_wait, new_mem);
 out_cleanup:
 	if (tmp_mem.mm_node) {
-		spin_lock(&rdev->mman.bdev.lru_lock);
+		struct ttm_bo_global *glob = rdev->mman.bdev.glob;
+
+		spin_lock(&glob->lru_lock);
 		drm_mm_put_block(tmp_mem.mm_node);
-		spin_unlock(&rdev->mman.bdev.lru_lock);
+		spin_unlock(&glob->lru_lock);
 		return r;
 	}
 	return r;
@@ -323,9 +342,11 @@ static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
 	}
 out_cleanup:
 	if (tmp_mem.mm_node) {
-		spin_lock(&rdev->mman.bdev.lru_lock);
+		struct ttm_bo_global *glob = rdev->mman.bdev.glob;
+
+		spin_lock(&glob->lru_lock);
 		drm_mm_put_block(tmp_mem.mm_node);
-		spin_unlock(&rdev->mman.bdev.lru_lock);
+		spin_unlock(&glob->lru_lock);
 		return r;
 	}
 	return r;
@@ -441,7 +462,7 @@ int radeon_ttm_init(struct radeon_device *rdev)
 	}
 	/* No others user of address space so set it to 0 */
 	r = ttm_bo_device_init(&rdev->mman.bdev,
-			       rdev->mman.mem_global_ref.object,
+			       rdev->mman.bo_global_ref.ref.object,
 			       &radeon_bo_driver, DRM_FILE_PAGE_OFFSET);
 	if (r) {
 		DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index f16909ceec9..0d0b1b7afbc 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -45,6 +45,39 @@
 static int ttm_bo_setup_vm(struct ttm_buffer_object *bo);
 static void ttm_bo_unmap_virtual(struct ttm_buffer_object *bo);
 static int ttm_bo_swapout(struct ttm_mem_shrink *shrink);
+static void ttm_bo_global_kobj_release(struct kobject *kobj);
+
+static struct attribute ttm_bo_count = {
+	.name = "bo_count",
+	.mode = S_IRUGO
+};
+
+static ssize_t ttm_bo_global_show(struct kobject *kobj,
+				  struct attribute *attr,
+				  char *buffer)
+{
+	struct ttm_bo_global *glob =
+		container_of(kobj, struct ttm_bo_global, kobj);
+
+	return snprintf(buffer, PAGE_SIZE, "%lu\n",
+			(unsigned long) atomic_read(&glob->bo_count));
+}
+
+static struct attribute *ttm_bo_global_attrs[] = {
+	&ttm_bo_count,
+	NULL
+};
+
+static struct sysfs_ops ttm_bo_global_ops = {
+	.show = &ttm_bo_global_show
+};
+
+static struct kobj_type ttm_bo_glob_kobj_type  = {
+	.release = &ttm_bo_global_kobj_release,
+	.sysfs_ops = &ttm_bo_global_ops,
+	.default_attrs = ttm_bo_global_attrs
+};
+
 
 static inline uint32_t ttm_bo_type_flags(unsigned type)
 {
@@ -67,10 +100,11 @@ static void ttm_bo_release_list(struct kref *list_kref)
 
 	if (bo->ttm)
 		ttm_tt_destroy(bo->ttm);
+	atomic_dec(&bo->glob->bo_count);
 	if (bo->destroy)
 		bo->destroy(bo);
 	else {
-		ttm_mem_global_free(bdev->mem_glob, bo->acc_size);
+		ttm_mem_global_free(bdev->glob->mem_glob, bo->acc_size);
 		kfree(bo);
 	}
 }
@@ -107,7 +141,7 @@ static void ttm_bo_add_to_lru(struct ttm_buffer_object *bo)
 		kref_get(&bo->list_kref);
 
 		if (bo->ttm != NULL) {
-			list_add_tail(&bo->swap, &bdev->swap_lru);
+			list_add_tail(&bo->swap, &bo->glob->swap_lru);
 			kref_get(&bo->list_kref);
 		}
 	}
@@ -142,7 +176,7 @@ int ttm_bo_reserve_locked(struct ttm_buffer_object *bo,
 			  bool interruptible,
 			  bool no_wait, bool use_sequence, uint32_t sequence)
 {
-	struct ttm_bo_device *bdev = bo->bdev;
+	struct ttm_bo_global *glob = bo->glob;
 	int ret;
 
 	while (unlikely(atomic_cmpxchg(&bo->reserved, 0, 1) != 0)) {
@@ -154,9 +188,9 @@ int ttm_bo_reserve_locked(struct ttm_buffer_object *bo,
 		if (no_wait)
 			return -EBUSY;
 
-		spin_unlock(&bdev->lru_lock);
+		spin_unlock(&glob->lru_lock);
 		ret = ttm_bo_wait_unreserved(bo, interruptible);
-		spin_lock(&bdev->lru_lock);
+		spin_lock(&glob->lru_lock);
 
 		if (unlikely(ret))
 			return ret;
@@ -182,16 +216,16 @@ int ttm_bo_reserve(struct ttm_buffer_object *bo,
 		   bool interruptible,
 		   bool no_wait, bool use_sequence, uint32_t sequence)
 {
-	struct ttm_bo_device *bdev = bo->bdev;
+	struct ttm_bo_global *glob = bo->glob;
 	int put_count = 0;
 	int ret;
 
-	spin_lock(&bdev->lru_lock);
+	spin_lock(&glob->lru_lock);
 	ret = ttm_bo_reserve_locked(bo, interruptible, no_wait, use_sequence,
 				    sequence);
 	if (likely(ret == 0))
 		put_count = ttm_bo_del_from_lru(bo);
-	spin_unlock(&bdev->lru_lock);
+	spin_unlock(&glob->lru_lock);
 
 	while (put_count--)
 		kref_put(&bo->list_kref, ttm_bo_ref_bug);
@@ -201,13 +235,13 @@ int ttm_bo_reserve(struct ttm_buffer_object *bo,
 
 void ttm_bo_unreserve(struct ttm_buffer_object *bo)
 {
-	struct ttm_bo_device *bdev = bo->bdev;
+	struct ttm_bo_global *glob = bo->glob;
 
-	spin_lock(&bdev->lru_lock);
+	spin_lock(&glob->lru_lock);
 	ttm_bo_add_to_lru(bo);
 	atomic_set(&bo->reserved, 0);
 	wake_up_all(&bo->event_queue);
-	spin_unlock(&bdev->lru_lock);
+	spin_unlock(&glob->lru_lock);
 }
 EXPORT_SYMBOL(ttm_bo_unreserve);
 
@@ -218,6 +252,7 @@ EXPORT_SYMBOL(ttm_bo_unreserve);
 static int ttm_bo_add_ttm(struct ttm_buffer_object *bo, bool zero_alloc)
 {
 	struct ttm_bo_device *bdev = bo->bdev;
+	struct ttm_bo_global *glob = bo->glob;
 	int ret = 0;
 	uint32_t page_flags = 0;
 
@@ -230,14 +265,14 @@ static int ttm_bo_add_ttm(struct ttm_buffer_object *bo, bool zero_alloc)
 			page_flags |= TTM_PAGE_FLAG_ZERO_ALLOC;
 	case ttm_bo_type_kernel:
 		bo->ttm = ttm_tt_create(bdev, bo->num_pages << PAGE_SHIFT,
-					page_flags, bdev->dummy_read_page);
+					page_flags, glob->dummy_read_page);
 		if (unlikely(bo->ttm == NULL))
 			ret = -ENOMEM;
 		break;
 	case ttm_bo_type_user:
 		bo->ttm = ttm_tt_create(bdev, bo->num_pages << PAGE_SHIFT,
 					page_flags | TTM_PAGE_FLAG_USER,
-					bdev->dummy_read_page);
+					glob->dummy_read_page);
 		if (unlikely(bo->ttm == NULL))
 			ret = -ENOMEM;
 		break;
@@ -355,6 +390,7 @@ out_err:
 static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all)
 {
 	struct ttm_bo_device *bdev = bo->bdev;
+	struct ttm_bo_global *glob = bo->glob;
 	struct ttm_bo_driver *driver = bdev->driver;
 	int ret;
 
@@ -366,7 +402,7 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all)
 
 		spin_unlock(&bo->lock);
 
-		spin_lock(&bdev->lru_lock);
+		spin_lock(&glob->lru_lock);
 		ret = ttm_bo_reserve_locked(bo, false, false, false, 0);
 		BUG_ON(ret);
 		if (bo->ttm)
@@ -381,7 +417,7 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all)
 			bo->mem.mm_node = NULL;
 		}
 		put_count = ttm_bo_del_from_lru(bo);
-		spin_unlock(&bdev->lru_lock);
+		spin_unlock(&glob->lru_lock);
 
 		atomic_set(&bo->reserved, 0);
 
@@ -391,14 +427,14 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all)
 		return 0;
 	}
 
-	spin_lock(&bdev->lru_lock);
+	spin_lock(&glob->lru_lock);
 	if (list_empty(&bo->ddestroy)) {
 		void *sync_obj = bo->sync_obj;
 		void *sync_obj_arg = bo->sync_obj_arg;
 
 		kref_get(&bo->list_kref);
 		list_add_tail(&bo->ddestroy, &bdev->ddestroy);
-		spin_unlock(&bdev->lru_lock);
+		spin_unlock(&glob->lru_lock);
 		spin_unlock(&bo->lock);
 
 		if (sync_obj)
@@ -408,7 +444,7 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all)
 		ret = 0;
 
 	} else {
-		spin_unlock(&bdev->lru_lock);
+		spin_unlock(&glob->lru_lock);
 		spin_unlock(&bo->lock);
 		ret = -EBUSY;
 	}
@@ -423,11 +459,12 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all)
 
 static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all)
 {
+	struct ttm_bo_global *glob = bdev->glob;
 	struct ttm_buffer_object *entry, *nentry;
 	struct list_head *list, *next;
 	int ret;
 
-	spin_lock(&bdev->lru_lock);
+	spin_lock(&glob->lru_lock);
 	list_for_each_safe(list, next, &bdev->ddestroy) {
 		entry = list_entry(list, struct ttm_buffer_object, ddestroy);
 		nentry = NULL;
@@ -444,16 +481,16 @@ static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all)
 		}
 		kref_get(&entry->list_kref);
 
-		spin_unlock(&bdev->lru_lock);
+		spin_unlock(&glob->lru_lock);
 		ret = ttm_bo_cleanup_refs(entry, remove_all);
 		kref_put(&entry->list_kref, ttm_bo_release_list);
 
-		spin_lock(&bdev->lru_lock);
+		spin_lock(&glob->lru_lock);
 		if (nentry) {
 			bool next_onlist = !list_empty(next);
-			spin_unlock(&bdev->lru_lock);
+			spin_unlock(&glob->lru_lock);
 			kref_put(&nentry->list_kref, ttm_bo_release_list);
-			spin_lock(&bdev->lru_lock);
+			spin_lock(&glob->lru_lock);
 			/*
 			 * Someone might have raced us and removed the
 			 * next entry from the list. We don't bother restarting
@@ -467,7 +504,7 @@ static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all)
 			break;
 	}
 	ret = !list_empty(&bdev->ddestroy);
-	spin_unlock(&bdev->lru_lock);
+	spin_unlock(&glob->lru_lock);
 
 	return ret;
 }
@@ -517,6 +554,7 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, unsigned mem_type,
 {
 	int ret = 0;
 	struct ttm_bo_device *bdev = bo->bdev;
+	struct ttm_bo_global *glob = bo->glob;
 	struct ttm_mem_reg evict_mem;
 	uint32_t proposed_placement;
 
@@ -565,12 +603,12 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, unsigned mem_type,
 		goto out;
 	}
 
-	spin_lock(&bdev->lru_lock);
+	spin_lock(&glob->lru_lock);
 	if (evict_mem.mm_node) {
 		drm_mm_put_block(evict_mem.mm_node);
 		evict_mem.mm_node = NULL;
 	}
-	spin_unlock(&bdev->lru_lock);
+	spin_unlock(&glob->lru_lock);
 	bo->evicted = true;
 out:
 	return ret;
@@ -585,6 +623,7 @@ static int ttm_bo_mem_force_space(struct ttm_bo_device *bdev,
 				  uint32_t mem_type,
 				  bool interruptible, bool no_wait)
 {
+	struct ttm_bo_global *glob = bdev->glob;
 	struct drm_mm_node *node;
 	struct ttm_buffer_object *entry;
 	struct ttm_mem_type_manager *man = &bdev->man[mem_type];
@@ -598,7 +637,7 @@ retry_pre_get:
 	if (unlikely(ret != 0))
 		return ret;
 
-	spin_lock(&bdev->lru_lock);
+	spin_lock(&glob->lru_lock);
 	do {
 		node = drm_mm_search_free(&man->manager, num_pages,
 					  mem->page_alignment, 1);
@@ -619,7 +658,7 @@ retry_pre_get:
 		if (likely(ret == 0))
 			put_count = ttm_bo_del_from_lru(entry);
 
-		spin_unlock(&bdev->lru_lock);
+		spin_unlock(&glob->lru_lock);
 
 		if (unlikely(ret != 0))
 			return ret;
@@ -635,21 +674,21 @@ retry_pre_get:
 		if (ret)
 			return ret;
 
-		spin_lock(&bdev->lru_lock);
+		spin_lock(&glob->lru_lock);
 	} while (1);
 
 	if (!node) {
-		spin_unlock(&bdev->lru_lock);
+		spin_unlock(&glob->lru_lock);
 		return -ENOMEM;
 	}
 
 	node = drm_mm_get_block_atomic(node, num_pages, mem->page_alignment);
 	if (unlikely(!node)) {
-		spin_unlock(&bdev->lru_lock);
+		spin_unlock(&glob->lru_lock);
 		goto retry_pre_get;
 	}
 
-	spin_unlock(&bdev->lru_lock);
+	spin_unlock(&glob->lru_lock);
 	mem->mm_node = node;
 	mem->mem_type = mem_type;
 	return 0;
@@ -697,6 +736,7 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo,
 		     bool interruptible, bool no_wait)
 {
 	struct ttm_bo_device *bdev = bo->bdev;
+	struct ttm_bo_global *glob = bo->glob;
 	struct ttm_mem_type_manager *man;
 
 	uint32_t num_prios = bdev->driver->num_mem_type_prio;
@@ -733,20 +773,20 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo,
 				if (unlikely(ret))
 					return ret;
 
-				spin_lock(&bdev->lru_lock);
+				spin_lock(&glob->lru_lock);
 				node = drm_mm_search_free(&man->manager,
 							  mem->num_pages,
 							  mem->page_alignment,
 							  1);
 				if (unlikely(!node)) {
-					spin_unlock(&bdev->lru_lock);
+					spin_unlock(&glob->lru_lock);
 					break;
 				}
 				node = drm_mm_get_block_atomic(node,
 							       mem->num_pages,
 							       mem->
 							       page_alignment);
-				spin_unlock(&bdev->lru_lock);
+				spin_unlock(&glob->lru_lock);
 			} while (!node);
 		}
 		if (node)
@@ -816,7 +856,7 @@ int ttm_bo_move_buffer(struct ttm_buffer_object *bo,
 		       uint32_t proposed_placement,
 		       bool interruptible, bool no_wait)
 {
-	struct ttm_bo_device *bdev = bo->bdev;
+	struct ttm_bo_global *glob = bo->glob;
 	int ret = 0;
 	struct ttm_mem_reg mem;
 
@@ -852,9 +892,9 @@ int ttm_bo_move_buffer(struct ttm_buffer_object *bo,
 
 out_unlock:
 	if (ret && mem.mm_node) {
-		spin_lock(&bdev->lru_lock);
+		spin_lock(&glob->lru_lock);
 		drm_mm_put_block(mem.mm_node);
-		spin_unlock(&bdev->lru_lock);
+		spin_unlock(&glob->lru_lock);
 	}
 	return ret;
 }
@@ -990,6 +1030,7 @@ int ttm_buffer_object_init(struct ttm_bo_device *bdev,
 	INIT_LIST_HEAD(&bo->ddestroy);
 	INIT_LIST_HEAD(&bo->swap);
 	bo->bdev = bdev;
+	bo->glob = bdev->glob;
 	bo->type = type;
 	bo->num_pages = num_pages;
 	bo->mem.mem_type = TTM_PL_SYSTEM;
@@ -1002,6 +1043,7 @@ int ttm_buffer_object_init(struct ttm_bo_device *bdev,
 	bo->seq_valid = false;
 	bo->persistant_swap_storage = persistant_swap_storage;
 	bo->acc_size = acc_size;
+	atomic_inc(&bo->glob->bo_count);
 
 	ret = ttm_bo_check_placement(bo, flags, 0ULL);
 	if (unlikely(ret != 0))
@@ -1040,13 +1082,13 @@ out_err:
 }
 EXPORT_SYMBOL(ttm_buffer_object_init);
 
-static inline size_t ttm_bo_size(struct ttm_bo_device *bdev,
+static inline size_t ttm_bo_size(struct ttm_bo_global *glob,
 				 unsigned long num_pages)
 {
 	size_t page_array_size = (num_pages * sizeof(void *) + PAGE_SIZE - 1) &
 	    PAGE_MASK;
 
-	return bdev->ttm_bo_size + 2 * page_array_size;
+	return glob->ttm_bo_size + 2 * page_array_size;
 }
 
 int ttm_buffer_object_create(struct ttm_bo_device *bdev,
@@ -1061,10 +1103,10 @@ int ttm_buffer_object_create(struct ttm_bo_device *bdev,
 {
 	struct ttm_buffer_object *bo;
 	int ret;
-	struct ttm_mem_global *mem_glob = bdev->mem_glob;
+	struct ttm_mem_global *mem_glob = bdev->glob->mem_glob;
 
 	size_t acc_size =
-	    ttm_bo_size(bdev, (size + PAGE_SIZE - 1) >> PAGE_SHIFT);
+	    ttm_bo_size(bdev->glob, (size + PAGE_SIZE - 1) >> PAGE_SHIFT);
 	ret = ttm_mem_global_alloc(mem_glob, acc_size, false, false);
 	if (unlikely(ret != 0))
 		return ret;
@@ -1118,6 +1160,7 @@ static int ttm_bo_force_list_clean(struct ttm_bo_device *bdev,
 				   struct list_head *head,
 				   unsigned mem_type, bool allow_errors)
 {
+	struct ttm_bo_global *glob = bdev->glob;
 	struct ttm_buffer_object *entry;
 	int ret;
 	int put_count;
@@ -1126,30 +1169,31 @@ static int ttm_bo_force_list_clean(struct ttm_bo_device *bdev,
 	 * Can't use standard list traversal since we're unlocking.
 	 */
 
-	spin_lock(&bdev->lru_lock);
+	spin_lock(&glob->lru_lock);
 
 	while (!list_empty(head)) {
 		entry = list_first_entry(head, struct ttm_buffer_object, lru);
 		kref_get(&entry->list_kref);
 		ret = ttm_bo_reserve_locked(entry, false, false, false, 0);
 		put_count = ttm_bo_del_from_lru(entry);
-		spin_unlock(&bdev->lru_lock);
+		spin_unlock(&glob->lru_lock);
 		while (put_count--)
 			kref_put(&entry->list_kref, ttm_bo_ref_bug);
 		BUG_ON(ret);
 		ret = ttm_bo_leave_list(entry, mem_type, allow_errors);
 		ttm_bo_unreserve(entry);
 		kref_put(&entry->list_kref, ttm_bo_release_list);
-		spin_lock(&bdev->lru_lock);
+		spin_lock(&glob->lru_lock);
 	}
 
-	spin_unlock(&bdev->lru_lock);
+	spin_unlock(&glob->lru_lock);
 
 	return 0;
 }
 
 int ttm_bo_clean_mm(struct ttm_bo_device *bdev, unsigned mem_type)
 {
+	struct ttm_bo_global *glob = bdev->glob;
 	struct ttm_mem_type_manager *man = &bdev->man[mem_type];
 	int ret = -EINVAL;
 
@@ -1171,13 +1215,13 @@ int ttm_bo_clean_mm(struct ttm_bo_device *bdev, unsigned mem_type)
 	if (mem_type > 0) {
 		ttm_bo_force_list_clean(bdev, &man->lru, mem_type, false);
 
-		spin_lock(&bdev->lru_lock);
+		spin_lock(&glob->lru_lock);
 		if (drm_mm_clean(&man->manager))
 			drm_mm_takedown(&man->manager);
 		else
 			ret = -EBUSY;
 
-		spin_unlock(&bdev->lru_lock);
+		spin_unlock(&glob->lru_lock);
 	}
 
 	return ret;
@@ -1251,11 +1295,83 @@ int ttm_bo_init_mm(struct ttm_bo_device *bdev, unsigned type,
 }
 EXPORT_SYMBOL(ttm_bo_init_mm);
 
+static void ttm_bo_global_kobj_release(struct kobject *kobj)
+{
+	struct ttm_bo_global *glob =
+		container_of(kobj, struct ttm_bo_global, kobj);
+
+	printk(KERN_INFO TTM_PFX "Freeing bo global.\n");
+	ttm_mem_unregister_shrink(glob->mem_glob, &glob->shrink);
+	__free_page(glob->dummy_read_page);
+	kfree(glob);
+}
+
+void ttm_bo_global_release(struct ttm_global_reference *ref)
+{
+	struct ttm_bo_global *glob = ref->object;
+
+	kobject_del(&glob->kobj);
+	kobject_put(&glob->kobj);
+}
+EXPORT_SYMBOL(ttm_bo_global_release);
+
+int ttm_bo_global_init(struct ttm_global_reference *ref)
+{
+	struct ttm_bo_global_ref *bo_ref =
+		container_of(ref, struct ttm_bo_global_ref, ref);
+	struct ttm_bo_global *glob = ref->object;
+	int ret;
+
+	mutex_init(&glob->device_list_mutex);
+	spin_lock_init(&glob->lru_lock);
+	glob->mem_glob = bo_ref->mem_glob;
+	glob->dummy_read_page = alloc_page(__GFP_ZERO | GFP_DMA32);
+
+	if (unlikely(glob->dummy_read_page == NULL)) {
+		ret = -ENOMEM;
+		goto out_no_drp;
+	}
+
+	INIT_LIST_HEAD(&glob->swap_lru);
+	INIT_LIST_HEAD(&glob->device_list);
+
+	ttm_mem_init_shrink(&glob->shrink, ttm_bo_swapout);
+	ret = ttm_mem_register_shrink(glob->mem_glob, &glob->shrink);
+	if (unlikely(ret != 0)) {
+		printk(KERN_ERR TTM_PFX
+		       "Could not register buffer object swapout.\n");
+		goto out_no_shrink;
+	}
+
+	glob->ttm_bo_extra_size =
+		ttm_round_pot(sizeof(struct ttm_tt)) +
+		ttm_round_pot(sizeof(struct ttm_backend));
+
+	glob->ttm_bo_size = glob->ttm_bo_extra_size +
+		ttm_round_pot(sizeof(struct ttm_buffer_object));
+
+	atomic_set(&glob->bo_count, 0);
+
+	kobject_init(&glob->kobj, &ttm_bo_glob_kobj_type);
+	ret = kobject_add(&glob->kobj, ttm_get_kobj(), "buffer_objects");
+	if (unlikely(ret != 0))
+		kobject_put(&glob->kobj);
+	return ret;
+out_no_shrink:
+	__free_page(glob->dummy_read_page);
+out_no_drp:
+	kfree(glob);
+	return ret;
+}
+EXPORT_SYMBOL(ttm_bo_global_init);
+
+
 int ttm_bo_device_release(struct ttm_bo_device *bdev)
 {
 	int ret = 0;
 	unsigned i = TTM_NUM_MEM_TYPES;
 	struct ttm_mem_type_manager *man;
+	struct ttm_bo_global *glob = bdev->glob;
 
 	while (i--) {
 		man = &bdev->man[i];
@@ -1271,98 +1387,74 @@ int ttm_bo_device_release(struct ttm_bo_device *bdev)
 		}
 	}
 
+	mutex_lock(&glob->device_list_mutex);
+	list_del(&bdev->device_list);
+	mutex_unlock(&glob->device_list_mutex);
+
 	if (!cancel_delayed_work(&bdev->wq))
 		flush_scheduled_work();
 
 	while (ttm_bo_delayed_delete(bdev, true))
 		;
 
-	spin_lock(&bdev->lru_lock);
+	spin_lock(&glob->lru_lock);
 	if (list_empty(&bdev->ddestroy))
 		TTM_DEBUG("Delayed destroy list was clean\n");
 
 	if (list_empty(&bdev->man[0].lru))
 		TTM_DEBUG("Swap list was clean\n");
-	spin_unlock(&bdev->lru_lock);
+	spin_unlock(&glob->lru_lock);
 
-	ttm_mem_unregister_shrink(bdev->mem_glob, &bdev->shrink);
 	BUG_ON(!drm_mm_clean(&bdev->addr_space_mm));
 	write_lock(&bdev->vm_lock);
 	drm_mm_takedown(&bdev->addr_space_mm);
 	write_unlock(&bdev->vm_lock);
 
-	__free_page(bdev->dummy_read_page);
 	return ret;
 }
 EXPORT_SYMBOL(ttm_bo_device_release);
 
-/*
- * This function is intended to be called on drm driver load.
- * If you decide to call it from firstopen, you must protect the call
- * from a potentially racing ttm_bo_driver_finish in lastclose.
- * (This may happen on X server restart).
- */
-
 int ttm_bo_device_init(struct ttm_bo_device *bdev,
-		       struct ttm_mem_global *mem_glob,
-		       struct ttm_bo_driver *driver, uint64_t file_page_offset)
+		       struct ttm_bo_global *glob,
+		       struct ttm_bo_driver *driver,
+		       uint64_t file_page_offset)
 {
 	int ret = -EINVAL;
 
-	bdev->dummy_read_page = NULL;
 	rwlock_init(&bdev->vm_lock);
-	spin_lock_init(&bdev->lru_lock);
+	spin_lock_init(&glob->lru_lock);
 
 	bdev->driver = driver;
-	bdev->mem_glob = mem_glob;
 
 	memset(bdev->man, 0, sizeof(bdev->man));
 
-	bdev->dummy_read_page = alloc_page(__GFP_ZERO | GFP_DMA32);
-	if (unlikely(bdev->dummy_read_page == NULL)) {
-		ret = -ENOMEM;
-		goto out_err0;
-	}
-
 	/*
 	 * Initialize the system memory buffer type.
 	 * Other types need to be driver / IOCTL initialized.
 	 */
 	ret = ttm_bo_init_mm(bdev, TTM_PL_SYSTEM, 0, 0);
 	if (unlikely(ret != 0))
-		goto out_err1;
+		goto out_no_sys;
 
 	bdev->addr_space_rb = RB_ROOT;
 	ret = drm_mm_init(&bdev->addr_space_mm, file_page_offset, 0x10000000);
 	if (unlikely(ret != 0))
-		goto out_err2;
+		goto out_no_addr_mm;
 
 	INIT_DELAYED_WORK(&bdev->wq, ttm_bo_delayed_workqueue);
 	bdev->nice_mode = true;
 	INIT_LIST_HEAD(&bdev->ddestroy);
-	INIT_LIST_HEAD(&bdev->swap_lru);
 	bdev->dev_mapping = NULL;
-	ttm_mem_init_shrink(&bdev->shrink, ttm_bo_swapout);
-	ret = ttm_mem_register_shrink(mem_glob, &bdev->shrink);
-	if (unlikely(ret != 0)) {
-		printk(KERN_ERR TTM_PFX
-		       "Could not register buffer object swapout.\n");
-		goto out_err2;
-	}
+	bdev->glob = glob;
 
-	bdev->ttm_bo_extra_size =
-		ttm_round_pot(sizeof(struct ttm_tt)) +
-		ttm_round_pot(sizeof(struct ttm_backend));
-
-	bdev->ttm_bo_size = bdev->ttm_bo_extra_size +
-		ttm_round_pot(sizeof(struct ttm_buffer_object));
+	mutex_lock(&glob->device_list_mutex);
+	list_add_tail(&bdev->device_list, &glob->device_list);
+	mutex_unlock(&glob->device_list_mutex);
 
 	return 0;
-out_err2:
+out_no_addr_mm:
 	ttm_bo_clean_mm(bdev, 0);
-out_err1:
-	__free_page(bdev->dummy_read_page);
-out_err0:
+out_no_sys:
 	return ret;
 }
 EXPORT_SYMBOL(ttm_bo_device_init);
@@ -1607,21 +1699,21 @@ void ttm_bo_synccpu_write_release(struct ttm_buffer_object *bo)
 
 static int ttm_bo_swapout(struct ttm_mem_shrink *shrink)
 {
-	struct ttm_bo_device *bdev =
-	    container_of(shrink, struct ttm_bo_device, shrink);
+	struct ttm_bo_global *glob =
+	    container_of(shrink, struct ttm_bo_global, shrink);
 	struct ttm_buffer_object *bo;
 	int ret = -EBUSY;
 	int put_count;
 	uint32_t swap_placement = (TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM);
 
-	spin_lock(&bdev->lru_lock);
+	spin_lock(&glob->lru_lock);
 	while (ret == -EBUSY) {
-		if (unlikely(list_empty(&bdev->swap_lru))) {
-			spin_unlock(&bdev->lru_lock);
+		if (unlikely(list_empty(&glob->swap_lru))) {
+			spin_unlock(&glob->lru_lock);
 			return -EBUSY;
 		}
 
-		bo = list_first_entry(&bdev->swap_lru,
+		bo = list_first_entry(&glob->swap_lru,
 				      struct ttm_buffer_object, swap);
 		kref_get(&bo->list_kref);
 
@@ -1633,16 +1725,16 @@ static int ttm_bo_swapout(struct ttm_mem_shrink *shrink)
 
 		ret = ttm_bo_reserve_locked(bo, false, true, false, 0);
 		if (unlikely(ret == -EBUSY)) {
-			spin_unlock(&bdev->lru_lock);
+			spin_unlock(&glob->lru_lock);
 			ttm_bo_wait_unreserved(bo, false);
 			kref_put(&bo->list_kref, ttm_bo_release_list);
-			spin_lock(&bdev->lru_lock);
+			spin_lock(&glob->lru_lock);
 		}
 	}
 
 	BUG_ON(ret != 0);
 	put_count = ttm_bo_del_from_lru(bo);
-	spin_unlock(&bdev->lru_lock);
+	spin_unlock(&glob->lru_lock);
 
 	while (put_count--)
 		kref_put(&bo->list_kref, ttm_bo_ref_bug);
@@ -1696,6 +1788,6 @@ out:
 
 void ttm_bo_swapout_all(struct ttm_bo_device *bdev)
 {
-	while (ttm_bo_swapout(&bdev->shrink) == 0)
+	while (ttm_bo_swapout(&bdev->glob->shrink) == 0)
 		;
 }
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c
index bdec583901e..12cd47aa18c 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -41,9 +41,9 @@ void ttm_bo_free_old_node(struct ttm_buffer_object *bo)
 	struct ttm_mem_reg *old_mem = &bo->mem;
 
 	if (old_mem->mm_node) {
-		spin_lock(&bo->bdev->lru_lock);
+		spin_lock(&bo->glob->lru_lock);
 		drm_mm_put_block(old_mem->mm_node);
-		spin_unlock(&bo->bdev->lru_lock);
+		spin_unlock(&bo->glob->lru_lock);
 	}
 	old_mem->mm_node = NULL;
 }
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 4e1e2566d51..b0f73096d37 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -166,7 +166,7 @@ static void ttm_tt_free_user_pages(struct ttm_tt *ttm)
 			set_page_dirty_lock(page);
 
 		ttm->pages[i] = NULL;
-		ttm_mem_global_free(ttm->bdev->mem_glob, PAGE_SIZE);
+		ttm_mem_global_free(ttm->glob->mem_glob, PAGE_SIZE);
 		put_page(page);
 	}
 	ttm->state = tt_unpopulated;
@@ -177,8 +177,7 @@ static void ttm_tt_free_user_pages(struct ttm_tt *ttm)
 static struct page *__ttm_tt_get_page(struct ttm_tt *ttm, int index)
 {
 	struct page *p;
-	struct ttm_bo_device *bdev = ttm->bdev;
-	struct ttm_mem_global *mem_glob = bdev->mem_glob;
+	struct ttm_mem_global *mem_glob = ttm->glob->mem_glob;
 	int ret;
 
 	while (NULL == (p = ttm->pages[index])) {
@@ -348,7 +347,7 @@ static void ttm_tt_free_alloced_pages(struct ttm_tt *ttm)
 				printk(KERN_ERR TTM_PFX
 				       "Erroneous page count. "
 				       "Leaking pages.\n");
-			ttm_mem_global_free_page(ttm->bdev->mem_glob,
+			ttm_mem_global_free_page(ttm->glob->mem_glob,
 						 cur_page);
 			__free_page(cur_page);
 		}
@@ -394,7 +393,7 @@ int ttm_tt_set_user(struct ttm_tt *ttm,
 	struct mm_struct *mm = tsk->mm;
 	int ret;
 	int write = (ttm->page_flags & TTM_PAGE_FLAG_WRITE) != 0;
-	struct ttm_mem_global *mem_glob = ttm->bdev->mem_glob;
+	struct ttm_mem_global *mem_glob = ttm->glob->mem_glob;
 
 	BUG_ON(num_pages != ttm->num_pages);
 	BUG_ON((ttm->page_flags & TTM_PAGE_FLAG_USER) == 0);
@@ -439,8 +438,7 @@ struct ttm_tt *ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size,
 	if (!ttm)
 		return NULL;
 
-	ttm->bdev = bdev;
-
+	ttm->glob = bdev->glob;
 	ttm->num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
 	ttm->first_himem_page = ttm->num_pages;
 	ttm->last_lomem_page = -1;
diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h
index 99dc521aa1a..49114617052 100644
--- a/include/drm/ttm/ttm_bo_api.h
+++ b/include/drm/ttm/ttm_bo_api.h
@@ -155,6 +155,7 @@ struct ttm_buffer_object {
 	 * Members constant at init.
 	 */
 
+	struct ttm_bo_global *glob;
 	struct ttm_bo_device *bdev;
 	unsigned long buffer_start;
 	enum ttm_bo_type type;
diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h
index 62ed733c52a..9dc32f70b9a 100644
--- a/include/drm/ttm/ttm_bo_driver.h
+++ b/include/drm/ttm/ttm_bo_driver.h
@@ -32,6 +32,7 @@
 
 #include "ttm/ttm_bo_api.h"
 #include "ttm/ttm_memory.h"
+#include "ttm/ttm_module.h"
 #include "drm_mm.h"
 #include "linux/workqueue.h"
 #include "linux/fs.h"
@@ -160,7 +161,7 @@ struct ttm_tt {
 	long last_lomem_page;
 	uint32_t page_flags;
 	unsigned long num_pages;
-	struct ttm_bo_device *bdev;
+	struct ttm_bo_global *glob;
 	struct ttm_backend *be;
 	struct task_struct *tsk;
 	unsigned long start;
@@ -355,24 +356,73 @@ struct ttm_bo_driver {
 	void *(*sync_obj_ref) (void *sync_obj);
 };
 
-#define TTM_NUM_MEM_TYPES 8
+/**
+ * struct ttm_bo_global_ref - Argument to initialize a struct ttm_bo_global.
+ */
+
+struct ttm_bo_global_ref {
+	struct ttm_global_reference ref;
+	struct ttm_mem_global *mem_glob;
+};
 
-#define TTM_BO_PRIV_FLAG_MOVING  0	/* Buffer object is moving and needs
-					   idling before CPU mapping */
-#define TTM_BO_PRIV_FLAG_MAX 1
 /**
- * struct ttm_bo_device - Buffer object driver device-specific data.
+ * struct ttm_bo_global - Buffer object driver global data.
  *
  * @mem_glob: Pointer to a struct ttm_mem_global object for accounting.
- * @driver: Pointer to a struct ttm_bo_driver struct setup by the driver.
- * @count: Current number of buffer object.
- * @pages: Current number of pinned pages.
  * @dummy_read_page: Pointer to a dummy page used for mapping requests
  * of unpopulated pages.
- * @shrink: A shrink callback object used for buffre object swap.
+ * @shrink: A shrink callback object used for buffer object swap.
  * @ttm_bo_extra_size: Extra size (sizeof(struct ttm_buffer_object) excluded)
  * used by a buffer object. This is excluding page arrays and backing pages.
  * @ttm_bo_size: This is @ttm_bo_extra_size + sizeof(struct ttm_buffer_object).
+ * @device_list_mutex: Mutex protecting the device list.
+ * This mutex is held while traversing the device list for pm options.
+ * @lru_lock: Spinlock protecting the bo subsystem lru lists.
+ * @device_list: List of buffer object devices.
+ * @swap_lru: Lru list of buffer objects used for swapping.
+ */
+
+struct ttm_bo_global {
+
+	/**
+	 * Constant after init.
+	 */
+
+	struct kobject kobj;
+	struct ttm_mem_global *mem_glob;
+	struct page *dummy_read_page;
+	struct ttm_mem_shrink shrink;
+	size_t ttm_bo_extra_size;
+	size_t ttm_bo_size;
+	struct mutex device_list_mutex;
+	spinlock_t lru_lock;
+
+	/**
+	 * Protected by device_list_mutex.
+	 */
+	struct list_head device_list;
+
+	/**
+	 * Protected by the lru_lock.
+	 */
+	struct list_head swap_lru;
+
+	/**
+	 * Internal protection.
+	 */
+	atomic_t bo_count;
+};
+
+
+#define TTM_NUM_MEM_TYPES 8
+
+#define TTM_BO_PRIV_FLAG_MOVING  0	/* Buffer object is moving and needs
+					   idling before CPU mapping */
+#define TTM_BO_PRIV_FLAG_MAX 1
+/**
+ * struct ttm_bo_device - Buffer object driver device-specific data.
+ *
+ * @driver: Pointer to a struct ttm_bo_driver struct setup by the driver.
  * @man: An array of mem_type_managers.
  * @addr_space_mm: Range manager for the device address space.
  * lru_lock: Spinlock that protects the buffer+device lru lists and
@@ -390,32 +440,21 @@ struct ttm_bo_device {
 	/*
 	 * Constant after bo device init / atomic.
 	 */
-
-	struct ttm_mem_global *mem_glob;
+	struct list_head device_list;
+	struct ttm_bo_global *glob;
 	struct ttm_bo_driver *driver;
-	struct page *dummy_read_page;
-	struct ttm_mem_shrink shrink;
-
-	size_t ttm_bo_extra_size;
-	size_t ttm_bo_size;
-
 	rwlock_t vm_lock;
+	struct ttm_mem_type_manager man[TTM_NUM_MEM_TYPES];
 	/*
 	 * Protected by the vm lock.
 	 */
-	struct ttm_mem_type_manager man[TTM_NUM_MEM_TYPES];
 	struct rb_root addr_space_rb;
 	struct drm_mm addr_space_mm;
 
 	/*
-	 * Might want to change this to one lock per manager.
-	 */
-	spinlock_t lru_lock;
-	/*
-	 * Protected by the lru lock.
+	 * Protected by the global:lru lock.
 	 */
 	struct list_head ddestroy;
-	struct list_head swap_lru;
 
 	/*
 	 * Protected by load / firstopen / lastclose /unload sync.
@@ -629,6 +668,9 @@ extern int ttm_bo_pci_offset(struct ttm_bo_device *bdev,
 			     unsigned long *bus_offset,
 			     unsigned long *bus_size);
 
+extern void ttm_bo_global_release(struct ttm_global_reference *ref);
+extern int ttm_bo_global_init(struct ttm_global_reference *ref);
+
 extern int ttm_bo_device_release(struct ttm_bo_device *bdev);
 
 /**
@@ -646,7 +688,7 @@ extern int ttm_bo_device_release(struct ttm_bo_device *bdev);
  * !0: Failure.
  */
 extern int ttm_bo_device_init(struct ttm_bo_device *bdev,
-			      struct ttm_mem_global *mem_glob,
+			      struct ttm_bo_global *glob,
 			      struct ttm_bo_driver *driver,
 			      uint64_t file_page_offset);
 
-- 
cgit v1.2.3


From 7f5f4db2d50ea1af8f160686d2e97bbfa5102b4f Mon Sep 17 00:00:00 2001
From: Thomas Hellstrom <thellstrom@vmware.com>
Date: Thu, 20 Aug 2009 10:29:08 +0200
Subject: drm/ttm: Fixes for "Make parts of a struct ttm_bo_device global"

ttm:
Remove a stray debug printout.
Remove a re-init of the lru spinlock at device init.

radeon:
Fix the size of the bo_global allocation.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/radeon_ttm.c | 2 +-
 drivers/gpu/drm/ttm/ttm_bo.c        | 3 ---
 2 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index 6f5ad0802fc..0a85e7b5d59 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -86,7 +86,7 @@ static int radeon_ttm_global_init(struct radeon_device *rdev)
 		rdev->mman.mem_global_ref.object;
 	global_ref = &rdev->mman.bo_global_ref.ref;
 	global_ref->global_type = TTM_GLOBAL_TTM_BO;
-	global_ref->size = sizeof(struct ttm_mem_global);
+	global_ref->size = sizeof(struct ttm_bo_global);
 	global_ref->init = &ttm_bo_global_init;
 	global_ref->release = &ttm_bo_global_release;
 	r = ttm_global_item_ref(global_ref);
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index fa87ccbcc6c..87c06252d46 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -1333,7 +1333,6 @@ static void ttm_bo_global_kobj_release(struct kobject *kobj)
 	struct ttm_bo_global *glob =
 		container_of(kobj, struct ttm_bo_global, kobj);
 
-	printk(KERN_INFO TTM_PFX "Freeing bo global.\n");
 	ttm_mem_unregister_shrink(glob->mem_glob, &glob->shrink);
 	__free_page(glob->dummy_read_page);
 	kfree(glob);
@@ -1456,8 +1455,6 @@ int ttm_bo_device_init(struct ttm_bo_device *bdev,
 	int ret = -EINVAL;
 
 	rwlock_init(&bdev->vm_lock);
-	spin_lock_init(&glob->lru_lock);
-
 	bdev->driver = driver;
 
 	memset(bdev->man, 0, sizeof(bdev->man));
-- 
cgit v1.2.3


From 759e4f83f418f4001e724042b4c0e408d615d9ec Mon Sep 17 00:00:00 2001
From: Thomas Hellstrom <thellstrom@vmware.com>
Date: Thu, 20 Aug 2009 10:29:09 +0200
Subject: drm/ttm: Fixes for "Memory accounting rework."

ttm:
Fix error paths when kobject_add returns an error.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/ttm/ttm_memory.c | 36 ++++++++++++++++++++++++++++--------
 1 file changed, 28 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/ttm/ttm_memory.c b/drivers/gpu/drm/ttm/ttm_memory.c
index 62fb5cf0899..072c281a6bb 100644
--- a/drivers/gpu/drm/ttm/ttm_memory.c
+++ b/drivers/gpu/drm/ttm/ttm_memory.c
@@ -244,6 +244,7 @@ static int ttm_mem_init_kernel_zone(struct ttm_mem_global *glob,
 {
 	struct ttm_mem_zone *zone = kzalloc(sizeof(*zone), GFP_KERNEL);
 	uint64_t mem;
+	int ret;
 
 	if (unlikely(!zone))
 		return -ENOMEM;
@@ -259,9 +260,14 @@ static int ttm_mem_init_kernel_zone(struct ttm_mem_global *glob,
 	zone->used_mem = 0;
 	zone->glob = glob;
 	glob->zone_kernel = zone;
-	glob->zones[glob->num_zones++] = zone;
 	kobject_init(&zone->kobj, &ttm_mem_zone_kobj_type);
-	return kobject_add(&zone->kobj, &glob->kobj, zone->name);
+	ret = kobject_add(&zone->kobj, &glob->kobj, zone->name);
+	if (unlikely(ret != 0)) {
+		kobject_put(&zone->kobj);
+		return ret;
+	}
+	glob->zones[glob->num_zones++] = zone;
+	return 0;
 }
 
 #ifdef CONFIG_HIGHMEM
@@ -270,6 +276,7 @@ static int ttm_mem_init_highmem_zone(struct ttm_mem_global *glob,
 {
 	struct ttm_mem_zone *zone = kzalloc(sizeof(*zone), GFP_KERNEL);
 	uint64_t mem;
+	int ret;
 
 	if (unlikely(!zone))
 		return -ENOMEM;
@@ -288,9 +295,14 @@ static int ttm_mem_init_highmem_zone(struct ttm_mem_global *glob,
 	zone->used_mem = 0;
 	zone->glob = glob;
 	glob->zone_highmem = zone;
-	glob->zones[glob->num_zones++] = zone;
 	kobject_init(&zone->kobj, &ttm_mem_zone_kobj_type);
-	return kobject_add(&zone->kobj, &glob->kobj, zone->name);
+	ret = kobject_add(&zone->kobj, &glob->kobj, zone->name);
+	if (unlikely(ret != 0)) {
+		kobject_put(&zone->kobj);
+		return ret;
+	}
+	glob->zones[glob->num_zones++] = zone;
+	return 0;
 }
 #else
 static int ttm_mem_init_dma32_zone(struct ttm_mem_global *glob,
@@ -298,6 +310,7 @@ static int ttm_mem_init_dma32_zone(struct ttm_mem_global *glob,
 {
 	struct ttm_mem_zone *zone = kzalloc(sizeof(*zone), GFP_KERNEL);
 	uint64_t mem;
+	int ret;
 
 	if (unlikely(!zone))
 		return -ENOMEM;
@@ -327,9 +340,14 @@ static int ttm_mem_init_dma32_zone(struct ttm_mem_global *glob,
 	zone->used_mem = 0;
 	zone->glob = glob;
 	glob->zone_dma32 = zone;
-	glob->zones[glob->num_zones++] = zone;
 	kobject_init(&zone->kobj, &ttm_mem_zone_kobj_type);
-	return kobject_add(&zone->kobj, &glob->kobj, zone->name);
+	ret = kobject_add(&zone->kobj, &glob->kobj, zone->name);
+	if (unlikely(ret != 0)) {
+		kobject_put(&zone->kobj);
+		return ret;
+	}
+	glob->zones[glob->num_zones++] = zone;
+	return 0;
 }
 #endif
 
@@ -348,8 +366,10 @@ int ttm_mem_global_init(struct ttm_mem_global *glob)
 	ret = kobject_add(&glob->kobj,
 			  ttm_get_kobj(),
 			  "memory_accounting");
-	if (unlikely(ret != 0))
-		goto out_no_zone;
+	if (unlikely(ret != 0)) {
+		kobject_put(&glob->kobj);
+		return ret;
+	}
 
 	si_meminfo(&si);
 
-- 
cgit v1.2.3


From 50f153036c9d9e4ae1768d5ca9c2ad4184f7a0b7 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Fri, 21 Aug 2009 13:21:01 +1000
Subject: drm/radeon/kms: generate the safe register tables.

Previously we just made these offline and included them,
but no reason we can't generate them at build time.

TODO: add rs690 + r100/r200 when done.
should we do rs480/rs690 no tcl version?

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/Makefile       |  15 +
 drivers/gpu/drm/radeon/mkregtable.c   | 726 +++++++++++++++++++++++++++++++++
 drivers/gpu/drm/radeon/r300.c         |  45 +--
 drivers/gpu/drm/radeon/reg_srcs/r300  | 728 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/radeon/reg_srcs/rv515 | 486 +++++++++++++++++++++++
 drivers/gpu/drm/radeon/rv515.c        |  64 +--
 6 files changed, 1960 insertions(+), 104 deletions(-)
 create mode 100644 drivers/gpu/drm/radeon/mkregtable.c
 create mode 100644 drivers/gpu/drm/radeon/reg_srcs/r300
 create mode 100644 drivers/gpu/drm/radeon/reg_srcs/rv515

diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index 013d3805994..8e1771889b4 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -6,6 +6,21 @@ ccflags-y := -Iinclude/drm
 radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \
 	radeon_irq.o r300_cmdbuf.o r600_cp.o
 
+hostprogs-y := mkregtable
+
+quiet_cmd_mkregtable = MKREGTABLE $@
+      cmd_mkregtable = $(obj)/mkregtable $< > $@
+
+$(obj)/rv515_reg_safe.h: $(src)/reg_srcs/rv515 $(obj)/mkregtable
+	$(call if_changed,mkregtable)
+
+$(obj)/r300_reg_safe.h: $(src)/reg_srcs/r300 $(obj)/mkregtable
+	$(call if_changed,mkregtable)
+
+$(obj)/rv515.o: $(obj)/rv515_reg_safe.h
+
+$(obj)/r300.o: $(obj)/r300_reg_safe.h
+
 radeon-$(CONFIG_DRM_RADEON_KMS) += radeon_device.o radeon_kms.o \
 	radeon_atombios.o radeon_agp.o atombios_crtc.o radeon_combios.o \
 	atom.o radeon_fence.o radeon_ttm.o radeon_object.o radeon_gart.o \
diff --git a/drivers/gpu/drm/radeon/mkregtable.c b/drivers/gpu/drm/radeon/mkregtable.c
new file mode 100644
index 00000000000..0acd1cf8c36
--- /dev/null
+++ b/drivers/gpu/drm/radeon/mkregtable.c
@@ -0,0 +1,726 @@
+/* utility to create the register check tables
+ * this includes inlined list.h safe for userspace.
+ *
+ * Copyright 2009 Jerome Glisse
+ * Copyright 2009 Red Hat Inc.
+ *
+ * Authors:
+ * 	Jerome Glisse
+ * 	Dave Airlie
+ */
+
+#include <sys/types.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include <regex.h>
+#include <libgen.h>
+
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @ptr:    the pointer to the member.
+ * @type:   the type of the container struct this is embedded in.
+ * @member: the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({          \
+    const typeof( ((type *)0)->member ) *__mptr = (ptr);    \
+        (type *)( (char *)__mptr - offsetof(type,member) );})
+
+
+
+/*
+ * Simple doubly linked list implementation.
+ *
+ * Some of the internal functions ("__xxx") are useful when
+ * manipulating whole lists rather than single entries, as
+ * sometimes we already know the next/prev entries and we can
+ * generate better code by using them directly rather than
+ * using the generic single-entry routines.
+ */
+
+struct list_head {
+	struct list_head *next, *prev;
+};
+
+#define LIST_HEAD_INIT(name) { &(name), &(name) }
+
+#define LIST_HEAD(name) \
+	struct list_head name = LIST_HEAD_INIT(name)
+
+static inline void INIT_LIST_HEAD(struct list_head *list)
+{
+	list->next = list;
+	list->prev = list;
+}
+
+/*
+ * Insert a new entry between two known consecutive entries.
+ *
+ * This is only for internal list manipulation where we know
+ * the prev/next entries already!
+ */
+#ifndef CONFIG_DEBUG_LIST
+static inline void __list_add(struct list_head *new,
+			      struct list_head *prev,
+			      struct list_head *next)
+{
+	next->prev = new;
+	new->next = next;
+	new->prev = prev;
+	prev->next = new;
+}
+#else
+extern void __list_add(struct list_head *new,
+			      struct list_head *prev,
+			      struct list_head *next);
+#endif
+
+/**
+ * list_add - add a new entry
+ * @new: new entry to be added
+ * @head: list head to add it after
+ *
+ * Insert a new entry after the specified head.
+ * This is good for implementing stacks.
+ */
+static inline void list_add(struct list_head *new, struct list_head *head)
+{
+	__list_add(new, head, head->next);
+}
+
+
+/**
+ * list_add_tail - add a new entry
+ * @new: new entry to be added
+ * @head: list head to add it before
+ *
+ * Insert a new entry before the specified head.
+ * This is useful for implementing queues.
+ */
+static inline void list_add_tail(struct list_head *new, struct list_head *head)
+{
+	__list_add(new, head->prev, head);
+}
+
+/*
+ * Delete a list entry by making the prev/next entries
+ * point to each other.
+ *
+ * This is only for internal list manipulation where we know
+ * the prev/next entries already!
+ */
+static inline void __list_del(struct list_head * prev, struct list_head * next)
+{
+	next->prev = prev;
+	prev->next = next;
+}
+
+/**
+ * list_del - deletes entry from list.
+ * @entry: the element to delete from the list.
+ * Note: list_empty() on entry does not return true after this, the entry is
+ * in an undefined state.
+ */
+#ifndef CONFIG_DEBUG_LIST
+static inline void list_del(struct list_head *entry)
+{
+	__list_del(entry->prev, entry->next);
+	entry->next = (void*)0xDEADBEEF;
+	entry->prev = (void*)0xBEEFDEAD;
+}
+#else
+extern void list_del(struct list_head *entry);
+#endif
+
+/**
+ * list_replace - replace old entry by new one
+ * @old : the element to be replaced
+ * @new : the new element to insert
+ *
+ * If @old was empty, it will be overwritten.
+ */
+static inline void list_replace(struct list_head *old,
+				struct list_head *new)
+{
+	new->next = old->next;
+	new->next->prev = new;
+	new->prev = old->prev;
+	new->prev->next = new;
+}
+
+static inline void list_replace_init(struct list_head *old,
+					struct list_head *new)
+{
+	list_replace(old, new);
+	INIT_LIST_HEAD(old);
+}
+
+/**
+ * list_del_init - deletes entry from list and reinitialize it.
+ * @entry: the element to delete from the list.
+ */
+static inline void list_del_init(struct list_head *entry)
+{
+	__list_del(entry->prev, entry->next);
+	INIT_LIST_HEAD(entry);
+}
+
+/**
+ * list_move - delete from one list and add as another's head
+ * @list: the entry to move
+ * @head: the head that will precede our entry
+ */
+static inline void list_move(struct list_head *list, struct list_head *head)
+{
+	__list_del(list->prev, list->next);
+	list_add(list, head);
+}
+
+/**
+ * list_move_tail - delete from one list and add as another's tail
+ * @list: the entry to move
+ * @head: the head that will follow our entry
+ */
+static inline void list_move_tail(struct list_head *list,
+				  struct list_head *head)
+{
+	__list_del(list->prev, list->next);
+	list_add_tail(list, head);
+}
+
+/**
+ * list_is_last - tests whether @list is the last entry in list @head
+ * @list: the entry to test
+ * @head: the head of the list
+ */
+static inline int list_is_last(const struct list_head *list,
+				const struct list_head *head)
+{
+	return list->next == head;
+}
+
+/**
+ * list_empty - tests whether a list is empty
+ * @head: the list to test.
+ */
+static inline int list_empty(const struct list_head *head)
+{
+	return head->next == head;
+}
+
+/**
+ * list_empty_careful - tests whether a list is empty and not being modified
+ * @head: the list to test
+ *
+ * Description:
+ * tests whether a list is empty _and_ checks that no other CPU might be
+ * in the process of modifying either member (next or prev)
+ *
+ * NOTE: using list_empty_careful() without synchronization
+ * can only be safe if the only activity that can happen
+ * to the list entry is list_del_init(). Eg. it cannot be used
+ * if another CPU could re-list_add() it.
+ */
+static inline int list_empty_careful(const struct list_head *head)
+{
+	struct list_head *next = head->next;
+	return (next == head) && (next == head->prev);
+}
+
+/**
+ * list_is_singular - tests whether a list has just one entry.
+ * @head: the list to test.
+ */
+static inline int list_is_singular(const struct list_head *head)
+{
+	return !list_empty(head) && (head->next == head->prev);
+}
+
+static inline void __list_cut_position(struct list_head *list,
+		struct list_head *head, struct list_head *entry)
+{
+	struct list_head *new_first = entry->next;
+	list->next = head->next;
+	list->next->prev = list;
+	list->prev = entry;
+	entry->next = list;
+	head->next = new_first;
+	new_first->prev = head;
+}
+
+/**
+ * list_cut_position - cut a list into two
+ * @list: a new list to add all removed entries
+ * @head: a list with entries
+ * @entry: an entry within head, could be the head itself
+ *	and if so we won't cut the list
+ *
+ * This helper moves the initial part of @head, up to and
+ * including @entry, from @head to @list. You should
+ * pass on @entry an element you know is on @head. @list
+ * should be an empty list or a list you do not care about
+ * losing its data.
+ *
+ */
+static inline void list_cut_position(struct list_head *list,
+		struct list_head *head, struct list_head *entry)
+{
+	if (list_empty(head))
+		return;
+	if (list_is_singular(head) &&
+		(head->next != entry && head != entry))
+		return;
+	if (entry == head)
+		INIT_LIST_HEAD(list);
+	else
+		__list_cut_position(list, head, entry);
+}
+
+static inline void __list_splice(const struct list_head *list,
+				 struct list_head *prev,
+				 struct list_head *next)
+{
+	struct list_head *first = list->next;
+	struct list_head *last = list->prev;
+
+	first->prev = prev;
+	prev->next = first;
+
+	last->next = next;
+	next->prev = last;
+}
+
+/**
+ * list_splice - join two lists, this is designed for stacks
+ * @list: the new list to add.
+ * @head: the place to add it in the first list.
+ */
+static inline void list_splice(const struct list_head *list,
+				struct list_head *head)
+{
+	if (!list_empty(list))
+		__list_splice(list, head, head->next);
+}
+
+/**
+ * list_splice_tail - join two lists, each list being a queue
+ * @list: the new list to add.
+ * @head: the place to add it in the first list.
+ */
+static inline void list_splice_tail(struct list_head *list,
+				struct list_head *head)
+{
+	if (!list_empty(list))
+		__list_splice(list, head->prev, head);
+}
+
+/**
+ * list_splice_init - join two lists and reinitialise the emptied list.
+ * @list: the new list to add.
+ * @head: the place to add it in the first list.
+ *
+ * The list at @list is reinitialised
+ */
+static inline void list_splice_init(struct list_head *list,
+				    struct list_head *head)
+{
+	if (!list_empty(list)) {
+		__list_splice(list, head, head->next);
+		INIT_LIST_HEAD(list);
+	}
+}
+
+/**
+ * list_splice_tail_init - join two lists and reinitialise the emptied list
+ * @list: the new list to add.
+ * @head: the place to add it in the first list.
+ *
+ * Each of the lists is a queue.
+ * The list at @list is reinitialised
+ */
+static inline void list_splice_tail_init(struct list_head *list,
+					 struct list_head *head)
+{
+	if (!list_empty(list)) {
+		__list_splice(list, head->prev, head);
+		INIT_LIST_HEAD(list);
+	}
+}
+
+/**
+ * list_entry - get the struct for this entry
+ * @ptr:	the &struct list_head pointer.
+ * @type:	the type of the struct this is embedded in.
+ * @member:	the name of the list_struct within the struct.
+ */
+#define list_entry(ptr, type, member) \
+	container_of(ptr, type, member)
+
+/**
+ * list_first_entry - get the first element from a list
+ * @ptr:	the list head to take the element from.
+ * @type:	the type of the struct this is embedded in.
+ * @member:	the name of the list_struct within the struct.
+ *
+ * Note, that list is expected to be not empty.
+ */
+#define list_first_entry(ptr, type, member) \
+	list_entry((ptr)->next, type, member)
+
+/**
+ * list_for_each	-	iterate over a list
+ * @pos:	the &struct list_head to use as a loop cursor.
+ * @head:	the head for your list.
+ */
+#define list_for_each(pos, head) \
+	for (pos = (head)->next; prefetch(pos->next), pos != (head); \
+        	pos = pos->next)
+
+/**
+ * __list_for_each	-	iterate over a list
+ * @pos:	the &struct list_head to use as a loop cursor.
+ * @head:	the head for your list.
+ *
+ * This variant differs from list_for_each() in that it's the
+ * simplest possible list iteration code, no prefetching is done.
+ * Use this for code that knows the list to be very short (empty
+ * or 1 entry) most of the time.
+ */
+#define __list_for_each(pos, head) \
+	for (pos = (head)->next; pos != (head); pos = pos->next)
+
+/**
+ * list_for_each_prev	-	iterate over a list backwards
+ * @pos:	the &struct list_head to use as a loop cursor.
+ * @head:	the head for your list.
+ */
+#define list_for_each_prev(pos, head) \
+	for (pos = (head)->prev; prefetch(pos->prev), pos != (head); \
+        	pos = pos->prev)
+
+/**
+ * list_for_each_safe - iterate over a list safe against removal of list entry
+ * @pos:	the &struct list_head to use as a loop cursor.
+ * @n:		another &struct list_head to use as temporary storage
+ * @head:	the head for your list.
+ */
+#define list_for_each_safe(pos, n, head) \
+	for (pos = (head)->next, n = pos->next; pos != (head); \
+		pos = n, n = pos->next)
+
+/**
+ * list_for_each_prev_safe - iterate over a list backwards safe against removal of list entry
+ * @pos:	the &struct list_head to use as a loop cursor.
+ * @n:		another &struct list_head to use as temporary storage
+ * @head:	the head for your list.
+ */
+#define list_for_each_prev_safe(pos, n, head) \
+	for (pos = (head)->prev, n = pos->prev; \
+	     prefetch(pos->prev), pos != (head); \
+	     pos = n, n = pos->prev)
+
+/**
+ * list_for_each_entry	-	iterate over list of given type
+ * @pos:	the type * to use as a loop cursor.
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ */
+#define list_for_each_entry(pos, head, member)				\
+	for (pos = list_entry((head)->next, typeof(*pos), member);	\
+	     &pos->member != (head); 	\
+	     pos = list_entry(pos->member.next, typeof(*pos), member))
+
+/**
+ * list_for_each_entry_reverse - iterate backwards over list of given type.
+ * @pos:	the type * to use as a loop cursor.
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ */
+#define list_for_each_entry_reverse(pos, head, member)			\
+	for (pos = list_entry((head)->prev, typeof(*pos), member);	\
+	     prefetch(pos->member.prev), &pos->member != (head); 	\
+	     pos = list_entry(pos->member.prev, typeof(*pos), member))
+
+/**
+ * list_prepare_entry - prepare a pos entry for use in list_for_each_entry_continue()
+ * @pos:	the type * to use as a start point
+ * @head:	the head of the list
+ * @member:	the name of the list_struct within the struct.
+ *
+ * Prepares a pos entry for use as a start point in list_for_each_entry_continue().
+ */
+#define list_prepare_entry(pos, head, member) \
+	((pos) ? : list_entry(head, typeof(*pos), member))
+
+/**
+ * list_for_each_entry_continue - continue iteration over list of given type
+ * @pos:	the type * to use as a loop cursor.
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ *
+ * Continue to iterate over list of given type, continuing after
+ * the current position.
+ */
+#define list_for_each_entry_continue(pos, head, member) 		\
+	for (pos = list_entry(pos->member.next, typeof(*pos), member);	\
+	     prefetch(pos->member.next), &pos->member != (head);	\
+	     pos = list_entry(pos->member.next, typeof(*pos), member))
+
+/**
+ * list_for_each_entry_continue_reverse - iterate backwards from the given point
+ * @pos:	the type * to use as a loop cursor.
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ *
+ * Start to iterate over list of given type backwards, continuing after
+ * the current position.
+ */
+#define list_for_each_entry_continue_reverse(pos, head, member)		\
+	for (pos = list_entry(pos->member.prev, typeof(*pos), member);	\
+	     prefetch(pos->member.prev), &pos->member != (head);	\
+	     pos = list_entry(pos->member.prev, typeof(*pos), member))
+
+/**
+ * list_for_each_entry_from - iterate over list of given type from the current point
+ * @pos:	the type * to use as a loop cursor.
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ *
+ * Iterate over list of given type, continuing from current position.
+ */
+#define list_for_each_entry_from(pos, head, member) 			\
+	for (; prefetch(pos->member.next), &pos->member != (head);	\
+	     pos = list_entry(pos->member.next, typeof(*pos), member))
+
+/**
+ * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry
+ * @pos:	the type * to use as a loop cursor.
+ * @n:		another type * to use as temporary storage
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ */
+#define list_for_each_entry_safe(pos, n, head, member)			\
+	for (pos = list_entry((head)->next, typeof(*pos), member),	\
+		n = list_entry(pos->member.next, typeof(*pos), member);	\
+	     &pos->member != (head); 					\
+	     pos = n, n = list_entry(n->member.next, typeof(*n), member))
+
+/**
+ * list_for_each_entry_safe_continue
+ * @pos:	the type * to use as a loop cursor.
+ * @n:		another type * to use as temporary storage
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ *
+ * Iterate over list of given type, continuing after current point,
+ * safe against removal of list entry.
+ */
+#define list_for_each_entry_safe_continue(pos, n, head, member) 		\
+	for (pos = list_entry(pos->member.next, typeof(*pos), member), 		\
+		n = list_entry(pos->member.next, typeof(*pos), member);		\
+	     &pos->member != (head);						\
+	     pos = n, n = list_entry(n->member.next, typeof(*n), member))
+
+/**
+ * list_for_each_entry_safe_from
+ * @pos:	the type * to use as a loop cursor.
+ * @n:		another type * to use as temporary storage
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ *
+ * Iterate over list of given type from current point, safe against
+ * removal of list entry.
+ */
+#define list_for_each_entry_safe_from(pos, n, head, member) 			\
+	for (n = list_entry(pos->member.next, typeof(*pos), member);		\
+	     &pos->member != (head);						\
+	     pos = n, n = list_entry(n->member.next, typeof(*n), member))
+
+/**
+ * list_for_each_entry_safe_reverse
+ * @pos:	the type * to use as a loop cursor.
+ * @n:		another type * to use as temporary storage
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ *
+ * Iterate backwards over list of given type, safe against removal
+ * of list entry.
+ */
+#define list_for_each_entry_safe_reverse(pos, n, head, member)		\
+	for (pos = list_entry((head)->prev, typeof(*pos), member),	\
+		n = list_entry(pos->member.prev, typeof(*pos), member);	\
+	     &pos->member != (head); 					\
+	     pos = n, n = list_entry(n->member.prev, typeof(*n), member))
+
+struct offset {
+    struct list_head    list;
+    unsigned            offset;
+};
+
+struct table {
+    struct list_head    offsets;
+    unsigned            offset_max;
+    unsigned            nentry;
+    unsigned            *table;
+    char 	*gpu_prefix;
+};
+
+struct offset* offset_new(unsigned o)
+{
+    struct offset *offset;
+
+    offset = (struct offset*)malloc(sizeof(struct offset));
+    if (offset) {
+        INIT_LIST_HEAD(&offset->list);
+        offset->offset = o;
+    }
+    return offset;
+}
+
+void table_offset_add(struct table *t, struct offset *offset)
+{
+    list_add_tail(&offset->list, &t->offsets);
+}
+
+void table_init(struct table *t)
+{
+    INIT_LIST_HEAD(&t->offsets);
+    t->offset_max = 0;
+    t->nentry = 0;
+    t->table = NULL;
+}
+
+void table_print(struct table *t)
+{
+    unsigned nlloop, i, j, n, c, id;
+
+    nlloop = (t->nentry + 3) / 4;
+    c = t->nentry;
+    printf("static const unsigned %s_reg_safe_bm[%d] = {\n", t->gpu_prefix, t->nentry);
+    for(i = 0, id = 0; i < nlloop; i++) {
+        n = 4;
+        if (n > c) {
+            n = c;
+        }
+        c -= n;
+        for(j = 0; j < n; j++) {
+	    if (j == 0) printf("\t");
+	    else printf(" ");
+            printf("0x%08X,", t->table[id++]);
+        }
+        printf("\n");
+    }
+    printf("};\n");
+}
+
+int table_build(struct table *t)
+{
+    struct offset *offset;
+    unsigned i, m;
+
+    t->nentry = ((t->offset_max >> 2) + 31) / 32;
+    t->table = (unsigned*)malloc(sizeof(unsigned) * t->nentry);
+    if (t->table == NULL) {
+        return -1;
+    }
+    memset(t->table, 0xff, sizeof(unsigned) * t->nentry);
+    list_for_each_entry(offset, &t->offsets, list) {
+        i = (offset->offset >> 2) / 32;
+        m = (offset->offset >> 2) & 31;
+        m = 1 << m;
+        t->table[i] ^= m;
+    }
+    return 0;
+}
+
+static char gpu_name[10];
+int parser_auth(struct table *t, const char *filename)
+{
+    FILE *file;
+    regex_t mask_rex;
+    regmatch_t match[4];
+    char buf[1024];
+    size_t end;
+    int len;
+    int done = 0;
+    int r;
+    unsigned o;
+    struct offset *offset;
+    char last_reg_s[10];
+    int last_reg;
+    
+    if (regcomp(&mask_rex, "(0x[0-9a-fA-F]*) *([_a-zA-Z0-9]*)", REG_EXTENDED)) {
+        fprintf(stderr, "Failed to compile regular expression\n");
+        return -1;
+    }
+    file = fopen(filename, "r");
+    if (file == NULL) {
+        fprintf(stderr, "Failed to open: %s\n", filename);
+        return -1;
+    }
+    fseek(file, 0, SEEK_END);
+    end = ftell(file);
+    fseek(file, 0, SEEK_SET);
+
+    /* get header */
+    if (fgets(buf, 1024, file) == NULL)
+        return -1;
+
+    /* first line will contain the last register 
+     * and gpu name */
+    sscanf(buf, "%s %s", gpu_name, last_reg_s);
+    t->gpu_prefix = gpu_name;
+    last_reg = strtol(last_reg_s, NULL, 16);
+
+    do {
+        if (fgets(buf, 1024, file) == NULL)
+            return -1;
+        len = strlen(buf);
+        if (ftell(file) == end) {
+            done = 1;
+        }
+        if (len) {
+            r = regexec(&mask_rex, buf, 4, match, 0);
+            if (r == REG_NOMATCH) {
+            } else if (r) {
+                fprintf(stderr, "Error matching regular expression %d in %s\n",
+                        r, filename);
+                return -1;
+            } else {
+                buf[match[0].rm_eo] = 0;
+                buf[match[1].rm_eo] = 0;
+                buf[match[2].rm_eo] = 0;
+                o = strtol(&buf[match[1].rm_so], NULL, 16);
+                offset = offset_new(o);
+                table_offset_add(t, offset);
+                if (o > t->offset_max) {
+                    t->offset_max = o;
+                }
+            }
+        }
+    } while (!done);
+    fclose(file);
+    if (t->offset_max < last_reg)
+	t->offset_max = last_reg;
+    return table_build(t);
+}
+
+int main(int argc, char *argv[])
+{
+    struct table t;
+
+    if (argc != 2) {
+        fprintf(stderr, "Usage: %s <authfile>\n",
+                argv[0]);
+        exit(1);
+    }
+    table_init(&t);
+    if (parser_auth(&t, argv[1])) {
+        fprintf(stderr, "Failed to parse file %s\n", argv[1]);
+        return -1;
+    }
+    table_print(&t);
+    return 0;
+}
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index c47579dcafa..482d6b296b7 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -33,6 +33,8 @@
 #include "radeon_drm.h"
 #include "radeon_share.h"
 
+#include "r300_reg_safe.h"
+
 /* r300,r350,rv350,rv370,rv380 depends on : */
 void r100_hdp_reset(struct radeon_device *rdev);
 int r100_cp_reset(struct radeon_device *rdev);
@@ -953,49 +955,6 @@ static inline void r300_cs_track_clear(struct r300_cs_track *track)
 	}
 }
 
-static const unsigned r300_reg_safe_bm[159] = {
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF,
-	0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000,
-	0xF0000078, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFC78, 0xFFFFFFFF, 0xFFFFFFFE, 0xFFFFFFFF,
-	0x38FF8F50, 0xFFF88082, 0xF000000C, 0xFAE009FF,
-	0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
-	0x00000000, 0x0000C100, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0xFFFF0000, 0xFFFFFFFF, 0xFF80FFFF,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x0003FC01, 0xFFFFFFF8, 0xFE800B19,
-};
-
 static int r300_packet0_check(struct radeon_cs_parser *p,
 		struct radeon_cs_packet *pkt,
 		unsigned idx, unsigned reg)
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r300 b/drivers/gpu/drm/radeon/reg_srcs/r300
new file mode 100644
index 00000000000..b4bd5b64fcb
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/r300
@@ -0,0 +1,728 @@
+r300 0x4f60
+0x1434 SRC_Y_X
+0x1438 DST_Y_X
+0x143C DST_HEIGHT_WIDTH
+0x146C DP_GUI_MASTER_CNTL
+0x1474 BRUSH_Y_X
+0x1478 DP_BRUSH_BKGD_CLR
+0x147C DP_BRUSH_FRGD_CLR
+0x1480 BRUSH_DATA0
+0x1484 BRUSH_DATA1
+0x1598 DST_WIDTH_HEIGHT
+0x15C0 CLR_CMP_CNTL
+0x15C4 CLR_CMP_CLR_SRC
+0x15C8 CLR_CMP_CLR_DST
+0x15CC CLR_CMP_MSK
+0x15D8 DP_SRC_FRGD_CLR
+0x15DC DP_SRC_BKGD_CLR
+0x1600 DST_LINE_START
+0x1604 DST_LINE_END
+0x1608 DST_LINE_PATCOUNT
+0x16C0 DP_CNTL
+0x16CC DP_WRITE_MSK
+0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
+0x16E8 DEFAULT_SC_BOTTOM_RIGHT
+0x16EC SC_TOP_LEFT
+0x16F0 SC_BOTTOM_RIGHT
+0x16F4 SRC_SC_BOTTOM_RIGHT
+0x1714 DSTCACHE_CTLSTAT
+0x1720 WAIT_UNTIL
+0x172C RBBM_GUICNTL
+0x1D98 VAP_VPORT_XSCALE
+0x1D9C VAP_VPORT_XOFFSET
+0x1DA0 VAP_VPORT_YSCALE
+0x1DA4 VAP_VPORT_YOFFSET
+0x1DA8 VAP_VPORT_ZSCALE
+0x1DAC VAP_VPORT_ZOFFSET
+0x2080 VAP_CNTL
+0x2090 VAP_OUT_VTX_FMT_0
+0x2094 VAP_OUT_VTX_FMT_1
+0x20B0 VAP_VTE_CNTL
+0x2138 VAP_VF_MIN_VTX_INDX
+0x2140 VAP_CNTL_STATUS
+0x2150 VAP_PROG_STREAM_CNTL_0
+0x2154 VAP_PROG_STREAM_CNTL_1
+0x2158 VAP_PROG_STREAM_CNTL_2
+0x215C VAP_PROG_STREAM_CNTL_3
+0x2160 VAP_PROG_STREAM_CNTL_4
+0x2164 VAP_PROG_STREAM_CNTL_5
+0x2168 VAP_PROG_STREAM_CNTL_6
+0x216C VAP_PROG_STREAM_CNTL_7
+0x2180 VAP_VTX_STATE_CNTL
+0x2184 VAP_VSM_VTX_ASSM
+0x2188 VAP_VTX_STATE_IND_REG_0
+0x218C VAP_VTX_STATE_IND_REG_1
+0x2190 VAP_VTX_STATE_IND_REG_2
+0x2194 VAP_VTX_STATE_IND_REG_3
+0x2198 VAP_VTX_STATE_IND_REG_4
+0x219C VAP_VTX_STATE_IND_REG_5
+0x21A0 VAP_VTX_STATE_IND_REG_6
+0x21A4 VAP_VTX_STATE_IND_REG_7
+0x21A8 VAP_VTX_STATE_IND_REG_8
+0x21AC VAP_VTX_STATE_IND_REG_9
+0x21B0 VAP_VTX_STATE_IND_REG_10
+0x21B4 VAP_VTX_STATE_IND_REG_11
+0x21B8 VAP_VTX_STATE_IND_REG_12
+0x21BC VAP_VTX_STATE_IND_REG_13
+0x21C0 VAP_VTX_STATE_IND_REG_14
+0x21C4 VAP_VTX_STATE_IND_REG_15
+0x21DC VAP_PSC_SGN_NORM_CNTL
+0x21E0 VAP_PROG_STREAM_CNTL_EXT_0
+0x21E4 VAP_PROG_STREAM_CNTL_EXT_1
+0x21E8 VAP_PROG_STREAM_CNTL_EXT_2
+0x21EC VAP_PROG_STREAM_CNTL_EXT_3
+0x21F0 VAP_PROG_STREAM_CNTL_EXT_4
+0x21F4 VAP_PROG_STREAM_CNTL_EXT_5
+0x21F8 VAP_PROG_STREAM_CNTL_EXT_6
+0x21FC VAP_PROG_STREAM_CNTL_EXT_7
+0x2200 VAP_PVS_VECTOR_INDX_REG
+0x2204 VAP_PVS_VECTOR_DATA_REG
+0x2208 VAP_PVS_VECTOR_DATA_REG_128
+0x221C VAP_CLIP_CNTL
+0x2220 VAP_GB_VERT_CLIP_ADJ
+0x2224 VAP_GB_VERT_DISC_ADJ
+0x2228 VAP_GB_HORZ_CLIP_ADJ
+0x222C VAP_GB_HORZ_DISC_ADJ
+0x2230 VAP_PVS_FLOW_CNTL_ADDRS_0
+0x2234 VAP_PVS_FLOW_CNTL_ADDRS_1
+0x2238 VAP_PVS_FLOW_CNTL_ADDRS_2
+0x223C VAP_PVS_FLOW_CNTL_ADDRS_3
+0x2240 VAP_PVS_FLOW_CNTL_ADDRS_4
+0x2244 VAP_PVS_FLOW_CNTL_ADDRS_5
+0x2248 VAP_PVS_FLOW_CNTL_ADDRS_6
+0x224C VAP_PVS_FLOW_CNTL_ADDRS_7
+0x2250 VAP_PVS_FLOW_CNTL_ADDRS_8
+0x2254 VAP_PVS_FLOW_CNTL_ADDRS_9
+0x2258 VAP_PVS_FLOW_CNTL_ADDRS_10
+0x225C VAP_PVS_FLOW_CNTL_ADDRS_11
+0x2260 VAP_PVS_FLOW_CNTL_ADDRS_12
+0x2264 VAP_PVS_FLOW_CNTL_ADDRS_13
+0x2268 VAP_PVS_FLOW_CNTL_ADDRS_14
+0x226C VAP_PVS_FLOW_CNTL_ADDRS_15
+0x2284 VAP_PVS_STATE_FLUSH_REG
+0x2288 VAP_PVS_VTX_TIMEOUT_REG
+0x2290 VAP_PVS_FLOW_CNTL_LOOP_INDEX_0
+0x2294 VAP_PVS_FLOW_CNTL_LOOP_INDEX_1
+0x2298 VAP_PVS_FLOW_CNTL_LOOP_INDEX_2
+0x229C VAP_PVS_FLOW_CNTL_LOOP_INDEX_3
+0x22A0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_4
+0x22A4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_5
+0x22A8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_6
+0x22AC VAP_PVS_FLOW_CNTL_LOOP_INDEX_7
+0x22B0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_8
+0x22B4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_9
+0x22B8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_10
+0x22BC VAP_PVS_FLOW_CNTL_LOOP_INDEX_11
+0x22C0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_12
+0x22C4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_13
+0x22C8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_14
+0x22CC VAP_PVS_FLOW_CNTL_LOOP_INDEX_15
+0x22D0 VAP_PVS_CODE_CNTL_0
+0x22D4 VAP_PVS_CONST_CNTL
+0x22D8 VAP_PVS_CODE_CNTL_1
+0x22DC VAP_PVS_FLOW_CNTL_OPC
+0x342C RB2D_DSTCACHE_CTLSTAT
+0x4000 GB_VAP_RASTER_VTX_FMT_0
+0x4004 GB_VAP_RASTER_VTX_FMT_1
+0x4008 GB_ENABLE
+0x401C GB_SELECT
+0x4020 GB_AA_CONFIG
+0x4024 GB_FIFO_SIZE
+0x4100 TX_INVALTAGS
+0x4200 GA_POINT_S0
+0x4204 GA_POINT_T0
+0x4208 GA_POINT_S1
+0x420C GA_POINT_T1
+0x4214 GA_TRIANGLE_STIPPLE
+0x421C GA_POINT_SIZE
+0x4230 GA_POINT_MINMAX
+0x4234 GA_LINE_CNTL
+0x4238 GA_LINE_STIPPLE_CONFIG
+0x4260 GA_LINE_STIPPLE_VALUE
+0x4264 GA_LINE_S0
+0x4268 GA_LINE_S1
+0x4278 GA_COLOR_CONTROL
+0x427C GA_SOLID_RG
+0x4280 GA_SOLID_BA
+0x4288 GA_POLY_MODE
+0x428C GA_ROUND_MODE
+0x4290 GA_OFFSET
+0x4294 GA_FOG_SCALE
+0x4298 GA_FOG_OFFSET
+0x42A0 SU_TEX_WRAP
+0x42A4 SU_POLY_OFFSET_FRONT_SCALE
+0x42A8 SU_POLY_OFFSET_FRONT_OFFSET
+0x42AC SU_POLY_OFFSET_BACK_SCALE
+0x42B0 SU_POLY_OFFSET_BACK_OFFSET 
+0x42B4 SU_POLY_OFFSET_ENABLE
+0x42B8 SU_CULL_MODE
+0x42C0 SU_DEPTH_SCALE
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+0x4338 RS_INST_2
+0x433C RS_INST_3
+0x4340 RS_INST_4
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+0x4348 RS_INST_6
+0x434C RS_INST_7
+0x4350 RS_INST_8
+0x4354 RS_INST_9
+0x4358 RS_INST_10
+0x435C RS_INST_11
+0x4360 RS_INST_12
+0x4364 RS_INST_13
+0x4368 RS_INST_14
+0x436C RS_INST_15
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+0x43B0 SC_CLIP_0_A
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+0x43E0 SC_SCISSOR0
+0x43E8 SC_SCREENDOOR
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+0x4448 TX_FILTER1_2
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+0x446C TX_FILTER1_11
+0x4470 TX_FILTER1_12
+0x4474 TX_FILTER1_13
+0x4478 TX_FILTER1_14
+0x447C TX_FILTER1_15
+0x4580 TX_CHROMA_KEY_0
+0x4584 TX_CHROMA_KEY_1
+0x4588 TX_CHROMA_KEY_2
+0x458C TX_CHROMA_KEY_3
+0x4590 TX_CHROMA_KEY_4
+0x4594 TX_CHROMA_KEY_5
+0x4598 TX_CHROMA_KEY_6
+0x459C TX_CHROMA_KEY_7
+0x45A0 TX_CHROMA_KEY_8
+0x45A4 TX_CHROMA_KEY_9
+0x45A8 TX_CHROMA_KEY_10
+0x45AC TX_CHROMA_KEY_11
+0x45B0 TX_CHROMA_KEY_12
+0x45B4 TX_CHROMA_KEY_13
+0x45B8 TX_CHROMA_KEY_14
+0x45BC TX_CHROMA_KEY_15
+0x45C0 TX_BORDER_COLOR_0
+0x45C4 TX_BORDER_COLOR_1
+0x45C8 TX_BORDER_COLOR_2
+0x45CC TX_BORDER_COLOR_3
+0x45D0 TX_BORDER_COLOR_4
+0x45D4 TX_BORDER_COLOR_5
+0x45D8 TX_BORDER_COLOR_6
+0x45DC TX_BORDER_COLOR_7
+0x45E0 TX_BORDER_COLOR_8
+0x45E4 TX_BORDER_COLOR_9
+0x45E8 TX_BORDER_COLOR_10
+0x45EC TX_BORDER_COLOR_11
+0x45F0 TX_BORDER_COLOR_12
+0x45F4 TX_BORDER_COLOR_13
+0x45F8 TX_BORDER_COLOR_14
+0x45FC TX_BORDER_COLOR_15
+0x4600 US_CONFIG
+0x4604 US_PIXSIZE
+0x4608 US_CODE_OFFSET
+0x460C US_RESET
+0x4610 US_CODE_ADDR_0
+0x4614 US_CODE_ADDR_1
+0x4618 US_CODE_ADDR_2
+0x461C US_CODE_ADDR_3
+0x4620 US_TEX_INST_0
+0x4624 US_TEX_INST_1
+0x4628 US_TEX_INST_2
+0x462C US_TEX_INST_3
+0x4630 US_TEX_INST_4
+0x4634 US_TEX_INST_5
+0x4638 US_TEX_INST_6
+0x463C US_TEX_INST_7
+0x4640 US_TEX_INST_8
+0x4644 US_TEX_INST_9
+0x4648 US_TEX_INST_10
+0x464C US_TEX_INST_11
+0x4650 US_TEX_INST_12
+0x4654 US_TEX_INST_13
+0x4658 US_TEX_INST_14
+0x465C US_TEX_INST_15
+0x4660 US_TEX_INST_16
+0x4664 US_TEX_INST_17
+0x4668 US_TEX_INST_18
+0x466C US_TEX_INST_19
+0x4670 US_TEX_INST_20
+0x4674 US_TEX_INST_21
+0x4678 US_TEX_INST_22
+0x467C US_TEX_INST_23
+0x4680 US_TEX_INST_24
+0x4684 US_TEX_INST_25
+0x4688 US_TEX_INST_26
+0x468C US_TEX_INST_27
+0x4690 US_TEX_INST_28
+0x4694 US_TEX_INST_29
+0x4698 US_TEX_INST_30
+0x469C US_TEX_INST_31
+0x46A4 US_OUT_FMT_0
+0x46A8 US_OUT_FMT_1
+0x46AC US_OUT_FMT_2
+0x46B0 US_OUT_FMT_3
+0x46B4 US_W_FMT
+0x46C0 US_ALU_RGB_ADDR_0
+0x46C4 US_ALU_RGB_ADDR_1
+0x46C8 US_ALU_RGB_ADDR_2
+0x46CC US_ALU_RGB_ADDR_3
+0x46D0 US_ALU_RGB_ADDR_4
+0x46D4 US_ALU_RGB_ADDR_5
+0x46D8 US_ALU_RGB_ADDR_6
+0x46DC US_ALU_RGB_ADDR_7
+0x46E0 US_ALU_RGB_ADDR_8
+0x46E4 US_ALU_RGB_ADDR_9
+0x46E8 US_ALU_RGB_ADDR_10
+0x46EC US_ALU_RGB_ADDR_11
+0x46F0 US_ALU_RGB_ADDR_12
+0x46F4 US_ALU_RGB_ADDR_13
+0x46F8 US_ALU_RGB_ADDR_14
+0x46FC US_ALU_RGB_ADDR_15
+0x4700 US_ALU_RGB_ADDR_16
+0x4704 US_ALU_RGB_ADDR_17
+0x4708 US_ALU_RGB_ADDR_18
+0x470C US_ALU_RGB_ADDR_19
+0x4710 US_ALU_RGB_ADDR_20
+0x4714 US_ALU_RGB_ADDR_21
+0x4718 US_ALU_RGB_ADDR_22
+0x471C US_ALU_RGB_ADDR_23
+0x4720 US_ALU_RGB_ADDR_24
+0x4724 US_ALU_RGB_ADDR_25
+0x4728 US_ALU_RGB_ADDR_26
+0x472C US_ALU_RGB_ADDR_27
+0x4730 US_ALU_RGB_ADDR_28
+0x4734 US_ALU_RGB_ADDR_29
+0x4738 US_ALU_RGB_ADDR_30
+0x473C US_ALU_RGB_ADDR_31
+0x4740 US_ALU_RGB_ADDR_32
+0x4744 US_ALU_RGB_ADDR_33
+0x4748 US_ALU_RGB_ADDR_34
+0x474C US_ALU_RGB_ADDR_35
+0x4750 US_ALU_RGB_ADDR_36
+0x4754 US_ALU_RGB_ADDR_37
+0x4758 US_ALU_RGB_ADDR_38
+0x475C US_ALU_RGB_ADDR_39
+0x4760 US_ALU_RGB_ADDR_40
+0x4764 US_ALU_RGB_ADDR_41
+0x4768 US_ALU_RGB_ADDR_42
+0x476C US_ALU_RGB_ADDR_43
+0x4770 US_ALU_RGB_ADDR_44
+0x4774 US_ALU_RGB_ADDR_45
+0x4778 US_ALU_RGB_ADDR_46
+0x477C US_ALU_RGB_ADDR_47
+0x4780 US_ALU_RGB_ADDR_48
+0x4784 US_ALU_RGB_ADDR_49
+0x4788 US_ALU_RGB_ADDR_50
+0x478C US_ALU_RGB_ADDR_51
+0x4790 US_ALU_RGB_ADDR_52
+0x4794 US_ALU_RGB_ADDR_53
+0x4798 US_ALU_RGB_ADDR_54
+0x479C US_ALU_RGB_ADDR_55
+0x47A0 US_ALU_RGB_ADDR_56
+0x47A4 US_ALU_RGB_ADDR_57
+0x47A8 US_ALU_RGB_ADDR_58
+0x47AC US_ALU_RGB_ADDR_59
+0x47B0 US_ALU_RGB_ADDR_60
+0x47B4 US_ALU_RGB_ADDR_61
+0x47B8 US_ALU_RGB_ADDR_62
+0x47BC US_ALU_RGB_ADDR_63
+0x47C0 US_ALU_ALPHA_ADDR_0
+0x47C4 US_ALU_ALPHA_ADDR_1
+0x47C8 US_ALU_ALPHA_ADDR_2
+0x47CC US_ALU_ALPHA_ADDR_3
+0x47D0 US_ALU_ALPHA_ADDR_4
+0x47D4 US_ALU_ALPHA_ADDR_5
+0x47D8 US_ALU_ALPHA_ADDR_6
+0x47DC US_ALU_ALPHA_ADDR_7
+0x47E0 US_ALU_ALPHA_ADDR_8
+0x47E4 US_ALU_ALPHA_ADDR_9
+0x47E8 US_ALU_ALPHA_ADDR_10
+0x47EC US_ALU_ALPHA_ADDR_11
+0x47F0 US_ALU_ALPHA_ADDR_12
+0x47F4 US_ALU_ALPHA_ADDR_13
+0x47F8 US_ALU_ALPHA_ADDR_14
+0x47FC US_ALU_ALPHA_ADDR_15
+0x4800 US_ALU_ALPHA_ADDR_16
+0x4804 US_ALU_ALPHA_ADDR_17
+0x4808 US_ALU_ALPHA_ADDR_18
+0x480C US_ALU_ALPHA_ADDR_19
+0x4810 US_ALU_ALPHA_ADDR_20
+0x4814 US_ALU_ALPHA_ADDR_21
+0x4818 US_ALU_ALPHA_ADDR_22
+0x481C US_ALU_ALPHA_ADDR_23
+0x4820 US_ALU_ALPHA_ADDR_24
+0x4824 US_ALU_ALPHA_ADDR_25
+0x4828 US_ALU_ALPHA_ADDR_26
+0x482C US_ALU_ALPHA_ADDR_27
+0x4830 US_ALU_ALPHA_ADDR_28
+0x4834 US_ALU_ALPHA_ADDR_29
+0x4838 US_ALU_ALPHA_ADDR_30
+0x483C US_ALU_ALPHA_ADDR_31
+0x4840 US_ALU_ALPHA_ADDR_32
+0x4844 US_ALU_ALPHA_ADDR_33
+0x4848 US_ALU_ALPHA_ADDR_34
+0x484C US_ALU_ALPHA_ADDR_35
+0x4850 US_ALU_ALPHA_ADDR_36
+0x4854 US_ALU_ALPHA_ADDR_37
+0x4858 US_ALU_ALPHA_ADDR_38
+0x485C US_ALU_ALPHA_ADDR_39
+0x4860 US_ALU_ALPHA_ADDR_40
+0x4864 US_ALU_ALPHA_ADDR_41
+0x4868 US_ALU_ALPHA_ADDR_42
+0x486C US_ALU_ALPHA_ADDR_43
+0x4870 US_ALU_ALPHA_ADDR_44
+0x4874 US_ALU_ALPHA_ADDR_45
+0x4878 US_ALU_ALPHA_ADDR_46
+0x487C US_ALU_ALPHA_ADDR_47
+0x4880 US_ALU_ALPHA_ADDR_48
+0x4884 US_ALU_ALPHA_ADDR_49
+0x4888 US_ALU_ALPHA_ADDR_50
+0x488C US_ALU_ALPHA_ADDR_51
+0x4890 US_ALU_ALPHA_ADDR_52
+0x4894 US_ALU_ALPHA_ADDR_53
+0x4898 US_ALU_ALPHA_ADDR_54
+0x489C US_ALU_ALPHA_ADDR_55
+0x48A0 US_ALU_ALPHA_ADDR_56
+0x48A4 US_ALU_ALPHA_ADDR_57
+0x48A8 US_ALU_ALPHA_ADDR_58
+0x48AC US_ALU_ALPHA_ADDR_59
+0x48B0 US_ALU_ALPHA_ADDR_60
+0x48B4 US_ALU_ALPHA_ADDR_61
+0x48B8 US_ALU_ALPHA_ADDR_62
+0x48BC US_ALU_ALPHA_ADDR_63
+0x48C0 US_ALU_RGB_INST_0
+0x48C4 US_ALU_RGB_INST_1
+0x48C8 US_ALU_RGB_INST_2
+0x48CC US_ALU_RGB_INST_3
+0x48D0 US_ALU_RGB_INST_4
+0x48D4 US_ALU_RGB_INST_5
+0x48D8 US_ALU_RGB_INST_6
+0x48DC US_ALU_RGB_INST_7
+0x48E0 US_ALU_RGB_INST_8
+0x48E4 US_ALU_RGB_INST_9
+0x48E8 US_ALU_RGB_INST_10
+0x48EC US_ALU_RGB_INST_11
+0x48F0 US_ALU_RGB_INST_12
+0x48F4 US_ALU_RGB_INST_13
+0x48F8 US_ALU_RGB_INST_14
+0x48FC US_ALU_RGB_INST_15
+0x4900 US_ALU_RGB_INST_16
+0x4904 US_ALU_RGB_INST_17
+0x4908 US_ALU_RGB_INST_18
+0x490C US_ALU_RGB_INST_19
+0x4910 US_ALU_RGB_INST_20
+0x4914 US_ALU_RGB_INST_21
+0x4918 US_ALU_RGB_INST_22
+0x491C US_ALU_RGB_INST_23
+0x4920 US_ALU_RGB_INST_24
+0x4924 US_ALU_RGB_INST_25
+0x4928 US_ALU_RGB_INST_26
+0x492C US_ALU_RGB_INST_27
+0x4930 US_ALU_RGB_INST_28
+0x4934 US_ALU_RGB_INST_29
+0x4938 US_ALU_RGB_INST_30
+0x493C US_ALU_RGB_INST_31
+0x4940 US_ALU_RGB_INST_32
+0x4944 US_ALU_RGB_INST_33
+0x4948 US_ALU_RGB_INST_34
+0x494C US_ALU_RGB_INST_35
+0x4950 US_ALU_RGB_INST_36
+0x4954 US_ALU_RGB_INST_37
+0x4958 US_ALU_RGB_INST_38
+0x495C US_ALU_RGB_INST_39
+0x4960 US_ALU_RGB_INST_40
+0x4964 US_ALU_RGB_INST_41
+0x4968 US_ALU_RGB_INST_42
+0x496C US_ALU_RGB_INST_43
+0x4970 US_ALU_RGB_INST_44
+0x4974 US_ALU_RGB_INST_45
+0x4978 US_ALU_RGB_INST_46
+0x497C US_ALU_RGB_INST_47
+0x4980 US_ALU_RGB_INST_48
+0x4984 US_ALU_RGB_INST_49
+0x4988 US_ALU_RGB_INST_50
+0x498C US_ALU_RGB_INST_51
+0x4990 US_ALU_RGB_INST_52
+0x4994 US_ALU_RGB_INST_53
+0x4998 US_ALU_RGB_INST_54
+0x499C US_ALU_RGB_INST_55
+0x49A0 US_ALU_RGB_INST_56
+0x49A4 US_ALU_RGB_INST_57
+0x49A8 US_ALU_RGB_INST_58
+0x49AC US_ALU_RGB_INST_59
+0x49B0 US_ALU_RGB_INST_60
+0x49B4 US_ALU_RGB_INST_61
+0x49B8 US_ALU_RGB_INST_62
+0x49BC US_ALU_RGB_INST_63
+0x49C0 US_ALU_ALPHA_INST_0
+0x49C4 US_ALU_ALPHA_INST_1
+0x49C8 US_ALU_ALPHA_INST_2
+0x49CC US_ALU_ALPHA_INST_3
+0x49D0 US_ALU_ALPHA_INST_4
+0x49D4 US_ALU_ALPHA_INST_5
+0x49D8 US_ALU_ALPHA_INST_6
+0x49DC US_ALU_ALPHA_INST_7
+0x49E0 US_ALU_ALPHA_INST_8
+0x49E4 US_ALU_ALPHA_INST_9
+0x49E8 US_ALU_ALPHA_INST_10
+0x49EC US_ALU_ALPHA_INST_11
+0x49F0 US_ALU_ALPHA_INST_12
+0x49F4 US_ALU_ALPHA_INST_13
+0x49F8 US_ALU_ALPHA_INST_14
+0x49FC US_ALU_ALPHA_INST_15
+0x4A00 US_ALU_ALPHA_INST_16
+0x4A04 US_ALU_ALPHA_INST_17
+0x4A08 US_ALU_ALPHA_INST_18
+0x4A0C US_ALU_ALPHA_INST_19
+0x4A10 US_ALU_ALPHA_INST_20
+0x4A14 US_ALU_ALPHA_INST_21
+0x4A18 US_ALU_ALPHA_INST_22
+0x4A1C US_ALU_ALPHA_INST_23
+0x4A20 US_ALU_ALPHA_INST_24
+0x4A24 US_ALU_ALPHA_INST_25
+0x4A28 US_ALU_ALPHA_INST_26
+0x4A2C US_ALU_ALPHA_INST_27
+0x4A30 US_ALU_ALPHA_INST_28
+0x4A34 US_ALU_ALPHA_INST_29
+0x4A38 US_ALU_ALPHA_INST_30
+0x4A3C US_ALU_ALPHA_INST_31
+0x4A40 US_ALU_ALPHA_INST_32
+0x4A44 US_ALU_ALPHA_INST_33
+0x4A48 US_ALU_ALPHA_INST_34
+0x4A4C US_ALU_ALPHA_INST_35
+0x4A50 US_ALU_ALPHA_INST_36
+0x4A54 US_ALU_ALPHA_INST_37
+0x4A58 US_ALU_ALPHA_INST_38
+0x4A5C US_ALU_ALPHA_INST_39
+0x4A60 US_ALU_ALPHA_INST_40
+0x4A64 US_ALU_ALPHA_INST_41
+0x4A68 US_ALU_ALPHA_INST_42
+0x4A6C US_ALU_ALPHA_INST_43
+0x4A70 US_ALU_ALPHA_INST_44
+0x4A74 US_ALU_ALPHA_INST_45
+0x4A78 US_ALU_ALPHA_INST_46
+0x4A7C US_ALU_ALPHA_INST_47
+0x4A80 US_ALU_ALPHA_INST_48
+0x4A84 US_ALU_ALPHA_INST_49
+0x4A88 US_ALU_ALPHA_INST_50
+0x4A8C US_ALU_ALPHA_INST_51
+0x4A90 US_ALU_ALPHA_INST_52
+0x4A94 US_ALU_ALPHA_INST_53
+0x4A98 US_ALU_ALPHA_INST_54
+0x4A9C US_ALU_ALPHA_INST_55
+0x4AA0 US_ALU_ALPHA_INST_56
+0x4AA4 US_ALU_ALPHA_INST_57
+0x4AA8 US_ALU_ALPHA_INST_58
+0x4AAC US_ALU_ALPHA_INST_59
+0x4AB0 US_ALU_ALPHA_INST_60
+0x4AB4 US_ALU_ALPHA_INST_61
+0x4AB8 US_ALU_ALPHA_INST_62
+0x4ABC US_ALU_ALPHA_INST_63
+0x4BC0 FG_FOG_BLEND
+0x4BC4 FG_FOG_FACTOR
+0x4BC8 FG_FOG_COLOR_R
+0x4BCC FG_FOG_COLOR_G
+0x4BD0 FG_FOG_COLOR_B
+0x4BD4 FG_ALPHA_FUNC
+0x4BD8 FG_DEPTH_SRC
+0x4C00 US_ALU_CONST_R_0
+0x4C04 US_ALU_CONST_G_0
+0x4C08 US_ALU_CONST_B_0
+0x4C0C US_ALU_CONST_A_0
+0x4C10 US_ALU_CONST_R_1
+0x4C14 US_ALU_CONST_G_1
+0x4C18 US_ALU_CONST_B_1
+0x4C1C US_ALU_CONST_A_1
+0x4C20 US_ALU_CONST_R_2
+0x4C24 US_ALU_CONST_G_2
+0x4C28 US_ALU_CONST_B_2
+0x4C2C US_ALU_CONST_A_2
+0x4C30 US_ALU_CONST_R_3
+0x4C34 US_ALU_CONST_G_3
+0x4C38 US_ALU_CONST_B_3
+0x4C3C US_ALU_CONST_A_3
+0x4C40 US_ALU_CONST_R_4
+0x4C44 US_ALU_CONST_G_4
+0x4C48 US_ALU_CONST_B_4
+0x4C4C US_ALU_CONST_A_4
+0x4C50 US_ALU_CONST_R_5
+0x4C54 US_ALU_CONST_G_5
+0x4C58 US_ALU_CONST_B_5
+0x4C5C US_ALU_CONST_A_5
+0x4C60 US_ALU_CONST_R_6
+0x4C64 US_ALU_CONST_G_6
+0x4C68 US_ALU_CONST_B_6
+0x4C6C US_ALU_CONST_A_6
+0x4C70 US_ALU_CONST_R_7
+0x4C74 US_ALU_CONST_G_7
+0x4C78 US_ALU_CONST_B_7
+0x4C7C US_ALU_CONST_A_7
+0x4C80 US_ALU_CONST_R_8
+0x4C84 US_ALU_CONST_G_8
+0x4C88 US_ALU_CONST_B_8
+0x4C8C US_ALU_CONST_A_8
+0x4C90 US_ALU_CONST_R_9
+0x4C94 US_ALU_CONST_G_9
+0x4C98 US_ALU_CONST_B_9
+0x4C9C US_ALU_CONST_A_9
+0x4CA0 US_ALU_CONST_R_10
+0x4CA4 US_ALU_CONST_G_10
+0x4CA8 US_ALU_CONST_B_10
+0x4CAC US_ALU_CONST_A_10
+0x4CB0 US_ALU_CONST_R_11
+0x4CB4 US_ALU_CONST_G_11
+0x4CB8 US_ALU_CONST_B_11
+0x4CBC US_ALU_CONST_A_11
+0x4CC0 US_ALU_CONST_R_12
+0x4CC4 US_ALU_CONST_G_12
+0x4CC8 US_ALU_CONST_B_12
+0x4CCC US_ALU_CONST_A_12
+0x4CD0 US_ALU_CONST_R_13
+0x4CD4 US_ALU_CONST_G_13
+0x4CD8 US_ALU_CONST_B_13
+0x4CDC US_ALU_CONST_A_13
+0x4CE0 US_ALU_CONST_R_14
+0x4CE4 US_ALU_CONST_G_14
+0x4CE8 US_ALU_CONST_B_14
+0x4CEC US_ALU_CONST_A_14
+0x4CF0 US_ALU_CONST_R_15
+0x4CF4 US_ALU_CONST_G_15
+0x4CF8 US_ALU_CONST_B_15
+0x4CFC US_ALU_CONST_A_15
+0x4D00 US_ALU_CONST_R_16
+0x4D04 US_ALU_CONST_G_16
+0x4D08 US_ALU_CONST_B_16
+0x4D0C US_ALU_CONST_A_16
+0x4D10 US_ALU_CONST_R_17
+0x4D14 US_ALU_CONST_G_17
+0x4D18 US_ALU_CONST_B_17
+0x4D1C US_ALU_CONST_A_17
+0x4D20 US_ALU_CONST_R_18
+0x4D24 US_ALU_CONST_G_18
+0x4D28 US_ALU_CONST_B_18
+0x4D2C US_ALU_CONST_A_18
+0x4D30 US_ALU_CONST_R_19
+0x4D34 US_ALU_CONST_G_19
+0x4D38 US_ALU_CONST_B_19
+0x4D3C US_ALU_CONST_A_19
+0x4D40 US_ALU_CONST_R_20
+0x4D44 US_ALU_CONST_G_20
+0x4D48 US_ALU_CONST_B_20
+0x4D4C US_ALU_CONST_A_20
+0x4D50 US_ALU_CONST_R_21
+0x4D54 US_ALU_CONST_G_21
+0x4D58 US_ALU_CONST_B_21
+0x4D5C US_ALU_CONST_A_21
+0x4D60 US_ALU_CONST_R_22
+0x4D64 US_ALU_CONST_G_22
+0x4D68 US_ALU_CONST_B_22
+0x4D6C US_ALU_CONST_A_22
+0x4D70 US_ALU_CONST_R_23
+0x4D74 US_ALU_CONST_G_23
+0x4D78 US_ALU_CONST_B_23
+0x4D7C US_ALU_CONST_A_23
+0x4D80 US_ALU_CONST_R_24
+0x4D84 US_ALU_CONST_G_24
+0x4D88 US_ALU_CONST_B_24
+0x4D8C US_ALU_CONST_A_24
+0x4D90 US_ALU_CONST_R_25
+0x4D94 US_ALU_CONST_G_25
+0x4D98 US_ALU_CONST_B_25
+0x4D9C US_ALU_CONST_A_25
+0x4DA0 US_ALU_CONST_R_26
+0x4DA4 US_ALU_CONST_G_26
+0x4DA8 US_ALU_CONST_B_26
+0x4DAC US_ALU_CONST_A_26
+0x4DB0 US_ALU_CONST_R_27
+0x4DB4 US_ALU_CONST_G_27
+0x4DB8 US_ALU_CONST_B_27
+0x4DBC US_ALU_CONST_A_27
+0x4DC0 US_ALU_CONST_R_28
+0x4DC4 US_ALU_CONST_G_28
+0x4DC8 US_ALU_CONST_B_28
+0x4DCC US_ALU_CONST_A_28
+0x4DD0 US_ALU_CONST_R_29
+0x4DD4 US_ALU_CONST_G_29
+0x4DD8 US_ALU_CONST_B_29
+0x4DDC US_ALU_CONST_A_29
+0x4DE0 US_ALU_CONST_R_30
+0x4DE4 US_ALU_CONST_G_30
+0x4DE8 US_ALU_CONST_B_30
+0x4DEC US_ALU_CONST_A_30
+0x4DF0 US_ALU_CONST_R_31
+0x4DF4 US_ALU_CONST_G_31
+0x4DF8 US_ALU_CONST_B_31
+0x4DFC US_ALU_CONST_A_31
+0x4E04 RB3D_BLENDCNTL_R3
+0x4E08 RB3D_ABLENDCNTL_R3
+0x4E0C RB3D_COLOR_CHANNEL_MASK
+0x4E10 RB3D_CONSTANT_COLOR
+0x4E14 RB3D_COLOR_CLEAR_VALUE
+0x4E18 RB3D_ROPCNTL_R3
+0x4E1C RB3D_CLRCMP_FLIPE_R3
+0x4E20 RB3D_CLRCMP_CLR_R3
+0x4E24 RB3D_CLRCMP_MSK_R3
+0x4E48 RB3D_DEBUG_CTL
+0x4E4C RB3D_DSTCACHE_CTLSTAT_R3
+0x4E50 RB3D_DITHER_CTL
+0x4E54 RB3D_CMASK_OFFSET0
+0x4E58 RB3D_CMASK_OFFSET1
+0x4E5C RB3D_CMASK_OFFSET2
+0x4E60 RB3D_CMASK_OFFSET3
+0x4E64 RB3D_CMASK_PITCH0
+0x4E68 RB3D_CMASK_PITCH1
+0x4E6C RB3D_CMASK_PITCH2
+0x4E70 RB3D_CMASK_PITCH3
+0x4E74 RB3D_CMASK_WRINDEX
+0x4E78 RB3D_CMASK_DWORD
+0x4E7C RB3D_CMASK_RDINDEX
+0x4E80 RB3D_AARESOLVE_OFFSET
+0x4E84 RB3D_AARESOLVE_PITCH
+0x4E88 RB3D_AARESOLVE_CTL
+0x4F04 ZB_ZSTENCILCNTL
+0x4F08 ZB_STENCILREFMASK
+0x4F14 ZB_ZTOP
+0x4F18 ZB_ZCACHE_CTLSTAT
+0x4F1C ZB_BW_CNTL
+0x4F28 ZB_DEPTHCLEARVALUE
+0x4F30 ZB_ZMASK_OFFSET
+0x4F34 ZB_ZMASK_PITCH
+0x4F38 ZB_ZMASK_WRINDEX
+0x4F3C ZB_ZMASK_DWORD
+0x4F40 ZB_ZMASK_RDINDEX
+0x4F44 ZB_HIZ_OFFSET
+0x4F48 ZB_HIZ_WRINDEX
+0x4F4C ZB_HIZ_DWORD
+0x4F50 ZB_HIZ_RDINDEX
+0x4F54 ZB_HIZ_PITCH
+0x4F58 ZB_ZPASS_DATA
+0x4F60 ZB_DEPTHXY_OFFSET
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rv515 b/drivers/gpu/drm/radeon/reg_srcs/rv515
new file mode 100644
index 00000000000..d1fcf382fd7
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/rv515
@@ -0,0 +1,486 @@
+rv515 0x6d40
+0x1434 SRC_Y_X
+0x1438 DST_Y_X
+0x143C DST_HEIGHT_WIDTH
+0x146C DP_GUI_MASTER_CNTL
+0x1474 BRUSH_Y_X
+0x1478 DP_BRUSH_BKGD_CLR
+0x147C DP_BRUSH_FRGD_CLR
+0x1480 BRUSH_DATA0
+0x1484 BRUSH_DATA1
+0x1598 DST_WIDTH_HEIGHT
+0x15C0 CLR_CMP_CNTL
+0x15C4 CLR_CMP_CLR_SRC
+0x15C8 CLR_CMP_CLR_DST
+0x15CC CLR_CMP_MSK
+0x15D8 DP_SRC_FRGD_CLR
+0x15DC DP_SRC_BKGD_CLR
+0x1600 DST_LINE_START
+0x1604 DST_LINE_END
+0x1608 DST_LINE_PATCOUNT
+0x16C0 DP_CNTL
+0x16CC DP_WRITE_MSK
+0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
+0x16E8 DEFAULT_SC_BOTTOM_RIGHT
+0x16EC SC_TOP_LEFT
+0x16F0 SC_BOTTOM_RIGHT
+0x16F4 SRC_SC_BOTTOM_RIGHT
+0x1714 DSTCACHE_CTLSTAT
+0x1720 WAIT_UNTIL
+0x172C RBBM_GUICNTL
+0x1D98 VAP_VPORT_XSCALE
+0x1D9C VAP_VPORT_XOFFSET
+0x1DA0 VAP_VPORT_YSCALE
+0x1DA4 VAP_VPORT_YOFFSET
+0x1DA8 VAP_VPORT_ZSCALE
+0x1DAC VAP_VPORT_ZOFFSET
+0x2080 VAP_CNTL
+0x2090 VAP_OUT_VTX_FMT_0
+0x2094 VAP_OUT_VTX_FMT_1
+0x20B0 VAP_VTE_CNTL
+0x2138 VAP_VF_MIN_VTX_INDX
+0x2140 VAP_CNTL_STATUS
+0x2150 VAP_PROG_STREAM_CNTL_0
+0x2154 VAP_PROG_STREAM_CNTL_1
+0x2158 VAP_PROG_STREAM_CNTL_2
+0x215C VAP_PROG_STREAM_CNTL_3
+0x2160 VAP_PROG_STREAM_CNTL_4
+0x2164 VAP_PROG_STREAM_CNTL_5
+0x2168 VAP_PROG_STREAM_CNTL_6
+0x216C VAP_PROG_STREAM_CNTL_7
+0x2180 VAP_VTX_STATE_CNTL
+0x2184 VAP_VSM_VTX_ASSM
+0x2188 VAP_VTX_STATE_IND_REG_0
+0x218C VAP_VTX_STATE_IND_REG_1
+0x2190 VAP_VTX_STATE_IND_REG_2
+0x2194 VAP_VTX_STATE_IND_REG_3
+0x2198 VAP_VTX_STATE_IND_REG_4
+0x219C VAP_VTX_STATE_IND_REG_5
+0x21A0 VAP_VTX_STATE_IND_REG_6
+0x21A4 VAP_VTX_STATE_IND_REG_7
+0x21A8 VAP_VTX_STATE_IND_REG_8
+0x21AC VAP_VTX_STATE_IND_REG_9
+0x21B0 VAP_VTX_STATE_IND_REG_10
+0x21B4 VAP_VTX_STATE_IND_REG_11
+0x21B8 VAP_VTX_STATE_IND_REG_12
+0x21BC VAP_VTX_STATE_IND_REG_13
+0x21C0 VAP_VTX_STATE_IND_REG_14
+0x21C4 VAP_VTX_STATE_IND_REG_15
+0x21DC VAP_PSC_SGN_NORM_CNTL
+0x21E0 VAP_PROG_STREAM_CNTL_EXT_0
+0x21E4 VAP_PROG_STREAM_CNTL_EXT_1
+0x21E8 VAP_PROG_STREAM_CNTL_EXT_2
+0x21EC VAP_PROG_STREAM_CNTL_EXT_3
+0x21F0 VAP_PROG_STREAM_CNTL_EXT_4
+0x21F4 VAP_PROG_STREAM_CNTL_EXT_5
+0x21F8 VAP_PROG_STREAM_CNTL_EXT_6
+0x21FC VAP_PROG_STREAM_CNTL_EXT_7
+0x2200 VAP_PVS_VECTOR_INDX_REG
+0x2204 VAP_PVS_VECTOR_DATA_REG
+0x2208 VAP_PVS_VECTOR_DATA_REG_128
+0x2218 VAP_TEX_TO_COLOR_CNTL
+0x221C VAP_CLIP_CNTL
+0x2220 VAP_GB_VERT_CLIP_ADJ
+0x2224 VAP_GB_VERT_DISC_ADJ
+0x2228 VAP_GB_HORZ_CLIP_ADJ
+0x222C VAP_GB_HORZ_DISC_ADJ
+0x2230 VAP_PVS_FLOW_CNTL_ADDRS_0
+0x2234 VAP_PVS_FLOW_CNTL_ADDRS_1
+0x2238 VAP_PVS_FLOW_CNTL_ADDRS_2
+0x223C VAP_PVS_FLOW_CNTL_ADDRS_3
+0x2240 VAP_PVS_FLOW_CNTL_ADDRS_4
+0x2244 VAP_PVS_FLOW_CNTL_ADDRS_5
+0x2248 VAP_PVS_FLOW_CNTL_ADDRS_6
+0x224C VAP_PVS_FLOW_CNTL_ADDRS_7
+0x2250 VAP_PVS_FLOW_CNTL_ADDRS_8
+0x2254 VAP_PVS_FLOW_CNTL_ADDRS_9
+0x2258 VAP_PVS_FLOW_CNTL_ADDRS_10
+0x225C VAP_PVS_FLOW_CNTL_ADDRS_11
+0x2260 VAP_PVS_FLOW_CNTL_ADDRS_12
+0x2264 VAP_PVS_FLOW_CNTL_ADDRS_13
+0x2268 VAP_PVS_FLOW_CNTL_ADDRS_14
+0x226C VAP_PVS_FLOW_CNTL_ADDRS_15
+0x2284 VAP_PVS_STATE_FLUSH_REG
+0x2288 VAP_PVS_VTX_TIMEOUT_REG
+0x2290 VAP_PVS_FLOW_CNTL_LOOP_INDEX_0
+0x2294 VAP_PVS_FLOW_CNTL_LOOP_INDEX_1
+0x2298 VAP_PVS_FLOW_CNTL_LOOP_INDEX_2
+0x229C VAP_PVS_FLOW_CNTL_LOOP_INDEX_3
+0x22A0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_4
+0x22A4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_5
+0x22A8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_6
+0x22AC VAP_PVS_FLOW_CNTL_LOOP_INDEX_7
+0x22B0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_8
+0x22B4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_9
+0x22B8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_10
+0x22BC VAP_PVS_FLOW_CNTL_LOOP_INDEX_11
+0x22C0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_12
+0x22C4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_13
+0x22C8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_14
+0x22CC VAP_PVS_FLOW_CNTL_LOOP_INDEX_15
+0x22D0 VAP_PVS_CODE_CNTL_0
+0x22D4 VAP_PVS_CONST_CNTL
+0x22D8 VAP_PVS_CODE_CNTL_1
+0x22DC VAP_PVS_FLOW_CNTL_OPC
+0x2500 VAP_PVS_FLOW_CNTL_ADDRS_LW_0
+0x2504 VAP_PVS_FLOW_CNTL_ADDRS_UW_0
+0x2508 VAP_PVS_FLOW_CNTL_ADDRS_LW_1
+0x250C VAP_PVS_FLOW_CNTL_ADDRS_UW_1
+0x2510 VAP_PVS_FLOW_CNTL_ADDRS_LW_2
+0x2514 VAP_PVS_FLOW_CNTL_ADDRS_UW_2
+0x2518 VAP_PVS_FLOW_CNTL_ADDRS_LW_3
+0x251C VAP_PVS_FLOW_CNTL_ADDRS_UW_3
+0x2520 VAP_PVS_FLOW_CNTL_ADDRS_LW_4
+0x2524 VAP_PVS_FLOW_CNTL_ADDRS_UW_4
+0x2528 VAP_PVS_FLOW_CNTL_ADDRS_LW_5
+0x252C VAP_PVS_FLOW_CNTL_ADDRS_UW_5
+0x2530 VAP_PVS_FLOW_CNTL_ADDRS_LW_6
+0x2534 VAP_PVS_FLOW_CNTL_ADDRS_UW_6
+0x2538 VAP_PVS_FLOW_CNTL_ADDRS_LW_7
+0x253C VAP_PVS_FLOW_CNTL_ADDRS_UW_7
+0x2540 VAP_PVS_FLOW_CNTL_ADDRS_LW_8
+0x2544 VAP_PVS_FLOW_CNTL_ADDRS_UW_8
+0x2548 VAP_PVS_FLOW_CNTL_ADDRS_LW_9
+0x254C VAP_PVS_FLOW_CNTL_ADDRS_UW_9
+0x2550 VAP_PVS_FLOW_CNTL_ADDRS_LW_10
+0x2554 VAP_PVS_FLOW_CNTL_ADDRS_UW_10
+0x2558 VAP_PVS_FLOW_CNTL_ADDRS_LW_11
+0x255C VAP_PVS_FLOW_CNTL_ADDRS_UW_11
+0x2560 VAP_PVS_FLOW_CNTL_ADDRS_LW_12
+0x2564 VAP_PVS_FLOW_CNTL_ADDRS_UW_12
+0x2568 VAP_PVS_FLOW_CNTL_ADDRS_LW_13
+0x256C VAP_PVS_FLOW_CNTL_ADDRS_UW_13
+0x2570 VAP_PVS_FLOW_CNTL_ADDRS_LW_14
+0x2574 VAP_PVS_FLOW_CNTL_ADDRS_UW_14
+0x2578 VAP_PVS_FLOW_CNTL_ADDRS_LW_15
+0x257C VAP_PVS_FLOW_CNTL_ADDRS_UW_15
+0x342C RB2D_DSTCACHE_CTLSTAT
+0x4000 GB_VAP_RASTER_VTX_FMT_0
+0x4004 GB_VAP_RASTER_VTX_FMT_1
+0x4008 GB_ENABLE
+0x401C GB_SELECT
+0x4020 GB_AA_CONFIG
+0x4024 GB_FIFO_SIZE
+0x4100 TX_INVALTAGS
+0x4200 GA_POINT_S0
+0x4204 GA_POINT_T0
+0x4208 GA_POINT_S1
+0x420C GA_POINT_T1
+0x4214 GA_TRIANGLE_STIPPLE
+0x421C GA_POINT_SIZE
+0x4230 GA_POINT_MINMAX
+0x4234 GA_LINE_CNTL
+0x4238 GA_LINE_STIPPLE_CONFIG
+0x4260 GA_LINE_STIPPLE_VALUE
+0x4264 GA_LINE_S0
+0x4268 GA_LINE_S1
+0x4278 GA_COLOR_CONTROL
+0x427C GA_SOLID_RG
+0x4280 GA_SOLID_BA
+0x4288 GA_POLY_MODE
+0x428C GA_ROUND_MODE
+0x4290 GA_OFFSET
+0x4294 GA_FOG_SCALE
+0x4298 GA_FOG_OFFSET
+0x42A0 SU_TEX_WRAP
+0x42A4 SU_POLY_OFFSET_FRONT_SCALE
+0x42A8 SU_POLY_OFFSET_FRONT_OFFSET
+0x42AC SU_POLY_OFFSET_BACK_SCALE
+0x42B0 SU_POLY_OFFSET_BACK_OFFSET 
+0x42B4 SU_POLY_OFFSET_ENABLE
+0x42B8 SU_CULL_MODE
+0x42C0 SU_DEPTH_SCALE
+0x42C4 SU_DEPTH_OFFSET
+0x42C8 SU_REG_DEST
+0x4300 RS_COUNT
+0x4304 RS_INST_COUNT
+0x4074 RS_IP_0
+0x4078 RS_IP_1
+0x407C RS_IP_2
+0x4080 RS_IP_3
+0x4084 RS_IP_4
+0x4088 RS_IP_5
+0x408C RS_IP_6
+0x4090 RS_IP_7
+0x4094 RS_IP_8
+0x4098 RS_IP_9
+0x409C RS_IP_10
+0x40A0 RS_IP_11
+0x40A4 RS_IP_12
+0x40A8 RS_IP_13
+0x40AC RS_IP_14
+0x40B0 RS_IP_15
+0x4320 RS_INST_0
+0x4324 RS_INST_1
+0x4328 RS_INST_2
+0x432C RS_INST_3
+0x4330 RS_INST_4
+0x4334 RS_INST_5
+0x4338 RS_INST_6
+0x433C RS_INST_7
+0x4340 RS_INST_8
+0x4344 RS_INST_9
+0x4348 RS_INST_10
+0x434C RS_INST_11
+0x4350 RS_INST_12
+0x4354 RS_INST_13
+0x4358 RS_INST_14
+0x435C RS_INST_15
+0x43A4 SC_HYPERZ_EN
+0x43A8 SC_EDGERULE
+0x43B0 SC_CLIP_0_A
+0x43B4 SC_CLIP_0_B
+0x43B8 SC_CLIP_1_A
+0x43BC SC_CLIP_1_B
+0x43C0 SC_CLIP_2_A
+0x43C4 SC_CLIP_2_B
+0x43C8 SC_CLIP_3_A
+0x43CC SC_CLIP_3_B
+0x43D0 SC_CLIP_RULE
+0x43E0 SC_SCISSOR0
+0x43E8 SC_SCREENDOOR
+0x4440 TX_FILTER1_0
+0x4444 TX_FILTER1_1
+0x4448 TX_FILTER1_2
+0x444C TX_FILTER1_3
+0x4450 TX_FILTER1_4
+0x4454 TX_FILTER1_5
+0x4458 TX_FILTER1_6
+0x445C TX_FILTER1_7
+0x4460 TX_FILTER1_8
+0x4464 TX_FILTER1_9
+0x4468 TX_FILTER1_10
+0x446C TX_FILTER1_11
+0x4470 TX_FILTER1_12
+0x4474 TX_FILTER1_13
+0x4478 TX_FILTER1_14
+0x447C TX_FILTER1_15
+0x4580 TX_CHROMA_KEY_0
+0x4584 TX_CHROMA_KEY_1
+0x4588 TX_CHROMA_KEY_2
+0x458C TX_CHROMA_KEY_3
+0x4590 TX_CHROMA_KEY_4
+0x4594 TX_CHROMA_KEY_5
+0x4598 TX_CHROMA_KEY_6
+0x459C TX_CHROMA_KEY_7
+0x45A0 TX_CHROMA_KEY_8
+0x45A4 TX_CHROMA_KEY_9
+0x45A8 TX_CHROMA_KEY_10
+0x45AC TX_CHROMA_KEY_11
+0x45B0 TX_CHROMA_KEY_12
+0x45B4 TX_CHROMA_KEY_13
+0x45B8 TX_CHROMA_KEY_14
+0x45BC TX_CHROMA_KEY_15
+0x45C0 TX_BORDER_COLOR_0
+0x45C4 TX_BORDER_COLOR_1
+0x45C8 TX_BORDER_COLOR_2
+0x45CC TX_BORDER_COLOR_3
+0x45D0 TX_BORDER_COLOR_4
+0x45D4 TX_BORDER_COLOR_5
+0x45D8 TX_BORDER_COLOR_6
+0x45DC TX_BORDER_COLOR_7
+0x45E0 TX_BORDER_COLOR_8
+0x45E4 TX_BORDER_COLOR_9
+0x45E8 TX_BORDER_COLOR_10
+0x45EC TX_BORDER_COLOR_11
+0x45F0 TX_BORDER_COLOR_12
+0x45F4 TX_BORDER_COLOR_13
+0x45F8 TX_BORDER_COLOR_14
+0x45FC TX_BORDER_COLOR_15
+0x4250 GA_US_VECTOR_INDEX
+0x4254 GA_US_VECTOR_DATA
+0x4600 US_CONFIG
+0x4604 US_PIXSIZE
+0x4620 US_FC_BOOL_CONST
+0x4624 US_FC_CTRL
+0x4630 US_CODE_ADDR
+0x4634 US_CODE_RANGE
+0x4638 US_CODE_OFFSET
+0x46A4 US_OUT_FMT_0
+0x46A8 US_OUT_FMT_1
+0x46AC US_OUT_FMT_2
+0x46B0 US_OUT_FMT_3
+0x46B4 US_W_FMT
+0x4BC0 FG_FOG_BLEND
+0x4BC4 FG_FOG_FACTOR
+0x4BC8 FG_FOG_COLOR_R
+0x4BCC FG_FOG_COLOR_G
+0x4BD0 FG_FOG_COLOR_B
+0x4BD4 FG_ALPHA_FUNC
+0x4BD8 FG_DEPTH_SRC
+0x4C00 US_ALU_CONST_R_0
+0x4C04 US_ALU_CONST_G_0
+0x4C08 US_ALU_CONST_B_0
+0x4C0C US_ALU_CONST_A_0
+0x4C10 US_ALU_CONST_R_1
+0x4C14 US_ALU_CONST_G_1
+0x4C18 US_ALU_CONST_B_1
+0x4C1C US_ALU_CONST_A_1
+0x4C20 US_ALU_CONST_R_2
+0x4C24 US_ALU_CONST_G_2
+0x4C28 US_ALU_CONST_B_2
+0x4C2C US_ALU_CONST_A_2
+0x4C30 US_ALU_CONST_R_3
+0x4C34 US_ALU_CONST_G_3
+0x4C38 US_ALU_CONST_B_3
+0x4C3C US_ALU_CONST_A_3
+0x4C40 US_ALU_CONST_R_4
+0x4C44 US_ALU_CONST_G_4
+0x4C48 US_ALU_CONST_B_4
+0x4C4C US_ALU_CONST_A_4
+0x4C50 US_ALU_CONST_R_5
+0x4C54 US_ALU_CONST_G_5
+0x4C58 US_ALU_CONST_B_5
+0x4C5C US_ALU_CONST_A_5
+0x4C60 US_ALU_CONST_R_6
+0x4C64 US_ALU_CONST_G_6
+0x4C68 US_ALU_CONST_B_6
+0x4C6C US_ALU_CONST_A_6
+0x4C70 US_ALU_CONST_R_7
+0x4C74 US_ALU_CONST_G_7
+0x4C78 US_ALU_CONST_B_7
+0x4C7C US_ALU_CONST_A_7
+0x4C80 US_ALU_CONST_R_8
+0x4C84 US_ALU_CONST_G_8
+0x4C88 US_ALU_CONST_B_8
+0x4C8C US_ALU_CONST_A_8
+0x4C90 US_ALU_CONST_R_9
+0x4C94 US_ALU_CONST_G_9
+0x4C98 US_ALU_CONST_B_9
+0x4C9C US_ALU_CONST_A_9
+0x4CA0 US_ALU_CONST_R_10
+0x4CA4 US_ALU_CONST_G_10
+0x4CA8 US_ALU_CONST_B_10
+0x4CAC US_ALU_CONST_A_10
+0x4CB0 US_ALU_CONST_R_11
+0x4CB4 US_ALU_CONST_G_11
+0x4CB8 US_ALU_CONST_B_11
+0x4CBC US_ALU_CONST_A_11
+0x4CC0 US_ALU_CONST_R_12
+0x4CC4 US_ALU_CONST_G_12
+0x4CC8 US_ALU_CONST_B_12
+0x4CCC US_ALU_CONST_A_12
+0x4CD0 US_ALU_CONST_R_13
+0x4CD4 US_ALU_CONST_G_13
+0x4CD8 US_ALU_CONST_B_13
+0x4CDC US_ALU_CONST_A_13
+0x4CE0 US_ALU_CONST_R_14
+0x4CE4 US_ALU_CONST_G_14
+0x4CE8 US_ALU_CONST_B_14
+0x4CEC US_ALU_CONST_A_14
+0x4CF0 US_ALU_CONST_R_15
+0x4CF4 US_ALU_CONST_G_15
+0x4CF8 US_ALU_CONST_B_15
+0x4CFC US_ALU_CONST_A_15
+0x4D00 US_ALU_CONST_R_16
+0x4D04 US_ALU_CONST_G_16
+0x4D08 US_ALU_CONST_B_16
+0x4D0C US_ALU_CONST_A_16
+0x4D10 US_ALU_CONST_R_17
+0x4D14 US_ALU_CONST_G_17
+0x4D18 US_ALU_CONST_B_17
+0x4D1C US_ALU_CONST_A_17
+0x4D20 US_ALU_CONST_R_18
+0x4D24 US_ALU_CONST_G_18
+0x4D28 US_ALU_CONST_B_18
+0x4D2C US_ALU_CONST_A_18
+0x4D30 US_ALU_CONST_R_19
+0x4D34 US_ALU_CONST_G_19
+0x4D38 US_ALU_CONST_B_19
+0x4D3C US_ALU_CONST_A_19
+0x4D40 US_ALU_CONST_R_20
+0x4D44 US_ALU_CONST_G_20
+0x4D48 US_ALU_CONST_B_20
+0x4D4C US_ALU_CONST_A_20
+0x4D50 US_ALU_CONST_R_21
+0x4D54 US_ALU_CONST_G_21
+0x4D58 US_ALU_CONST_B_21
+0x4D5C US_ALU_CONST_A_21
+0x4D60 US_ALU_CONST_R_22
+0x4D64 US_ALU_CONST_G_22
+0x4D68 US_ALU_CONST_B_22
+0x4D6C US_ALU_CONST_A_22
+0x4D70 US_ALU_CONST_R_23
+0x4D74 US_ALU_CONST_G_23
+0x4D78 US_ALU_CONST_B_23
+0x4D7C US_ALU_CONST_A_23
+0x4D80 US_ALU_CONST_R_24
+0x4D84 US_ALU_CONST_G_24
+0x4D88 US_ALU_CONST_B_24
+0x4D8C US_ALU_CONST_A_24
+0x4D90 US_ALU_CONST_R_25
+0x4D94 US_ALU_CONST_G_25
+0x4D98 US_ALU_CONST_B_25
+0x4D9C US_ALU_CONST_A_25
+0x4DA0 US_ALU_CONST_R_26
+0x4DA4 US_ALU_CONST_G_26
+0x4DA8 US_ALU_CONST_B_26
+0x4DAC US_ALU_CONST_A_26
+0x4DB0 US_ALU_CONST_R_27
+0x4DB4 US_ALU_CONST_G_27
+0x4DB8 US_ALU_CONST_B_27
+0x4DBC US_ALU_CONST_A_27
+0x4DC0 US_ALU_CONST_R_28
+0x4DC4 US_ALU_CONST_G_28
+0x4DC8 US_ALU_CONST_B_28
+0x4DCC US_ALU_CONST_A_28
+0x4DD0 US_ALU_CONST_R_29
+0x4DD4 US_ALU_CONST_G_29
+0x4DD8 US_ALU_CONST_B_29
+0x4DDC US_ALU_CONST_A_29
+0x4DE0 US_ALU_CONST_R_30
+0x4DE4 US_ALU_CONST_G_30
+0x4DE8 US_ALU_CONST_B_30
+0x4DEC US_ALU_CONST_A_30
+0x4DF0 US_ALU_CONST_R_31
+0x4DF4 US_ALU_CONST_G_31
+0x4DF8 US_ALU_CONST_B_31
+0x4DFC US_ALU_CONST_A_31
+0x4E04 RB3D_BLENDCNTL_R3
+0x4E08 RB3D_ABLENDCNTL_R3
+0x4E0C RB3D_COLOR_CHANNEL_MASK
+0x4E10 RB3D_CONSTANT_COLOR
+0x4E14 RB3D_COLOR_CLEAR_VALUE
+0x4E18 RB3D_ROPCNTL_R3
+0x4E1C RB3D_CLRCMP_FLIPE_R3
+0x4E20 RB3D_CLRCMP_CLR_R3
+0x4E24 RB3D_CLRCMP_MSK_R3
+0x4E48 RB3D_DEBUG_CTL
+0x4E4C RB3D_DSTCACHE_CTLSTAT_R3
+0x4E50 RB3D_DITHER_CTL
+0x4E54 RB3D_CMASK_OFFSET0
+0x4E58 RB3D_CMASK_OFFSET1
+0x4E5C RB3D_CMASK_OFFSET2
+0x4E60 RB3D_CMASK_OFFSET3
+0x4E64 RB3D_CMASK_PITCH0
+0x4E68 RB3D_CMASK_PITCH1
+0x4E6C RB3D_CMASK_PITCH2
+0x4E70 RB3D_CMASK_PITCH3
+0x4E74 RB3D_CMASK_WRINDEX
+0x4E78 RB3D_CMASK_DWORD
+0x4E7C RB3D_CMASK_RDINDEX
+0x4E80 RB3D_AARESOLVE_OFFSET
+0x4E84 RB3D_AARESOLVE_PITCH
+0x4E88 RB3D_AARESOLVE_CTL
+0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
+0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD
+0x4EF8 RB3D_CONSTANT_COLOR_AR
+0x4EFC RB3D_CONSTANT_COLOR_GB
+0x4F04 ZB_ZSTENCILCNTL
+0x4F08 ZB_STENCILREFMASK
+0x4F14 ZB_ZTOP
+0x4F18 ZB_ZCACHE_CTLSTAT
+0x4F1C ZB_BW_CNTL
+0x4F28 ZB_DEPTHCLEARVALUE
+0x4F30 ZB_ZMASK_OFFSET
+0x4F34 ZB_ZMASK_PITCH
+0x4F38 ZB_ZMASK_WRINDEX
+0x4F3C ZB_ZMASK_DWORD
+0x4F40 ZB_ZMASK_RDINDEX
+0x4F44 ZB_HIZ_OFFSET
+0x4F48 ZB_HIZ_WRINDEX
+0x4F4C ZB_HIZ_DWORD
+0x4F50 ZB_HIZ_RDINDEX
+0x4F54 ZB_HIZ_PITCH
+0x4F58 ZB_ZPASS_DATA
+0x4F60 ZB_DEPTHXY_OFFSET
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 31a7f668ae5..60a194f1d9a 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -31,6 +31,7 @@
 #include "radeon.h"
 #include "radeon_share.h"
 
+#include "rv515_reg_safe.h"
 /* rv515 depends on : */
 void r100_hdp_reset(struct radeon_device *rdev);
 int r100_cp_reset(struct radeon_device *rdev);
@@ -464,72 +465,13 @@ int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
 #endif
 }
 
-
 /*
  * Asic initialization
  */
-static const unsigned r500_reg_safe_bm[219] = {
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF,
-	0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000,
-	0xF0000038, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0x1FFFFC78, 0xFFFFE000, 0xFFFFFFFE, 0xFFFFFFFF,
-	0x38CF8F50, 0xFFF88082, 0xFF0000FC, 0xFAE009FF,
-	0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
-	0xFFFF8CFC, 0xFFFFC1FF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF80FFFF,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x0003FC01, 0x3FFFFCF8, 0xFE800B19, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-};
-
 int rv515_init(struct radeon_device *rdev)
 {
-	rdev->config.r300.reg_safe_bm = r500_reg_safe_bm;
-	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r500_reg_safe_bm);
+	rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
+	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
 	return 0;
 }
 
-- 
cgit v1.2.3


From c9c97b8c75019814d8c007059bc827bb475be917 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 27 Aug 2009 09:53:47 +1000
Subject: drm/ttm: consolidate cache flushing code in one place.

This merges the TTM and drm cache flushing into one file in the
drm core.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_cache.c  | 51 +++++++++++++++++++++++++++------
 drivers/gpu/drm/ttm/ttm_tt.c | 67 ++------------------------------------------
 include/drm/drm_cache.h      | 38 +++++++++++++++++++++++++
 3 files changed, 82 insertions(+), 74 deletions(-)
 create mode 100644 include/drm/drm_cache.h

diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
index 0e994a0e46d..3a5575e638d 100644
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu/drm/drm_cache.c
@@ -45,25 +45,58 @@ drm_clflush_page(struct page *page)
 		clflush(page_virtual + i);
 	kunmap_atomic(page_virtual, KM_USER0);
 }
-#endif
 
+static void drm_cache_flush_clflush(struct page *pages[],
+				    unsigned long num_pages)
+{
+	unsigned long i;
+
+	mb();
+	for (i = 0; i < num_pages; i++)
+		drm_clflush_page(*pages++);
+	mb();
+}
+
+static void
+drm_clflush_ipi_handler(void *null)
+{
+	wbinvd();
+}
+#elif !defined(__powerpc__)
+static void drm_cache_ipi_handler(void *dummy)
+{
+}
+#endif
 void
 drm_clflush_pages(struct page *pages[], unsigned long num_pages)
 {
 
 #if defined(CONFIG_X86)
 	if (cpu_has_clflush) {
-		unsigned long i;
-
-		mb();
-		for (i = 0; i < num_pages; ++i)
-			drm_clflush_page(*pages++);
-		mb();
-
+		drm_cache_flush_clflush(pages, num_pages);
 		return;
 	}
 
-	wbinvd();
+	if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0)
+		printk(KERN_ERR "Timed out waiting for cache flush.\n");
+
+#elif defined(__powerpc__)
+	unsigned long i;
+	for (i = 0; i < num_pages; i++) {
+		struct page *page = pages[i];
+		void *page_virtual;
+
+		if (unlikely(page == NULL))
+			continue;
+
+		page_virtual = kmap_atomic(page, KM_USER0);
+		flush_dcache_range((unsigned long)page_virtual,
+				   (unsigned long)page_virtual + PAGE_SIZE);
+		kunmap_atomic(page_virtual, KM_USER0);
+	}
+#else
+	if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0)
+		printk(KERN_ERR "Timed out waiting for drm cache flush\n");
 #endif
 }
 EXPORT_SYMBOL(drm_clflush_pages);
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 42cca551976..a55ee1a56c1 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -34,76 +34,13 @@
 #include <linux/pagemap.h>
 #include <linux/file.h>
 #include <linux/swap.h>
+#include "drm_cache.h"
 #include "ttm/ttm_module.h"
 #include "ttm/ttm_bo_driver.h"
 #include "ttm/ttm_placement.h"
 
 static int ttm_tt_swapin(struct ttm_tt *ttm);
 
-#if defined(CONFIG_X86)
-static void ttm_tt_clflush_page(struct page *page)
-{
-	uint8_t *page_virtual;
-	unsigned int i;
-
-	if (unlikely(page == NULL))
-		return;
-
-	page_virtual = kmap_atomic(page, KM_USER0);
-
-	for (i = 0; i < PAGE_SIZE; i += boot_cpu_data.x86_clflush_size)
-		clflush(page_virtual + i);
-
-	kunmap_atomic(page_virtual, KM_USER0);
-}
-
-static void ttm_tt_cache_flush_clflush(struct page *pages[],
-				       unsigned long num_pages)
-{
-	unsigned long i;
-
-	mb();
-	for (i = 0; i < num_pages; ++i)
-		ttm_tt_clflush_page(*pages++);
-	mb();
-}
-#elif !defined(__powerpc__)
-static void ttm_tt_ipi_handler(void *null)
-{
-	;
-}
-#endif
-
-void ttm_tt_cache_flush(struct page *pages[], unsigned long num_pages)
-{
-
-#if defined(CONFIG_X86)
-	if (cpu_has_clflush) {
-		ttm_tt_cache_flush_clflush(pages, num_pages);
-		return;
-	}
-#elif defined(__powerpc__)
-	unsigned long i;
-
-	for (i = 0; i < num_pages; ++i) {
-		struct page *page = pages[i];
-		void *page_virtual;
-
-		if (unlikely(page == NULL))
-			continue;
-
-		page_virtual = kmap_atomic(page, KM_USER0);
-		flush_dcache_range((unsigned long) page_virtual,
-				   (unsigned long) page_virtual + PAGE_SIZE);
-		kunmap_atomic(page_virtual, KM_USER0);
-	}
-#else
-	if (on_each_cpu(ttm_tt_ipi_handler, NULL, 1) != 0)
-		printk(KERN_ERR TTM_PFX
-		       "Timed out waiting for drm cache flush.\n");
-#endif
-}
-
 /**
  * Allocates storage for pointers to the pages that back the ttm.
  *
@@ -302,7 +239,7 @@ static int ttm_tt_set_caching(struct ttm_tt *ttm,
 	}
 
 	if (ttm->caching_state == tt_cached)
-		ttm_tt_cache_flush(ttm->pages, ttm->num_pages);
+		drm_clflush_pages(ttm->pages, ttm->num_pages);
 
 	for (i = 0; i < ttm->num_pages; ++i) {
 		cur_page = ttm->pages[i];
diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h
new file mode 100644
index 00000000000..7bfb063029d
--- /dev/null
+++ b/include/drm/drm_cache.h
@@ -0,0 +1,38 @@
+/**************************************************************************
+ *
+ * Copyright 2009 Red Hat Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ **************************************************************************/
+/*
+ * Authors:
+ * Dave Airlie <airlied@redhat.com>
+ */
+
+#ifndef _DRM_CACHE_H_
+#define _DRM_CACHE_H_
+
+void drm_clflush_pages(struct page *pages[], unsigned long num_pages);
+
+#endif
-- 
cgit v1.2.3


From ece2be7993cc5e269cbf0cad6442b401a2c31915 Mon Sep 17 00:00:00 2001
From: Ben Hutchings <ben@decadent.org.uk>
Date: Sun, 23 Aug 2009 18:34:25 +0100
Subject: drm/mga: Use request_firmware() to load microcode

Image format is IHEX, one record for each pipe in order (record
addresses are ignored).

Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/Kconfig         |     1 +
 drivers/gpu/drm/mga/mga_dma.c   |     4 +-
 drivers/gpu/drm/mga/mga_drv.h   |     1 -
 drivers/gpu/drm/mga/mga_ucode.h | 11645 --------------------------------------
 drivers/gpu/drm/mga/mga_warp.c  |   180 +-
 firmware/Makefile               |     1 +
 firmware/WHENCE                 |    32 +
 firmware/matrox/g200_warp.H16   |    28 +
 firmware/matrox/g400_warp.H16   |    44 +
 9 files changed, 186 insertions(+), 11750 deletions(-)
 delete mode 100644 drivers/gpu/drm/mga/mga_ucode.h
 create mode 100644 firmware/matrox/g200_warp.H16
 create mode 100644 firmware/matrox/g400_warp.H16

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 39b393d38bb..10edc9b0022 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -116,6 +116,7 @@ endchoice
 config DRM_MGA
 	tristate "Matrox g200/g400"
 	depends on DRM
+	select FW_LOADER
 	help
 	  Choose this option if you have a Matrox G200, G400 or G450 graphics
 	  card.  If M is selected, the module will be called mga.  AGP
diff --git a/drivers/gpu/drm/mga/mga_dma.c b/drivers/gpu/drm/mga/mga_dma.c
index 6c67a02910c..3c917fb3a60 100644
--- a/drivers/gpu/drm/mga/mga_dma.c
+++ b/drivers/gpu/drm/mga/mga_dma.c
@@ -444,7 +444,7 @@ static int mga_do_agp_dma_bootstrap(struct drm_device * dev,
 {
 	drm_mga_private_t *const dev_priv =
 	    (drm_mga_private_t *) dev->dev_private;
-	unsigned int warp_size = mga_warp_microcode_size(dev_priv);
+	unsigned int warp_size = MGA_WARP_UCODE_SIZE;
 	int err;
 	unsigned offset;
 	const unsigned secondary_size = dma_bs->secondary_bin_count
@@ -619,7 +619,7 @@ static int mga_do_pci_dma_bootstrap(struct drm_device * dev,
 {
 	drm_mga_private_t *const dev_priv =
 	    (drm_mga_private_t *) dev->dev_private;
-	unsigned int warp_size = mga_warp_microcode_size(dev_priv);
+	unsigned int warp_size = MGA_WARP_UCODE_SIZE;
 	unsigned int primary_size;
 	unsigned int bin_count;
 	int err;
diff --git a/drivers/gpu/drm/mga/mga_drv.h b/drivers/gpu/drm/mga/mga_drv.h
index 3d264f28823..be6c6b9b0e8 100644
--- a/drivers/gpu/drm/mga/mga_drv.h
+++ b/drivers/gpu/drm/mga/mga_drv.h
@@ -177,7 +177,6 @@ extern void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv);
 extern int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf);
 
 				/* mga_warp.c */
-extern unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv);
 extern int mga_warp_install_microcode(drm_mga_private_t * dev_priv);
 extern int mga_warp_init(drm_mga_private_t * dev_priv);
 
diff --git a/drivers/gpu/drm/mga/mga_ucode.h b/drivers/gpu/drm/mga/mga_ucode.h
deleted file mode 100644
index b611e27470e..00000000000
--- a/drivers/gpu/drm/mga/mga_ucode.h
+++ /dev/null
@@ -1,11645 +0,0 @@
-/* mga_ucode.h -- Matrox G200/G400 WARP engine microcode -*- linux-c -*-
- * Created: Thu Jan 11 21:20:43 2001 by gareth@valinux.com
- *
- * Copyright 1999 Matrox Graphics Inc.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * MATROX GRAPHICS INC., OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
- * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Kernel-based WARP engine management:
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-/*
- * WARP pipes are named according to the functions they perform, where:
- *
- *   - T stands for computation of texture stage 0
- *   - T2 stands for computation of both texture stage 0 and texture stage 1
- *   - G stands for computation of triangle intensity (Gouraud interpolation)
- *   - Z stands for computation of Z buffer interpolation
- *   - S stands for computation of specular highlight
- *   - A stands for computation of the alpha channel
- *   - F stands for computation of vertex fog interpolation
- */
-
-static unsigned char warp_g200_tgz[] = {
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x98, 0xA0, 0xE9,
-	0x40, 0x40, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x1F, 0xD7, 0x18, 0xBD,
-	0x3F, 0xD7, 0x22, 0xBD,
-
-	0x81, 0x04,
-	0x89, 0x04,
-	0x01, 0x04,
-	0x09, 0x04,
-
-	0xC9, 0x41, 0xC0, 0xEC,
-	0x11, 0x04,
-	0x00, 0xE0,
-
-	0x41, 0xCC, 0x41, 0xCD,
-	0x49, 0xCC, 0x49, 0xCD,
-
-	0xD1, 0x41, 0xC0, 0xEC,
-	0x51, 0xCC, 0x51, 0xCD,
-
-	0x80, 0x04,
-	0x10, 0x04,
-	0x08, 0x04,
-	0x00, 0xE0,
-
-	0x00, 0xCC, 0xC0, 0xCD,
-	0xD1, 0x49, 0xC0, 0xEC,
-
-	0x8A, 0x1F, 0x20, 0xE9,
-	0x8B, 0x3F, 0x20, 0xE9,
-
-	0x41, 0x3C, 0x41, 0xAD,
-	0x49, 0x3C, 0x49, 0xAD,
-
-	0x10, 0xCC, 0x10, 0xCD,
-	0x08, 0xCC, 0x08, 0xCD,
-
-	0xB9, 0x41, 0x49, 0xBB,
-	0x1F, 0xF0, 0x41, 0xCD,
-
-	0x51, 0x3C, 0x51, 0xAD,
-	0x00, 0x98, 0x80, 0xE9,
-
-	0x72, 0x80, 0x07, 0xEA,
-	0x24, 0x1F, 0x20, 0xE9,
-
-	0x15, 0x41, 0x49, 0xBD,
-	0x1D, 0x41, 0x51, 0xBD,
-
-	0x2E, 0x41, 0x2A, 0xB8,
-	0x34, 0x53, 0xA0, 0xE8,
-
-	0x15, 0x30,
-	0x1D, 0x30,
-	0x58, 0xE3,
-	0x00, 0xE0,
-
-	0xB5, 0x40, 0x48, 0xBD,
-	0x3D, 0x40, 0x50, 0xBD,
-
-	0x24, 0x43, 0xA0, 0xE8,
-	0x2C, 0x4B, 0xA0, 0xE8,
-
-	0x15, 0x72,
-	0x09, 0xE3,
-	0x00, 0xE0,
-	0x1D, 0x72,
-
-	0x35, 0x30,
-	0xB5, 0x30,
-	0xBD, 0x30,
-	0x3D, 0x30,
-
-	0x9C, 0x97, 0x57, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x6C, 0x64, 0xC8, 0xEC,
-	0x98, 0xE1,
-	0xB5, 0x05,
-
-	0xBD, 0x05,
-	0x2E, 0x30,
-	0x32, 0xC0, 0xA0, 0xE8,
-
-	0x33, 0xC0, 0xA0, 0xE8,
-	0x74, 0x64, 0xC8, 0xEC,
-
-	0x40, 0x3C, 0x40, 0xAD,
-	0x32, 0x6A,
-	0x2A, 0x30,
-
-	0x20, 0x73,
-	0x33, 0x6A,
-	0x00, 0xE0,
-	0x28, 0x73,
-
-	0x1C, 0x72,
-	0x83, 0xE2,
-	0x60, 0x80, 0x15, 0xEA,
-
-	0xB8, 0x3D, 0x28, 0xDF,
-	0x30, 0x35, 0x20, 0xDF,
-
-	0x40, 0x30,
-	0x00, 0xE0,
-	0xCC, 0xE2,
-	0x64, 0x72,
-
-	0x25, 0x42, 0x52, 0xBF,
-	0x2D, 0x42, 0x4A, 0xBF,
-
-	0x30, 0x2E, 0x30, 0xDF,
-	0x38, 0x2E, 0x38, 0xDF,
-
-	0x18, 0x1D, 0x45, 0xE9,
-	0x1E, 0x15, 0x45, 0xE9,
-
-	0x2B, 0x49, 0x51, 0xBD,
-	0x00, 0xE0,
-	0x1F, 0x73,
-
-	0x38, 0x38, 0x40, 0xAF,
-	0x30, 0x30, 0x40, 0xAF,
-
-	0x24, 0x1F, 0x24, 0xDF,
-	0x1D, 0x32, 0x20, 0xE9,
-
-	0x2C, 0x1F, 0x2C, 0xDF,
-	0x1A, 0x33, 0x20, 0xE9,
-
-	0xB0, 0x10,
-	0x08, 0xE3,
-	0x40, 0x10,
-	0xB8, 0x10,
-
-	0x26, 0xF0, 0x30, 0xCD,
-	0x2F, 0xF0, 0x38, 0xCD,
-
-	0x2B, 0x80, 0x20, 0xE9,
-	0x2A, 0x80, 0x20, 0xE9,
-
-	0xA6, 0x20,
-	0x88, 0xE2,
-	0x00, 0xE0,
-	0xAF, 0x20,
-
-	0x28, 0x2A, 0x26, 0xAF,
-	0x20, 0x2A, 0xC0, 0xAF,
-
-	0x34, 0x1F, 0x34, 0xDF,
-	0x46, 0x24, 0x46, 0xDF,
-
-	0x28, 0x30, 0x80, 0xBF,
-	0x20, 0x38, 0x80, 0xBF,
-
-	0x47, 0x24, 0x47, 0xDF,
-	0x4E, 0x2C, 0x4E, 0xDF,
-
-	0x4F, 0x2C, 0x4F, 0xDF,
-	0x56, 0x34, 0x56, 0xDF,
-
-	0x28, 0x15, 0x28, 0xDF,
-	0x20, 0x1D, 0x20, 0xDF,
-
-	0x57, 0x34, 0x57, 0xDF,
-	0x00, 0xE0,
-	0x1D, 0x05,
-
-	0x04, 0x80, 0x10, 0xEA,
-	0x89, 0xE2,
-	0x2B, 0x30,
-
-	0x3F, 0xC1, 0x1D, 0xBD,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xA0, 0x68,
-	0xBF, 0x25,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x20, 0xC0, 0x20, 0xAF,
-	0x28, 0x05,
-	0x97, 0x74,
-
-	0x00, 0xE0,
-	0x2A, 0x10,
-	0x16, 0xC0, 0x20, 0xE9,
-
-	0x04, 0x80, 0x10, 0xEA,
-	0x8C, 0xE2,
-	0x95, 0x05,
-
-	0x28, 0xC1, 0x28, 0xAD,
-	0x1F, 0xC1, 0x15, 0xBD,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xA8, 0x67,
-	0x9F, 0x6B,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x28, 0xC0, 0x28, 0xAD,
-	0x1D, 0x25,
-	0x20, 0x05,
-
-	0x28, 0x32, 0x80, 0xAD,
-	0x40, 0x2A, 0x40, 0xBD,
-
-	0x1C, 0x80, 0x20, 0xE9,
-	0x20, 0x33, 0x20, 0xAD,
-
-	0x20, 0x73,
-	0x00, 0xE0,
-	0xB6, 0x49, 0x51, 0xBB,
-
-	0x26, 0x2F, 0xB0, 0xE8,
-	0x19, 0x20, 0x20, 0xE9,
-
-	0x35, 0x20, 0x35, 0xDF,
-	0x3D, 0x20, 0x3D, 0xDF,
-
-	0x15, 0x20, 0x15, 0xDF,
-	0x1D, 0x20, 0x1D, 0xDF,
-
-	0x26, 0xD0, 0x26, 0xCD,
-	0x29, 0x49, 0x2A, 0xB8,
-
-	0x26, 0x40, 0x80, 0xBD,
-	0x3B, 0x48, 0x50, 0xBD,
-
-	0x3E, 0x54, 0x57, 0x9F,
-	0x00, 0xE0,
-	0x82, 0xE1,
-
-	0x1E, 0xAF, 0x59, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x26, 0x30,
-	0x29, 0x30,
-	0x48, 0x3C, 0x48, 0xAD,
-
-	0x2B, 0x72,
-	0xC2, 0xE1,
-	0x2C, 0xC0, 0x44, 0xC2,
-
-	0x05, 0x24, 0x34, 0xBF,
-	0x0D, 0x24, 0x2C, 0xBF,
-
-	0x2D, 0x46, 0x4E, 0xBF,
-	0x25, 0x46, 0x56, 0xBF,
-
-	0x20, 0x1D, 0x6F, 0x8F,
-	0x32, 0x3E, 0x5F, 0xE9,
-
-	0x3E, 0x50, 0x56, 0x9F,
-	0x00, 0xE0,
-	0x3B, 0x30,
-
-	0x1E, 0x8F, 0x51, 0x9F,
-	0x33, 0x1E, 0x5F, 0xE9,
-
-	0x05, 0x44, 0x54, 0xB2,
-	0x0D, 0x44, 0x4C, 0xB2,
-
-	0x19, 0xC0, 0xB0, 0xE8,
-	0x34, 0xC0, 0x44, 0xC4,
-
-	0x33, 0x73,
-	0x00, 0xE0,
-	0x3E, 0x62, 0x57, 0x9F,
-
-	0x1E, 0xAF, 0x59, 0x9F,
-	0x00, 0xE0,
-	0x0D, 0x20,
-
-	0x84, 0x3E, 0x58, 0xE9,
-	0x28, 0x1D, 0x6F, 0x8F,
-
-	0x05, 0x20,
-	0x00, 0xE0,
-	0x85, 0x1E, 0x58, 0xE9,
-
-	0x9B, 0x3B, 0x33, 0xDF,
-	0x20, 0x20, 0x42, 0xAF,
-
-	0x30, 0x42, 0x56, 0x9F,
-	0x80, 0x3E, 0x57, 0xE9,
-
-	0x3F, 0x8F, 0x51, 0x9F,
-	0x30, 0x80, 0x5F, 0xE9,
-
-	0x28, 0x28, 0x24, 0xAF,
-	0x81, 0x1E, 0x57, 0xE9,
-
-	0x05, 0x47, 0x57, 0xBF,
-	0x0D, 0x47, 0x4F, 0xBF,
-
-	0x88, 0x80, 0x58, 0xE9,
-	0x1B, 0x29, 0x1B, 0xDF,
-
-	0x30, 0x1D, 0x6F, 0x8F,
-	0x3A, 0x30, 0x4F, 0xE9,
-
-	0x1C, 0x30, 0x26, 0xDF,
-	0x09, 0xE3,
-	0x3B, 0x05,
-
-	0x3E, 0x50, 0x56, 0x9F,
-	0x3B, 0x3F, 0x4F, 0xE9,
-
-	0x1E, 0x8F, 0x51, 0x9F,
-	0x00, 0xE0,
-	0xAC, 0x20,
-
-	0x2D, 0x44, 0x4C, 0xB4,
-	0x2C, 0x1C, 0xC0, 0xAF,
-
-	0x25, 0x44, 0x54, 0xB4,
-	0x00, 0xE0,
-	0xC8, 0x30,
-
-	0x30, 0x46, 0x30, 0xAF,
-	0x1B, 0x1B, 0x48, 0xAF,
-
-	0x00, 0xE0,
-	0x25, 0x20,
-	0x38, 0x2C, 0x4F, 0xE9,
-
-	0x86, 0x80, 0x57, 0xE9,
-	0x38, 0x1D, 0x6F, 0x8F,
-
-	0x28, 0x74,
-	0x00, 0xE0,
-	0x0D, 0x44, 0x4C, 0xB0,
-
-	0x05, 0x44, 0x54, 0xB0,
-	0x2D, 0x20,
-	0x9B, 0x10,
-
-	0x82, 0x3E, 0x57, 0xE9,
-	0x32, 0xF0, 0x1B, 0xCD,
-
-	0x1E, 0xBD, 0x59, 0x9F,
-	0x83, 0x1E, 0x57, 0xE9,
-
-	0x38, 0x47, 0x38, 0xAF,
-	0x34, 0x20,
-	0x2A, 0x30,
-
-	0x00, 0xE0,
-	0x0D, 0x20,
-	0x32, 0x20,
-	0x05, 0x20,
-
-	0x87, 0x80, 0x57, 0xE9,
-	0x1F, 0x54, 0x57, 0x9F,
-
-	0x17, 0x42, 0x56, 0x9F,
-	0x00, 0xE0,
-	0x3B, 0x6A,
-
-	0x3F, 0x8F, 0x51, 0x9F,
-	0x37, 0x1E, 0x4F, 0xE9,
-
-	0x37, 0x32, 0x2A, 0xAF,
-	0x00, 0xE0,
-	0x32, 0x00,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x27, 0xC0, 0x44, 0xC0,
-
-	0x36, 0x1F, 0x4F, 0xE9,
-	0x1F, 0x1F, 0x26, 0xDF,
-
-	0x37, 0x1B, 0x37, 0xBF,
-	0x17, 0x26, 0x17, 0xDF,
-
-	0x3E, 0x17, 0x4F, 0xE9,
-	0x3F, 0x3F, 0x4F, 0xE9,
-
-	0x34, 0x1F, 0x34, 0xAF,
-	0x2B, 0x05,
-	0xA7, 0x20,
-
-	0x33, 0x2B, 0x37, 0xDF,
-	0x27, 0x17, 0xC0, 0xAF,
-
-	0x34, 0x80, 0x4F, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x03, 0x80, 0x0A, 0xEA,
-	0x17, 0xC1, 0x2B, 0xBD,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xB3, 0x68,
-	0x97, 0x25,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x33, 0xC0, 0x33, 0xAF,
-	0x3C, 0x27, 0x4F, 0xE9,
-
-	0x57, 0x39, 0x20, 0xE9,
-	0x28, 0x19, 0x60, 0xEC,
-
-	0x2B, 0x32, 0x20, 0xE9,
-	0x1D, 0x3B, 0x20, 0xE9,
-
-	0xB3, 0x05,
-	0x00, 0xE0,
-	0x16, 0x28, 0x20, 0xE9,
-
-	0x23, 0x3B, 0x33, 0xAD,
-	0x1E, 0x2B, 0x20, 0xE9,
-
-	0x1C, 0x80, 0x20, 0xE9,
-	0x57, 0x36, 0x20, 0xE9,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x40, 0x40, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x90, 0xE2,
-	0x00, 0xE0,
-
-	0x85, 0xFF, 0x20, 0xEA,
-	0x19, 0xC8, 0xC1, 0xCD,
-
-	0x1F, 0xD7, 0x18, 0xBD,
-	0x3F, 0xD7, 0x22, 0xBD,
-
-	0x9F, 0x41, 0x49, 0xBD,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x25, 0x41, 0x49, 0xBD,
-	0x2D, 0x41, 0x51, 0xBD,
-
-	0x0D, 0x80, 0x07, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x35, 0x40, 0x48, 0xBD,
-	0x3D, 0x40, 0x50, 0xBD,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x25, 0x30,
-	0x2D, 0x30,
-
-	0x35, 0x30,
-	0xB5, 0x30,
-	0xBD, 0x30,
-	0x3D, 0x30,
-
-	0x9C, 0xA7, 0x5B, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x84, 0xFF, 0x0A, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xC9, 0x41, 0xC8, 0xEC,
-	0x42, 0xE1,
-	0x00, 0xE0,
-
-	0x82, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xC8, 0x40, 0xC0, 0xEC,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x7F, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-};
-
-static unsigned char warp_g200_tgza[] = {
-
-	0x00, 0x98, 0xA0, 0xE9,
-	0x40, 0x40, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x1F, 0xD7, 0x18, 0xBD,
-	0x3F, 0xD7, 0x22, 0xBD,
-
-	0x81, 0x04,
-	0x89, 0x04,
-	0x01, 0x04,
-	0x09, 0x04,
-
-	0xC9, 0x41, 0xC0, 0xEC,
-	0x11, 0x04,
-	0x00, 0xE0,
-
-	0x41, 0xCC, 0x41, 0xCD,
-	0x49, 0xCC, 0x49, 0xCD,
-
-	0xD1, 0x41, 0xC0, 0xEC,
-	0x51, 0xCC, 0x51, 0xCD,
-
-	0x80, 0x04,
-	0x10, 0x04,
-	0x08, 0x04,
-	0x00, 0xE0,
-
-	0x00, 0xCC, 0xC0, 0xCD,
-	0xD1, 0x49, 0xC0, 0xEC,
-
-	0x8A, 0x1F, 0x20, 0xE9,
-	0x8B, 0x3F, 0x20, 0xE9,
-
-	0x41, 0x3C, 0x41, 0xAD,
-	0x49, 0x3C, 0x49, 0xAD,
-
-	0x10, 0xCC, 0x10, 0xCD,
-	0x08, 0xCC, 0x08, 0xCD,
-
-	0xB9, 0x41, 0x49, 0xBB,
-	0x1F, 0xF0, 0x41, 0xCD,
-
-	0x51, 0x3C, 0x51, 0xAD,
-	0x00, 0x98, 0x80, 0xE9,
-
-	0x7D, 0x80, 0x07, 0xEA,
-	0x24, 0x1F, 0x20, 0xE9,
-
-	0x15, 0x41, 0x49, 0xBD,
-	0x1D, 0x41, 0x51, 0xBD,
-
-	0x2E, 0x41, 0x2A, 0xB8,
-	0x34, 0x53, 0xA0, 0xE8,
-
-	0x15, 0x30,
-	0x1D, 0x30,
-	0x58, 0xE3,
-	0x00, 0xE0,
-
-	0xB5, 0x40, 0x48, 0xBD,
-	0x3D, 0x40, 0x50, 0xBD,
-
-	0x24, 0x43, 0xA0, 0xE8,
-	0x2C, 0x4B, 0xA0, 0xE8,
-
-	0x15, 0x72,
-	0x09, 0xE3,
-	0x00, 0xE0,
-	0x1D, 0x72,
-
-	0x35, 0x30,
-	0xB5, 0x30,
-	0xBD, 0x30,
-	0x3D, 0x30,
-
-	0x9C, 0x97, 0x57, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x6C, 0x64, 0xC8, 0xEC,
-	0x98, 0xE1,
-	0xB5, 0x05,
-
-	0xBD, 0x05,
-	0x2E, 0x30,
-	0x32, 0xC0, 0xA0, 0xE8,
-
-	0x33, 0xC0, 0xA0, 0xE8,
-	0x74, 0x64, 0xC8, 0xEC,
-
-	0x40, 0x3C, 0x40, 0xAD,
-	0x32, 0x6A,
-	0x2A, 0x30,
-
-	0x20, 0x73,
-	0x33, 0x6A,
-	0x00, 0xE0,
-	0x28, 0x73,
-
-	0x1C, 0x72,
-	0x83, 0xE2,
-	0x6B, 0x80, 0x15, 0xEA,
-
-	0xB8, 0x3D, 0x28, 0xDF,
-	0x30, 0x35, 0x20, 0xDF,
-
-	0x40, 0x30,
-	0x00, 0xE0,
-	0xCC, 0xE2,
-	0x64, 0x72,
-
-	0x25, 0x42, 0x52, 0xBF,
-	0x2D, 0x42, 0x4A, 0xBF,
-
-	0x30, 0x2E, 0x30, 0xDF,
-	0x38, 0x2E, 0x38, 0xDF,
-
-	0x18, 0x1D, 0x45, 0xE9,
-	0x1E, 0x15, 0x45, 0xE9,
-
-	0x2B, 0x49, 0x51, 0xBD,
-	0x00, 0xE0,
-	0x1F, 0x73,
-
-	0x38, 0x38, 0x40, 0xAF,
-	0x30, 0x30, 0x40, 0xAF,
-
-	0x24, 0x1F, 0x24, 0xDF,
-	0x1D, 0x32, 0x20, 0xE9,
-
-	0x2C, 0x1F, 0x2C, 0xDF,
-	0x1A, 0x33, 0x20, 0xE9,
-
-	0xB0, 0x10,
-	0x08, 0xE3,
-	0x40, 0x10,
-	0xB8, 0x10,
-
-	0x26, 0xF0, 0x30, 0xCD,
-	0x2F, 0xF0, 0x38, 0xCD,
-
-	0x2B, 0x80, 0x20, 0xE9,
-	0x2A, 0x80, 0x20, 0xE9,
-
-	0xA6, 0x20,
-	0x88, 0xE2,
-	0x00, 0xE0,
-	0xAF, 0x20,
-
-	0x28, 0x2A, 0x26, 0xAF,
-	0x20, 0x2A, 0xC0, 0xAF,
-
-	0x34, 0x1F, 0x34, 0xDF,
-	0x46, 0x24, 0x46, 0xDF,
-
-	0x28, 0x30, 0x80, 0xBF,
-	0x20, 0x38, 0x80, 0xBF,
-
-	0x47, 0x24, 0x47, 0xDF,
-	0x4E, 0x2C, 0x4E, 0xDF,
-
-	0x4F, 0x2C, 0x4F, 0xDF,
-	0x56, 0x34, 0x56, 0xDF,
-
-	0x28, 0x15, 0x28, 0xDF,
-	0x20, 0x1D, 0x20, 0xDF,
-
-	0x57, 0x34, 0x57, 0xDF,
-	0x00, 0xE0,
-	0x1D, 0x05,
-
-	0x04, 0x80, 0x10, 0xEA,
-	0x89, 0xE2,
-	0x2B, 0x30,
-
-	0x3F, 0xC1, 0x1D, 0xBD,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xA0, 0x68,
-	0xBF, 0x25,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x20, 0xC0, 0x20, 0xAF,
-	0x28, 0x05,
-	0x97, 0x74,
-
-	0x00, 0xE0,
-	0x2A, 0x10,
-	0x16, 0xC0, 0x20, 0xE9,
-
-	0x04, 0x80, 0x10, 0xEA,
-	0x8C, 0xE2,
-	0x95, 0x05,
-
-	0x28, 0xC1, 0x28, 0xAD,
-	0x1F, 0xC1, 0x15, 0xBD,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xA8, 0x67,
-	0x9F, 0x6B,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x28, 0xC0, 0x28, 0xAD,
-	0x1D, 0x25,
-	0x20, 0x05,
-
-	0x28, 0x32, 0x80, 0xAD,
-	0x40, 0x2A, 0x40, 0xBD,
-
-	0x1C, 0x80, 0x20, 0xE9,
-	0x20, 0x33, 0x20, 0xAD,
-
-	0x20, 0x73,
-	0x00, 0xE0,
-	0xB6, 0x49, 0x51, 0xBB,
-
-	0x26, 0x2F, 0xB0, 0xE8,
-	0x19, 0x20, 0x20, 0xE9,
-
-	0x35, 0x20, 0x35, 0xDF,
-	0x3D, 0x20, 0x3D, 0xDF,
-
-	0x15, 0x20, 0x15, 0xDF,
-	0x1D, 0x20, 0x1D, 0xDF,
-
-	0x26, 0xD0, 0x26, 0xCD,
-	0x29, 0x49, 0x2A, 0xB8,
-
-	0x26, 0x40, 0x80, 0xBD,
-	0x3B, 0x48, 0x50, 0xBD,
-
-	0x3E, 0x54, 0x57, 0x9F,
-	0x00, 0xE0,
-	0x82, 0xE1,
-
-	0x1E, 0xAF, 0x59, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x26, 0x30,
-	0x29, 0x30,
-	0x48, 0x3C, 0x48, 0xAD,
-
-	0x2B, 0x72,
-	0xC2, 0xE1,
-	0x2C, 0xC0, 0x44, 0xC2,
-
-	0x05, 0x24, 0x34, 0xBF,
-	0x0D, 0x24, 0x2C, 0xBF,
-
-	0x2D, 0x46, 0x4E, 0xBF,
-	0x25, 0x46, 0x56, 0xBF,
-
-	0x20, 0x1D, 0x6F, 0x8F,
-	0x32, 0x3E, 0x5F, 0xE9,
-
-	0x3E, 0x50, 0x56, 0x9F,
-	0x00, 0xE0,
-	0x3B, 0x30,
-
-	0x1E, 0x8F, 0x51, 0x9F,
-	0x33, 0x1E, 0x5F, 0xE9,
-
-	0x05, 0x44, 0x54, 0xB2,
-	0x0D, 0x44, 0x4C, 0xB2,
-
-	0x19, 0xC0, 0xB0, 0xE8,
-	0x34, 0xC0, 0x44, 0xC4,
-
-	0x33, 0x73,
-	0x00, 0xE0,
-	0x3E, 0x62, 0x57, 0x9F,
-
-	0x1E, 0xAF, 0x59, 0x9F,
-	0x00, 0xE0,
-	0x0D, 0x20,
-
-	0x84, 0x3E, 0x58, 0xE9,
-	0x28, 0x1D, 0x6F, 0x8F,
-
-	0x05, 0x20,
-	0x00, 0xE0,
-	0x85, 0x1E, 0x58, 0xE9,
-
-	0x9B, 0x3B, 0x33, 0xDF,
-	0x20, 0x20, 0x42, 0xAF,
-
-	0x30, 0x42, 0x56, 0x9F,
-	0x80, 0x3E, 0x57, 0xE9,
-
-	0x3F, 0x8F, 0x51, 0x9F,
-	0x30, 0x80, 0x5F, 0xE9,
-
-	0x28, 0x28, 0x24, 0xAF,
-	0x81, 0x1E, 0x57, 0xE9,
-
-	0x05, 0x47, 0x57, 0xBF,
-	0x0D, 0x47, 0x4F, 0xBF,
-
-	0x88, 0x80, 0x58, 0xE9,
-	0x1B, 0x29, 0x1B, 0xDF,
-
-	0x30, 0x1D, 0x6F, 0x8F,
-	0x3A, 0x30, 0x4F, 0xE9,
-
-	0x1C, 0x30, 0x26, 0xDF,
-	0x09, 0xE3,
-	0x3B, 0x05,
-
-	0x3E, 0x50, 0x56, 0x9F,
-	0x3B, 0x3F, 0x4F, 0xE9,
-
-	0x1E, 0x8F, 0x51, 0x9F,
-	0x00, 0xE0,
-	0xAC, 0x20,
-
-	0x2D, 0x44, 0x4C, 0xB4,
-	0x2C, 0x1C, 0xC0, 0xAF,
-
-	0x25, 0x44, 0x54, 0xB4,
-	0x00, 0xE0,
-	0xC8, 0x30,
-
-	0x30, 0x46, 0x30, 0xAF,
-	0x1B, 0x1B, 0x48, 0xAF,
-
-	0x00, 0xE0,
-	0x25, 0x20,
-	0x38, 0x2C, 0x4F, 0xE9,
-
-	0x86, 0x80, 0x57, 0xE9,
-	0x38, 0x1D, 0x6F, 0x8F,
-
-	0x28, 0x74,
-	0x00, 0xE0,
-	0x0D, 0x44, 0x4C, 0xB0,
-
-	0x05, 0x44, 0x54, 0xB0,
-	0x2D, 0x20,
-	0x9B, 0x10,
-
-	0x82, 0x3E, 0x57, 0xE9,
-	0x32, 0xF0, 0x1B, 0xCD,
-
-	0x1E, 0xBD, 0x59, 0x9F,
-	0x83, 0x1E, 0x57, 0xE9,
-
-	0x38, 0x47, 0x38, 0xAF,
-	0x34, 0x20,
-	0x2A, 0x30,
-
-	0x00, 0xE0,
-	0x0D, 0x20,
-	0x32, 0x20,
-	0x05, 0x20,
-
-	0x87, 0x80, 0x57, 0xE9,
-	0x1F, 0x54, 0x57, 0x9F,
-
-	0x17, 0x42, 0x56, 0x9F,
-	0x00, 0xE0,
-	0x3B, 0x6A,
-
-	0x3F, 0x8F, 0x51, 0x9F,
-	0x37, 0x1E, 0x4F, 0xE9,
-
-	0x37, 0x32, 0x2A, 0xAF,
-	0x00, 0xE0,
-	0x32, 0x00,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x27, 0xC0, 0x44, 0xC0,
-
-	0x36, 0x1F, 0x4F, 0xE9,
-	0x1F, 0x1F, 0x26, 0xDF,
-
-	0x37, 0x1B, 0x37, 0xBF,
-	0x17, 0x26, 0x17, 0xDF,
-
-	0x3E, 0x17, 0x4F, 0xE9,
-	0x3F, 0x3F, 0x4F, 0xE9,
-
-	0x34, 0x1F, 0x34, 0xAF,
-	0x2B, 0x05,
-	0xA7, 0x20,
-
-	0x33, 0x2B, 0x37, 0xDF,
-	0x27, 0x17, 0xC0, 0xAF,
-
-	0x34, 0x80, 0x4F, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x2D, 0x44, 0x4C, 0xB6,
-	0x25, 0x44, 0x54, 0xB6,
-
-	0x03, 0x80, 0x2A, 0xEA,
-	0x17, 0xC1, 0x2B, 0xBD,
-
-	0x2D, 0x20,
-	0x25, 0x20,
-	0x07, 0xC0, 0x44, 0xC6,
-
-	0xB3, 0x68,
-	0x97, 0x25,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x33, 0xC0, 0x33, 0xAF,
-	0x3C, 0x27, 0x4F, 0xE9,
-
-	0x1F, 0x62, 0x57, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x3F, 0x3D, 0x5D, 0x9F,
-	0x00, 0xE0,
-	0x07, 0x20,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x28, 0x19, 0x60, 0xEC,
-
-	0xB3, 0x05,
-	0x00, 0xE0,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x23, 0x3B, 0x33, 0xAD,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x1F, 0x26, 0x1F, 0xDF,
-	0x9D, 0x1F, 0x4F, 0xE9,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x9E, 0x3F, 0x4F, 0xE9,
-
-	0x07, 0x07, 0x1F, 0xAF,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x9C, 0x80, 0x4F, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x57, 0x39, 0x20, 0xE9,
-
-	0x16, 0x28, 0x20, 0xE9,
-	0x1D, 0x3B, 0x20, 0xE9,
-
-	0x1E, 0x2B, 0x20, 0xE9,
-	0x2B, 0x32, 0x20, 0xE9,
-
-	0x1C, 0x23, 0x20, 0xE9,
-	0x57, 0x36, 0x20, 0xE9,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x40, 0x40, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x90, 0xE2,
-	0x00, 0xE0,
-
-	0x7A, 0xFF, 0x20, 0xEA,
-	0x19, 0xC8, 0xC1, 0xCD,
-
-	0x1F, 0xD7, 0x18, 0xBD,
-	0x3F, 0xD7, 0x22, 0xBD,
-
-	0x9F, 0x41, 0x49, 0xBD,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x25, 0x41, 0x49, 0xBD,
-	0x2D, 0x41, 0x51, 0xBD,
-
-	0x0D, 0x80, 0x07, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x35, 0x40, 0x48, 0xBD,
-	0x3D, 0x40, 0x50, 0xBD,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x25, 0x30,
-	0x2D, 0x30,
-
-	0x35, 0x30,
-	0xB5, 0x30,
-	0xBD, 0x30,
-	0x3D, 0x30,
-
-	0x9C, 0xA7, 0x5B, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x79, 0xFF, 0x0A, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xC9, 0x41, 0xC8, 0xEC,
-	0x42, 0xE1,
-	0x00, 0xE0,
-
-	0x77, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xC8, 0x40, 0xC0, 0xEC,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x74, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-};
-
-static unsigned char warp_g200_tgzaf[] = {
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x98, 0xA0, 0xE9,
-	0x40, 0x40, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x1F, 0xD7, 0x18, 0xBD,
-	0x3F, 0xD7, 0x22, 0xBD,
-
-	0x81, 0x04,
-	0x89, 0x04,
-	0x01, 0x04,
-	0x09, 0x04,
-
-	0xC9, 0x41, 0xC0, 0xEC,
-	0x11, 0x04,
-	0x00, 0xE0,
-
-	0x41, 0xCC, 0x41, 0xCD,
-	0x49, 0xCC, 0x49, 0xCD,
-
-	0xD1, 0x41, 0xC0, 0xEC,
-	0x51, 0xCC, 0x51, 0xCD,
-
-	0x80, 0x04,
-	0x10, 0x04,
-	0x08, 0x04,
-	0x00, 0xE0,
-
-	0x00, 0xCC, 0xC0, 0xCD,
-	0xD1, 0x49, 0xC0, 0xEC,
-
-	0x8A, 0x1F, 0x20, 0xE9,
-	0x8B, 0x3F, 0x20, 0xE9,
-
-	0x41, 0x3C, 0x41, 0xAD,
-	0x49, 0x3C, 0x49, 0xAD,
-
-	0x10, 0xCC, 0x10, 0xCD,
-	0x08, 0xCC, 0x08, 0xCD,
-
-	0xB9, 0x41, 0x49, 0xBB,
-	0x1F, 0xF0, 0x41, 0xCD,
-
-	0x51, 0x3C, 0x51, 0xAD,
-	0x00, 0x98, 0x80, 0xE9,
-
-	0x83, 0x80, 0x07, 0xEA,
-	0x24, 0x1F, 0x20, 0xE9,
-
-	0x21, 0x45, 0x80, 0xE8,
-	0x1A, 0x4D, 0x80, 0xE8,
-
-	0x31, 0x55, 0x80, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x15, 0x41, 0x49, 0xBD,
-	0x1D, 0x41, 0x51, 0xBD,
-
-	0x2E, 0x41, 0x2A, 0xB8,
-	0x34, 0x53, 0xA0, 0xE8,
-
-	0x15, 0x30,
-	0x1D, 0x30,
-	0x58, 0xE3,
-	0x00, 0xE0,
-
-	0xB5, 0x40, 0x48, 0xBD,
-	0x3D, 0x40, 0x50, 0xBD,
-
-	0x24, 0x43, 0xA0, 0xE8,
-	0x2C, 0x4B, 0xA0, 0xE8,
-
-	0x15, 0x72,
-	0x09, 0xE3,
-	0x00, 0xE0,
-	0x1D, 0x72,
-
-	0x35, 0x30,
-	0xB5, 0x30,
-	0xBD, 0x30,
-	0x3D, 0x30,
-
-	0x9C, 0x97, 0x57, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x6C, 0x64, 0xC8, 0xEC,
-	0x98, 0xE1,
-	0xB5, 0x05,
-
-	0xBD, 0x05,
-	0x2E, 0x30,
-	0x32, 0xC0, 0xA0, 0xE8,
-
-	0x33, 0xC0, 0xA0, 0xE8,
-	0x74, 0x64, 0xC8, 0xEC,
-
-	0x40, 0x3C, 0x40, 0xAD,
-	0x32, 0x6A,
-	0x2A, 0x30,
-
-	0x20, 0x73,
-	0x33, 0x6A,
-	0x00, 0xE0,
-	0x28, 0x73,
-
-	0x1C, 0x72,
-	0x83, 0xE2,
-	0x6F, 0x80, 0x15, 0xEA,
-
-	0xB8, 0x3D, 0x28, 0xDF,
-	0x30, 0x35, 0x20, 0xDF,
-
-	0x40, 0x30,
-	0x00, 0xE0,
-	0xCC, 0xE2,
-	0x64, 0x72,
-
-	0x25, 0x42, 0x52, 0xBF,
-	0x2D, 0x42, 0x4A, 0xBF,
-
-	0x30, 0x2E, 0x30, 0xDF,
-	0x38, 0x2E, 0x38, 0xDF,
-
-	0x18, 0x1D, 0x45, 0xE9,
-	0x1E, 0x15, 0x45, 0xE9,
-
-	0x2B, 0x49, 0x51, 0xBD,
-	0x00, 0xE0,
-	0x1F, 0x73,
-
-	0x38, 0x38, 0x40, 0xAF,
-	0x30, 0x30, 0x40, 0xAF,
-
-	0x24, 0x1F, 0x24, 0xDF,
-	0x1D, 0x32, 0x20, 0xE9,
-
-	0x2C, 0x1F, 0x2C, 0xDF,
-	0x1A, 0x33, 0x20, 0xE9,
-
-	0xB0, 0x10,
-	0x08, 0xE3,
-	0x40, 0x10,
-	0xB8, 0x10,
-
-	0x26, 0xF0, 0x30, 0xCD,
-	0x2F, 0xF0, 0x38, 0xCD,
-
-	0x2B, 0x80, 0x20, 0xE9,
-	0x2A, 0x80, 0x20, 0xE9,
-
-	0xA6, 0x20,
-	0x88, 0xE2,
-	0x00, 0xE0,
-	0xAF, 0x20,
-
-	0x28, 0x2A, 0x26, 0xAF,
-	0x20, 0x2A, 0xC0, 0xAF,
-
-	0x34, 0x1F, 0x34, 0xDF,
-	0x46, 0x24, 0x46, 0xDF,
-
-	0x28, 0x30, 0x80, 0xBF,
-	0x20, 0x38, 0x80, 0xBF,
-
-	0x47, 0x24, 0x47, 0xDF,
-	0x4E, 0x2C, 0x4E, 0xDF,
-
-	0x4F, 0x2C, 0x4F, 0xDF,
-	0x56, 0x34, 0x56, 0xDF,
-
-	0x28, 0x15, 0x28, 0xDF,
-	0x20, 0x1D, 0x20, 0xDF,
-
-	0x57, 0x34, 0x57, 0xDF,
-	0x00, 0xE0,
-	0x1D, 0x05,
-
-	0x04, 0x80, 0x10, 0xEA,
-	0x89, 0xE2,
-	0x2B, 0x30,
-
-	0x3F, 0xC1, 0x1D, 0xBD,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xA0, 0x68,
-	0xBF, 0x25,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x20, 0xC0, 0x20, 0xAF,
-	0x28, 0x05,
-	0x97, 0x74,
-
-	0x00, 0xE0,
-	0x2A, 0x10,
-	0x16, 0xC0, 0x20, 0xE9,
-
-	0x04, 0x80, 0x10, 0xEA,
-	0x8C, 0xE2,
-	0x95, 0x05,
-
-	0x28, 0xC1, 0x28, 0xAD,
-	0x1F, 0xC1, 0x15, 0xBD,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xA8, 0x67,
-	0x9F, 0x6B,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x28, 0xC0, 0x28, 0xAD,
-	0x1D, 0x25,
-	0x20, 0x05,
-
-	0x28, 0x32, 0x80, 0xAD,
-	0x40, 0x2A, 0x40, 0xBD,
-
-	0x1C, 0x80, 0x20, 0xE9,
-	0x20, 0x33, 0x20, 0xAD,
-
-	0x20, 0x73,
-	0x00, 0xE0,
-	0xB6, 0x49, 0x51, 0xBB,
-
-	0x26, 0x2F, 0xB0, 0xE8,
-	0x19, 0x20, 0x20, 0xE9,
-
-	0x35, 0x20, 0x35, 0xDF,
-	0x3D, 0x20, 0x3D, 0xDF,
-
-	0x15, 0x20, 0x15, 0xDF,
-	0x1D, 0x20, 0x1D, 0xDF,
-
-	0x26, 0xD0, 0x26, 0xCD,
-	0x29, 0x49, 0x2A, 0xB8,
-
-	0x26, 0x40, 0x80, 0xBD,
-	0x3B, 0x48, 0x50, 0xBD,
-
-	0x3E, 0x54, 0x57, 0x9F,
-	0x00, 0xE0,
-	0x82, 0xE1,
-
-	0x1E, 0xAF, 0x59, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x26, 0x30,
-	0x29, 0x30,
-	0x48, 0x3C, 0x48, 0xAD,
-
-	0x2B, 0x72,
-	0xC2, 0xE1,
-	0x2C, 0xC0, 0x44, 0xC2,
-
-	0x05, 0x24, 0x34, 0xBF,
-	0x0D, 0x24, 0x2C, 0xBF,
-
-	0x2D, 0x46, 0x4E, 0xBF,
-	0x25, 0x46, 0x56, 0xBF,
-
-	0x20, 0x1D, 0x6F, 0x8F,
-	0x32, 0x3E, 0x5F, 0xE9,
-
-	0x3E, 0x50, 0x56, 0x9F,
-	0x00, 0xE0,
-	0x3B, 0x30,
-
-	0x1E, 0x8F, 0x51, 0x9F,
-	0x33, 0x1E, 0x5F, 0xE9,
-
-	0x05, 0x44, 0x54, 0xB2,
-	0x0D, 0x44, 0x4C, 0xB2,
-
-	0x19, 0xC0, 0xB0, 0xE8,
-	0x34, 0xC0, 0x44, 0xC4,
-
-	0x33, 0x73,
-	0x00, 0xE0,
-	0x3E, 0x62, 0x57, 0x9F,
-
-	0x1E, 0xAF, 0x59, 0x9F,
-	0x00, 0xE0,
-	0x0D, 0x20,
-
-	0x84, 0x3E, 0x58, 0xE9,
-	0x28, 0x1D, 0x6F, 0x8F,
-
-	0x05, 0x20,
-	0x00, 0xE0,
-	0x85, 0x1E, 0x58, 0xE9,
-
-	0x9B, 0x3B, 0x33, 0xDF,
-	0x20, 0x20, 0x42, 0xAF,
-
-	0x30, 0x42, 0x56, 0x9F,
-	0x80, 0x3E, 0x57, 0xE9,
-
-	0x3F, 0x8F, 0x51, 0x9F,
-	0x30, 0x80, 0x5F, 0xE9,
-
-	0x28, 0x28, 0x24, 0xAF,
-	0x81, 0x1E, 0x57, 0xE9,
-
-	0x05, 0x47, 0x57, 0xBF,
-	0x0D, 0x47, 0x4F, 0xBF,
-
-	0x88, 0x80, 0x58, 0xE9,
-	0x1B, 0x29, 0x1B, 0xDF,
-
-	0x30, 0x1D, 0x6F, 0x8F,
-	0x3A, 0x30, 0x4F, 0xE9,
-
-	0x1C, 0x30, 0x26, 0xDF,
-	0x09, 0xE3,
-	0x3B, 0x05,
-
-	0x3E, 0x50, 0x56, 0x9F,
-	0x3B, 0x3F, 0x4F, 0xE9,
-
-	0x1E, 0x8F, 0x51, 0x9F,
-	0x00, 0xE0,
-	0xAC, 0x20,
-
-	0x2D, 0x44, 0x4C, 0xB4,
-	0x2C, 0x1C, 0xC0, 0xAF,
-
-	0x25, 0x44, 0x54, 0xB4,
-	0x00, 0xE0,
-	0xC8, 0x30,
-
-	0x30, 0x46, 0x30, 0xAF,
-	0x1B, 0x1B, 0x48, 0xAF,
-
-	0x00, 0xE0,
-	0x25, 0x20,
-	0x38, 0x2C, 0x4F, 0xE9,
-
-	0x86, 0x80, 0x57, 0xE9,
-	0x38, 0x1D, 0x6F, 0x8F,
-
-	0x28, 0x74,
-	0x00, 0xE0,
-	0x0D, 0x44, 0x4C, 0xB0,
-
-	0x05, 0x44, 0x54, 0xB0,
-	0x2D, 0x20,
-	0x9B, 0x10,
-
-	0x82, 0x3E, 0x57, 0xE9,
-	0x32, 0xF0, 0x1B, 0xCD,
-
-	0x1E, 0xBD, 0x59, 0x9F,
-	0x83, 0x1E, 0x57, 0xE9,
-
-	0x38, 0x47, 0x38, 0xAF,
-	0x34, 0x20,
-	0x2A, 0x30,
-
-	0x00, 0xE0,
-	0x0D, 0x20,
-	0x32, 0x20,
-	0x05, 0x20,
-
-	0x87, 0x80, 0x57, 0xE9,
-	0x1F, 0x54, 0x57, 0x9F,
-
-	0x17, 0x42, 0x56, 0x9F,
-	0x00, 0xE0,
-	0x3B, 0x6A,
-
-	0x3F, 0x8F, 0x51, 0x9F,
-	0x37, 0x1E, 0x4F, 0xE9,
-
-	0x37, 0x32, 0x2A, 0xAF,
-	0x00, 0xE0,
-	0x32, 0x00,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x27, 0xC0, 0x44, 0xC0,
-
-	0x36, 0x1F, 0x4F, 0xE9,
-	0x1F, 0x1F, 0x26, 0xDF,
-
-	0x37, 0x1B, 0x37, 0xBF,
-	0x17, 0x26, 0x17, 0xDF,
-
-	0x3E, 0x17, 0x4F, 0xE9,
-	0x3F, 0x3F, 0x4F, 0xE9,
-
-	0x34, 0x1F, 0x34, 0xAF,
-	0x2B, 0x05,
-	0xA7, 0x20,
-
-	0x33, 0x2B, 0x37, 0xDF,
-	0x27, 0x17, 0xC0, 0xAF,
-
-	0x34, 0x80, 0x4F, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x0D, 0x21, 0x1A, 0xB6,
-	0x05, 0x21, 0x31, 0xB6,
-
-	0x2D, 0x44, 0x4C, 0xB6,
-	0x25, 0x44, 0x54, 0xB6,
-
-	0x03, 0x80, 0x2A, 0xEA,
-	0x17, 0xC1, 0x2B, 0xBD,
-
-	0x0D, 0x20,
-	0x05, 0x20,
-	0x2F, 0xC0, 0x21, 0xC6,
-
-	0xB3, 0x68,
-	0x97, 0x25,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x33, 0xC0, 0x33, 0xAF,
-	0x3C, 0x27, 0x4F, 0xE9,
-
-	0x00, 0xE0,
-	0x25, 0x20,
-	0x07, 0xC0, 0x44, 0xC6,
-
-	0x17, 0x50, 0x56, 0x9F,
-	0x00, 0xE0,
-	0x2D, 0x20,
-
-	0x37, 0x0F, 0x5C, 0x9F,
-	0x00, 0xE0,
-	0x2F, 0x20,
-
-	0x1F, 0x62, 0x57, 0x9F,
-	0x00, 0xE0,
-	0x07, 0x20,
-
-	0x3F, 0x3D, 0x5D, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x28, 0x19, 0x60, 0xEC,
-
-	0xB3, 0x05,
-	0x00, 0xE0,
-	0x17, 0x26, 0x17, 0xDF,
-
-	0x23, 0x3B, 0x33, 0xAD,
-	0x35, 0x17, 0x4F, 0xE9,
-
-	0x1F, 0x26, 0x1F, 0xDF,
-	0x9D, 0x1F, 0x4F, 0xE9,
-
-	0x9E, 0x3F, 0x4F, 0xE9,
-	0x39, 0x37, 0x4F, 0xE9,
-
-	0x2F, 0x2F, 0x17, 0xAF,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x07, 0x07, 0x1F, 0xAF,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x31, 0x80, 0x4F, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x9C, 0x80, 0x4F, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x57, 0x39, 0x20, 0xE9,
-
-	0x16, 0x28, 0x20, 0xE9,
-	0x1D, 0x3B, 0x20, 0xE9,
-
-	0x1E, 0x2B, 0x20, 0xE9,
-	0x2B, 0x32, 0x20, 0xE9,
-
-	0x1C, 0x23, 0x20, 0xE9,
-	0x57, 0x36, 0x20, 0xE9,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x40, 0x40, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x90, 0xE2,
-	0x00, 0xE0,
-
-	0x74, 0xFF, 0x20, 0xEA,
-	0x19, 0xC8, 0xC1, 0xCD,
-
-	0x1F, 0xD7, 0x18, 0xBD,
-	0x3F, 0xD7, 0x22, 0xBD,
-
-	0x9F, 0x41, 0x49, 0xBD,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x25, 0x41, 0x49, 0xBD,
-	0x2D, 0x41, 0x51, 0xBD,
-
-	0x0D, 0x80, 0x07, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x35, 0x40, 0x48, 0xBD,
-	0x3D, 0x40, 0x50, 0xBD,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x25, 0x30,
-	0x2D, 0x30,
-
-	0x35, 0x30,
-	0xB5, 0x30,
-	0xBD, 0x30,
-	0x3D, 0x30,
-
-	0x9C, 0xA7, 0x5B, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x73, 0xFF, 0x0A, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xC9, 0x41, 0xC8, 0xEC,
-	0x42, 0xE1,
-	0x00, 0xE0,
-
-	0x71, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xC8, 0x40, 0xC0, 0xEC,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x6E, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-};
-
-static unsigned char warp_g200_tgzf[] = {
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x98, 0xA0, 0xE9,
-	0x40, 0x40, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x1F, 0xD7, 0x18, 0xBD,
-	0x3F, 0xD7, 0x22, 0xBD,
-
-	0x81, 0x04,
-	0x89, 0x04,
-	0x01, 0x04,
-	0x09, 0x04,
-
-	0xC9, 0x41, 0xC0, 0xEC,
-	0x11, 0x04,
-	0x00, 0xE0,
-
-	0x41, 0xCC, 0x41, 0xCD,
-	0x49, 0xCC, 0x49, 0xCD,
-
-	0xD1, 0x41, 0xC0, 0xEC,
-	0x51, 0xCC, 0x51, 0xCD,
-
-	0x80, 0x04,
-	0x10, 0x04,
-	0x08, 0x04,
-	0x00, 0xE0,
-
-	0x00, 0xCC, 0xC0, 0xCD,
-	0xD1, 0x49, 0xC0, 0xEC,
-
-	0x8A, 0x1F, 0x20, 0xE9,
-	0x8B, 0x3F, 0x20, 0xE9,
-
-	0x41, 0x3C, 0x41, 0xAD,
-	0x49, 0x3C, 0x49, 0xAD,
-
-	0x10, 0xCC, 0x10, 0xCD,
-	0x08, 0xCC, 0x08, 0xCD,
-
-	0xB9, 0x41, 0x49, 0xBB,
-	0x1F, 0xF0, 0x41, 0xCD,
-
-	0x51, 0x3C, 0x51, 0xAD,
-	0x00, 0x98, 0x80, 0xE9,
-
-	0x7F, 0x80, 0x07, 0xEA,
-	0x24, 0x1F, 0x20, 0xE9,
-
-	0x21, 0x45, 0x80, 0xE8,
-	0x1A, 0x4D, 0x80, 0xE8,
-
-	0x31, 0x55, 0x80, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x15, 0x41, 0x49, 0xBD,
-	0x1D, 0x41, 0x51, 0xBD,
-
-	0x2E, 0x41, 0x2A, 0xB8,
-	0x34, 0x53, 0xA0, 0xE8,
-
-	0x15, 0x30,
-	0x1D, 0x30,
-	0x58, 0xE3,
-	0x00, 0xE0,
-
-	0xB5, 0x40, 0x48, 0xBD,
-	0x3D, 0x40, 0x50, 0xBD,
-
-	0x24, 0x43, 0xA0, 0xE8,
-	0x2C, 0x4B, 0xA0, 0xE8,
-
-	0x15, 0x72,
-	0x09, 0xE3,
-	0x00, 0xE0,
-	0x1D, 0x72,
-
-	0x35, 0x30,
-	0xB5, 0x30,
-	0xBD, 0x30,
-	0x3D, 0x30,
-
-	0x9C, 0x97, 0x57, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x6C, 0x64, 0xC8, 0xEC,
-	0x98, 0xE1,
-	0xB5, 0x05,
-
-	0xBD, 0x05,
-	0x2E, 0x30,
-	0x32, 0xC0, 0xA0, 0xE8,
-
-	0x33, 0xC0, 0xA0, 0xE8,
-	0x74, 0x64, 0xC8, 0xEC,
-
-	0x40, 0x3C, 0x40, 0xAD,
-	0x32, 0x6A,
-	0x2A, 0x30,
-
-	0x20, 0x73,
-	0x33, 0x6A,
-	0x00, 0xE0,
-	0x28, 0x73,
-
-	0x1C, 0x72,
-	0x83, 0xE2,
-	0x6B, 0x80, 0x15, 0xEA,
-
-	0xB8, 0x3D, 0x28, 0xDF,
-	0x30, 0x35, 0x20, 0xDF,
-
-	0x40, 0x30,
-	0x00, 0xE0,
-	0xCC, 0xE2,
-	0x64, 0x72,
-
-	0x25, 0x42, 0x52, 0xBF,
-	0x2D, 0x42, 0x4A, 0xBF,
-
-	0x30, 0x2E, 0x30, 0xDF,
-	0x38, 0x2E, 0x38, 0xDF,
-
-	0x18, 0x1D, 0x45, 0xE9,
-	0x1E, 0x15, 0x45, 0xE9,
-
-	0x2B, 0x49, 0x51, 0xBD,
-	0x00, 0xE0,
-	0x1F, 0x73,
-
-	0x38, 0x38, 0x40, 0xAF,
-	0x30, 0x30, 0x40, 0xAF,
-
-	0x24, 0x1F, 0x24, 0xDF,
-	0x1D, 0x32, 0x20, 0xE9,
-
-	0x2C, 0x1F, 0x2C, 0xDF,
-	0x1A, 0x33, 0x20, 0xE9,
-
-	0xB0, 0x10,
-	0x08, 0xE3,
-	0x40, 0x10,
-	0xB8, 0x10,
-
-	0x26, 0xF0, 0x30, 0xCD,
-	0x2F, 0xF0, 0x38, 0xCD,
-
-	0x2B, 0x80, 0x20, 0xE9,
-	0x2A, 0x80, 0x20, 0xE9,
-
-	0xA6, 0x20,
-	0x88, 0xE2,
-	0x00, 0xE0,
-	0xAF, 0x20,
-
-	0x28, 0x2A, 0x26, 0xAF,
-	0x20, 0x2A, 0xC0, 0xAF,
-
-	0x34, 0x1F, 0x34, 0xDF,
-	0x46, 0x24, 0x46, 0xDF,
-
-	0x28, 0x30, 0x80, 0xBF,
-	0x20, 0x38, 0x80, 0xBF,
-
-	0x47, 0x24, 0x47, 0xDF,
-	0x4E, 0x2C, 0x4E, 0xDF,
-
-	0x4F, 0x2C, 0x4F, 0xDF,
-	0x56, 0x34, 0x56, 0xDF,
-
-	0x28, 0x15, 0x28, 0xDF,
-	0x20, 0x1D, 0x20, 0xDF,
-
-	0x57, 0x34, 0x57, 0xDF,
-	0x00, 0xE0,
-	0x1D, 0x05,
-
-	0x04, 0x80, 0x10, 0xEA,
-	0x89, 0xE2,
-	0x2B, 0x30,
-
-	0x3F, 0xC1, 0x1D, 0xBD,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xA0, 0x68,
-	0xBF, 0x25,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x20, 0xC0, 0x20, 0xAF,
-	0x28, 0x05,
-	0x97, 0x74,
-
-	0x00, 0xE0,
-	0x2A, 0x10,
-	0x16, 0xC0, 0x20, 0xE9,
-
-	0x04, 0x80, 0x10, 0xEA,
-	0x8C, 0xE2,
-	0x95, 0x05,
-
-	0x28, 0xC1, 0x28, 0xAD,
-	0x1F, 0xC1, 0x15, 0xBD,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xA8, 0x67,
-	0x9F, 0x6B,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x28, 0xC0, 0x28, 0xAD,
-	0x1D, 0x25,
-	0x20, 0x05,
-
-	0x28, 0x32, 0x80, 0xAD,
-	0x40, 0x2A, 0x40, 0xBD,
-
-	0x1C, 0x80, 0x20, 0xE9,
-	0x20, 0x33, 0x20, 0xAD,
-
-	0x20, 0x73,
-	0x00, 0xE0,
-	0xB6, 0x49, 0x51, 0xBB,
-
-	0x26, 0x2F, 0xB0, 0xE8,
-	0x19, 0x20, 0x20, 0xE9,
-
-	0x35, 0x20, 0x35, 0xDF,
-	0x3D, 0x20, 0x3D, 0xDF,
-
-	0x15, 0x20, 0x15, 0xDF,
-	0x1D, 0x20, 0x1D, 0xDF,
-
-	0x26, 0xD0, 0x26, 0xCD,
-	0x29, 0x49, 0x2A, 0xB8,
-
-	0x26, 0x40, 0x80, 0xBD,
-	0x3B, 0x48, 0x50, 0xBD,
-
-	0x3E, 0x54, 0x57, 0x9F,
-	0x00, 0xE0,
-	0x82, 0xE1,
-
-	0x1E, 0xAF, 0x59, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x26, 0x30,
-	0x29, 0x30,
-	0x48, 0x3C, 0x48, 0xAD,
-
-	0x2B, 0x72,
-	0xC2, 0xE1,
-	0x2C, 0xC0, 0x44, 0xC2,
-
-	0x05, 0x24, 0x34, 0xBF,
-	0x0D, 0x24, 0x2C, 0xBF,
-
-	0x2D, 0x46, 0x4E, 0xBF,
-	0x25, 0x46, 0x56, 0xBF,
-
-	0x20, 0x1D, 0x6F, 0x8F,
-	0x32, 0x3E, 0x5F, 0xE9,
-
-	0x3E, 0x50, 0x56, 0x9F,
-	0x00, 0xE0,
-	0x3B, 0x30,
-
-	0x1E, 0x8F, 0x51, 0x9F,
-	0x33, 0x1E, 0x5F, 0xE9,
-
-	0x05, 0x44, 0x54, 0xB2,
-	0x0D, 0x44, 0x4C, 0xB2,
-
-	0x19, 0xC0, 0xB0, 0xE8,
-	0x34, 0xC0, 0x44, 0xC4,
-
-	0x33, 0x73,
-	0x00, 0xE0,
-	0x3E, 0x62, 0x57, 0x9F,
-
-	0x1E, 0xAF, 0x59, 0x9F,
-	0x00, 0xE0,
-	0x0D, 0x20,
-
-	0x84, 0x3E, 0x58, 0xE9,
-	0x28, 0x1D, 0x6F, 0x8F,
-
-	0x05, 0x20,
-	0x00, 0xE0,
-	0x85, 0x1E, 0x58, 0xE9,
-
-	0x9B, 0x3B, 0x33, 0xDF,
-	0x20, 0x20, 0x42, 0xAF,
-
-	0x30, 0x42, 0x56, 0x9F,
-	0x80, 0x3E, 0x57, 0xE9,
-
-	0x3F, 0x8F, 0x51, 0x9F,
-	0x30, 0x80, 0x5F, 0xE9,
-
-	0x28, 0x28, 0x24, 0xAF,
-	0x81, 0x1E, 0x57, 0xE9,
-
-	0x05, 0x47, 0x57, 0xBF,
-	0x0D, 0x47, 0x4F, 0xBF,
-
-	0x88, 0x80, 0x58, 0xE9,
-	0x1B, 0x29, 0x1B, 0xDF,
-
-	0x30, 0x1D, 0x6F, 0x8F,
-	0x3A, 0x30, 0x4F, 0xE9,
-
-	0x1C, 0x30, 0x26, 0xDF,
-	0x09, 0xE3,
-	0x3B, 0x05,
-
-	0x3E, 0x50, 0x56, 0x9F,
-	0x3B, 0x3F, 0x4F, 0xE9,
-
-	0x1E, 0x8F, 0x51, 0x9F,
-	0x00, 0xE0,
-	0xAC, 0x20,
-
-	0x2D, 0x44, 0x4C, 0xB4,
-	0x2C, 0x1C, 0xC0, 0xAF,
-
-	0x25, 0x44, 0x54, 0xB4,
-	0x00, 0xE0,
-	0xC8, 0x30,
-
-	0x30, 0x46, 0x30, 0xAF,
-	0x1B, 0x1B, 0x48, 0xAF,
-
-	0x00, 0xE0,
-	0x25, 0x20,
-	0x38, 0x2C, 0x4F, 0xE9,
-
-	0x86, 0x80, 0x57, 0xE9,
-	0x38, 0x1D, 0x6F, 0x8F,
-
-	0x28, 0x74,
-	0x00, 0xE0,
-	0x0D, 0x44, 0x4C, 0xB0,
-
-	0x05, 0x44, 0x54, 0xB0,
-	0x2D, 0x20,
-	0x9B, 0x10,
-
-	0x82, 0x3E, 0x57, 0xE9,
-	0x32, 0xF0, 0x1B, 0xCD,
-
-	0x1E, 0xBD, 0x59, 0x9F,
-	0x83, 0x1E, 0x57, 0xE9,
-
-	0x38, 0x47, 0x38, 0xAF,
-	0x34, 0x20,
-	0x2A, 0x30,
-
-	0x00, 0xE0,
-	0x0D, 0x20,
-	0x32, 0x20,
-	0x05, 0x20,
-
-	0x87, 0x80, 0x57, 0xE9,
-	0x1F, 0x54, 0x57, 0x9F,
-
-	0x17, 0x42, 0x56, 0x9F,
-	0x00, 0xE0,
-	0x3B, 0x6A,
-
-	0x3F, 0x8F, 0x51, 0x9F,
-	0x37, 0x1E, 0x4F, 0xE9,
-
-	0x37, 0x32, 0x2A, 0xAF,
-	0x00, 0xE0,
-	0x32, 0x00,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x27, 0xC0, 0x44, 0xC0,
-
-	0x36, 0x1F, 0x4F, 0xE9,
-	0x1F, 0x1F, 0x26, 0xDF,
-
-	0x37, 0x1B, 0x37, 0xBF,
-	0x17, 0x26, 0x17, 0xDF,
-
-	0x3E, 0x17, 0x4F, 0xE9,
-	0x3F, 0x3F, 0x4F, 0xE9,
-
-	0x34, 0x1F, 0x34, 0xAF,
-	0x2B, 0x05,
-	0xA7, 0x20,
-
-	0x33, 0x2B, 0x37, 0xDF,
-	0x27, 0x17, 0xC0, 0xAF,
-
-	0x34, 0x80, 0x4F, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x0D, 0x21, 0x1A, 0xB6,
-	0x05, 0x21, 0x31, 0xB6,
-
-	0x03, 0x80, 0x2A, 0xEA,
-	0x17, 0xC1, 0x2B, 0xBD,
-
-	0x0D, 0x20,
-	0x05, 0x20,
-	0x2F, 0xC0, 0x21, 0xC6,
-
-	0xB3, 0x68,
-	0x97, 0x25,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x33, 0xC0, 0x33, 0xAF,
-	0x3C, 0x27, 0x4F, 0xE9,
-
-	0x17, 0x50, 0x56, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x37, 0x0F, 0x5C, 0x9F,
-	0x00, 0xE0,
-	0x2F, 0x20,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x28, 0x19, 0x60, 0xEC,
-
-	0xB3, 0x05,
-	0x00, 0xE0,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x23, 0x3B, 0x33, 0xAD,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x17, 0x26, 0x17, 0xDF,
-	0x35, 0x17, 0x4F, 0xE9,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x39, 0x37, 0x4F, 0xE9,
-
-	0x2F, 0x2F, 0x17, 0xAF,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x31, 0x80, 0x4F, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x57, 0x39, 0x20, 0xE9,
-
-	0x16, 0x28, 0x20, 0xE9,
-	0x1D, 0x3B, 0x20, 0xE9,
-
-	0x1E, 0x2B, 0x20, 0xE9,
-	0x2B, 0x32, 0x20, 0xE9,
-
-	0x1C, 0x23, 0x20, 0xE9,
-	0x57, 0x36, 0x20, 0xE9,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x40, 0x40, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x90, 0xE2,
-	0x00, 0xE0,
-
-	0x78, 0xFF, 0x20, 0xEA,
-	0x19, 0xC8, 0xC1, 0xCD,
-
-	0x1F, 0xD7, 0x18, 0xBD,
-	0x3F, 0xD7, 0x22, 0xBD,
-
-	0x9F, 0x41, 0x49, 0xBD,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x25, 0x41, 0x49, 0xBD,
-	0x2D, 0x41, 0x51, 0xBD,
-
-	0x0D, 0x80, 0x07, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x35, 0x40, 0x48, 0xBD,
-	0x3D, 0x40, 0x50, 0xBD,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x25, 0x30,
-	0x2D, 0x30,
-
-	0x35, 0x30,
-	0xB5, 0x30,
-	0xBD, 0x30,
-	0x3D, 0x30,
-
-	0x9C, 0xA7, 0x5B, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x77, 0xFF, 0x0A, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xC9, 0x41, 0xC8, 0xEC,
-	0x42, 0xE1,
-	0x00, 0xE0,
-
-	0x75, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xC8, 0x40, 0xC0, 0xEC,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x72, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-};
-
-static unsigned char warp_g200_tgzs[] = {
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x98, 0xA0, 0xE9,
-	0x40, 0x40, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x1F, 0xD7, 0x18, 0xBD,
-	0x3F, 0xD7, 0x22, 0xBD,
-
-	0x81, 0x04,
-	0x89, 0x04,
-	0x01, 0x04,
-	0x09, 0x04,
-
-	0xC9, 0x41, 0xC0, 0xEC,
-	0x11, 0x04,
-	0x00, 0xE0,
-
-	0x41, 0xCC, 0x41, 0xCD,
-	0x49, 0xCC, 0x49, 0xCD,
-
-	0xD1, 0x41, 0xC0, 0xEC,
-	0x51, 0xCC, 0x51, 0xCD,
-
-	0x80, 0x04,
-	0x10, 0x04,
-	0x08, 0x04,
-	0x00, 0xE0,
-
-	0x00, 0xCC, 0xC0, 0xCD,
-	0xD1, 0x49, 0xC0, 0xEC,
-
-	0x8A, 0x1F, 0x20, 0xE9,
-	0x8B, 0x3F, 0x20, 0xE9,
-
-	0x41, 0x3C, 0x41, 0xAD,
-	0x49, 0x3C, 0x49, 0xAD,
-
-	0x10, 0xCC, 0x10, 0xCD,
-	0x08, 0xCC, 0x08, 0xCD,
-
-	0xB9, 0x41, 0x49, 0xBB,
-	0x1F, 0xF0, 0x41, 0xCD,
-
-	0x51, 0x3C, 0x51, 0xAD,
-	0x00, 0x98, 0x80, 0xE9,
-
-	0x8B, 0x80, 0x07, 0xEA,
-	0x24, 0x1F, 0x20, 0xE9,
-
-	0x21, 0x45, 0x80, 0xE8,
-	0x1A, 0x4D, 0x80, 0xE8,
-
-	0x31, 0x55, 0x80, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x15, 0x41, 0x49, 0xBD,
-	0x1D, 0x41, 0x51, 0xBD,
-
-	0x2E, 0x41, 0x2A, 0xB8,
-	0x34, 0x53, 0xA0, 0xE8,
-
-	0x15, 0x30,
-	0x1D, 0x30,
-	0x58, 0xE3,
-	0x00, 0xE0,
-
-	0xB5, 0x40, 0x48, 0xBD,
-	0x3D, 0x40, 0x50, 0xBD,
-
-	0x24, 0x43, 0xA0, 0xE8,
-	0x2C, 0x4B, 0xA0, 0xE8,
-
-	0x15, 0x72,
-	0x09, 0xE3,
-	0x00, 0xE0,
-	0x1D, 0x72,
-
-	0x35, 0x30,
-	0xB5, 0x30,
-	0xBD, 0x30,
-	0x3D, 0x30,
-
-	0x9C, 0x97, 0x57, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x6C, 0x64, 0xC8, 0xEC,
-	0x98, 0xE1,
-	0xB5, 0x05,
-
-	0xBD, 0x05,
-	0x2E, 0x30,
-	0x32, 0xC0, 0xA0, 0xE8,
-
-	0x33, 0xC0, 0xA0, 0xE8,
-	0x74, 0x64, 0xC8, 0xEC,
-
-	0x40, 0x3C, 0x40, 0xAD,
-	0x32, 0x6A,
-	0x2A, 0x30,
-
-	0x20, 0x73,
-	0x33, 0x6A,
-	0x00, 0xE0,
-	0x28, 0x73,
-
-	0x1C, 0x72,
-	0x83, 0xE2,
-	0x77, 0x80, 0x15, 0xEA,
-
-	0xB8, 0x3D, 0x28, 0xDF,
-	0x30, 0x35, 0x20, 0xDF,
-
-	0x40, 0x30,
-	0x00, 0xE0,
-	0xCC, 0xE2,
-	0x64, 0x72,
-
-	0x25, 0x42, 0x52, 0xBF,
-	0x2D, 0x42, 0x4A, 0xBF,
-
-	0x30, 0x2E, 0x30, 0xDF,
-	0x38, 0x2E, 0x38, 0xDF,
-
-	0x18, 0x1D, 0x45, 0xE9,
-	0x1E, 0x15, 0x45, 0xE9,
-
-	0x2B, 0x49, 0x51, 0xBD,
-	0x00, 0xE0,
-	0x1F, 0x73,
-
-	0x38, 0x38, 0x40, 0xAF,
-	0x30, 0x30, 0x40, 0xAF,
-
-	0x24, 0x1F, 0x24, 0xDF,
-	0x1D, 0x32, 0x20, 0xE9,
-
-	0x2C, 0x1F, 0x2C, 0xDF,
-	0x1A, 0x33, 0x20, 0xE9,
-
-	0xB0, 0x10,
-	0x08, 0xE3,
-	0x40, 0x10,
-	0xB8, 0x10,
-
-	0x26, 0xF0, 0x30, 0xCD,
-	0x2F, 0xF0, 0x38, 0xCD,
-
-	0x2B, 0x80, 0x20, 0xE9,
-	0x2A, 0x80, 0x20, 0xE9,
-
-	0xA6, 0x20,
-	0x88, 0xE2,
-	0x00, 0xE0,
-	0xAF, 0x20,
-
-	0x28, 0x2A, 0x26, 0xAF,
-	0x20, 0x2A, 0xC0, 0xAF,
-
-	0x34, 0x1F, 0x34, 0xDF,
-	0x46, 0x24, 0x46, 0xDF,
-
-	0x28, 0x30, 0x80, 0xBF,
-	0x20, 0x38, 0x80, 0xBF,
-
-	0x47, 0x24, 0x47, 0xDF,
-	0x4E, 0x2C, 0x4E, 0xDF,
-
-	0x4F, 0x2C, 0x4F, 0xDF,
-	0x56, 0x34, 0x56, 0xDF,
-
-	0x28, 0x15, 0x28, 0xDF,
-	0x20, 0x1D, 0x20, 0xDF,
-
-	0x57, 0x34, 0x57, 0xDF,
-	0x00, 0xE0,
-	0x1D, 0x05,
-
-	0x04, 0x80, 0x10, 0xEA,
-	0x89, 0xE2,
-	0x2B, 0x30,
-
-	0x3F, 0xC1, 0x1D, 0xBD,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xA0, 0x68,
-	0xBF, 0x25,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x20, 0xC0, 0x20, 0xAF,
-	0x28, 0x05,
-	0x97, 0x74,
-
-	0x00, 0xE0,
-	0x2A, 0x10,
-	0x16, 0xC0, 0x20, 0xE9,
-
-	0x04, 0x80, 0x10, 0xEA,
-	0x8C, 0xE2,
-	0x95, 0x05,
-
-	0x28, 0xC1, 0x28, 0xAD,
-	0x1F, 0xC1, 0x15, 0xBD,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xA8, 0x67,
-	0x9F, 0x6B,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x28, 0xC0, 0x28, 0xAD,
-	0x1D, 0x25,
-	0x20, 0x05,
-
-	0x28, 0x32, 0x80, 0xAD,
-	0x40, 0x2A, 0x40, 0xBD,
-
-	0x1C, 0x80, 0x20, 0xE9,
-	0x20, 0x33, 0x20, 0xAD,
-
-	0x20, 0x73,
-	0x00, 0xE0,
-	0xB6, 0x49, 0x51, 0xBB,
-
-	0x26, 0x2F, 0xB0, 0xE8,
-	0x19, 0x20, 0x20, 0xE9,
-
-	0x35, 0x20, 0x35, 0xDF,
-	0x3D, 0x20, 0x3D, 0xDF,
-
-	0x15, 0x20, 0x15, 0xDF,
-	0x1D, 0x20, 0x1D, 0xDF,
-
-	0x26, 0xD0, 0x26, 0xCD,
-	0x29, 0x49, 0x2A, 0xB8,
-
-	0x26, 0x40, 0x80, 0xBD,
-	0x3B, 0x48, 0x50, 0xBD,
-
-	0x3E, 0x54, 0x57, 0x9F,
-	0x00, 0xE0,
-	0x82, 0xE1,
-
-	0x1E, 0xAF, 0x59, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x26, 0x30,
-	0x29, 0x30,
-	0x48, 0x3C, 0x48, 0xAD,
-
-	0x2B, 0x72,
-	0xC2, 0xE1,
-	0x2C, 0xC0, 0x44, 0xC2,
-
-	0x05, 0x24, 0x34, 0xBF,
-	0x0D, 0x24, 0x2C, 0xBF,
-
-	0x2D, 0x46, 0x4E, 0xBF,
-	0x25, 0x46, 0x56, 0xBF,
-
-	0x20, 0x1D, 0x6F, 0x8F,
-	0x32, 0x3E, 0x5F, 0xE9,
-
-	0x3E, 0x50, 0x56, 0x9F,
-	0x00, 0xE0,
-	0x3B, 0x30,
-
-	0x1E, 0x8F, 0x51, 0x9F,
-	0x33, 0x1E, 0x5F, 0xE9,
-
-	0x05, 0x44, 0x54, 0xB2,
-	0x0D, 0x44, 0x4C, 0xB2,
-
-	0x19, 0xC0, 0xB0, 0xE8,
-	0x34, 0xC0, 0x44, 0xC4,
-
-	0x33, 0x73,
-	0x00, 0xE0,
-	0x3E, 0x62, 0x57, 0x9F,
-
-	0x1E, 0xAF, 0x59, 0x9F,
-	0x00, 0xE0,
-	0x0D, 0x20,
-
-	0x84, 0x3E, 0x58, 0xE9,
-	0x28, 0x1D, 0x6F, 0x8F,
-
-	0x05, 0x20,
-	0x00, 0xE0,
-	0x85, 0x1E, 0x58, 0xE9,
-
-	0x9B, 0x3B, 0x33, 0xDF,
-	0x20, 0x20, 0x42, 0xAF,
-
-	0x30, 0x42, 0x56, 0x9F,
-	0x80, 0x3E, 0x57, 0xE9,
-
-	0x3F, 0x8F, 0x51, 0x9F,
-	0x30, 0x80, 0x5F, 0xE9,
-
-	0x28, 0x28, 0x24, 0xAF,
-	0x81, 0x1E, 0x57, 0xE9,
-
-	0x05, 0x47, 0x57, 0xBF,
-	0x0D, 0x47, 0x4F, 0xBF,
-
-	0x88, 0x80, 0x58, 0xE9,
-	0x1B, 0x29, 0x1B, 0xDF,
-
-	0x30, 0x1D, 0x6F, 0x8F,
-	0x3A, 0x30, 0x4F, 0xE9,
-
-	0x1C, 0x30, 0x26, 0xDF,
-	0x09, 0xE3,
-	0x3B, 0x05,
-
-	0x3E, 0x50, 0x56, 0x9F,
-	0x3B, 0x3F, 0x4F, 0xE9,
-
-	0x1E, 0x8F, 0x51, 0x9F,
-	0x00, 0xE0,
-	0xAC, 0x20,
-
-	0x2D, 0x44, 0x4C, 0xB4,
-	0x2C, 0x1C, 0xC0, 0xAF,
-
-	0x25, 0x44, 0x54, 0xB4,
-	0x00, 0xE0,
-	0xC8, 0x30,
-
-	0x30, 0x46, 0x30, 0xAF,
-	0x1B, 0x1B, 0x48, 0xAF,
-
-	0x00, 0xE0,
-	0x25, 0x20,
-	0x38, 0x2C, 0x4F, 0xE9,
-
-	0x86, 0x80, 0x57, 0xE9,
-	0x38, 0x1D, 0x6F, 0x8F,
-
-	0x28, 0x74,
-	0x00, 0xE0,
-	0x0D, 0x44, 0x4C, 0xB0,
-
-	0x05, 0x44, 0x54, 0xB0,
-	0x2D, 0x20,
-	0x9B, 0x10,
-
-	0x82, 0x3E, 0x57, 0xE9,
-	0x32, 0xF0, 0x1B, 0xCD,
-
-	0x1E, 0xBD, 0x59, 0x9F,
-	0x83, 0x1E, 0x57, 0xE9,
-
-	0x38, 0x47, 0x38, 0xAF,
-	0x34, 0x20,
-	0x2A, 0x30,
-
-	0x00, 0xE0,
-	0x0D, 0x20,
-	0x32, 0x20,
-	0x05, 0x20,
-
-	0x87, 0x80, 0x57, 0xE9,
-	0x1F, 0x54, 0x57, 0x9F,
-
-	0x17, 0x42, 0x56, 0x9F,
-	0x00, 0xE0,
-	0x3B, 0x6A,
-
-	0x3F, 0x8F, 0x51, 0x9F,
-	0x37, 0x1E, 0x4F, 0xE9,
-
-	0x37, 0x32, 0x2A, 0xAF,
-	0x00, 0xE0,
-	0x32, 0x00,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x27, 0xC0, 0x44, 0xC0,
-
-	0x36, 0x1F, 0x4F, 0xE9,
-	0x1F, 0x1F, 0x26, 0xDF,
-
-	0x37, 0x1B, 0x37, 0xBF,
-	0x17, 0x26, 0x17, 0xDF,
-
-	0x3E, 0x17, 0x4F, 0xE9,
-	0x3F, 0x3F, 0x4F, 0xE9,
-
-	0x34, 0x1F, 0x34, 0xAF,
-	0x2B, 0x05,
-	0xA7, 0x20,
-
-	0x33, 0x2B, 0x37, 0xDF,
-	0x27, 0x17, 0xC0, 0xAF,
-
-	0x34, 0x80, 0x4F, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x2D, 0x21, 0x1A, 0xB0,
-	0x25, 0x21, 0x31, 0xB0,
-
-	0x0D, 0x21, 0x1A, 0xB2,
-	0x05, 0x21, 0x31, 0xB2,
-
-	0x03, 0x80, 0x2A, 0xEA,
-	0x17, 0xC1, 0x2B, 0xBD,
-
-	0x2D, 0x20,
-	0x25, 0x20,
-	0x05, 0x20,
-	0x0D, 0x20,
-
-	0xB3, 0x68,
-	0x97, 0x25,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x33, 0xC0, 0x33, 0xAF,
-	0x2F, 0xC0, 0x21, 0xC0,
-
-	0x16, 0x42, 0x56, 0x9F,
-	0x3C, 0x27, 0x4F, 0xE9,
-
-	0x1E, 0x62, 0x57, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x25, 0x21, 0x31, 0xB4,
-	0x2D, 0x21, 0x1A, 0xB4,
-
-	0x3F, 0x2F, 0x5D, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x33, 0x05,
-	0x00, 0xE0,
-	0x28, 0x19, 0x60, 0xEC,
-
-	0x37, 0x0F, 0x5C, 0x9F,
-	0x00, 0xE0,
-	0x2F, 0x20,
-
-	0x23, 0x3B, 0x33, 0xAD,
-	0x1E, 0x26, 0x1E, 0xDF,
-
-	0xA7, 0x1E, 0x4F, 0xE9,
-	0x17, 0x26, 0x16, 0xDF,
-
-	0x2D, 0x20,
-	0x00, 0xE0,
-	0xA8, 0x3F, 0x4F, 0xE9,
-
-	0x2F, 0x2F, 0x1E, 0xAF,
-	0x25, 0x20,
-	0x00, 0xE0,
-
-	0xA4, 0x16, 0x4F, 0xE9,
-	0x0F, 0xC0, 0x21, 0xC2,
-
-	0xA6, 0x80, 0x4F, 0xE9,
-	0x1F, 0x62, 0x57, 0x9F,
-
-	0x3F, 0x2F, 0x5D, 0x9F,
-	0x00, 0xE0,
-	0x8F, 0x20,
-
-	0xA5, 0x37, 0x4F, 0xE9,
-	0x0F, 0x17, 0x0F, 0xAF,
-
-	0x06, 0xC0, 0x21, 0xC4,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0xA3, 0x80, 0x4F, 0xE9,
-
-	0x06, 0x20,
-	0x00, 0xE0,
-	0x1F, 0x26, 0x1F, 0xDF,
-
-	0xA1, 0x1F, 0x4F, 0xE9,
-	0xA2, 0x3F, 0x4F, 0xE9,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x06, 0x06, 0x1F, 0xAF,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xA0, 0x80, 0x4F, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x57, 0x39, 0x20, 0xE9,
-
-	0x16, 0x28, 0x20, 0xE9,
-	0x1D, 0x3B, 0x20, 0xE9,
-
-	0x1E, 0x2B, 0x20, 0xE9,
-	0x2B, 0x32, 0x20, 0xE9,
-
-	0x1C, 0x23, 0x20, 0xE9,
-	0x57, 0x36, 0x20, 0xE9,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x40, 0x40, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x90, 0xE2,
-	0x00, 0xE0,
-
-	0x6C, 0xFF, 0x20, 0xEA,
-	0x19, 0xC8, 0xC1, 0xCD,
-
-	0x1F, 0xD7, 0x18, 0xBD,
-	0x3F, 0xD7, 0x22, 0xBD,
-
-	0x9F, 0x41, 0x49, 0xBD,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x25, 0x41, 0x49, 0xBD,
-	0x2D, 0x41, 0x51, 0xBD,
-
-	0x0D, 0x80, 0x07, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x35, 0x40, 0x48, 0xBD,
-	0x3D, 0x40, 0x50, 0xBD,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x25, 0x30,
-	0x2D, 0x30,
-
-	0x35, 0x30,
-	0xB5, 0x30,
-	0xBD, 0x30,
-	0x3D, 0x30,
-
-	0x9C, 0xA7, 0x5B, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x6B, 0xFF, 0x0A, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xC9, 0x41, 0xC8, 0xEC,
-	0x42, 0xE1,
-	0x00, 0xE0,
-
-	0x69, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xC8, 0x40, 0xC0, 0xEC,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x66, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-};
-
-static unsigned char warp_g200_tgzsa[] = {
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x98, 0xA0, 0xE9,
-	0x40, 0x40, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x1F, 0xD7, 0x18, 0xBD,
-	0x3F, 0xD7, 0x22, 0xBD,
-
-	0x81, 0x04,
-	0x89, 0x04,
-	0x01, 0x04,
-	0x09, 0x04,
-
-	0xC9, 0x41, 0xC0, 0xEC,
-	0x11, 0x04,
-	0x00, 0xE0,
-
-	0x41, 0xCC, 0x41, 0xCD,
-	0x49, 0xCC, 0x49, 0xCD,
-
-	0xD1, 0x41, 0xC0, 0xEC,
-	0x51, 0xCC, 0x51, 0xCD,
-
-	0x80, 0x04,
-	0x10, 0x04,
-	0x08, 0x04,
-	0x00, 0xE0,
-
-	0x00, 0xCC, 0xC0, 0xCD,
-	0xD1, 0x49, 0xC0, 0xEC,
-
-	0x8A, 0x1F, 0x20, 0xE9,
-	0x8B, 0x3F, 0x20, 0xE9,
-
-	0x41, 0x3C, 0x41, 0xAD,
-	0x49, 0x3C, 0x49, 0xAD,
-
-	0x10, 0xCC, 0x10, 0xCD,
-	0x08, 0xCC, 0x08, 0xCD,
-
-	0xB9, 0x41, 0x49, 0xBB,
-	0x1F, 0xF0, 0x41, 0xCD,
-
-	0x51, 0x3C, 0x51, 0xAD,
-	0x00, 0x98, 0x80, 0xE9,
-
-	0x8F, 0x80, 0x07, 0xEA,
-	0x24, 0x1F, 0x20, 0xE9,
-
-	0x21, 0x45, 0x80, 0xE8,
-	0x1A, 0x4D, 0x80, 0xE8,
-
-	0x31, 0x55, 0x80, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x15, 0x41, 0x49, 0xBD,
-	0x1D, 0x41, 0x51, 0xBD,
-
-	0x2E, 0x41, 0x2A, 0xB8,
-	0x34, 0x53, 0xA0, 0xE8,
-
-	0x15, 0x30,
-	0x1D, 0x30,
-	0x58, 0xE3,
-	0x00, 0xE0,
-
-	0xB5, 0x40, 0x48, 0xBD,
-	0x3D, 0x40, 0x50, 0xBD,
-
-	0x24, 0x43, 0xA0, 0xE8,
-	0x2C, 0x4B, 0xA0, 0xE8,
-
-	0x15, 0x72,
-	0x09, 0xE3,
-	0x00, 0xE0,
-	0x1D, 0x72,
-
-	0x35, 0x30,
-	0xB5, 0x30,
-	0xBD, 0x30,
-	0x3D, 0x30,
-
-	0x9C, 0x97, 0x57, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x6C, 0x64, 0xC8, 0xEC,
-	0x98, 0xE1,
-	0xB5, 0x05,
-
-	0xBD, 0x05,
-	0x2E, 0x30,
-	0x32, 0xC0, 0xA0, 0xE8,
-
-	0x33, 0xC0, 0xA0, 0xE8,
-	0x74, 0x64, 0xC8, 0xEC,
-
-	0x40, 0x3C, 0x40, 0xAD,
-	0x32, 0x6A,
-	0x2A, 0x30,
-
-	0x20, 0x73,
-	0x33, 0x6A,
-	0x00, 0xE0,
-	0x28, 0x73,
-
-	0x1C, 0x72,
-	0x83, 0xE2,
-	0x7B, 0x80, 0x15, 0xEA,
-
-	0xB8, 0x3D, 0x28, 0xDF,
-	0x30, 0x35, 0x20, 0xDF,
-
-	0x40, 0x30,
-	0x00, 0xE0,
-	0xCC, 0xE2,
-	0x64, 0x72,
-
-	0x25, 0x42, 0x52, 0xBF,
-	0x2D, 0x42, 0x4A, 0xBF,
-
-	0x30, 0x2E, 0x30, 0xDF,
-	0x38, 0x2E, 0x38, 0xDF,
-
-	0x18, 0x1D, 0x45, 0xE9,
-	0x1E, 0x15, 0x45, 0xE9,
-
-	0x2B, 0x49, 0x51, 0xBD,
-	0x00, 0xE0,
-	0x1F, 0x73,
-
-	0x38, 0x38, 0x40, 0xAF,
-	0x30, 0x30, 0x40, 0xAF,
-
-	0x24, 0x1F, 0x24, 0xDF,
-	0x1D, 0x32, 0x20, 0xE9,
-
-	0x2C, 0x1F, 0x2C, 0xDF,
-	0x1A, 0x33, 0x20, 0xE9,
-
-	0xB0, 0x10,
-	0x08, 0xE3,
-	0x40, 0x10,
-	0xB8, 0x10,
-
-	0x26, 0xF0, 0x30, 0xCD,
-	0x2F, 0xF0, 0x38, 0xCD,
-
-	0x2B, 0x80, 0x20, 0xE9,
-	0x2A, 0x80, 0x20, 0xE9,
-
-	0xA6, 0x20,
-	0x88, 0xE2,
-	0x00, 0xE0,
-	0xAF, 0x20,
-
-	0x28, 0x2A, 0x26, 0xAF,
-	0x20, 0x2A, 0xC0, 0xAF,
-
-	0x34, 0x1F, 0x34, 0xDF,
-	0x46, 0x24, 0x46, 0xDF,
-
-	0x28, 0x30, 0x80, 0xBF,
-	0x20, 0x38, 0x80, 0xBF,
-
-	0x47, 0x24, 0x47, 0xDF,
-	0x4E, 0x2C, 0x4E, 0xDF,
-
-	0x4F, 0x2C, 0x4F, 0xDF,
-	0x56, 0x34, 0x56, 0xDF,
-
-	0x28, 0x15, 0x28, 0xDF,
-	0x20, 0x1D, 0x20, 0xDF,
-
-	0x57, 0x34, 0x57, 0xDF,
-	0x00, 0xE0,
-	0x1D, 0x05,
-
-	0x04, 0x80, 0x10, 0xEA,
-	0x89, 0xE2,
-	0x2B, 0x30,
-
-	0x3F, 0xC1, 0x1D, 0xBD,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xA0, 0x68,
-	0xBF, 0x25,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x20, 0xC0, 0x20, 0xAF,
-	0x28, 0x05,
-	0x97, 0x74,
-
-	0x00, 0xE0,
-	0x2A, 0x10,
-	0x16, 0xC0, 0x20, 0xE9,
-
-	0x04, 0x80, 0x10, 0xEA,
-	0x8C, 0xE2,
-	0x95, 0x05,
-
-	0x28, 0xC1, 0x28, 0xAD,
-	0x1F, 0xC1, 0x15, 0xBD,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xA8, 0x67,
-	0x9F, 0x6B,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x28, 0xC0, 0x28, 0xAD,
-	0x1D, 0x25,
-	0x20, 0x05,
-
-	0x28, 0x32, 0x80, 0xAD,
-	0x40, 0x2A, 0x40, 0xBD,
-
-	0x1C, 0x80, 0x20, 0xE9,
-	0x20, 0x33, 0x20, 0xAD,
-
-	0x20, 0x73,
-	0x00, 0xE0,
-	0xB6, 0x49, 0x51, 0xBB,
-
-	0x26, 0x2F, 0xB0, 0xE8,
-	0x19, 0x20, 0x20, 0xE9,
-
-	0x35, 0x20, 0x35, 0xDF,
-	0x3D, 0x20, 0x3D, 0xDF,
-
-	0x15, 0x20, 0x15, 0xDF,
-	0x1D, 0x20, 0x1D, 0xDF,
-
-	0x26, 0xD0, 0x26, 0xCD,
-	0x29, 0x49, 0x2A, 0xB8,
-
-	0x26, 0x40, 0x80, 0xBD,
-	0x3B, 0x48, 0x50, 0xBD,
-
-	0x3E, 0x54, 0x57, 0x9F,
-	0x00, 0xE0,
-	0x82, 0xE1,
-
-	0x1E, 0xAF, 0x59, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x26, 0x30,
-	0x29, 0x30,
-	0x48, 0x3C, 0x48, 0xAD,
-
-	0x2B, 0x72,
-	0xC2, 0xE1,
-	0x2C, 0xC0, 0x44, 0xC2,
-
-	0x05, 0x24, 0x34, 0xBF,
-	0x0D, 0x24, 0x2C, 0xBF,
-
-	0x2D, 0x46, 0x4E, 0xBF,
-	0x25, 0x46, 0x56, 0xBF,
-
-	0x20, 0x1D, 0x6F, 0x8F,
-	0x32, 0x3E, 0x5F, 0xE9,
-
-	0x3E, 0x50, 0x56, 0x9F,
-	0x00, 0xE0,
-	0x3B, 0x30,
-
-	0x1E, 0x8F, 0x51, 0x9F,
-	0x33, 0x1E, 0x5F, 0xE9,
-
-	0x05, 0x44, 0x54, 0xB2,
-	0x0D, 0x44, 0x4C, 0xB2,
-
-	0x19, 0xC0, 0xB0, 0xE8,
-	0x34, 0xC0, 0x44, 0xC4,
-
-	0x33, 0x73,
-	0x00, 0xE0,
-	0x3E, 0x62, 0x57, 0x9F,
-
-	0x1E, 0xAF, 0x59, 0x9F,
-	0x00, 0xE0,
-	0x0D, 0x20,
-
-	0x84, 0x3E, 0x58, 0xE9,
-	0x28, 0x1D, 0x6F, 0x8F,
-
-	0x05, 0x20,
-	0x00, 0xE0,
-	0x85, 0x1E, 0x58, 0xE9,
-
-	0x9B, 0x3B, 0x33, 0xDF,
-	0x20, 0x20, 0x42, 0xAF,
-
-	0x30, 0x42, 0x56, 0x9F,
-	0x80, 0x3E, 0x57, 0xE9,
-
-	0x3F, 0x8F, 0x51, 0x9F,
-	0x30, 0x80, 0x5F, 0xE9,
-
-	0x28, 0x28, 0x24, 0xAF,
-	0x81, 0x1E, 0x57, 0xE9,
-
-	0x05, 0x47, 0x57, 0xBF,
-	0x0D, 0x47, 0x4F, 0xBF,
-
-	0x88, 0x80, 0x58, 0xE9,
-	0x1B, 0x29, 0x1B, 0xDF,
-
-	0x30, 0x1D, 0x6F, 0x8F,
-	0x3A, 0x30, 0x4F, 0xE9,
-
-	0x1C, 0x30, 0x26, 0xDF,
-	0x09, 0xE3,
-	0x3B, 0x05,
-
-	0x3E, 0x50, 0x56, 0x9F,
-	0x3B, 0x3F, 0x4F, 0xE9,
-
-	0x1E, 0x8F, 0x51, 0x9F,
-	0x00, 0xE0,
-	0xAC, 0x20,
-
-	0x2D, 0x44, 0x4C, 0xB4,
-	0x2C, 0x1C, 0xC0, 0xAF,
-
-	0x25, 0x44, 0x54, 0xB4,
-	0x00, 0xE0,
-	0xC8, 0x30,
-
-	0x30, 0x46, 0x30, 0xAF,
-	0x1B, 0x1B, 0x48, 0xAF,
-
-	0x00, 0xE0,
-	0x25, 0x20,
-	0x38, 0x2C, 0x4F, 0xE9,
-
-	0x86, 0x80, 0x57, 0xE9,
-	0x38, 0x1D, 0x6F, 0x8F,
-
-	0x28, 0x74,
-	0x00, 0xE0,
-	0x0D, 0x44, 0x4C, 0xB0,
-
-	0x05, 0x44, 0x54, 0xB0,
-	0x2D, 0x20,
-	0x9B, 0x10,
-
-	0x82, 0x3E, 0x57, 0xE9,
-	0x32, 0xF0, 0x1B, 0xCD,
-
-	0x1E, 0xBD, 0x59, 0x9F,
-	0x83, 0x1E, 0x57, 0xE9,
-
-	0x38, 0x47, 0x38, 0xAF,
-	0x34, 0x20,
-	0x2A, 0x30,
-
-	0x00, 0xE0,
-	0x0D, 0x20,
-	0x32, 0x20,
-	0x05, 0x20,
-
-	0x87, 0x80, 0x57, 0xE9,
-	0x1F, 0x54, 0x57, 0x9F,
-
-	0x17, 0x42, 0x56, 0x9F,
-	0x00, 0xE0,
-	0x3B, 0x6A,
-
-	0x3F, 0x8F, 0x51, 0x9F,
-	0x37, 0x1E, 0x4F, 0xE9,
-
-	0x37, 0x32, 0x2A, 0xAF,
-	0x00, 0xE0,
-	0x32, 0x00,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x27, 0xC0, 0x44, 0xC0,
-
-	0x36, 0x1F, 0x4F, 0xE9,
-	0x1F, 0x1F, 0x26, 0xDF,
-
-	0x37, 0x1B, 0x37, 0xBF,
-	0x17, 0x26, 0x17, 0xDF,
-
-	0x3E, 0x17, 0x4F, 0xE9,
-	0x3F, 0x3F, 0x4F, 0xE9,
-
-	0x34, 0x1F, 0x34, 0xAF,
-	0x2B, 0x05,
-	0xA7, 0x20,
-
-	0x33, 0x2B, 0x37, 0xDF,
-	0x27, 0x17, 0xC0, 0xAF,
-
-	0x34, 0x80, 0x4F, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x2D, 0x21, 0x1A, 0xB0,
-	0x25, 0x21, 0x31, 0xB0,
-
-	0x0D, 0x21, 0x1A, 0xB2,
-	0x05, 0x21, 0x31, 0xB2,
-
-	0x03, 0x80, 0x2A, 0xEA,
-	0x17, 0xC1, 0x2B, 0xBD,
-
-	0x2D, 0x20,
-	0x25, 0x20,
-	0x05, 0x20,
-	0x0D, 0x20,
-
-	0xB3, 0x68,
-	0x97, 0x25,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x33, 0xC0, 0x33, 0xAF,
-	0x2F, 0xC0, 0x21, 0xC0,
-
-	0x16, 0x42, 0x56, 0x9F,
-	0x3C, 0x27, 0x4F, 0xE9,
-
-	0x1E, 0x62, 0x57, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x25, 0x21, 0x31, 0xB4,
-	0x2D, 0x21, 0x1A, 0xB4,
-
-	0x3F, 0x2F, 0x5D, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x33, 0x05,
-	0x00, 0xE0,
-	0x28, 0x19, 0x60, 0xEC,
-
-	0x0D, 0x44, 0x4C, 0xB6,
-	0x05, 0x44, 0x54, 0xB6,
-
-	0x37, 0x0F, 0x5C, 0x9F,
-	0x00, 0xE0,
-	0x2F, 0x20,
-
-	0x23, 0x3B, 0x33, 0xAD,
-	0x1E, 0x26, 0x1E, 0xDF,
-
-	0xA7, 0x1E, 0x4F, 0xE9,
-	0x17, 0x26, 0x16, 0xDF,
-
-	0x2D, 0x20,
-	0x00, 0xE0,
-	0xA8, 0x3F, 0x4F, 0xE9,
-
-	0x2F, 0x2F, 0x1E, 0xAF,
-	0x25, 0x20,
-	0x00, 0xE0,
-
-	0xA4, 0x16, 0x4F, 0xE9,
-	0x0F, 0xC0, 0x21, 0xC2,
-
-	0xA6, 0x80, 0x4F, 0xE9,
-	0x1F, 0x62, 0x57, 0x9F,
-
-	0x0D, 0x20,
-	0x05, 0x20,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x3F, 0x2F, 0x5D, 0x9F,
-	0x00, 0xE0,
-	0x0F, 0x20,
-
-	0x17, 0x50, 0x56, 0x9F,
-	0xA5, 0x37, 0x4F, 0xE9,
-
-	0x06, 0xC0, 0x21, 0xC4,
-	0x0F, 0x17, 0x0F, 0xAF,
-
-	0x37, 0x0F, 0x5C, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x2F, 0xC0, 0x44, 0xC6,
-	0xA3, 0x80, 0x4F, 0xE9,
-
-	0x06, 0x20,
-	0x00, 0xE0,
-	0x1F, 0x26, 0x1F, 0xDF,
-
-	0x17, 0x26, 0x17, 0xDF,
-	0x9D, 0x17, 0x4F, 0xE9,
-
-	0xA1, 0x1F, 0x4F, 0xE9,
-	0xA2, 0x3F, 0x4F, 0xE9,
-
-	0x06, 0x06, 0x1F, 0xAF,
-	0x00, 0xE0,
-	0xAF, 0x20,
-
-	0x9E, 0x37, 0x4F, 0xE9,
-	0x2F, 0x17, 0x2F, 0xAF,
-
-	0xA0, 0x80, 0x4F, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x9C, 0x80, 0x4F, 0xE9,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x57, 0x39, 0x20, 0xE9,
-
-	0x16, 0x28, 0x20, 0xE9,
-	0x1D, 0x3B, 0x20, 0xE9,
-
-	0x1E, 0x2B, 0x20, 0xE9,
-	0x2B, 0x32, 0x20, 0xE9,
-
-	0x1C, 0x23, 0x20, 0xE9,
-	0x57, 0x36, 0x20, 0xE9,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x40, 0x40, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x90, 0xE2,
-	0x00, 0xE0,
-
-	0x68, 0xFF, 0x20, 0xEA,
-	0x19, 0xC8, 0xC1, 0xCD,
-
-	0x1F, 0xD7, 0x18, 0xBD,
-	0x3F, 0xD7, 0x22, 0xBD,
-
-	0x9F, 0x41, 0x49, 0xBD,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x25, 0x41, 0x49, 0xBD,
-	0x2D, 0x41, 0x51, 0xBD,
-
-	0x0D, 0x80, 0x07, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x35, 0x40, 0x48, 0xBD,
-	0x3D, 0x40, 0x50, 0xBD,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x25, 0x30,
-	0x2D, 0x30,
-
-	0x35, 0x30,
-	0xB5, 0x30,
-	0xBD, 0x30,
-	0x3D, 0x30,
-
-	0x9C, 0xA7, 0x5B, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x67, 0xFF, 0x0A, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xC9, 0x41, 0xC8, 0xEC,
-	0x42, 0xE1,
-	0x00, 0xE0,
-
-	0x65, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xC8, 0x40, 0xC0, 0xEC,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x62, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-};
-
-static unsigned char warp_g200_tgzsaf[] = {
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x98, 0xA0, 0xE9,
-	0x40, 0x40, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x1F, 0xD7, 0x18, 0xBD,
-	0x3F, 0xD7, 0x22, 0xBD,
-
-	0x81, 0x04,
-	0x89, 0x04,
-	0x01, 0x04,
-	0x09, 0x04,
-
-	0xC9, 0x41, 0xC0, 0xEC,
-	0x11, 0x04,
-	0x00, 0xE0,
-
-	0x41, 0xCC, 0x41, 0xCD,
-	0x49, 0xCC, 0x49, 0xCD,
-
-	0xD1, 0x41, 0xC0, 0xEC,
-	0x51, 0xCC, 0x51, 0xCD,
-
-	0x80, 0x04,
-	0x10, 0x04,
-	0x08, 0x04,
-	0x00, 0xE0,
-
-	0x00, 0xCC, 0xC0, 0xCD,
-	0xD1, 0x49, 0xC0, 0xEC,
-
-	0x8A, 0x1F, 0x20, 0xE9,
-	0x8B, 0x3F, 0x20, 0xE9,
-
-	0x41, 0x3C, 0x41, 0xAD,
-	0x49, 0x3C, 0x49, 0xAD,
-
-	0x10, 0xCC, 0x10, 0xCD,
-	0x08, 0xCC, 0x08, 0xCD,
-
-	0xB9, 0x41, 0x49, 0xBB,
-	0x1F, 0xF0, 0x41, 0xCD,
-
-	0x51, 0x3C, 0x51, 0xAD,
-	0x00, 0x98, 0x80, 0xE9,
-
-	0x94, 0x80, 0x07, 0xEA,
-	0x24, 0x1F, 0x20, 0xE9,
-
-	0x21, 0x45, 0x80, 0xE8,
-	0x1A, 0x4D, 0x80, 0xE8,
-
-	0x31, 0x55, 0x80, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x15, 0x41, 0x49, 0xBD,
-	0x1D, 0x41, 0x51, 0xBD,
-
-	0x2E, 0x41, 0x2A, 0xB8,
-	0x34, 0x53, 0xA0, 0xE8,
-
-	0x15, 0x30,
-	0x1D, 0x30,
-	0x58, 0xE3,
-	0x00, 0xE0,
-
-	0xB5, 0x40, 0x48, 0xBD,
-	0x3D, 0x40, 0x50, 0xBD,
-
-	0x24, 0x43, 0xA0, 0xE8,
-	0x2C, 0x4B, 0xA0, 0xE8,
-
-	0x15, 0x72,
-	0x09, 0xE3,
-	0x00, 0xE0,
-	0x1D, 0x72,
-
-	0x35, 0x30,
-	0xB5, 0x30,
-	0xBD, 0x30,
-	0x3D, 0x30,
-
-	0x9C, 0x97, 0x57, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x6C, 0x64, 0xC8, 0xEC,
-	0x98, 0xE1,
-	0xB5, 0x05,
-
-	0xBD, 0x05,
-	0x2E, 0x30,
-	0x32, 0xC0, 0xA0, 0xE8,
-
-	0x33, 0xC0, 0xA0, 0xE8,
-	0x74, 0x64, 0xC8, 0xEC,
-
-	0x40, 0x3C, 0x40, 0xAD,
-	0x32, 0x6A,
-	0x2A, 0x30,
-
-	0x20, 0x73,
-	0x33, 0x6A,
-	0x00, 0xE0,
-	0x28, 0x73,
-
-	0x1C, 0x72,
-	0x83, 0xE2,
-	0x80, 0x80, 0x15, 0xEA,
-
-	0xB8, 0x3D, 0x28, 0xDF,
-	0x30, 0x35, 0x20, 0xDF,
-
-	0x40, 0x30,
-	0x00, 0xE0,
-	0xCC, 0xE2,
-	0x64, 0x72,
-
-	0x25, 0x42, 0x52, 0xBF,
-	0x2D, 0x42, 0x4A, 0xBF,
-
-	0x30, 0x2E, 0x30, 0xDF,
-	0x38, 0x2E, 0x38, 0xDF,
-
-	0x18, 0x1D, 0x45, 0xE9,
-	0x1E, 0x15, 0x45, 0xE9,
-
-	0x2B, 0x49, 0x51, 0xBD,
-	0x00, 0xE0,
-	0x1F, 0x73,
-
-	0x38, 0x38, 0x40, 0xAF,
-	0x30, 0x30, 0x40, 0xAF,
-
-	0x24, 0x1F, 0x24, 0xDF,
-	0x1D, 0x32, 0x20, 0xE9,
-
-	0x2C, 0x1F, 0x2C, 0xDF,
-	0x1A, 0x33, 0x20, 0xE9,
-
-	0xB0, 0x10,
-	0x08, 0xE3,
-	0x40, 0x10,
-	0xB8, 0x10,
-
-	0x26, 0xF0, 0x30, 0xCD,
-	0x2F, 0xF0, 0x38, 0xCD,
-
-	0x2B, 0x80, 0x20, 0xE9,
-	0x2A, 0x80, 0x20, 0xE9,
-
-	0xA6, 0x20,
-	0x88, 0xE2,
-	0x00, 0xE0,
-	0xAF, 0x20,
-
-	0x28, 0x2A, 0x26, 0xAF,
-	0x20, 0x2A, 0xC0, 0xAF,
-
-	0x34, 0x1F, 0x34, 0xDF,
-	0x46, 0x24, 0x46, 0xDF,
-
-	0x28, 0x30, 0x80, 0xBF,
-	0x20, 0x38, 0x80, 0xBF,
-
-	0x47, 0x24, 0x47, 0xDF,
-	0x4E, 0x2C, 0x4E, 0xDF,
-
-	0x4F, 0x2C, 0x4F, 0xDF,
-	0x56, 0x34, 0x56, 0xDF,
-
-	0x28, 0x15, 0x28, 0xDF,
-	0x20, 0x1D, 0x20, 0xDF,
-
-	0x57, 0x34, 0x57, 0xDF,
-	0x00, 0xE0,
-	0x1D, 0x05,
-
-	0x04, 0x80, 0x10, 0xEA,
-	0x89, 0xE2,
-	0x2B, 0x30,
-
-	0x3F, 0xC1, 0x1D, 0xBD,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xA0, 0x68,
-	0xBF, 0x25,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x20, 0xC0, 0x20, 0xAF,
-	0x28, 0x05,
-	0x97, 0x74,
-
-	0x00, 0xE0,
-	0x2A, 0x10,
-	0x16, 0xC0, 0x20, 0xE9,
-
-	0x04, 0x80, 0x10, 0xEA,
-	0x8C, 0xE2,
-	0x95, 0x05,
-
-	0x28, 0xC1, 0x28, 0xAD,
-	0x1F, 0xC1, 0x15, 0xBD,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xA8, 0x67,
-	0x9F, 0x6B,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x28, 0xC0, 0x28, 0xAD,
-	0x1D, 0x25,
-	0x20, 0x05,
-
-	0x28, 0x32, 0x80, 0xAD,
-	0x40, 0x2A, 0x40, 0xBD,
-
-	0x1C, 0x80, 0x20, 0xE9,
-	0x20, 0x33, 0x20, 0xAD,
-
-	0x20, 0x73,
-	0x00, 0xE0,
-	0xB6, 0x49, 0x51, 0xBB,
-
-	0x26, 0x2F, 0xB0, 0xE8,
-	0x19, 0x20, 0x20, 0xE9,
-
-	0x35, 0x20, 0x35, 0xDF,
-	0x3D, 0x20, 0x3D, 0xDF,
-
-	0x15, 0x20, 0x15, 0xDF,
-	0x1D, 0x20, 0x1D, 0xDF,
-
-	0x26, 0xD0, 0x26, 0xCD,
-	0x29, 0x49, 0x2A, 0xB8,
-
-	0x26, 0x40, 0x80, 0xBD,
-	0x3B, 0x48, 0x50, 0xBD,
-
-	0x3E, 0x54, 0x57, 0x9F,
-	0x00, 0xE0,
-	0x82, 0xE1,
-
-	0x1E, 0xAF, 0x59, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x26, 0x30,
-	0x29, 0x30,
-	0x48, 0x3C, 0x48, 0xAD,
-
-	0x2B, 0x72,
-	0xC2, 0xE1,
-	0x2C, 0xC0, 0x44, 0xC2,
-
-	0x05, 0x24, 0x34, 0xBF,
-	0x0D, 0x24, 0x2C, 0xBF,
-
-	0x2D, 0x46, 0x4E, 0xBF,
-	0x25, 0x46, 0x56, 0xBF,
-
-	0x20, 0x1D, 0x6F, 0x8F,
-	0x32, 0x3E, 0x5F, 0xE9,
-
-	0x3E, 0x50, 0x56, 0x9F,
-	0x00, 0xE0,
-	0x3B, 0x30,
-
-	0x1E, 0x8F, 0x51, 0x9F,
-	0x33, 0x1E, 0x5F, 0xE9,
-
-	0x05, 0x44, 0x54, 0xB2,
-	0x0D, 0x44, 0x4C, 0xB2,
-
-	0x19, 0xC0, 0xB0, 0xE8,
-	0x34, 0xC0, 0x44, 0xC4,
-
-	0x33, 0x73,
-	0x00, 0xE0,
-	0x3E, 0x62, 0x57, 0x9F,
-
-	0x1E, 0xAF, 0x59, 0x9F,
-	0x00, 0xE0,
-	0x0D, 0x20,
-
-	0x84, 0x3E, 0x58, 0xE9,
-	0x28, 0x1D, 0x6F, 0x8F,
-
-	0x05, 0x20,
-	0x00, 0xE0,
-	0x85, 0x1E, 0x58, 0xE9,
-
-	0x9B, 0x3B, 0x33, 0xDF,
-	0x20, 0x20, 0x42, 0xAF,
-
-	0x30, 0x42, 0x56, 0x9F,
-	0x80, 0x3E, 0x57, 0xE9,
-
-	0x3F, 0x8F, 0x51, 0x9F,
-	0x30, 0x80, 0x5F, 0xE9,
-
-	0x28, 0x28, 0x24, 0xAF,
-	0x81, 0x1E, 0x57, 0xE9,
-
-	0x05, 0x47, 0x57, 0xBF,
-	0x0D, 0x47, 0x4F, 0xBF,
-
-	0x88, 0x80, 0x58, 0xE9,
-	0x1B, 0x29, 0x1B, 0xDF,
-
-	0x30, 0x1D, 0x6F, 0x8F,
-	0x3A, 0x30, 0x4F, 0xE9,
-
-	0x1C, 0x30, 0x26, 0xDF,
-	0x09, 0xE3,
-	0x3B, 0x05,
-
-	0x3E, 0x50, 0x56, 0x9F,
-	0x3B, 0x3F, 0x4F, 0xE9,
-
-	0x1E, 0x8F, 0x51, 0x9F,
-	0x00, 0xE0,
-	0xAC, 0x20,
-
-	0x2D, 0x44, 0x4C, 0xB4,
-	0x2C, 0x1C, 0xC0, 0xAF,
-
-	0x25, 0x44, 0x54, 0xB4,
-	0x00, 0xE0,
-	0xC8, 0x30,
-
-	0x30, 0x46, 0x30, 0xAF,
-	0x1B, 0x1B, 0x48, 0xAF,
-
-	0x00, 0xE0,
-	0x25, 0x20,
-	0x38, 0x2C, 0x4F, 0xE9,
-
-	0x86, 0x80, 0x57, 0xE9,
-	0x38, 0x1D, 0x6F, 0x8F,
-
-	0x28, 0x74,
-	0x00, 0xE0,
-	0x0D, 0x44, 0x4C, 0xB0,
-
-	0x05, 0x44, 0x54, 0xB0,
-	0x2D, 0x20,
-	0x9B, 0x10,
-
-	0x82, 0x3E, 0x57, 0xE9,
-	0x32, 0xF0, 0x1B, 0xCD,
-
-	0x1E, 0xBD, 0x59, 0x9F,
-	0x83, 0x1E, 0x57, 0xE9,
-
-	0x38, 0x47, 0x38, 0xAF,
-	0x34, 0x20,
-	0x2A, 0x30,
-
-	0x00, 0xE0,
-	0x0D, 0x20,
-	0x32, 0x20,
-	0x05, 0x20,
-
-	0x87, 0x80, 0x57, 0xE9,
-	0x1F, 0x54, 0x57, 0x9F,
-
-	0x17, 0x42, 0x56, 0x9F,
-	0x00, 0xE0,
-	0x3B, 0x6A,
-
-	0x3F, 0x8F, 0x51, 0x9F,
-	0x37, 0x1E, 0x4F, 0xE9,
-
-	0x37, 0x32, 0x2A, 0xAF,
-	0x00, 0xE0,
-	0x32, 0x00,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x27, 0xC0, 0x44, 0xC0,
-
-	0x36, 0x1F, 0x4F, 0xE9,
-	0x1F, 0x1F, 0x26, 0xDF,
-
-	0x37, 0x1B, 0x37, 0xBF,
-	0x17, 0x26, 0x17, 0xDF,
-
-	0x3E, 0x17, 0x4F, 0xE9,
-	0x3F, 0x3F, 0x4F, 0xE9,
-
-	0x34, 0x1F, 0x34, 0xAF,
-	0x2B, 0x05,
-	0xA7, 0x20,
-
-	0x33, 0x2B, 0x37, 0xDF,
-	0x27, 0x17, 0xC0, 0xAF,
-
-	0x34, 0x80, 0x4F, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x2D, 0x21, 0x1A, 0xB0,
-	0x25, 0x21, 0x31, 0xB0,
-
-	0x0D, 0x21, 0x1A, 0xB2,
-	0x05, 0x21, 0x31, 0xB2,
-
-	0x03, 0x80, 0x2A, 0xEA,
-	0x17, 0xC1, 0x2B, 0xBD,
-
-	0x2D, 0x20,
-	0x25, 0x20,
-	0x05, 0x20,
-	0x0D, 0x20,
-
-	0xB3, 0x68,
-	0x97, 0x25,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x33, 0xC0, 0x33, 0xAF,
-	0x2F, 0xC0, 0x21, 0xC0,
-
-	0x16, 0x42, 0x56, 0x9F,
-	0x3C, 0x27, 0x4F, 0xE9,
-
-	0x1E, 0x62, 0x57, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x25, 0x21, 0x31, 0xB4,
-	0x2D, 0x21, 0x1A, 0xB4,
-
-	0x3F, 0x2F, 0x5D, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x33, 0x05,
-	0x00, 0xE0,
-	0x28, 0x19, 0x60, 0xEC,
-
-	0x0D, 0x21, 0x1A, 0xB6,
-	0x05, 0x21, 0x31, 0xB6,
-
-	0x37, 0x0F, 0x5C, 0x9F,
-	0x00, 0xE0,
-	0x2F, 0x20,
-
-	0x23, 0x3B, 0x33, 0xAD,
-	0x1E, 0x26, 0x1E, 0xDF,
-
-	0xA7, 0x1E, 0x4F, 0xE9,
-	0x17, 0x26, 0x16, 0xDF,
-
-	0x2D, 0x20,
-	0x00, 0xE0,
-	0xA8, 0x3F, 0x4F, 0xE9,
-
-	0x2F, 0x2F, 0x1E, 0xAF,
-	0x25, 0x20,
-	0x00, 0xE0,
-
-	0xA4, 0x16, 0x4F, 0xE9,
-	0x0F, 0xC0, 0x21, 0xC2,
-
-	0xA6, 0x80, 0x4F, 0xE9,
-	0x1F, 0x62, 0x57, 0x9F,
-
-	0x0D, 0x20,
-	0x05, 0x20,
-	0x2F, 0xC0, 0x21, 0xC6,
-
-	0x2D, 0x44, 0x4C, 0xB6,
-	0x25, 0x44, 0x54, 0xB6,
-
-	0x3F, 0x2F, 0x5D, 0x9F,
-	0x00, 0xE0,
-	0x0F, 0x20,
-
-	0x2D, 0x20,
-	0x25, 0x20,
-	0x07, 0xC0, 0x44, 0xC6,
-
-	0x17, 0x50, 0x56, 0x9F,
-	0xA5, 0x37, 0x4F, 0xE9,
-
-	0x06, 0xC0, 0x21, 0xC4,
-	0x0F, 0x17, 0x0F, 0xAF,
-
-	0x37, 0x0F, 0x5C, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x1E, 0x62, 0x57, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x3E, 0x3D, 0x5D, 0x9F,
-	0x00, 0xE0,
-	0x07, 0x20,
-
-	0x2F, 0x20,
-	0x00, 0xE0,
-	0xA3, 0x0F, 0x4F, 0xE9,
-
-	0x06, 0x20,
-	0x00, 0xE0,
-	0x1F, 0x26, 0x1F, 0xDF,
-
-	0x17, 0x26, 0x17, 0xDF,
-	0xA1, 0x1F, 0x4F, 0xE9,
-
-	0x1E, 0x26, 0x1E, 0xDF,
-	0x9D, 0x1E, 0x4F, 0xE9,
-
-	0x35, 0x17, 0x4F, 0xE9,
-	0xA2, 0x3F, 0x4F, 0xE9,
-
-	0x06, 0x06, 0x1F, 0xAF,
-	0x39, 0x37, 0x4F, 0xE9,
-
-	0x2F, 0x2F, 0x17, 0xAF,
-	0x07, 0x07, 0x1E, 0xAF,
-
-	0xA0, 0x80, 0x4F, 0xE9,
-	0x9E, 0x3E, 0x4F, 0xE9,
-
-	0x31, 0x80, 0x4F, 0xE9,
-	0x9C, 0x80, 0x4F, 0xE9,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x57, 0x39, 0x20, 0xE9,
-
-	0x16, 0x28, 0x20, 0xE9,
-	0x1D, 0x3B, 0x20, 0xE9,
-
-	0x1E, 0x2B, 0x20, 0xE9,
-	0x2B, 0x32, 0x20, 0xE9,
-
-	0x1C, 0x23, 0x20, 0xE9,
-	0x57, 0x36, 0x20, 0xE9,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x40, 0x40, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x90, 0xE2,
-	0x00, 0xE0,
-
-	0x63, 0xFF, 0x20, 0xEA,
-	0x19, 0xC8, 0xC1, 0xCD,
-
-	0x1F, 0xD7, 0x18, 0xBD,
-	0x3F, 0xD7, 0x22, 0xBD,
-
-	0x9F, 0x41, 0x49, 0xBD,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x25, 0x41, 0x49, 0xBD,
-	0x2D, 0x41, 0x51, 0xBD,
-
-	0x0D, 0x80, 0x07, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x35, 0x40, 0x48, 0xBD,
-	0x3D, 0x40, 0x50, 0xBD,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x25, 0x30,
-	0x2D, 0x30,
-
-	0x35, 0x30,
-	0xB5, 0x30,
-	0xBD, 0x30,
-	0x3D, 0x30,
-
-	0x9C, 0xA7, 0x5B, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x62, 0xFF, 0x0A, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xC9, 0x41, 0xC8, 0xEC,
-	0x42, 0xE1,
-	0x00, 0xE0,
-
-	0x60, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xC8, 0x40, 0xC0, 0xEC,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x5D, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-};
-
-static unsigned char warp_g200_tgzsf[] = {
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x98, 0xA0, 0xE9,
-	0x40, 0x40, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x1F, 0xD7, 0x18, 0xBD,
-	0x3F, 0xD7, 0x22, 0xBD,
-
-	0x81, 0x04,
-	0x89, 0x04,
-	0x01, 0x04,
-	0x09, 0x04,
-
-	0xC9, 0x41, 0xC0, 0xEC,
-	0x11, 0x04,
-	0x00, 0xE0,
-
-	0x41, 0xCC, 0x41, 0xCD,
-	0x49, 0xCC, 0x49, 0xCD,
-
-	0xD1, 0x41, 0xC0, 0xEC,
-	0x51, 0xCC, 0x51, 0xCD,
-
-	0x80, 0x04,
-	0x10, 0x04,
-	0x08, 0x04,
-	0x00, 0xE0,
-
-	0x00, 0xCC, 0xC0, 0xCD,
-	0xD1, 0x49, 0xC0, 0xEC,
-
-	0x8A, 0x1F, 0x20, 0xE9,
-	0x8B, 0x3F, 0x20, 0xE9,
-
-	0x41, 0x3C, 0x41, 0xAD,
-	0x49, 0x3C, 0x49, 0xAD,
-
-	0x10, 0xCC, 0x10, 0xCD,
-	0x08, 0xCC, 0x08, 0xCD,
-
-	0xB9, 0x41, 0x49, 0xBB,
-	0x1F, 0xF0, 0x41, 0xCD,
-
-	0x51, 0x3C, 0x51, 0xAD,
-	0x00, 0x98, 0x80, 0xE9,
-
-	0x8F, 0x80, 0x07, 0xEA,
-	0x24, 0x1F, 0x20, 0xE9,
-
-	0x21, 0x45, 0x80, 0xE8,
-	0x1A, 0x4D, 0x80, 0xE8,
-
-	0x31, 0x55, 0x80, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x15, 0x41, 0x49, 0xBD,
-	0x1D, 0x41, 0x51, 0xBD,
-
-	0x2E, 0x41, 0x2A, 0xB8,
-	0x34, 0x53, 0xA0, 0xE8,
-
-	0x15, 0x30,
-	0x1D, 0x30,
-	0x58, 0xE3,
-	0x00, 0xE0,
-
-	0xB5, 0x40, 0x48, 0xBD,
-	0x3D, 0x40, 0x50, 0xBD,
-
-	0x24, 0x43, 0xA0, 0xE8,
-	0x2C, 0x4B, 0xA0, 0xE8,
-
-	0x15, 0x72,
-	0x09, 0xE3,
-	0x00, 0xE0,
-	0x1D, 0x72,
-
-	0x35, 0x30,
-	0xB5, 0x30,
-	0xBD, 0x30,
-	0x3D, 0x30,
-
-	0x9C, 0x97, 0x57, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x6C, 0x64, 0xC8, 0xEC,
-	0x98, 0xE1,
-	0xB5, 0x05,
-
-	0xBD, 0x05,
-	0x2E, 0x30,
-	0x32, 0xC0, 0xA0, 0xE8,
-
-	0x33, 0xC0, 0xA0, 0xE8,
-	0x74, 0x64, 0xC8, 0xEC,
-
-	0x40, 0x3C, 0x40, 0xAD,
-	0x32, 0x6A,
-	0x2A, 0x30,
-
-	0x20, 0x73,
-	0x33, 0x6A,
-	0x00, 0xE0,
-	0x28, 0x73,
-
-	0x1C, 0x72,
-	0x83, 0xE2,
-	0x7B, 0x80, 0x15, 0xEA,
-
-	0xB8, 0x3D, 0x28, 0xDF,
-	0x30, 0x35, 0x20, 0xDF,
-
-	0x40, 0x30,
-	0x00, 0xE0,
-	0xCC, 0xE2,
-	0x64, 0x72,
-
-	0x25, 0x42, 0x52, 0xBF,
-	0x2D, 0x42, 0x4A, 0xBF,
-
-	0x30, 0x2E, 0x30, 0xDF,
-	0x38, 0x2E, 0x38, 0xDF,
-
-	0x18, 0x1D, 0x45, 0xE9,
-	0x1E, 0x15, 0x45, 0xE9,
-
-	0x2B, 0x49, 0x51, 0xBD,
-	0x00, 0xE0,
-	0x1F, 0x73,
-
-	0x38, 0x38, 0x40, 0xAF,
-	0x30, 0x30, 0x40, 0xAF,
-
-	0x24, 0x1F, 0x24, 0xDF,
-	0x1D, 0x32, 0x20, 0xE9,
-
-	0x2C, 0x1F, 0x2C, 0xDF,
-	0x1A, 0x33, 0x20, 0xE9,
-
-	0xB0, 0x10,
-	0x08, 0xE3,
-	0x40, 0x10,
-	0xB8, 0x10,
-
-	0x26, 0xF0, 0x30, 0xCD,
-	0x2F, 0xF0, 0x38, 0xCD,
-
-	0x2B, 0x80, 0x20, 0xE9,
-	0x2A, 0x80, 0x20, 0xE9,
-
-	0xA6, 0x20,
-	0x88, 0xE2,
-	0x00, 0xE0,
-	0xAF, 0x20,
-
-	0x28, 0x2A, 0x26, 0xAF,
-	0x20, 0x2A, 0xC0, 0xAF,
-
-	0x34, 0x1F, 0x34, 0xDF,
-	0x46, 0x24, 0x46, 0xDF,
-
-	0x28, 0x30, 0x80, 0xBF,
-	0x20, 0x38, 0x80, 0xBF,
-
-	0x47, 0x24, 0x47, 0xDF,
-	0x4E, 0x2C, 0x4E, 0xDF,
-
-	0x4F, 0x2C, 0x4F, 0xDF,
-	0x56, 0x34, 0x56, 0xDF,
-
-	0x28, 0x15, 0x28, 0xDF,
-	0x20, 0x1D, 0x20, 0xDF,
-
-	0x57, 0x34, 0x57, 0xDF,
-	0x00, 0xE0,
-	0x1D, 0x05,
-
-	0x04, 0x80, 0x10, 0xEA,
-	0x89, 0xE2,
-	0x2B, 0x30,
-
-	0x3F, 0xC1, 0x1D, 0xBD,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xA0, 0x68,
-	0xBF, 0x25,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x20, 0xC0, 0x20, 0xAF,
-	0x28, 0x05,
-	0x97, 0x74,
-
-	0x00, 0xE0,
-	0x2A, 0x10,
-	0x16, 0xC0, 0x20, 0xE9,
-
-	0x04, 0x80, 0x10, 0xEA,
-	0x8C, 0xE2,
-	0x95, 0x05,
-
-	0x28, 0xC1, 0x28, 0xAD,
-	0x1F, 0xC1, 0x15, 0xBD,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xA8, 0x67,
-	0x9F, 0x6B,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x28, 0xC0, 0x28, 0xAD,
-	0x1D, 0x25,
-	0x20, 0x05,
-
-	0x28, 0x32, 0x80, 0xAD,
-	0x40, 0x2A, 0x40, 0xBD,
-
-	0x1C, 0x80, 0x20, 0xE9,
-	0x20, 0x33, 0x20, 0xAD,
-
-	0x20, 0x73,
-	0x00, 0xE0,
-	0xB6, 0x49, 0x51, 0xBB,
-
-	0x26, 0x2F, 0xB0, 0xE8,
-	0x19, 0x20, 0x20, 0xE9,
-
-	0x35, 0x20, 0x35, 0xDF,
-	0x3D, 0x20, 0x3D, 0xDF,
-
-	0x15, 0x20, 0x15, 0xDF,
-	0x1D, 0x20, 0x1D, 0xDF,
-
-	0x26, 0xD0, 0x26, 0xCD,
-	0x29, 0x49, 0x2A, 0xB8,
-
-	0x26, 0x40, 0x80, 0xBD,
-	0x3B, 0x48, 0x50, 0xBD,
-
-	0x3E, 0x54, 0x57, 0x9F,
-	0x00, 0xE0,
-	0x82, 0xE1,
-
-	0x1E, 0xAF, 0x59, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x26, 0x30,
-	0x29, 0x30,
-	0x48, 0x3C, 0x48, 0xAD,
-
-	0x2B, 0x72,
-	0xC2, 0xE1,
-	0x2C, 0xC0, 0x44, 0xC2,
-
-	0x05, 0x24, 0x34, 0xBF,
-	0x0D, 0x24, 0x2C, 0xBF,
-
-	0x2D, 0x46, 0x4E, 0xBF,
-	0x25, 0x46, 0x56, 0xBF,
-
-	0x20, 0x1D, 0x6F, 0x8F,
-	0x32, 0x3E, 0x5F, 0xE9,
-
-	0x3E, 0x50, 0x56, 0x9F,
-	0x00, 0xE0,
-	0x3B, 0x30,
-
-	0x1E, 0x8F, 0x51, 0x9F,
-	0x33, 0x1E, 0x5F, 0xE9,
-
-	0x05, 0x44, 0x54, 0xB2,
-	0x0D, 0x44, 0x4C, 0xB2,
-
-	0x19, 0xC0, 0xB0, 0xE8,
-	0x34, 0xC0, 0x44, 0xC4,
-
-	0x33, 0x73,
-	0x00, 0xE0,
-	0x3E, 0x62, 0x57, 0x9F,
-
-	0x1E, 0xAF, 0x59, 0x9F,
-	0x00, 0xE0,
-	0x0D, 0x20,
-
-	0x84, 0x3E, 0x58, 0xE9,
-	0x28, 0x1D, 0x6F, 0x8F,
-
-	0x05, 0x20,
-	0x00, 0xE0,
-	0x85, 0x1E, 0x58, 0xE9,
-
-	0x9B, 0x3B, 0x33, 0xDF,
-	0x20, 0x20, 0x42, 0xAF,
-
-	0x30, 0x42, 0x56, 0x9F,
-	0x80, 0x3E, 0x57, 0xE9,
-
-	0x3F, 0x8F, 0x51, 0x9F,
-	0x30, 0x80, 0x5F, 0xE9,
-
-	0x28, 0x28, 0x24, 0xAF,
-	0x81, 0x1E, 0x57, 0xE9,
-
-	0x05, 0x47, 0x57, 0xBF,
-	0x0D, 0x47, 0x4F, 0xBF,
-
-	0x88, 0x80, 0x58, 0xE9,
-	0x1B, 0x29, 0x1B, 0xDF,
-
-	0x30, 0x1D, 0x6F, 0x8F,
-	0x3A, 0x30, 0x4F, 0xE9,
-
-	0x1C, 0x30, 0x26, 0xDF,
-	0x09, 0xE3,
-	0x3B, 0x05,
-
-	0x3E, 0x50, 0x56, 0x9F,
-	0x3B, 0x3F, 0x4F, 0xE9,
-
-	0x1E, 0x8F, 0x51, 0x9F,
-	0x00, 0xE0,
-	0xAC, 0x20,
-
-	0x2D, 0x44, 0x4C, 0xB4,
-	0x2C, 0x1C, 0xC0, 0xAF,
-
-	0x25, 0x44, 0x54, 0xB4,
-	0x00, 0xE0,
-	0xC8, 0x30,
-
-	0x30, 0x46, 0x30, 0xAF,
-	0x1B, 0x1B, 0x48, 0xAF,
-
-	0x00, 0xE0,
-	0x25, 0x20,
-	0x38, 0x2C, 0x4F, 0xE9,
-
-	0x86, 0x80, 0x57, 0xE9,
-	0x38, 0x1D, 0x6F, 0x8F,
-
-	0x28, 0x74,
-	0x00, 0xE0,
-	0x0D, 0x44, 0x4C, 0xB0,
-
-	0x05, 0x44, 0x54, 0xB0,
-	0x2D, 0x20,
-	0x9B, 0x10,
-
-	0x82, 0x3E, 0x57, 0xE9,
-	0x32, 0xF0, 0x1B, 0xCD,
-
-	0x1E, 0xBD, 0x59, 0x9F,
-	0x83, 0x1E, 0x57, 0xE9,
-
-	0x38, 0x47, 0x38, 0xAF,
-	0x34, 0x20,
-	0x2A, 0x30,
-
-	0x00, 0xE0,
-	0x0D, 0x20,
-	0x32, 0x20,
-	0x05, 0x20,
-
-	0x87, 0x80, 0x57, 0xE9,
-	0x1F, 0x54, 0x57, 0x9F,
-
-	0x17, 0x42, 0x56, 0x9F,
-	0x00, 0xE0,
-	0x3B, 0x6A,
-
-	0x3F, 0x8F, 0x51, 0x9F,
-	0x37, 0x1E, 0x4F, 0xE9,
-
-	0x37, 0x32, 0x2A, 0xAF,
-	0x00, 0xE0,
-	0x32, 0x00,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x27, 0xC0, 0x44, 0xC0,
-
-	0x36, 0x1F, 0x4F, 0xE9,
-	0x1F, 0x1F, 0x26, 0xDF,
-
-	0x37, 0x1B, 0x37, 0xBF,
-	0x17, 0x26, 0x17, 0xDF,
-
-	0x3E, 0x17, 0x4F, 0xE9,
-	0x3F, 0x3F, 0x4F, 0xE9,
-
-	0x34, 0x1F, 0x34, 0xAF,
-	0x2B, 0x05,
-	0xA7, 0x20,
-
-	0x33, 0x2B, 0x37, 0xDF,
-	0x27, 0x17, 0xC0, 0xAF,
-
-	0x34, 0x80, 0x4F, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x2D, 0x21, 0x1A, 0xB0,
-	0x25, 0x21, 0x31, 0xB0,
-
-	0x0D, 0x21, 0x1A, 0xB2,
-	0x05, 0x21, 0x31, 0xB2,
-
-	0x03, 0x80, 0x2A, 0xEA,
-	0x17, 0xC1, 0x2B, 0xBD,
-
-	0x2D, 0x20,
-	0x25, 0x20,
-	0x05, 0x20,
-	0x0D, 0x20,
-
-	0xB3, 0x68,
-	0x97, 0x25,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x33, 0xC0, 0x33, 0xAF,
-	0x2F, 0xC0, 0x21, 0xC0,
-
-	0x16, 0x42, 0x56, 0x9F,
-	0x3C, 0x27, 0x4F, 0xE9,
-
-	0x1E, 0x62, 0x57, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x25, 0x21, 0x31, 0xB4,
-	0x2D, 0x21, 0x1A, 0xB4,
-
-	0x3F, 0x2F, 0x5D, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x33, 0x05,
-	0x00, 0xE0,
-	0x28, 0x19, 0x60, 0xEC,
-
-	0x0D, 0x21, 0x1A, 0xB6,
-	0x05, 0x21, 0x31, 0xB6,
-
-	0x37, 0x0F, 0x5C, 0x9F,
-	0x00, 0xE0,
-	0x2F, 0x20,
-
-	0x23, 0x3B, 0x33, 0xAD,
-	0x1E, 0x26, 0x1E, 0xDF,
-
-	0xA7, 0x1E, 0x4F, 0xE9,
-	0x17, 0x26, 0x16, 0xDF,
-
-	0x2D, 0x20,
-	0x00, 0xE0,
-	0xA8, 0x3F, 0x4F, 0xE9,
-
-	0x2F, 0x2F, 0x1E, 0xAF,
-	0x25, 0x20,
-	0x00, 0xE0,
-
-	0xA4, 0x16, 0x4F, 0xE9,
-	0x0F, 0xC0, 0x21, 0xC2,
-
-	0xA6, 0x80, 0x4F, 0xE9,
-	0x1F, 0x62, 0x57, 0x9F,
-
-	0x0D, 0x20,
-	0x05, 0x20,
-	0x2F, 0xC0, 0x21, 0xC6,
-
-	0x3F, 0x2F, 0x5D, 0x9F,
-	0x00, 0xE0,
-	0x0F, 0x20,
-
-	0x17, 0x50, 0x56, 0x9F,
-	0xA5, 0x37, 0x4F, 0xE9,
-
-	0x06, 0xC0, 0x21, 0xC4,
-	0x0F, 0x17, 0x0F, 0xAF,
-
-	0x37, 0x0F, 0x5C, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x2F, 0x20,
-	0x00, 0xE0,
-	0xA3, 0x80, 0x4F, 0xE9,
-
-	0x06, 0x20,
-	0x00, 0xE0,
-	0x1F, 0x26, 0x1F, 0xDF,
-
-	0x17, 0x26, 0x17, 0xDF,
-	0x35, 0x17, 0x4F, 0xE9,
-
-	0xA1, 0x1F, 0x4F, 0xE9,
-	0xA2, 0x3F, 0x4F, 0xE9,
-
-	0x06, 0x06, 0x1F, 0xAF,
-	0x39, 0x37, 0x4F, 0xE9,
-
-	0x2F, 0x2F, 0x17, 0xAF,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xA0, 0x80, 0x4F, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x31, 0x80, 0x4F, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x57, 0x39, 0x20, 0xE9,
-
-	0x16, 0x28, 0x20, 0xE9,
-	0x1D, 0x3B, 0x20, 0xE9,
-
-	0x1E, 0x2B, 0x20, 0xE9,
-	0x2B, 0x32, 0x20, 0xE9,
-
-	0x1C, 0x23, 0x20, 0xE9,
-	0x57, 0x36, 0x20, 0xE9,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x40, 0x40, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x90, 0xE2,
-	0x00, 0xE0,
-
-	0x68, 0xFF, 0x20, 0xEA,
-	0x19, 0xC8, 0xC1, 0xCD,
-
-	0x1F, 0xD7, 0x18, 0xBD,
-	0x3F, 0xD7, 0x22, 0xBD,
-
-	0x9F, 0x41, 0x49, 0xBD,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x25, 0x41, 0x49, 0xBD,
-	0x2D, 0x41, 0x51, 0xBD,
-
-	0x0D, 0x80, 0x07, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x35, 0x40, 0x48, 0xBD,
-	0x3D, 0x40, 0x50, 0xBD,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x25, 0x30,
-	0x2D, 0x30,
-
-	0x35, 0x30,
-	0xB5, 0x30,
-	0xBD, 0x30,
-	0x3D, 0x30,
-
-	0x9C, 0xA7, 0x5B, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x67, 0xFF, 0x0A, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xC9, 0x41, 0xC8, 0xEC,
-	0x42, 0xE1,
-	0x00, 0xE0,
-
-	0x65, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xC8, 0x40, 0xC0, 0xEC,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x62, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-};
-
-static unsigned char warp_g400_t2gz[] = {
-
-	0x00, 0x8A, 0x98, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x0A, 0x40, 0x50, 0xBF,
-	0x2A, 0x40, 0x60, 0xBF,
-
-	0x32, 0x41, 0x51, 0xBF,
-	0x3A, 0x41, 0x61, 0xBF,
-
-	0xC3, 0x6B,
-	0xD3, 0x6B,
-	0x00, 0x8A, 0x98, 0xE9,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x96, 0xE2,
-	0x41, 0x04,
-
-	0x7B, 0x43, 0xA0, 0xE8,
-	0x73, 0x53, 0xA0, 0xE8,
-
-	0xAD, 0xEE, 0x23, 0x9F,
-	0x00, 0xE0,
-	0x51, 0x04,
-
-	0x90, 0xE2,
-	0x61, 0x04,
-	0x31, 0x46, 0xB1, 0xE8,
-
-	0x51, 0x41, 0xE0, 0xEC,
-	0x39, 0x67, 0xB1, 0xE8,
-
-	0x00, 0x04,
-	0x46, 0xE2,
-	0x73, 0x63, 0xA0, 0xE8,
-
-	0x61, 0x41, 0xE0, 0xEC,
-	0x31, 0x00,
-	0x39, 0x00,
-
-	0x78, 0x80, 0x15, 0xEA,
-	0x10, 0x04,
-	0x20, 0x04,
-
-	0x61, 0x51, 0xE0, 0xEC,
-	0x2F, 0x41, 0x60, 0xEA,
-
-	0x31, 0x20,
-	0x39, 0x20,
-	0x1F, 0x42, 0xA0, 0xE8,
-
-	0x2A, 0x42, 0x52, 0xBF,
-	0x0F, 0x52, 0xA0, 0xE8,
-
-	0x1A, 0x42, 0x62, 0xBF,
-	0x1E, 0x51, 0x60, 0xEA,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x0E, 0x61, 0x60, 0xEA,
-
-	0x32, 0x40, 0x50, 0xBD,
-	0x22, 0x40, 0x60, 0xBD,
-
-	0x12, 0x41, 0x51, 0xBD,
-	0x3A, 0x41, 0x61, 0xBD,
-
-	0xBF, 0x2F, 0x0E, 0xBD,
-	0x97, 0xE2,
-	0x7B, 0x72,
-
-	0x32, 0x20,
-	0x22, 0x20,
-	0x12, 0x20,
-	0x3A, 0x20,
-
-	0x35, 0x48, 0xB1, 0xE8,
-	0x3D, 0x59, 0xB1, 0xE8,
-
-	0x46, 0x31, 0x46, 0xBF,
-	0x56, 0x31, 0x56, 0xBF,
-
-	0xB3, 0xE2, 0x2D, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x66, 0x31, 0x66, 0xBF,
-	0x47, 0x39, 0x47, 0xBF,
-
-	0x57, 0x39, 0x57, 0xBF,
-	0x67, 0x39, 0x67, 0xBF,
-
-	0x69, 0x80, 0x07, 0xEA,
-	0x24, 0x41, 0x20, 0xE9,
-
-	0x35, 0x00,
-	0x3D, 0x00,
-	0x00, 0xE0,
-	0x2D, 0x73,
-
-	0x33, 0x72,
-	0x0C, 0xE3,
-	0x8D, 0x2F, 0x1E, 0xBD,
-
-	0x43, 0x75, 0xF8, 0xEC,
-	0x35, 0x20,
-	0x3D, 0x20,
-
-	0x43, 0x43, 0x2D, 0xDF,
-	0x53, 0x53, 0x2D, 0xDF,
-
-	0xAE, 0x1E, 0x0E, 0xBD,
-	0x58, 0xE3,
-	0x33, 0x66,
-
-	0x48, 0x35, 0x48, 0xBF,
-	0x58, 0x35, 0x58, 0xBF,
-
-	0x68, 0x35, 0x68, 0xBF,
-	0x49, 0x3D, 0x49, 0xBF,
-
-	0x59, 0x3D, 0x59, 0xBF,
-	0x69, 0x3D, 0x69, 0xBF,
-
-	0x63, 0x63, 0x2D, 0xDF,
-	0x4D, 0x7D, 0xF8, 0xEC,
-
-	0x59, 0xE3,
-	0x00, 0xE0,
-	0xB8, 0x38, 0x33, 0xBF,
-
-	0x2D, 0x73,
-	0x30, 0x76,
-	0x18, 0x3A, 0x41, 0xE9,
-
-	0x3F, 0x53, 0xA0, 0xE8,
-	0x05, 0x80, 0x3D, 0xEA,
-
-	0x37, 0x43, 0xA0, 0xE8,
-	0x3D, 0x63, 0xA0, 0xE8,
-
-	0x50, 0x70, 0xF8, 0xEC,
-	0x2B, 0x50, 0x3C, 0xE9,
-
-	0x1F, 0x0F, 0xBC, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x59, 0x78, 0xF8, 0xEC,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x1E, 0x12, 0x41, 0xE9,
-	0x1A, 0x22, 0x41, 0xE9,
-
-	0x46, 0x37, 0x46, 0xDF,
-	0x56, 0x3F, 0x56, 0xDF,
-
-	0x2B, 0x40, 0x3D, 0xE9,
-	0x66, 0x3D, 0x66, 0xDF,
-
-	0x1D, 0x32, 0x41, 0xE9,
-	0x67, 0x3D, 0x67, 0xDF,
-
-	0x47, 0x37, 0x47, 0xDF,
-	0x57, 0x3F, 0x57, 0xDF,
-
-	0x2A, 0x40, 0x20, 0xE9,
-	0x59, 0x3F, 0x59, 0xDF,
-
-	0x16, 0x30, 0x20, 0xE9,
-	0x69, 0x3D, 0x69, 0xDF,
-
-	0x48, 0x37, 0x48, 0xDF,
-	0x58, 0x3F, 0x58, 0xDF,
-
-	0x12, 0x12, 0x2D, 0xDF,
-	0x22, 0x22, 0x2D, 0xDF,
-
-	0x32, 0x32, 0x2D, 0xDF,
-	0x3A, 0x3A, 0x2D, 0xDF,
-
-	0x68, 0x3D, 0x68, 0xDF,
-	0x49, 0x37, 0x49, 0xDF,
-
-	0x3D, 0xCF, 0x74, 0xC0,
-	0x37, 0xCF, 0x74, 0xC4,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x34, 0x80, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3C, 0x3D, 0x20, 0xE9,
-
-	0x0A, 0x44, 0x54, 0xB0,
-	0x02, 0x44, 0x64, 0xB0,
-
-	0x2A, 0x44, 0x54, 0xB2,
-	0x1A, 0x44, 0x64, 0xB2,
-
-	0x25, 0x80, 0x3A, 0xEA,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x3D, 0xCF, 0x74, 0xC2,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x32, 0x31, 0x5F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x33, 0x39, 0x5F, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x2A, 0x44, 0x54, 0xB4,
-	0x1A, 0x44, 0x64, 0xB4,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x38, 0x3D, 0x20, 0xE9,
-
-	0x88, 0x73, 0x5E, 0xE9,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x2A, 0x46, 0x56, 0xBF,
-	0x1A, 0x46, 0x66, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x3E, 0x30, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3F, 0x38, 0x4F, 0xE9,
-
-	0x0A, 0x47, 0x57, 0xBF,
-	0x02, 0x47, 0x67, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x3A, 0x31, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3B, 0x39, 0x4F, 0xE9,
-
-	0x2A, 0x43, 0x53, 0xBF,
-	0x1A, 0x43, 0x63, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x36, 0x31, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x37, 0x39, 0x4F, 0xE9,
-
-	0x0A, 0x48, 0x58, 0xBF,
-	0x02, 0x48, 0x68, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x80, 0x31, 0x57, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x81, 0x39, 0x57, 0xE9,
-
-	0x2A, 0x49, 0x59, 0xBF,
-	0x1A, 0x49, 0x69, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x82, 0x30, 0x57, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x83, 0x38, 0x57, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x84, 0x31, 0x5E, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x85, 0x39, 0x5E, 0xE9,
-
-	0x86, 0x76, 0x57, 0xE9,
-	0x8A, 0x36, 0x20, 0xE9,
-
-	0x87, 0x77, 0x57, 0xE9,
-	0x8B, 0x3E, 0xBF, 0xEA,
-
-	0x80, 0x30, 0x57, 0xE9,
-	0x81, 0x38, 0x57, 0xE9,
-
-	0x82, 0x31, 0x57, 0xE9,
-	0x86, 0x78, 0x57, 0xE9,
-
-	0x83, 0x39, 0x57, 0xE9,
-	0x87, 0x79, 0x57, 0xE9,
-
-	0x30, 0x1F, 0x5F, 0xE9,
-	0x8A, 0x34, 0x20, 0xE9,
-
-	0x8B, 0x3C, 0x20, 0xE9,
-	0x37, 0x50, 0x60, 0xBD,
-
-	0x57, 0x0D, 0x20, 0xE9,
-	0x35, 0x51, 0x61, 0xBD,
-
-	0x2B, 0x50, 0x20, 0xE9,
-	0x1D, 0x37, 0xE1, 0xEA,
-
-	0x1E, 0x35, 0xE1, 0xEA,
-	0x00, 0xE0,
-	0x0E, 0x77,
-
-	0x24, 0x51, 0x20, 0xE9,
-	0x9F, 0xFF, 0x20, 0xEA,
-
-	0x16, 0x0E, 0x20, 0xE9,
-	0x57, 0x2E, 0xBF, 0xEA,
-
-	0x0B, 0x46, 0xA0, 0xE8,
-	0x1B, 0x56, 0xA0, 0xE8,
-
-	0x2B, 0x66, 0xA0, 0xE8,
-	0x0C, 0x47, 0xA0, 0xE8,
-
-	0x1C, 0x57, 0xA0, 0xE8,
-	0x2C, 0x67, 0xA0, 0xE8,
-
-	0x0B, 0x00,
-	0x1B, 0x00,
-	0x2B, 0x00,
-	0x00, 0xE0,
-
-	0x0C, 0x00,
-	0x1C, 0x00,
-	0x2C, 0x00,
-	0x00, 0xE0,
-
-	0x0B, 0x65,
-	0x1B, 0x65,
-	0x2B, 0x65,
-	0x00, 0xE0,
-
-	0x0C, 0x65,
-	0x1C, 0x65,
-	0x2C, 0x65,
-	0x00, 0xE0,
-
-	0x0B, 0x1B, 0x60, 0xEC,
-	0x36, 0xD7, 0x36, 0xAD,
-
-	0x2B, 0x80, 0x60, 0xEC,
-	0x0C, 0x1C, 0x60, 0xEC,
-
-	0x3E, 0xD7, 0x3E, 0xAD,
-	0x2C, 0x80, 0x60, 0xEC,
-
-	0x0B, 0x2B, 0xDE, 0xE8,
-	0x1B, 0x80, 0xDE, 0xE8,
-
-	0x36, 0x80, 0x36, 0xBD,
-	0x3E, 0x80, 0x3E, 0xBD,
-
-	0x33, 0xD7, 0x0B, 0xBD,
-	0x3B, 0xD7, 0x1B, 0xBD,
-
-	0x46, 0x80, 0x46, 0xCF,
-	0x57, 0x80, 0x57, 0xCF,
-
-	0x66, 0x33, 0x66, 0xCF,
-	0x47, 0x3B, 0x47, 0xCF,
-
-	0x56, 0x33, 0x56, 0xCF,
-	0x67, 0x3B, 0x67, 0xCF,
-
-	0x0B, 0x48, 0xA0, 0xE8,
-	0x1B, 0x58, 0xA0, 0xE8,
-
-	0x2B, 0x68, 0xA0, 0xE8,
-	0x0C, 0x49, 0xA0, 0xE8,
-
-	0x1C, 0x59, 0xA0, 0xE8,
-	0x2C, 0x69, 0xA0, 0xE8,
-
-	0x0B, 0x00,
-	0x1B, 0x00,
-	0x2B, 0x00,
-	0x00, 0xE0,
-
-	0x0C, 0x00,
-	0x1C, 0x00,
-	0x2C, 0x00,
-	0x00, 0xE0,
-
-	0x0B, 0x65,
-	0x1B, 0x65,
-	0x2B, 0x65,
-	0x00, 0xE0,
-
-	0x0C, 0x65,
-	0x1C, 0x65,
-	0x2C, 0x65,
-	0x00, 0xE0,
-
-	0x0B, 0x1B, 0x60, 0xEC,
-	0x34, 0xD7, 0x34, 0xAD,
-
-	0x2B, 0x80, 0x60, 0xEC,
-	0x0C, 0x1C, 0x60, 0xEC,
-
-	0x3C, 0xD7, 0x3C, 0xAD,
-	0x2C, 0x80, 0x60, 0xEC,
-
-	0x0B, 0x2B, 0xDE, 0xE8,
-	0x1B, 0x80, 0xDE, 0xE8,
-
-	0x34, 0x80, 0x34, 0xBD,
-	0x3C, 0x80, 0x3C, 0xBD,
-
-	0x33, 0xD7, 0x0B, 0xBD,
-	0x3B, 0xD7, 0x1B, 0xBD,
-
-	0x48, 0x80, 0x48, 0xCF,
-	0x59, 0x80, 0x59, 0xCF,
-
-	0x68, 0x33, 0x68, 0xCF,
-	0x49, 0x3B, 0x49, 0xCF,
-
-	0xBE, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x58, 0x33, 0x58, 0xCF,
-	0x69, 0x3B, 0x69, 0xCF,
-
-	0x7D, 0xFF, 0x20, 0xEA,
-	0x57, 0xC0, 0xBF, 0xEA,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_t2gza[] = {
-
-	0x00, 0x8A, 0x98, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x0A, 0x40, 0x50, 0xBF,
-	0x2A, 0x40, 0x60, 0xBF,
-
-	0x32, 0x41, 0x51, 0xBF,
-	0x3A, 0x41, 0x61, 0xBF,
-
-	0xC3, 0x6B,
-	0xD3, 0x6B,
-	0x00, 0x8A, 0x98, 0xE9,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x96, 0xE2,
-	0x41, 0x04,
-
-	0x7B, 0x43, 0xA0, 0xE8,
-	0x73, 0x53, 0xA0, 0xE8,
-
-	0xAD, 0xEE, 0x23, 0x9F,
-	0x00, 0xE0,
-	0x51, 0x04,
-
-	0x90, 0xE2,
-	0x61, 0x04,
-	0x31, 0x46, 0xB1, 0xE8,
-
-	0x51, 0x41, 0xE0, 0xEC,
-	0x39, 0x67, 0xB1, 0xE8,
-
-	0x00, 0x04,
-	0x46, 0xE2,
-	0x73, 0x63, 0xA0, 0xE8,
-
-	0x61, 0x41, 0xE0, 0xEC,
-	0x31, 0x00,
-	0x39, 0x00,
-
-	0x7C, 0x80, 0x15, 0xEA,
-	0x10, 0x04,
-	0x20, 0x04,
-
-	0x61, 0x51, 0xE0, 0xEC,
-	0x2F, 0x41, 0x60, 0xEA,
-
-	0x31, 0x20,
-	0x39, 0x20,
-	0x1F, 0x42, 0xA0, 0xE8,
-
-	0x2A, 0x42, 0x52, 0xBF,
-	0x0F, 0x52, 0xA0, 0xE8,
-
-	0x1A, 0x42, 0x62, 0xBF,
-	0x1E, 0x51, 0x60, 0xEA,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x0E, 0x61, 0x60, 0xEA,
-
-	0x32, 0x40, 0x50, 0xBD,
-	0x22, 0x40, 0x60, 0xBD,
-
-	0x12, 0x41, 0x51, 0xBD,
-	0x3A, 0x41, 0x61, 0xBD,
-
-	0xBF, 0x2F, 0x0E, 0xBD,
-	0x97, 0xE2,
-	0x7B, 0x72,
-
-	0x32, 0x20,
-	0x22, 0x20,
-	0x12, 0x20,
-	0x3A, 0x20,
-
-	0x35, 0x48, 0xB1, 0xE8,
-	0x3D, 0x59, 0xB1, 0xE8,
-
-	0x46, 0x31, 0x46, 0xBF,
-	0x56, 0x31, 0x56, 0xBF,
-
-	0xB3, 0xE2, 0x2D, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x66, 0x31, 0x66, 0xBF,
-	0x47, 0x39, 0x47, 0xBF,
-
-	0x57, 0x39, 0x57, 0xBF,
-	0x67, 0x39, 0x67, 0xBF,
-
-	0x6D, 0x80, 0x07, 0xEA,
-	0x24, 0x41, 0x20, 0xE9,
-
-	0x35, 0x00,
-	0x3D, 0x00,
-	0x00, 0xE0,
-	0x2D, 0x73,
-
-	0x33, 0x72,
-	0x0C, 0xE3,
-	0x8D, 0x2F, 0x1E, 0xBD,
-
-	0x43, 0x75, 0xF8, 0xEC,
-	0x35, 0x20,
-	0x3D, 0x20,
-
-	0x43, 0x43, 0x2D, 0xDF,
-	0x53, 0x53, 0x2D, 0xDF,
-
-	0xAE, 0x1E, 0x0E, 0xBD,
-	0x58, 0xE3,
-	0x33, 0x66,
-
-	0x48, 0x35, 0x48, 0xBF,
-	0x58, 0x35, 0x58, 0xBF,
-
-	0x68, 0x35, 0x68, 0xBF,
-	0x49, 0x3D, 0x49, 0xBF,
-
-	0x59, 0x3D, 0x59, 0xBF,
-	0x69, 0x3D, 0x69, 0xBF,
-
-	0x63, 0x63, 0x2D, 0xDF,
-	0x4D, 0x7D, 0xF8, 0xEC,
-
-	0x59, 0xE3,
-	0x00, 0xE0,
-	0xB8, 0x38, 0x33, 0xBF,
-
-	0x2D, 0x73,
-	0x30, 0x76,
-	0x18, 0x3A, 0x41, 0xE9,
-
-	0x3F, 0x53, 0xA0, 0xE8,
-	0x05, 0x80, 0x3D, 0xEA,
-
-	0x37, 0x43, 0xA0, 0xE8,
-	0x3D, 0x63, 0xA0, 0xE8,
-
-	0x50, 0x70, 0xF8, 0xEC,
-	0x2B, 0x50, 0x3C, 0xE9,
-
-	0x1F, 0x0F, 0xBC, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x59, 0x78, 0xF8, 0xEC,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x1E, 0x12, 0x41, 0xE9,
-	0x1A, 0x22, 0x41, 0xE9,
-
-	0x46, 0x37, 0x46, 0xDF,
-	0x56, 0x3F, 0x56, 0xDF,
-
-	0x2B, 0x40, 0x3D, 0xE9,
-	0x66, 0x3D, 0x66, 0xDF,
-
-	0x1D, 0x32, 0x41, 0xE9,
-	0x67, 0x3D, 0x67, 0xDF,
-
-	0x47, 0x37, 0x47, 0xDF,
-	0x57, 0x3F, 0x57, 0xDF,
-
-	0x2A, 0x40, 0x20, 0xE9,
-	0x59, 0x3F, 0x59, 0xDF,
-
-	0x16, 0x30, 0x20, 0xE9,
-	0x69, 0x3D, 0x69, 0xDF,
-
-	0x48, 0x37, 0x48, 0xDF,
-	0x58, 0x3F, 0x58, 0xDF,
-
-	0x12, 0x12, 0x2D, 0xDF,
-	0x22, 0x22, 0x2D, 0xDF,
-
-	0x32, 0x32, 0x2D, 0xDF,
-	0x3A, 0x3A, 0x2D, 0xDF,
-
-	0x68, 0x3D, 0x68, 0xDF,
-	0x49, 0x37, 0x49, 0xDF,
-
-	0x3D, 0xCF, 0x74, 0xC0,
-	0x37, 0xCF, 0x74, 0xC4,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x34, 0x80, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3C, 0x3D, 0x20, 0xE9,
-
-	0x0A, 0x44, 0x54, 0xB0,
-	0x02, 0x44, 0x64, 0xB0,
-
-	0x2A, 0x44, 0x54, 0xB2,
-	0x1A, 0x44, 0x64, 0xB2,
-
-	0x29, 0x80, 0x3A, 0xEA,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x0F, 0xCF, 0x74, 0xC6,
-	0x3D, 0xCF, 0x74, 0xC2,
-
-	0x88, 0x73, 0x5E, 0xE9,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x32, 0x31, 0x5F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x33, 0x39, 0x5F, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x9C, 0x0F, 0x20, 0xE9,
-
-	0x0A, 0x44, 0x54, 0xB4,
-	0x02, 0x44, 0x64, 0xB4,
-
-	0x2A, 0x44, 0x54, 0xB6,
-	0x1A, 0x44, 0x64, 0xB6,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x38, 0x3D, 0x20, 0xE9,
-
-	0x0A, 0x20,
-	0x02, 0x20,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x0A, 0x47, 0x57, 0xBF,
-	0x02, 0x47, 0x67, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x3E, 0x30, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x3F, 0x38, 0x4F, 0xE9,
-
-	0x2A, 0x46, 0x56, 0xBF,
-	0x1A, 0x46, 0x66, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x3A, 0x31, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3B, 0x39, 0x4F, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x36, 0x30, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x37, 0x38, 0x4F, 0xE9,
-
-	0x2A, 0x43, 0x53, 0xBF,
-	0x1A, 0x43, 0x63, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x9D, 0x31, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x9E, 0x39, 0x4F, 0xE9,
-
-	0x0A, 0x48, 0x58, 0xBF,
-	0x02, 0x48, 0x68, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x80, 0x31, 0x57, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x81, 0x39, 0x57, 0xE9,
-
-	0x2A, 0x49, 0x59, 0xBF,
-	0x1A, 0x49, 0x69, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x82, 0x30, 0x57, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x83, 0x38, 0x57, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x84, 0x31, 0x5E, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x85, 0x39, 0x5E, 0xE9,
-
-	0x86, 0x76, 0x57, 0xE9,
-	0x8A, 0x36, 0x20, 0xE9,
-
-	0x87, 0x77, 0x57, 0xE9,
-	0x8B, 0x3E, 0xBF, 0xEA,
-
-	0x80, 0x30, 0x57, 0xE9,
-	0x81, 0x38, 0x57, 0xE9,
-
-	0x82, 0x31, 0x57, 0xE9,
-	0x86, 0x78, 0x57, 0xE9,
-
-	0x83, 0x39, 0x57, 0xE9,
-	0x87, 0x79, 0x57, 0xE9,
-
-	0x30, 0x1F, 0x5F, 0xE9,
-	0x8A, 0x34, 0x20, 0xE9,
-
-	0x8B, 0x3C, 0x20, 0xE9,
-	0x37, 0x50, 0x60, 0xBD,
-
-	0x57, 0x0D, 0x20, 0xE9,
-	0x35, 0x51, 0x61, 0xBD,
-
-	0x2B, 0x50, 0x20, 0xE9,
-	0x1D, 0x37, 0xE1, 0xEA,
-
-	0x1E, 0x35, 0xE1, 0xEA,
-	0x00, 0xE0,
-	0x0E, 0x77,
-
-	0x24, 0x51, 0x20, 0xE9,
-	0x9B, 0xFF, 0x20, 0xEA,
-
-	0x16, 0x0E, 0x20, 0xE9,
-	0x57, 0x2E, 0xBF, 0xEA,
-
-	0x0B, 0x46, 0xA0, 0xE8,
-	0x1B, 0x56, 0xA0, 0xE8,
-
-	0x2B, 0x66, 0xA0, 0xE8,
-	0x0C, 0x47, 0xA0, 0xE8,
-
-	0x1C, 0x57, 0xA0, 0xE8,
-	0x2C, 0x67, 0xA0, 0xE8,
-
-	0x0B, 0x00,
-	0x1B, 0x00,
-	0x2B, 0x00,
-	0x00, 0xE0,
-
-	0x0C, 0x00,
-	0x1C, 0x00,
-	0x2C, 0x00,
-	0x00, 0xE0,
-
-	0x0B, 0x65,
-	0x1B, 0x65,
-	0x2B, 0x65,
-	0x00, 0xE0,
-
-	0x0C, 0x65,
-	0x1C, 0x65,
-	0x2C, 0x65,
-	0x00, 0xE0,
-
-	0x0B, 0x1B, 0x60, 0xEC,
-	0x36, 0xD7, 0x36, 0xAD,
-
-	0x2B, 0x80, 0x60, 0xEC,
-	0x0C, 0x1C, 0x60, 0xEC,
-
-	0x3E, 0xD7, 0x3E, 0xAD,
-	0x2C, 0x80, 0x60, 0xEC,
-
-	0x0B, 0x2B, 0xDE, 0xE8,
-	0x1B, 0x80, 0xDE, 0xE8,
-
-	0x36, 0x80, 0x36, 0xBD,
-	0x3E, 0x80, 0x3E, 0xBD,
-
-	0x33, 0xD7, 0x0B, 0xBD,
-	0x3B, 0xD7, 0x1B, 0xBD,
-
-	0x46, 0x80, 0x46, 0xCF,
-	0x57, 0x80, 0x57, 0xCF,
-
-	0x66, 0x33, 0x66, 0xCF,
-	0x47, 0x3B, 0x47, 0xCF,
-
-	0x56, 0x33, 0x56, 0xCF,
-	0x67, 0x3B, 0x67, 0xCF,
-
-	0x0B, 0x48, 0xA0, 0xE8,
-	0x1B, 0x58, 0xA0, 0xE8,
-
-	0x2B, 0x68, 0xA0, 0xE8,
-	0x0C, 0x49, 0xA0, 0xE8,
-
-	0x1C, 0x59, 0xA0, 0xE8,
-	0x2C, 0x69, 0xA0, 0xE8,
-
-	0x0B, 0x00,
-	0x1B, 0x00,
-	0x2B, 0x00,
-	0x00, 0xE0,
-
-	0x0C, 0x00,
-	0x1C, 0x00,
-	0x2C, 0x00,
-	0x00, 0xE0,
-
-	0x0B, 0x65,
-	0x1B, 0x65,
-	0x2B, 0x65,
-	0x00, 0xE0,
-
-	0x0C, 0x65,
-	0x1C, 0x65,
-	0x2C, 0x65,
-	0x00, 0xE0,
-
-	0x0B, 0x1B, 0x60, 0xEC,
-	0x34, 0xD7, 0x34, 0xAD,
-
-	0x2B, 0x80, 0x60, 0xEC,
-	0x0C, 0x1C, 0x60, 0xEC,
-
-	0x3C, 0xD7, 0x3C, 0xAD,
-	0x2C, 0x80, 0x60, 0xEC,
-
-	0x0B, 0x2B, 0xDE, 0xE8,
-	0x1B, 0x80, 0xDE, 0xE8,
-
-	0x34, 0x80, 0x34, 0xBD,
-	0x3C, 0x80, 0x3C, 0xBD,
-
-	0x33, 0xD7, 0x0B, 0xBD,
-	0x3B, 0xD7, 0x1B, 0xBD,
-
-	0x48, 0x80, 0x48, 0xCF,
-	0x59, 0x80, 0x59, 0xCF,
-
-	0x68, 0x33, 0x68, 0xCF,
-	0x49, 0x3B, 0x49, 0xCF,
-
-	0xBA, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x58, 0x33, 0x58, 0xCF,
-	0x69, 0x3B, 0x69, 0xCF,
-
-	0x79, 0xFF, 0x20, 0xEA,
-	0x57, 0xC0, 0xBF, 0xEA,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_t2gzaf[] = {
-
-	0x00, 0x8A, 0x98, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x0A, 0x40, 0x50, 0xBF,
-	0x2A, 0x40, 0x60, 0xBF,
-
-	0x32, 0x41, 0x51, 0xBF,
-	0x3A, 0x41, 0x61, 0xBF,
-
-	0xC3, 0x6B,
-	0xD3, 0x6B,
-	0x00, 0x8A, 0x98, 0xE9,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x96, 0xE2,
-	0x41, 0x04,
-
-	0x7B, 0x43, 0xA0, 0xE8,
-	0x73, 0x53, 0xA0, 0xE8,
-
-	0xAD, 0xEE, 0x23, 0x9F,
-	0x00, 0xE0,
-	0x51, 0x04,
-
-	0x90, 0xE2,
-	0x61, 0x04,
-	0x31, 0x46, 0xB1, 0xE8,
-
-	0x51, 0x41, 0xE0, 0xEC,
-	0x39, 0x67, 0xB1, 0xE8,
-
-	0x00, 0x04,
-	0x46, 0xE2,
-	0x73, 0x63, 0xA0, 0xE8,
-
-	0x61, 0x41, 0xE0, 0xEC,
-	0x31, 0x00,
-	0x39, 0x00,
-
-	0x81, 0x80, 0x15, 0xEA,
-	0x10, 0x04,
-	0x20, 0x04,
-
-	0x61, 0x51, 0xE0, 0xEC,
-	0x2F, 0x41, 0x60, 0xEA,
-
-	0x31, 0x20,
-	0x39, 0x20,
-	0x1F, 0x42, 0xA0, 0xE8,
-
-	0x2A, 0x42, 0x52, 0xBF,
-	0x0F, 0x52, 0xA0, 0xE8,
-
-	0x1A, 0x42, 0x62, 0xBF,
-	0x1E, 0x51, 0x60, 0xEA,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x0E, 0x61, 0x60, 0xEA,
-
-	0x32, 0x40, 0x50, 0xBD,
-	0x22, 0x40, 0x60, 0xBD,
-
-	0x12, 0x41, 0x51, 0xBD,
-	0x3A, 0x41, 0x61, 0xBD,
-
-	0xBF, 0x2F, 0x0E, 0xBD,
-	0x97, 0xE2,
-	0x7B, 0x72,
-
-	0x32, 0x20,
-	0x22, 0x20,
-	0x12, 0x20,
-	0x3A, 0x20,
-
-	0x35, 0x48, 0xB1, 0xE8,
-	0x3D, 0x59, 0xB1, 0xE8,
-
-	0x46, 0x31, 0x46, 0xBF,
-	0x56, 0x31, 0x56, 0xBF,
-
-	0xB3, 0xE2, 0x2D, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x66, 0x31, 0x66, 0xBF,
-	0x47, 0x39, 0x47, 0xBF,
-
-	0x57, 0x39, 0x57, 0xBF,
-	0x67, 0x39, 0x67, 0xBF,
-
-	0x72, 0x80, 0x07, 0xEA,
-	0x24, 0x41, 0x20, 0xE9,
-
-	0x35, 0x00,
-	0x3D, 0x00,
-	0x00, 0xE0,
-	0x2D, 0x73,
-
-	0x33, 0x72,
-	0x0C, 0xE3,
-	0x8D, 0x2F, 0x1E, 0xBD,
-
-	0x43, 0x75, 0xF8, 0xEC,
-	0x35, 0x20,
-	0x3D, 0x20,
-
-	0x43, 0x43, 0x2D, 0xDF,
-	0x53, 0x53, 0x2D, 0xDF,
-
-	0xAE, 0x1E, 0x0E, 0xBD,
-	0x58, 0xE3,
-	0x33, 0x66,
-
-	0x48, 0x35, 0x48, 0xBF,
-	0x58, 0x35, 0x58, 0xBF,
-
-	0x68, 0x35, 0x68, 0xBF,
-	0x49, 0x3D, 0x49, 0xBF,
-
-	0x59, 0x3D, 0x59, 0xBF,
-	0x69, 0x3D, 0x69, 0xBF,
-
-	0x63, 0x63, 0x2D, 0xDF,
-	0x4D, 0x7D, 0xF8, 0xEC,
-
-	0x59, 0xE3,
-	0x00, 0xE0,
-	0xB8, 0x38, 0x33, 0xBF,
-
-	0x2D, 0x73,
-	0x30, 0x76,
-	0x18, 0x3A, 0x41, 0xE9,
-
-	0x3F, 0x53, 0xA0, 0xE8,
-	0x05, 0x80, 0x3D, 0xEA,
-
-	0x37, 0x43, 0xA0, 0xE8,
-	0x3D, 0x63, 0xA0, 0xE8,
-
-	0x50, 0x70, 0xF8, 0xEC,
-	0x2B, 0x50, 0x3C, 0xE9,
-
-	0x1F, 0x0F, 0xBC, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x59, 0x78, 0xF8, 0xEC,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x1E, 0x12, 0x41, 0xE9,
-	0x1A, 0x22, 0x41, 0xE9,
-
-	0x46, 0x37, 0x46, 0xDF,
-	0x56, 0x3F, 0x56, 0xDF,
-
-	0x2B, 0x40, 0x3D, 0xE9,
-	0x66, 0x3D, 0x66, 0xDF,
-
-	0x1D, 0x32, 0x41, 0xE9,
-	0x67, 0x3D, 0x67, 0xDF,
-
-	0x47, 0x37, 0x47, 0xDF,
-	0x57, 0x3F, 0x57, 0xDF,
-
-	0x2A, 0x40, 0x20, 0xE9,
-	0x59, 0x3F, 0x59, 0xDF,
-
-	0x16, 0x30, 0x20, 0xE9,
-	0x69, 0x3D, 0x69, 0xDF,
-
-	0x48, 0x37, 0x48, 0xDF,
-	0x58, 0x3F, 0x58, 0xDF,
-
-	0x12, 0x12, 0x2D, 0xDF,
-	0x22, 0x22, 0x2D, 0xDF,
-
-	0x32, 0x32, 0x2D, 0xDF,
-	0x3A, 0x3A, 0x2D, 0xDF,
-
-	0x68, 0x3D, 0x68, 0xDF,
-	0x49, 0x37, 0x49, 0xDF,
-
-	0x3D, 0xCF, 0x74, 0xC0,
-	0x37, 0xCF, 0x74, 0xC4,
-
-	0x0A, 0x44, 0x54, 0xB0,
-	0x02, 0x44, 0x64, 0xB0,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x34, 0x37, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3C, 0x3D, 0x20, 0xE9,
-
-	0x2A, 0x44, 0x54, 0xB2,
-	0x1A, 0x44, 0x64, 0xB2,
-
-	0x2E, 0x80, 0x3A, 0xEA,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x88, 0x73, 0x5E, 0xE9,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x3D, 0xCF, 0x74, 0xC2,
-	0x0F, 0xCF, 0x74, 0xC6,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x32, 0x31, 0x5F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x33, 0x39, 0x5F, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x9C, 0x0F, 0x20, 0xE9,
-
-	0x0A, 0x44, 0x54, 0xB4,
-	0x02, 0x44, 0x64, 0xB4,
-
-	0x2A, 0x44, 0x54, 0xB6,
-	0x1A, 0x44, 0x64, 0xB6,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x38, 0x3D, 0x20, 0xE9,
-
-	0x0A, 0x20,
-	0x02, 0x20,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x3D, 0xCF, 0x75, 0xC6,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x3E, 0x30, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x3F, 0x38, 0x4F, 0xE9,
-
-	0x0A, 0x45, 0x55, 0xB6,
-	0x02, 0x45, 0x65, 0xB6,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x3A, 0x31, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3B, 0x39, 0x4F, 0xE9,
-
-	0x31, 0x3D, 0x20, 0xE9,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x2A, 0x46, 0x56, 0xBF,
-	0x1A, 0x46, 0x66, 0xBF,
-
-	0x0A, 0x47, 0x57, 0xBF,
-	0x02, 0x47, 0x67, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x36, 0x30, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x37, 0x38, 0x4F, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x9D, 0x31, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x9E, 0x39, 0x4F, 0xE9,
-
-	0x2A, 0x43, 0x53, 0xBF,
-	0x1A, 0x43, 0x63, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x35, 0x30, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x39, 0x38, 0x4F, 0xE9,
-
-	0x0A, 0x48, 0x58, 0xBF,
-	0x02, 0x48, 0x68, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x80, 0x31, 0x57, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x81, 0x39, 0x57, 0xE9,
-
-	0x2A, 0x49, 0x59, 0xBF,
-	0x1A, 0x49, 0x69, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x82, 0x30, 0x57, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x83, 0x38, 0x57, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x84, 0x31, 0x5E, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x85, 0x39, 0x5E, 0xE9,
-
-	0x86, 0x76, 0x57, 0xE9,
-	0x8A, 0x36, 0x20, 0xE9,
-
-	0x87, 0x77, 0x57, 0xE9,
-	0x8B, 0x3E, 0xBF, 0xEA,
-
-	0x80, 0x30, 0x57, 0xE9,
-	0x81, 0x38, 0x57, 0xE9,
-
-	0x82, 0x31, 0x57, 0xE9,
-	0x86, 0x78, 0x57, 0xE9,
-
-	0x83, 0x39, 0x57, 0xE9,
-	0x87, 0x79, 0x57, 0xE9,
-
-	0x30, 0x1F, 0x5F, 0xE9,
-	0x8A, 0x34, 0x20, 0xE9,
-
-	0x8B, 0x3C, 0x20, 0xE9,
-	0x37, 0x50, 0x60, 0xBD,
-
-	0x57, 0x0D, 0x20, 0xE9,
-	0x35, 0x51, 0x61, 0xBD,
-
-	0x2B, 0x50, 0x20, 0xE9,
-	0x1D, 0x37, 0xE1, 0xEA,
-
-	0x1E, 0x35, 0xE1, 0xEA,
-	0x00, 0xE0,
-	0x0E, 0x77,
-
-	0x24, 0x51, 0x20, 0xE9,
-	0x96, 0xFF, 0x20, 0xEA,
-
-	0x16, 0x0E, 0x20, 0xE9,
-	0x57, 0x2E, 0xBF, 0xEA,
-
-	0x0B, 0x46, 0xA0, 0xE8,
-	0x1B, 0x56, 0xA0, 0xE8,
-
-	0x2B, 0x66, 0xA0, 0xE8,
-	0x0C, 0x47, 0xA0, 0xE8,
-
-	0x1C, 0x57, 0xA0, 0xE8,
-	0x2C, 0x67, 0xA0, 0xE8,
-
-	0x0B, 0x00,
-	0x1B, 0x00,
-	0x2B, 0x00,
-	0x00, 0xE0,
-
-	0x0C, 0x00,
-	0x1C, 0x00,
-	0x2C, 0x00,
-	0x00, 0xE0,
-
-	0x0B, 0x65,
-	0x1B, 0x65,
-	0x2B, 0x65,
-	0x00, 0xE0,
-
-	0x0C, 0x65,
-	0x1C, 0x65,
-	0x2C, 0x65,
-	0x00, 0xE0,
-
-	0x0B, 0x1B, 0x60, 0xEC,
-	0x36, 0xD7, 0x36, 0xAD,
-
-	0x2B, 0x80, 0x60, 0xEC,
-	0x0C, 0x1C, 0x60, 0xEC,
-
-	0x3E, 0xD7, 0x3E, 0xAD,
-	0x2C, 0x80, 0x60, 0xEC,
-
-	0x0B, 0x2B, 0xDE, 0xE8,
-	0x1B, 0x80, 0xDE, 0xE8,
-
-	0x36, 0x80, 0x36, 0xBD,
-	0x3E, 0x80, 0x3E, 0xBD,
-
-	0x33, 0xD7, 0x0B, 0xBD,
-	0x3B, 0xD7, 0x1B, 0xBD,
-
-	0x46, 0x80, 0x46, 0xCF,
-	0x57, 0x80, 0x57, 0xCF,
-
-	0x66, 0x33, 0x66, 0xCF,
-	0x47, 0x3B, 0x47, 0xCF,
-
-	0x56, 0x33, 0x56, 0xCF,
-	0x67, 0x3B, 0x67, 0xCF,
-
-	0x0B, 0x48, 0xA0, 0xE8,
-	0x1B, 0x58, 0xA0, 0xE8,
-
-	0x2B, 0x68, 0xA0, 0xE8,
-	0x0C, 0x49, 0xA0, 0xE8,
-
-	0x1C, 0x59, 0xA0, 0xE8,
-	0x2C, 0x69, 0xA0, 0xE8,
-
-	0x0B, 0x00,
-	0x1B, 0x00,
-	0x2B, 0x00,
-	0x00, 0xE0,
-
-	0x0C, 0x00,
-	0x1C, 0x00,
-	0x2C, 0x00,
-	0x00, 0xE0,
-
-	0x0B, 0x65,
-	0x1B, 0x65,
-	0x2B, 0x65,
-	0x00, 0xE0,
-
-	0x0C, 0x65,
-	0x1C, 0x65,
-	0x2C, 0x65,
-	0x00, 0xE0,
-
-	0x0B, 0x1B, 0x60, 0xEC,
-	0x34, 0xD7, 0x34, 0xAD,
-
-	0x2B, 0x80, 0x60, 0xEC,
-	0x0C, 0x1C, 0x60, 0xEC,
-
-	0x3C, 0xD7, 0x3C, 0xAD,
-	0x2C, 0x80, 0x60, 0xEC,
-
-	0x0B, 0x2B, 0xDE, 0xE8,
-	0x1B, 0x80, 0xDE, 0xE8,
-
-	0x34, 0x80, 0x34, 0xBD,
-	0x3C, 0x80, 0x3C, 0xBD,
-
-	0x33, 0xD7, 0x0B, 0xBD,
-	0x3B, 0xD7, 0x1B, 0xBD,
-
-	0x48, 0x80, 0x48, 0xCF,
-	0x59, 0x80, 0x59, 0xCF,
-
-	0x68, 0x33, 0x68, 0xCF,
-	0x49, 0x3B, 0x49, 0xCF,
-
-	0xB5, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x58, 0x33, 0x58, 0xCF,
-	0x69, 0x3B, 0x69, 0xCF,
-
-	0x74, 0xFF, 0x20, 0xEA,
-	0x57, 0xC0, 0xBF, 0xEA,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_t2gzf[] = {
-
-	0x00, 0x8A, 0x98, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x0A, 0x40, 0x50, 0xBF,
-	0x2A, 0x40, 0x60, 0xBF,
-
-	0x32, 0x41, 0x51, 0xBF,
-	0x3A, 0x41, 0x61, 0xBF,
-
-	0xC3, 0x6B,
-	0xD3, 0x6B,
-	0x00, 0x8A, 0x98, 0xE9,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x96, 0xE2,
-	0x41, 0x04,
-
-	0x7B, 0x43, 0xA0, 0xE8,
-	0x73, 0x53, 0xA0, 0xE8,
-
-	0xAD, 0xEE, 0x23, 0x9F,
-	0x00, 0xE0,
-	0x51, 0x04,
-
-	0x90, 0xE2,
-	0x61, 0x04,
-	0x31, 0x46, 0xB1, 0xE8,
-
-	0x51, 0x41, 0xE0, 0xEC,
-	0x39, 0x67, 0xB1, 0xE8,
-
-	0x00, 0x04,
-	0x46, 0xE2,
-	0x73, 0x63, 0xA0, 0xE8,
-
-	0x61, 0x41, 0xE0, 0xEC,
-	0x31, 0x00,
-	0x39, 0x00,
-
-	0x7D, 0x80, 0x15, 0xEA,
-	0x10, 0x04,
-	0x20, 0x04,
-
-	0x61, 0x51, 0xE0, 0xEC,
-	0x2F, 0x41, 0x60, 0xEA,
-
-	0x31, 0x20,
-	0x39, 0x20,
-	0x1F, 0x42, 0xA0, 0xE8,
-
-	0x2A, 0x42, 0x52, 0xBF,
-	0x0F, 0x52, 0xA0, 0xE8,
-
-	0x1A, 0x42, 0x62, 0xBF,
-	0x1E, 0x51, 0x60, 0xEA,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x0E, 0x61, 0x60, 0xEA,
-
-	0x32, 0x40, 0x50, 0xBD,
-	0x22, 0x40, 0x60, 0xBD,
-
-	0x12, 0x41, 0x51, 0xBD,
-	0x3A, 0x41, 0x61, 0xBD,
-
-	0xBF, 0x2F, 0x0E, 0xBD,
-	0x97, 0xE2,
-	0x7B, 0x72,
-
-	0x32, 0x20,
-	0x22, 0x20,
-	0x12, 0x20,
-	0x3A, 0x20,
-
-	0x35, 0x48, 0xB1, 0xE8,
-	0x3D, 0x59, 0xB1, 0xE8,
-
-	0x46, 0x31, 0x46, 0xBF,
-	0x56, 0x31, 0x56, 0xBF,
-
-	0xB3, 0xE2, 0x2D, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x66, 0x31, 0x66, 0xBF,
-	0x47, 0x39, 0x47, 0xBF,
-
-	0x57, 0x39, 0x57, 0xBF,
-	0x67, 0x39, 0x67, 0xBF,
-
-	0x6E, 0x80, 0x07, 0xEA,
-	0x24, 0x41, 0x20, 0xE9,
-
-	0x35, 0x00,
-	0x3D, 0x00,
-	0x00, 0xE0,
-	0x2D, 0x73,
-
-	0x33, 0x72,
-	0x0C, 0xE3,
-	0x8D, 0x2F, 0x1E, 0xBD,
-
-	0x43, 0x75, 0xF8, 0xEC,
-	0x35, 0x20,
-	0x3D, 0x20,
-
-	0x43, 0x43, 0x2D, 0xDF,
-	0x53, 0x53, 0x2D, 0xDF,
-
-	0xAE, 0x1E, 0x0E, 0xBD,
-	0x58, 0xE3,
-	0x33, 0x66,
-
-	0x48, 0x35, 0x48, 0xBF,
-	0x58, 0x35, 0x58, 0xBF,
-
-	0x68, 0x35, 0x68, 0xBF,
-	0x49, 0x3D, 0x49, 0xBF,
-
-	0x59, 0x3D, 0x59, 0xBF,
-	0x69, 0x3D, 0x69, 0xBF,
-
-	0x63, 0x63, 0x2D, 0xDF,
-	0x4D, 0x7D, 0xF8, 0xEC,
-
-	0x59, 0xE3,
-	0x00, 0xE0,
-	0xB8, 0x38, 0x33, 0xBF,
-
-	0x2D, 0x73,
-	0x30, 0x76,
-	0x18, 0x3A, 0x41, 0xE9,
-
-	0x3F, 0x53, 0xA0, 0xE8,
-	0x05, 0x80, 0x3D, 0xEA,
-
-	0x37, 0x43, 0xA0, 0xE8,
-	0x3D, 0x63, 0xA0, 0xE8,
-
-	0x50, 0x70, 0xF8, 0xEC,
-	0x2B, 0x50, 0x3C, 0xE9,
-
-	0x1F, 0x0F, 0xBC, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x59, 0x78, 0xF8, 0xEC,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x1E, 0x12, 0x41, 0xE9,
-	0x1A, 0x22, 0x41, 0xE9,
-
-	0x46, 0x37, 0x46, 0xDF,
-	0x56, 0x3F, 0x56, 0xDF,
-
-	0x2B, 0x40, 0x3D, 0xE9,
-	0x66, 0x3D, 0x66, 0xDF,
-
-	0x1D, 0x32, 0x41, 0xE9,
-	0x67, 0x3D, 0x67, 0xDF,
-
-	0x47, 0x37, 0x47, 0xDF,
-	0x57, 0x3F, 0x57, 0xDF,
-
-	0x2A, 0x40, 0x20, 0xE9,
-	0x59, 0x3F, 0x59, 0xDF,
-
-	0x16, 0x30, 0x20, 0xE9,
-	0x69, 0x3D, 0x69, 0xDF,
-
-	0x48, 0x37, 0x48, 0xDF,
-	0x58, 0x3F, 0x58, 0xDF,
-
-	0x12, 0x12, 0x2D, 0xDF,
-	0x22, 0x22, 0x2D, 0xDF,
-
-	0x32, 0x32, 0x2D, 0xDF,
-	0x3A, 0x3A, 0x2D, 0xDF,
-
-	0x68, 0x3D, 0x68, 0xDF,
-	0x49, 0x37, 0x49, 0xDF,
-
-	0x3D, 0xCF, 0x74, 0xC0,
-	0x37, 0xCF, 0x74, 0xC4,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x34, 0x80, 0x20, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x88, 0x73, 0x5E, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x0F, 0xCF, 0x75, 0xC6,
-	0x3C, 0x3D, 0x20, 0xE9,
-
-	0x0A, 0x44, 0x54, 0xB0,
-	0x02, 0x44, 0x64, 0xB0,
-
-	0x2A, 0x44, 0x54, 0xB2,
-	0x1A, 0x44, 0x64, 0xB2,
-
-	0x28, 0x80, 0x3A, 0xEA,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x3D, 0xCF, 0x74, 0xC2,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x32, 0x31, 0x5F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x33, 0x39, 0x5F, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x31, 0x0F, 0x20, 0xE9,
-
-	0x0A, 0x44, 0x54, 0xB4,
-	0x02, 0x44, 0x64, 0xB4,
-
-	0x2A, 0x45, 0x55, 0xB6,
-	0x1A, 0x45, 0x65, 0xB6,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x38, 0x3D, 0x20, 0xE9,
-
-	0x0A, 0x20,
-	0x02, 0x20,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x0A, 0x47, 0x57, 0xBF,
-	0x02, 0x47, 0x67, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x3E, 0x30, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x3F, 0x38, 0x4F, 0xE9,
-
-	0x2A, 0x46, 0x56, 0xBF,
-	0x1A, 0x46, 0x66, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x3A, 0x31, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3B, 0x39, 0x4F, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x36, 0x30, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x37, 0x38, 0x4F, 0xE9,
-
-	0x2A, 0x43, 0x53, 0xBF,
-	0x1A, 0x43, 0x63, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x35, 0x31, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x39, 0x39, 0x4F, 0xE9,
-
-	0x0A, 0x48, 0x58, 0xBF,
-	0x02, 0x48, 0x68, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x80, 0x31, 0x57, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x81, 0x39, 0x57, 0xE9,
-
-	0x2A, 0x49, 0x59, 0xBF,
-	0x1A, 0x49, 0x69, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x82, 0x30, 0x57, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x83, 0x38, 0x57, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x84, 0x31, 0x5E, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x85, 0x39, 0x5E, 0xE9,
-
-	0x86, 0x76, 0x57, 0xE9,
-	0x8A, 0x36, 0x20, 0xE9,
-
-	0x87, 0x77, 0x57, 0xE9,
-	0x8B, 0x3E, 0xBF, 0xEA,
-
-	0x80, 0x30, 0x57, 0xE9,
-	0x81, 0x38, 0x57, 0xE9,
-
-	0x82, 0x31, 0x57, 0xE9,
-	0x86, 0x78, 0x57, 0xE9,
-
-	0x83, 0x39, 0x57, 0xE9,
-	0x87, 0x79, 0x57, 0xE9,
-
-	0x30, 0x1F, 0x5F, 0xE9,
-	0x8A, 0x34, 0x20, 0xE9,
-
-	0x8B, 0x3C, 0x20, 0xE9,
-	0x37, 0x50, 0x60, 0xBD,
-
-	0x57, 0x0D, 0x20, 0xE9,
-	0x35, 0x51, 0x61, 0xBD,
-
-	0x2B, 0x50, 0x20, 0xE9,
-	0x1D, 0x37, 0xE1, 0xEA,
-
-	0x1E, 0x35, 0xE1, 0xEA,
-	0x00, 0xE0,
-	0x0E, 0x77,
-
-	0x24, 0x51, 0x20, 0xE9,
-	0x9A, 0xFF, 0x20, 0xEA,
-
-	0x16, 0x0E, 0x20, 0xE9,
-	0x57, 0x2E, 0xBF, 0xEA,
-
-	0x0B, 0x46, 0xA0, 0xE8,
-	0x1B, 0x56, 0xA0, 0xE8,
-
-	0x2B, 0x66, 0xA0, 0xE8,
-	0x0C, 0x47, 0xA0, 0xE8,
-
-	0x1C, 0x57, 0xA0, 0xE8,
-	0x2C, 0x67, 0xA0, 0xE8,
-
-	0x0B, 0x00,
-	0x1B, 0x00,
-	0x2B, 0x00,
-	0x00, 0xE0,
-
-	0x0C, 0x00,
-	0x1C, 0x00,
-	0x2C, 0x00,
-	0x00, 0xE0,
-
-	0x0B, 0x65,
-	0x1B, 0x65,
-	0x2B, 0x65,
-	0x00, 0xE0,
-
-	0x0C, 0x65,
-	0x1C, 0x65,
-	0x2C, 0x65,
-	0x00, 0xE0,
-
-	0x0B, 0x1B, 0x60, 0xEC,
-	0x36, 0xD7, 0x36, 0xAD,
-
-	0x2B, 0x80, 0x60, 0xEC,
-	0x0C, 0x1C, 0x60, 0xEC,
-
-	0x3E, 0xD7, 0x3E, 0xAD,
-	0x2C, 0x80, 0x60, 0xEC,
-
-	0x0B, 0x2B, 0xDE, 0xE8,
-	0x1B, 0x80, 0xDE, 0xE8,
-
-	0x36, 0x80, 0x36, 0xBD,
-	0x3E, 0x80, 0x3E, 0xBD,
-
-	0x33, 0xD7, 0x0B, 0xBD,
-	0x3B, 0xD7, 0x1B, 0xBD,
-
-	0x46, 0x80, 0x46, 0xCF,
-	0x57, 0x80, 0x57, 0xCF,
-
-	0x66, 0x33, 0x66, 0xCF,
-	0x47, 0x3B, 0x47, 0xCF,
-
-	0x56, 0x33, 0x56, 0xCF,
-	0x67, 0x3B, 0x67, 0xCF,
-
-	0x0B, 0x48, 0xA0, 0xE8,
-	0x1B, 0x58, 0xA0, 0xE8,
-
-	0x2B, 0x68, 0xA0, 0xE8,
-	0x0C, 0x49, 0xA0, 0xE8,
-
-	0x1C, 0x59, 0xA0, 0xE8,
-	0x2C, 0x69, 0xA0, 0xE8,
-
-	0x0B, 0x00,
-	0x1B, 0x00,
-	0x2B, 0x00,
-	0x00, 0xE0,
-
-	0x0C, 0x00,
-	0x1C, 0x00,
-	0x2C, 0x00,
-	0x00, 0xE0,
-
-	0x0B, 0x65,
-	0x1B, 0x65,
-	0x2B, 0x65,
-	0x00, 0xE0,
-
-	0x0C, 0x65,
-	0x1C, 0x65,
-	0x2C, 0x65,
-	0x00, 0xE0,
-
-	0x0B, 0x1B, 0x60, 0xEC,
-	0x34, 0xD7, 0x34, 0xAD,
-
-	0x2B, 0x80, 0x60, 0xEC,
-	0x0C, 0x1C, 0x60, 0xEC,
-
-	0x3C, 0xD7, 0x3C, 0xAD,
-	0x2C, 0x80, 0x60, 0xEC,
-
-	0x0B, 0x2B, 0xDE, 0xE8,
-	0x1B, 0x80, 0xDE, 0xE8,
-
-	0x34, 0x80, 0x34, 0xBD,
-	0x3C, 0x80, 0x3C, 0xBD,
-
-	0x33, 0xD7, 0x0B, 0xBD,
-	0x3B, 0xD7, 0x1B, 0xBD,
-
-	0x48, 0x80, 0x48, 0xCF,
-	0x59, 0x80, 0x59, 0xCF,
-
-	0x68, 0x33, 0x68, 0xCF,
-	0x49, 0x3B, 0x49, 0xCF,
-
-	0xBB, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x58, 0x33, 0x58, 0xCF,
-	0x69, 0x3B, 0x69, 0xCF,
-
-	0x78, 0xFF, 0x20, 0xEA,
-	0x57, 0xC0, 0xBF, 0xEA,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_t2gzs[] = {
-
-	0x00, 0x8A, 0x98, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x0A, 0x40, 0x50, 0xBF,
-	0x2A, 0x40, 0x60, 0xBF,
-
-	0x32, 0x41, 0x51, 0xBF,
-	0x3A, 0x41, 0x61, 0xBF,
-
-	0xC3, 0x6B,
-	0xD3, 0x6B,
-	0x00, 0x8A, 0x98, 0xE9,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x96, 0xE2,
-	0x41, 0x04,
-
-	0x7B, 0x43, 0xA0, 0xE8,
-	0x73, 0x53, 0xA0, 0xE8,
-
-	0xAD, 0xEE, 0x23, 0x9F,
-	0x00, 0xE0,
-	0x51, 0x04,
-
-	0x90, 0xE2,
-	0x61, 0x04,
-	0x31, 0x46, 0xB1, 0xE8,
-
-	0x51, 0x41, 0xE0, 0xEC,
-	0x39, 0x67, 0xB1, 0xE8,
-
-	0x00, 0x04,
-	0x46, 0xE2,
-	0x73, 0x63, 0xA0, 0xE8,
-
-	0x61, 0x41, 0xE0, 0xEC,
-	0x31, 0x00,
-	0x39, 0x00,
-
-	0x85, 0x80, 0x15, 0xEA,
-	0x10, 0x04,
-	0x20, 0x04,
-
-	0x61, 0x51, 0xE0, 0xEC,
-	0x2F, 0x41, 0x60, 0xEA,
-
-	0x31, 0x20,
-	0x39, 0x20,
-	0x1F, 0x42, 0xA0, 0xE8,
-
-	0x2A, 0x42, 0x52, 0xBF,
-	0x0F, 0x52, 0xA0, 0xE8,
-
-	0x1A, 0x42, 0x62, 0xBF,
-	0x1E, 0x51, 0x60, 0xEA,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x0E, 0x61, 0x60, 0xEA,
-
-	0x32, 0x40, 0x50, 0xBD,
-	0x22, 0x40, 0x60, 0xBD,
-
-	0x12, 0x41, 0x51, 0xBD,
-	0x3A, 0x41, 0x61, 0xBD,
-
-	0xBF, 0x2F, 0x0E, 0xBD,
-	0x97, 0xE2,
-	0x7B, 0x72,
-
-	0x32, 0x20,
-	0x22, 0x20,
-	0x12, 0x20,
-	0x3A, 0x20,
-
-	0x35, 0x48, 0xB1, 0xE8,
-	0x3D, 0x59, 0xB1, 0xE8,
-
-	0x46, 0x31, 0x46, 0xBF,
-	0x56, 0x31, 0x56, 0xBF,
-
-	0xB3, 0xE2, 0x2D, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x66, 0x31, 0x66, 0xBF,
-	0x47, 0x39, 0x47, 0xBF,
-
-	0x57, 0x39, 0x57, 0xBF,
-	0x67, 0x39, 0x67, 0xBF,
-
-	0x76, 0x80, 0x07, 0xEA,
-	0x24, 0x41, 0x20, 0xE9,
-
-	0x35, 0x00,
-	0x3D, 0x00,
-	0x00, 0xE0,
-	0x2D, 0x73,
-
-	0x33, 0x72,
-	0x0C, 0xE3,
-	0x8D, 0x2F, 0x1E, 0xBD,
-
-	0x43, 0x75, 0xF8, 0xEC,
-	0x35, 0x20,
-	0x3D, 0x20,
-
-	0x43, 0x43, 0x2D, 0xDF,
-	0x53, 0x53, 0x2D, 0xDF,
-
-	0xAE, 0x1E, 0x0E, 0xBD,
-	0x58, 0xE3,
-	0x33, 0x66,
-
-	0x48, 0x35, 0x48, 0xBF,
-	0x58, 0x35, 0x58, 0xBF,
-
-	0x68, 0x35, 0x68, 0xBF,
-	0x49, 0x3D, 0x49, 0xBF,
-
-	0x59, 0x3D, 0x59, 0xBF,
-	0x69, 0x3D, 0x69, 0xBF,
-
-	0x63, 0x63, 0x2D, 0xDF,
-	0x4D, 0x7D, 0xF8, 0xEC,
-
-	0x59, 0xE3,
-	0x00, 0xE0,
-	0xB8, 0x38, 0x33, 0xBF,
-
-	0x2D, 0x73,
-	0x30, 0x76,
-	0x18, 0x3A, 0x41, 0xE9,
-
-	0x3F, 0x53, 0xA0, 0xE8,
-	0x05, 0x80, 0x3D, 0xEA,
-
-	0x37, 0x43, 0xA0, 0xE8,
-	0x3D, 0x63, 0xA0, 0xE8,
-
-	0x50, 0x70, 0xF8, 0xEC,
-	0x2B, 0x50, 0x3C, 0xE9,
-
-	0x1F, 0x0F, 0xBC, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x59, 0x78, 0xF8, 0xEC,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x1E, 0x12, 0x41, 0xE9,
-	0x1A, 0x22, 0x41, 0xE9,
-
-	0x46, 0x37, 0x46, 0xDF,
-	0x56, 0x3F, 0x56, 0xDF,
-
-	0x2B, 0x40, 0x3D, 0xE9,
-	0x66, 0x3D, 0x66, 0xDF,
-
-	0x1D, 0x32, 0x41, 0xE9,
-	0x67, 0x3D, 0x67, 0xDF,
-
-	0x47, 0x37, 0x47, 0xDF,
-	0x57, 0x3F, 0x57, 0xDF,
-
-	0x2A, 0x40, 0x20, 0xE9,
-	0x59, 0x3F, 0x59, 0xDF,
-
-	0x16, 0x30, 0x20, 0xE9,
-	0x69, 0x3D, 0x69, 0xDF,
-
-	0x48, 0x37, 0x48, 0xDF,
-	0x58, 0x3F, 0x58, 0xDF,
-
-	0x68, 0x3D, 0x68, 0xDF,
-	0x49, 0x37, 0x49, 0xDF,
-
-	0x32, 0x32, 0x2D, 0xDF,
-	0x22, 0x22, 0x2D, 0xDF,
-
-	0x12, 0x12, 0x2D, 0xDF,
-	0x3A, 0x3A, 0x2D, 0xDF,
-
-	0x0F, 0xCF, 0x74, 0xC2,
-	0x37, 0xCF, 0x74, 0xC4,
-
-	0x0A, 0x44, 0x54, 0xB0,
-	0x02, 0x44, 0x64, 0xB0,
-
-	0x3D, 0xCF, 0x74, 0xC0,
-	0x34, 0x37, 0x20, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x38, 0x0F, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3C, 0x3D, 0x20, 0xE9,
-
-	0x2A, 0x44, 0x54, 0xB2,
-	0x1A, 0x44, 0x64, 0xB2,
-
-	0x31, 0x80, 0x3A, 0xEA,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x0F, 0xCF, 0x75, 0xC0,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x32, 0x31, 0x5F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x33, 0x39, 0x5F, 0xE9,
-
-	0x3D, 0xCF, 0x75, 0xC2,
-	0x37, 0xCF, 0x75, 0xC4,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0xA6, 0x0F, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0xA3, 0x3D, 0x20, 0xE9,
-
-	0x2A, 0x44, 0x54, 0xB4,
-	0x1A, 0x44, 0x64, 0xB4,
-
-	0x0A, 0x45, 0x55, 0xB0,
-	0x02, 0x45, 0x65, 0xB0,
-
-	0x88, 0x73, 0x5E, 0xE9,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0xA0, 0x37, 0x20, 0xE9,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x3E, 0x30, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3F, 0x38, 0x4F, 0xE9,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x3A, 0x31, 0x4F, 0xE9,
-
-	0x2A, 0x45, 0x55, 0xB2,
-	0x1A, 0x45, 0x65, 0xB2,
-
-	0x0A, 0x45, 0x55, 0xB4,
-	0x02, 0x45, 0x65, 0xB4,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x3B, 0x39, 0x4F, 0xE9,
-
-	0x2A, 0x20,
-	0x1A, 0x20,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x2A, 0x46, 0x56, 0xBF,
-	0x1A, 0x46, 0x66, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x36, 0x31, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x37, 0x39, 0x4F, 0xE9,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0xA7, 0x30, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0xA8, 0x38, 0x4F, 0xE9,
-
-	0x0A, 0x47, 0x57, 0xBF,
-	0x02, 0x47, 0x67, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0xA4, 0x31, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0xA5, 0x39, 0x4F, 0xE9,
-
-	0x2A, 0x43, 0x53, 0xBF,
-	0x1A, 0x43, 0x63, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0xA1, 0x30, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0xA2, 0x38, 0x4F, 0xE9,
-
-	0x0A, 0x48, 0x58, 0xBF,
-	0x02, 0x48, 0x68, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x80, 0x31, 0x57, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x81, 0x39, 0x57, 0xE9,
-
-	0x2A, 0x49, 0x59, 0xBF,
-	0x1A, 0x49, 0x69, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x82, 0x30, 0x57, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x83, 0x38, 0x57, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x84, 0x31, 0x5E, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x85, 0x39, 0x5E, 0xE9,
-
-	0x86, 0x76, 0x57, 0xE9,
-	0x8A, 0x36, 0x20, 0xE9,
-
-	0x87, 0x77, 0x57, 0xE9,
-	0x8B, 0x3E, 0xBF, 0xEA,
-
-	0x80, 0x30, 0x57, 0xE9,
-	0x81, 0x38, 0x57, 0xE9,
-
-	0x82, 0x31, 0x57, 0xE9,
-	0x86, 0x78, 0x57, 0xE9,
-
-	0x83, 0x39, 0x57, 0xE9,
-	0x87, 0x79, 0x57, 0xE9,
-
-	0x30, 0x1F, 0x5F, 0xE9,
-	0x8A, 0x34, 0x20, 0xE9,
-
-	0x8B, 0x3C, 0x20, 0xE9,
-	0x37, 0x50, 0x60, 0xBD,
-
-	0x57, 0x0D, 0x20, 0xE9,
-	0x35, 0x51, 0x61, 0xBD,
-
-	0x2B, 0x50, 0x20, 0xE9,
-	0x1D, 0x37, 0xE1, 0xEA,
-
-	0x1E, 0x35, 0xE1, 0xEA,
-	0x00, 0xE0,
-	0x0E, 0x77,
-
-	0x24, 0x51, 0x20, 0xE9,
-	0x92, 0xFF, 0x20, 0xEA,
-
-	0x16, 0x0E, 0x20, 0xE9,
-	0x57, 0x2E, 0xBF, 0xEA,
-
-	0x0B, 0x46, 0xA0, 0xE8,
-	0x1B, 0x56, 0xA0, 0xE8,
-
-	0x2B, 0x66, 0xA0, 0xE8,
-	0x0C, 0x47, 0xA0, 0xE8,
-
-	0x1C, 0x57, 0xA0, 0xE8,
-	0x2C, 0x67, 0xA0, 0xE8,
-
-	0x0B, 0x00,
-	0x1B, 0x00,
-	0x2B, 0x00,
-	0x00, 0xE0,
-
-	0x0C, 0x00,
-	0x1C, 0x00,
-	0x2C, 0x00,
-	0x00, 0xE0,
-
-	0x0B, 0x65,
-	0x1B, 0x65,
-	0x2B, 0x65,
-	0x00, 0xE0,
-
-	0x0C, 0x65,
-	0x1C, 0x65,
-	0x2C, 0x65,
-	0x00, 0xE0,
-
-	0x0B, 0x1B, 0x60, 0xEC,
-	0x36, 0xD7, 0x36, 0xAD,
-
-	0x2B, 0x80, 0x60, 0xEC,
-	0x0C, 0x1C, 0x60, 0xEC,
-
-	0x3E, 0xD7, 0x3E, 0xAD,
-	0x2C, 0x80, 0x60, 0xEC,
-
-	0x0B, 0x2B, 0xDE, 0xE8,
-	0x1B, 0x80, 0xDE, 0xE8,
-
-	0x36, 0x80, 0x36, 0xBD,
-	0x3E, 0x80, 0x3E, 0xBD,
-
-	0x33, 0xD7, 0x0B, 0xBD,
-	0x3B, 0xD7, 0x1B, 0xBD,
-
-	0x46, 0x80, 0x46, 0xCF,
-	0x57, 0x80, 0x57, 0xCF,
-
-	0x66, 0x33, 0x66, 0xCF,
-	0x47, 0x3B, 0x47, 0xCF,
-
-	0x56, 0x33, 0x56, 0xCF,
-	0x67, 0x3B, 0x67, 0xCF,
-
-	0x0B, 0x48, 0xA0, 0xE8,
-	0x1B, 0x58, 0xA0, 0xE8,
-
-	0x2B, 0x68, 0xA0, 0xE8,
-	0x0C, 0x49, 0xA0, 0xE8,
-
-	0x1C, 0x59, 0xA0, 0xE8,
-	0x2C, 0x69, 0xA0, 0xE8,
-
-	0x0B, 0x00,
-	0x1B, 0x00,
-	0x2B, 0x00,
-	0x00, 0xE0,
-
-	0x0C, 0x00,
-	0x1C, 0x00,
-	0x2C, 0x00,
-	0x00, 0xE0,
-
-	0x0B, 0x65,
-	0x1B, 0x65,
-	0x2B, 0x65,
-	0x00, 0xE0,
-
-	0x0C, 0x65,
-	0x1C, 0x65,
-	0x2C, 0x65,
-	0x00, 0xE0,
-
-	0x0B, 0x1B, 0x60, 0xEC,
-	0x34, 0xD7, 0x34, 0xAD,
-
-	0x2B, 0x80, 0x60, 0xEC,
-	0x0C, 0x1C, 0x60, 0xEC,
-
-	0x3C, 0xD7, 0x3C, 0xAD,
-	0x2C, 0x80, 0x60, 0xEC,
-
-	0x0B, 0x2B, 0xDE, 0xE8,
-	0x1B, 0x80, 0xDE, 0xE8,
-
-	0x34, 0x80, 0x34, 0xBD,
-	0x3C, 0x80, 0x3C, 0xBD,
-
-	0x33, 0xD7, 0x0B, 0xBD,
-	0x3B, 0xD7, 0x1B, 0xBD,
-
-	0x48, 0x80, 0x48, 0xCF,
-	0x59, 0x80, 0x59, 0xCF,
-
-	0x68, 0x33, 0x68, 0xCF,
-	0x49, 0x3B, 0x49, 0xCF,
-
-	0xB2, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x58, 0x33, 0x58, 0xCF,
-	0x69, 0x3B, 0x69, 0xCF,
-
-	0x70, 0xFF, 0x20, 0xEA,
-	0x57, 0xC0, 0xBF, 0xEA,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_t2gzsa[] = {
-
-	0x00, 0x8A, 0x98, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x0A, 0x40, 0x50, 0xBF,
-	0x2A, 0x40, 0x60, 0xBF,
-
-	0x32, 0x41, 0x51, 0xBF,
-	0x3A, 0x41, 0x61, 0xBF,
-
-	0xC3, 0x6B,
-	0xD3, 0x6B,
-	0x00, 0x8A, 0x98, 0xE9,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x96, 0xE2,
-	0x41, 0x04,
-
-	0x7B, 0x43, 0xA0, 0xE8,
-	0x73, 0x53, 0xA0, 0xE8,
-
-	0xAD, 0xEE, 0x23, 0x9F,
-	0x00, 0xE0,
-	0x51, 0x04,
-
-	0x90, 0xE2,
-	0x61, 0x04,
-	0x31, 0x46, 0xB1, 0xE8,
-
-	0x51, 0x41, 0xE0, 0xEC,
-	0x39, 0x67, 0xB1, 0xE8,
-
-	0x00, 0x04,
-	0x46, 0xE2,
-	0x73, 0x63, 0xA0, 0xE8,
-
-	0x61, 0x41, 0xE0, 0xEC,
-	0x31, 0x00,
-	0x39, 0x00,
-
-	0x8A, 0x80, 0x15, 0xEA,
-	0x10, 0x04,
-	0x20, 0x04,
-
-	0x61, 0x51, 0xE0, 0xEC,
-	0x2F, 0x41, 0x60, 0xEA,
-
-	0x31, 0x20,
-	0x39, 0x20,
-	0x1F, 0x42, 0xA0, 0xE8,
-
-	0x2A, 0x42, 0x52, 0xBF,
-	0x0F, 0x52, 0xA0, 0xE8,
-
-	0x1A, 0x42, 0x62, 0xBF,
-	0x1E, 0x51, 0x60, 0xEA,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x0E, 0x61, 0x60, 0xEA,
-
-	0x32, 0x40, 0x50, 0xBD,
-	0x22, 0x40, 0x60, 0xBD,
-
-	0x12, 0x41, 0x51, 0xBD,
-	0x3A, 0x41, 0x61, 0xBD,
-
-	0xBF, 0x2F, 0x0E, 0xBD,
-	0x97, 0xE2,
-	0x7B, 0x72,
-
-	0x32, 0x20,
-	0x22, 0x20,
-	0x12, 0x20,
-	0x3A, 0x20,
-
-	0x35, 0x48, 0xB1, 0xE8,
-	0x3D, 0x59, 0xB1, 0xE8,
-
-	0x46, 0x31, 0x46, 0xBF,
-	0x56, 0x31, 0x56, 0xBF,
-
-	0xB3, 0xE2, 0x2D, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x66, 0x31, 0x66, 0xBF,
-	0x47, 0x39, 0x47, 0xBF,
-
-	0x57, 0x39, 0x57, 0xBF,
-	0x67, 0x39, 0x67, 0xBF,
-
-	0x7B, 0x80, 0x07, 0xEA,
-	0x24, 0x41, 0x20, 0xE9,
-
-	0x35, 0x00,
-	0x3D, 0x00,
-	0x00, 0xE0,
-	0x2D, 0x73,
-
-	0x33, 0x72,
-	0x0C, 0xE3,
-	0x8D, 0x2F, 0x1E, 0xBD,
-
-	0x43, 0x75, 0xF8, 0xEC,
-	0x35, 0x20,
-	0x3D, 0x20,
-
-	0x43, 0x43, 0x2D, 0xDF,
-	0x53, 0x53, 0x2D, 0xDF,
-
-	0xAE, 0x1E, 0x0E, 0xBD,
-	0x58, 0xE3,
-	0x33, 0x66,
-
-	0x48, 0x35, 0x48, 0xBF,
-	0x58, 0x35, 0x58, 0xBF,
-
-	0x68, 0x35, 0x68, 0xBF,
-	0x49, 0x3D, 0x49, 0xBF,
-
-	0x59, 0x3D, 0x59, 0xBF,
-	0x69, 0x3D, 0x69, 0xBF,
-
-	0x63, 0x63, 0x2D, 0xDF,
-	0x4D, 0x7D, 0xF8, 0xEC,
-
-	0x59, 0xE3,
-	0x00, 0xE0,
-	0xB8, 0x38, 0x33, 0xBF,
-
-	0x2D, 0x73,
-	0x30, 0x76,
-	0x18, 0x3A, 0x41, 0xE9,
-
-	0x3F, 0x53, 0xA0, 0xE8,
-	0x05, 0x80, 0x3D, 0xEA,
-
-	0x37, 0x43, 0xA0, 0xE8,
-	0x3D, 0x63, 0xA0, 0xE8,
-
-	0x50, 0x70, 0xF8, 0xEC,
-	0x2B, 0x50, 0x3C, 0xE9,
-
-	0x1F, 0x0F, 0xBC, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x59, 0x78, 0xF8, 0xEC,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x1E, 0x12, 0x41, 0xE9,
-	0x1A, 0x22, 0x41, 0xE9,
-
-	0x46, 0x37, 0x46, 0xDF,
-	0x56, 0x3F, 0x56, 0xDF,
-
-	0x2B, 0x40, 0x3D, 0xE9,
-	0x66, 0x3D, 0x66, 0xDF,
-
-	0x1D, 0x32, 0x41, 0xE9,
-	0x67, 0x3D, 0x67, 0xDF,
-
-	0x47, 0x37, 0x47, 0xDF,
-	0x57, 0x3F, 0x57, 0xDF,
-
-	0x2A, 0x40, 0x20, 0xE9,
-	0x59, 0x3F, 0x59, 0xDF,
-
-	0x16, 0x30, 0x20, 0xE9,
-	0x69, 0x3D, 0x69, 0xDF,
-
-	0x48, 0x37, 0x48, 0xDF,
-	0x58, 0x3F, 0x58, 0xDF,
-
-	0x68, 0x3D, 0x68, 0xDF,
-	0x49, 0x37, 0x49, 0xDF,
-
-	0x32, 0x32, 0x2D, 0xDF,
-	0x22, 0x22, 0x2D, 0xDF,
-
-	0x12, 0x12, 0x2D, 0xDF,
-	0x3A, 0x3A, 0x2D, 0xDF,
-
-	0x0F, 0xCF, 0x74, 0xC2,
-	0x37, 0xCF, 0x74, 0xC4,
-
-	0x0A, 0x44, 0x54, 0xB0,
-	0x02, 0x44, 0x64, 0xB0,
-
-	0x3D, 0xCF, 0x74, 0xC0,
-	0x34, 0x37, 0x20, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x38, 0x0F, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3C, 0x3D, 0x20, 0xE9,
-
-	0x2A, 0x44, 0x54, 0xB2,
-	0x1A, 0x44, 0x64, 0xB2,
-
-	0x36, 0x80, 0x3A, 0xEA,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x0F, 0xCF, 0x75, 0xC0,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x32, 0x31, 0x5F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x33, 0x39, 0x5F, 0xE9,
-
-	0x3D, 0xCF, 0x75, 0xC2,
-	0x37, 0xCF, 0x75, 0xC4,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0xA6, 0x0F, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0xA3, 0x3D, 0x20, 0xE9,
-
-	0x2A, 0x44, 0x54, 0xB4,
-	0x1A, 0x44, 0x64, 0xB4,
-
-	0x0A, 0x45, 0x55, 0xB0,
-	0x02, 0x45, 0x65, 0xB0,
-
-	0x88, 0x73, 0x5E, 0xE9,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0xA0, 0x37, 0x20, 0xE9,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x3E, 0x30, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3F, 0x38, 0x4F, 0xE9,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x3A, 0x31, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x3B, 0x39, 0x4F, 0xE9,
-
-	0x2A, 0x45, 0x55, 0xB2,
-	0x1A, 0x45, 0x65, 0xB2,
-
-	0x0A, 0x45, 0x55, 0xB4,
-	0x02, 0x45, 0x65, 0xB4,
-
-	0x0F, 0xCF, 0x74, 0xC6,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0xA7, 0x30, 0x4F, 0xE9,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x9C, 0x0F, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0xA8, 0x38, 0x4F, 0xE9,
-
-	0x2A, 0x44, 0x54, 0xB6,
-	0x1A, 0x44, 0x64, 0xB6,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x36, 0x31, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x37, 0x39, 0x4F, 0xE9,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x2A, 0x46, 0x56, 0xBF,
-	0x1A, 0x46, 0x66, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0xA4, 0x31, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0xA5, 0x39, 0x4F, 0xE9,
-
-	0x0A, 0x47, 0x57, 0xBF,
-	0x02, 0x47, 0x67, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0xA1, 0x30, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0xA2, 0x38, 0x4F, 0xE9,
-
-	0x2A, 0x43, 0x53, 0xBF,
-	0x1A, 0x43, 0x63, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x9D, 0x31, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x9E, 0x39, 0x4F, 0xE9,
-
-	0x0A, 0x48, 0x58, 0xBF,
-	0x02, 0x48, 0x68, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x80, 0x31, 0x57, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x81, 0x39, 0x57, 0xE9,
-
-	0x2A, 0x49, 0x59, 0xBF,
-	0x1A, 0x49, 0x69, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x82, 0x30, 0x57, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x83, 0x38, 0x57, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x84, 0x31, 0x5E, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x85, 0x39, 0x5E, 0xE9,
-
-	0x86, 0x76, 0x57, 0xE9,
-	0x8A, 0x36, 0x20, 0xE9,
-
-	0x87, 0x77, 0x57, 0xE9,
-	0x8B, 0x3E, 0xBF, 0xEA,
-
-	0x80, 0x30, 0x57, 0xE9,
-	0x81, 0x38, 0x57, 0xE9,
-
-	0x82, 0x31, 0x57, 0xE9,
-	0x86, 0x78, 0x57, 0xE9,
-
-	0x83, 0x39, 0x57, 0xE9,
-	0x87, 0x79, 0x57, 0xE9,
-
-	0x30, 0x1F, 0x5F, 0xE9,
-	0x8A, 0x34, 0x20, 0xE9,
-
-	0x8B, 0x3C, 0x20, 0xE9,
-	0x37, 0x50, 0x60, 0xBD,
-
-	0x57, 0x0D, 0x20, 0xE9,
-	0x35, 0x51, 0x61, 0xBD,
-
-	0x2B, 0x50, 0x20, 0xE9,
-	0x1D, 0x37, 0xE1, 0xEA,
-
-	0x1E, 0x35, 0xE1, 0xEA,
-	0x00, 0xE0,
-	0x0E, 0x77,
-
-	0x24, 0x51, 0x20, 0xE9,
-	0x8D, 0xFF, 0x20, 0xEA,
-
-	0x16, 0x0E, 0x20, 0xE9,
-	0x57, 0x2E, 0xBF, 0xEA,
-
-	0x0B, 0x46, 0xA0, 0xE8,
-	0x1B, 0x56, 0xA0, 0xE8,
-
-	0x2B, 0x66, 0xA0, 0xE8,
-	0x0C, 0x47, 0xA0, 0xE8,
-
-	0x1C, 0x57, 0xA0, 0xE8,
-	0x2C, 0x67, 0xA0, 0xE8,
-
-	0x0B, 0x00,
-	0x1B, 0x00,
-	0x2B, 0x00,
-	0x00, 0xE0,
-
-	0x0C, 0x00,
-	0x1C, 0x00,
-	0x2C, 0x00,
-	0x00, 0xE0,
-
-	0x0B, 0x65,
-	0x1B, 0x65,
-	0x2B, 0x65,
-	0x00, 0xE0,
-
-	0x0C, 0x65,
-	0x1C, 0x65,
-	0x2C, 0x65,
-	0x00, 0xE0,
-
-	0x0B, 0x1B, 0x60, 0xEC,
-	0x36, 0xD7, 0x36, 0xAD,
-
-	0x2B, 0x80, 0x60, 0xEC,
-	0x0C, 0x1C, 0x60, 0xEC,
-
-	0x3E, 0xD7, 0x3E, 0xAD,
-	0x2C, 0x80, 0x60, 0xEC,
-
-	0x0B, 0x2B, 0xDE, 0xE8,
-	0x1B, 0x80, 0xDE, 0xE8,
-
-	0x36, 0x80, 0x36, 0xBD,
-	0x3E, 0x80, 0x3E, 0xBD,
-
-	0x33, 0xD7, 0x0B, 0xBD,
-	0x3B, 0xD7, 0x1B, 0xBD,
-
-	0x46, 0x80, 0x46, 0xCF,
-	0x57, 0x80, 0x57, 0xCF,
-
-	0x66, 0x33, 0x66, 0xCF,
-	0x47, 0x3B, 0x47, 0xCF,
-
-	0x56, 0x33, 0x56, 0xCF,
-	0x67, 0x3B, 0x67, 0xCF,
-
-	0x0B, 0x48, 0xA0, 0xE8,
-	0x1B, 0x58, 0xA0, 0xE8,
-
-	0x2B, 0x68, 0xA0, 0xE8,
-	0x0C, 0x49, 0xA0, 0xE8,
-
-	0x1C, 0x59, 0xA0, 0xE8,
-	0x2C, 0x69, 0xA0, 0xE8,
-
-	0x0B, 0x00,
-	0x1B, 0x00,
-	0x2B, 0x00,
-	0x00, 0xE0,
-
-	0x0C, 0x00,
-	0x1C, 0x00,
-	0x2C, 0x00,
-	0x00, 0xE0,
-
-	0x0B, 0x65,
-	0x1B, 0x65,
-	0x2B, 0x65,
-	0x00, 0xE0,
-
-	0x0C, 0x65,
-	0x1C, 0x65,
-	0x2C, 0x65,
-	0x00, 0xE0,
-
-	0x0B, 0x1B, 0x60, 0xEC,
-	0x34, 0xD7, 0x34, 0xAD,
-
-	0x2B, 0x80, 0x60, 0xEC,
-	0x0C, 0x1C, 0x60, 0xEC,
-
-	0x3C, 0xD7, 0x3C, 0xAD,
-	0x2C, 0x80, 0x60, 0xEC,
-
-	0x0B, 0x2B, 0xDE, 0xE8,
-	0x1B, 0x80, 0xDE, 0xE8,
-
-	0x34, 0x80, 0x34, 0xBD,
-	0x3C, 0x80, 0x3C, 0xBD,
-
-	0x33, 0xD7, 0x0B, 0xBD,
-	0x3B, 0xD7, 0x1B, 0xBD,
-
-	0x48, 0x80, 0x48, 0xCF,
-	0x59, 0x80, 0x59, 0xCF,
-
-	0x68, 0x33, 0x68, 0xCF,
-	0x49, 0x3B, 0x49, 0xCF,
-
-	0xAD, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x58, 0x33, 0x58, 0xCF,
-	0x69, 0x3B, 0x69, 0xCF,
-
-	0x6B, 0xFF, 0x20, 0xEA,
-	0x57, 0xC0, 0xBF, 0xEA,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_t2gzsaf[] = {
-
-	0x00, 0x8A, 0x98, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x0A, 0x40, 0x50, 0xBF,
-	0x2A, 0x40, 0x60, 0xBF,
-
-	0x32, 0x41, 0x51, 0xBF,
-	0x3A, 0x41, 0x61, 0xBF,
-
-	0xC3, 0x6B,
-	0xD3, 0x6B,
-	0x00, 0x8A, 0x98, 0xE9,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x96, 0xE2,
-	0x41, 0x04,
-
-	0x7B, 0x43, 0xA0, 0xE8,
-	0x73, 0x53, 0xA0, 0xE8,
-
-	0xAD, 0xEE, 0x23, 0x9F,
-	0x00, 0xE0,
-	0x51, 0x04,
-
-	0x90, 0xE2,
-	0x61, 0x04,
-	0x31, 0x46, 0xB1, 0xE8,
-
-	0x51, 0x41, 0xE0, 0xEC,
-	0x39, 0x67, 0xB1, 0xE8,
-
-	0x00, 0x04,
-	0x46, 0xE2,
-	0x73, 0x63, 0xA0, 0xE8,
-
-	0x61, 0x41, 0xE0, 0xEC,
-	0x31, 0x00,
-	0x39, 0x00,
-
-	0x8E, 0x80, 0x15, 0xEA,
-	0x10, 0x04,
-	0x20, 0x04,
-
-	0x61, 0x51, 0xE0, 0xEC,
-	0x2F, 0x41, 0x60, 0xEA,
-
-	0x31, 0x20,
-	0x39, 0x20,
-	0x1F, 0x42, 0xA0, 0xE8,
-
-	0x2A, 0x42, 0x52, 0xBF,
-	0x0F, 0x52, 0xA0, 0xE8,
-
-	0x1A, 0x42, 0x62, 0xBF,
-	0x1E, 0x51, 0x60, 0xEA,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x0E, 0x61, 0x60, 0xEA,
-
-	0x32, 0x40, 0x50, 0xBD,
-	0x22, 0x40, 0x60, 0xBD,
-
-	0x12, 0x41, 0x51, 0xBD,
-	0x3A, 0x41, 0x61, 0xBD,
-
-	0xBF, 0x2F, 0x0E, 0xBD,
-	0x97, 0xE2,
-	0x7B, 0x72,
-
-	0x32, 0x20,
-	0x22, 0x20,
-	0x12, 0x20,
-	0x3A, 0x20,
-
-	0x35, 0x48, 0xB1, 0xE8,
-	0x3D, 0x59, 0xB1, 0xE8,
-
-	0x46, 0x31, 0x46, 0xBF,
-	0x56, 0x31, 0x56, 0xBF,
-
-	0xB3, 0xE2, 0x2D, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x66, 0x31, 0x66, 0xBF,
-	0x47, 0x39, 0x47, 0xBF,
-
-	0x57, 0x39, 0x57, 0xBF,
-	0x67, 0x39, 0x67, 0xBF,
-
-	0x7F, 0x80, 0x07, 0xEA,
-	0x24, 0x41, 0x20, 0xE9,
-
-	0x35, 0x00,
-	0x3D, 0x00,
-	0x00, 0xE0,
-	0x2D, 0x73,
-
-	0x33, 0x72,
-	0x0C, 0xE3,
-	0x8D, 0x2F, 0x1E, 0xBD,
-
-	0x43, 0x75, 0xF8, 0xEC,
-	0x35, 0x20,
-	0x3D, 0x20,
-
-	0x43, 0x43, 0x2D, 0xDF,
-	0x53, 0x53, 0x2D, 0xDF,
-
-	0xAE, 0x1E, 0x0E, 0xBD,
-	0x58, 0xE3,
-	0x33, 0x66,
-
-	0x48, 0x35, 0x48, 0xBF,
-	0x58, 0x35, 0x58, 0xBF,
-
-	0x68, 0x35, 0x68, 0xBF,
-	0x49, 0x3D, 0x49, 0xBF,
-
-	0x59, 0x3D, 0x59, 0xBF,
-	0x69, 0x3D, 0x69, 0xBF,
-
-	0x63, 0x63, 0x2D, 0xDF,
-	0x4D, 0x7D, 0xF8, 0xEC,
-
-	0x59, 0xE3,
-	0x00, 0xE0,
-	0xB8, 0x38, 0x33, 0xBF,
-
-	0x2D, 0x73,
-	0x30, 0x76,
-	0x18, 0x3A, 0x41, 0xE9,
-
-	0x3F, 0x53, 0xA0, 0xE8,
-	0x05, 0x80, 0x3D, 0xEA,
-
-	0x37, 0x43, 0xA0, 0xE8,
-	0x3D, 0x63, 0xA0, 0xE8,
-
-	0x50, 0x70, 0xF8, 0xEC,
-	0x2B, 0x50, 0x3C, 0xE9,
-
-	0x1F, 0x0F, 0xBC, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x59, 0x78, 0xF8, 0xEC,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x1E, 0x12, 0x41, 0xE9,
-	0x1A, 0x22, 0x41, 0xE9,
-
-	0x46, 0x37, 0x46, 0xDF,
-	0x56, 0x3F, 0x56, 0xDF,
-
-	0x2B, 0x40, 0x3D, 0xE9,
-	0x66, 0x3D, 0x66, 0xDF,
-
-	0x1D, 0x32, 0x41, 0xE9,
-	0x67, 0x3D, 0x67, 0xDF,
-
-	0x47, 0x37, 0x47, 0xDF,
-	0x57, 0x3F, 0x57, 0xDF,
-
-	0x2A, 0x40, 0x20, 0xE9,
-	0x59, 0x3F, 0x59, 0xDF,
-
-	0x16, 0x30, 0x20, 0xE9,
-	0x69, 0x3D, 0x69, 0xDF,
-
-	0x48, 0x37, 0x48, 0xDF,
-	0x58, 0x3F, 0x58, 0xDF,
-
-	0x68, 0x3D, 0x68, 0xDF,
-	0x49, 0x37, 0x49, 0xDF,
-
-	0x32, 0x32, 0x2D, 0xDF,
-	0x22, 0x22, 0x2D, 0xDF,
-
-	0x12, 0x12, 0x2D, 0xDF,
-	0x3A, 0x3A, 0x2D, 0xDF,
-
-	0x0F, 0xCF, 0x74, 0xC2,
-	0x37, 0xCF, 0x74, 0xC4,
-
-	0x0A, 0x44, 0x54, 0xB0,
-	0x02, 0x44, 0x64, 0xB0,
-
-	0x3D, 0xCF, 0x74, 0xC0,
-	0x34, 0x37, 0x20, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x38, 0x0F, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3C, 0x3D, 0x20, 0xE9,
-
-	0x2A, 0x44, 0x54, 0xB2,
-	0x1A, 0x44, 0x64, 0xB2,
-
-	0x3A, 0x80, 0x3A, 0xEA,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x0F, 0xCF, 0x75, 0xC0,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x32, 0x31, 0x5F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x33, 0x39, 0x5F, 0xE9,
-
-	0x3D, 0xCF, 0x75, 0xC2,
-	0x37, 0xCF, 0x75, 0xC4,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0xA6, 0x0F, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0xA3, 0x3D, 0x20, 0xE9,
-
-	0x2A, 0x44, 0x54, 0xB4,
-	0x1A, 0x44, 0x64, 0xB4,
-
-	0x0A, 0x45, 0x55, 0xB0,
-	0x02, 0x45, 0x65, 0xB0,
-
-	0x88, 0x73, 0x5E, 0xE9,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0xA0, 0x37, 0x20, 0xE9,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x3E, 0x30, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3F, 0x38, 0x4F, 0xE9,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x3A, 0x31, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x3B, 0x39, 0x4F, 0xE9,
-
-	0x2A, 0x45, 0x55, 0xB2,
-	0x1A, 0x45, 0x65, 0xB2,
-
-	0x0A, 0x45, 0x55, 0xB4,
-	0x02, 0x45, 0x65, 0xB4,
-
-	0x0F, 0xCF, 0x74, 0xC6,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0xA7, 0x30, 0x4F, 0xE9,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x9C, 0x0F, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0xA8, 0x38, 0x4F, 0xE9,
-
-	0x2A, 0x44, 0x54, 0xB6,
-	0x1A, 0x44, 0x64, 0xB6,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x36, 0x31, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x37, 0x39, 0x4F, 0xE9,
-
-	0x0A, 0x45, 0x55, 0xB6,
-	0x02, 0x45, 0x65, 0xB6,
-
-	0x3D, 0xCF, 0x75, 0xC6,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x2A, 0x46, 0x56, 0xBF,
-	0x1A, 0x46, 0x66, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0xA4, 0x31, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0xA5, 0x39, 0x4F, 0xE9,
-
-	0x31, 0x3D, 0x20, 0xE9,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x0A, 0x47, 0x57, 0xBF,
-	0x02, 0x47, 0x67, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0xA1, 0x30, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0xA2, 0x38, 0x4F, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x9D, 0x31, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x9E, 0x39, 0x4F, 0xE9,
-
-	0x2A, 0x43, 0x53, 0xBF,
-	0x1A, 0x43, 0x63, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x35, 0x30, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x39, 0x38, 0x4F, 0xE9,
-
-	0x0A, 0x48, 0x58, 0xBF,
-	0x02, 0x48, 0x68, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x80, 0x31, 0x57, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x81, 0x39, 0x57, 0xE9,
-
-	0x2A, 0x49, 0x59, 0xBF,
-	0x1A, 0x49, 0x69, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x82, 0x30, 0x57, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x83, 0x38, 0x57, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x84, 0x31, 0x5E, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x85, 0x39, 0x5E, 0xE9,
-
-	0x86, 0x76, 0x57, 0xE9,
-	0x8A, 0x36, 0x20, 0xE9,
-
-	0x87, 0x77, 0x57, 0xE9,
-	0x8B, 0x3E, 0xBF, 0xEA,
-
-	0x80, 0x30, 0x57, 0xE9,
-	0x81, 0x38, 0x57, 0xE9,
-
-	0x82, 0x31, 0x57, 0xE9,
-	0x86, 0x78, 0x57, 0xE9,
-
-	0x83, 0x39, 0x57, 0xE9,
-	0x87, 0x79, 0x57, 0xE9,
-
-	0x30, 0x1F, 0x5F, 0xE9,
-	0x8A, 0x34, 0x20, 0xE9,
-
-	0x8B, 0x3C, 0x20, 0xE9,
-	0x37, 0x50, 0x60, 0xBD,
-
-	0x57, 0x0D, 0x20, 0xE9,
-	0x35, 0x51, 0x61, 0xBD,
-
-	0x2B, 0x50, 0x20, 0xE9,
-	0x1D, 0x37, 0xE1, 0xEA,
-
-	0x1E, 0x35, 0xE1, 0xEA,
-	0x00, 0xE0,
-	0x0E, 0x77,
-
-	0x24, 0x51, 0x20, 0xE9,
-	0x89, 0xFF, 0x20, 0xEA,
-
-	0x16, 0x0E, 0x20, 0xE9,
-	0x57, 0x2E, 0xBF, 0xEA,
-
-	0x0B, 0x46, 0xA0, 0xE8,
-	0x1B, 0x56, 0xA0, 0xE8,
-
-	0x2B, 0x66, 0xA0, 0xE8,
-	0x0C, 0x47, 0xA0, 0xE8,
-
-	0x1C, 0x57, 0xA0, 0xE8,
-	0x2C, 0x67, 0xA0, 0xE8,
-
-	0x0B, 0x00,
-	0x1B, 0x00,
-	0x2B, 0x00,
-	0x00, 0xE0,
-
-	0x0C, 0x00,
-	0x1C, 0x00,
-	0x2C, 0x00,
-	0x00, 0xE0,
-
-	0x0B, 0x65,
-	0x1B, 0x65,
-	0x2B, 0x65,
-	0x00, 0xE0,
-
-	0x0C, 0x65,
-	0x1C, 0x65,
-	0x2C, 0x65,
-	0x00, 0xE0,
-
-	0x0B, 0x1B, 0x60, 0xEC,
-	0x36, 0xD7, 0x36, 0xAD,
-
-	0x2B, 0x80, 0x60, 0xEC,
-	0x0C, 0x1C, 0x60, 0xEC,
-
-	0x3E, 0xD7, 0x3E, 0xAD,
-	0x2C, 0x80, 0x60, 0xEC,
-
-	0x0B, 0x2B, 0xDE, 0xE8,
-	0x1B, 0x80, 0xDE, 0xE8,
-
-	0x36, 0x80, 0x36, 0xBD,
-	0x3E, 0x80, 0x3E, 0xBD,
-
-	0x33, 0xD7, 0x0B, 0xBD,
-	0x3B, 0xD7, 0x1B, 0xBD,
-
-	0x46, 0x80, 0x46, 0xCF,
-	0x57, 0x80, 0x57, 0xCF,
-
-	0x66, 0x33, 0x66, 0xCF,
-	0x47, 0x3B, 0x47, 0xCF,
-
-	0x56, 0x33, 0x56, 0xCF,
-	0x67, 0x3B, 0x67, 0xCF,
-
-	0x0B, 0x48, 0xA0, 0xE8,
-	0x1B, 0x58, 0xA0, 0xE8,
-
-	0x2B, 0x68, 0xA0, 0xE8,
-	0x0C, 0x49, 0xA0, 0xE8,
-
-	0x1C, 0x59, 0xA0, 0xE8,
-	0x2C, 0x69, 0xA0, 0xE8,
-
-	0x0B, 0x00,
-	0x1B, 0x00,
-	0x2B, 0x00,
-	0x00, 0xE0,
-
-	0x0C, 0x00,
-	0x1C, 0x00,
-	0x2C, 0x00,
-	0x00, 0xE0,
-
-	0x0B, 0x65,
-	0x1B, 0x65,
-	0x2B, 0x65,
-	0x00, 0xE0,
-
-	0x0C, 0x65,
-	0x1C, 0x65,
-	0x2C, 0x65,
-	0x00, 0xE0,
-
-	0x0B, 0x1B, 0x60, 0xEC,
-	0x34, 0xD7, 0x34, 0xAD,
-
-	0x2B, 0x80, 0x60, 0xEC,
-	0x0C, 0x1C, 0x60, 0xEC,
-
-	0x3C, 0xD7, 0x3C, 0xAD,
-	0x2C, 0x80, 0x60, 0xEC,
-
-	0x0B, 0x2B, 0xDE, 0xE8,
-	0x1B, 0x80, 0xDE, 0xE8,
-
-	0x34, 0x80, 0x34, 0xBD,
-	0x3C, 0x80, 0x3C, 0xBD,
-
-	0x33, 0xD7, 0x0B, 0xBD,
-	0x3B, 0xD7, 0x1B, 0xBD,
-
-	0x48, 0x80, 0x48, 0xCF,
-	0x59, 0x80, 0x59, 0xCF,
-
-	0x68, 0x33, 0x68, 0xCF,
-	0x49, 0x3B, 0x49, 0xCF,
-
-	0xA9, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x58, 0x33, 0x58, 0xCF,
-	0x69, 0x3B, 0x69, 0xCF,
-
-	0x67, 0xFF, 0x20, 0xEA,
-	0x57, 0xC0, 0xBF, 0xEA,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_t2gzsf[] = {
-
-	0x00, 0x8A, 0x98, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x0A, 0x40, 0x50, 0xBF,
-	0x2A, 0x40, 0x60, 0xBF,
-
-	0x32, 0x41, 0x51, 0xBF,
-	0x3A, 0x41, 0x61, 0xBF,
-
-	0xC3, 0x6B,
-	0xD3, 0x6B,
-	0x00, 0x8A, 0x98, 0xE9,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x96, 0xE2,
-	0x41, 0x04,
-
-	0x7B, 0x43, 0xA0, 0xE8,
-	0x73, 0x53, 0xA0, 0xE8,
-
-	0xAD, 0xEE, 0x23, 0x9F,
-	0x00, 0xE0,
-	0x51, 0x04,
-
-	0x90, 0xE2,
-	0x61, 0x04,
-	0x31, 0x46, 0xB1, 0xE8,
-
-	0x51, 0x41, 0xE0, 0xEC,
-	0x39, 0x67, 0xB1, 0xE8,
-
-	0x00, 0x04,
-	0x46, 0xE2,
-	0x73, 0x63, 0xA0, 0xE8,
-
-	0x61, 0x41, 0xE0, 0xEC,
-	0x31, 0x00,
-	0x39, 0x00,
-
-	0x8A, 0x80, 0x15, 0xEA,
-	0x10, 0x04,
-	0x20, 0x04,
-
-	0x61, 0x51, 0xE0, 0xEC,
-	0x2F, 0x41, 0x60, 0xEA,
-
-	0x31, 0x20,
-	0x39, 0x20,
-	0x1F, 0x42, 0xA0, 0xE8,
-
-	0x2A, 0x42, 0x52, 0xBF,
-	0x0F, 0x52, 0xA0, 0xE8,
-
-	0x1A, 0x42, 0x62, 0xBF,
-	0x1E, 0x51, 0x60, 0xEA,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x0E, 0x61, 0x60, 0xEA,
-
-	0x32, 0x40, 0x50, 0xBD,
-	0x22, 0x40, 0x60, 0xBD,
-
-	0x12, 0x41, 0x51, 0xBD,
-	0x3A, 0x41, 0x61, 0xBD,
-
-	0xBF, 0x2F, 0x0E, 0xBD,
-	0x97, 0xE2,
-	0x7B, 0x72,
-
-	0x32, 0x20,
-	0x22, 0x20,
-	0x12, 0x20,
-	0x3A, 0x20,
-
-	0x35, 0x48, 0xB1, 0xE8,
-	0x3D, 0x59, 0xB1, 0xE8,
-
-	0x46, 0x31, 0x46, 0xBF,
-	0x56, 0x31, 0x56, 0xBF,
-
-	0xB3, 0xE2, 0x2D, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x66, 0x31, 0x66, 0xBF,
-	0x47, 0x39, 0x47, 0xBF,
-
-	0x57, 0x39, 0x57, 0xBF,
-	0x67, 0x39, 0x67, 0xBF,
-
-	0x7B, 0x80, 0x07, 0xEA,
-	0x24, 0x41, 0x20, 0xE9,
-
-	0x35, 0x00,
-	0x3D, 0x00,
-	0x00, 0xE0,
-	0x2D, 0x73,
-
-	0x33, 0x72,
-	0x0C, 0xE3,
-	0x8D, 0x2F, 0x1E, 0xBD,
-
-	0x43, 0x75, 0xF8, 0xEC,
-	0x35, 0x20,
-	0x3D, 0x20,
-
-	0x43, 0x43, 0x2D, 0xDF,
-	0x53, 0x53, 0x2D, 0xDF,
-
-	0xAE, 0x1E, 0x0E, 0xBD,
-	0x58, 0xE3,
-	0x33, 0x66,
-
-	0x48, 0x35, 0x48, 0xBF,
-	0x58, 0x35, 0x58, 0xBF,
-
-	0x68, 0x35, 0x68, 0xBF,
-	0x49, 0x3D, 0x49, 0xBF,
-
-	0x59, 0x3D, 0x59, 0xBF,
-	0x69, 0x3D, 0x69, 0xBF,
-
-	0x63, 0x63, 0x2D, 0xDF,
-	0x4D, 0x7D, 0xF8, 0xEC,
-
-	0x59, 0xE3,
-	0x00, 0xE0,
-	0xB8, 0x38, 0x33, 0xBF,
-
-	0x2D, 0x73,
-	0x30, 0x76,
-	0x18, 0x3A, 0x41, 0xE9,
-
-	0x3F, 0x53, 0xA0, 0xE8,
-	0x05, 0x80, 0x3D, 0xEA,
-
-	0x37, 0x43, 0xA0, 0xE8,
-	0x3D, 0x63, 0xA0, 0xE8,
-
-	0x50, 0x70, 0xF8, 0xEC,
-	0x2B, 0x50, 0x3C, 0xE9,
-
-	0x1F, 0x0F, 0xBC, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x59, 0x78, 0xF8, 0xEC,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x1E, 0x12, 0x41, 0xE9,
-	0x1A, 0x22, 0x41, 0xE9,
-
-	0x46, 0x37, 0x46, 0xDF,
-	0x56, 0x3F, 0x56, 0xDF,
-
-	0x2B, 0x40, 0x3D, 0xE9,
-	0x66, 0x3D, 0x66, 0xDF,
-
-	0x1D, 0x32, 0x41, 0xE9,
-	0x67, 0x3D, 0x67, 0xDF,
-
-	0x47, 0x37, 0x47, 0xDF,
-	0x57, 0x3F, 0x57, 0xDF,
-
-	0x2A, 0x40, 0x20, 0xE9,
-	0x59, 0x3F, 0x59, 0xDF,
-
-	0x16, 0x30, 0x20, 0xE9,
-	0x69, 0x3D, 0x69, 0xDF,
-
-	0x48, 0x37, 0x48, 0xDF,
-	0x58, 0x3F, 0x58, 0xDF,
-
-	0x68, 0x3D, 0x68, 0xDF,
-	0x49, 0x37, 0x49, 0xDF,
-
-	0x32, 0x32, 0x2D, 0xDF,
-	0x22, 0x22, 0x2D, 0xDF,
-
-	0x12, 0x12, 0x2D, 0xDF,
-	0x3A, 0x3A, 0x2D, 0xDF,
-
-	0x0F, 0xCF, 0x74, 0xC2,
-	0x37, 0xCF, 0x74, 0xC4,
-
-	0x0A, 0x44, 0x54, 0xB0,
-	0x02, 0x44, 0x64, 0xB0,
-
-	0x3D, 0xCF, 0x74, 0xC0,
-	0x34, 0x37, 0x20, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x38, 0x0F, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3C, 0x3D, 0x20, 0xE9,
-
-	0x2A, 0x44, 0x54, 0xB2,
-	0x1A, 0x44, 0x64, 0xB2,
-
-	0x36, 0x80, 0x3A, 0xEA,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x0F, 0xCF, 0x75, 0xC0,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x32, 0x31, 0x5F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x33, 0x39, 0x5F, 0xE9,
-
-	0x3D, 0xCF, 0x75, 0xC2,
-	0x37, 0xCF, 0x75, 0xC4,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0xA6, 0x0F, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0xA3, 0x3D, 0x20, 0xE9,
-
-	0x2A, 0x44, 0x54, 0xB4,
-	0x1A, 0x44, 0x64, 0xB4,
-
-	0x0A, 0x45, 0x55, 0xB0,
-	0x02, 0x45, 0x65, 0xB0,
-
-	0x88, 0x73, 0x5E, 0xE9,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0xA0, 0x37, 0x20, 0xE9,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x3E, 0x30, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3F, 0x38, 0x4F, 0xE9,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x3A, 0x31, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x3B, 0x39, 0x4F, 0xE9,
-
-	0x2A, 0x45, 0x55, 0xB2,
-	0x1A, 0x45, 0x65, 0xB2,
-
-	0x0A, 0x45, 0x55, 0xB4,
-	0x02, 0x45, 0x65, 0xB4,
-
-	0x0F, 0xCF, 0x75, 0xC6,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0xA7, 0x30, 0x4F, 0xE9,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x31, 0x0F, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0xA8, 0x38, 0x4F, 0xE9,
-
-	0x2A, 0x45, 0x55, 0xB6,
-	0x1A, 0x45, 0x65, 0xB6,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x36, 0x31, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x37, 0x39, 0x4F, 0xE9,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x2A, 0x46, 0x56, 0xBF,
-	0x1A, 0x46, 0x66, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0xA4, 0x31, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0xA5, 0x39, 0x4F, 0xE9,
-
-	0x0A, 0x47, 0x57, 0xBF,
-	0x02, 0x47, 0x67, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0xA1, 0x30, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0xA2, 0x38, 0x4F, 0xE9,
-
-	0x2A, 0x43, 0x53, 0xBF,
-	0x1A, 0x43, 0x63, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x35, 0x31, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x39, 0x39, 0x4F, 0xE9,
-
-	0x0A, 0x48, 0x58, 0xBF,
-	0x02, 0x48, 0x68, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x80, 0x31, 0x57, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x81, 0x39, 0x57, 0xE9,
-
-	0x2A, 0x49, 0x59, 0xBF,
-	0x1A, 0x49, 0x69, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x82, 0x30, 0x57, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x83, 0x38, 0x57, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x84, 0x31, 0x5E, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x85, 0x39, 0x5E, 0xE9,
-
-	0x86, 0x76, 0x57, 0xE9,
-	0x8A, 0x36, 0x20, 0xE9,
-
-	0x87, 0x77, 0x57, 0xE9,
-	0x8B, 0x3E, 0xBF, 0xEA,
-
-	0x80, 0x30, 0x57, 0xE9,
-	0x81, 0x38, 0x57, 0xE9,
-
-	0x82, 0x31, 0x57, 0xE9,
-	0x86, 0x78, 0x57, 0xE9,
-
-	0x83, 0x39, 0x57, 0xE9,
-	0x87, 0x79, 0x57, 0xE9,
-
-	0x30, 0x1F, 0x5F, 0xE9,
-	0x8A, 0x34, 0x20, 0xE9,
-
-	0x8B, 0x3C, 0x20, 0xE9,
-	0x37, 0x50, 0x60, 0xBD,
-
-	0x57, 0x0D, 0x20, 0xE9,
-	0x35, 0x51, 0x61, 0xBD,
-
-	0x2B, 0x50, 0x20, 0xE9,
-	0x1D, 0x37, 0xE1, 0xEA,
-
-	0x1E, 0x35, 0xE1, 0xEA,
-	0x00, 0xE0,
-	0x0E, 0x77,
-
-	0x24, 0x51, 0x20, 0xE9,
-	0x8D, 0xFF, 0x20, 0xEA,
-
-	0x16, 0x0E, 0x20, 0xE9,
-	0x57, 0x2E, 0xBF, 0xEA,
-
-	0x0B, 0x46, 0xA0, 0xE8,
-	0x1B, 0x56, 0xA0, 0xE8,
-
-	0x2B, 0x66, 0xA0, 0xE8,
-	0x0C, 0x47, 0xA0, 0xE8,
-
-	0x1C, 0x57, 0xA0, 0xE8,
-	0x2C, 0x67, 0xA0, 0xE8,
-
-	0x0B, 0x00,
-	0x1B, 0x00,
-	0x2B, 0x00,
-	0x00, 0xE0,
-
-	0x0C, 0x00,
-	0x1C, 0x00,
-	0x2C, 0x00,
-	0x00, 0xE0,
-
-	0x0B, 0x65,
-	0x1B, 0x65,
-	0x2B, 0x65,
-	0x00, 0xE0,
-
-	0x0C, 0x65,
-	0x1C, 0x65,
-	0x2C, 0x65,
-	0x00, 0xE0,
-
-	0x0B, 0x1B, 0x60, 0xEC,
-	0x36, 0xD7, 0x36, 0xAD,
-
-	0x2B, 0x80, 0x60, 0xEC,
-	0x0C, 0x1C, 0x60, 0xEC,
-
-	0x3E, 0xD7, 0x3E, 0xAD,
-	0x2C, 0x80, 0x60, 0xEC,
-
-	0x0B, 0x2B, 0xDE, 0xE8,
-	0x1B, 0x80, 0xDE, 0xE8,
-
-	0x36, 0x80, 0x36, 0xBD,
-	0x3E, 0x80, 0x3E, 0xBD,
-
-	0x33, 0xD7, 0x0B, 0xBD,
-	0x3B, 0xD7, 0x1B, 0xBD,
-
-	0x46, 0x80, 0x46, 0xCF,
-	0x57, 0x80, 0x57, 0xCF,
-
-	0x66, 0x33, 0x66, 0xCF,
-	0x47, 0x3B, 0x47, 0xCF,
-
-	0x56, 0x33, 0x56, 0xCF,
-	0x67, 0x3B, 0x67, 0xCF,
-
-	0x0B, 0x48, 0xA0, 0xE8,
-	0x1B, 0x58, 0xA0, 0xE8,
-
-	0x2B, 0x68, 0xA0, 0xE8,
-	0x0C, 0x49, 0xA0, 0xE8,
-
-	0x1C, 0x59, 0xA0, 0xE8,
-	0x2C, 0x69, 0xA0, 0xE8,
-
-	0x0B, 0x00,
-	0x1B, 0x00,
-	0x2B, 0x00,
-	0x00, 0xE0,
-
-	0x0C, 0x00,
-	0x1C, 0x00,
-	0x2C, 0x00,
-	0x00, 0xE0,
-
-	0x0B, 0x65,
-	0x1B, 0x65,
-	0x2B, 0x65,
-	0x00, 0xE0,
-
-	0x0C, 0x65,
-	0x1C, 0x65,
-	0x2C, 0x65,
-	0x00, 0xE0,
-
-	0x0B, 0x1B, 0x60, 0xEC,
-	0x34, 0xD7, 0x34, 0xAD,
-
-	0x2B, 0x80, 0x60, 0xEC,
-	0x0C, 0x1C, 0x60, 0xEC,
-
-	0x3C, 0xD7, 0x3C, 0xAD,
-	0x2C, 0x80, 0x60, 0xEC,
-
-	0x0B, 0x2B, 0xDE, 0xE8,
-	0x1B, 0x80, 0xDE, 0xE8,
-
-	0x34, 0x80, 0x34, 0xBD,
-	0x3C, 0x80, 0x3C, 0xBD,
-
-	0x33, 0xD7, 0x0B, 0xBD,
-	0x3B, 0xD7, 0x1B, 0xBD,
-
-	0x48, 0x80, 0x48, 0xCF,
-	0x59, 0x80, 0x59, 0xCF,
-
-	0x68, 0x33, 0x68, 0xCF,
-	0x49, 0x3B, 0x49, 0xCF,
-
-	0xAD, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x58, 0x33, 0x58, 0xCF,
-	0x69, 0x3B, 0x69, 0xCF,
-
-	0x6B, 0xFF, 0x20, 0xEA,
-	0x57, 0xC0, 0xBF, 0xEA,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_tgz[] = {
-
-	0x00, 0x88, 0x98, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x22, 0x40, 0x48, 0xBF,
-	0x2A, 0x40, 0x50, 0xBF,
-
-	0x32, 0x41, 0x49, 0xBF,
-	0x3A, 0x41, 0x51, 0xBF,
-
-	0xC3, 0x6B,
-	0xCB, 0x6B,
-	0x00, 0x88, 0x98, 0xE9,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x96, 0xE2,
-	0x41, 0x04,
-
-	0x7B, 0x43, 0xA0, 0xE8,
-	0x73, 0x4B, 0xA0, 0xE8,
-
-	0xAD, 0xEE, 0x29, 0x9F,
-	0x00, 0xE0,
-	0x49, 0x04,
-
-	0x90, 0xE2,
-	0x51, 0x04,
-	0x31, 0x46, 0xB1, 0xE8,
-
-	0x49, 0x41, 0xC0, 0xEC,
-	0x39, 0x57, 0xB1, 0xE8,
-
-	0x00, 0x04,
-	0x46, 0xE2,
-	0x73, 0x53, 0xA0, 0xE8,
-
-	0x51, 0x41, 0xC0, 0xEC,
-	0x31, 0x00,
-	0x39, 0x00,
-
-	0x58, 0x80, 0x15, 0xEA,
-	0x08, 0x04,
-	0x10, 0x04,
-
-	0x51, 0x49, 0xC0, 0xEC,
-	0x2F, 0x41, 0x60, 0xEA,
-
-	0x31, 0x20,
-	0x39, 0x20,
-	0x1F, 0x42, 0xA0, 0xE8,
-
-	0x2A, 0x42, 0x4A, 0xBF,
-	0x27, 0x4A, 0xA0, 0xE8,
-
-	0x1A, 0x42, 0x52, 0xBF,
-	0x1E, 0x49, 0x60, 0xEA,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x26, 0x51, 0x60, 0xEA,
-
-	0x32, 0x40, 0x48, 0xBD,
-	0x22, 0x40, 0x50, 0xBD,
-
-	0x12, 0x41, 0x49, 0xBD,
-	0x3A, 0x41, 0x51, 0xBD,
-
-	0xBF, 0x2F, 0x26, 0xBD,
-	0x00, 0xE0,
-	0x7B, 0x72,
-
-	0x32, 0x20,
-	0x22, 0x20,
-	0x12, 0x20,
-	0x3A, 0x20,
-
-	0x46, 0x31, 0x46, 0xBF,
-	0x4E, 0x31, 0x4E, 0xBF,
-
-	0xB3, 0xE2, 0x2D, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x56, 0x31, 0x56, 0xBF,
-	0x47, 0x39, 0x47, 0xBF,
-
-	0x4F, 0x39, 0x4F, 0xBF,
-	0x57, 0x39, 0x57, 0xBF,
-
-	0x4A, 0x80, 0x07, 0xEA,
-	0x24, 0x41, 0x20, 0xE9,
-
-	0x42, 0x73, 0xF8, 0xEC,
-	0x00, 0xE0,
-	0x2D, 0x73,
-
-	0x33, 0x72,
-	0x0C, 0xE3,
-	0xA5, 0x2F, 0x1E, 0xBD,
-
-	0x43, 0x43, 0x2D, 0xDF,
-	0x4B, 0x4B, 0x2D, 0xDF,
-
-	0xAE, 0x1E, 0x26, 0xBD,
-	0x58, 0xE3,
-	0x33, 0x66,
-
-	0x53, 0x53, 0x2D, 0xDF,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xB8, 0x38, 0x33, 0xBF,
-	0x00, 0xE0,
-	0x59, 0xE3,
-
-	0x1E, 0x12, 0x41, 0xE9,
-	0x1A, 0x22, 0x41, 0xE9,
-
-	0x2B, 0x40, 0x3D, 0xE9,
-	0x3F, 0x4B, 0xA0, 0xE8,
-
-	0x2D, 0x73,
-	0x30, 0x76,
-	0x05, 0x80, 0x3D, 0xEA,
-
-	0x37, 0x43, 0xA0, 0xE8,
-	0x3D, 0x53, 0xA0, 0xE8,
-
-	0x48, 0x70, 0xF8, 0xEC,
-	0x2B, 0x48, 0x3C, 0xE9,
-
-	0x1F, 0x27, 0xBC, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x18, 0x3A, 0x41, 0xE9,
-	0x1D, 0x32, 0x41, 0xE9,
-
-	0x2A, 0x40, 0x20, 0xE9,
-	0x56, 0x3D, 0x56, 0xDF,
-
-	0x46, 0x37, 0x46, 0xDF,
-	0x4E, 0x3F, 0x4E, 0xDF,
-
-	0x16, 0x30, 0x20, 0xE9,
-	0x4F, 0x3F, 0x4F, 0xDF,
-
-	0x32, 0x32, 0x2D, 0xDF,
-	0x22, 0x22, 0x2D, 0xDF,
-
-	0x12, 0x12, 0x2D, 0xDF,
-	0x3A, 0x3A, 0x2D, 0xDF,
-
-	0x47, 0x37, 0x47, 0xDF,
-	0x57, 0x3D, 0x57, 0xDF,
-
-	0x3D, 0xCF, 0x74, 0xC0,
-	0x37, 0xCF, 0x74, 0xC4,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x34, 0x80, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3C, 0x3D, 0x20, 0xE9,
-
-	0x0A, 0x44, 0x4C, 0xB0,
-	0x02, 0x44, 0x54, 0xB0,
-
-	0x2A, 0x44, 0x4C, 0xB2,
-	0x1A, 0x44, 0x54, 0xB2,
-
-	0x1D, 0x80, 0x3A, 0xEA,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x3D, 0xCF, 0x74, 0xC2,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x32, 0x31, 0x5F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x33, 0x39, 0x5F, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x2A, 0x44, 0x4C, 0xB4,
-	0x1A, 0x44, 0x54, 0xB4,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x38, 0x3D, 0x20, 0xE9,
-
-	0x88, 0x73, 0x5E, 0xE9,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x2A, 0x46, 0x4E, 0xBF,
-	0x1A, 0x46, 0x56, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x3E, 0x30, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3F, 0x38, 0x4F, 0xE9,
-
-	0x0A, 0x47, 0x4F, 0xBF,
-	0x02, 0x47, 0x57, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x3A, 0x31, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3B, 0x39, 0x4F, 0xE9,
-
-	0x2A, 0x43, 0x4B, 0xBF,
-	0x1A, 0x43, 0x53, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x36, 0x31, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x37, 0x39, 0x4F, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x80, 0x31, 0x57, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x81, 0x39, 0x57, 0xE9,
-
-	0x37, 0x48, 0x50, 0xBD,
-	0x8A, 0x36, 0x20, 0xE9,
-
-	0x86, 0x76, 0x57, 0xE9,
-	0x8B, 0x3E, 0x20, 0xE9,
-
-	0x82, 0x30, 0x57, 0xE9,
-	0x87, 0x77, 0x57, 0xE9,
-
-	0x83, 0x38, 0x57, 0xE9,
-	0x35, 0x49, 0x51, 0xBD,
-
-	0x84, 0x31, 0x5E, 0xE9,
-	0x30, 0x1F, 0x5F, 0xE9,
-
-	0x85, 0x39, 0x5E, 0xE9,
-	0x57, 0x25, 0x20, 0xE9,
-
-	0x2B, 0x48, 0x20, 0xE9,
-	0x1D, 0x37, 0xE1, 0xEA,
-
-	0x1E, 0x35, 0xE1, 0xEA,
-	0x00, 0xE0,
-	0x26, 0x77,
-
-	0x24, 0x49, 0x20, 0xE9,
-	0xAF, 0xFF, 0x20, 0xEA,
-
-	0x16, 0x26, 0x20, 0xE9,
-	0x57, 0x2E, 0xBF, 0xEA,
-
-	0x1C, 0x46, 0xA0, 0xE8,
-	0x23, 0x4E, 0xA0, 0xE8,
-
-	0x2B, 0x56, 0xA0, 0xE8,
-	0x1D, 0x47, 0xA0, 0xE8,
-
-	0x24, 0x4F, 0xA0, 0xE8,
-	0x2C, 0x57, 0xA0, 0xE8,
-
-	0x1C, 0x00,
-	0x23, 0x00,
-	0x2B, 0x00,
-	0x00, 0xE0,
-
-	0x1D, 0x00,
-	0x24, 0x00,
-	0x2C, 0x00,
-	0x00, 0xE0,
-
-	0x1C, 0x65,
-	0x23, 0x65,
-	0x2B, 0x65,
-	0x00, 0xE0,
-
-	0x1D, 0x65,
-	0x24, 0x65,
-	0x2C, 0x65,
-	0x00, 0xE0,
-
-	0x1C, 0x23, 0x60, 0xEC,
-	0x36, 0xD7, 0x36, 0xAD,
-
-	0x2B, 0x80, 0x60, 0xEC,
-	0x1D, 0x24, 0x60, 0xEC,
-
-	0x3E, 0xD7, 0x3E, 0xAD,
-	0x2C, 0x80, 0x60, 0xEC,
-
-	0x1C, 0x2B, 0xDE, 0xE8,
-	0x23, 0x80, 0xDE, 0xE8,
-
-	0x36, 0x80, 0x36, 0xBD,
-	0x3E, 0x80, 0x3E, 0xBD,
-
-	0x33, 0xD7, 0x1C, 0xBD,
-	0x3B, 0xD7, 0x23, 0xBD,
-
-	0x46, 0x80, 0x46, 0xCF,
-	0x4F, 0x80, 0x4F, 0xCF,
-
-	0x56, 0x33, 0x56, 0xCF,
-	0x47, 0x3B, 0x47, 0xCF,
-
-	0xD6, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x4E, 0x33, 0x4E, 0xCF,
-	0x57, 0x3B, 0x57, 0xCF,
-
-	0x9D, 0xFF, 0x20, 0xEA,
-	0x57, 0xC0, 0xBF, 0xEA,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_tgza[] = {
-
-	0x00, 0x88, 0x98, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x22, 0x40, 0x48, 0xBF,
-	0x2A, 0x40, 0x50, 0xBF,
-
-	0x32, 0x41, 0x49, 0xBF,
-	0x3A, 0x41, 0x51, 0xBF,
-
-	0xC3, 0x6B,
-	0xCB, 0x6B,
-	0x00, 0x88, 0x98, 0xE9,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x96, 0xE2,
-	0x41, 0x04,
-
-	0x7B, 0x43, 0xA0, 0xE8,
-	0x73, 0x4B, 0xA0, 0xE8,
-
-	0xAD, 0xEE, 0x29, 0x9F,
-	0x00, 0xE0,
-	0x49, 0x04,
-
-	0x90, 0xE2,
-	0x51, 0x04,
-	0x31, 0x46, 0xB1, 0xE8,
-
-	0x49, 0x41, 0xC0, 0xEC,
-	0x39, 0x57, 0xB1, 0xE8,
-
-	0x00, 0x04,
-	0x46, 0xE2,
-	0x73, 0x53, 0xA0, 0xE8,
-
-	0x51, 0x41, 0xC0, 0xEC,
-	0x31, 0x00,
-	0x39, 0x00,
-
-	0x5C, 0x80, 0x15, 0xEA,
-	0x08, 0x04,
-	0x10, 0x04,
-
-	0x51, 0x49, 0xC0, 0xEC,
-	0x2F, 0x41, 0x60, 0xEA,
-
-	0x31, 0x20,
-	0x39, 0x20,
-	0x1F, 0x42, 0xA0, 0xE8,
-
-	0x2A, 0x42, 0x4A, 0xBF,
-	0x27, 0x4A, 0xA0, 0xE8,
-
-	0x1A, 0x42, 0x52, 0xBF,
-	0x1E, 0x49, 0x60, 0xEA,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x26, 0x51, 0x60, 0xEA,
-
-	0x32, 0x40, 0x48, 0xBD,
-	0x22, 0x40, 0x50, 0xBD,
-
-	0x12, 0x41, 0x49, 0xBD,
-	0x3A, 0x41, 0x51, 0xBD,
-
-	0xBF, 0x2F, 0x26, 0xBD,
-	0x00, 0xE0,
-	0x7B, 0x72,
-
-	0x32, 0x20,
-	0x22, 0x20,
-	0x12, 0x20,
-	0x3A, 0x20,
-
-	0x46, 0x31, 0x46, 0xBF,
-	0x4E, 0x31, 0x4E, 0xBF,
-
-	0xB3, 0xE2, 0x2D, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x56, 0x31, 0x56, 0xBF,
-	0x47, 0x39, 0x47, 0xBF,
-
-	0x4F, 0x39, 0x4F, 0xBF,
-	0x57, 0x39, 0x57, 0xBF,
-
-	0x4E, 0x80, 0x07, 0xEA,
-	0x24, 0x41, 0x20, 0xE9,
-
-	0x42, 0x73, 0xF8, 0xEC,
-	0x00, 0xE0,
-	0x2D, 0x73,
-
-	0x33, 0x72,
-	0x0C, 0xE3,
-	0xA5, 0x2F, 0x1E, 0xBD,
-
-	0x43, 0x43, 0x2D, 0xDF,
-	0x4B, 0x4B, 0x2D, 0xDF,
-
-	0xAE, 0x1E, 0x26, 0xBD,
-	0x58, 0xE3,
-	0x33, 0x66,
-
-	0x53, 0x53, 0x2D, 0xDF,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xB8, 0x38, 0x33, 0xBF,
-	0x00, 0xE0,
-	0x59, 0xE3,
-
-	0x1E, 0x12, 0x41, 0xE9,
-	0x1A, 0x22, 0x41, 0xE9,
-
-	0x2B, 0x40, 0x3D, 0xE9,
-	0x3F, 0x4B, 0xA0, 0xE8,
-
-	0x2D, 0x73,
-	0x30, 0x76,
-	0x05, 0x80, 0x3D, 0xEA,
-
-	0x37, 0x43, 0xA0, 0xE8,
-	0x3D, 0x53, 0xA0, 0xE8,
-
-	0x48, 0x70, 0xF8, 0xEC,
-	0x2B, 0x48, 0x3C, 0xE9,
-
-	0x1F, 0x27, 0xBC, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x18, 0x3A, 0x41, 0xE9,
-	0x1D, 0x32, 0x41, 0xE9,
-
-	0x2A, 0x40, 0x20, 0xE9,
-	0x56, 0x3D, 0x56, 0xDF,
-
-	0x46, 0x37, 0x46, 0xDF,
-	0x4E, 0x3F, 0x4E, 0xDF,
-
-	0x16, 0x30, 0x20, 0xE9,
-	0x4F, 0x3F, 0x4F, 0xDF,
-
-	0x32, 0x32, 0x2D, 0xDF,
-	0x22, 0x22, 0x2D, 0xDF,
-
-	0x12, 0x12, 0x2D, 0xDF,
-	0x3A, 0x3A, 0x2D, 0xDF,
-
-	0x47, 0x37, 0x47, 0xDF,
-	0x57, 0x3D, 0x57, 0xDF,
-
-	0x3D, 0xCF, 0x74, 0xC0,
-	0x37, 0xCF, 0x74, 0xC4,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x34, 0x80, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3C, 0x3D, 0x20, 0xE9,
-
-	0x27, 0xCF, 0x74, 0xC6,
-	0x3D, 0xCF, 0x74, 0xC2,
-
-	0x0A, 0x44, 0x4C, 0xB0,
-	0x02, 0x44, 0x54, 0xB0,
-
-	0x2A, 0x44, 0x4C, 0xB2,
-	0x1A, 0x44, 0x54, 0xB2,
-
-	0x20, 0x80, 0x3A, 0xEA,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x88, 0x73, 0x5E, 0xE9,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x32, 0x31, 0x5F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x33, 0x39, 0x5F, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x9C, 0x27, 0x20, 0xE9,
-
-	0x0A, 0x44, 0x4C, 0xB4,
-	0x02, 0x44, 0x54, 0xB4,
-
-	0x2A, 0x44, 0x4C, 0xB6,
-	0x1A, 0x44, 0x54, 0xB6,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x38, 0x3D, 0x20, 0xE9,
-
-	0x0A, 0x20,
-	0x02, 0x20,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x0A, 0x47, 0x4F, 0xBF,
-	0x02, 0x47, 0x57, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x3E, 0x30, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x3F, 0x38, 0x4F, 0xE9,
-
-	0x2A, 0x46, 0x4E, 0xBF,
-	0x1A, 0x46, 0x56, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x3A, 0x31, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3B, 0x39, 0x4F, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x36, 0x30, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x37, 0x38, 0x4F, 0xE9,
-
-	0x2A, 0x43, 0x4B, 0xBF,
-	0x1A, 0x43, 0x53, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x9D, 0x31, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x9E, 0x39, 0x4F, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x80, 0x31, 0x57, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x81, 0x39, 0x57, 0xE9,
-
-	0x37, 0x48, 0x50, 0xBD,
-	0x8A, 0x36, 0x20, 0xE9,
-
-	0x86, 0x76, 0x57, 0xE9,
-	0x8B, 0x3E, 0x20, 0xE9,
-
-	0x82, 0x30, 0x57, 0xE9,
-	0x87, 0x77, 0x57, 0xE9,
-
-	0x83, 0x38, 0x57, 0xE9,
-	0x35, 0x49, 0x51, 0xBD,
-
-	0x84, 0x31, 0x5E, 0xE9,
-	0x30, 0x1F, 0x5F, 0xE9,
-
-	0x85, 0x39, 0x5E, 0xE9,
-	0x57, 0x25, 0x20, 0xE9,
-
-	0x2B, 0x48, 0x20, 0xE9,
-	0x1D, 0x37, 0xE1, 0xEA,
-
-	0x1E, 0x35, 0xE1, 0xEA,
-	0x00, 0xE0,
-	0x26, 0x77,
-
-	0x24, 0x49, 0x20, 0xE9,
-	0xAB, 0xFF, 0x20, 0xEA,
-
-	0x16, 0x26, 0x20, 0xE9,
-	0x57, 0x2E, 0xBF, 0xEA,
-
-	0x1C, 0x46, 0xA0, 0xE8,
-	0x23, 0x4E, 0xA0, 0xE8,
-
-	0x2B, 0x56, 0xA0, 0xE8,
-	0x1D, 0x47, 0xA0, 0xE8,
-
-	0x24, 0x4F, 0xA0, 0xE8,
-	0x2C, 0x57, 0xA0, 0xE8,
-
-	0x1C, 0x00,
-	0x23, 0x00,
-	0x2B, 0x00,
-	0x00, 0xE0,
-
-	0x1D, 0x00,
-	0x24, 0x00,
-	0x2C, 0x00,
-	0x00, 0xE0,
-
-	0x1C, 0x65,
-	0x23, 0x65,
-	0x2B, 0x65,
-	0x00, 0xE0,
-
-	0x1D, 0x65,
-	0x24, 0x65,
-	0x2C, 0x65,
-	0x00, 0xE0,
-
-	0x1C, 0x23, 0x60, 0xEC,
-	0x36, 0xD7, 0x36, 0xAD,
-
-	0x2B, 0x80, 0x60, 0xEC,
-	0x1D, 0x24, 0x60, 0xEC,
-
-	0x3E, 0xD7, 0x3E, 0xAD,
-	0x2C, 0x80, 0x60, 0xEC,
-
-	0x1C, 0x2B, 0xDE, 0xE8,
-	0x23, 0x80, 0xDE, 0xE8,
-
-	0x36, 0x80, 0x36, 0xBD,
-	0x3E, 0x80, 0x3E, 0xBD,
-
-	0x33, 0xD7, 0x1C, 0xBD,
-	0x3B, 0xD7, 0x23, 0xBD,
-
-	0x46, 0x80, 0x46, 0xCF,
-	0x4F, 0x80, 0x4F, 0xCF,
-
-	0x56, 0x33, 0x56, 0xCF,
-	0x47, 0x3B, 0x47, 0xCF,
-
-	0xD3, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x4E, 0x33, 0x4E, 0xCF,
-	0x57, 0x3B, 0x57, 0xCF,
-
-	0x99, 0xFF, 0x20, 0xEA,
-	0x57, 0xC0, 0xBF, 0xEA,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_tgzaf[] = {
-
-	0x00, 0x88, 0x98, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x22, 0x40, 0x48, 0xBF,
-	0x2A, 0x40, 0x50, 0xBF,
-
-	0x32, 0x41, 0x49, 0xBF,
-	0x3A, 0x41, 0x51, 0xBF,
-
-	0xC3, 0x6B,
-	0xCB, 0x6B,
-	0x00, 0x88, 0x98, 0xE9,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x96, 0xE2,
-	0x41, 0x04,
-
-	0x7B, 0x43, 0xA0, 0xE8,
-	0x73, 0x4B, 0xA0, 0xE8,
-
-	0xAD, 0xEE, 0x29, 0x9F,
-	0x00, 0xE0,
-	0x49, 0x04,
-
-	0x90, 0xE2,
-	0x51, 0x04,
-	0x31, 0x46, 0xB1, 0xE8,
-
-	0x49, 0x41, 0xC0, 0xEC,
-	0x39, 0x57, 0xB1, 0xE8,
-
-	0x00, 0x04,
-	0x46, 0xE2,
-	0x73, 0x53, 0xA0, 0xE8,
-
-	0x51, 0x41, 0xC0, 0xEC,
-	0x31, 0x00,
-	0x39, 0x00,
-
-	0x61, 0x80, 0x15, 0xEA,
-	0x08, 0x04,
-	0x10, 0x04,
-
-	0x51, 0x49, 0xC0, 0xEC,
-	0x2F, 0x41, 0x60, 0xEA,
-
-	0x31, 0x20,
-	0x39, 0x20,
-	0x1F, 0x42, 0xA0, 0xE8,
-
-	0x2A, 0x42, 0x4A, 0xBF,
-	0x27, 0x4A, 0xA0, 0xE8,
-
-	0x1A, 0x42, 0x52, 0xBF,
-	0x1E, 0x49, 0x60, 0xEA,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x26, 0x51, 0x60, 0xEA,
-
-	0x32, 0x40, 0x48, 0xBD,
-	0x22, 0x40, 0x50, 0xBD,
-
-	0x12, 0x41, 0x49, 0xBD,
-	0x3A, 0x41, 0x51, 0xBD,
-
-	0xBF, 0x2F, 0x26, 0xBD,
-	0x00, 0xE0,
-	0x7B, 0x72,
-
-	0x32, 0x20,
-	0x22, 0x20,
-	0x12, 0x20,
-	0x3A, 0x20,
-
-	0x46, 0x31, 0x46, 0xBF,
-	0x4E, 0x31, 0x4E, 0xBF,
-
-	0xB3, 0xE2, 0x2D, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x56, 0x31, 0x56, 0xBF,
-	0x47, 0x39, 0x47, 0xBF,
-
-	0x4F, 0x39, 0x4F, 0xBF,
-	0x57, 0x39, 0x57, 0xBF,
-
-	0x53, 0x80, 0x07, 0xEA,
-	0x24, 0x41, 0x20, 0xE9,
-
-	0x42, 0x73, 0xF8, 0xEC,
-	0x00, 0xE0,
-	0x2D, 0x73,
-
-	0x33, 0x72,
-	0x0C, 0xE3,
-	0xA5, 0x2F, 0x1E, 0xBD,
-
-	0x43, 0x43, 0x2D, 0xDF,
-	0x4B, 0x4B, 0x2D, 0xDF,
-
-	0xAE, 0x1E, 0x26, 0xBD,
-	0x58, 0xE3,
-	0x33, 0x66,
-
-	0x53, 0x53, 0x2D, 0xDF,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xB8, 0x38, 0x33, 0xBF,
-	0x00, 0xE0,
-	0x59, 0xE3,
-
-	0x1E, 0x12, 0x41, 0xE9,
-	0x1A, 0x22, 0x41, 0xE9,
-
-	0x2B, 0x40, 0x3D, 0xE9,
-	0x3F, 0x4B, 0xA0, 0xE8,
-
-	0x2D, 0x73,
-	0x30, 0x76,
-	0x05, 0x80, 0x3D, 0xEA,
-
-	0x37, 0x43, 0xA0, 0xE8,
-	0x3D, 0x53, 0xA0, 0xE8,
-
-	0x48, 0x70, 0xF8, 0xEC,
-	0x2B, 0x48, 0x3C, 0xE9,
-
-	0x1F, 0x27, 0xBC, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x18, 0x3A, 0x41, 0xE9,
-	0x1D, 0x32, 0x41, 0xE9,
-
-	0x2A, 0x40, 0x20, 0xE9,
-	0x56, 0x3D, 0x56, 0xDF,
-
-	0x46, 0x37, 0x46, 0xDF,
-	0x4E, 0x3F, 0x4E, 0xDF,
-
-	0x16, 0x30, 0x20, 0xE9,
-	0x4F, 0x3F, 0x4F, 0xDF,
-
-	0x32, 0x32, 0x2D, 0xDF,
-	0x22, 0x22, 0x2D, 0xDF,
-
-	0x12, 0x12, 0x2D, 0xDF,
-	0x3A, 0x3A, 0x2D, 0xDF,
-
-	0x47, 0x37, 0x47, 0xDF,
-	0x57, 0x3D, 0x57, 0xDF,
-
-	0x3D, 0xCF, 0x74, 0xC0,
-	0x37, 0xCF, 0x74, 0xC4,
-
-	0x0A, 0x44, 0x4C, 0xB0,
-	0x02, 0x44, 0x54, 0xB0,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x34, 0x37, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3C, 0x3D, 0x20, 0xE9,
-
-	0x2A, 0x44, 0x4C, 0xB2,
-	0x1A, 0x44, 0x54, 0xB2,
-
-	0x26, 0x80, 0x3A, 0xEA,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x88, 0x73, 0x5E, 0xE9,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x3D, 0xCF, 0x74, 0xC2,
-	0x27, 0xCF, 0x74, 0xC6,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x32, 0x31, 0x5F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x33, 0x39, 0x5F, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x9C, 0x27, 0x20, 0xE9,
-
-	0x0A, 0x44, 0x4C, 0xB4,
-	0x02, 0x44, 0x54, 0xB4,
-
-	0x2A, 0x44, 0x4C, 0xB6,
-	0x1A, 0x44, 0x54, 0xB6,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x38, 0x3D, 0x20, 0xE9,
-
-	0x0A, 0x20,
-	0x02, 0x20,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x3D, 0xCF, 0x75, 0xC6,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x3E, 0x30, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x3F, 0x38, 0x4F, 0xE9,
-
-	0x0A, 0x45, 0x4D, 0xB6,
-	0x02, 0x45, 0x55, 0xB6,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x3A, 0x31, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3B, 0x39, 0x4F, 0xE9,
-
-	0x31, 0x3D, 0x20, 0xE9,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x2A, 0x46, 0x4E, 0xBF,
-	0x1A, 0x46, 0x56, 0xBF,
-
-	0x0A, 0x47, 0x4F, 0xBF,
-	0x02, 0x47, 0x57, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x36, 0x30, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x37, 0x38, 0x4F, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x9D, 0x31, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x9E, 0x39, 0x4F, 0xE9,
-
-	0x2A, 0x43, 0x4B, 0xBF,
-	0x1A, 0x43, 0x53, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x35, 0x30, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x39, 0x38, 0x4F, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x80, 0x31, 0x57, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x81, 0x39, 0x57, 0xE9,
-
-	0x37, 0x48, 0x50, 0xBD,
-	0x8A, 0x36, 0x20, 0xE9,
-
-	0x86, 0x76, 0x57, 0xE9,
-	0x8B, 0x3E, 0x20, 0xE9,
-
-	0x82, 0x30, 0x57, 0xE9,
-	0x87, 0x77, 0x57, 0xE9,
-
-	0x83, 0x38, 0x57, 0xE9,
-	0x35, 0x49, 0x51, 0xBD,
-
-	0x84, 0x31, 0x5E, 0xE9,
-	0x30, 0x1F, 0x5F, 0xE9,
-
-	0x85, 0x39, 0x5E, 0xE9,
-	0x57, 0x25, 0x20, 0xE9,
-
-	0x2B, 0x48, 0x20, 0xE9,
-	0x1D, 0x37, 0xE1, 0xEA,
-
-	0x1E, 0x35, 0xE1, 0xEA,
-	0x00, 0xE0,
-	0x26, 0x77,
-
-	0x24, 0x49, 0x20, 0xE9,
-	0xA6, 0xFF, 0x20, 0xEA,
-
-	0x16, 0x26, 0x20, 0xE9,
-	0x57, 0x2E, 0xBF, 0xEA,
-
-	0x1C, 0x46, 0xA0, 0xE8,
-	0x23, 0x4E, 0xA0, 0xE8,
-
-	0x2B, 0x56, 0xA0, 0xE8,
-	0x1D, 0x47, 0xA0, 0xE8,
-
-	0x24, 0x4F, 0xA0, 0xE8,
-	0x2C, 0x57, 0xA0, 0xE8,
-
-	0x1C, 0x00,
-	0x23, 0x00,
-	0x2B, 0x00,
-	0x00, 0xE0,
-
-	0x1D, 0x00,
-	0x24, 0x00,
-	0x2C, 0x00,
-	0x00, 0xE0,
-
-	0x1C, 0x65,
-	0x23, 0x65,
-	0x2B, 0x65,
-	0x00, 0xE0,
-
-	0x1D, 0x65,
-	0x24, 0x65,
-	0x2C, 0x65,
-	0x00, 0xE0,
-
-	0x1C, 0x23, 0x60, 0xEC,
-	0x36, 0xD7, 0x36, 0xAD,
-
-	0x2B, 0x80, 0x60, 0xEC,
-	0x1D, 0x24, 0x60, 0xEC,
-
-	0x3E, 0xD7, 0x3E, 0xAD,
-	0x2C, 0x80, 0x60, 0xEC,
-
-	0x1C, 0x2B, 0xDE, 0xE8,
-	0x23, 0x80, 0xDE, 0xE8,
-
-	0x36, 0x80, 0x36, 0xBD,
-	0x3E, 0x80, 0x3E, 0xBD,
-
-	0x33, 0xD7, 0x1C, 0xBD,
-	0x3B, 0xD7, 0x23, 0xBD,
-
-	0x46, 0x80, 0x46, 0xCF,
-	0x4F, 0x80, 0x4F, 0xCF,
-
-	0x56, 0x33, 0x56, 0xCF,
-	0x47, 0x3B, 0x47, 0xCF,
-
-	0xCD, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x4E, 0x33, 0x4E, 0xCF,
-	0x57, 0x3B, 0x57, 0xCF,
-
-	0x94, 0xFF, 0x20, 0xEA,
-	0x57, 0xC0, 0xBF, 0xEA,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_tgzf[] = {
-
-	0x00, 0x88, 0x98, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x22, 0x40, 0x48, 0xBF,
-	0x2A, 0x40, 0x50, 0xBF,
-
-	0x32, 0x41, 0x49, 0xBF,
-	0x3A, 0x41, 0x51, 0xBF,
-
-	0xC3, 0x6B,
-	0xCB, 0x6B,
-	0x00, 0x88, 0x98, 0xE9,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x96, 0xE2,
-	0x41, 0x04,
-
-	0x7B, 0x43, 0xA0, 0xE8,
-	0x73, 0x4B, 0xA0, 0xE8,
-
-	0xAD, 0xEE, 0x29, 0x9F,
-	0x00, 0xE0,
-	0x49, 0x04,
-
-	0x90, 0xE2,
-	0x51, 0x04,
-	0x31, 0x46, 0xB1, 0xE8,
-
-	0x49, 0x41, 0xC0, 0xEC,
-	0x39, 0x57, 0xB1, 0xE8,
-
-	0x00, 0x04,
-	0x46, 0xE2,
-	0x73, 0x53, 0xA0, 0xE8,
-
-	0x51, 0x41, 0xC0, 0xEC,
-	0x31, 0x00,
-	0x39, 0x00,
-
-	0x5D, 0x80, 0x15, 0xEA,
-	0x08, 0x04,
-	0x10, 0x04,
-
-	0x51, 0x49, 0xC0, 0xEC,
-	0x2F, 0x41, 0x60, 0xEA,
-
-	0x31, 0x20,
-	0x39, 0x20,
-	0x1F, 0x42, 0xA0, 0xE8,
-
-	0x2A, 0x42, 0x4A, 0xBF,
-	0x27, 0x4A, 0xA0, 0xE8,
-
-	0x1A, 0x42, 0x52, 0xBF,
-	0x1E, 0x49, 0x60, 0xEA,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x26, 0x51, 0x60, 0xEA,
-
-	0x32, 0x40, 0x48, 0xBD,
-	0x22, 0x40, 0x50, 0xBD,
-
-	0x12, 0x41, 0x49, 0xBD,
-	0x3A, 0x41, 0x51, 0xBD,
-
-	0xBF, 0x2F, 0x26, 0xBD,
-	0x00, 0xE0,
-	0x7B, 0x72,
-
-	0x32, 0x20,
-	0x22, 0x20,
-	0x12, 0x20,
-	0x3A, 0x20,
-
-	0x46, 0x31, 0x46, 0xBF,
-	0x4E, 0x31, 0x4E, 0xBF,
-
-	0xB3, 0xE2, 0x2D, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x56, 0x31, 0x56, 0xBF,
-	0x47, 0x39, 0x47, 0xBF,
-
-	0x4F, 0x39, 0x4F, 0xBF,
-	0x57, 0x39, 0x57, 0xBF,
-
-	0x4F, 0x80, 0x07, 0xEA,
-	0x24, 0x41, 0x20, 0xE9,
-
-	0x42, 0x73, 0xF8, 0xEC,
-	0x00, 0xE0,
-	0x2D, 0x73,
-
-	0x33, 0x72,
-	0x0C, 0xE3,
-	0xA5, 0x2F, 0x1E, 0xBD,
-
-	0x43, 0x43, 0x2D, 0xDF,
-	0x4B, 0x4B, 0x2D, 0xDF,
-
-	0xAE, 0x1E, 0x26, 0xBD,
-	0x58, 0xE3,
-	0x33, 0x66,
-
-	0x53, 0x53, 0x2D, 0xDF,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xB8, 0x38, 0x33, 0xBF,
-	0x00, 0xE0,
-	0x59, 0xE3,
-
-	0x1E, 0x12, 0x41, 0xE9,
-	0x1A, 0x22, 0x41, 0xE9,
-
-	0x2B, 0x40, 0x3D, 0xE9,
-	0x3F, 0x4B, 0xA0, 0xE8,
-
-	0x2D, 0x73,
-	0x30, 0x76,
-	0x05, 0x80, 0x3D, 0xEA,
-
-	0x37, 0x43, 0xA0, 0xE8,
-	0x3D, 0x53, 0xA0, 0xE8,
-
-	0x48, 0x70, 0xF8, 0xEC,
-	0x2B, 0x48, 0x3C, 0xE9,
-
-	0x1F, 0x27, 0xBC, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x18, 0x3A, 0x41, 0xE9,
-	0x1D, 0x32, 0x41, 0xE9,
-
-	0x2A, 0x40, 0x20, 0xE9,
-	0x56, 0x3D, 0x56, 0xDF,
-
-	0x46, 0x37, 0x46, 0xDF,
-	0x4E, 0x3F, 0x4E, 0xDF,
-
-	0x16, 0x30, 0x20, 0xE9,
-	0x4F, 0x3F, 0x4F, 0xDF,
-
-	0x32, 0x32, 0x2D, 0xDF,
-	0x22, 0x22, 0x2D, 0xDF,
-
-	0x12, 0x12, 0x2D, 0xDF,
-	0x3A, 0x3A, 0x2D, 0xDF,
-
-	0x47, 0x37, 0x47, 0xDF,
-	0x57, 0x3D, 0x57, 0xDF,
-
-	0x3D, 0xCF, 0x74, 0xC0,
-	0x37, 0xCF, 0x74, 0xC4,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x34, 0x80, 0x20, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x88, 0x73, 0x5E, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x27, 0xCF, 0x75, 0xC6,
-	0x3C, 0x3D, 0x20, 0xE9,
-
-	0x0A, 0x44, 0x4C, 0xB0,
-	0x02, 0x44, 0x54, 0xB0,
-
-	0x2A, 0x44, 0x4C, 0xB2,
-	0x1A, 0x44, 0x54, 0xB2,
-
-	0x20, 0x80, 0x3A, 0xEA,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x3D, 0xCF, 0x74, 0xC2,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x32, 0x31, 0x5F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x33, 0x39, 0x5F, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x31, 0x27, 0x20, 0xE9,
-
-	0x0A, 0x44, 0x4C, 0xB4,
-	0x02, 0x44, 0x54, 0xB4,
-
-	0x2A, 0x45, 0x4D, 0xB6,
-	0x1A, 0x45, 0x55, 0xB6,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x38, 0x3D, 0x20, 0xE9,
-
-	0x0A, 0x20,
-	0x02, 0x20,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x0A, 0x47, 0x4F, 0xBF,
-	0x02, 0x47, 0x57, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x3E, 0x30, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x3F, 0x38, 0x4F, 0xE9,
-
-	0x2A, 0x46, 0x4E, 0xBF,
-	0x1A, 0x46, 0x56, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x3A, 0x31, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3B, 0x39, 0x4F, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x36, 0x30, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x37, 0x38, 0x4F, 0xE9,
-
-	0x2A, 0x43, 0x4B, 0xBF,
-	0x1A, 0x43, 0x53, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x35, 0x31, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x39, 0x39, 0x4F, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x80, 0x31, 0x57, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x81, 0x39, 0x57, 0xE9,
-
-	0x37, 0x48, 0x50, 0xBD,
-	0x8A, 0x36, 0x20, 0xE9,
-
-	0x86, 0x76, 0x57, 0xE9,
-	0x8B, 0x3E, 0x20, 0xE9,
-
-	0x82, 0x30, 0x57, 0xE9,
-	0x87, 0x77, 0x57, 0xE9,
-
-	0x83, 0x38, 0x57, 0xE9,
-	0x35, 0x49, 0x51, 0xBD,
-
-	0x84, 0x31, 0x5E, 0xE9,
-	0x30, 0x1F, 0x5F, 0xE9,
-
-	0x85, 0x39, 0x5E, 0xE9,
-	0x57, 0x25, 0x20, 0xE9,
-
-	0x2B, 0x48, 0x20, 0xE9,
-	0x1D, 0x37, 0xE1, 0xEA,
-
-	0x1E, 0x35, 0xE1, 0xEA,
-	0x00, 0xE0,
-	0x26, 0x77,
-
-	0x24, 0x49, 0x20, 0xE9,
-	0xAA, 0xFF, 0x20, 0xEA,
-
-	0x16, 0x26, 0x20, 0xE9,
-	0x57, 0x2E, 0xBF, 0xEA,
-
-	0x1C, 0x46, 0xA0, 0xE8,
-	0x23, 0x4E, 0xA0, 0xE8,
-
-	0x2B, 0x56, 0xA0, 0xE8,
-	0x1D, 0x47, 0xA0, 0xE8,
-
-	0x24, 0x4F, 0xA0, 0xE8,
-	0x2C, 0x57, 0xA0, 0xE8,
-
-	0x1C, 0x00,
-	0x23, 0x00,
-	0x2B, 0x00,
-	0x00, 0xE0,
-
-	0x1D, 0x00,
-	0x24, 0x00,
-	0x2C, 0x00,
-	0x00, 0xE0,
-
-	0x1C, 0x65,
-	0x23, 0x65,
-	0x2B, 0x65,
-	0x00, 0xE0,
-
-	0x1D, 0x65,
-	0x24, 0x65,
-	0x2C, 0x65,
-	0x00, 0xE0,
-
-	0x1C, 0x23, 0x60, 0xEC,
-	0x36, 0xD7, 0x36, 0xAD,
-
-	0x2B, 0x80, 0x60, 0xEC,
-	0x1D, 0x24, 0x60, 0xEC,
-
-	0x3E, 0xD7, 0x3E, 0xAD,
-	0x2C, 0x80, 0x60, 0xEC,
-
-	0x1C, 0x2B, 0xDE, 0xE8,
-	0x23, 0x80, 0xDE, 0xE8,
-
-	0x36, 0x80, 0x36, 0xBD,
-	0x3E, 0x80, 0x3E, 0xBD,
-
-	0x33, 0xD7, 0x1C, 0xBD,
-	0x3B, 0xD7, 0x23, 0xBD,
-
-	0x46, 0x80, 0x46, 0xCF,
-	0x4F, 0x80, 0x4F, 0xCF,
-
-	0x56, 0x33, 0x56, 0xCF,
-	0x47, 0x3B, 0x47, 0xCF,
-
-	0xD3, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x4E, 0x33, 0x4E, 0xCF,
-	0x57, 0x3B, 0x57, 0xCF,
-
-	0x98, 0xFF, 0x20, 0xEA,
-	0x57, 0xC0, 0xBF, 0xEA,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_tgzs[] = {
-
-	0x00, 0x88, 0x98, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x22, 0x40, 0x48, 0xBF,
-	0x2A, 0x40, 0x50, 0xBF,
-
-	0x32, 0x41, 0x49, 0xBF,
-	0x3A, 0x41, 0x51, 0xBF,
-
-	0xC3, 0x6B,
-	0xCB, 0x6B,
-	0x00, 0x88, 0x98, 0xE9,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x96, 0xE2,
-	0x41, 0x04,
-
-	0x7B, 0x43, 0xA0, 0xE8,
-	0x73, 0x4B, 0xA0, 0xE8,
-
-	0xAD, 0xEE, 0x29, 0x9F,
-	0x00, 0xE0,
-	0x49, 0x04,
-
-	0x90, 0xE2,
-	0x51, 0x04,
-	0x31, 0x46, 0xB1, 0xE8,
-
-	0x49, 0x41, 0xC0, 0xEC,
-	0x39, 0x57, 0xB1, 0xE8,
-
-	0x00, 0x04,
-	0x46, 0xE2,
-	0x73, 0x53, 0xA0, 0xE8,
-
-	0x51, 0x41, 0xC0, 0xEC,
-	0x31, 0x00,
-	0x39, 0x00,
-
-	0x65, 0x80, 0x15, 0xEA,
-	0x08, 0x04,
-	0x10, 0x04,
-
-	0x51, 0x49, 0xC0, 0xEC,
-	0x2F, 0x41, 0x60, 0xEA,
-
-	0x31, 0x20,
-	0x39, 0x20,
-	0x1F, 0x42, 0xA0, 0xE8,
-
-	0x2A, 0x42, 0x4A, 0xBF,
-	0x27, 0x4A, 0xA0, 0xE8,
-
-	0x1A, 0x42, 0x52, 0xBF,
-	0x1E, 0x49, 0x60, 0xEA,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x26, 0x51, 0x60, 0xEA,
-
-	0x32, 0x40, 0x48, 0xBD,
-	0x22, 0x40, 0x50, 0xBD,
-
-	0x12, 0x41, 0x49, 0xBD,
-	0x3A, 0x41, 0x51, 0xBD,
-
-	0xBF, 0x2F, 0x26, 0xBD,
-	0x00, 0xE0,
-	0x7B, 0x72,
-
-	0x32, 0x20,
-	0x22, 0x20,
-	0x12, 0x20,
-	0x3A, 0x20,
-
-	0x46, 0x31, 0x46, 0xBF,
-	0x4E, 0x31, 0x4E, 0xBF,
-
-	0xB3, 0xE2, 0x2D, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x56, 0x31, 0x56, 0xBF,
-	0x47, 0x39, 0x47, 0xBF,
-
-	0x4F, 0x39, 0x4F, 0xBF,
-	0x57, 0x39, 0x57, 0xBF,
-
-	0x57, 0x80, 0x07, 0xEA,
-	0x24, 0x41, 0x20, 0xE9,
-
-	0x42, 0x73, 0xF8, 0xEC,
-	0x00, 0xE0,
-	0x2D, 0x73,
-
-	0x33, 0x72,
-	0x0C, 0xE3,
-	0xA5, 0x2F, 0x1E, 0xBD,
-
-	0x43, 0x43, 0x2D, 0xDF,
-	0x4B, 0x4B, 0x2D, 0xDF,
-
-	0xAE, 0x1E, 0x26, 0xBD,
-	0x58, 0xE3,
-	0x33, 0x66,
-
-	0x53, 0x53, 0x2D, 0xDF,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xB8, 0x38, 0x33, 0xBF,
-	0x00, 0xE0,
-	0x59, 0xE3,
-
-	0x1E, 0x12, 0x41, 0xE9,
-	0x1A, 0x22, 0x41, 0xE9,
-
-	0x2B, 0x40, 0x3D, 0xE9,
-	0x3F, 0x4B, 0xA0, 0xE8,
-
-	0x2D, 0x73,
-	0x30, 0x76,
-	0x05, 0x80, 0x3D, 0xEA,
-
-	0x37, 0x43, 0xA0, 0xE8,
-	0x3D, 0x53, 0xA0, 0xE8,
-
-	0x48, 0x70, 0xF8, 0xEC,
-	0x2B, 0x48, 0x3C, 0xE9,
-
-	0x1F, 0x27, 0xBC, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x18, 0x3A, 0x41, 0xE9,
-	0x1D, 0x32, 0x41, 0xE9,
-
-	0x2A, 0x40, 0x20, 0xE9,
-	0x56, 0x3D, 0x56, 0xDF,
-
-	0x46, 0x37, 0x46, 0xDF,
-	0x4E, 0x3F, 0x4E, 0xDF,
-
-	0x16, 0x30, 0x20, 0xE9,
-	0x4F, 0x3F, 0x4F, 0xDF,
-
-	0x47, 0x37, 0x47, 0xDF,
-	0x57, 0x3D, 0x57, 0xDF,
-
-	0x32, 0x32, 0x2D, 0xDF,
-	0x22, 0x22, 0x2D, 0xDF,
-
-	0x12, 0x12, 0x2D, 0xDF,
-	0x3A, 0x3A, 0x2D, 0xDF,
-
-	0x27, 0xCF, 0x74, 0xC2,
-	0x37, 0xCF, 0x74, 0xC4,
-
-	0x0A, 0x44, 0x4C, 0xB0,
-	0x02, 0x44, 0x54, 0xB0,
-
-	0x3D, 0xCF, 0x74, 0xC0,
-	0x34, 0x37, 0x20, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x38, 0x27, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3C, 0x3D, 0x20, 0xE9,
-
-	0x2A, 0x44, 0x4C, 0xB2,
-	0x1A, 0x44, 0x54, 0xB2,
-
-	0x29, 0x80, 0x3A, 0xEA,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x27, 0xCF, 0x75, 0xC0,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x32, 0x31, 0x5F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x33, 0x39, 0x5F, 0xE9,
-
-	0x3D, 0xCF, 0x75, 0xC2,
-	0x37, 0xCF, 0x75, 0xC4,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0xA6, 0x27, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0xA3, 0x3D, 0x20, 0xE9,
-
-	0x2A, 0x44, 0x4C, 0xB4,
-	0x1A, 0x44, 0x54, 0xB4,
-
-	0x0A, 0x45, 0x4D, 0xB0,
-	0x02, 0x45, 0x55, 0xB0,
-
-	0x88, 0x73, 0x5E, 0xE9,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0xA0, 0x37, 0x20, 0xE9,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x3E, 0x30, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3F, 0x38, 0x4F, 0xE9,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x3A, 0x31, 0x4F, 0xE9,
-
-	0x2A, 0x45, 0x4D, 0xB2,
-	0x1A, 0x45, 0x55, 0xB2,
-
-	0x0A, 0x45, 0x4D, 0xB4,
-	0x02, 0x45, 0x55, 0xB4,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x3B, 0x39, 0x4F, 0xE9,
-
-	0x0A, 0x20,
-	0x02, 0x20,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x2A, 0x46, 0x4E, 0xBF,
-	0x1A, 0x46, 0x56, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x36, 0x31, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x37, 0x39, 0x4F, 0xE9,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0xA7, 0x30, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0xA8, 0x38, 0x4F, 0xE9,
-
-	0x0A, 0x47, 0x4F, 0xBF,
-	0x02, 0x47, 0x57, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0xA4, 0x31, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0xA5, 0x39, 0x4F, 0xE9,
-
-	0x2A, 0x43, 0x4B, 0xBF,
-	0x1A, 0x43, 0x53, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0xA1, 0x30, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0xA2, 0x38, 0x4F, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x80, 0x31, 0x57, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x81, 0x39, 0x57, 0xE9,
-
-	0x37, 0x48, 0x50, 0xBD,
-	0x8A, 0x36, 0x20, 0xE9,
-
-	0x86, 0x76, 0x57, 0xE9,
-	0x8B, 0x3E, 0x20, 0xE9,
-
-	0x82, 0x30, 0x57, 0xE9,
-	0x87, 0x77, 0x57, 0xE9,
-
-	0x83, 0x38, 0x57, 0xE9,
-	0x35, 0x49, 0x51, 0xBD,
-
-	0x84, 0x31, 0x5E, 0xE9,
-	0x30, 0x1F, 0x5F, 0xE9,
-
-	0x85, 0x39, 0x5E, 0xE9,
-	0x57, 0x25, 0x20, 0xE9,
-
-	0x2B, 0x48, 0x20, 0xE9,
-	0x1D, 0x37, 0xE1, 0xEA,
-
-	0x1E, 0x35, 0xE1, 0xEA,
-	0x00, 0xE0,
-	0x26, 0x77,
-
-	0x24, 0x49, 0x20, 0xE9,
-	0xA2, 0xFF, 0x20, 0xEA,
-
-	0x16, 0x26, 0x20, 0xE9,
-	0x57, 0x2E, 0xBF, 0xEA,
-
-	0x1C, 0x46, 0xA0, 0xE8,
-	0x23, 0x4E, 0xA0, 0xE8,
-
-	0x2B, 0x56, 0xA0, 0xE8,
-	0x1D, 0x47, 0xA0, 0xE8,
-
-	0x24, 0x4F, 0xA0, 0xE8,
-	0x2C, 0x57, 0xA0, 0xE8,
-
-	0x1C, 0x00,
-	0x23, 0x00,
-	0x2B, 0x00,
-	0x00, 0xE0,
-
-	0x1D, 0x00,
-	0x24, 0x00,
-	0x2C, 0x00,
-	0x00, 0xE0,
-
-	0x1C, 0x65,
-	0x23, 0x65,
-	0x2B, 0x65,
-	0x00, 0xE0,
-
-	0x1D, 0x65,
-	0x24, 0x65,
-	0x2C, 0x65,
-	0x00, 0xE0,
-
-	0x1C, 0x23, 0x60, 0xEC,
-	0x36, 0xD7, 0x36, 0xAD,
-
-	0x2B, 0x80, 0x60, 0xEC,
-	0x1D, 0x24, 0x60, 0xEC,
-
-	0x3E, 0xD7, 0x3E, 0xAD,
-	0x2C, 0x80, 0x60, 0xEC,
-
-	0x1C, 0x2B, 0xDE, 0xE8,
-	0x23, 0x80, 0xDE, 0xE8,
-
-	0x36, 0x80, 0x36, 0xBD,
-	0x3E, 0x80, 0x3E, 0xBD,
-
-	0x33, 0xD7, 0x1C, 0xBD,
-	0x3B, 0xD7, 0x23, 0xBD,
-
-	0x46, 0x80, 0x46, 0xCF,
-	0x4F, 0x80, 0x4F, 0xCF,
-
-	0x56, 0x33, 0x56, 0xCF,
-	0x47, 0x3B, 0x47, 0xCF,
-
-	0xCA, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x4E, 0x33, 0x4E, 0xCF,
-	0x57, 0x3B, 0x57, 0xCF,
-
-	0x90, 0xFF, 0x20, 0xEA,
-	0x57, 0xC0, 0xBF, 0xEA,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_tgzsa[] = {
-
-	0x00, 0x88, 0x98, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x22, 0x40, 0x48, 0xBF,
-	0x2A, 0x40, 0x50, 0xBF,
-
-	0x32, 0x41, 0x49, 0xBF,
-	0x3A, 0x41, 0x51, 0xBF,
-
-	0xC3, 0x6B,
-	0xCB, 0x6B,
-	0x00, 0x88, 0x98, 0xE9,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x96, 0xE2,
-	0x41, 0x04,
-
-	0x7B, 0x43, 0xA0, 0xE8,
-	0x73, 0x4B, 0xA0, 0xE8,
-
-	0xAD, 0xEE, 0x29, 0x9F,
-	0x00, 0xE0,
-	0x49, 0x04,
-
-	0x90, 0xE2,
-	0x51, 0x04,
-	0x31, 0x46, 0xB1, 0xE8,
-
-	0x49, 0x41, 0xC0, 0xEC,
-	0x39, 0x57, 0xB1, 0xE8,
-
-	0x00, 0x04,
-	0x46, 0xE2,
-	0x73, 0x53, 0xA0, 0xE8,
-
-	0x51, 0x41, 0xC0, 0xEC,
-	0x31, 0x00,
-	0x39, 0x00,
-
-	0x6A, 0x80, 0x15, 0xEA,
-	0x08, 0x04,
-	0x10, 0x04,
-
-	0x51, 0x49, 0xC0, 0xEC,
-	0x2F, 0x41, 0x60, 0xEA,
-
-	0x31, 0x20,
-	0x39, 0x20,
-	0x1F, 0x42, 0xA0, 0xE8,
-
-	0x2A, 0x42, 0x4A, 0xBF,
-	0x27, 0x4A, 0xA0, 0xE8,
-
-	0x1A, 0x42, 0x52, 0xBF,
-	0x1E, 0x49, 0x60, 0xEA,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x26, 0x51, 0x60, 0xEA,
-
-	0x32, 0x40, 0x48, 0xBD,
-	0x22, 0x40, 0x50, 0xBD,
-
-	0x12, 0x41, 0x49, 0xBD,
-	0x3A, 0x41, 0x51, 0xBD,
-
-	0xBF, 0x2F, 0x26, 0xBD,
-	0x00, 0xE0,
-	0x7B, 0x72,
-
-	0x32, 0x20,
-	0x22, 0x20,
-	0x12, 0x20,
-	0x3A, 0x20,
-
-	0x46, 0x31, 0x46, 0xBF,
-	0x4E, 0x31, 0x4E, 0xBF,
-
-	0xB3, 0xE2, 0x2D, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x56, 0x31, 0x56, 0xBF,
-	0x47, 0x39, 0x47, 0xBF,
-
-	0x4F, 0x39, 0x4F, 0xBF,
-	0x57, 0x39, 0x57, 0xBF,
-
-	0x5C, 0x80, 0x07, 0xEA,
-	0x24, 0x41, 0x20, 0xE9,
-
-	0x42, 0x73, 0xF8, 0xEC,
-	0x00, 0xE0,
-	0x2D, 0x73,
-
-	0x33, 0x72,
-	0x0C, 0xE3,
-	0xA5, 0x2F, 0x1E, 0xBD,
-
-	0x43, 0x43, 0x2D, 0xDF,
-	0x4B, 0x4B, 0x2D, 0xDF,
-
-	0xAE, 0x1E, 0x26, 0xBD,
-	0x58, 0xE3,
-	0x33, 0x66,
-
-	0x53, 0x53, 0x2D, 0xDF,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xB8, 0x38, 0x33, 0xBF,
-	0x00, 0xE0,
-	0x59, 0xE3,
-
-	0x1E, 0x12, 0x41, 0xE9,
-	0x1A, 0x22, 0x41, 0xE9,
-
-	0x2B, 0x40, 0x3D, 0xE9,
-	0x3F, 0x4B, 0xA0, 0xE8,
-
-	0x2D, 0x73,
-	0x30, 0x76,
-	0x05, 0x80, 0x3D, 0xEA,
-
-	0x37, 0x43, 0xA0, 0xE8,
-	0x3D, 0x53, 0xA0, 0xE8,
-
-	0x48, 0x70, 0xF8, 0xEC,
-	0x2B, 0x48, 0x3C, 0xE9,
-
-	0x1F, 0x27, 0xBC, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x18, 0x3A, 0x41, 0xE9,
-	0x1D, 0x32, 0x41, 0xE9,
-
-	0x2A, 0x40, 0x20, 0xE9,
-	0x56, 0x3D, 0x56, 0xDF,
-
-	0x46, 0x37, 0x46, 0xDF,
-	0x4E, 0x3F, 0x4E, 0xDF,
-
-	0x16, 0x30, 0x20, 0xE9,
-	0x4F, 0x3F, 0x4F, 0xDF,
-
-	0x47, 0x37, 0x47, 0xDF,
-	0x57, 0x3D, 0x57, 0xDF,
-
-	0x32, 0x32, 0x2D, 0xDF,
-	0x22, 0x22, 0x2D, 0xDF,
-
-	0x12, 0x12, 0x2D, 0xDF,
-	0x3A, 0x3A, 0x2D, 0xDF,
-
-	0x27, 0xCF, 0x74, 0xC2,
-	0x37, 0xCF, 0x74, 0xC4,
-
-	0x0A, 0x44, 0x4C, 0xB0,
-	0x02, 0x44, 0x54, 0xB0,
-
-	0x3D, 0xCF, 0x74, 0xC0,
-	0x34, 0x37, 0x20, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x38, 0x27, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3C, 0x3D, 0x20, 0xE9,
-
-	0x2A, 0x44, 0x4C, 0xB2,
-	0x1A, 0x44, 0x54, 0xB2,
-
-	0x2E, 0x80, 0x3A, 0xEA,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x27, 0xCF, 0x75, 0xC0,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x32, 0x31, 0x5F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x33, 0x39, 0x5F, 0xE9,
-
-	0x3D, 0xCF, 0x75, 0xC2,
-	0x37, 0xCF, 0x75, 0xC4,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0xA6, 0x27, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0xA3, 0x3D, 0x20, 0xE9,
-
-	0x2A, 0x44, 0x4C, 0xB4,
-	0x1A, 0x44, 0x54, 0xB4,
-
-	0x0A, 0x45, 0x4D, 0xB0,
-	0x02, 0x45, 0x55, 0xB0,
-
-	0x88, 0x73, 0x5E, 0xE9,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0xA0, 0x37, 0x20, 0xE9,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x3E, 0x30, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3F, 0x38, 0x4F, 0xE9,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x3A, 0x31, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x3B, 0x39, 0x4F, 0xE9,
-
-	0x2A, 0x45, 0x4D, 0xB2,
-	0x1A, 0x45, 0x55, 0xB2,
-
-	0x0A, 0x45, 0x4D, 0xB4,
-	0x02, 0x45, 0x55, 0xB4,
-
-	0x27, 0xCF, 0x74, 0xC6,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0xA7, 0x30, 0x4F, 0xE9,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x9C, 0x27, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0xA8, 0x38, 0x4F, 0xE9,
-
-	0x2A, 0x44, 0x4C, 0xB6,
-	0x1A, 0x44, 0x54, 0xB6,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x36, 0x31, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x37, 0x39, 0x4F, 0xE9,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x2A, 0x46, 0x4E, 0xBF,
-	0x1A, 0x46, 0x56, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0xA4, 0x31, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0xA5, 0x39, 0x4F, 0xE9,
-
-	0x0A, 0x47, 0x4F, 0xBF,
-	0x02, 0x47, 0x57, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0xA1, 0x30, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0xA2, 0x38, 0x4F, 0xE9,
-
-	0x2A, 0x43, 0x4B, 0xBF,
-	0x1A, 0x43, 0x53, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x9D, 0x31, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x9E, 0x39, 0x4F, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x80, 0x31, 0x57, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x81, 0x39, 0x57, 0xE9,
-
-	0x37, 0x48, 0x50, 0xBD,
-	0x8A, 0x36, 0x20, 0xE9,
-
-	0x86, 0x76, 0x57, 0xE9,
-	0x8B, 0x3E, 0x20, 0xE9,
-
-	0x82, 0x30, 0x57, 0xE9,
-	0x87, 0x77, 0x57, 0xE9,
-
-	0x83, 0x38, 0x57, 0xE9,
-	0x35, 0x49, 0x51, 0xBD,
-
-	0x84, 0x31, 0x5E, 0xE9,
-	0x30, 0x1F, 0x5F, 0xE9,
-
-	0x85, 0x39, 0x5E, 0xE9,
-	0x57, 0x25, 0x20, 0xE9,
-
-	0x2B, 0x48, 0x20, 0xE9,
-	0x1D, 0x37, 0xE1, 0xEA,
-
-	0x1E, 0x35, 0xE1, 0xEA,
-	0x00, 0xE0,
-	0x26, 0x77,
-
-	0x24, 0x49, 0x20, 0xE9,
-	0x9D, 0xFF, 0x20, 0xEA,
-
-	0x16, 0x26, 0x20, 0xE9,
-	0x57, 0x2E, 0xBF, 0xEA,
-
-	0x1C, 0x46, 0xA0, 0xE8,
-	0x23, 0x4E, 0xA0, 0xE8,
-
-	0x2B, 0x56, 0xA0, 0xE8,
-	0x1D, 0x47, 0xA0, 0xE8,
-
-	0x24, 0x4F, 0xA0, 0xE8,
-	0x2C, 0x57, 0xA0, 0xE8,
-
-	0x1C, 0x00,
-	0x23, 0x00,
-	0x2B, 0x00,
-	0x00, 0xE0,
-
-	0x1D, 0x00,
-	0x24, 0x00,
-	0x2C, 0x00,
-	0x00, 0xE0,
-
-	0x1C, 0x65,
-	0x23, 0x65,
-	0x2B, 0x65,
-	0x00, 0xE0,
-
-	0x1D, 0x65,
-	0x24, 0x65,
-	0x2C, 0x65,
-	0x00, 0xE0,
-
-	0x1C, 0x23, 0x60, 0xEC,
-	0x36, 0xD7, 0x36, 0xAD,
-
-	0x2B, 0x80, 0x60, 0xEC,
-	0x1D, 0x24, 0x60, 0xEC,
-
-	0x3E, 0xD7, 0x3E, 0xAD,
-	0x2C, 0x80, 0x60, 0xEC,
-
-	0x1C, 0x2B, 0xDE, 0xE8,
-	0x23, 0x80, 0xDE, 0xE8,
-
-	0x36, 0x80, 0x36, 0xBD,
-	0x3E, 0x80, 0x3E, 0xBD,
-
-	0x33, 0xD7, 0x1C, 0xBD,
-	0x3B, 0xD7, 0x23, 0xBD,
-
-	0x46, 0x80, 0x46, 0xCF,
-	0x4F, 0x80, 0x4F, 0xCF,
-
-	0x56, 0x33, 0x56, 0xCF,
-	0x47, 0x3B, 0x47, 0xCF,
-
-	0xC5, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x4E, 0x33, 0x4E, 0xCF,
-	0x57, 0x3B, 0x57, 0xCF,
-
-	0x8B, 0xFF, 0x20, 0xEA,
-	0x57, 0xC0, 0xBF, 0xEA,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_tgzsaf[] = {
-
-	0x00, 0x88, 0x98, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x22, 0x40, 0x48, 0xBF,
-	0x2A, 0x40, 0x50, 0xBF,
-
-	0x32, 0x41, 0x49, 0xBF,
-	0x3A, 0x41, 0x51, 0xBF,
-
-	0xC3, 0x6B,
-	0xCB, 0x6B,
-	0x00, 0x88, 0x98, 0xE9,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x96, 0xE2,
-	0x41, 0x04,
-
-	0x7B, 0x43, 0xA0, 0xE8,
-	0x73, 0x4B, 0xA0, 0xE8,
-
-	0xAD, 0xEE, 0x29, 0x9F,
-	0x00, 0xE0,
-	0x49, 0x04,
-
-	0x90, 0xE2,
-	0x51, 0x04,
-	0x31, 0x46, 0xB1, 0xE8,
-
-	0x49, 0x41, 0xC0, 0xEC,
-	0x39, 0x57, 0xB1, 0xE8,
-
-	0x00, 0x04,
-	0x46, 0xE2,
-	0x73, 0x53, 0xA0, 0xE8,
-
-	0x51, 0x41, 0xC0, 0xEC,
-	0x31, 0x00,
-	0x39, 0x00,
-
-	0x6E, 0x80, 0x15, 0xEA,
-	0x08, 0x04,
-	0x10, 0x04,
-
-	0x51, 0x49, 0xC0, 0xEC,
-	0x2F, 0x41, 0x60, 0xEA,
-
-	0x31, 0x20,
-	0x39, 0x20,
-	0x1F, 0x42, 0xA0, 0xE8,
-
-	0x2A, 0x42, 0x4A, 0xBF,
-	0x27, 0x4A, 0xA0, 0xE8,
-
-	0x1A, 0x42, 0x52, 0xBF,
-	0x1E, 0x49, 0x60, 0xEA,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x26, 0x51, 0x60, 0xEA,
-
-	0x32, 0x40, 0x48, 0xBD,
-	0x22, 0x40, 0x50, 0xBD,
-
-	0x12, 0x41, 0x49, 0xBD,
-	0x3A, 0x41, 0x51, 0xBD,
-
-	0xBF, 0x2F, 0x26, 0xBD,
-	0x00, 0xE0,
-	0x7B, 0x72,
-
-	0x32, 0x20,
-	0x22, 0x20,
-	0x12, 0x20,
-	0x3A, 0x20,
-
-	0x46, 0x31, 0x46, 0xBF,
-	0x4E, 0x31, 0x4E, 0xBF,
-
-	0xB3, 0xE2, 0x2D, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x56, 0x31, 0x56, 0xBF,
-	0x47, 0x39, 0x47, 0xBF,
-
-	0x4F, 0x39, 0x4F, 0xBF,
-	0x57, 0x39, 0x57, 0xBF,
-
-	0x60, 0x80, 0x07, 0xEA,
-	0x24, 0x41, 0x20, 0xE9,
-
-	0x42, 0x73, 0xF8, 0xEC,
-	0x00, 0xE0,
-	0x2D, 0x73,
-
-	0x33, 0x72,
-	0x0C, 0xE3,
-	0xA5, 0x2F, 0x1E, 0xBD,
-
-	0x43, 0x43, 0x2D, 0xDF,
-	0x4B, 0x4B, 0x2D, 0xDF,
-
-	0xAE, 0x1E, 0x26, 0xBD,
-	0x58, 0xE3,
-	0x33, 0x66,
-
-	0x53, 0x53, 0x2D, 0xDF,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xB8, 0x38, 0x33, 0xBF,
-	0x00, 0xE0,
-	0x59, 0xE3,
-
-	0x1E, 0x12, 0x41, 0xE9,
-	0x1A, 0x22, 0x41, 0xE9,
-
-	0x2B, 0x40, 0x3D, 0xE9,
-	0x3F, 0x4B, 0xA0, 0xE8,
-
-	0x2D, 0x73,
-	0x30, 0x76,
-	0x05, 0x80, 0x3D, 0xEA,
-
-	0x37, 0x43, 0xA0, 0xE8,
-	0x3D, 0x53, 0xA0, 0xE8,
-
-	0x48, 0x70, 0xF8, 0xEC,
-	0x2B, 0x48, 0x3C, 0xE9,
-
-	0x1F, 0x27, 0xBC, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x18, 0x3A, 0x41, 0xE9,
-	0x1D, 0x32, 0x41, 0xE9,
-
-	0x2A, 0x40, 0x20, 0xE9,
-	0x56, 0x3D, 0x56, 0xDF,
-
-	0x46, 0x37, 0x46, 0xDF,
-	0x4E, 0x3F, 0x4E, 0xDF,
-
-	0x16, 0x30, 0x20, 0xE9,
-	0x4F, 0x3F, 0x4F, 0xDF,
-
-	0x47, 0x37, 0x47, 0xDF,
-	0x57, 0x3D, 0x57, 0xDF,
-
-	0x32, 0x32, 0x2D, 0xDF,
-	0x22, 0x22, 0x2D, 0xDF,
-
-	0x12, 0x12, 0x2D, 0xDF,
-	0x3A, 0x3A, 0x2D, 0xDF,
-
-	0x27, 0xCF, 0x74, 0xC2,
-	0x37, 0xCF, 0x74, 0xC4,
-
-	0x0A, 0x44, 0x4C, 0xB0,
-	0x02, 0x44, 0x54, 0xB0,
-
-	0x3D, 0xCF, 0x74, 0xC0,
-	0x34, 0x37, 0x20, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x38, 0x27, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3C, 0x3D, 0x20, 0xE9,
-
-	0x2A, 0x44, 0x4C, 0xB2,
-	0x1A, 0x44, 0x54, 0xB2,
-
-	0x32, 0x80, 0x3A, 0xEA,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x27, 0xCF, 0x75, 0xC0,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x32, 0x31, 0x5F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x33, 0x39, 0x5F, 0xE9,
-
-	0x3D, 0xCF, 0x75, 0xC2,
-	0x37, 0xCF, 0x75, 0xC4,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0xA6, 0x27, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0xA3, 0x3D, 0x20, 0xE9,
-
-	0x2A, 0x44, 0x4C, 0xB4,
-	0x1A, 0x44, 0x54, 0xB4,
-
-	0x0A, 0x45, 0x4D, 0xB0,
-	0x02, 0x45, 0x55, 0xB0,
-
-	0x88, 0x73, 0x5E, 0xE9,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0xA0, 0x37, 0x20, 0xE9,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x3E, 0x30, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3F, 0x38, 0x4F, 0xE9,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x3A, 0x31, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x3B, 0x39, 0x4F, 0xE9,
-
-	0x2A, 0x45, 0x4D, 0xB2,
-	0x1A, 0x45, 0x55, 0xB2,
-
-	0x0A, 0x45, 0x4D, 0xB4,
-	0x02, 0x45, 0x55, 0xB4,
-
-	0x27, 0xCF, 0x74, 0xC6,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0xA7, 0x30, 0x4F, 0xE9,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x9C, 0x27, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0xA8, 0x38, 0x4F, 0xE9,
-
-	0x2A, 0x44, 0x4C, 0xB6,
-	0x1A, 0x44, 0x54, 0xB6,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x36, 0x31, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x37, 0x39, 0x4F, 0xE9,
-
-	0x0A, 0x45, 0x4D, 0xB6,
-	0x02, 0x45, 0x55, 0xB6,
-
-	0x3D, 0xCF, 0x75, 0xC6,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x2A, 0x46, 0x4E, 0xBF,
-	0x1A, 0x46, 0x56, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0xA4, 0x31, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0xA5, 0x39, 0x4F, 0xE9,
-
-	0x31, 0x3D, 0x20, 0xE9,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x0A, 0x47, 0x4F, 0xBF,
-	0x02, 0x47, 0x57, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0xA1, 0x30, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0xA2, 0x38, 0x4F, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x9D, 0x31, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x9E, 0x39, 0x4F, 0xE9,
-
-	0x2A, 0x43, 0x4B, 0xBF,
-	0x1A, 0x43, 0x53, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x35, 0x30, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x39, 0x38, 0x4F, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x80, 0x31, 0x57, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x81, 0x39, 0x57, 0xE9,
-
-	0x37, 0x48, 0x50, 0xBD,
-	0x8A, 0x36, 0x20, 0xE9,
-
-	0x86, 0x76, 0x57, 0xE9,
-	0x8B, 0x3E, 0x20, 0xE9,
-
-	0x82, 0x30, 0x57, 0xE9,
-	0x87, 0x77, 0x57, 0xE9,
-
-	0x83, 0x38, 0x57, 0xE9,
-	0x35, 0x49, 0x51, 0xBD,
-
-	0x84, 0x31, 0x5E, 0xE9,
-	0x30, 0x1F, 0x5F, 0xE9,
-
-	0x85, 0x39, 0x5E, 0xE9,
-	0x57, 0x25, 0x20, 0xE9,
-
-	0x2B, 0x48, 0x20, 0xE9,
-	0x1D, 0x37, 0xE1, 0xEA,
-
-	0x1E, 0x35, 0xE1, 0xEA,
-	0x00, 0xE0,
-	0x26, 0x77,
-
-	0x24, 0x49, 0x20, 0xE9,
-	0x99, 0xFF, 0x20, 0xEA,
-
-	0x16, 0x26, 0x20, 0xE9,
-	0x57, 0x2E, 0xBF, 0xEA,
-
-	0x1C, 0x46, 0xA0, 0xE8,
-	0x23, 0x4E, 0xA0, 0xE8,
-
-	0x2B, 0x56, 0xA0, 0xE8,
-	0x1D, 0x47, 0xA0, 0xE8,
-
-	0x24, 0x4F, 0xA0, 0xE8,
-	0x2C, 0x57, 0xA0, 0xE8,
-
-	0x1C, 0x00,
-	0x23, 0x00,
-	0x2B, 0x00,
-	0x00, 0xE0,
-
-	0x1D, 0x00,
-	0x24, 0x00,
-	0x2C, 0x00,
-	0x00, 0xE0,
-
-	0x1C, 0x65,
-	0x23, 0x65,
-	0x2B, 0x65,
-	0x00, 0xE0,
-
-	0x1D, 0x65,
-	0x24, 0x65,
-	0x2C, 0x65,
-	0x00, 0xE0,
-
-	0x1C, 0x23, 0x60, 0xEC,
-	0x36, 0xD7, 0x36, 0xAD,
-
-	0x2B, 0x80, 0x60, 0xEC,
-	0x1D, 0x24, 0x60, 0xEC,
-
-	0x3E, 0xD7, 0x3E, 0xAD,
-	0x2C, 0x80, 0x60, 0xEC,
-
-	0x1C, 0x2B, 0xDE, 0xE8,
-	0x23, 0x80, 0xDE, 0xE8,
-
-	0x36, 0x80, 0x36, 0xBD,
-	0x3E, 0x80, 0x3E, 0xBD,
-
-	0x33, 0xD7, 0x1C, 0xBD,
-	0x3B, 0xD7, 0x23, 0xBD,
-
-	0x46, 0x80, 0x46, 0xCF,
-	0x4F, 0x80, 0x4F, 0xCF,
-
-	0x56, 0x33, 0x56, 0xCF,
-	0x47, 0x3B, 0x47, 0xCF,
-
-	0xC1, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x4E, 0x33, 0x4E, 0xCF,
-	0x57, 0x3B, 0x57, 0xCF,
-
-	0x87, 0xFF, 0x20, 0xEA,
-	0x57, 0xC0, 0xBF, 0xEA,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_tgzsf[] = {
-
-	0x00, 0x88, 0x98, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-	0xFF, 0x80, 0xC0, 0xE9,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x22, 0x40, 0x48, 0xBF,
-	0x2A, 0x40, 0x50, 0xBF,
-
-	0x32, 0x41, 0x49, 0xBF,
-	0x3A, 0x41, 0x51, 0xBF,
-
-	0xC3, 0x6B,
-	0xCB, 0x6B,
-	0x00, 0x88, 0x98, 0xE9,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x96, 0xE2,
-	0x41, 0x04,
-
-	0x7B, 0x43, 0xA0, 0xE8,
-	0x73, 0x4B, 0xA0, 0xE8,
-
-	0xAD, 0xEE, 0x29, 0x9F,
-	0x00, 0xE0,
-	0x49, 0x04,
-
-	0x90, 0xE2,
-	0x51, 0x04,
-	0x31, 0x46, 0xB1, 0xE8,
-
-	0x49, 0x41, 0xC0, 0xEC,
-	0x39, 0x57, 0xB1, 0xE8,
-
-	0x00, 0x04,
-	0x46, 0xE2,
-	0x73, 0x53, 0xA0, 0xE8,
-
-	0x51, 0x41, 0xC0, 0xEC,
-	0x31, 0x00,
-	0x39, 0x00,
-
-	0x6A, 0x80, 0x15, 0xEA,
-	0x08, 0x04,
-	0x10, 0x04,
-
-	0x51, 0x49, 0xC0, 0xEC,
-	0x2F, 0x41, 0x60, 0xEA,
-
-	0x31, 0x20,
-	0x39, 0x20,
-	0x1F, 0x42, 0xA0, 0xE8,
-
-	0x2A, 0x42, 0x4A, 0xBF,
-	0x27, 0x4A, 0xA0, 0xE8,
-
-	0x1A, 0x42, 0x52, 0xBF,
-	0x1E, 0x49, 0x60, 0xEA,
-
-	0x73, 0x7B, 0xC8, 0xEC,
-	0x26, 0x51, 0x60, 0xEA,
-
-	0x32, 0x40, 0x48, 0xBD,
-	0x22, 0x40, 0x50, 0xBD,
-
-	0x12, 0x41, 0x49, 0xBD,
-	0x3A, 0x41, 0x51, 0xBD,
-
-	0xBF, 0x2F, 0x26, 0xBD,
-	0x00, 0xE0,
-	0x7B, 0x72,
-
-	0x32, 0x20,
-	0x22, 0x20,
-	0x12, 0x20,
-	0x3A, 0x20,
-
-	0x46, 0x31, 0x46, 0xBF,
-	0x4E, 0x31, 0x4E, 0xBF,
-
-	0xB3, 0xE2, 0x2D, 0x9F,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x56, 0x31, 0x56, 0xBF,
-	0x47, 0x39, 0x47, 0xBF,
-
-	0x4F, 0x39, 0x4F, 0xBF,
-	0x57, 0x39, 0x57, 0xBF,
-
-	0x5C, 0x80, 0x07, 0xEA,
-	0x24, 0x41, 0x20, 0xE9,
-
-	0x42, 0x73, 0xF8, 0xEC,
-	0x00, 0xE0,
-	0x2D, 0x73,
-
-	0x33, 0x72,
-	0x0C, 0xE3,
-	0xA5, 0x2F, 0x1E, 0xBD,
-
-	0x43, 0x43, 0x2D, 0xDF,
-	0x4B, 0x4B, 0x2D, 0xDF,
-
-	0xAE, 0x1E, 0x26, 0xBD,
-	0x58, 0xE3,
-	0x33, 0x66,
-
-	0x53, 0x53, 0x2D, 0xDF,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0xB8, 0x38, 0x33, 0xBF,
-	0x00, 0xE0,
-	0x59, 0xE3,
-
-	0x1E, 0x12, 0x41, 0xE9,
-	0x1A, 0x22, 0x41, 0xE9,
-
-	0x2B, 0x40, 0x3D, 0xE9,
-	0x3F, 0x4B, 0xA0, 0xE8,
-
-	0x2D, 0x73,
-	0x30, 0x76,
-	0x05, 0x80, 0x3D, 0xEA,
-
-	0x37, 0x43, 0xA0, 0xE8,
-	0x3D, 0x53, 0xA0, 0xE8,
-
-	0x48, 0x70, 0xF8, 0xEC,
-	0x2B, 0x48, 0x3C, 0xE9,
-
-	0x1F, 0x27, 0xBC, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x15, 0xC0, 0x20, 0xE9,
-	0x15, 0xC0, 0x20, 0xE9,
-
-	0x18, 0x3A, 0x41, 0xE9,
-	0x1D, 0x32, 0x41, 0xE9,
-
-	0x2A, 0x40, 0x20, 0xE9,
-	0x56, 0x3D, 0x56, 0xDF,
-
-	0x46, 0x37, 0x46, 0xDF,
-	0x4E, 0x3F, 0x4E, 0xDF,
-
-	0x16, 0x30, 0x20, 0xE9,
-	0x4F, 0x3F, 0x4F, 0xDF,
-
-	0x47, 0x37, 0x47, 0xDF,
-	0x57, 0x3D, 0x57, 0xDF,
-
-	0x32, 0x32, 0x2D, 0xDF,
-	0x22, 0x22, 0x2D, 0xDF,
-
-	0x12, 0x12, 0x2D, 0xDF,
-	0x3A, 0x3A, 0x2D, 0xDF,
-
-	0x27, 0xCF, 0x74, 0xC2,
-	0x37, 0xCF, 0x74, 0xC4,
-
-	0x0A, 0x44, 0x4C, 0xB0,
-	0x02, 0x44, 0x54, 0xB0,
-
-	0x3D, 0xCF, 0x74, 0xC0,
-	0x34, 0x37, 0x20, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x38, 0x27, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3C, 0x3D, 0x20, 0xE9,
-
-	0x2A, 0x44, 0x4C, 0xB2,
-	0x1A, 0x44, 0x54, 0xB2,
-
-	0x2E, 0x80, 0x3A, 0xEA,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x27, 0xCF, 0x75, 0xC0,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x32, 0x31, 0x5F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x33, 0x39, 0x5F, 0xE9,
-
-	0x3D, 0xCF, 0x75, 0xC2,
-	0x37, 0xCF, 0x75, 0xC4,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0xA6, 0x27, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0xA3, 0x3D, 0x20, 0xE9,
-
-	0x2A, 0x44, 0x4C, 0xB4,
-	0x1A, 0x44, 0x54, 0xB4,
-
-	0x0A, 0x45, 0x4D, 0xB0,
-	0x02, 0x45, 0x55, 0xB0,
-
-	0x88, 0x73, 0x5E, 0xE9,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0xA0, 0x37, 0x20, 0xE9,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x3E, 0x30, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x3F, 0x38, 0x4F, 0xE9,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x3A, 0x31, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x3B, 0x39, 0x4F, 0xE9,
-
-	0x2A, 0x45, 0x4D, 0xB2,
-	0x1A, 0x45, 0x55, 0xB2,
-
-	0x0A, 0x45, 0x4D, 0xB4,
-	0x02, 0x45, 0x55, 0xB4,
-
-	0x27, 0xCF, 0x75, 0xC6,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0xA7, 0x30, 0x4F, 0xE9,
-	0x0A, 0x20,
-	0x02, 0x20,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x31, 0x27, 0x20, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0xA8, 0x38, 0x4F, 0xE9,
-
-	0x2A, 0x45, 0x4D, 0xB6,
-	0x1A, 0x45, 0x55, 0xB6,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x36, 0x31, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x37, 0x39, 0x4F, 0xE9,
-
-	0x00, 0x80, 0x00, 0xE8,
-	0x2A, 0x20,
-	0x1A, 0x20,
-
-	0x2A, 0x46, 0x4E, 0xBF,
-	0x1A, 0x46, 0x56, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0xA4, 0x31, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0xA5, 0x39, 0x4F, 0xE9,
-
-	0x0A, 0x47, 0x4F, 0xBF,
-	0x02, 0x47, 0x57, 0xBF,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0xA1, 0x30, 0x4F, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0xA2, 0x38, 0x4F, 0xE9,
-
-	0x2A, 0x43, 0x4B, 0xBF,
-	0x1A, 0x43, 0x53, 0xBF,
-
-	0x30, 0x50, 0x2E, 0x9F,
-	0x35, 0x31, 0x4F, 0xE9,
-
-	0x38, 0x21, 0x2C, 0x9F,
-	0x39, 0x39, 0x4F, 0xE9,
-
-	0x31, 0x53, 0x2F, 0x9F,
-	0x80, 0x31, 0x57, 0xE9,
-
-	0x39, 0xE5, 0x2C, 0x9F,
-	0x81, 0x39, 0x57, 0xE9,
-
-	0x37, 0x48, 0x50, 0xBD,
-	0x8A, 0x36, 0x20, 0xE9,
-
-	0x86, 0x76, 0x57, 0xE9,
-	0x8B, 0x3E, 0x20, 0xE9,
-
-	0x82, 0x30, 0x57, 0xE9,
-	0x87, 0x77, 0x57, 0xE9,
-
-	0x83, 0x38, 0x57, 0xE9,
-	0x35, 0x49, 0x51, 0xBD,
-
-	0x84, 0x31, 0x5E, 0xE9,
-	0x30, 0x1F, 0x5F, 0xE9,
-
-	0x85, 0x39, 0x5E, 0xE9,
-	0x57, 0x25, 0x20, 0xE9,
-
-	0x2B, 0x48, 0x20, 0xE9,
-	0x1D, 0x37, 0xE1, 0xEA,
-
-	0x1E, 0x35, 0xE1, 0xEA,
-	0x00, 0xE0,
-	0x26, 0x77,
-
-	0x24, 0x49, 0x20, 0xE9,
-	0x9D, 0xFF, 0x20, 0xEA,
-
-	0x16, 0x26, 0x20, 0xE9,
-	0x57, 0x2E, 0xBF, 0xEA,
-
-	0x1C, 0x46, 0xA0, 0xE8,
-	0x23, 0x4E, 0xA0, 0xE8,
-
-	0x2B, 0x56, 0xA0, 0xE8,
-	0x1D, 0x47, 0xA0, 0xE8,
-
-	0x24, 0x4F, 0xA0, 0xE8,
-	0x2C, 0x57, 0xA0, 0xE8,
-
-	0x1C, 0x00,
-	0x23, 0x00,
-	0x2B, 0x00,
-	0x00, 0xE0,
-
-	0x1D, 0x00,
-	0x24, 0x00,
-	0x2C, 0x00,
-	0x00, 0xE0,
-
-	0x1C, 0x65,
-	0x23, 0x65,
-	0x2B, 0x65,
-	0x00, 0xE0,
-
-	0x1D, 0x65,
-	0x24, 0x65,
-	0x2C, 0x65,
-	0x00, 0xE0,
-
-	0x1C, 0x23, 0x60, 0xEC,
-	0x36, 0xD7, 0x36, 0xAD,
-
-	0x2B, 0x80, 0x60, 0xEC,
-	0x1D, 0x24, 0x60, 0xEC,
-
-	0x3E, 0xD7, 0x3E, 0xAD,
-	0x2C, 0x80, 0x60, 0xEC,
-
-	0x1C, 0x2B, 0xDE, 0xE8,
-	0x23, 0x80, 0xDE, 0xE8,
-
-	0x36, 0x80, 0x36, 0xBD,
-	0x3E, 0x80, 0x3E, 0xBD,
-
-	0x33, 0xD7, 0x1C, 0xBD,
-	0x3B, 0xD7, 0x23, 0xBD,
-
-	0x46, 0x80, 0x46, 0xCF,
-	0x4F, 0x80, 0x4F, 0xCF,
-
-	0x56, 0x33, 0x56, 0xCF,
-	0x47, 0x3B, 0x47, 0xCF,
-
-	0xC5, 0xFF, 0x20, 0xEA,
-	0x00, 0x80, 0x00, 0xE8,
-
-	0x4E, 0x33, 0x4E, 0xCF,
-	0x57, 0x3B, 0x57, 0xCF,
-
-	0x8B, 0xFF, 0x20, 0xEA,
-	0x57, 0xC0, 0xBF, 0xEA,
-
-	0x00, 0x80, 0xA0, 0xE9,
-	0x00, 0x00, 0xD8, 0xEC,
-
-};
diff --git a/drivers/gpu/drm/mga/mga_warp.c b/drivers/gpu/drm/mga/mga_warp.c
index 651b93c8ab5..9aad4847afd 100644
--- a/drivers/gpu/drm/mga/mga_warp.c
+++ b/drivers/gpu/drm/mga/mga_warp.c
@@ -27,132 +27,108 @@
  *    Gareth Hughes <gareth@valinux.com>
  */
 
+#include <linux/firmware.h>
+#include <linux/ihex.h>
+#include <linux/platform_device.h>
+
 #include "drmP.h"
 #include "drm.h"
 #include "mga_drm.h"
 #include "mga_drv.h"
-#include "mga_ucode.h"
+
+#define FIRMWARE_G200 "matrox/g200_warp.fw"
+#define FIRMWARE_G400 "matrox/g400_warp.fw"
+
+MODULE_FIRMWARE(FIRMWARE_G200);
+MODULE_FIRMWARE(FIRMWARE_G400);
 
 #define MGA_WARP_CODE_ALIGN		256	/* in bytes */
 
-#define WARP_UCODE_SIZE( which )					\
-	((sizeof(which) / MGA_WARP_CODE_ALIGN + 1) * MGA_WARP_CODE_ALIGN)
-
-#define WARP_UCODE_INSTALL( which, where )				\
-do {									\
-	DRM_DEBUG( " pcbase = 0x%08lx  vcbase = %p\n", pcbase, vcbase );\
-	dev_priv->warp_pipe_phys[where] = pcbase;			\
-	memcpy( vcbase, which, sizeof(which) );				\
-	pcbase += WARP_UCODE_SIZE( which );				\
-	vcbase += WARP_UCODE_SIZE( which );				\
-} while (0)
-
-static const unsigned int mga_warp_g400_microcode_size =
-    (WARP_UCODE_SIZE(warp_g400_tgz) +
-     WARP_UCODE_SIZE(warp_g400_tgza) +
-     WARP_UCODE_SIZE(warp_g400_tgzaf) +
-     WARP_UCODE_SIZE(warp_g400_tgzf) +
-     WARP_UCODE_SIZE(warp_g400_tgzs) +
-     WARP_UCODE_SIZE(warp_g400_tgzsa) +
-     WARP_UCODE_SIZE(warp_g400_tgzsaf) +
-     WARP_UCODE_SIZE(warp_g400_tgzsf) +
-     WARP_UCODE_SIZE(warp_g400_t2gz) +
-     WARP_UCODE_SIZE(warp_g400_t2gza) +
-     WARP_UCODE_SIZE(warp_g400_t2gzaf) +
-     WARP_UCODE_SIZE(warp_g400_t2gzf) +
-     WARP_UCODE_SIZE(warp_g400_t2gzs) +
-     WARP_UCODE_SIZE(warp_g400_t2gzsa) +
-     WARP_UCODE_SIZE(warp_g400_t2gzsaf) + WARP_UCODE_SIZE(warp_g400_t2gzsf));
-
-static const unsigned int mga_warp_g200_microcode_size =
-    (WARP_UCODE_SIZE(warp_g200_tgz) +
-     WARP_UCODE_SIZE(warp_g200_tgza) +
-     WARP_UCODE_SIZE(warp_g200_tgzaf) +
-     WARP_UCODE_SIZE(warp_g200_tgzf) +
-     WARP_UCODE_SIZE(warp_g200_tgzs) +
-     WARP_UCODE_SIZE(warp_g200_tgzsa) +
-     WARP_UCODE_SIZE(warp_g200_tgzsaf) + WARP_UCODE_SIZE(warp_g200_tgzsf));
-
-unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv)
+#define WARP_UCODE_SIZE(size)		ALIGN(size, MGA_WARP_CODE_ALIGN)
+
+int mga_warp_install_microcode(drm_mga_private_t * dev_priv)
 {
+	unsigned char *vcbase = dev_priv->warp->handle;
+	unsigned long pcbase = dev_priv->warp->offset;
+	const char *firmware_name;
+	struct platform_device *pdev;
+	const struct firmware *fw = NULL;
+	const struct ihex_binrec *rec;
+	unsigned int size;
+	int n_pipes, where;
+	int rc = 0;
+
 	switch (dev_priv->chipset) {
 	case MGA_CARD_TYPE_G400:
 	case MGA_CARD_TYPE_G550:
-		return PAGE_ALIGN(mga_warp_g400_microcode_size);
+		firmware_name = FIRMWARE_G400;
+		n_pipes = MGA_MAX_G400_PIPES;
+		break;
 	case MGA_CARD_TYPE_G200:
-		return PAGE_ALIGN(mga_warp_g200_microcode_size);
+		firmware_name = FIRMWARE_G200;
+		n_pipes = MGA_MAX_G200_PIPES;
+		break;
 	default:
-		return 0;
+		return -EINVAL;
 	}
-}
-
-static int mga_warp_install_g400_microcode(drm_mga_private_t * dev_priv)
-{
-	unsigned char *vcbase = dev_priv->warp->handle;
-	unsigned long pcbase = dev_priv->warp->offset;
-
-	memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys));
-
-	WARP_UCODE_INSTALL(warp_g400_tgz, MGA_WARP_TGZ);
-	WARP_UCODE_INSTALL(warp_g400_tgzf, MGA_WARP_TGZF);
-	WARP_UCODE_INSTALL(warp_g400_tgza, MGA_WARP_TGZA);
-	WARP_UCODE_INSTALL(warp_g400_tgzaf, MGA_WARP_TGZAF);
-	WARP_UCODE_INSTALL(warp_g400_tgzs, MGA_WARP_TGZS);
-	WARP_UCODE_INSTALL(warp_g400_tgzsf, MGA_WARP_TGZSF);
-	WARP_UCODE_INSTALL(warp_g400_tgzsa, MGA_WARP_TGZSA);
-	WARP_UCODE_INSTALL(warp_g400_tgzsaf, MGA_WARP_TGZSAF);
-
-	WARP_UCODE_INSTALL(warp_g400_t2gz, MGA_WARP_T2GZ);
-	WARP_UCODE_INSTALL(warp_g400_t2gzf, MGA_WARP_T2GZF);
-	WARP_UCODE_INSTALL(warp_g400_t2gza, MGA_WARP_T2GZA);
-	WARP_UCODE_INSTALL(warp_g400_t2gzaf, MGA_WARP_T2GZAF);
-	WARP_UCODE_INSTALL(warp_g400_t2gzs, MGA_WARP_T2GZS);
-	WARP_UCODE_INSTALL(warp_g400_t2gzsf, MGA_WARP_T2GZSF);
-	WARP_UCODE_INSTALL(warp_g400_t2gzsa, MGA_WARP_T2GZSA);
-	WARP_UCODE_INSTALL(warp_g400_t2gzsaf, MGA_WARP_T2GZSAF);
-
-	return 0;
-}
-
-static int mga_warp_install_g200_microcode(drm_mga_private_t * dev_priv)
-{
-	unsigned char *vcbase = dev_priv->warp->handle;
-	unsigned long pcbase = dev_priv->warp->offset;
-
-	memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys));
-
-	WARP_UCODE_INSTALL(warp_g200_tgz, MGA_WARP_TGZ);
-	WARP_UCODE_INSTALL(warp_g200_tgzf, MGA_WARP_TGZF);
-	WARP_UCODE_INSTALL(warp_g200_tgza, MGA_WARP_TGZA);
-	WARP_UCODE_INSTALL(warp_g200_tgzaf, MGA_WARP_TGZAF);
-	WARP_UCODE_INSTALL(warp_g200_tgzs, MGA_WARP_TGZS);
-	WARP_UCODE_INSTALL(warp_g200_tgzsf, MGA_WARP_TGZSF);
-	WARP_UCODE_INSTALL(warp_g200_tgzsa, MGA_WARP_TGZSA);
-	WARP_UCODE_INSTALL(warp_g200_tgzsaf, MGA_WARP_TGZSAF);
 
-	return 0;
-}
+	pdev = platform_device_register_simple("mga_warp", 0, NULL, 0);
+	if (IS_ERR(pdev)) {
+		DRM_ERROR("mga: Failed to register microcode\n");
+		return PTR_ERR(pdev);
+	}
+	rc = request_ihex_firmware(&fw, firmware_name, &pdev->dev);
+	platform_device_unregister(pdev);
+	if (rc) {
+		DRM_ERROR("mga: Failed to load microcode \"%s\"\n",
+			  firmware_name);
+		return rc;
+	}
 
-int mga_warp_install_microcode(drm_mga_private_t * dev_priv)
-{
-	const unsigned int size = mga_warp_microcode_size(dev_priv);
+	size = 0;
+	where = 0;
+	for (rec = (const struct ihex_binrec *)fw->data;
+	     rec;
+	     rec = ihex_next_binrec(rec)) {
+		size += WARP_UCODE_SIZE(be16_to_cpu(rec->len));
+		where++;
+	}
 
+	if (where != n_pipes) {
+		DRM_ERROR("mga: Invalid microcode \"%s\"\n", firmware_name);
+		rc = -EINVAL;
+		goto out;
+	}
+	size = PAGE_ALIGN(size);
 	DRM_DEBUG("MGA ucode size = %d bytes\n", size);
 	if (size > dev_priv->warp->size) {
 		DRM_ERROR("microcode too large! (%u > %lu)\n",
 			  size, dev_priv->warp->size);
-		return -ENOMEM;
+		rc = -ENOMEM;
+		goto out;
 	}
 
-	switch (dev_priv->chipset) {
-	case MGA_CARD_TYPE_G400:
-	case MGA_CARD_TYPE_G550:
-		return mga_warp_install_g400_microcode(dev_priv);
-	case MGA_CARD_TYPE_G200:
-		return mga_warp_install_g200_microcode(dev_priv);
-	default:
-		return -EINVAL;
+	memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys));
+
+	where = 0;
+	for (rec = (const struct ihex_binrec *)fw->data;
+	     rec;
+	     rec = ihex_next_binrec(rec)) {
+		unsigned int src_size, dst_size;
+
+		DRM_DEBUG(" pcbase = 0x%08lx  vcbase = %p\n", pcbase, vcbase);
+		dev_priv->warp_pipe_phys[where] = pcbase;
+		src_size = be16_to_cpu(rec->len);
+		dst_size = WARP_UCODE_SIZE(src_size);
+		memcpy(vcbase, rec->data, src_size);
+		pcbase += dst_size;
+		vcbase += dst_size;
+		where++;
 	}
+
+out:
+	release_firmware(fw);
+	return rc;
 }
 
 #define WMISC_EXPECTED		(MGA_WUCODECACHE_ENABLE | MGA_WMASTER_ENABLE)
diff --git a/firmware/Makefile b/firmware/Makefile
index 621de8e952f..0e39f7e73ba 100644
--- a/firmware/Makefile
+++ b/firmware/Makefile
@@ -42,6 +42,7 @@ fw-shipped-$(CONFIG_COMPUTONE) += intelliport2.bin
 fw-shipped-$(CONFIG_CHELSIO_T3) += cxgb3/t3b_psram-1.1.0.bin \
 				   cxgb3/t3c_psram-1.1.0.bin \
 				   cxgb3/t3fw-7.4.0.bin
+fw-shipped-$(CONFIG_DRM_MGA) += matrox/g200_warp.fw matrox/g400_warp.fw
 fw-shipped-$(CONFIG_DVB_AV7110) += av7110/bootcode.bin
 fw-shipped-$(CONFIG_DVB_TTUSB_BUDGET) += ttusb-budget/dspbootcode.bin
 fw-shipped-$(CONFIG_E100) += e100/d101m_ucode.bin e100/d101s_ucode.bin \
diff --git a/firmware/WHENCE b/firmware/WHENCE
index 0f5649a08c0..5db34a88d6e 100644
--- a/firmware/WHENCE
+++ b/firmware/WHENCE
@@ -698,3 +698,35 @@ Found in hex form in kernel source, with the following comment:
    Copyright (c) 1998-2002 by Paul Davis <pbd@op.net>
 
 --------------------------------------------------------------------------
+
+Driver: mga - Matrox G200/G400/G550
+
+File: matrox/g200_warp.fw
+File: matrox/g400_warp.fw
+
+Licence:
+
+Copyright 1999 Matrox Graphics Inc.
+All Rights Reserved.
+
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and associated documentation files (the "Software"),
+to deal in the Software without restriction, including without limitation
+the rights to use, copy, modify, merge, publish, distribute, sublicense,
+and/or sell copies of the Software, and to permit persons to whom the
+Software is furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included
+in all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+MATROX GRAPHICS INC., OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
+DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+Found in hex form in kernel source.
+
+--------------------------------------------------------------------------
diff --git a/firmware/matrox/g200_warp.H16 b/firmware/matrox/g200_warp.H16
new file mode 100644
index 00000000000..5064b6f01bb
--- /dev/null
+++ b/firmware/matrox/g200_warp.H16
@@ -0,0 +1,28 @@
+/*
+ * WARP pipes are named according to the functions they perform, where
+ *
+ *   - T stands for computation of texture stage 0
+ *   - T2 stands for computation of both texture stage 0 and texture stage 1
+ *   - G stands for computation of triangle intensity (Gouraud interpolation)
+ *   - Z stands for computation of Z buffer interpolation
+ *   - S stands for computation of specular highlight
+ *   - A stands for computation of the alpha channel
+ *   - F stands for computation of vertex fog interpolation
+ */
+/* TGZ */
+:04B8000000008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E9728007EA241F20E9154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E2608015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E803800AEA17C12BBD008000E8008000E8B3689725008000E833C033AF3C274FE9573920E9281960EC2B3220E91D3B20E9B30500E0162820E9233B33AD1E2B20E91C8020E9573620E90080A0E94040D8ECFF80C0E990E200E085FF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E884FF0AEA008000E8C941C8EC42E100E082FF20EA008000E8008000E8008000E8C840C0EC008000E87FFF20EA008000E8008000E8008000E871
+/* TGZF */
+:0548000000008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E97F8007EA241F20E9214580E81A4D80E8315580E8008000E8154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E26B8015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E80D211AB6052131B603802AEA17C12BBD0D2005202FC021C6B3689725008000E833C033AF3C274FE91750569F008000E8370F5C9F00E02F20008000E8281960ECB30500E0008000E8233B33AD008000E8172617DF35174FE9008000E8008000E8008000E839374FE92F2F17AF008000E8008000E8008000E831804FE9008000E8008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E078FF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E877FF0AEA008000E8C941C8EC42E100E075FF20EA008000E8008000E8008000E8C840C0EC008000E872FF20EA008000E8008000E8008000E8BB
+/* TGZA */
+:04E80000000098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E97D8007EA241F20E9154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E26B8015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E82D444CB6254454B603802AEA17C12BBD2D20252007C044C6B3689725008000E833C033AF3C274FE91F62579F008000E83F3D5D9F00E00720008000E8281960ECB30500E0008000E8233B33AD008000E81F261FDF9D1F4FE9008000E8008000E8008000E89E3F4FE907071FAF008000E8008000E8008000E89C804FE9008000E8008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E07AFF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E879FF0AEA008000E8C941C8EC42E100E077FF20EA008000E8008000E8008000E8C840C0EC008000E874FF20EA008000E8008000E8008000E8D9
+/* TGZAF */
+:0568000000008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E9838007EA241F20E9214580E81A4D80E8315580E8008000E8154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E26F8015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E80D211AB6052131B62D444CB6254454B603802AEA17C12BBD0D2005202FC021C6B3689725008000E833C033AF3C274FE900E0252007C044C61750569F00E02D20370F5C9F00E02F201F62579F00E007203F3D5D9F008000E8008000E8281960ECB30500E0172617DF233B33AD35174FE91F261FDF9D1F4FE99E3F4FE939374FE92F2F17AF008000E807071FAF008000E831804FE9008000E89C804FE9008000E8008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E074FF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E873FF0AEA008000E8C941C8EC42E100E071FF20EA008000E8008000E8008000E8C840C0EC008000E86EFF20EA008000E8008000E8008000E830
+/* TGZS */
+:05C0000000008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E98B8007EA241F20E9214580E81A4D80E8315580E8008000E8154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E2778015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E82D211AB0252131B00D211AB2052131B203802AEA17C12BBD2D20252005200D20B3689725008000E833C033AF2FC021C01642569F3C274FE91E62579F008000E8252131B42D211AB43F2F5D9F008000E8330500E0281960EC370F5C9F00E02F20233B33AD1E261EDFA71E4FE9172616DF2D2000E0A83F4FE92F2F1EAF252000E0A4164FE90FC021C2A6804FE91F62579F3F2F5D9F00E08F20A5374FE90F170FAF06C021C4008000E8008000E8A3804FE9062000E01F261FDFA11F4FE9A23F4FE9008000E8008000E806061FAF008000E8008000E8008000E8A0804FE9008000E8008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E06CFF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E86BFF0AEA008000E8C941C8EC42E100E069FF20EA008000E8008000E8008000E8C840C0EC008000E866FF20EA008000E8008000E8008000E85C
+/* TGZSF */
+:05E0000000008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E98F8007EA241F20E9214580E81A4D80E8315580E8008000E8154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E27B8015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E82D211AB0252131B00D211AB2052131B203802AEA17C12BBD2D20252005200D20B3689725008000E833C033AF2FC021C01642569F3C274FE91E62579F008000E8252131B42D211AB43F2F5D9F008000E8330500E0281960EC0D211AB6052131B6370F5C9F00E02F20233B33AD1E261EDFA71E4FE9172616DF2D2000E0A83F4FE92F2F1EAF252000E0A4164FE90FC021C2A6804FE91F62579F0D2005202FC021C63F2F5D9F00E00F201750569FA5374FE906C021C40F170FAF370F5C9F008000E82F2000E0A3804FE9062000E01F261FDF172617DF35174FE9A11F4FE9A23F4FE906061FAF39374FE92F2F17AF008000E8A0804FE9008000E831804FE9008000E8008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E068FF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E867FF0AEA008000E8C941C8EC42E100E065FF20EA008000E8008000E8008000E8C840C0EC008000E862FF20EA008000E8008000E8008000E8F9
+/* TGZSA */
+:05E0000000008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E98F8007EA241F20E9214580E81A4D80E8315580E8008000E8154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E27B8015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E82D211AB0252131B00D211AB2052131B203802AEA17C12BBD2D20252005200D20B3689725008000E833C033AF2FC021C01642569F3C274FE91E62579F008000E8252131B42D211AB43F2F5D9F008000E8330500E0281960EC0D444CB6054454B6370F5C9F00E02F20233B33AD1E261EDFA71E4FE9172616DF2D2000E0A83F4FE92F2F1EAF252000E0A4164FE90FC021C2A6804FE91F62579F0D200520008000E83F2F5D9F00E00F201750569FA5374FE906C021C40F170FAF370F5C9F008000E82FC044C6A3804FE9062000E01F261FDF172617DF9D174FE9A11F4FE9A23F4FE906061FAF00E0AF209E374FE92F172FAFA0804FE9008000E8008000E89C804FE9008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E068FF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E867FF0AEA008000E8C941C8EC42E100E065FF20EA008000E8008000E8008000E8C840C0EC008000E862FF20EA008000E8008000E8008000E883
+/* TGZAF */
+:05B8000000008000E8008000E8008000E8008000E8008000E8008000E80098A0E94040D8ECFF80C0E9008000E81FD718BD3FD722BD8104890401040904C941C0EC110400E041CC41CD49CC49CDD141C0EC51CC51CD80041004080400E000CCC0CDD149C0EC8A1F20E98B3F20E9413C41AD493C49AD10CC10CD08CC08CDB94149BB1FF041CD513C51AD009880E9948007EA241F20E9214580E81A4D80E8315580E8008000E8154149BD1D4151BD2E412AB83453A0E815301D3058E300E0B54048BD3D4050BD2443A0E82C4BA0E8157209E300E01D723530B530BD303D309C97579F008000E86C64C8EC98E1B505BD052E3032C0A0E833C0A0E87464C8EC403C40AD326A2A302073336A00E028731C7283E2808015EAB83D28DF303520DF403000E0CCE26472254252BF2D424ABF302E30DF382E38DF181D45E91E1545E92B4951BD00E01F73383840AF303040AF241F24DF1D3220E92C1F2CDF1A3320E9B01008E34010B81026F030CD2FF038CD2B8020E92A8020E9A62088E200E0AF20282A26AF202AC0AF341F34DF462446DF283080BF203880BF472447DF4E2C4EDF4F2C4FDF563456DF281528DF201D20DF573457DF00E01D05048010EA89E22B303FC11DBD008000E8008000E8008000E8A068BF25008000E820C020AF2805977400E02A1016C020E9048010EA8CE2950528C128AD1FC115BD008000E8008000E8A8679F6B008000E828C028AD1D252005283280AD402A40BD1C8020E9203320AD207300E0B64951BB262FB0E8192020E9352035DF3D203DDF152015DF1D201DDF26D026CD29492AB8264080BD3B4850BD3E54579F00E082E11EAF599F008000E826302930483C48AD2B72C2E12CC044C2052434BF0D242CBF2D464EBF254656BF201D6F8F323E5FE93E50569F00E03B301E8F519F331E5FE9054454B20D444CB219C0B0E834C044C4337300E03E62579F1EAF599F00E00D20843E58E9281D6F8F052000E0851E58E99B3B33DF202042AF3042569F803E57E93F8F519F30805FE9282824AF811E57E9054757BF0D474FBF888058E91B291BDF301D6F8F3A304FE91C3026DF09E33B053E50569F3B3F4FE91E8F519F00E0AC202D444CB42C1CC0AF254454B400E0C830304630AF1B1B48AF00E02520382C4FE9868057E9381D6F8F287400E00D444CB0054454B02D209B10823E57E932F01BCD1EBD599F831E57E9384738AF34202A3000E00D2032200520878057E91F54579F1742569F00E03B6A3F8F519F371E4FE937322AAF00E03200008000E827C044C0361F4FE91F1F26DF371B37BF172617DF3E174FE93F3F4FE9341F34AF2B05A720332B37DF2717C0AF34804FE9008000E82D211AB0252131B00D211AB2052131B203802AEA17C12BBD2D20252005200D20B3689725008000E833C033AF2FC021C01642569F3C274FE91E62579F008000E8252131B42D211AB43F2F5D9F008000E8330500E0281960EC0D211AB6052131B6370F5C9F00E02F20233B33AD1E261EDFA71E4FE9172616DF2D2000E0A83F4FE92F2F1EAF252000E0A4164FE90FC021C2A6804FE91F62579F0D2005202FC021C62D444CB6254454B63F2F5D9F00E00F202D20252007C044C61750569FA5374FE906C021C40F170FAF370F5C9F008000E81E62579F008000E83E3D5D9F00E007202F2000E0A30F4FE9062000E01F261FDF172617DFA11F4FE91E261EDF9D1E4FE935174FE9A23F4FE906061FAF39374FE92F2F17AF07071EAFA0804FE99E3E4FE931804FE99C804FE9008000E8573920E9162820E91D3B20E91E2B20E92B3220E91C2320E9573620E90080A0E94040D8ECFF80C0E990E200E063FF20EA19C8C1CD1FD718BD3FD722BD9F4149BD008000E8254149BD2D4151BD0D8007EA008000E8354048BD3D4050BD008000E825302D303530B530BD303D309CA75B9F008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E8008000E862FF0AEA008000E8C941C8EC42E100E060FF20EA008000E8008000E8008000E8C840C0EC008000E85DFF20EA008000E8008000E8008000E8D8
+:0000000001FF
diff --git a/firmware/matrox/g400_warp.H16 b/firmware/matrox/g400_warp.H16
new file mode 100644
index 00000000000..b432d1074d8
--- /dev/null
+++ b/firmware/matrox/g400_warp.H16
@@ -0,0 +1,44 @@
+/*
+ * WARP pipes are named according to the functions they perform, where
+ *
+ *   - T stands for computation of texture stage 0
+ *   - T2 stands for computation of both texture stage 0 and texture stage 1
+ *   - G stands for computation of triangle intensity (Gouraud interpolation)
+ *   - Z stands for computation of Z buffer interpolation
+ *   - S stands for computation of specular highlight
+ *   - A stands for computation of the alpha channel
+ *   - F stands for computation of vertex fog interpolation
+ */
+/* TGZ */
+:0338000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC31003900588015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF4A8007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF32322DDF22222DDF12122DDF3A3A2DDF473747DF573D57DF3DCF74C037CF74C431532F9F348020E939E52C9F3C3D20E90A444CB0024454B02A444CB21A4454B21D803AEA0A2002203DCF74C22A201A2030502E9F32315FE938212C9F33395FE931532F9F008000E82A444CB41A4454B439E52C9F383D20E988735EE92A201A202A464EBF1A4656BF31532F9F3E304FE939E52C9F3F384FE90A474FBF024757BF31532F9F3A314FE939E52C9F3B394FE92A434BBF1A4353BF30502E9F36314FE938212C9F37394FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E9AFFF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFD6FF20EA008000E84E334ECF573B57CF9DFF20EA57C0BFEA0080A0E90000D8EC59
+/* TGZF */
+:0360000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC310039005D8015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF4F8007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF32322DDF22222DDF12122DDF3A3A2DDF473747DF573D57DF3DCF74C037CF74C439E52C9F348020E931532F9F008000E888735EE9008000E827CF75C63C3D20E90A444CB0024454B02A444CB21A4454B220803AEA0A2002203DCF74C22A201A2030502E9F32315FE938212C9F33395FE931532F9F312720E90A444CB4024454B42A454DB61A4555B639E52C9F383D20E90A2002202A201A200A474FBF024757BF30502E9F3E304FE938212C9F3F384FE92A464EBF1A4656BF31532F9F3A314FE939E52C9F3B394FE931532F9F36304FE939E52C9F37384FE92A434BBF1A4353BF30502E9F35314FE938212C9F39394FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E9AAFF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFD3FF20EA008000E84E334ECF573B57CF98FF20EA57C0BFEA0080A0E90000D8EC90
+/* TGZA */
+:0358000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC310039005C8015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF4E8007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF32322DDF22222DDF12122DDF3A3A2DDF473747DF573D57DF3DCF74C037CF74C431532F9F348020E939E52C9F3C3D20E927CF74C63DCF74C20A444CB0024454B02A444CB21A4454B220803AEA0A20022088735EE92A201A2030502E9F32315FE938212C9F33395FE931532F9F9C2720E90A444CB4024454B42A444CB61A4454B639E52C9F383D20E90A2002202A201A200A474FBF024757BF30502E9F3E304FE938212C9F3F384FE92A464EBF1A4656BF31532F9F3A314FE939E52C9F3B394FE931532F9F36304FE939E52C9F37384FE92A434BBF1A4353BF30502E9F9D314FE938212C9F9E394FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E9ABFF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFD3FF20EA008000E84E334ECF573B57CF99FF20EA57C0BFEA0080A0E90000D8EC35
+/* TGZAF */
+:0380000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC31003900618015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF538007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF32322DDF22222DDF12122DDF3A3A2DDF473747DF573D57DF3DCF74C037CF74C40A444CB0024454B031532F9F343720E939E52C9F3C3D20E92A444CB21A4454B226803AEA0A20022088735EE92A201A203DCF74C227CF74C630502E9F32315FE938212C9F33395FE931532F9F9C2720E90A444CB4024454B42A444CB61A4454B639E52C9F383D20E90A2002202A201A203DCF75C6008000E830502E9F3E304FE938212C9F3F384FE90A454DB6024555B631532F9F3A314FE939E52C9F3B394FE9313D20E90A2002202A464EBF1A4656BF0A474FBF024757BF30502E9F36304FE938212C9F37384FE931532F9F9D314FE939E52C9F9E394FE92A434BBF1A4353BF30502E9F35304FE938212C9F39384FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E9A6FF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFCDFF20EA008000E84E334ECF573B57CF94FF20EA57C0BFEA0080A0E90000D8EC89
+/* TGZS */
+:03A0000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC31003900658015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF578007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF473747DF573D57DF32322DDF22222DDF12122DDF3A3A2DDF27CF74C237CF74C40A444CB0024454B03DCF74C0343720E931532F9F382720E939E52C9F3C3D20E92A444CB21A4454B229803AEA0A20022027CF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA62720E939E52C9FA33D20E92A444CB41A4454B40A454DB0024555B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE92A454DB21A4555B20A454DB4024555B438212C9F3B394FE90A2002202A201A202A464EBF1A4656BF31532F9F36314FE939E52C9F37394FE930502E9FA7304FE938212C9FA8384FE90A474FBF024757BF31532F9FA4314FE939E52C9FA5394FE92A434BBF1A4353BF30502E9FA1304FE938212C9FA2384FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E9A2FF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFCAFF20EA008000E84E334ECF573B57CF90FF20EA57C0BFEA0080A0E90000D8ECD8
+/* TGZSF */
+:03C8000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC310039006A8015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF5C8007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF473747DF573D57DF32322DDF22222DDF12122DDF3A3A2DDF27CF74C237CF74C40A444CB0024454B03DCF74C0343720E931532F9F382720E939E52C9F3C3D20E92A444CB21A4454B22E803AEA0A20022027CF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA62720E939E52C9FA33D20E92A444CB41A4454B40A454DB0024555B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE938212C9F3B394FE92A454DB21A4555B20A454DB4024555B427CF75C62A201A20A7304FE90A20022031532F9F312720E939E52C9FA8384FE92A454DB61A4555B630502E9F36314FE938212C9F37394FE9008000E82A201A202A464EBF1A4656BF31532F9FA4314FE939E52C9FA5394FE90A474FBF024757BF31532F9FA1304FE939E52C9FA2384FE92A434BBF1A4353BF30502E9F35314FE938212C9F39394FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E99DFF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFC5FF20EA008000E84E334ECF573B57CF8BFF20EA57C0BFEA0080A0E90000D8ECD3
+/* TGZSA */
+:03C8000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC310039006A8015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF5C8007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF473747DF573D57DF32322DDF22222DDF12122DDF3A3A2DDF27CF74C237CF74C40A444CB0024454B03DCF74C0343720E931532F9F382720E939E52C9F3C3D20E92A444CB21A4454B22E803AEA0A20022027CF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA62720E939E52C9FA33D20E92A444CB41A4454B40A454DB0024555B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE938212C9F3B394FE92A454DB21A4555B20A454DB4024555B427CF74C62A201A20A7304FE90A20022031532F9F9C2720E939E52C9FA8384FE92A444CB61A4454B630502E9F36314FE938212C9F37394FE9008000E82A201A202A464EBF1A4656BF31532F9FA4314FE939E52C9FA5394FE90A474FBF024757BF31532F9FA1304FE939E52C9FA2384FE92A434BBF1A4353BF30502E9F9D314FE938212C9F9E394FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E99DFF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFC5FF20EA008000E84E334ECF573B57CF8BFF20EA57C0BFEA0080A0E90000D8ECA0
+/* TGZSAF */
+:03E8000000008898E9008000E80080A0E90000D8ECFF80C0E9008000E8224048BF2A4050BF324149BF3A4151BFC36BCB6B008898E9737BC8EC96E241047B43A0E8734BA0E8ADEE299F00E0490490E251043146B1E84941C0EC3957B1E8000446E27353A0E85141C0EC310039006E8015EA080410045149C0EC2F4160EA312039201F42A0E82A424ABF274AA0E81A4252BF1E4960EA737BC8EC265160EA324048BD224050BD124149BD3A4151BDBF2F26BD00E07B723220222012203A20463146BF4E314EBFB3E22D9F008000E8563156BF473947BF4F394FBF573957BF608007EA244120E94273F8EC00E02D7333720CE3A52F1EBD43432DDF4B4B2DDFAE1E26BD58E3336653532DDF008000E8B83833BF00E059E31E1241E91A2241E92B403DE93F4BA0E82D73307605803DEA3743A0E83D53A0E84870F8EC2B483CE91F27BCE8008000E8008000E8008000E815C020E915C020E915C020E915C020E9183A41E91D3241E92A4020E9563D56DF463746DF4E3F4EDF163020E94F3F4FDF473747DF573D57DF32322DDF22222DDF12122DDF3A3A2DDF27CF74C237CF74C40A444CB0024454B03DCF74C0343720E931532F9F382720E939E52C9F3C3D20E92A444CB21A4454B232803AEA0A20022027CF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA62720E939E52C9FA33D20E92A444CB41A4454B40A454DB0024555B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE938212C9F3B394FE92A454DB21A4555B20A454DB4024555B427CF74C62A201A20A7304FE90A20022031532F9F9C2720E939E52C9FA8384FE92A444CB61A4454B630502E9F36314FE938212C9F37394FE90A454DB6024555B63DCF75C62A201A202A464EBF1A4656BF31532F9FA4314FE939E52C9FA5394FE9313D20E90A2002200A474FBF024757BF30502E9FA1304FE938212C9FA2384FE931532F9F9D314FE939E52C9F9E394FE92A434BBF1A4353BF30502E9F35304FE938212C9F39384FE931532F9F803157E939E52C9F813957E9374850BD8A3620E9867657E98B3E20E9823057E9877757E9833857E9354951BD84315EE9301F5FE985395EE9572520E92B4820E91D37E1EA1E35E1EA00E02677244920E999FF20EA162620E9572EBFEA1C46A0E8234EA0E82B56A0E81D47A0E8244FA0E82C57A0E81C0023002B0000E01D0024002C0000E01C6523652B6500E01D6524652C6500E01C2360EC36D736AD2B8060EC1D2460EC3ED73EAD2C8060EC1C2BDEE82380DEE8368036BD3E803EBD33D71CBD3BD723BD468046CF4F804FCF563356CF473B47CFC1FF20EA008000E84E334ECF573B57CF87FF20EA57C0BFEA0080A0E90000D8EC83
+/* T2GZ */
+:0438000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC31003900788015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF698007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF12122DDF22222DDF32322DDF3A3A2DDF683D68DF493749DF3DCF74C037CF74C431532F9F348020E939E52C9F3C3D20E90A4454B0024464B02A4454B21A4464B225803AEA0A2002203DCF74C22A201A2030502E9F32315FE938212C9F33395FE931532F9F008000E82A4454B41A4464B439E52C9F383D20E988735EE92A201A202A4656BF1A4666BF31532F9F3E304FE939E52C9F3F384FE90A4757BF024767BF31532F9F3A314FE939E52C9F3B394FE92A4353BF1A4363BF30502E9F36314FE938212C9F37394FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E99FFF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFBEFF20EA008000E8583358CF693B69CF7DFF20EA57C0BFEA0080A0E90000D8ECAC
+/* T2GZF */
+:0460000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC310039007D8015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF6E8007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF12122DDF22222DDF32322DDF3A3A2DDF683D68DF493749DF3DCF74C037CF74C439E52C9F348020E931532F9F008000E888735EE9008000E80FCF75C63C3D20E90A4454B0024464B02A4454B21A4464B228803AEA0A2002203DCF74C22A201A2030502E9F32315FE938212C9F33395FE931532F9F310F20E90A4454B4024464B42A4555B61A4565B639E52C9F383D20E90A2002202A201A200A4757BF024767BF30502E9F3E304FE938212C9F3F384FE92A4656BF1A4666BF31532F9F3A314FE939E52C9F3B394FE931532F9F36304FE939E52C9F37384FE92A4353BF1A4363BF30502E9F35314FE938212C9F39394FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E99AFF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFBBFF20EA008000E8583358CF693B69CF78FF20EA57C0BFEA0080A0E90000D8ECFB
+/* T2GZA */
+:0458000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC310039007C8015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF6D8007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF12122DDF22222DDF32322DDF3A3A2DDF683D68DF493749DF3DCF74C037CF74C431532F9F348020E939E52C9F3C3D20E90A4454B0024464B02A4454B21A4464B229803AEA0A2002200FCF74C63DCF74C288735EE92A201A2030502E9F32315FE938212C9F33395FE931532F9F9C0F20E90A4454B4024464B42A4454B61A4464B639E52C9F383D20E90A2002202A201A200A4757BF024767BF30502E9F3E304FE938212C9F3F384FE92A4656BF1A4666BF31532F9F3A314FE939E52C9F3B394FE931532F9F36304FE939E52C9F37384FE92A4353BF1A4363BF30502E9F9D314FE938212C9F9E394FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E99BFF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFBAFF20EA008000E8583358CF693B69CF79FF20EA57C0BFEA0080A0E90000D8ECA0
+/* T2GZAF */
+:0480000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC31003900818015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF728007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF12122DDF22222DDF32322DDF3A3A2DDF683D68DF493749DF3DCF74C037CF74C40A4454B0024464B031532F9F343720E939E52C9F3C3D20E92A4454B21A4464B22E803AEA0A20022088735EE92A201A203DCF74C20FCF74C630502E9F32315FE938212C9F33395FE931532F9F9C0F20E90A4454B4024464B42A4454B61A4464B639E52C9F383D20E90A2002202A201A203DCF75C6008000E830502E9F3E304FE938212C9F3F384FE90A4555B6024565B631532F9F3A314FE939E52C9F3B394FE9313D20E90A2002202A4656BF1A4666BF0A4757BF024767BF30502E9F36304FE938212C9F37384FE931532F9F9D314FE939E52C9F9E394FE92A4353BF1A4363BF30502E9F35304FE938212C9F39384FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E996FF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFB5FF20EA008000E8583358CF693B69CF74FF20EA57C0BFEA0080A0E90000D8ECDC
+/* T2GZS */
+:04A0000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC31003900858015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF768007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF683D68DF493749DF32322DDF22222DDF12122DDF3A3A2DDF0FCF74C237CF74C40A4454B0024464B03DCF74C0343720E931532F9F380F20E939E52C9F3C3D20E92A4454B21A4464B231803AEA0A2002200FCF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA60F20E939E52C9FA33D20E92A4454B41A4464B40A4555B0024565B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE92A4555B21A4565B20A4555B4024565B438212C9F3B394FE92A201A200A2002202A4656BF1A4666BF31532F9F36314FE939E52C9F37394FE930502E9FA7304FE938212C9FA8384FE90A4757BF024767BF31532F9FA4314FE939E52C9FA5394FE92A4353BF1A4363BF30502E9FA1304FE938212C9FA2384FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E992FF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFB2FF20EA008000E8583358CF693B69CF70FF20EA57C0BFEA0080A0E90000D8EC43
+/* T2GZSF */
+:04C8000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC310039008A8015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF7B8007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF683D68DF493749DF32322DDF22222DDF12122DDF3A3A2DDF0FCF74C237CF74C40A4454B0024464B03DCF74C0343720E931532F9F380F20E939E52C9F3C3D20E92A4454B21A4464B236803AEA0A2002200FCF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA60F20E939E52C9FA33D20E92A4454B41A4464B40A4555B0024565B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE938212C9F3B394FE92A4555B21A4565B20A4555B4024565B40FCF75C62A201A20A7304FE90A20022031532F9F310F20E939E52C9FA8384FE92A4555B61A4565B630502E9F36314FE938212C9F37394FE9008000E82A201A202A4656BF1A4666BF31532F9FA4314FE939E52C9FA5394FE90A4757BF024767BF31532F9FA1304FE939E52C9FA2384FE92A4353BF1A4363BF30502E9F35314FE938212C9F39394FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E98DFF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFADFF20EA008000E8583358CF693B69CF6BFF20EA57C0BFEA0080A0E90000D8EC56
+/* T2GZSA */
+:04C8000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC310039008A8015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF7B8007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF683D68DF493749DF32322DDF22222DDF12122DDF3A3A2DDF0FCF74C237CF74C40A4454B0024464B03DCF74C0343720E931532F9F380F20E939E52C9F3C3D20E92A4454B21A4464B236803AEA0A2002200FCF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA60F20E939E52C9FA33D20E92A4454B41A4464B40A4555B0024565B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE938212C9F3B394FE92A4555B21A4565B20A4555B4024565B40FCF74C62A201A20A7304FE90A20022031532F9F9C0F20E939E52C9FA8384FE92A4454B61A4464B630502E9F36314FE938212C9F37394FE9008000E82A201A202A4656BF1A4666BF31532F9FA4314FE939E52C9FA5394FE90A4757BF024767BF31532F9FA1304FE939E52C9FA2384FE92A4353BF1A4363BF30502E9F9D314FE938212C9F9E394FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E98DFF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFADFF20EA008000E8583358CF693B69CF6BFF20EA57C0BFEA0080A0E90000D8EC23
+/* T2GZSAF */
+:04E8000000008A98E9008000E80080A0E90000D8ECFF80C0E9008000E80A4050BF2A4060BF324151BF3A4161BFC36BD36B008A98E9737BC8EC96E241047B43A0E87353A0E8ADEE239F00E0510490E261043146B1E85141E0EC3967B1E8000446E27363A0E86141E0EC310039008E8015EA100420046151E0EC2F4160EA312039201F42A0E82A4252BF0F52A0E81A4262BF1E5160EA737BC8EC0E6160EA324050BD224060BD124151BD3A4161BDBF2F0EBD97E27B723220222012203A203548B1E83D59B1E8463146BF563156BFB3E22D9F008000E8663166BF473947BF573957BF673967BF7F8007EA244120E935003D0000E02D7333720CE38D2F1EBD4375F8EC35203D2043432DDF53532DDFAE1E0EBD58E33366483548BF583558BF683568BF493D49BF593D59BF693D69BF63632DDF4D7DF8EC59E300E0B83833BF2D733076183A41E93F53A0E805803DEA3743A0E83D63A0E85070F8EC2B503CE91F0FBCE8008000E85978F8EC008000E815C020E915C020E915C020E915C020E91E1241E91A2241E9463746DF563F56DF2B403DE9663D66DF1D3241E9673D67DF473747DF573F57DF2A4020E9593F59DF163020E9693D69DF483748DF583F58DF683D68DF493749DF32322DDF22222DDF12122DDF3A3A2DDF0FCF74C237CF74C40A4454B0024464B03DCF74C0343720E931532F9F380F20E939E52C9F3C3D20E92A4454B21A4464B23A803AEA0A2002200FCF75C02A201A2030502E9F32315FE938212C9F33395FE93DCF75C237CF75C431532F9FA60F20E939E52C9FA33D20E92A4454B41A4464B40A4555B0024565B088735EE92A201A20A03720E90A20022031532F9F3E304FE939E52C9F3F384FE930502E9F3A314FE938212C9F3B394FE92A4555B21A4565B20A4555B4024565B40FCF74C62A201A20A7304FE90A20022031532F9F9C0F20E939E52C9FA8384FE92A4454B61A4464B630502E9F36314FE938212C9F37394FE90A4555B6024565B63DCF75C62A201A202A4656BF1A4666BF31532F9FA4314FE939E52C9FA5394FE9313D20E90A2002200A4757BF024767BF30502E9FA1304FE938212C9FA2384FE931532F9F9D314FE939E52C9F9E394FE92A4353BF1A4363BF30502E9F35304FE938212C9F39384FE90A4858BF024868BF31532F9F803157E939E52C9F813957E92A4959BF1A4969BF30502E9F823057E938212C9F833857E931532F9F84315EE939E52C9F85395EE9867657E98A3620E9877757E98B3EBFEA803057E9813857E9823157E9867857E9833957E9877957E9301F5FE98A3420E98B3C20E9375060BD570D20E9355161BD2B5020E91D37E1EA1E35E1EA00E00E77245120E989FF20EA160E20E9572EBFEA0B46A0E81B56A0E82B66A0E80C47A0E81C57A0E82C67A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC36D736AD2B8060EC0C1C60EC3ED73EAD2C8060EC0B2BDEE81B80DEE8368036BD3E803EBD33D70BBD3BD71BBD468046CF578057CF663366CF473B47CF563356CF673B67CF0B48A0E81B58A0E82B68A0E80C49A0E81C59A0E82C69A0E80B001B002B0000E00C001C002C0000E00B651B652B6500E00C651C652C6500E00B1B60EC34D734AD2B8060EC0C1C60EC3CD73CAD2C8060EC0B2BDEE81B80DEE8348034BD3C803CBD33D70BBD3BD71BBD488048CF598059CF683368CF493B49CFA9FF20EA008000E8583358CF693B69CF67FF20EA57C0BFEA0080A0E90000D8ECEE
+:0000000001FF
-- 
cgit v1.2.3


From 52f97df5da1f94d2b7db1bb53a2f053ae162b649 Mon Sep 17 00:00:00 2001
From: Ben Hutchings <ben@decadent.org.uk>
Date: Sun, 23 Aug 2009 18:37:26 +0100
Subject: drm/r128: Use request_firmware() to load CCE microcode

Firmware blob looks like this:
    __be32 datah
    __be32 datal

Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/Kconfig         |   1 +
 drivers/gpu/drm/r128/r128_cce.c |  98 +++++++++++++++---------------
 firmware/Makefile               |   1 +
 firmware/WHENCE                 |  31 ++++++++++
 firmware/r128/r128_cce.bin.ihex | 129 ++++++++++++++++++++++++++++++++++++++++
 5 files changed, 210 insertions(+), 50 deletions(-)
 create mode 100644 firmware/r128/r128_cce.bin.ihex

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 10edc9b0022..a07abb818f5 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -36,6 +36,7 @@ config DRM_TDFX
 config DRM_R128
 	tristate "ATI Rage 128"
 	depends on DRM && PCI
+	select FW_LOADER
 	help
 	  Choose this option if you have an ATI Rage 128 graphics card.  If M
 	  is selected, the module will be called r128.  AGP support for
diff --git a/drivers/gpu/drm/r128/r128_cce.c b/drivers/gpu/drm/r128/r128_cce.c
index c75fd356404..15252f60bbd 100644
--- a/drivers/gpu/drm/r128/r128_cce.c
+++ b/drivers/gpu/drm/r128/r128_cce.c
@@ -29,6 +29,9 @@
  *    Gareth Hughes <gareth@valinux.com>
  */
 
+#include <linux/firmware.h>
+#include <linux/platform_device.h>
+
 #include "drmP.h"
 #include "drm.h"
 #include "r128_drm.h"
@@ -36,50 +39,9 @@
 
 #define R128_FIFO_DEBUG		0
 
-/* CCE microcode (from ATI) */
-static u32 r128_cce_microcode[] = {
-	0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0,
-	1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0,
-	599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1,
-	11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11,
-	262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28,
-	1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9,
-	30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656,
-	1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1,
-	15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071,
-	12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2,
-	46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1,
-	459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1,
-	18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1,
-	15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2,
-	268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1,
-	15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82,
-	1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729,
-	3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008,
-	1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0,
-	15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1,
-	180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1,
-	114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0,
-	33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370,
-	1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1,
-	14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793,
-	1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1,
-	198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1,
-	114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1,
-	1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1,
-	1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894,
-	16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14,
-	174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1,
-	33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1,
-	33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1,
-	409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-};
+#define FIRMWARE_NAME		"r128/r128_cce.bin"
+
+MODULE_FIRMWARE(FIRMWARE_NAME);
 
 static int R128_READ_PLL(struct drm_device * dev, int addr)
 {
@@ -176,20 +138,50 @@ static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv)
  */
 
 /* Load the microcode for the CCE */
-static void r128_cce_load_microcode(drm_r128_private_t * dev_priv)
+static int r128_cce_load_microcode(drm_r128_private_t *dev_priv)
 {
-	int i;
+	struct platform_device *pdev;
+	const struct firmware *fw;
+	const __be32 *fw_data;
+	int rc, i;
 
 	DRM_DEBUG("\n");
 
+	pdev = platform_device_register_simple("r128_cce", 0, NULL, 0);
+	if (IS_ERR(pdev)) {
+		printk(KERN_ERR "r128_cce: Failed to register firmware\n");
+		return PTR_ERR(pdev);
+	}
+	rc = request_firmware(&fw, FIRMWARE_NAME, &pdev->dev);
+	platform_device_unregister(pdev);
+	if (rc) {
+		printk(KERN_ERR "r128_cce: Failed to load firmware \"%s\"\n",
+		       FIRMWARE_NAME);
+		return rc;
+	}
+
+	if (fw->size != 256 * 8) {
+		printk(KERN_ERR
+		       "r128_cce: Bogus length %zu in firmware \"%s\"\n",
+		       fw->size, FIRMWARE_NAME);
+		rc = -EINVAL;
+		goto out_release;
+	}
+
 	r128_do_wait_for_idle(dev_priv);
 
+	fw_data = (const __be32 *)fw->data;
 	R128_WRITE(R128_PM4_MICROCODE_ADDR, 0);
 	for (i = 0; i < 256; i++) {
-		R128_WRITE(R128_PM4_MICROCODE_DATAH, r128_cce_microcode[i * 2]);
+		R128_WRITE(R128_PM4_MICROCODE_DATAH,
+			   be32_to_cpup(&fw_data[i * 2]));
 		R128_WRITE(R128_PM4_MICROCODE_DATAL,
-			   r128_cce_microcode[i * 2 + 1]);
+			   be32_to_cpup(&fw_data[i * 2 + 1]));
 	}
+
+out_release:
+	release_firmware(fw);
+	return rc;
 }
 
 /* Flush any pending commands to the CCE.  This should only be used just
@@ -350,6 +342,7 @@ static void r128_cce_init_ring_buffer(struct drm_device * dev,
 static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init)
 {
 	drm_r128_private_t *dev_priv;
+	int rc;
 
 	DRM_DEBUG("\n");
 
@@ -575,13 +568,18 @@ static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init)
 #endif
 
 	r128_cce_init_ring_buffer(dev, dev_priv);
-	r128_cce_load_microcode(dev_priv);
+	rc = r128_cce_load_microcode(dev_priv);
 
 	dev->dev_private = (void *)dev_priv;
 
 	r128_do_engine_reset(dev);
 
-	return 0;
+	if (rc) {
+		DRM_ERROR("Failed to load firmware!\n");
+		r128_do_cleanup_cce(dev);
+	}
+
+	return rc;
 }
 
 int r128_do_cleanup_cce(struct drm_device * dev)
diff --git a/firmware/Makefile b/firmware/Makefile
index 0e39f7e73ba..6ea4e3d9f05 100644
--- a/firmware/Makefile
+++ b/firmware/Makefile
@@ -43,6 +43,7 @@ fw-shipped-$(CONFIG_CHELSIO_T3) += cxgb3/t3b_psram-1.1.0.bin \
 				   cxgb3/t3c_psram-1.1.0.bin \
 				   cxgb3/t3fw-7.4.0.bin
 fw-shipped-$(CONFIG_DRM_MGA) += matrox/g200_warp.fw matrox/g400_warp.fw
+fw-shipped-$(CONFIG_DRM_R128) += r128/r128_cce.bin
 fw-shipped-$(CONFIG_DVB_AV7110) += av7110/bootcode.bin
 fw-shipped-$(CONFIG_DVB_TTUSB_BUDGET) += ttusb-budget/dspbootcode.bin
 fw-shipped-$(CONFIG_E100) += e100/d101m_ucode.bin e100/d101s_ucode.bin \
diff --git a/firmware/WHENCE b/firmware/WHENCE
index 5db34a88d6e..578d859c41f 100644
--- a/firmware/WHENCE
+++ b/firmware/WHENCE
@@ -730,3 +730,34 @@ OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 Found in hex form in kernel source.
 
 --------------------------------------------------------------------------
+
+Driver: r128 - ATI Rage 128
+
+File: r128/r128_cce.bin
+
+Licence:
+
+Copyright 2000 Advanced Micro Devices, Inc.
+
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+
+Found in decimal form in kernel source.
+
+--------------------------------------------------------------------------
diff --git a/firmware/r128/r128_cce.bin.ihex b/firmware/r128/r128_cce.bin.ihex
new file mode 100644
index 00000000000..4831315d7b9
--- /dev/null
+++ b/firmware/r128/r128_cce.bin.ihex
@@ -0,0 +1,129 @@
+:1000000000000000108038000000000010003800E0
+:10001000000000020000008E0000000200000091BD
+:1000200000000000402E2423000000006062124FF8
+:10003000000000002E2B596D000000007677753E01
+:1000400000000000898984820000000023BC8B0D21
+:10005000000000002323232300000000238DABB405
+:1000600000000000232323230000000100B028002B
+:100070000000000100032800000000010004C0008F
+:100080000000000100030800000000023660300E8E
+:100090000000000B00040000000000000000000051
+:1000A000000000010200151D0000000100001D0EEF
+:1000B00000000001000039D900000001000019D73C
+:1000C0000000000C0000001C00000001000019D618
+:1000D0000000000C0000001C0000000200000017DF
+:1000E0000000000B01200000000000000100358A24
+:1000F0000000000100064000000000090000001E92
+:100100000000000108D015B4000000101910100004
+:100110000000000300002000000000000000280094
+:1001200000000001000308000000000100003D0E77
+:10013000000000010000C8000000000A0000882A3A
+:10014000000000090000002A000000010200150F55
+:1001500000000002000028240000000100003D65AE
+:100160000000000100003D66000000020000002BBE
+:100170000000000100F32DB4000000012200D8BFF0
+:100180000000000100E088BF0000000C1333383786
+:1001900000000001020615650000000C0000003799
+:1001A00000000001020015640000000100003D662F
+:1001B000000000020000002E000000040020083AA9
+:1001C0000000000100080800000000010006C0FF58
+:1001D000000000040040003D000000010007C800CE
+:1001E00000000001000700FF000000030000000005
+:1001F0000000000C0000005C000000020000002E67
+:100200000000000C000000B00000000100003D767E
+:100210000000000100032800000000010000480069
+:1002200000000001000208000000000106001D0E91
+:1002300000000001000248000000000100028800E8
+:100240000000000100F3C5F80000000100100000EC
+:10025000000000060030004E0000000100003D6379
+:100260000000001080303DF0000000021000384314
+:1002700000000002000028430000000C000000B055
+:100280000000000100003D760000000100003D7705
+:100290000000000100003D0E0000000100003D0FC5
+:1002A000000000010050280000000006003000524D
+:1002B0000000001080303DF00000000100003DF81B
+:1002C00000000002000000520000000100053D0E89
+:1002D0000000000100103D0F00000002003000553A
+:1002E0000000000100003D700000000100001E89B8
+:1002F0000000000100003D710000000300003D729D
+:100300000000000C0000005C000000020000006221
+:100310000000000100003F280000000100003F270E
+:100320000000000100003E820000000100003E8845
+:100330000000000100003E660000000100003E6772
+:100340000000000100003E760000000100003E6851
+:100350000000000100003E690000000100003E6C4A
+:100360000000000000003E6D0000000100002800B9
+:1003700000000001005028000000000100003D685E
+:100380000000000100030800000000060000006EED
+:10039000000000010002C0000000000106303D62C4
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-- 
cgit v1.2.3


From 3f7dc91adef90a20f806282724c40d68d5b020aa Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 27 Aug 2009 11:10:15 +1000
Subject: drm/rs600/690: use autogenerated safe register tables.

This ports rs690 to the safe reg tables and makes rs600 also
use the same table.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/Makefile       |   5 +
 drivers/gpu/drm/radeon/radeon_asic.h  |   6 +-
 drivers/gpu/drm/radeon/reg_srcs/rs600 | 728 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/radeon/rs600.c        |   9 +
 drivers/gpu/drm/radeon/rs690.c        |  65 ---
 5 files changed, 745 insertions(+), 68 deletions(-)
 create mode 100644 drivers/gpu/drm/radeon/reg_srcs/rs600

diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index 8e1771889b4..b2213a576a8 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -17,10 +17,15 @@ $(obj)/rv515_reg_safe.h: $(src)/reg_srcs/rv515 $(obj)/mkregtable
 $(obj)/r300_reg_safe.h: $(src)/reg_srcs/r300 $(obj)/mkregtable
 	$(call if_changed,mkregtable)
 
+$(obj)/rs600_reg_safe.h: $(src)/reg_srcs/rs600 $(obj)/mkregtable
+	$(call if_changed,mkregtable)
+
 $(obj)/rv515.o: $(obj)/rv515_reg_safe.h
 
 $(obj)/r300.o: $(obj)/r300_reg_safe.h
 
+$(obj)/rs600.o: $(obj)/rs600_reg_safe.h
+
 radeon-$(CONFIG_DRM_RADEON_KMS) += radeon_device.o radeon_kms.o \
 	radeon_atombios.o radeon_agp.o atombios_crtc.o radeon_combios.o \
 	atom.o radeon_fence.o radeon_ttm.o radeon_object.o radeon_gart.o \
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 7ca6c13569b..8ace15156c4 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -266,6 +266,7 @@ static struct radeon_asic rs400_asic = {
 /*
  * rs600.
  */
+int rs600_init(struct radeon_device *rdev);
 void rs600_errata(struct radeon_device *rdev);
 void rs600_vram_info(struct radeon_device *rdev);
 int rs600_mc_init(struct radeon_device *rdev);
@@ -281,7 +282,7 @@ uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 void rs600_bandwidth_update(struct radeon_device *rdev);
 static struct radeon_asic rs600_asic = {
-	.init = &r300_init,
+	.init = &rs600_init,
 	.errata = &rs600_errata,
 	.vram_info = &rs600_vram_info,
 	.gpu_reset = &r300_gpu_reset,
@@ -316,7 +317,6 @@ static struct radeon_asic rs600_asic = {
 /*
  * rs690,rs740
  */
-int rs690_init(struct radeon_device *rdev);
 void rs690_errata(struct radeon_device *rdev);
 void rs690_vram_info(struct radeon_device *rdev);
 int rs690_mc_init(struct radeon_device *rdev);
@@ -325,7 +325,7 @@ uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 void rs690_bandwidth_update(struct radeon_device *rdev);
 static struct radeon_asic rs690_asic = {
-	.init = &rs690_init,
+	.init = &rs600_init,
 	.errata = &rs690_errata,
 	.vram_info = &rs690_vram_info,
 	.gpu_reset = &r300_gpu_reset,
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rs600 b/drivers/gpu/drm/radeon/reg_srcs/rs600
new file mode 100644
index 00000000000..498c581a328
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/rs600
@@ -0,0 +1,728 @@
+rs600 0x6d40
+0x1434 SRC_Y_X
+0x1438 DST_Y_X
+0x143C DST_HEIGHT_WIDTH
+0x146C DP_GUI_MASTER_CNTL
+0x1474 BRUSH_Y_X
+0x1478 DP_BRUSH_BKGD_CLR
+0x147C DP_BRUSH_FRGD_CLR
+0x1480 BRUSH_DATA0
+0x1484 BRUSH_DATA1
+0x1598 DST_WIDTH_HEIGHT
+0x15C0 CLR_CMP_CNTL
+0x15C4 CLR_CMP_CLR_SRC
+0x15C8 CLR_CMP_CLR_DST
+0x15CC CLR_CMP_MSK
+0x15D8 DP_SRC_FRGD_CLR
+0x15DC DP_SRC_BKGD_CLR
+0x1600 DST_LINE_START
+0x1604 DST_LINE_END
+0x1608 DST_LINE_PATCOUNT
+0x16C0 DP_CNTL
+0x16CC DP_WRITE_MSK
+0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
+0x16E8 DEFAULT_SC_BOTTOM_RIGHT
+0x16EC SC_TOP_LEFT
+0x16F0 SC_BOTTOM_RIGHT
+0x16F4 SRC_SC_BOTTOM_RIGHT
+0x1714 DSTCACHE_CTLSTAT
+0x1720 WAIT_UNTIL
+0x172C RBBM_GUICNTL
+0x1D98 VAP_VPORT_XSCALE
+0x1D9C VAP_VPORT_XOFFSET
+0x1DA0 VAP_VPORT_YSCALE
+0x1DA4 VAP_VPORT_YOFFSET
+0x1DA8 VAP_VPORT_ZSCALE
+0x1DAC VAP_VPORT_ZOFFSET
+0x2080 VAP_CNTL
+0x2090 VAP_OUT_VTX_FMT_0
+0x2094 VAP_OUT_VTX_FMT_1
+0x20B0 VAP_VTE_CNTL
+0x2138 VAP_VF_MIN_VTX_INDX
+0x2140 VAP_CNTL_STATUS
+0x2150 VAP_PROG_STREAM_CNTL_0
+0x2154 VAP_PROG_STREAM_CNTL_1
+0x2158 VAP_PROG_STREAM_CNTL_2
+0x215C VAP_PROG_STREAM_CNTL_3
+0x2160 VAP_PROG_STREAM_CNTL_4
+0x2164 VAP_PROG_STREAM_CNTL_5
+0x2168 VAP_PROG_STREAM_CNTL_6
+0x216C VAP_PROG_STREAM_CNTL_7
+0x2180 VAP_VTX_STATE_CNTL
+0x2184 VAP_VSM_VTX_ASSM
+0x2188 VAP_VTX_STATE_IND_REG_0
+0x218C VAP_VTX_STATE_IND_REG_1
+0x2190 VAP_VTX_STATE_IND_REG_2
+0x2194 VAP_VTX_STATE_IND_REG_3
+0x2198 VAP_VTX_STATE_IND_REG_4
+0x219C VAP_VTX_STATE_IND_REG_5
+0x21A0 VAP_VTX_STATE_IND_REG_6
+0x21A4 VAP_VTX_STATE_IND_REG_7
+0x21A8 VAP_VTX_STATE_IND_REG_8
+0x21AC VAP_VTX_STATE_IND_REG_9
+0x21B0 VAP_VTX_STATE_IND_REG_10
+0x21B4 VAP_VTX_STATE_IND_REG_11
+0x21B8 VAP_VTX_STATE_IND_REG_12
+0x21BC VAP_VTX_STATE_IND_REG_13
+0x21C0 VAP_VTX_STATE_IND_REG_14
+0x21C4 VAP_VTX_STATE_IND_REG_15
+0x21DC VAP_PSC_SGN_NORM_CNTL
+0x21E0 VAP_PROG_STREAM_CNTL_EXT_0
+0x21E4 VAP_PROG_STREAM_CNTL_EXT_1
+0x21E8 VAP_PROG_STREAM_CNTL_EXT_2
+0x21EC VAP_PROG_STREAM_CNTL_EXT_3
+0x21F0 VAP_PROG_STREAM_CNTL_EXT_4
+0x21F4 VAP_PROG_STREAM_CNTL_EXT_5
+0x21F8 VAP_PROG_STREAM_CNTL_EXT_6
+0x21FC VAP_PROG_STREAM_CNTL_EXT_7
+0x2200 VAP_PVS_VECTOR_INDX_REG
+0x2204 VAP_PVS_VECTOR_DATA_REG
+0x2208 VAP_PVS_VECTOR_DATA_REG_128
+0x221C VAP_CLIP_CNTL
+0x2220 VAP_GB_VERT_CLIP_ADJ
+0x2224 VAP_GB_VERT_DISC_ADJ
+0x2228 VAP_GB_HORZ_CLIP_ADJ
+0x222C VAP_GB_HORZ_DISC_ADJ
+0x2230 VAP_PVS_FLOW_CNTL_ADDRS_0
+0x2234 VAP_PVS_FLOW_CNTL_ADDRS_1
+0x2238 VAP_PVS_FLOW_CNTL_ADDRS_2
+0x223C VAP_PVS_FLOW_CNTL_ADDRS_3
+0x2240 VAP_PVS_FLOW_CNTL_ADDRS_4
+0x2244 VAP_PVS_FLOW_CNTL_ADDRS_5
+0x2248 VAP_PVS_FLOW_CNTL_ADDRS_6
+0x224C VAP_PVS_FLOW_CNTL_ADDRS_7
+0x2250 VAP_PVS_FLOW_CNTL_ADDRS_8
+0x2254 VAP_PVS_FLOW_CNTL_ADDRS_9
+0x2258 VAP_PVS_FLOW_CNTL_ADDRS_10
+0x225C VAP_PVS_FLOW_CNTL_ADDRS_11
+0x2260 VAP_PVS_FLOW_CNTL_ADDRS_12
+0x2264 VAP_PVS_FLOW_CNTL_ADDRS_13
+0x2268 VAP_PVS_FLOW_CNTL_ADDRS_14
+0x226C VAP_PVS_FLOW_CNTL_ADDRS_15
+0x2284 VAP_PVS_STATE_FLUSH_REG
+0x2288 VAP_PVS_VTX_TIMEOUT_REG
+0x2290 VAP_PVS_FLOW_CNTL_LOOP_INDEX_0
+0x2294 VAP_PVS_FLOW_CNTL_LOOP_INDEX_1
+0x2298 VAP_PVS_FLOW_CNTL_LOOP_INDEX_2
+0x229C VAP_PVS_FLOW_CNTL_LOOP_INDEX_3
+0x22A0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_4
+0x22A4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_5
+0x22A8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_6
+0x22AC VAP_PVS_FLOW_CNTL_LOOP_INDEX_7
+0x22B0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_8
+0x22B4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_9
+0x22B8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_10
+0x22BC VAP_PVS_FLOW_CNTL_LOOP_INDEX_11
+0x22C0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_12
+0x22C4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_13
+0x22C8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_14
+0x22CC VAP_PVS_FLOW_CNTL_LOOP_INDEX_15
+0x22D0 VAP_PVS_CODE_CNTL_0
+0x22D4 VAP_PVS_CONST_CNTL
+0x22D8 VAP_PVS_CODE_CNTL_1
+0x22DC VAP_PVS_FLOW_CNTL_OPC
+0x342C RB2D_DSTCACHE_CTLSTAT
+0x4000 GB_VAP_RASTER_VTX_FMT_0
+0x4004 GB_VAP_RASTER_VTX_FMT_1
+0x4008 GB_ENABLE
+0x401C GB_SELECT
+0x4020 GB_AA_CONFIG
+0x4024 GB_FIFO_SIZE
+0x4100 TX_INVALTAGS
+0x4200 GA_POINT_S0
+0x4204 GA_POINT_T0
+0x4208 GA_POINT_S1
+0x420C GA_POINT_T1
+0x4214 GA_TRIANGLE_STIPPLE
+0x421C GA_POINT_SIZE
+0x4230 GA_POINT_MINMAX
+0x4234 GA_LINE_CNTL
+0x4238 GA_LINE_STIPPLE_CONFIG
+0x4260 GA_LINE_STIPPLE_VALUE
+0x4264 GA_LINE_S0
+0x4268 GA_LINE_S1
+0x4278 GA_COLOR_CONTROL
+0x427C GA_SOLID_RG
+0x4280 GA_SOLID_BA
+0x4288 GA_POLY_MODE
+0x428C GA_ROUND_MODE
+0x4290 GA_OFFSET
+0x4294 GA_FOG_SCALE
+0x4298 GA_FOG_OFFSET
+0x42A0 SU_TEX_WRAP
+0x42A4 SU_POLY_OFFSET_FRONT_SCALE
+0x42A8 SU_POLY_OFFSET_FRONT_OFFSET
+0x42AC SU_POLY_OFFSET_BACK_SCALE
+0x42B0 SU_POLY_OFFSET_BACK_OFFSET 
+0x42B4 SU_POLY_OFFSET_ENABLE
+0x42B8 SU_CULL_MODE
+0x42C0 SU_DEPTH_SCALE
+0x42C4 SU_DEPTH_OFFSET
+0x42C8 SU_REG_DEST
+0x4300 RS_COUNT
+0x4304 RS_INST_COUNT
+0x4310 RS_IP_0
+0x4314 RS_IP_1
+0x4318 RS_IP_2
+0x431C RS_IP_3
+0x4320 RS_IP_4
+0x4324 RS_IP_5
+0x4328 RS_IP_6
+0x432C RS_IP_7
+0x4330 RS_INST_0
+0x4334 RS_INST_1
+0x4338 RS_INST_2
+0x433C RS_INST_3
+0x4340 RS_INST_4
+0x4344 RS_INST_5
+0x4348 RS_INST_6
+0x434C RS_INST_7
+0x4350 RS_INST_8
+0x4354 RS_INST_9
+0x4358 RS_INST_10
+0x435C RS_INST_11
+0x4360 RS_INST_12
+0x4364 RS_INST_13
+0x4368 RS_INST_14
+0x436C RS_INST_15
+0x43A4 SC_HYPERZ_EN
+0x43A8 SC_EDGERULE
+0x43B0 SC_CLIP_0_A
+0x43B4 SC_CLIP_0_B
+0x43B8 SC_CLIP_1_A
+0x43BC SC_CLIP_1_B
+0x43C0 SC_CLIP_2_A
+0x43C4 SC_CLIP_2_B
+0x43C8 SC_CLIP_3_A
+0x43CC SC_CLIP_3_B
+0x43D0 SC_CLIP_RULE
+0x43E0 SC_SCISSOR0
+0x43E8 SC_SCREENDOOR
+0x4440 TX_FILTER1_0
+0x4444 TX_FILTER1_1
+0x4448 TX_FILTER1_2
+0x444C TX_FILTER1_3
+0x4450 TX_FILTER1_4
+0x4454 TX_FILTER1_5
+0x4458 TX_FILTER1_6
+0x445C TX_FILTER1_7
+0x4460 TX_FILTER1_8
+0x4464 TX_FILTER1_9
+0x4468 TX_FILTER1_10
+0x446C TX_FILTER1_11
+0x4470 TX_FILTER1_12
+0x4474 TX_FILTER1_13
+0x4478 TX_FILTER1_14
+0x447C TX_FILTER1_15
+0x4580 TX_CHROMA_KEY_0
+0x4584 TX_CHROMA_KEY_1
+0x4588 TX_CHROMA_KEY_2
+0x458C TX_CHROMA_KEY_3
+0x4590 TX_CHROMA_KEY_4
+0x4594 TX_CHROMA_KEY_5
+0x4598 TX_CHROMA_KEY_6
+0x459C TX_CHROMA_KEY_7
+0x45A0 TX_CHROMA_KEY_8
+0x45A4 TX_CHROMA_KEY_9
+0x45A8 TX_CHROMA_KEY_10
+0x45AC TX_CHROMA_KEY_11
+0x45B0 TX_CHROMA_KEY_12
+0x45B4 TX_CHROMA_KEY_13
+0x45B8 TX_CHROMA_KEY_14
+0x45BC TX_CHROMA_KEY_15
+0x45C0 TX_BORDER_COLOR_0
+0x45C4 TX_BORDER_COLOR_1
+0x45C8 TX_BORDER_COLOR_2
+0x45CC TX_BORDER_COLOR_3
+0x45D0 TX_BORDER_COLOR_4
+0x45D4 TX_BORDER_COLOR_5
+0x45D8 TX_BORDER_COLOR_6
+0x45DC TX_BORDER_COLOR_7
+0x45E0 TX_BORDER_COLOR_8
+0x45E4 TX_BORDER_COLOR_9
+0x45E8 TX_BORDER_COLOR_10
+0x45EC TX_BORDER_COLOR_11
+0x45F0 TX_BORDER_COLOR_12
+0x45F4 TX_BORDER_COLOR_13
+0x45F8 TX_BORDER_COLOR_14
+0x45FC TX_BORDER_COLOR_15
+0x4600 US_CONFIG
+0x4604 US_PIXSIZE
+0x4608 US_CODE_OFFSET
+0x460C US_RESET
+0x4610 US_CODE_ADDR_0
+0x4614 US_CODE_ADDR_1
+0x4618 US_CODE_ADDR_2
+0x461C US_CODE_ADDR_3
+0x4620 US_TEX_INST_0
+0x4624 US_TEX_INST_1
+0x4628 US_TEX_INST_2
+0x462C US_TEX_INST_3
+0x4630 US_TEX_INST_4
+0x4634 US_TEX_INST_5
+0x4638 US_TEX_INST_6
+0x463C US_TEX_INST_7
+0x4640 US_TEX_INST_8
+0x4644 US_TEX_INST_9
+0x4648 US_TEX_INST_10
+0x464C US_TEX_INST_11
+0x4650 US_TEX_INST_12
+0x4654 US_TEX_INST_13
+0x4658 US_TEX_INST_14
+0x465C US_TEX_INST_15
+0x4660 US_TEX_INST_16
+0x4664 US_TEX_INST_17
+0x4668 US_TEX_INST_18
+0x466C US_TEX_INST_19
+0x4670 US_TEX_INST_20
+0x4674 US_TEX_INST_21
+0x4678 US_TEX_INST_22
+0x467C US_TEX_INST_23
+0x4680 US_TEX_INST_24
+0x4684 US_TEX_INST_25
+0x4688 US_TEX_INST_26
+0x468C US_TEX_INST_27
+0x4690 US_TEX_INST_28
+0x4694 US_TEX_INST_29
+0x4698 US_TEX_INST_30
+0x469C US_TEX_INST_31
+0x46A4 US_OUT_FMT_0
+0x46A8 US_OUT_FMT_1
+0x46AC US_OUT_FMT_2
+0x46B0 US_OUT_FMT_3
+0x46B4 US_W_FMT
+0x46C0 US_ALU_RGB_ADDR_0
+0x46C4 US_ALU_RGB_ADDR_1
+0x46C8 US_ALU_RGB_ADDR_2
+0x46CC US_ALU_RGB_ADDR_3
+0x46D0 US_ALU_RGB_ADDR_4
+0x46D4 US_ALU_RGB_ADDR_5
+0x46D8 US_ALU_RGB_ADDR_6
+0x46DC US_ALU_RGB_ADDR_7
+0x46E0 US_ALU_RGB_ADDR_8
+0x46E4 US_ALU_RGB_ADDR_9
+0x46E8 US_ALU_RGB_ADDR_10
+0x46EC US_ALU_RGB_ADDR_11
+0x46F0 US_ALU_RGB_ADDR_12
+0x46F4 US_ALU_RGB_ADDR_13
+0x46F8 US_ALU_RGB_ADDR_14
+0x46FC US_ALU_RGB_ADDR_15
+0x4700 US_ALU_RGB_ADDR_16
+0x4704 US_ALU_RGB_ADDR_17
+0x4708 US_ALU_RGB_ADDR_18
+0x470C US_ALU_RGB_ADDR_19
+0x4710 US_ALU_RGB_ADDR_20
+0x4714 US_ALU_RGB_ADDR_21
+0x4718 US_ALU_RGB_ADDR_22
+0x471C US_ALU_RGB_ADDR_23
+0x4720 US_ALU_RGB_ADDR_24
+0x4724 US_ALU_RGB_ADDR_25
+0x4728 US_ALU_RGB_ADDR_26
+0x472C US_ALU_RGB_ADDR_27
+0x4730 US_ALU_RGB_ADDR_28
+0x4734 US_ALU_RGB_ADDR_29
+0x4738 US_ALU_RGB_ADDR_30
+0x473C US_ALU_RGB_ADDR_31
+0x4740 US_ALU_RGB_ADDR_32
+0x4744 US_ALU_RGB_ADDR_33
+0x4748 US_ALU_RGB_ADDR_34
+0x474C US_ALU_RGB_ADDR_35
+0x4750 US_ALU_RGB_ADDR_36
+0x4754 US_ALU_RGB_ADDR_37
+0x4758 US_ALU_RGB_ADDR_38
+0x475C US_ALU_RGB_ADDR_39
+0x4760 US_ALU_RGB_ADDR_40
+0x4764 US_ALU_RGB_ADDR_41
+0x4768 US_ALU_RGB_ADDR_42
+0x476C US_ALU_RGB_ADDR_43
+0x4770 US_ALU_RGB_ADDR_44
+0x4774 US_ALU_RGB_ADDR_45
+0x4778 US_ALU_RGB_ADDR_46
+0x477C US_ALU_RGB_ADDR_47
+0x4780 US_ALU_RGB_ADDR_48
+0x4784 US_ALU_RGB_ADDR_49
+0x4788 US_ALU_RGB_ADDR_50
+0x478C US_ALU_RGB_ADDR_51
+0x4790 US_ALU_RGB_ADDR_52
+0x4794 US_ALU_RGB_ADDR_53
+0x4798 US_ALU_RGB_ADDR_54
+0x479C US_ALU_RGB_ADDR_55
+0x47A0 US_ALU_RGB_ADDR_56
+0x47A4 US_ALU_RGB_ADDR_57
+0x47A8 US_ALU_RGB_ADDR_58
+0x47AC US_ALU_RGB_ADDR_59
+0x47B0 US_ALU_RGB_ADDR_60
+0x47B4 US_ALU_RGB_ADDR_61
+0x47B8 US_ALU_RGB_ADDR_62
+0x47BC US_ALU_RGB_ADDR_63
+0x47C0 US_ALU_ALPHA_ADDR_0
+0x47C4 US_ALU_ALPHA_ADDR_1
+0x47C8 US_ALU_ALPHA_ADDR_2
+0x47CC US_ALU_ALPHA_ADDR_3
+0x47D0 US_ALU_ALPHA_ADDR_4
+0x47D4 US_ALU_ALPHA_ADDR_5
+0x47D8 US_ALU_ALPHA_ADDR_6
+0x47DC US_ALU_ALPHA_ADDR_7
+0x47E0 US_ALU_ALPHA_ADDR_8
+0x47E4 US_ALU_ALPHA_ADDR_9
+0x47E8 US_ALU_ALPHA_ADDR_10
+0x47EC US_ALU_ALPHA_ADDR_11
+0x47F0 US_ALU_ALPHA_ADDR_12
+0x47F4 US_ALU_ALPHA_ADDR_13
+0x47F8 US_ALU_ALPHA_ADDR_14
+0x47FC US_ALU_ALPHA_ADDR_15
+0x4800 US_ALU_ALPHA_ADDR_16
+0x4804 US_ALU_ALPHA_ADDR_17
+0x4808 US_ALU_ALPHA_ADDR_18
+0x480C US_ALU_ALPHA_ADDR_19
+0x4810 US_ALU_ALPHA_ADDR_20
+0x4814 US_ALU_ALPHA_ADDR_21
+0x4818 US_ALU_ALPHA_ADDR_22
+0x481C US_ALU_ALPHA_ADDR_23
+0x4820 US_ALU_ALPHA_ADDR_24
+0x4824 US_ALU_ALPHA_ADDR_25
+0x4828 US_ALU_ALPHA_ADDR_26
+0x482C US_ALU_ALPHA_ADDR_27
+0x4830 US_ALU_ALPHA_ADDR_28
+0x4834 US_ALU_ALPHA_ADDR_29
+0x4838 US_ALU_ALPHA_ADDR_30
+0x483C US_ALU_ALPHA_ADDR_31
+0x4840 US_ALU_ALPHA_ADDR_32
+0x4844 US_ALU_ALPHA_ADDR_33
+0x4848 US_ALU_ALPHA_ADDR_34
+0x484C US_ALU_ALPHA_ADDR_35
+0x4850 US_ALU_ALPHA_ADDR_36
+0x4854 US_ALU_ALPHA_ADDR_37
+0x4858 US_ALU_ALPHA_ADDR_38
+0x485C US_ALU_ALPHA_ADDR_39
+0x4860 US_ALU_ALPHA_ADDR_40
+0x4864 US_ALU_ALPHA_ADDR_41
+0x4868 US_ALU_ALPHA_ADDR_42
+0x486C US_ALU_ALPHA_ADDR_43
+0x4870 US_ALU_ALPHA_ADDR_44
+0x4874 US_ALU_ALPHA_ADDR_45
+0x4878 US_ALU_ALPHA_ADDR_46
+0x487C US_ALU_ALPHA_ADDR_47
+0x4880 US_ALU_ALPHA_ADDR_48
+0x4884 US_ALU_ALPHA_ADDR_49
+0x4888 US_ALU_ALPHA_ADDR_50
+0x488C US_ALU_ALPHA_ADDR_51
+0x4890 US_ALU_ALPHA_ADDR_52
+0x4894 US_ALU_ALPHA_ADDR_53
+0x4898 US_ALU_ALPHA_ADDR_54
+0x489C US_ALU_ALPHA_ADDR_55
+0x48A0 US_ALU_ALPHA_ADDR_56
+0x48A4 US_ALU_ALPHA_ADDR_57
+0x48A8 US_ALU_ALPHA_ADDR_58
+0x48AC US_ALU_ALPHA_ADDR_59
+0x48B0 US_ALU_ALPHA_ADDR_60
+0x48B4 US_ALU_ALPHA_ADDR_61
+0x48B8 US_ALU_ALPHA_ADDR_62
+0x48BC US_ALU_ALPHA_ADDR_63
+0x48C0 US_ALU_RGB_INST_0
+0x48C4 US_ALU_RGB_INST_1
+0x48C8 US_ALU_RGB_INST_2
+0x48CC US_ALU_RGB_INST_3
+0x48D0 US_ALU_RGB_INST_4
+0x48D4 US_ALU_RGB_INST_5
+0x48D8 US_ALU_RGB_INST_6
+0x48DC US_ALU_RGB_INST_7
+0x48E0 US_ALU_RGB_INST_8
+0x48E4 US_ALU_RGB_INST_9
+0x48E8 US_ALU_RGB_INST_10
+0x48EC US_ALU_RGB_INST_11
+0x48F0 US_ALU_RGB_INST_12
+0x48F4 US_ALU_RGB_INST_13
+0x48F8 US_ALU_RGB_INST_14
+0x48FC US_ALU_RGB_INST_15
+0x4900 US_ALU_RGB_INST_16
+0x4904 US_ALU_RGB_INST_17
+0x4908 US_ALU_RGB_INST_18
+0x490C US_ALU_RGB_INST_19
+0x4910 US_ALU_RGB_INST_20
+0x4914 US_ALU_RGB_INST_21
+0x4918 US_ALU_RGB_INST_22
+0x491C US_ALU_RGB_INST_23
+0x4920 US_ALU_RGB_INST_24
+0x4924 US_ALU_RGB_INST_25
+0x4928 US_ALU_RGB_INST_26
+0x492C US_ALU_RGB_INST_27
+0x4930 US_ALU_RGB_INST_28
+0x4934 US_ALU_RGB_INST_29
+0x4938 US_ALU_RGB_INST_30
+0x493C US_ALU_RGB_INST_31
+0x4940 US_ALU_RGB_INST_32
+0x4944 US_ALU_RGB_INST_33
+0x4948 US_ALU_RGB_INST_34
+0x494C US_ALU_RGB_INST_35
+0x4950 US_ALU_RGB_INST_36
+0x4954 US_ALU_RGB_INST_37
+0x4958 US_ALU_RGB_INST_38
+0x495C US_ALU_RGB_INST_39
+0x4960 US_ALU_RGB_INST_40
+0x4964 US_ALU_RGB_INST_41
+0x4968 US_ALU_RGB_INST_42
+0x496C US_ALU_RGB_INST_43
+0x4970 US_ALU_RGB_INST_44
+0x4974 US_ALU_RGB_INST_45
+0x4978 US_ALU_RGB_INST_46
+0x497C US_ALU_RGB_INST_47
+0x4980 US_ALU_RGB_INST_48
+0x4984 US_ALU_RGB_INST_49
+0x4988 US_ALU_RGB_INST_50
+0x498C US_ALU_RGB_INST_51
+0x4990 US_ALU_RGB_INST_52
+0x4994 US_ALU_RGB_INST_53
+0x4998 US_ALU_RGB_INST_54
+0x499C US_ALU_RGB_INST_55
+0x49A0 US_ALU_RGB_INST_56
+0x49A4 US_ALU_RGB_INST_57
+0x49A8 US_ALU_RGB_INST_58
+0x49AC US_ALU_RGB_INST_59
+0x49B0 US_ALU_RGB_INST_60
+0x49B4 US_ALU_RGB_INST_61
+0x49B8 US_ALU_RGB_INST_62
+0x49BC US_ALU_RGB_INST_63
+0x49C0 US_ALU_ALPHA_INST_0
+0x49C4 US_ALU_ALPHA_INST_1
+0x49C8 US_ALU_ALPHA_INST_2
+0x49CC US_ALU_ALPHA_INST_3
+0x49D0 US_ALU_ALPHA_INST_4
+0x49D4 US_ALU_ALPHA_INST_5
+0x49D8 US_ALU_ALPHA_INST_6
+0x49DC US_ALU_ALPHA_INST_7
+0x49E0 US_ALU_ALPHA_INST_8
+0x49E4 US_ALU_ALPHA_INST_9
+0x49E8 US_ALU_ALPHA_INST_10
+0x49EC US_ALU_ALPHA_INST_11
+0x49F0 US_ALU_ALPHA_INST_12
+0x49F4 US_ALU_ALPHA_INST_13
+0x49F8 US_ALU_ALPHA_INST_14
+0x49FC US_ALU_ALPHA_INST_15
+0x4A00 US_ALU_ALPHA_INST_16
+0x4A04 US_ALU_ALPHA_INST_17
+0x4A08 US_ALU_ALPHA_INST_18
+0x4A0C US_ALU_ALPHA_INST_19
+0x4A10 US_ALU_ALPHA_INST_20
+0x4A14 US_ALU_ALPHA_INST_21
+0x4A18 US_ALU_ALPHA_INST_22
+0x4A1C US_ALU_ALPHA_INST_23
+0x4A20 US_ALU_ALPHA_INST_24
+0x4A24 US_ALU_ALPHA_INST_25
+0x4A28 US_ALU_ALPHA_INST_26
+0x4A2C US_ALU_ALPHA_INST_27
+0x4A30 US_ALU_ALPHA_INST_28
+0x4A34 US_ALU_ALPHA_INST_29
+0x4A38 US_ALU_ALPHA_INST_30
+0x4A3C US_ALU_ALPHA_INST_31
+0x4A40 US_ALU_ALPHA_INST_32
+0x4A44 US_ALU_ALPHA_INST_33
+0x4A48 US_ALU_ALPHA_INST_34
+0x4A4C US_ALU_ALPHA_INST_35
+0x4A50 US_ALU_ALPHA_INST_36
+0x4A54 US_ALU_ALPHA_INST_37
+0x4A58 US_ALU_ALPHA_INST_38
+0x4A5C US_ALU_ALPHA_INST_39
+0x4A60 US_ALU_ALPHA_INST_40
+0x4A64 US_ALU_ALPHA_INST_41
+0x4A68 US_ALU_ALPHA_INST_42
+0x4A6C US_ALU_ALPHA_INST_43
+0x4A70 US_ALU_ALPHA_INST_44
+0x4A74 US_ALU_ALPHA_INST_45
+0x4A78 US_ALU_ALPHA_INST_46
+0x4A7C US_ALU_ALPHA_INST_47
+0x4A80 US_ALU_ALPHA_INST_48
+0x4A84 US_ALU_ALPHA_INST_49
+0x4A88 US_ALU_ALPHA_INST_50
+0x4A8C US_ALU_ALPHA_INST_51
+0x4A90 US_ALU_ALPHA_INST_52
+0x4A94 US_ALU_ALPHA_INST_53
+0x4A98 US_ALU_ALPHA_INST_54
+0x4A9C US_ALU_ALPHA_INST_55
+0x4AA0 US_ALU_ALPHA_INST_56
+0x4AA4 US_ALU_ALPHA_INST_57
+0x4AA8 US_ALU_ALPHA_INST_58
+0x4AAC US_ALU_ALPHA_INST_59
+0x4AB0 US_ALU_ALPHA_INST_60
+0x4AB4 US_ALU_ALPHA_INST_61
+0x4AB8 US_ALU_ALPHA_INST_62
+0x4ABC US_ALU_ALPHA_INST_63
+0x4BC0 FG_FOG_BLEND
+0x4BC4 FG_FOG_FACTOR
+0x4BC8 FG_FOG_COLOR_R
+0x4BCC FG_FOG_COLOR_G
+0x4BD0 FG_FOG_COLOR_B
+0x4BD4 FG_ALPHA_FUNC
+0x4BD8 FG_DEPTH_SRC
+0x4C00 US_ALU_CONST_R_0
+0x4C04 US_ALU_CONST_G_0
+0x4C08 US_ALU_CONST_B_0
+0x4C0C US_ALU_CONST_A_0
+0x4C10 US_ALU_CONST_R_1
+0x4C14 US_ALU_CONST_G_1
+0x4C18 US_ALU_CONST_B_1
+0x4C1C US_ALU_CONST_A_1
+0x4C20 US_ALU_CONST_R_2
+0x4C24 US_ALU_CONST_G_2
+0x4C28 US_ALU_CONST_B_2
+0x4C2C US_ALU_CONST_A_2
+0x4C30 US_ALU_CONST_R_3
+0x4C34 US_ALU_CONST_G_3
+0x4C38 US_ALU_CONST_B_3
+0x4C3C US_ALU_CONST_A_3
+0x4C40 US_ALU_CONST_R_4
+0x4C44 US_ALU_CONST_G_4
+0x4C48 US_ALU_CONST_B_4
+0x4C4C US_ALU_CONST_A_4
+0x4C50 US_ALU_CONST_R_5
+0x4C54 US_ALU_CONST_G_5
+0x4C58 US_ALU_CONST_B_5
+0x4C5C US_ALU_CONST_A_5
+0x4C60 US_ALU_CONST_R_6
+0x4C64 US_ALU_CONST_G_6
+0x4C68 US_ALU_CONST_B_6
+0x4C6C US_ALU_CONST_A_6
+0x4C70 US_ALU_CONST_R_7
+0x4C74 US_ALU_CONST_G_7
+0x4C78 US_ALU_CONST_B_7
+0x4C7C US_ALU_CONST_A_7
+0x4C80 US_ALU_CONST_R_8
+0x4C84 US_ALU_CONST_G_8
+0x4C88 US_ALU_CONST_B_8
+0x4C8C US_ALU_CONST_A_8
+0x4C90 US_ALU_CONST_R_9
+0x4C94 US_ALU_CONST_G_9
+0x4C98 US_ALU_CONST_B_9
+0x4C9C US_ALU_CONST_A_9
+0x4CA0 US_ALU_CONST_R_10
+0x4CA4 US_ALU_CONST_G_10
+0x4CA8 US_ALU_CONST_B_10
+0x4CAC US_ALU_CONST_A_10
+0x4CB0 US_ALU_CONST_R_11
+0x4CB4 US_ALU_CONST_G_11
+0x4CB8 US_ALU_CONST_B_11
+0x4CBC US_ALU_CONST_A_11
+0x4CC0 US_ALU_CONST_R_12
+0x4CC4 US_ALU_CONST_G_12
+0x4CC8 US_ALU_CONST_B_12
+0x4CCC US_ALU_CONST_A_12
+0x4CD0 US_ALU_CONST_R_13
+0x4CD4 US_ALU_CONST_G_13
+0x4CD8 US_ALU_CONST_B_13
+0x4CDC US_ALU_CONST_A_13
+0x4CE0 US_ALU_CONST_R_14
+0x4CE4 US_ALU_CONST_G_14
+0x4CE8 US_ALU_CONST_B_14
+0x4CEC US_ALU_CONST_A_14
+0x4CF0 US_ALU_CONST_R_15
+0x4CF4 US_ALU_CONST_G_15
+0x4CF8 US_ALU_CONST_B_15
+0x4CFC US_ALU_CONST_A_15
+0x4D00 US_ALU_CONST_R_16
+0x4D04 US_ALU_CONST_G_16
+0x4D08 US_ALU_CONST_B_16
+0x4D0C US_ALU_CONST_A_16
+0x4D10 US_ALU_CONST_R_17
+0x4D14 US_ALU_CONST_G_17
+0x4D18 US_ALU_CONST_B_17
+0x4D1C US_ALU_CONST_A_17
+0x4D20 US_ALU_CONST_R_18
+0x4D24 US_ALU_CONST_G_18
+0x4D28 US_ALU_CONST_B_18
+0x4D2C US_ALU_CONST_A_18
+0x4D30 US_ALU_CONST_R_19
+0x4D34 US_ALU_CONST_G_19
+0x4D38 US_ALU_CONST_B_19
+0x4D3C US_ALU_CONST_A_19
+0x4D40 US_ALU_CONST_R_20
+0x4D44 US_ALU_CONST_G_20
+0x4D48 US_ALU_CONST_B_20
+0x4D4C US_ALU_CONST_A_20
+0x4D50 US_ALU_CONST_R_21
+0x4D54 US_ALU_CONST_G_21
+0x4D58 US_ALU_CONST_B_21
+0x4D5C US_ALU_CONST_A_21
+0x4D60 US_ALU_CONST_R_22
+0x4D64 US_ALU_CONST_G_22
+0x4D68 US_ALU_CONST_B_22
+0x4D6C US_ALU_CONST_A_22
+0x4D70 US_ALU_CONST_R_23
+0x4D74 US_ALU_CONST_G_23
+0x4D78 US_ALU_CONST_B_23
+0x4D7C US_ALU_CONST_A_23
+0x4D80 US_ALU_CONST_R_24
+0x4D84 US_ALU_CONST_G_24
+0x4D88 US_ALU_CONST_B_24
+0x4D8C US_ALU_CONST_A_24
+0x4D90 US_ALU_CONST_R_25
+0x4D94 US_ALU_CONST_G_25
+0x4D98 US_ALU_CONST_B_25
+0x4D9C US_ALU_CONST_A_25
+0x4DA0 US_ALU_CONST_R_26
+0x4DA4 US_ALU_CONST_G_26
+0x4DA8 US_ALU_CONST_B_26
+0x4DAC US_ALU_CONST_A_26
+0x4DB0 US_ALU_CONST_R_27
+0x4DB4 US_ALU_CONST_G_27
+0x4DB8 US_ALU_CONST_B_27
+0x4DBC US_ALU_CONST_A_27
+0x4DC0 US_ALU_CONST_R_28
+0x4DC4 US_ALU_CONST_G_28
+0x4DC8 US_ALU_CONST_B_28
+0x4DCC US_ALU_CONST_A_28
+0x4DD0 US_ALU_CONST_R_29
+0x4DD4 US_ALU_CONST_G_29
+0x4DD8 US_ALU_CONST_B_29
+0x4DDC US_ALU_CONST_A_29
+0x4DE0 US_ALU_CONST_R_30
+0x4DE4 US_ALU_CONST_G_30
+0x4DE8 US_ALU_CONST_B_30
+0x4DEC US_ALU_CONST_A_30
+0x4DF0 US_ALU_CONST_R_31
+0x4DF4 US_ALU_CONST_G_31
+0x4DF8 US_ALU_CONST_B_31
+0x4DFC US_ALU_CONST_A_31
+0x4E04 RB3D_BLENDCNTL_R3
+0x4E08 RB3D_ABLENDCNTL_R3
+0x4E0C RB3D_COLOR_CHANNEL_MASK
+0x4E10 RB3D_CONSTANT_COLOR
+0x4E14 RB3D_COLOR_CLEAR_VALUE
+0x4E18 RB3D_ROPCNTL_R3
+0x4E1C RB3D_CLRCMP_FLIPE_R3
+0x4E20 RB3D_CLRCMP_CLR_R3
+0x4E24 RB3D_CLRCMP_MSK_R3
+0x4E48 RB3D_DEBUG_CTL
+0x4E4C RB3D_DSTCACHE_CTLSTAT_R3
+0x4E50 RB3D_DITHER_CTL
+0x4E54 RB3D_CMASK_OFFSET0
+0x4E58 RB3D_CMASK_OFFSET1
+0x4E5C RB3D_CMASK_OFFSET2
+0x4E60 RB3D_CMASK_OFFSET3
+0x4E64 RB3D_CMASK_PITCH0
+0x4E68 RB3D_CMASK_PITCH1
+0x4E6C RB3D_CMASK_PITCH2
+0x4E70 RB3D_CMASK_PITCH3
+0x4E74 RB3D_CMASK_WRINDEX
+0x4E78 RB3D_CMASK_DWORD
+0x4E7C RB3D_CMASK_RDINDEX
+0x4E80 RB3D_AARESOLVE_OFFSET
+0x4E84 RB3D_AARESOLVE_PITCH
+0x4E88 RB3D_AARESOLVE_CTL
+0x4F04 ZB_ZSTENCILCNTL
+0x4F08 ZB_STENCILREFMASK
+0x4F14 ZB_ZTOP
+0x4F18 ZB_ZCACHE_CTLSTAT
+0x4F1C ZB_BW_CNTL
+0x4F28 ZB_DEPTHCLEARVALUE
+0x4F30 ZB_ZMASK_OFFSET
+0x4F34 ZB_ZMASK_PITCH
+0x4F38 ZB_ZMASK_WRINDEX
+0x4F3C ZB_ZMASK_DWORD
+0x4F40 ZB_ZMASK_RDINDEX
+0x4F44 ZB_HIZ_OFFSET
+0x4F48 ZB_HIZ_WRINDEX
+0x4F4C ZB_HIZ_DWORD
+0x4F50 ZB_HIZ_RDINDEX
+0x4F54 ZB_HIZ_PITCH
+0x4F58 ZB_ZPASS_DATA
+0x4F60 ZB_DEPTHXY_OFFSET
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 7e8ce983a90..1b8d62f5e73 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -29,6 +29,8 @@
 #include "radeon_reg.h"
 #include "radeon.h"
 
+#include "rs600_reg_safe.h"
+
 /* rs600 depends on : */
 void r100_hdp_reset(struct radeon_device *rdev);
 int r100_gui_wait_for_idle(struct radeon_device *rdev);
@@ -409,3 +411,10 @@ void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 		((reg) & RS600_MC_ADDR_MASK));
 	WREG32(RS600_MC_DATA, v);
 }
+
+int rs600_init(struct radeon_device *rdev)
+{
+	rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
+	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
+	return 0;
+}
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index bc6b7c5339b..839595b0072 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -652,68 +652,3 @@ void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 	WREG32(RS690_MC_DATA, v);
 	WREG32(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);
 }
-
-static const unsigned rs690_reg_safe_bm[219] = {
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0x17FF1FFF,0xFFFFFFFC,0xFFFFFFFF,0xFF30FFBF,
-	0xFFFFFFF8,0xC3E6FFFF,0xFFFFF6DF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFF03F,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFEFCE,0xF00EBFFF,0x007C0000,
-	0xF0000078,0xFF000009,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFF7FF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFC78,0xFFFFFFFF,0xFFFFFFFE,0xFFFFFFFF,
-	0x38FF8F50,0xFFF88082,0xF000000C,0xFAE009FF,
-	0x0000FFFF,0xFFFFFFFF,0xFFFFFFFF,0x00000000,
-	0x00000000,0x0000C100,0x00000000,0x00000000,
-	0x00000000,0x00000000,0x00000000,0x00000000,
-	0x00000000,0xFFFF0000,0xFFFFFFFF,0xFF80FFFF,
-	0x00000000,0x00000000,0x00000000,0x00000000,
-	0x0003FC01,0xFFFFFFF8,0xFE800B19,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
-};
-
-int rs690_init(struct radeon_device *rdev)
-{
-	rdev->config.r300.reg_safe_bm = rs690_reg_safe_bm;
-	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs690_reg_safe_bm);
-	return 0;
-}
-- 
cgit v1.2.3


From a1a2d1d32250f6fcc317419e9dfb4a5a6946d2e6 Mon Sep 17 00:00:00 2001
From: Pekka Paalanen <pq@iki.fi>
Date: Sun, 23 Aug 2009 12:40:55 +0300
Subject: drm: GEM handles are u32, not int

Several functions in the GEM kernel API used int as handle type, but
user API has it __u32 which is also the intended type.

Replace int with u32.

Signed-off-by: Pekka Paalanen <pq@iki.fi>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_gem.c       | 11 +++++------
 drivers/gpu/drm/i915/i915_gem.c |  3 ++-
 include/drm/drmP.h              |  4 ++--
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index ffe8f4394d5..230c9ffdd5e 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -164,7 +164,7 @@ EXPORT_SYMBOL(drm_gem_object_alloc);
  * Removes the mapping from handle to filp for this object.
  */
 static int
-drm_gem_handle_delete(struct drm_file *filp, int handle)
+drm_gem_handle_delete(struct drm_file *filp, u32 handle)
 {
 	struct drm_device *dev;
 	struct drm_gem_object *obj;
@@ -207,7 +207,7 @@ drm_gem_handle_delete(struct drm_file *filp, int handle)
 int
 drm_gem_handle_create(struct drm_file *file_priv,
 		       struct drm_gem_object *obj,
-		       int *handlep)
+		       u32 *handlep)
 {
 	int	ret;
 
@@ -221,7 +221,7 @@ again:
 
 	/* do the allocation under our spinlock */
 	spin_lock(&file_priv->table_lock);
-	ret = idr_get_new_above(&file_priv->object_idr, obj, 1, handlep);
+	ret = idr_get_new_above(&file_priv->object_idr, obj, 1, (int *)handlep);
 	spin_unlock(&file_priv->table_lock);
 	if (ret == -EAGAIN)
 		goto again;
@@ -237,7 +237,7 @@ EXPORT_SYMBOL(drm_gem_handle_create);
 /** Returns a reference to the object named by the handle. */
 struct drm_gem_object *
 drm_gem_object_lookup(struct drm_device *dev, struct drm_file *filp,
-		      int handle)
+		      u32 handle)
 {
 	struct drm_gem_object *obj;
 
@@ -344,7 +344,7 @@ drm_gem_open_ioctl(struct drm_device *dev, void *data,
 	struct drm_gem_open *args = data;
 	struct drm_gem_object *obj;
 	int ret;
-	int handle;
+	u32 handle;
 
 	if (!(dev->driver->driver_features & DRIVER_GEM))
 		return -ENODEV;
@@ -539,7 +539,6 @@ int drm_gem_mmap(struct file *filp, struct vm_area_struct *vma)
 	vma->vm_flags |= VM_RESERVED | VM_IO | VM_PFNMAP | VM_DONTEXPAND;
 	vma->vm_ops = obj->dev->driver->gem_vm_ops;
 	vma->vm_private_data = map->handle;
-	/* FIXME: use pgprot_writecombine when available */
 	vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
 
 	/* Take a ref for this mapping of the object, so that the fault
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 140bee142fc..0e6c9cca897 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -111,7 +111,8 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
 {
 	struct drm_i915_gem_create *args = data;
 	struct drm_gem_object *obj;
-	int handle, ret;
+	int ret;
+	u32 handle;
 
 	args->size = roundup(args->size, PAGE_SIZE);
 
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index e0f1c1fee58..eeefb6369e1 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -1441,7 +1441,7 @@ drm_gem_object_unreference(struct drm_gem_object *obj)
 
 int drm_gem_handle_create(struct drm_file *file_priv,
 			  struct drm_gem_object *obj,
-			  int *handlep);
+			  u32 *handlep);
 
 static inline void
 drm_gem_object_handle_reference(struct drm_gem_object *obj)
@@ -1467,7 +1467,7 @@ drm_gem_object_handle_unreference(struct drm_gem_object *obj)
 
 struct drm_gem_object *drm_gem_object_lookup(struct drm_device *dev,
 					     struct drm_file *filp,
-					     int handle);
+					     u32 handle);
 int drm_gem_close_ioctl(struct drm_device *dev, void *data,
 			struct drm_file *file_priv);
 int drm_gem_flink_ioctl(struct drm_device *dev, void *data,
-- 
cgit v1.2.3


From 689d7c2a1127378854c7d7ea8d7c81238a824240 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 27 Aug 2009 11:51:23 +1000
Subject: drm/radeon: cleanup mkregtable.c

This cleans up the code in mkregtable.c to be more kernel style.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/mkregtable.c   | 320 +++++++++++++++++-----------------
 drivers/gpu/drm/radeon/reg_srcs/r300  |   2 +-
 drivers/gpu/drm/radeon/reg_srcs/rv515 |   2 +-
 3 files changed, 159 insertions(+), 165 deletions(-)

diff --git a/drivers/gpu/drm/radeon/mkregtable.c b/drivers/gpu/drm/radeon/mkregtable.c
index 0acd1cf8c36..fb211e585de 100644
--- a/drivers/gpu/drm/radeon/mkregtable.c
+++ b/drivers/gpu/drm/radeon/mkregtable.c
@@ -25,10 +25,8 @@
  *
  */
 #define container_of(ptr, type, member) ({          \
-    const typeof( ((type *)0)->member ) *__mptr = (ptr);    \
-        (type *)( (char *)__mptr - offsetof(type,member) );})
-
-
+	const typeof(((type *)0)->member)*__mptr = (ptr);    \
+		     (type *)((char *)__mptr - offsetof(type, member)); })
 
 /*
  * Simple doubly linked list implementation.
@@ -63,8 +61,7 @@ static inline void INIT_LIST_HEAD(struct list_head *list)
  */
 #ifndef CONFIG_DEBUG_LIST
 static inline void __list_add(struct list_head *new,
-			      struct list_head *prev,
-			      struct list_head *next)
+			      struct list_head *prev, struct list_head *next)
 {
 	next->prev = new;
 	new->next = next;
@@ -73,8 +70,7 @@ static inline void __list_add(struct list_head *new,
 }
 #else
 extern void __list_add(struct list_head *new,
-			      struct list_head *prev,
-			      struct list_head *next);
+		       struct list_head *prev, struct list_head *next);
 #endif
 
 /**
@@ -90,7 +86,6 @@ static inline void list_add(struct list_head *new, struct list_head *head)
 	__list_add(new, head, head->next);
 }
 
-
 /**
  * list_add_tail - add a new entry
  * @new: new entry to be added
@@ -111,7 +106,7 @@ static inline void list_add_tail(struct list_head *new, struct list_head *head)
  * This is only for internal list manipulation where we know
  * the prev/next entries already!
  */
-static inline void __list_del(struct list_head * prev, struct list_head * next)
+static inline void __list_del(struct list_head *prev, struct list_head *next)
 {
 	next->prev = prev;
 	prev->next = next;
@@ -127,8 +122,8 @@ static inline void __list_del(struct list_head * prev, struct list_head * next)
 static inline void list_del(struct list_head *entry)
 {
 	__list_del(entry->prev, entry->next);
-	entry->next = (void*)0xDEADBEEF;
-	entry->prev = (void*)0xBEEFDEAD;
+	entry->next = (void *)0xDEADBEEF;
+	entry->prev = (void *)0xBEEFDEAD;
 }
 #else
 extern void list_del(struct list_head *entry);
@@ -141,8 +136,7 @@ extern void list_del(struct list_head *entry);
  *
  * If @old was empty, it will be overwritten.
  */
-static inline void list_replace(struct list_head *old,
-				struct list_head *new)
+static inline void list_replace(struct list_head *old, struct list_head *new)
 {
 	new->next = old->next;
 	new->next->prev = new;
@@ -151,7 +145,7 @@ static inline void list_replace(struct list_head *old,
 }
 
 static inline void list_replace_init(struct list_head *old,
-					struct list_head *new)
+				     struct list_head *new)
 {
 	list_replace(old, new);
 	INIT_LIST_HEAD(old);
@@ -196,7 +190,7 @@ static inline void list_move_tail(struct list_head *list,
  * @head: the head of the list
  */
 static inline int list_is_last(const struct list_head *list,
-				const struct list_head *head)
+			       const struct list_head *head)
 {
 	return list->next == head;
 }
@@ -239,7 +233,8 @@ static inline int list_is_singular(const struct list_head *head)
 }
 
 static inline void __list_cut_position(struct list_head *list,
-		struct list_head *head, struct list_head *entry)
+				       struct list_head *head,
+				       struct list_head *entry)
 {
 	struct list_head *new_first = entry->next;
 	list->next = head->next;
@@ -265,12 +260,12 @@ static inline void __list_cut_position(struct list_head *list,
  *
  */
 static inline void list_cut_position(struct list_head *list,
-		struct list_head *head, struct list_head *entry)
+				     struct list_head *head,
+				     struct list_head *entry)
 {
 	if (list_empty(head))
 		return;
-	if (list_is_singular(head) &&
-		(head->next != entry && head != entry))
+	if (list_is_singular(head) && (head->next != entry && head != entry))
 		return;
 	if (entry == head)
 		INIT_LIST_HEAD(list);
@@ -279,8 +274,7 @@ static inline void list_cut_position(struct list_head *list,
 }
 
 static inline void __list_splice(const struct list_head *list,
-				 struct list_head *prev,
-				 struct list_head *next)
+				 struct list_head *prev, struct list_head *next)
 {
 	struct list_head *first = list->next;
 	struct list_head *last = list->prev;
@@ -298,7 +292,7 @@ static inline void __list_splice(const struct list_head *list,
  * @head: the place to add it in the first list.
  */
 static inline void list_splice(const struct list_head *list,
-				struct list_head *head)
+			       struct list_head *head)
 {
 	if (!list_empty(list))
 		__list_splice(list, head, head->next);
@@ -310,7 +304,7 @@ static inline void list_splice(const struct list_head *list,
  * @head: the place to add it in the first list.
  */
 static inline void list_splice_tail(struct list_head *list,
-				struct list_head *head)
+				    struct list_head *head)
 {
 	if (!list_empty(list))
 		__list_splice(list, head->prev, head);
@@ -376,7 +370,7 @@ static inline void list_splice_tail_init(struct list_head *list,
  */
 #define list_for_each(pos, head) \
 	for (pos = (head)->next; prefetch(pos->next), pos != (head); \
-        	pos = pos->next)
+		pos = pos->next)
 
 /**
  * __list_for_each	-	iterate over a list
@@ -398,7 +392,7 @@ static inline void list_splice_tail_init(struct list_head *list,
  */
 #define list_for_each_prev(pos, head) \
 	for (pos = (head)->prev; prefetch(pos->prev), pos != (head); \
-        	pos = pos->prev)
+		pos = pos->prev)
 
 /**
  * list_for_each_safe - iterate over a list safe against removal of list entry
@@ -555,172 +549,172 @@ static inline void list_splice_tail_init(struct list_head *list,
 	     pos = n, n = list_entry(n->member.prev, typeof(*n), member))
 
 struct offset {
-    struct list_head    list;
-    unsigned            offset;
+	struct list_head list;
+	unsigned offset;
 };
 
 struct table {
-    struct list_head    offsets;
-    unsigned            offset_max;
-    unsigned            nentry;
-    unsigned            *table;
-    char 	*gpu_prefix;
+	struct list_head offsets;
+	unsigned offset_max;
+	unsigned nentry;
+	unsigned *table;
+	char *gpu_prefix;
 };
 
-struct offset* offset_new(unsigned o)
+struct offset *offset_new(unsigned o)
 {
-    struct offset *offset;
-
-    offset = (struct offset*)malloc(sizeof(struct offset));
-    if (offset) {
-        INIT_LIST_HEAD(&offset->list);
-        offset->offset = o;
-    }
-    return offset;
+	struct offset *offset;
+
+	offset = (struct offset *)malloc(sizeof(struct offset));
+	if (offset) {
+		INIT_LIST_HEAD(&offset->list);
+		offset->offset = o;
+	}
+	return offset;
 }
 
 void table_offset_add(struct table *t, struct offset *offset)
 {
-    list_add_tail(&offset->list, &t->offsets);
+	list_add_tail(&offset->list, &t->offsets);
 }
 
 void table_init(struct table *t)
 {
-    INIT_LIST_HEAD(&t->offsets);
-    t->offset_max = 0;
-    t->nentry = 0;
-    t->table = NULL;
+	INIT_LIST_HEAD(&t->offsets);
+	t->offset_max = 0;
+	t->nentry = 0;
+	t->table = NULL;
 }
 
 void table_print(struct table *t)
 {
-    unsigned nlloop, i, j, n, c, id;
-
-    nlloop = (t->nentry + 3) / 4;
-    c = t->nentry;
-    printf("static const unsigned %s_reg_safe_bm[%d] = {\n", t->gpu_prefix, t->nentry);
-    for(i = 0, id = 0; i < nlloop; i++) {
-        n = 4;
-        if (n > c) {
-            n = c;
-        }
-        c -= n;
-        for(j = 0; j < n; j++) {
-	    if (j == 0) printf("\t");
-	    else printf(" ");
-            printf("0x%08X,", t->table[id++]);
-        }
-        printf("\n");
-    }
-    printf("};\n");
+	unsigned nlloop, i, j, n, c, id;
+
+	nlloop = (t->nentry + 3) / 4;
+	c = t->nentry;
+	printf("static const unsigned %s_reg_safe_bm[%d] = {\n", t->gpu_prefix,
+	       t->nentry);
+	for (i = 0, id = 0; i < nlloop; i++) {
+		n = 4;
+		if (n > c)
+			n = c;
+		c -= n;
+		for (j = 0; j < n; j++) {
+			if (j == 0)
+				printf("\t");
+			else
+				printf(" ");
+			printf("0x%08X,", t->table[id++]);
+		}
+		printf("\n");
+	}
+	printf("};\n");
 }
 
 int table_build(struct table *t)
 {
-    struct offset *offset;
-    unsigned i, m;
-
-    t->nentry = ((t->offset_max >> 2) + 31) / 32;
-    t->table = (unsigned*)malloc(sizeof(unsigned) * t->nentry);
-    if (t->table == NULL) {
-        return -1;
-    }
-    memset(t->table, 0xff, sizeof(unsigned) * t->nentry);
-    list_for_each_entry(offset, &t->offsets, list) {
-        i = (offset->offset >> 2) / 32;
-        m = (offset->offset >> 2) & 31;
-        m = 1 << m;
-        t->table[i] ^= m;
-    }
-    return 0;
+	struct offset *offset;
+	unsigned i, m;
+
+	t->nentry = ((t->offset_max >> 2) + 31) / 32;
+	t->table = (unsigned *)malloc(sizeof(unsigned) * t->nentry);
+	if (t->table == NULL)
+		return -1;
+	memset(t->table, 0xff, sizeof(unsigned) * t->nentry);
+	list_for_each_entry(offset, &t->offsets, list) {
+		i = (offset->offset >> 2) / 32;
+		m = (offset->offset >> 2) & 31;
+		m = 1 << m;
+		t->table[i] ^= m;
+	}
+	return 0;
 }
 
 static char gpu_name[10];
 int parser_auth(struct table *t, const char *filename)
 {
-    FILE *file;
-    regex_t mask_rex;
-    regmatch_t match[4];
-    char buf[1024];
-    size_t end;
-    int len;
-    int done = 0;
-    int r;
-    unsigned o;
-    struct offset *offset;
-    char last_reg_s[10];
-    int last_reg;
-    
-    if (regcomp(&mask_rex, "(0x[0-9a-fA-F]*) *([_a-zA-Z0-9]*)", REG_EXTENDED)) {
-        fprintf(stderr, "Failed to compile regular expression\n");
-        return -1;
-    }
-    file = fopen(filename, "r");
-    if (file == NULL) {
-        fprintf(stderr, "Failed to open: %s\n", filename);
-        return -1;
-    }
-    fseek(file, 0, SEEK_END);
-    end = ftell(file);
-    fseek(file, 0, SEEK_SET);
-
-    /* get header */
-    if (fgets(buf, 1024, file) == NULL)
-        return -1;
-
-    /* first line will contain the last register 
-     * and gpu name */
-    sscanf(buf, "%s %s", gpu_name, last_reg_s);
-    t->gpu_prefix = gpu_name;
-    last_reg = strtol(last_reg_s, NULL, 16);
-
-    do {
-        if (fgets(buf, 1024, file) == NULL)
-            return -1;
-        len = strlen(buf);
-        if (ftell(file) == end) {
-            done = 1;
-        }
-        if (len) {
-            r = regexec(&mask_rex, buf, 4, match, 0);
-            if (r == REG_NOMATCH) {
-            } else if (r) {
-                fprintf(stderr, "Error matching regular expression %d in %s\n",
-                        r, filename);
-                return -1;
-            } else {
-                buf[match[0].rm_eo] = 0;
-                buf[match[1].rm_eo] = 0;
-                buf[match[2].rm_eo] = 0;
-                o = strtol(&buf[match[1].rm_so], NULL, 16);
-                offset = offset_new(o);
-                table_offset_add(t, offset);
-                if (o > t->offset_max) {
-                    t->offset_max = o;
-                }
-            }
-        }
-    } while (!done);
-    fclose(file);
-    if (t->offset_max < last_reg)
-	t->offset_max = last_reg;
-    return table_build(t);
+	FILE *file;
+	regex_t mask_rex;
+	regmatch_t match[4];
+	char buf[1024];
+	size_t end;
+	int len;
+	int done = 0;
+	int r;
+	unsigned o;
+	struct offset *offset;
+	char last_reg_s[10];
+	int last_reg;
+
+	if (regcomp
+	    (&mask_rex, "(0x[0-9a-fA-F]*) *([_a-zA-Z0-9]*)", REG_EXTENDED)) {
+		fprintf(stderr, "Failed to compile regular expression\n");
+		return -1;
+	}
+	file = fopen(filename, "r");
+	if (file == NULL) {
+		fprintf(stderr, "Failed to open: %s\n", filename);
+		return -1;
+	}
+	fseek(file, 0, SEEK_END);
+	end = ftell(file);
+	fseek(file, 0, SEEK_SET);
+
+	/* get header */
+	if (fgets(buf, 1024, file) == NULL)
+		return -1;
+
+	/* first line will contain the last register
+	 * and gpu name */
+	sscanf(buf, "%s %s", gpu_name, last_reg_s);
+	t->gpu_prefix = gpu_name;
+	last_reg = strtol(last_reg_s, NULL, 16);
+
+	do {
+		if (fgets(buf, 1024, file) == NULL)
+			return -1;
+		len = strlen(buf);
+		if (ftell(file) == end)
+			done = 1;
+		if (len) {
+			r = regexec(&mask_rex, buf, 4, match, 0);
+			if (r == REG_NOMATCH) {
+			} else if (r) {
+				fprintf(stderr,
+					"Error matching regular expression %d in %s\n",
+					r, filename);
+				return -1;
+			} else {
+				buf[match[0].rm_eo] = 0;
+				buf[match[1].rm_eo] = 0;
+				buf[match[2].rm_eo] = 0;
+				o = strtol(&buf[match[1].rm_so], NULL, 16);
+				offset = offset_new(o);
+				table_offset_add(t, offset);
+				if (o > t->offset_max)
+					t->offset_max = o;
+			}
+		}
+	} while (!done);
+	fclose(file);
+	if (t->offset_max < last_reg)
+		t->offset_max = last_reg;
+	return table_build(t);
 }
 
 int main(int argc, char *argv[])
 {
-    struct table t;
-
-    if (argc != 2) {
-        fprintf(stderr, "Usage: %s <authfile>\n",
-                argv[0]);
-        exit(1);
-    }
-    table_init(&t);
-    if (parser_auth(&t, argv[1])) {
-        fprintf(stderr, "Failed to parse file %s\n", argv[1]);
-        return -1;
-    }
-    table_print(&t);
-    return 0;
+	struct table t;
+
+	if (argc != 2) {
+		fprintf(stderr, "Usage: %s <authfile>\n", argv[0]);
+		exit(1);
+	}
+	table_init(&t);
+	if (parser_auth(&t, argv[1])) {
+		fprintf(stderr, "Failed to parse file %s\n", argv[1]);
+		return -1;
+	}
+	table_print(&t);
+	return 0;
 }
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r300 b/drivers/gpu/drm/radeon/reg_srcs/r300
index b4bd5b64fcb..16f8f38264f 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/r300
+++ b/drivers/gpu/drm/radeon/reg_srcs/r300
@@ -153,7 +153,7 @@ r300 0x4f60
 0x42A4 SU_POLY_OFFSET_FRONT_SCALE
 0x42A8 SU_POLY_OFFSET_FRONT_OFFSET
 0x42AC SU_POLY_OFFSET_BACK_SCALE
-0x42B0 SU_POLY_OFFSET_BACK_OFFSET 
+0x42B0 SU_POLY_OFFSET_BACK_OFFSET
 0x42B4 SU_POLY_OFFSET_ENABLE
 0x42B8 SU_CULL_MODE
 0x42C0 SU_DEPTH_SCALE
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rv515 b/drivers/gpu/drm/radeon/reg_srcs/rv515
index d1fcf382fd7..7432df7f1c1 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/rv515
+++ b/drivers/gpu/drm/radeon/reg_srcs/rv515
@@ -186,7 +186,7 @@ rv515 0x6d40
 0x42A4 SU_POLY_OFFSET_FRONT_SCALE
 0x42A8 SU_POLY_OFFSET_FRONT_OFFSET
 0x42AC SU_POLY_OFFSET_BACK_SCALE
-0x42B0 SU_POLY_OFFSET_BACK_OFFSET 
+0x42B0 SU_POLY_OFFSET_BACK_OFFSET
 0x42B4 SU_POLY_OFFSET_ENABLE
 0x42B8 SU_CULL_MODE
 0x42C0 SU_DEPTH_SCALE
-- 
cgit v1.2.3


From e67aae79f93d9584aaa24d2a2c76383e9d588f98 Mon Sep 17 00:00:00 2001
From: Maarten Maathuis <madman2003@gmail.com>
Date: Thu, 27 Aug 2009 10:18:29 +0200
Subject: drm/crtc_helper: replace modeset fail path with something simpler

- The previous system was not very transparent, nor flexible.
- This is needed to be able to fix a few bugs in the mechanism.

Signed-off-by: Maarten Maathuis <madman2003@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_crtc_helper.c | 86 ++++++++++++++++++++++++---------------
 1 file changed, 54 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index a06c5f52c28..a3837b39bb8 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -704,13 +704,12 @@ EXPORT_SYMBOL(drm_crtc_helper_set_mode);
 int drm_crtc_helper_set_config(struct drm_mode_set *set)
 {
 	struct drm_device *dev;
-	struct drm_crtc **save_crtcs, *new_crtc;
-	struct drm_encoder **save_encoders, *new_encoder;
+	struct drm_crtc *save_crtcs, *new_crtc, *crtc;
+	struct drm_encoder *save_encoders, *new_encoder, *encoder;
 	struct drm_framebuffer *old_fb = NULL;
-	bool save_enabled;
 	bool mode_changed = false; /* if true do a full mode set */
 	bool fb_changed = false; /* if true and !mode_changed just do a flip */
-	struct drm_connector *connector;
+	struct drm_connector *save_connectors, *connector;
 	int count = 0, ro, fail = 0;
 	struct drm_crtc_helper_funcs *crtc_funcs;
 	int ret = 0;
@@ -735,25 +734,47 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
 
 	dev = set->crtc->dev;
 
-	/* save previous config */
-	save_enabled = set->crtc->enabled;
-
-	/*
-	 * We do mode_config.num_connectors here since we'll look at the
-	 * CRTC and encoder associated with each connector later.
-	 */
-	save_crtcs = kzalloc(dev->mode_config.num_connector *
-			     sizeof(struct drm_crtc *), GFP_KERNEL);
+	/* Allocate space for the backup of all (non-pointer) crtc, encoder and
+	 * connector data. */
+	save_crtcs = kzalloc(dev->mode_config.num_crtc *
+			     sizeof(struct drm_crtc), GFP_KERNEL);
 	if (!save_crtcs)
 		return -ENOMEM;
 
-	save_encoders = kzalloc(dev->mode_config.num_connector *
-				sizeof(struct drm_encoders *), GFP_KERNEL);
+	save_encoders = kzalloc(dev->mode_config.num_encoder *
+				sizeof(struct drm_encoder), GFP_KERNEL);
 	if (!save_encoders) {
 		kfree(save_crtcs);
 		return -ENOMEM;
 	}
 
+	save_connectors = kzalloc(dev->mode_config.num_connector *
+				sizeof(struct drm_connector), GFP_KERNEL);
+	if (!save_connectors) {
+		kfree(save_crtcs);
+		kfree(save_encoders);
+		return -ENOMEM;
+	}
+
+	/* Copy data. Note that driver private data is not affected.
+	 * Should anything bad happen only the expected state is
+	 * restored, not the drivers personal bookkeeping.
+	 */
+	count = 0;
+	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+		save_crtcs[count++] = *crtc;
+	}
+
+	count = 0;
+	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+		save_encoders[count++] = *encoder;
+	}
+
+	count = 0;
+	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+		save_connectors[count++] = *connector;
+	}
+
 	/* We should be able to check here if the fb has the same properties
 	 * and then just flip_or_move it */
 	if (set->crtc->fb != set->fb) {
@@ -786,7 +807,6 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 		struct drm_connector_helper_funcs *connector_funcs =
 			connector->helper_private;
-		save_encoders[count++] = connector->encoder;
 		new_encoder = connector->encoder;
 		for (ro = 0; ro < set->num_connectors; ro++) {
 			if (set->connectors[ro] == connector) {
@@ -809,7 +829,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
 
 	if (fail) {
 		ret = -EINVAL;
-		goto fail_no_encoder;
+		goto fail;
 	}
 
 	count = 0;
@@ -817,8 +837,6 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
 		if (!connector->encoder)
 			continue;
 
-		save_crtcs[count++] = connector->encoder->crtc;
-
 		if (connector->encoder->crtc == set->crtc)
 			new_crtc = NULL;
 		else
@@ -833,7 +851,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
 		if (new_crtc &&
 		    !drm_encoder_crtc_ok(connector->encoder, new_crtc)) {
 			ret = -EINVAL;
-			goto fail_set_mode;
+			goto fail;
 		}
 		if (new_crtc != connector->encoder->crtc) {
 			DRM_DEBUG_KMS("crtc changed, full mode switch\n");
@@ -862,7 +880,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
 				DRM_ERROR("failed to set mode on crtc %p\n",
 					  set->crtc);
 				ret = -EINVAL;
-				goto fail_set_mode;
+				goto fail;
 			}
 			/* TODO are these needed? */
 			set->crtc->desired_x = set->x;
@@ -877,30 +895,34 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
 		ret = crtc_funcs->mode_set_base(set->crtc,
 						set->x, set->y, old_fb);
 		if (ret != 0)
-		    goto fail_set_mode;
+			goto fail;
 	}
 
+	kfree(save_connectors);
 	kfree(save_encoders);
 	kfree(save_crtcs);
 	return 0;
 
-fail_set_mode:
-	set->crtc->enabled = save_enabled;
-	set->crtc->fb = old_fb;
+fail:
+	/* Restore all previous data. */
 	count = 0;
-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-		if (!connector->encoder)
-			continue;
+	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+		*crtc = save_crtcs[count++];
+	}
 
-		connector->encoder->crtc = save_crtcs[count++];
+	count = 0;
+	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+		*encoder = save_encoders[count++];
 	}
-fail_no_encoder:
-	kfree(save_crtcs);
+
 	count = 0;
 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-		connector->encoder = save_encoders[count++];
+		*connector = save_connectors[count++];
 	}
+
+	kfree(save_connectors);
 	kfree(save_encoders);
+	kfree(save_crtcs);
 	return ret;
 }
 EXPORT_SYMBOL(drm_crtc_helper_set_config);
-- 
cgit v1.2.3


From f380ef86916904e4b79f7bec599deb51057b2d0c Mon Sep 17 00:00:00 2001
From: Maarten Maathuis <madman2003@gmail.com>
Date: Wed, 19 Aug 2009 00:56:44 +0200
Subject: drm/crtc_helper: place drm_helper_encoder_in_use() in the header file

- The symbol was already exported.

Signed-off-by: Maarten Maathuis <madman2003@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 include/drm/drm_crtc_helper.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/drm_crtc_helper.h b/include/drm/drm_crtc_helper.h
index 6769ff6c1bc..e44a4f87303 100644
--- a/include/drm/drm_crtc_helper.h
+++ b/include/drm/drm_crtc_helper.h
@@ -98,6 +98,7 @@ extern bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
 				     int x, int y,
 				     struct drm_framebuffer *old_fb);
 extern bool drm_helper_crtc_in_use(struct drm_crtc *crtc);
+extern bool drm_helper_encoder_in_use(struct drm_encoder *encoder);
 
 extern void drm_helper_connector_dpms(struct drm_connector *connector, int mode);
 
-- 
cgit v1.2.3


From ff846ab7f76ffecba4f0bef026163d2a2364d7d0 Mon Sep 17 00:00:00 2001
From: Maarten Maathuis <madman2003@gmail.com>
Date: Wed, 19 Aug 2009 00:56:45 +0200
Subject: drm/crtc_helper: NULL encoder->crtc when switching encoders

- Previously the old encoder would be called during modeset and without a connector bad things happened.

Signed-off-by: Maarten Maathuis <madman2003@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_crtc_helper.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index a3837b39bb8..205349ea107 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -823,6 +823,10 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
 		if (new_encoder != connector->encoder) {
 			DRM_DEBUG_KMS("encoder changed, full mode switch\n");
 			mode_changed = true;
+			/* If the encoder is reused for another connector, then
+			 * the appropriate crtc will be set later.
+			 */
+			connector->encoder->crtc = NULL;
 			connector->encoder = new_encoder;
 		}
 	}
-- 
cgit v1.2.3


From 1ae70072f0699916c1a77a9bacad958ee46f7395 Mon Sep 17 00:00:00 2001
From: Roel Kluin <roel.kluin@gmail.com>
Date: Sat, 29 Aug 2009 22:20:34 +0200
Subject: drm: dereference of tmp in drm_proc_create_files()

tmp allocation may fail, prevent a dereference.

Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_proc.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/drm_proc.c b/drivers/gpu/drm/drm_proc.c
index bbd4b3d1074..dc967af7a33 100644
--- a/drivers/gpu/drm/drm_proc.c
+++ b/drivers/gpu/drm/drm_proc.c
@@ -106,6 +106,10 @@ int drm_proc_create_files(struct drm_info_list *files, int count,
 			continue;
 
 		tmp = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
+		if (tmp == NULL) {
+			ret = -1;
+			goto fail;
+		}
 		ent = create_proc_entry(files[i].name, S_IFREG | S_IRUGO, root);
 		if (!ent) {
 			DRM_ERROR("Cannot create /proc/dri/%s/%s\n",
-- 
cgit v1.2.3


From 70967ab9c0c9017645d167d33675eab996633631 Mon Sep 17 00:00:00 2001
From: Ben Hutchings <ben@decadent.org.uk>
Date: Sat, 29 Aug 2009 14:53:51 +0100
Subject: radeon: Use request_firmware()

Loosely based on a patch by
Jaswinder Singh Rajput <jaswinderlinux@gmail.com>.

KMS support by Dave Airlie <airlied@redhat.com>.

For Radeon 100- to 500-series, firmware blobs look like:
    struct {
        __be32 datah;
        __be32 datal;
    } cp_ucode[256];

For Radeon 600-series, there are two separate firmware blobs:
    __be32 me_ucode[PM4_UCODE_SIZE * 3];
    __be32 pfp_ucode[PFP_UCODE_SIZE];

For Radeon 700-series, likewise:
    __be32 me_ucode[R700_PM4_UCODE_SIZE];
    __be32 pfp_ucode[R700_PFP_UCODE_SIZE];

Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/Kconfig                   |     1 +
 drivers/gpu/drm/radeon/r100.c             |   119 +-
 drivers/gpu/drm/radeon/r600_cp.c          |   289 +-
 drivers/gpu/drm/radeon/r600_microcode.h   | 23297 ----------------------------
 drivers/gpu/drm/radeon/radeon.h           |     1 +
 drivers/gpu/drm/radeon/radeon_cp.c        |   128 +-
 drivers/gpu/drm/radeon/radeon_drv.h       |     5 +
 drivers/gpu/drm/radeon/radeon_irq_kms.c   |     1 -
 drivers/gpu/drm/radeon/radeon_microcode.h |  1844 ---
 firmware/Makefile                         |    14 +
 firmware/WHENCE                           |    58 +
 firmware/radeon/R100_cp.bin.ihex          |   130 +
 firmware/radeon/R200_cp.bin.ihex          |   130 +
 firmware/radeon/R300_cp.bin.ihex          |   130 +
 firmware/radeon/R420_cp.bin.ihex          |   130 +
 firmware/radeon/R520_cp.bin.ihex          |   130 +
 firmware/radeon/R600_me.bin.ihex          |  1345 ++
 firmware/radeon/R600_pfp.bin.ihex         |   145 +
 firmware/radeon/RS600_cp.bin.ihex         |   130 +
 firmware/radeon/RS690_cp.bin.ihex         |   130 +
 firmware/radeon/RS780_me.bin.ihex         |  1345 ++
 firmware/radeon/RS780_pfp.bin.ihex        |   145 +
 firmware/radeon/RV610_me.bin.ihex         |  1345 ++
 firmware/radeon/RV610_pfp.bin.ihex        |   145 +
 firmware/radeon/RV620_me.bin.ihex         |  1345 ++
 firmware/radeon/RV620_pfp.bin.ihex        |   145 +
 firmware/radeon/RV630_me.bin.ihex         |  1345 ++
 firmware/radeon/RV630_pfp.bin.ihex        |   145 +
 firmware/radeon/RV635_me.bin.ihex         |  1345 ++
 firmware/radeon/RV635_pfp.bin.ihex        |   145 +
 firmware/radeon/RV670_me.bin.ihex         |  1345 ++
 firmware/radeon/RV670_pfp.bin.ihex        |   145 +
 firmware/radeon/RV710_me.bin.ihex         |   341 +
 firmware/radeon/RV710_pfp.bin.ihex        |   213 +
 firmware/radeon/RV730_me.bin.ihex         |   341 +
 firmware/radeon/RV730_pfp.bin.ihex        |   213 +
 firmware/radeon/RV770_me.bin.ihex         |   341 +
 firmware/radeon/RV770_pfp.bin.ihex        |   213 +
 38 files changed, 13388 insertions(+), 25371 deletions(-)
 delete mode 100644 drivers/gpu/drm/radeon/r600_microcode.h
 delete mode 100644 drivers/gpu/drm/radeon/radeon_microcode.h
 create mode 100644 firmware/radeon/R100_cp.bin.ihex
 create mode 100644 firmware/radeon/R200_cp.bin.ihex
 create mode 100644 firmware/radeon/R300_cp.bin.ihex
 create mode 100644 firmware/radeon/R420_cp.bin.ihex
 create mode 100644 firmware/radeon/R520_cp.bin.ihex
 create mode 100644 firmware/radeon/R600_me.bin.ihex
 create mode 100644 firmware/radeon/R600_pfp.bin.ihex
 create mode 100644 firmware/radeon/RS600_cp.bin.ihex
 create mode 100644 firmware/radeon/RS690_cp.bin.ihex
 create mode 100644 firmware/radeon/RS780_me.bin.ihex
 create mode 100644 firmware/radeon/RS780_pfp.bin.ihex
 create mode 100644 firmware/radeon/RV610_me.bin.ihex
 create mode 100644 firmware/radeon/RV610_pfp.bin.ihex
 create mode 100644 firmware/radeon/RV620_me.bin.ihex
 create mode 100644 firmware/radeon/RV620_pfp.bin.ihex
 create mode 100644 firmware/radeon/RV630_me.bin.ihex
 create mode 100644 firmware/radeon/RV630_pfp.bin.ihex
 create mode 100644 firmware/radeon/RV635_me.bin.ihex
 create mode 100644 firmware/radeon/RV635_pfp.bin.ihex
 create mode 100644 firmware/radeon/RV670_me.bin.ihex
 create mode 100644 firmware/radeon/RV670_pfp.bin.ihex
 create mode 100644 firmware/radeon/RV710_me.bin.ihex
 create mode 100644 firmware/radeon/RV710_pfp.bin.ihex
 create mode 100644 firmware/radeon/RV730_me.bin.ihex
 create mode 100644 firmware/radeon/RV730_pfp.bin.ihex
 create mode 100644 firmware/radeon/RV770_me.bin.ihex
 create mode 100644 firmware/radeon/RV770_pfp.bin.ihex

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index a07abb818f5..ebafad18e31 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -50,6 +50,7 @@ config DRM_RADEON
 	select FB_CFB_IMAGEBLIT
 	select FB
 	select FRAMEBUFFER_CONSOLE if !EMBEDDED
+	select FW_LOADER
 	help
 	  Choose this option if you have an ATI Radeon graphics card.  There
 	  are both PCI and AGP versions.  You don't need to choose this to
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 90ff8e0ac04..639d5b216ee 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -29,9 +29,27 @@
 #include "drmP.h"
 #include "drm.h"
 #include "radeon_drm.h"
-#include "radeon_microcode.h"
 #include "radeon_reg.h"
 #include "radeon.h"
+#include <linux/firmware.h>
+#include <linux/platform_device.h>
+
+/* Firmware Names */
+#define FIRMWARE_R100		"radeon/R100_cp.bin"
+#define FIRMWARE_R200		"radeon/R200_cp.bin"
+#define FIRMWARE_R300		"radeon/R300_cp.bin"
+#define FIRMWARE_R420		"radeon/R420_cp.bin"
+#define FIRMWARE_RS690		"radeon/RS690_cp.bin"
+#define FIRMWARE_RS600		"radeon/RS600_cp.bin"
+#define FIRMWARE_R520		"radeon/R520_cp.bin"
+
+MODULE_FIRMWARE(FIRMWARE_R100);
+MODULE_FIRMWARE(FIRMWARE_R200);
+MODULE_FIRMWARE(FIRMWARE_R300);
+MODULE_FIRMWARE(FIRMWARE_R420);
+MODULE_FIRMWARE(FIRMWARE_RS690);
+MODULE_FIRMWARE(FIRMWARE_RS600);
+MODULE_FIRMWARE(FIRMWARE_R520);
 
 /* This files gather functions specifics to:
  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
@@ -478,33 +496,33 @@ void r100_ring_start(struct radeon_device *rdev)
 	radeon_ring_unlock_commit(rdev);
 }
 
-static void r100_cp_load_microcode(struct radeon_device *rdev)
+
+/* Load the microcode for the CP */
+static int r100_cp_init_microcode(struct radeon_device *rdev)
 {
-	int i;
+	struct platform_device *pdev;
+	const char *fw_name = NULL;
+	int err;
 
-	if (r100_gui_wait_for_idle(rdev)) {
-		printk(KERN_WARNING "Failed to wait GUI idle while "
-		       "programming pipes. Bad things might happen.\n");
-	}
+	DRM_DEBUG("\n");
 
-	WREG32(RADEON_CP_ME_RAM_ADDR, 0);
+	pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
+	err = IS_ERR(pdev);
+	if (err) {
+		printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
+		return -EINVAL;
+	}
 	if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 	    (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 	    (rdev->family == CHIP_RS200)) {
 		DRM_INFO("Loading R100 Microcode\n");
-		for (i = 0; i < 256; i++) {
-			WREG32(RADEON_CP_ME_RAM_DATAH, R100_cp_microcode[i][1]);
-			WREG32(RADEON_CP_ME_RAM_DATAL, R100_cp_microcode[i][0]);
-		}
+		fw_name = FIRMWARE_R100;
 	} else if ((rdev->family == CHIP_R200) ||
 		   (rdev->family == CHIP_RV250) ||
 		   (rdev->family == CHIP_RV280) ||
 		   (rdev->family == CHIP_RS300)) {
 		DRM_INFO("Loading R200 Microcode\n");
-		for (i = 0; i < 256; i++) {
-			WREG32(RADEON_CP_ME_RAM_DATAH, R200_cp_microcode[i][1]);
-			WREG32(RADEON_CP_ME_RAM_DATAL, R200_cp_microcode[i][0]);
-		}
+		fw_name = FIRMWARE_R200;
 	} else if ((rdev->family == CHIP_R300) ||
 		   (rdev->family == CHIP_R350) ||
 		   (rdev->family == CHIP_RV350) ||
@@ -512,31 +530,19 @@ static void r100_cp_load_microcode(struct radeon_device *rdev)
 		   (rdev->family == CHIP_RS400) ||
 		   (rdev->family == CHIP_RS480)) {
 		DRM_INFO("Loading R300 Microcode\n");
-		for (i = 0; i < 256; i++) {
-			WREG32(RADEON_CP_ME_RAM_DATAH, R300_cp_microcode[i][1]);
-			WREG32(RADEON_CP_ME_RAM_DATAL, R300_cp_microcode[i][0]);
-		}
+		fw_name = FIRMWARE_R300;
 	} else if ((rdev->family == CHIP_R420) ||
 		   (rdev->family == CHIP_R423) ||
 		   (rdev->family == CHIP_RV410)) {
 		DRM_INFO("Loading R400 Microcode\n");
-		for (i = 0; i < 256; i++) {
-			WREG32(RADEON_CP_ME_RAM_DATAH, R420_cp_microcode[i][1]);
-			WREG32(RADEON_CP_ME_RAM_DATAL, R420_cp_microcode[i][0]);
-		}
+		fw_name = FIRMWARE_R420;
 	} else if ((rdev->family == CHIP_RS690) ||
 		   (rdev->family == CHIP_RS740)) {
 		DRM_INFO("Loading RS690/RS740 Microcode\n");
-		for (i = 0; i < 256; i++) {
-			WREG32(RADEON_CP_ME_RAM_DATAH, RS690_cp_microcode[i][1]);
-			WREG32(RADEON_CP_ME_RAM_DATAL, RS690_cp_microcode[i][0]);
-		}
+		fw_name = FIRMWARE_RS690;
 	} else if (rdev->family == CHIP_RS600) {
 		DRM_INFO("Loading RS600 Microcode\n");
-		for (i = 0; i < 256; i++) {
-			WREG32(RADEON_CP_ME_RAM_DATAH, RS600_cp_microcode[i][1]);
-			WREG32(RADEON_CP_ME_RAM_DATAL, RS600_cp_microcode[i][0]);
-		}
+		fw_name = FIRMWARE_RS600;
 	} else if ((rdev->family == CHIP_RV515) ||
 		   (rdev->family == CHIP_R520) ||
 		   (rdev->family == CHIP_RV530) ||
@@ -544,9 +550,43 @@ static void r100_cp_load_microcode(struct radeon_device *rdev)
 		   (rdev->family == CHIP_RV560) ||
 		   (rdev->family == CHIP_RV570)) {
 		DRM_INFO("Loading R500 Microcode\n");
-		for (i = 0; i < 256; i++) {
-			WREG32(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]);
-			WREG32(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]);
+		fw_name = FIRMWARE_R520;
+	}
+
+	err = request_firmware(&rdev->fw, fw_name, &pdev->dev);
+	platform_device_unregister(pdev);
+	if (err) {
+		printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
+		       fw_name);
+	} else if (rdev->fw->size % 8) {
+		printk(KERN_ERR
+		       "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
+		       rdev->fw->size, fw_name);
+		err = -EINVAL;
+		release_firmware(rdev->fw);
+		rdev->fw = NULL;
+	}
+	return err;
+}
+static void r100_cp_load_microcode(struct radeon_device *rdev)
+{
+	const __be32 *fw_data;
+	int i, size;
+
+	if (r100_gui_wait_for_idle(rdev)) {
+		printk(KERN_WARNING "Failed to wait GUI idle while "
+		       "programming pipes. Bad things might happen.\n");
+	}
+
+	if (rdev->fw) {
+		size = rdev->fw->size / 4;
+		fw_data = (const __be32 *)&rdev->fw->data[0];
+		WREG32(RADEON_CP_ME_RAM_ADDR, 0);
+		for (i = 0; i < size; i += 2) {
+			WREG32(RADEON_CP_ME_RAM_DATAH,
+			       be32_to_cpup(&fw_data[i]));
+			WREG32(RADEON_CP_ME_RAM_DATAL,
+			       be32_to_cpup(&fw_data[i + 1]));
 		}
 	}
 }
@@ -585,6 +625,15 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
 	} else {
 		DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
 	}
+
+	if (!rdev->fw) {
+		r = r100_cp_init_microcode(rdev);
+		if (r) {
+			DRM_ERROR("Failed to load firmware!\n");
+			return r;
+		}
+	}
+
 	/* Align ring size */
 	rb_bufsz = drm_order(ring_size / 8);
 	ring_size = (1 << (rb_bufsz + 1)) * 4;
diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c
index 20f17908b03..8327912de96 100644
--- a/drivers/gpu/drm/radeon/r600_cp.c
+++ b/drivers/gpu/drm/radeon/r600_cp.c
@@ -31,7 +31,32 @@
 #include "radeon_drm.h"
 #include "radeon_drv.h"
 
-#include "r600_microcode.h"
+#define PFP_UCODE_SIZE 576
+#define PM4_UCODE_SIZE 1792
+#define R700_PFP_UCODE_SIZE 848
+#define R700_PM4_UCODE_SIZE 1360
+
+/* Firmware Names */
+MODULE_FIRMWARE("radeon/R600_pfp.bin");
+MODULE_FIRMWARE("radeon/R600_me.bin");
+MODULE_FIRMWARE("radeon/RV610_pfp.bin");
+MODULE_FIRMWARE("radeon/RV610_me.bin");
+MODULE_FIRMWARE("radeon/RV630_pfp.bin");
+MODULE_FIRMWARE("radeon/RV630_me.bin");
+MODULE_FIRMWARE("radeon/RV620_pfp.bin");
+MODULE_FIRMWARE("radeon/RV620_me.bin");
+MODULE_FIRMWARE("radeon/RV635_pfp.bin");
+MODULE_FIRMWARE("radeon/RV635_me.bin");
+MODULE_FIRMWARE("radeon/RV670_pfp.bin");
+MODULE_FIRMWARE("radeon/RV670_me.bin");
+MODULE_FIRMWARE("radeon/RS780_pfp.bin");
+MODULE_FIRMWARE("radeon/RS780_me.bin");
+MODULE_FIRMWARE("radeon/RV770_pfp.bin");
+MODULE_FIRMWARE("radeon/RV770_me.bin");
+MODULE_FIRMWARE("radeon/RV730_pfp.bin");
+MODULE_FIRMWARE("radeon/RV730_me.bin");
+MODULE_FIRMWARE("radeon/RV710_pfp.bin");
+MODULE_FIRMWARE("radeon/RV710_me.bin");
 
 # define ATI_PCIGART_PAGE_SIZE		4096	/**< PCI GART page size */
 # define ATI_PCIGART_PAGE_MASK		(~(ATI_PCIGART_PAGE_SIZE-1))
@@ -275,11 +300,93 @@ static void r600_vm_init(struct drm_device *dev)
 	r600_vm_flush_gart_range(dev);
 }
 
-/* load r600 microcode */
+static int r600_cp_init_microcode(drm_radeon_private_t *dev_priv)
+{
+	struct platform_device *pdev;
+	const char *chip_name;
+	size_t pfp_req_size, me_req_size;
+	char fw_name[30];
+	int err;
+
+	pdev = platform_device_register_simple("r600_cp", 0, NULL, 0);
+	err = IS_ERR(pdev);
+	if (err) {
+		printk(KERN_ERR "r600_cp: Failed to register firmware\n");
+		return -EINVAL;
+	}
+
+	switch (dev_priv->flags & RADEON_FAMILY_MASK) {
+	case CHIP_R600:  chip_name = "R600";  break;
+	case CHIP_RV610: chip_name = "RV610"; break;
+	case CHIP_RV630: chip_name = "RV630"; break;
+	case CHIP_RV620: chip_name = "RV620"; break;
+	case CHIP_RV635: chip_name = "RV635"; break;
+	case CHIP_RV670: chip_name = "RV670"; break;
+	case CHIP_RS780:
+	case CHIP_RS880: chip_name = "RS780"; break;
+	case CHIP_RV770: chip_name = "RV770"; break;
+	case CHIP_RV730:
+	case CHIP_RV740: chip_name = "RV730"; break;
+	case CHIP_RV710: chip_name = "RV710"; break;
+	default:         BUG();
+	}
+
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
+		pfp_req_size = R700_PFP_UCODE_SIZE * 4;
+		me_req_size = R700_PM4_UCODE_SIZE * 4;
+	} else {
+		pfp_req_size = PFP_UCODE_SIZE * 4;
+		me_req_size = PM4_UCODE_SIZE * 12;
+	}
+
+	DRM_INFO("Loading %s CP Microcode\n", chip_name);
+
+	snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
+	err = request_firmware(&dev_priv->pfp_fw, fw_name, &pdev->dev);
+	if (err)
+		goto out;
+	if (dev_priv->pfp_fw->size != pfp_req_size) {
+		printk(KERN_ERR
+		       "r600_cp: Bogus length %zu in firmware \"%s\"\n",
+		       dev_priv->pfp_fw->size, fw_name);
+		err = -EINVAL;
+		goto out;
+	}
+
+	snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
+	err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev);
+	if (err)
+		goto out;
+	if (dev_priv->me_fw->size != me_req_size) {
+		printk(KERN_ERR
+		       "r600_cp: Bogus length %zu in firmware \"%s\"\n",
+		       dev_priv->me_fw->size, fw_name);
+		err = -EINVAL;
+	}
+out:
+	platform_device_unregister(pdev);
+
+	if (err) {
+		if (err != -EINVAL)
+			printk(KERN_ERR
+			       "r600_cp: Failed to load firmware \"%s\"\n",
+			       fw_name);
+		release_firmware(dev_priv->pfp_fw);
+		dev_priv->pfp_fw = NULL;
+		release_firmware(dev_priv->me_fw);
+		dev_priv->me_fw = NULL;
+	}
+	return err;
+}
+
 static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
 {
+	const __be32 *fw_data;
 	int i;
 
+	if (!dev_priv->me_fw || !dev_priv->pfp_fw)
+		return;
+
 	r600_do_cp_stop(dev_priv);
 
 	RADEON_WRITE(R600_CP_RB_CNTL,
@@ -292,115 +399,18 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
 	DRM_UDELAY(15000);
 	RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
 
+	fw_data = (const __be32 *)dev_priv->me_fw->data;
 	RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
+	for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
+		RADEON_WRITE(R600_CP_ME_RAM_DATA,
+			     be32_to_cpup(fw_data++));
 
-	if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600)) {
-		DRM_INFO("Loading R600 CP Microcode\n");
-		for (i = 0; i < PM4_UCODE_SIZE; i++) {
-			RADEON_WRITE(R600_CP_ME_RAM_DATA,
-				     R600_cp_microcode[i][0]);
-			RADEON_WRITE(R600_CP_ME_RAM_DATA,
-				     R600_cp_microcode[i][1]);
-			RADEON_WRITE(R600_CP_ME_RAM_DATA,
-				     R600_cp_microcode[i][2]);
-		}
-
-		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
-		DRM_INFO("Loading R600 PFP Microcode\n");
-		for (i = 0; i < PFP_UCODE_SIZE; i++)
-			RADEON_WRITE(R600_CP_PFP_UCODE_DATA, R600_pfp_microcode[i]);
-	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610)) {
-		DRM_INFO("Loading RV610 CP Microcode\n");
-		for (i = 0; i < PM4_UCODE_SIZE; i++) {
-			RADEON_WRITE(R600_CP_ME_RAM_DATA,
-				     RV610_cp_microcode[i][0]);
-			RADEON_WRITE(R600_CP_ME_RAM_DATA,
-				     RV610_cp_microcode[i][1]);
-			RADEON_WRITE(R600_CP_ME_RAM_DATA,
-				     RV610_cp_microcode[i][2]);
-		}
-
-		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
-		DRM_INFO("Loading RV610 PFP Microcode\n");
-		for (i = 0; i < PFP_UCODE_SIZE; i++)
-			RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV610_pfp_microcode[i]);
-	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
-		DRM_INFO("Loading RV630 CP Microcode\n");
-		for (i = 0; i < PM4_UCODE_SIZE; i++) {
-			RADEON_WRITE(R600_CP_ME_RAM_DATA,
-				     RV630_cp_microcode[i][0]);
-			RADEON_WRITE(R600_CP_ME_RAM_DATA,
-				     RV630_cp_microcode[i][1]);
-			RADEON_WRITE(R600_CP_ME_RAM_DATA,
-				     RV630_cp_microcode[i][2]);
-		}
-
-		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
-		DRM_INFO("Loading RV630 PFP Microcode\n");
-		for (i = 0; i < PFP_UCODE_SIZE; i++)
-			RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV630_pfp_microcode[i]);
-	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620)) {
-		DRM_INFO("Loading RV620 CP Microcode\n");
-		for (i = 0; i < PM4_UCODE_SIZE; i++) {
-			RADEON_WRITE(R600_CP_ME_RAM_DATA,
-				     RV620_cp_microcode[i][0]);
-			RADEON_WRITE(R600_CP_ME_RAM_DATA,
-				     RV620_cp_microcode[i][1]);
-			RADEON_WRITE(R600_CP_ME_RAM_DATA,
-				     RV620_cp_microcode[i][2]);
-		}
-
-		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
-		DRM_INFO("Loading RV620 PFP Microcode\n");
-		for (i = 0; i < PFP_UCODE_SIZE; i++)
-			RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV620_pfp_microcode[i]);
-	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
-		DRM_INFO("Loading RV635 CP Microcode\n");
-		for (i = 0; i < PM4_UCODE_SIZE; i++) {
-			RADEON_WRITE(R600_CP_ME_RAM_DATA,
-				     RV635_cp_microcode[i][0]);
-			RADEON_WRITE(R600_CP_ME_RAM_DATA,
-				     RV635_cp_microcode[i][1]);
-			RADEON_WRITE(R600_CP_ME_RAM_DATA,
-				     RV635_cp_microcode[i][2]);
-		}
-
-		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
-		DRM_INFO("Loading RV635 PFP Microcode\n");
-		for (i = 0; i < PFP_UCODE_SIZE; i++)
-			RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV635_pfp_microcode[i]);
-	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)) {
-		DRM_INFO("Loading RV670 CP Microcode\n");
-		for (i = 0; i < PM4_UCODE_SIZE; i++) {
-			RADEON_WRITE(R600_CP_ME_RAM_DATA,
-				     RV670_cp_microcode[i][0]);
-			RADEON_WRITE(R600_CP_ME_RAM_DATA,
-				     RV670_cp_microcode[i][1]);
-			RADEON_WRITE(R600_CP_ME_RAM_DATA,
-				     RV670_cp_microcode[i][2]);
-		}
-
-		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
-		DRM_INFO("Loading RV670 PFP Microcode\n");
-		for (i = 0; i < PFP_UCODE_SIZE; i++)
-			RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV670_pfp_microcode[i]);
-	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
-		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
-		DRM_INFO("Loading RS780/RS880 CP Microcode\n");
-		for (i = 0; i < PM4_UCODE_SIZE; i++) {
-			RADEON_WRITE(R600_CP_ME_RAM_DATA,
-				     RS780_cp_microcode[i][0]);
-			RADEON_WRITE(R600_CP_ME_RAM_DATA,
-				     RS780_cp_microcode[i][1]);
-			RADEON_WRITE(R600_CP_ME_RAM_DATA,
-				     RS780_cp_microcode[i][2]);
-		}
+	fw_data = (const __be32 *)dev_priv->pfp_fw->data;
+	RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
+	for (i = 0; i < PFP_UCODE_SIZE; i++)
+		RADEON_WRITE(R600_CP_PFP_UCODE_DATA,
+			     be32_to_cpup(fw_data++));
 
-		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
-		DRM_INFO("Loading RS780/RS880 PFP Microcode\n");
-		for (i = 0; i < PFP_UCODE_SIZE; i++)
-			RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RS780_pfp_microcode[i]);
-	}
 	RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 	RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 	RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
@@ -459,11 +469,14 @@ static void r700_vm_init(struct drm_device *dev)
 	r600_vm_flush_gart_range(dev);
 }
 
-/* load r600 microcode */
 static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
 {
+	const __be32 *fw_data;
 	int i;
 
+	if (!dev_priv->me_fw || !dev_priv->pfp_fw)
+		return;
+
 	r600_do_cp_stop(dev_priv);
 
 	RADEON_WRITE(R600_CP_RB_CNTL,
@@ -476,48 +489,18 @@ static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
 	DRM_UDELAY(15000);
 	RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
 
+	fw_data = (const __be32 *)dev_priv->pfp_fw->data;
+	RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
+	for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
+		RADEON_WRITE(R600_CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
+	RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 
-	if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)) {
-		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
-		DRM_INFO("Loading RV770/RV790 PFP Microcode\n");
-		for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
-			RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV770_pfp_microcode[i]);
-		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
-
-		RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
-		DRM_INFO("Loading RV770/RV790 CP Microcode\n");
-		for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
-			RADEON_WRITE(R600_CP_ME_RAM_DATA, RV770_cp_microcode[i]);
-		RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
-
-	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV730) ||
-		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740)) {
-		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
-		DRM_INFO("Loading RV730/RV740 PFP Microcode\n");
-		for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
-			RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV730_pfp_microcode[i]);
-		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
-
-		RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
-		DRM_INFO("Loading RV730/RV740 CP Microcode\n");
-		for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
-			RADEON_WRITE(R600_CP_ME_RAM_DATA, RV730_cp_microcode[i]);
-		RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
-
-	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)) {
-		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
-		DRM_INFO("Loading RV710 PFP Microcode\n");
-		for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
-			RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV710_pfp_microcode[i]);
-		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
-
-		RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
-		DRM_INFO("Loading RV710 CP Microcode\n");
-		for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
-			RADEON_WRITE(R600_CP_ME_RAM_DATA, RV710_cp_microcode[i]);
-		RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
+	fw_data = (const __be32 *)dev_priv->me_fw->data;
+	RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
+	for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
+		RADEON_WRITE(R600_CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
+	RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 
-	}
 	RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 	RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 	RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
@@ -2147,6 +2130,14 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
 			r600_vm_init(dev);
 	}
 
+	if (!dev_priv->me_fw || !dev_priv->pfp_fw) {
+		int err = r600_cp_init_microcode(dev_priv);
+		if (err) {
+			DRM_ERROR("Failed to load firmware!\n");
+			r600_do_cleanup_cp(dev);
+			return err;
+		}
+	}
 	if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
 		r700_cp_load_microcode(dev_priv);
 	else
diff --git a/drivers/gpu/drm/radeon/r600_microcode.h b/drivers/gpu/drm/radeon/r600_microcode.h
deleted file mode 100644
index 778c8b4b2fd..00000000000
--- a/drivers/gpu/drm/radeon/r600_microcode.h
+++ /dev/null
@@ -1,23297 +0,0 @@
-/*
- * Copyright 2008-2009 Advanced Micro Devices, Inc.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef R600_MICROCODE_H
-#define R600_MICROCODE_H
-
-static const int ME_JUMP_TABLE_START = 1764;
-static const int ME_JUMP_TABLE_END   = 1792;
-
-#define PFP_UCODE_SIZE 576
-#define PM4_UCODE_SIZE 1792
-#define R700_PFP_UCODE_SIZE 848
-#define R700_PM4_UCODE_SIZE 1360
-
-static const u32 R600_cp_microcode[][3] = {
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x0000ffff, 0x00284621, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x00000000, 0x00e00000, 0x000 },
-    { 0x00010000, 0xc0294620, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00042004, 0x00604411, 0x614 },
-    { 0x00000000, 0x00600000, 0x5b2 },
-    { 0x00000000, 0x00600000, 0x5c5 },
-    { 0x00000000, 0xc0200800, 0x000 },
-    { 0x00000f00, 0x00281622, 0x000 },
-    { 0x00000008, 0x00211625, 0x000 },
-    { 0x00000020, 0x00203625, 0x000 },
-    { 0x8d000000, 0x00204411, 0x000 },
-    { 0x00000004, 0x002f0225, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x018 },
-    { 0x00412000, 0x00404811, 0x019 },
-    { 0x00422000, 0x00204811, 0x000 },
-    { 0x8e000000, 0x00204411, 0x000 },
-    { 0x00000031, 0x00204a2d, 0x000 },
-    { 0x90000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204805, 0x000 },
-    { 0x0000000c, 0x00211622, 0x000 },
-    { 0x00000003, 0x00281625, 0x000 },
-    { 0x00000019, 0x00211a22, 0x000 },
-    { 0x00000004, 0x00281a26, 0x000 },
-    { 0x00000000, 0x002914c5, 0x000 },
-    { 0x00000021, 0x00203625, 0x000 },
-    { 0x00000000, 0x003a1402, 0x000 },
-    { 0x00000016, 0x00211625, 0x000 },
-    { 0x00000003, 0x00281625, 0x000 },
-    { 0x0000001d, 0x00200e2d, 0x000 },
-    { 0xfffffffc, 0x00280e23, 0x000 },
-    { 0x00000000, 0x002914a3, 0x000 },
-    { 0x0000001d, 0x00203625, 0x000 },
-    { 0x00008000, 0x00280e22, 0x000 },
-    { 0x00000007, 0x00220e23, 0x000 },
-    { 0x00000000, 0x0029386e, 0x000 },
-    { 0x20000000, 0x00280e22, 0x000 },
-    { 0x00000006, 0x00210e23, 0x000 },
-    { 0x00000000, 0x0029386e, 0x000 },
-    { 0x00000000, 0x00220222, 0x000 },
-    { 0x00000000, 0x14e00000, 0x038 },
-    { 0x00000000, 0x2ee00000, 0x035 },
-    { 0x00000000, 0x2ce00000, 0x037 },
-    { 0x00000000, 0x00400e2d, 0x039 },
-    { 0x00000008, 0x00200e2d, 0x000 },
-    { 0x00000009, 0x0040122d, 0x046 },
-    { 0x00000001, 0x00400e2d, 0x039 },
-    { 0x00000000, 0xc0200c00, 0x000 },
-    { 0x003ffffc, 0x00281223, 0x000 },
-    { 0x00000002, 0x00221224, 0x000 },
-    { 0x0000001f, 0x00211e23, 0x000 },
-    { 0x00000000, 0x14e00000, 0x03e },
-    { 0x00000008, 0x00401c11, 0x041 },
-    { 0x0000000d, 0x00201e2d, 0x000 },
-    { 0x0000000f, 0x00281e27, 0x000 },
-    { 0x00000003, 0x00221e27, 0x000 },
-    { 0x7fc00000, 0x00281a23, 0x000 },
-    { 0x00000014, 0x00211a26, 0x000 },
-    { 0x00000001, 0x00331a26, 0x000 },
-    { 0x00000008, 0x00221a26, 0x000 },
-    { 0x00000000, 0x00290cc7, 0x000 },
-    { 0x00000030, 0x00203624, 0x000 },
-    { 0x00007f00, 0x00281221, 0x000 },
-    { 0x00001400, 0x002f0224, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x04b },
-    { 0x00000001, 0x00290e23, 0x000 },
-    { 0x00000010, 0x00203623, 0x000 },
-    { 0x0000e000, 0x00204411, 0x000 },
-    { 0xfff80000, 0x00294a23, 0x000 },
-    { 0x00000000, 0x003a2c02, 0x000 },
-    { 0x00000002, 0x00220e2b, 0x000 },
-    { 0xfc000000, 0x00280e23, 0x000 },
-    { 0x00000011, 0x00203623, 0x000 },
-    { 0x00001fff, 0x00294a23, 0x000 },
-    { 0x00000030, 0x00204a2d, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000032, 0x00200e2d, 0x000 },
-    { 0x060a0200, 0x00294a23, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000001, 0x00210222, 0x000 },
-    { 0x00000000, 0x14e00000, 0x061 },
-    { 0x00000000, 0x2ee00000, 0x05f },
-    { 0x00000000, 0x2ce00000, 0x05e },
-    { 0x00000000, 0x00400e2d, 0x062 },
-    { 0x00000001, 0x00400e2d, 0x062 },
-    { 0x0000000a, 0x00200e2d, 0x000 },
-    { 0x0000000b, 0x0040122d, 0x06a },
-    { 0x00000000, 0xc0200c00, 0x000 },
-    { 0x003ffffc, 0x00281223, 0x000 },
-    { 0x00000002, 0x00221224, 0x000 },
-    { 0x7fc00000, 0x00281623, 0x000 },
-    { 0x00000014, 0x00211625, 0x000 },
-    { 0x00000001, 0x00331625, 0x000 },
-    { 0x80000000, 0x00280e23, 0x000 },
-    { 0x00000000, 0x00290ca3, 0x000 },
-    { 0x3ffffc00, 0x00290e23, 0x000 },
-    { 0x0000001f, 0x00211e23, 0x000 },
-    { 0x00000000, 0x14e00000, 0x06d },
-    { 0x00000100, 0x00401c11, 0x070 },
-    { 0x0000000d, 0x00201e2d, 0x000 },
-    { 0x000000f0, 0x00281e27, 0x000 },
-    { 0x00000004, 0x00221e27, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000d, 0x00204811, 0x000 },
-    { 0xfffff0ff, 0x00281a30, 0x000 },
-    { 0x0000a028, 0x00204411, 0x000 },
-    { 0x00000000, 0x002948e6, 0x000 },
-    { 0x0000a018, 0x00204411, 0x000 },
-    { 0x3fffffff, 0x00284a23, 0x000 },
-    { 0x0000a010, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204804, 0x000 },
-    { 0x0000002d, 0x0020162d, 0x000 },
-    { 0x00000000, 0x002f00a3, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x080 },
-    { 0x0000002e, 0x0020162d, 0x000 },
-    { 0x00000000, 0x002f00a4, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x081 },
-    { 0x00000000, 0x00400000, 0x087 },
-    { 0x0000002d, 0x00203623, 0x000 },
-    { 0x0000002e, 0x00203624, 0x000 },
-    { 0x0000001d, 0x00201e2d, 0x000 },
-    { 0x00000002, 0x00210227, 0x000 },
-    { 0x00000000, 0x14e00000, 0x087 },
-    { 0x00000000, 0x00600000, 0x5ed },
-    { 0x00000000, 0x00600000, 0x5e1 },
-    { 0x00000002, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x08a },
-    { 0x00000018, 0xc0403620, 0x090 },
-    { 0x00000000, 0x2ee00000, 0x08e },
-    { 0x00000000, 0x2ce00000, 0x08d },
-    { 0x00000002, 0x00400e2d, 0x08f },
-    { 0x00000003, 0x00400e2d, 0x08f },
-    { 0x0000000c, 0x00200e2d, 0x000 },
-    { 0x00000018, 0x00203623, 0x000 },
-    { 0x00000003, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x095 },
-    { 0x0000a00c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0404800, 0x09d },
-    { 0x0000a00c, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x2ee00000, 0x09b },
-    { 0x00000000, 0x2ce00000, 0x09a },
-    { 0x00000002, 0x00400e2d, 0x09c },
-    { 0x00000003, 0x00400e2d, 0x09c },
-    { 0x0000000c, 0x00200e2d, 0x000 },
-    { 0x00000000, 0x00204803, 0x000 },
-    { 0x00000000, 0x003a0c02, 0x000 },
-    { 0x003f0000, 0x00280e23, 0x000 },
-    { 0x00000010, 0x00210e23, 0x000 },
-    { 0x00000013, 0x00203623, 0x000 },
-    { 0x0000001e, 0x0021022b, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0a4 },
-    { 0x0000001c, 0xc0203620, 0x000 },
-    { 0x0000001f, 0x0021022b, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0a7 },
-    { 0x0000001b, 0xc0203620, 0x000 },
-    { 0x00000008, 0x00210e2b, 0x000 },
-    { 0x0000007f, 0x00280e23, 0x000 },
-    { 0x00000000, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0db },
-    { 0x00000000, 0x27000000, 0x000 },
-    { 0x00000000, 0x00600000, 0x28c },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000006, 0x00204811, 0x000 },
-    { 0x0000000c, 0x00221e30, 0x000 },
-    { 0x99800000, 0x00204411, 0x000 },
-    { 0x00000004, 0x0020122d, 0x000 },
-    { 0x00000008, 0x00221224, 0x000 },
-    { 0x00000010, 0x00201811, 0x000 },
-    { 0x00000000, 0x00291ce4, 0x000 },
-    { 0x00000000, 0x00604807, 0x128 },
-    { 0x9b000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204802, 0x000 },
-    { 0x9c000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x0033146f, 0x000 },
-    { 0x00000001, 0x00333e23, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0x00203c05, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000e, 0x00204811, 0x000 },
-    { 0x00000000, 0x00201010, 0x000 },
-    { 0x0000e007, 0x00204411, 0x000 },
-    { 0x0000000f, 0x0021022b, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0c5 },
-    { 0x00f8ff08, 0x00204811, 0x000 },
-    { 0x98000000, 0x00404811, 0x0d6 },
-    { 0x000000f0, 0x00280e22, 0x000 },
-    { 0x000000a0, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x0d4 },
-    { 0x00000013, 0x00200e2d, 0x000 },
-    { 0x00000001, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0cf },
-    { 0x00000002, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0ce },
-    { 0x00003f00, 0x00400c11, 0x0d0 },
-    { 0x00001f00, 0x00400c11, 0x0d0 },
-    { 0x00000f00, 0x00200c11, 0x000 },
-    { 0x00380009, 0x00294a23, 0x000 },
-    { 0x3f000000, 0x00280e2b, 0x000 },
-    { 0x00000002, 0x00220e23, 0x000 },
-    { 0x00000007, 0x00494a23, 0x0d6 },
-    { 0x00380f09, 0x00204811, 0x000 },
-    { 0x68000007, 0x00204811, 0x000 },
-    { 0x00000008, 0x00214a27, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x060a0200, 0x00294a24, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000a202, 0x00204411, 0x000 },
-    { 0x00ff0000, 0x00284a22, 0x000 },
-    { 0x00000030, 0x00200e2d, 0x000 },
-    { 0x0000002e, 0x0020122d, 0x000 },
-    { 0x00000000, 0x002f0083, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0e3 },
-    { 0x00000000, 0x00600000, 0x5e7 },
-    { 0x00000000, 0x00400000, 0x0e4 },
-    { 0x00000000, 0x00600000, 0x5ea },
-    { 0x00000007, 0x0020222d, 0x000 },
-    { 0x00000005, 0x00220e22, 0x000 },
-    { 0x00100000, 0x00280e23, 0x000 },
-    { 0x00000000, 0x00292068, 0x000 },
-    { 0x00000000, 0x003a0c02, 0x000 },
-    { 0x000000ef, 0x00280e23, 0x000 },
-    { 0x00000000, 0x00292068, 0x000 },
-    { 0x0000001d, 0x00200e2d, 0x000 },
-    { 0x00000003, 0x00210223, 0x000 },
-    { 0x00000000, 0x14e00000, 0x0f1 },
-    { 0x0000000b, 0x00210228, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0f1 },
-    { 0x00000400, 0x00292228, 0x000 },
-    { 0x0000001a, 0x00203628, 0x000 },
-    { 0x0000001c, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0f6 },
-    { 0x0000a30c, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000001e, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x104 },
-    { 0x0000a30f, 0x00204411, 0x000 },
-    { 0x00000013, 0x00200e2d, 0x000 },
-    { 0x00000001, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x0fd },
-    { 0xffffffff, 0x00404811, 0x104 },
-    { 0x00000002, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x100 },
-    { 0x0000ffff, 0x00404811, 0x104 },
-    { 0x00000004, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x103 },
-    { 0x000000ff, 0x00404811, 0x104 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0002c400, 0x00204411, 0x000 },
-    { 0x0000001f, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x10b },
-    { 0x00000010, 0x40210e20, 0x000 },
-    { 0x00000019, 0x00203623, 0x000 },
-    { 0x00000018, 0x40224a20, 0x000 },
-    { 0x00000010, 0xc0424a20, 0x10d },
-    { 0x00000000, 0x00200c11, 0x000 },
-    { 0x00000019, 0x00203623, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000000a, 0x00201011, 0x000 },
-    { 0x00000000, 0x002f0224, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x114 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000001, 0x00531224, 0x110 },
-    { 0xffbfffff, 0x00283a2e, 0x000 },
-    { 0x0000001b, 0x00210222, 0x000 },
-    { 0x00000000, 0x14c00000, 0x127 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000d, 0x00204811, 0x000 },
-    { 0x00000018, 0x00220e30, 0x000 },
-    { 0xfc000000, 0x00280e23, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000e, 0x00204811, 0x000 },
-    { 0x00000000, 0x00201010, 0x000 },
-    { 0x0000e00e, 0x00204411, 0x000 },
-    { 0x07f8ff08, 0x00204811, 0x000 },
-    { 0x00000000, 0x00294a23, 0x000 },
-    { 0x00000024, 0x00201e2d, 0x000 },
-    { 0x00000008, 0x00214a27, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x060a0200, 0x00294a24, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0000217c, 0x00204411, 0x000 },
-    { 0x00800000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204806, 0x000 },
-    { 0x00000008, 0x00214a27, 0x000 },
-    { 0x00000000, 0x17000000, 0x000 },
-    { 0x0004217f, 0x00604411, 0x614 },
-    { 0x0000001f, 0x00210230, 0x000 },
-    { 0x00000000, 0x14c00000, 0x613 },
-    { 0x00000004, 0x00404c11, 0x12e },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600411, 0x2fe },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x19f },
-    { 0x00000000, 0x00600000, 0x151 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x00000010, 0xc0211220, 0x000 },
-    { 0x0000ffff, 0x40280620, 0x000 },
-    { 0x00000010, 0xc0210a20, 0x000 },
-    { 0x00000000, 0x00341461, 0x000 },
-    { 0x00000000, 0x00741882, 0x2a4 },
-    { 0x0001a1fd, 0x00604411, 0x2c9 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x138 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600411, 0x2fe },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x19f },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00600000, 0x151 },
-    { 0x00000010, 0x40210e20, 0x000 },
-    { 0x0000ffff, 0xc0281220, 0x000 },
-    { 0x00000010, 0x40211620, 0x000 },
-    { 0x0000ffff, 0xc0681a20, 0x2a4 },
-    { 0x0001a1fd, 0x00604411, 0x2c9 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x149 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000001, 0x00300a2f, 0x000 },
-    { 0x00000001, 0x00210a22, 0x000 },
-    { 0x00000003, 0x00384a22, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001a, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00804811, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600000, 0x17c },
-    { 0x00000000, 0x00600000, 0x18d },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00202c08, 0x000 },
-    { 0x00000000, 0x00202411, 0x000 },
-    { 0x00000000, 0x00202811, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x00000016, 0x00204811, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x93800000, 0x00204411, 0x000 },
-    { 0x00000002, 0x00221e29, 0x000 },
-    { 0x00000000, 0x007048eb, 0x189 },
-    { 0x00000000, 0x00600000, 0x2a4 },
-    { 0x00000001, 0x40330620, 0x000 },
-    { 0x00000000, 0xc0302409, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00600000, 0x28c },
-    { 0x95000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x173 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000001, 0x00530621, 0x16f },
-    { 0x92000000, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0604800, 0x184 },
-    { 0x0001a1fd, 0x00204411, 0x000 },
-    { 0x00000013, 0x0020062d, 0x000 },
-    { 0x00000000, 0x0078042a, 0x2e4 },
-    { 0x00000000, 0x00202809, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x165 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000210, 0x00600411, 0x2fe },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x181 },
-    { 0x0000001b, 0xc0203620, 0x000 },
-    { 0x0000001c, 0xc0203620, 0x000 },
-    { 0x3f800000, 0x00200411, 0x000 },
-    { 0x46000000, 0x00600811, 0x19f },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x188 },
-    { 0x00000001, 0x00804811, 0x000 },
-    { 0x00000021, 0x00804811, 0x000 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x00000010, 0xc0211220, 0x000 },
-    { 0x0000ffff, 0x40281620, 0x000 },
-    { 0x00000010, 0xc0811a20, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000006, 0x00204811, 0x000 },
-    { 0x00000008, 0x00221e30, 0x000 },
-    { 0x00000032, 0x00201a2d, 0x000 },
-    { 0x0000e000, 0x00204411, 0x000 },
-    { 0xfffbff09, 0x00204811, 0x000 },
-    { 0x00000011, 0x0020222d, 0x000 },
-    { 0x00001fff, 0x00294a28, 0x000 },
-    { 0x00000006, 0x0020222d, 0x000 },
-    { 0x00000000, 0x002920e8, 0x000 },
-    { 0x00000000, 0x00204808, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x060a0200, 0x00294a26, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000100, 0x00201811, 0x000 },
-    { 0x00000008, 0x00621e28, 0x128 },
-    { 0x00000008, 0x00822228, 0x000 },
-    { 0x0002c000, 0x00204411, 0x000 },
-    { 0x0000001b, 0x00600e2d, 0x1aa },
-    { 0x0000001c, 0x00600e2d, 0x1aa },
-    { 0x0000c008, 0x00204411, 0x000 },
-    { 0x0000001d, 0x00200e2d, 0x000 },
-    { 0x00000000, 0x14c00000, 0x1a6 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00204801, 0x000 },
-    { 0x39000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00804802, 0x000 },
-    { 0x00000020, 0x00202e2d, 0x000 },
-    { 0x00000000, 0x003b0d63, 0x000 },
-    { 0x00000008, 0x00224a23, 0x000 },
-    { 0x00000010, 0x00224a23, 0x000 },
-    { 0x00000018, 0x00224a23, 0x000 },
-    { 0x00000000, 0x00804803, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00001000, 0x00600411, 0x2fe },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x19f },
-    { 0x00000007, 0x0021062f, 0x000 },
-    { 0x00000019, 0x00200a2d, 0x000 },
-    { 0x00000001, 0x00202c11, 0x000 },
-    { 0x0000ffff, 0x40282220, 0x000 },
-    { 0x0000000f, 0x00262228, 0x000 },
-    { 0x00000010, 0x40212620, 0x000 },
-    { 0x0000000f, 0x00262629, 0x000 },
-    { 0x00000000, 0x00202802, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001b, 0x00204811, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x1cd },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000081, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00000080, 0x00201c11, 0x000 },
-    { 0x00000000, 0x002f0227, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x1c9 },
-    { 0x00000000, 0x00600000, 0x1d6 },
-    { 0x00000001, 0x00531e27, 0x1c5 },
-    { 0x00000001, 0x00202c11, 0x000 },
-    { 0x0000001f, 0x00280a22, 0x000 },
-    { 0x0000001f, 0x00282a2a, 0x000 },
-    { 0x00000001, 0x00530621, 0x1be },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000002, 0x00304a2f, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00000001, 0x00301e2f, 0x000 },
-    { 0x00000000, 0x002f0227, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00600000, 0x1d6 },
-    { 0x00000001, 0x00531e27, 0x1d2 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x0000000f, 0x00260e23, 0x000 },
-    { 0x00000010, 0xc0211220, 0x000 },
-    { 0x0000000f, 0x00261224, 0x000 },
-    { 0x00000000, 0x00201411, 0x000 },
-    { 0x00000000, 0x00601811, 0x2a4 },
-    { 0x0001a1fd, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f022b, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x1e5 },
-    { 0x00000010, 0x00221628, 0x000 },
-    { 0xffff0000, 0x00281625, 0x000 },
-    { 0x0000ffff, 0x00281a29, 0x000 },
-    { 0x00000000, 0x002948c5, 0x000 },
-    { 0x00000000, 0x0020480a, 0x000 },
-    { 0x00000000, 0x00202c11, 0x000 },
-    { 0x00000010, 0x00221623, 0x000 },
-    { 0xffff0000, 0x00281625, 0x000 },
-    { 0x0000ffff, 0x00281a24, 0x000 },
-    { 0x00000000, 0x002948c5, 0x000 },
-    { 0x00000000, 0x00731503, 0x1f2 },
-    { 0x00000000, 0x00201805, 0x000 },
-    { 0x00000000, 0x00731524, 0x1f2 },
-    { 0x00000000, 0x002d14c5, 0x000 },
-    { 0x00000000, 0x003008a2, 0x000 },
-    { 0x00000000, 0x00204802, 0x000 },
-    { 0x00000000, 0x00202802, 0x000 },
-    { 0x00000000, 0x00202003, 0x000 },
-    { 0x00000000, 0x00802404, 0x000 },
-    { 0x0000000f, 0x00210225, 0x000 },
-    { 0x00000000, 0x14c00000, 0x613 },
-    { 0x00000000, 0x002b1405, 0x000 },
-    { 0x00000001, 0x00901625, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600411, 0x2fe },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x19f },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001a, 0x00294a22, 0x000 },
-    { 0x00000000, 0xc0200000, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00384a21, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0000ffff, 0x40281220, 0x000 },
-    { 0x00000010, 0xc0211a20, 0x000 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x00000010, 0xc0211620, 0x000 },
-    { 0x00000000, 0x00741465, 0x2a4 },
-    { 0x0001a1fd, 0x00604411, 0x2c9 },
-    { 0x00000001, 0x00330621, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x206 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x1ff },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000000, 0x00600000, 0x5c5 },
-    { 0x00000000, 0x0040040f, 0x200 },
-    { 0x00000000, 0x00600000, 0x5b2 },
-    { 0x00000000, 0x00600000, 0x5c5 },
-    { 0x00000210, 0x00600411, 0x2fe },
-    { 0x00000000, 0x00600000, 0x18d },
-    { 0x00000000, 0x00600000, 0x189 },
-    { 0x00000000, 0x00600000, 0x2a4 },
-    { 0x00000000, 0x00600000, 0x28c },
-    { 0x93800000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204808, 0x000 },
-    { 0x95000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x21f },
-    { 0x00000000, 0xc0404800, 0x21c },
-    { 0x92000000, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x00000016, 0x00204811, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0001a1fd, 0x00204411, 0x000 },
-    { 0x00000000, 0x00600411, 0x2e4 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000000, 0x00600000, 0x5b2 },
-    { 0x0000a00c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0404800, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000018, 0x40210a20, 0x000 },
-    { 0x00000003, 0x002f0222, 0x000 },
-    { 0x00000000, 0x0ae00000, 0x235 },
-    { 0x0000001a, 0x0020222d, 0x000 },
-    { 0x00080101, 0x00292228, 0x000 },
-    { 0x0000001a, 0x00203628, 0x000 },
-    { 0x0000a30c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0404800, 0x23a },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000010, 0x00600411, 0x2fe },
-    { 0x3f800000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x19f },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x00000000, 0x00600000, 0x265 },
-    { 0x0000001d, 0x00201e2d, 0x000 },
-    { 0x00000001, 0x00211e27, 0x000 },
-    { 0x00000000, 0x14e00000, 0x253 },
-    { 0x00000018, 0x00201e2d, 0x000 },
-    { 0x0000ffff, 0x00281e27, 0x000 },
-    { 0x00000000, 0x00341c27, 0x000 },
-    { 0x00000000, 0x12c00000, 0x248 },
-    { 0x00000000, 0x00201c11, 0x000 },
-    { 0x00000000, 0x002f00e5, 0x000 },
-    { 0x00000000, 0x08c00000, 0x24b },
-    { 0x00000000, 0x00201407, 0x000 },
-    { 0x00000018, 0x00201e2d, 0x000 },
-    { 0x00000010, 0x00211e27, 0x000 },
-    { 0x00000000, 0x00341c47, 0x000 },
-    { 0x00000000, 0x12c00000, 0x250 },
-    { 0x00000000, 0x00201c11, 0x000 },
-    { 0x00000000, 0x002f00e6, 0x000 },
-    { 0x00000000, 0x08c00000, 0x253 },
-    { 0x00000000, 0x00201807, 0x000 },
-    { 0x00000000, 0x00600000, 0x2aa },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x00000000, 0x00342023, 0x000 },
-    { 0x00000000, 0x12c00000, 0x25b },
-    { 0x00000000, 0x00342044, 0x000 },
-    { 0x00000000, 0x12c00000, 0x25a },
-    { 0x00000016, 0x00404811, 0x25f },
-    { 0x00000018, 0x00404811, 0x25f },
-    { 0x00000000, 0x00342044, 0x000 },
-    { 0x00000000, 0x12c00000, 0x25e },
-    { 0x00000017, 0x00404811, 0x25f },
-    { 0x00000019, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0001a1fd, 0x00604411, 0x2d2 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x23f },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000010, 0x40210620, 0x000 },
-    { 0x0000ffff, 0xc0280a20, 0x000 },
-    { 0x00000010, 0x40210e20, 0x000 },
-    { 0x0000ffff, 0xc0281220, 0x000 },
-    { 0x00000010, 0x40211620, 0x000 },
-    { 0x0000ffff, 0xc0881a20, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00042004, 0x00604411, 0x614 },
-    { 0x00000000, 0x00600000, 0x5b2 },
-    { 0x00000000, 0xc0600000, 0x28c },
-    { 0x00000005, 0x00200a2d, 0x000 },
-    { 0x00000008, 0x00220a22, 0x000 },
-    { 0x00000034, 0x00201a2d, 0x000 },
-    { 0x00000024, 0x00201e2d, 0x000 },
-    { 0x00007000, 0x00281e27, 0x000 },
-    { 0x00000000, 0x00311ce6, 0x000 },
-    { 0x00000033, 0x00201a2d, 0x000 },
-    { 0x0000000c, 0x00221a26, 0x000 },
-    { 0x00000000, 0x002f00e6, 0x000 },
-    { 0x00000000, 0x06e00000, 0x27b },
-    { 0x00000000, 0x00201c11, 0x000 },
-    { 0x00000000, 0x00200c11, 0x000 },
-    { 0x00000034, 0x00203623, 0x000 },
-    { 0x00000010, 0x00201811, 0x000 },
-    { 0x00000000, 0x00691ce2, 0x128 },
-    { 0x93800000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204807, 0x000 },
-    { 0x95000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x286 },
-    { 0x00000001, 0x00333e2f, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x92000000, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000024, 0x00403627, 0x000 },
-    { 0x0000000c, 0xc0220a20, 0x000 },
-    { 0x00000032, 0x00203622, 0x000 },
-    { 0x00000031, 0xc0403620, 0x000 },
-    { 0x0000a2a4, 0x00204411, 0x000 },
-    { 0x00000009, 0x00204811, 0x000 },
-    { 0xa1000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00804811, 0x000 },
-    { 0x00000029, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x002c1ce3, 0x000 },
-    { 0x00000029, 0x00203627, 0x000 },
-    { 0x0000002a, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x002c1ce4, 0x000 },
-    { 0x0000002a, 0x00203627, 0x000 },
-    { 0x0000002b, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x003120a3, 0x000 },
-    { 0x00000000, 0x002d1d07, 0x000 },
-    { 0x0000002b, 0x00203627, 0x000 },
-    { 0x0000002c, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x003120c4, 0x000 },
-    { 0x00000000, 0x002d1d07, 0x000 },
-    { 0x0000002c, 0x00803627, 0x000 },
-    { 0x00000029, 0x00203623, 0x000 },
-    { 0x0000002a, 0x00203624, 0x000 },
-    { 0x00000000, 0x00311ca3, 0x000 },
-    { 0x0000002b, 0x00203627, 0x000 },
-    { 0x00000000, 0x00311cc4, 0x000 },
-    { 0x0000002c, 0x00803627, 0x000 },
-    { 0x00000022, 0x00203627, 0x000 },
-    { 0x00000023, 0x00203628, 0x000 },
-    { 0x0000001d, 0x00201e2d, 0x000 },
-    { 0x00000002, 0x00210227, 0x000 },
-    { 0x00000000, 0x14c00000, 0x2c5 },
-    { 0x00000000, 0x00400000, 0x2c2 },
-    { 0x00000022, 0x00203627, 0x000 },
-    { 0x00000023, 0x00203628, 0x000 },
-    { 0x0000001d, 0x00201e2d, 0x000 },
-    { 0x00000002, 0x00210227, 0x000 },
-    { 0x00000000, 0x14e00000, 0x2c2 },
-    { 0x00000003, 0x00210227, 0x000 },
-    { 0x00000000, 0x14e00000, 0x2c5 },
-    { 0x0000002b, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x002e00e1, 0x000 },
-    { 0x00000000, 0x02c00000, 0x2c5 },
-    { 0x00000029, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x003120a1, 0x000 },
-    { 0x00000000, 0x002e00e8, 0x000 },
-    { 0x00000000, 0x06c00000, 0x2c5 },
-    { 0x0000002c, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x002e00e2, 0x000 },
-    { 0x00000000, 0x02c00000, 0x2c5 },
-    { 0x0000002a, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x003120c2, 0x000 },
-    { 0x00000000, 0x002e00e8, 0x000 },
-    { 0x00000000, 0x06c00000, 0x2c5 },
-    { 0x00000000, 0x00600000, 0x5ed },
-    { 0x00000000, 0x00600000, 0x29e },
-    { 0x00000000, 0x00400000, 0x2c7 },
-    { 0x00000000, 0x00600000, 0x29e },
-    { 0x00000000, 0x00600000, 0x5e4 },
-    { 0x00000000, 0x00400000, 0x2c7 },
-    { 0x00000000, 0x00600000, 0x290 },
-    { 0x00000000, 0x00400000, 0x2c7 },
-    { 0x00000022, 0x00201e2d, 0x000 },
-    { 0x00000023, 0x0080222d, 0x000 },
-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000000, 0x00311ca3, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x003120c4, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00894907, 0x000 },
-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000010, 0x00221e21, 0x000 },
-    { 0x00000000, 0x00294847, 0x000 },
-    { 0x00000000, 0x00311ca3, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000000, 0x00311ca1, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294847, 0x000 },
-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x003120c4, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000010, 0x00221e21, 0x000 },
-    { 0x00000000, 0x003120c2, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00894907, 0x000 },
-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000001, 0x00220a21, 0x000 },
-    { 0x00000000, 0x003308a2, 0x000 },
-    { 0x00000010, 0x00221e22, 0x000 },
-    { 0x00000010, 0x00212222, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x00311ca3, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000001, 0x00220a21, 0x000 },
-    { 0x00000000, 0x003008a2, 0x000 },
-    { 0x00000010, 0x00221e22, 0x000 },
-    { 0x00000010, 0x00212222, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x003120c4, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x003808c5, 0x000 },
-    { 0x00000000, 0x00300841, 0x000 },
-    { 0x00000001, 0x00220a22, 0x000 },
-    { 0x00000000, 0x003308a2, 0x000 },
-    { 0x00000010, 0x00221e22, 0x000 },
-    { 0x00000010, 0x00212222, 0x000 },
-    { 0x00000000, 0x00894907, 0x000 },
-    { 0x0000001d, 0x0020222d, 0x000 },
-    { 0x00000000, 0x14c00000, 0x301 },
-    { 0xffffffef, 0x00280621, 0x000 },
-    { 0x0000001a, 0x0020222d, 0x000 },
-    { 0x0000f8e0, 0x00204411, 0x000 },
-    { 0x00000000, 0x00294901, 0x000 },
-    { 0x00000000, 0x00894901, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x060a0200, 0x00804811, 0x000 },
-    { 0x00000000, 0xc0200000, 0x000 },
-    { 0x97000000, 0xc0204411, 0x000 },
-    { 0x00000000, 0xc0204811, 0x000 },
-    { 0x8a000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x97000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x8a000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x97000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
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-    { 0x00000000, 0x00204811, 0x000 },
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-    { 0x00000000, 0x40204800, 0x000 },
-    { 0x00000001, 0x40304a20, 0x000 },
-    { 0x00000002, 0xc0304a20, 0x000 },
-    { 0x00000001, 0x00530a22, 0x334 },
-    { 0x0000003f, 0xc0280a20, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
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-    { 0x00000001, 0x00331a26, 0x000 },
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-    { 0x00000000, 0x00404803, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x000021f8, 0x00204411, 0x000 },
-    { 0x00000015, 0x00204811, 0x000 },
-    { 0x000421f9, 0x00604411, 0x614 },
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-    { 0x00000000, 0x00404802, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x000021f8, 0x00204411, 0x000 },
-    { 0x00000016, 0x00204811, 0x000 },
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-    { 0x00000001, 0x00204811, 0x000 },
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-    { 0x00000001, 0x00204811, 0x000 },
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-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00000000, 0xc0200800, 0x000 },
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-    { 0x00000001, 0x00204811, 0x000 },
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-    { 0x00000001, 0x00204811, 0x000 },
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-    { 0x00000000, 0xc0600000, 0x614 },
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-    { 0x00000000, 0x14c00000, 0x4b9 },
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-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0xcafebabe, 0x00404811, 0x000 },
-    { 0x00000000, 0xc0204400, 0x000 },
-    { 0x00000000, 0xc0404810, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x000021f8, 0x00204411, 0x000 },
-    { 0x0000000d, 0x00204811, 0x000 },
-    { 0x000421f9, 0x00604411, 0x614 },
-    { 0x00000000, 0x00210230, 0x000 },
-    { 0x00000000, 0x14c00000, 0x4bb },
-    { 0x00002180, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0200000, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0200000, 0x000 },
-    { 0x00000000, 0xc0404800, 0x000 },
-    { 0x00000003, 0x00333e2f, 0x000 },
-    { 0x00000001, 0x00210221, 0x000 },
-    { 0x00000000, 0x14e00000, 0x4eb },
-    { 0x00000035, 0x00200a2d, 0x000 },
-    { 0x00040000, 0x18e00c11, 0x4da },
-    { 0x00000001, 0x00333e2f, 0x000 },
-    { 0x00002169, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204802, 0x000 },
-    { 0x00000000, 0x00204803, 0x000 },
-    { 0x00000008, 0x00300a22, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00002169, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204802, 0x000 },
-    { 0x00000000, 0x00204803, 0x000 },
-    { 0x00000008, 0x00300a22, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xd8c04800, 0x4ce },
-    { 0x00002169, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204802, 0x000 },
-    { 0x00000000, 0x00204803, 0x000 },
-    { 0x00000008, 0x00300a22, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000036, 0x0020122d, 0x000 },
-    { 0x00000000, 0x00290c83, 0x000 },
-    { 0x00002169, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204802, 0x000 },
-    { 0x00000000, 0x00204803, 0x000 },
-    { 0x00000008, 0x00300a22, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000011, 0x00210224, 0x000 },
-    { 0x00000000, 0x14c00000, 0x000 },
-    { 0x00000000, 0x00400000, 0x491 },
-    { 0x00000035, 0xc0203620, 0x000 },
-    { 0x00000036, 0xc0403620, 0x000 },
-    { 0x0000304a, 0x00204411, 0x000 },
-    { 0xe0000000, 0xc0484a20, 0x000 },
-    { 0x0000000f, 0x00210221, 0x000 },
-    { 0x00000000, 0x14c00000, 0x4f2 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0xd9000000, 0x000 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000002, 0x00204811, 0x000 },
-    { 0x000000ff, 0x00280e30, 0x000 },
-    { 0x00000000, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x4f6 },
-    { 0x00000000, 0xc0200800, 0x000 },
-    { 0x00000000, 0x14c00000, 0x50b },
-    { 0x00000000, 0x00200c11, 0x000 },
-    { 0x00000024, 0x00203623, 0x000 },
-    { 0x00000034, 0x00203623, 0x000 },
-    { 0x00000032, 0x00203623, 0x000 },
-    { 0x00000031, 0x00203623, 0x000 },
-    { 0x0000001d, 0x00203623, 0x000 },
-    { 0x0000002d, 0x00203623, 0x000 },
-    { 0x0000002e, 0x00203623, 0x000 },
-    { 0x0000001b, 0x00203623, 0x000 },
-    { 0x0000001c, 0x00203623, 0x000 },
-    { 0xffffe000, 0x00200c11, 0x000 },
-    { 0x00000029, 0x00203623, 0x000 },
-    { 0x0000002a, 0x00203623, 0x000 },
-    { 0x00001fff, 0x00200c11, 0x000 },
-    { 0x0000002b, 0x00203623, 0x000 },
-    { 0x0000002c, 0x00203623, 0x000 },
-    { 0xf1ffffff, 0x00283a2e, 0x000 },
-    { 0x0000001a, 0xc0220e20, 0x000 },
-    { 0x00000000, 0x0029386e, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000006, 0x00204811, 0x000 },
-    { 0x00000033, 0x40203620, 0x000 },
-    { 0x87000000, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x0000a1f4, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x9d000000, 0x00204411, 0x000 },
-    { 0x0000001f, 0x40214a20, 0x000 },
-    { 0x96000000, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0200c00, 0x000 },
-    { 0x00000000, 0xc0201000, 0x000 },
-    { 0x0000001f, 0x00211624, 0x000 },
-    { 0x00000000, 0x14c00000, 0x000 },
-    { 0x00000025, 0x00203623, 0x000 },
-    { 0x00000003, 0x00281e23, 0x000 },
-    { 0x00000008, 0x00222223, 0x000 },
-    { 0xfffff000, 0x00282228, 0x000 },
-    { 0x00000000, 0x002920e8, 0x000 },
-    { 0x00000027, 0x00203628, 0x000 },
-    { 0x00000018, 0x00211e23, 0x000 },
-    { 0x00000028, 0x00203627, 0x000 },
-    { 0x00000002, 0x00221624, 0x000 },
-    { 0x00000000, 0x003014a8, 0x000 },
-    { 0x00000026, 0x00203625, 0x000 },
-    { 0x00000003, 0x00211a24, 0x000 },
-    { 0x10000000, 0x00281a26, 0x000 },
-    { 0xefffffff, 0x00283a2e, 0x000 },
-    { 0x00000000, 0x004938ce, 0x602 },
-    { 0x00000001, 0x40280a20, 0x000 },
-    { 0x00000006, 0x40280e20, 0x000 },
-    { 0x00000300, 0xc0281220, 0x000 },
-    { 0x00000008, 0x00211224, 0x000 },
-    { 0x00000000, 0xc0201620, 0x000 },
-    { 0x00000000, 0xc0201a20, 0x000 },
-    { 0x00000000, 0x00210222, 0x000 },
-    { 0x00000000, 0x14c00000, 0x541 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00002258, 0x00300a24, 0x000 },
-    { 0x00040000, 0x00694622, 0x614 },
-    { 0x00002169, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204805, 0x000 },
-    { 0x00020000, 0x00294a26, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0xcafebabe, 0x00204811, 0x000 },
-    { 0x00000002, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x549 },
-    { 0x00000000, 0xc0201c10, 0x000 },
-    { 0x00000000, 0xc0400000, 0x55b },
-    { 0x00000002, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x549 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00002258, 0x00300a24, 0x000 },
-    { 0x00040000, 0x00694622, 0x614 },
-    { 0x00000000, 0xc0201c10, 0x000 },
-    { 0x00000000, 0xc0400000, 0x55b },
-    { 0x00000000, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x54d },
-    { 0x00000000, 0xc0201c00, 0x000 },
-    { 0x00000000, 0xc0400000, 0x55b },
-    { 0x00000004, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x559 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000216d, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0x1ac00000, 0x554 },
-    { 0x9e000000, 0x00204411, 0x000 },
-    { 0xcafebabe, 0x00204811, 0x000 },
-    { 0x00000000, 0x1ae00000, 0x557 },
-    { 0x00000000, 0x00401c10, 0x55b },
-    { 0x00000000, 0xc0200000, 0x000 },
-    { 0x00000000, 0xc0400000, 0x000 },
-    { 0x00000000, 0x0ee00000, 0x55d },
-    { 0x00000000, 0x00600000, 0x5a4 },
-    { 0x00000000, 0x002f0224, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x56d },
-    { 0x0000a2b7, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204807, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0004a2b6, 0x00604411, 0x614 },
-    { 0x0000001a, 0x00212230, 0x000 },
-    { 0x00000006, 0x00222630, 0x000 },
-    { 0x0000a2c4, 0x00204411, 0x000 },
-    { 0x00000000, 0x003048e9, 0x000 },
-    { 0x00000000, 0x00e00000, 0x56b },
-    { 0x0000a2d1, 0x00204411, 0x000 },
-    { 0x00000000, 0x00404808, 0x000 },
-    { 0x0000a2d1, 0x00204411, 0x000 },
-    { 0x00000001, 0x00504a28, 0x000 },
-    { 0x00000001, 0x002f0224, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x57d },
-    { 0x0000a2bb, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204807, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0004a2ba, 0x00604411, 0x614 },
-    { 0x0000001a, 0x00212230, 0x000 },
-    { 0x00000006, 0x00222630, 0x000 },
-    { 0x0000a2c5, 0x00204411, 0x000 },
-    { 0x00000000, 0x003048e9, 0x000 },
-    { 0x00000000, 0x00e00000, 0x57b },
-    { 0x0000a2d2, 0x00204411, 0x000 },
-    { 0x00000000, 0x00404808, 0x000 },
-    { 0x0000a2d2, 0x00204411, 0x000 },
-    { 0x00000001, 0x00504a28, 0x000 },
-    { 0x00000002, 0x002f0224, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x58d },
-    { 0x0000a2bf, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204807, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0004a2be, 0x00604411, 0x614 },
-    { 0x0000001a, 0x00212230, 0x000 },
-    { 0x00000006, 0x00222630, 0x000 },
-    { 0x0000a2c6, 0x00204411, 0x000 },
-    { 0x00000000, 0x003048e9, 0x000 },
-    { 0x00000000, 0x00e00000, 0x58b },
-    { 0x0000a2d3, 0x00204411, 0x000 },
-    { 0x00000000, 0x00404808, 0x000 },
-    { 0x0000a2d3, 0x00204411, 0x000 },
-    { 0x00000001, 0x00504a28, 0x000 },
-    { 0x0000a2c3, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204807, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0004a2c2, 0x00604411, 0x614 },
-    { 0x0000001a, 0x00212230, 0x000 },
-    { 0x00000006, 0x00222630, 0x000 },
-    { 0x0000a2c7, 0x00204411, 0x000 },
-    { 0x00000000, 0x003048e9, 0x000 },
-    { 0x00000000, 0x00e00000, 0x599 },
-    { 0x0000a2d4, 0x00204411, 0x000 },
-    { 0x00000000, 0x00404808, 0x000 },
-    { 0x0000a2d4, 0x00204411, 0x000 },
-    { 0x00000001, 0x00504a28, 0x000 },
-    { 0x85000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204801, 0x000 },
-    { 0x0000304a, 0x00204411, 0x000 },
-    { 0x01000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00400000, 0x59f },
-    { 0xa4000000, 0xc0204411, 0x000 },
-    { 0x00000000, 0xc0404800, 0x000 },
-    { 0x00000000, 0xc0600000, 0x5a4 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x0001a2a4, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000005, 0x00204811, 0x000 },
-    { 0x0000a1f4, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x88000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0xff000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00000002, 0x00804811, 0x000 },
-    { 0x00000000, 0x0ee00000, 0x5b7 },
-    { 0x00001000, 0x00200811, 0x000 },
-    { 0x00000034, 0x00203622, 0x000 },
-    { 0x00000000, 0x00600000, 0x5bb },
-    { 0x00000000, 0x00600000, 0x5a4 },
-    { 0x98000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00804811, 0x000 },
-    { 0x00000000, 0xc0600000, 0x5bb },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x0000a2a4, 0x00204411, 0x000 },
-    { 0x00000022, 0x00204811, 0x000 },
-    { 0x89000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0xff000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00000002, 0x00804811, 0x000 },
-    { 0x0000217a, 0xc0204411, 0x000 },
-    { 0x00000000, 0x00404811, 0x000 },
-    { 0x97000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x8a000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0xff000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00000002, 0x00804811, 0x000 },
-    { 0x00000000, 0x00600000, 0x5e1 },
-    { 0x00002010, 0x00204411, 0x000 },
-    { 0x00008000, 0x00204811, 0x000 },
-    { 0x0001a2a4, 0xc0204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000016, 0x00604811, 0x35e },
-    { 0x00000016, 0x00204811, 0x000 },
-    { 0x00002010, 0x00204411, 0x000 },
-    { 0x00010000, 0x00204811, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0000217c, 0x00204411, 0x000 },
-    { 0x09800000, 0x00204811, 0x000 },
-    { 0xffffffff, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x17000000, 0x000 },
-    { 0x0004217f, 0x00604411, 0x614 },
-    { 0x0000001f, 0x00210230, 0x000 },
-    { 0x00000000, 0x14c00000, 0x000 },
-    { 0x00000004, 0x00404c11, 0x5dc },
-    { 0x0000001d, 0x00201e2d, 0x000 },
-    { 0x00000004, 0x00291e27, 0x000 },
-    { 0x0000001d, 0x00803627, 0x000 },
-    { 0x0000001d, 0x00201e2d, 0x000 },
-    { 0xfffffffb, 0x00281e27, 0x000 },
-    { 0x0000001d, 0x00803627, 0x000 },
-    { 0x0000001d, 0x00201e2d, 0x000 },
-    { 0x00000008, 0x00291e27, 0x000 },
-    { 0x0000001d, 0x00803627, 0x000 },
-    { 0x0000001d, 0x00201e2d, 0x000 },
-    { 0xfffffff7, 0x00281e27, 0x000 },
-    { 0x0000001d, 0x00803627, 0x000 },
-    { 0x00002010, 0x00204411, 0x000 },
-    { 0x00008000, 0x00204811, 0x000 },
-    { 0x0001a2a4, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000016, 0x00604811, 0x35e },
-    { 0x00000016, 0x00204811, 0x000 },
-    { 0x00002010, 0x00204411, 0x000 },
-    { 0x00010000, 0x00204811, 0x000 },
-    { 0x0000217c, 0x00204411, 0x000 },
-    { 0x01800000, 0x00204811, 0x000 },
-    { 0x00ffffff, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x17000000, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0004217f, 0x00604411, 0x614 },
-    { 0x00000000, 0x00200010, 0x000 },
-    { 0x00000000, 0x14c00000, 0x613 },
-    { 0x00000010, 0x00404c11, 0x5f9 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x38c00000, 0x000 },
-    { 0x00000025, 0x00200a2d, 0x000 },
-    { 0x00000026, 0x00200e2d, 0x000 },
-    { 0x00000027, 0x0020122d, 0x000 },
-    { 0x00000028, 0x0020162d, 0x000 },
-    { 0x00002169, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204804, 0x000 },
-    { 0x00000000, 0x00204805, 0x000 },
-    { 0x00000000, 0x00204801, 0x000 },
-    { 0xcafebabe, 0x00204811, 0x000 },
-    { 0x00000004, 0x00301224, 0x000 },
-    { 0x00000000, 0x002f0064, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x612 },
-    { 0x00000003, 0x00281a22, 0x000 },
-    { 0x00000008, 0x00221222, 0x000 },
-    { 0xfffff000, 0x00281224, 0x000 },
-    { 0x00000000, 0x002910c4, 0x000 },
-    { 0x00000027, 0x00403624, 0x000 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x00000000, 0x1ac00000, 0x614 },
-    { 0x9f000000, 0x00204411, 0x000 },
-    { 0xcafebabe, 0x00204811, 0x000 },
-    { 0x00000000, 0x1ae00000, 0x617 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00001000, 0x00600411, 0x2fe },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x19f },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001b, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0001a1fd, 0xc0204411, 0x000 },
-    { 0x00000029, 0x00201e2d, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x0000002c, 0x0020222d, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000002a, 0x0020222d, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000002b, 0x00201e2d, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x00404811, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x013304ef, 0x059b0239, 0x000 },
-    { 0x01b00159, 0x0425059b, 0x000 },
-    { 0x021201f6, 0x02390142, 0x000 },
-    { 0x0210022e, 0x0289022a, 0x000 },
-    { 0x03c2059b, 0x059b059b, 0x000 },
-    { 0x05cd05ce, 0x0308059b, 0x000 },
-    { 0x059b05a0, 0x03090329, 0x000 },
-    { 0x0313026b, 0x032b031d, 0x000 },
-    { 0x059b059b, 0x059b059b, 0x000 },
-    { 0x059b052c, 0x059b059b, 0x000 },
-    { 0x03a5059b, 0x04a2032d, 0x000 },
-    { 0x04810433, 0x0423059b, 0x000 },
-    { 0x04bb04ed, 0x042704c8, 0x000 },
-    { 0x043304f4, 0x033a0365, 0x000 },
-    { 0x059b059b, 0x059b059b, 0x000 },
-    { 0x059b059b, 0x059b059b, 0x000 },
-    { 0x059b059b, 0x05b905a2, 0x000 },
-    { 0x059b059b, 0x0007059b, 0x000 },
-    { 0x059b059b, 0x059b059b, 0x000 },
-    { 0x059b059b, 0x059b059b, 0x000 },
-    { 0x03e303d8, 0x03f303f1, 0x000 },
-    { 0x03f903f5, 0x03f703fb, 0x000 },
-    { 0x04070403, 0x040f040b, 0x000 },
-    { 0x04170413, 0x041f041b, 0x000 },
-    { 0x059b059b, 0x059b059b, 0x000 },
-    { 0x059b059b, 0x059b059b, 0x000 },
-    { 0x059b059b, 0x059b059b, 0x000 },
-    { 0x00020600, 0x06190006, 0x000 },
-};
-
-static const u32 R600_pfp_microcode[] = {
-0xd40071,
-0xd40072,
-0xca0400,
-0xa00000,
-0x7e828b,
-0x800003,
-0xca0400,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xc41838,
-0xca2400,
-0xca2800,
-0x9581a8,
-0xc41c3a,
-0xc3c000,
-0xca0800,
-0xca0c00,
-0x7c744b,
-0xc20005,
-0x99c000,
-0xc41c3a,
-0x7c744c,
-0xc0fff0,
-0x042c04,
-0x309002,
-0x7d2500,
-0x351402,
-0x7d350b,
-0x255403,
-0x7cd580,
-0x259c03,
-0x95c004,
-0xd5001b,
-0x7eddc1,
-0x7d9d80,
-0xd6801b,
-0xd5801b,
-0xd4401e,
-0xd5401e,
-0xd6401e,
-0xd6801e,
-0xd4801e,
-0xd4c01e,
-0x9783d4,
-0xd5c01e,
-0xca0800,
-0x80001b,
-0xca0c00,
-0xe4011e,
-0xd4001e,
-0x80000d,
-0xc41838,
-0xe4013e,
-0xd4001e,
-0x80000d,
-0xc41838,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca1800,
-0xd4401e,
-0xd5801e,
-0x800054,
-0xd40073,
-0xd4401e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd48019,
-0xd4c018,
-0xd50017,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xe2001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0xd48060,
-0xd4401e,
-0x800002,
-0xd4801e,
-0xca0800,
-0xd48061,
-0xd4401e,
-0x800002,
-0xd4801e,
-0xca0800,
-0xca0c00,
-0xd4401e,
-0xd48016,
-0xd4c016,
-0xd4801e,
-0x8001b9,
-0xd4c01e,
-0xc6083e,
-0xca0c00,
-0xca1000,
-0x948004,
-0xca1400,
-0xe420f3,
-0xd42013,
-0xd56065,
-0xd4e01c,
-0xd5201c,
-0xd5601c,
-0x800002,
-0x062001,
-0xc6083e,
-0xca0c00,
-0xca1000,
-0x9483f7,
-0xca1400,
-0xe420f3,
-0x80007a,
-0xd42013,
-0xc6083e,
-0xca0c00,
-0xca1000,
-0x9883ef,
-0xca1400,
-0xd40064,
-0x80008e,
-0x000000,
-0xc41432,
-0xc6183e,
-0xc4082f,
-0x954005,
-0xc40c30,
-0xd4401e,
-0x800002,
-0xee001e,
-0x9583f5,
-0xc41031,
-0xd44033,
-0xd52065,
-0xd4a01c,
-0xd4e01c,
-0xd5201c,
-0xd40073,
-0xe4015e,
-0xd4001e,
-0x8001b9,
-0x062001,
-0x0a2001,
-0xd60074,
-0xc40836,
-0xc61040,
-0x988007,
-0xcc3835,
-0x95010f,
-0xd4001f,
-0xd46062,
-0x800002,
-0xd42062,
-0xcc1433,
-0x8401bc,
-0xd40070,
-0xd5401e,
-0x800002,
-0xee001e,
-0xca0c00,
-0xca1000,
-0xd4c01a,
-0x8401bc,
-0xd5001a,
-0xcc0443,
-0x35101f,
-0x2c9401,
-0x7d098b,
-0x984005,
-0x7d15cb,
-0xd4001a,
-0x8001b9,
-0xd4006d,
-0x344401,
-0xcc0c44,
-0x98403a,
-0xcc2c46,
-0x958004,
-0xcc0445,
-0x8001b9,
-0xd4001a,
-0xd4c01a,
-0x282801,
-0x8400f3,
-0xcc1003,
-0x98801b,
-0x04380c,
-0x8400f3,
-0xcc1003,
-0x988017,
-0x043808,
-0x8400f3,
-0xcc1003,
-0x988013,
-0x043804,
-0x8400f3,
-0xcc1003,
-0x988014,
-0xcc1047,
-0x9a8009,
-0xcc1448,
-0x9840da,
-0xd4006d,
-0xcc1844,
-0xd5001a,
-0xd5401a,
-0x8000cc,
-0xd5801a,
-0x96c0d3,
-0xd4006d,
-0x8001b9,
-0xd4006e,
-0x9ac003,
-0xd4006d,
-0xd4006e,
-0x800002,
-0xec007f,
-0x9ac0ca,
-0xd4006d,
-0x8001b9,
-0xd4006e,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0x7d9103,
-0x7dd583,
-0x7d190c,
-0x35cc1f,
-0x35701f,
-0x7cf0cb,
-0x7cd08b,
-0x880000,
-0x7e8e8b,
-0x95c004,
-0xd4006e,
-0x8001b9,
-0xd4001a,
-0xd4c01a,
-0xcc0803,
-0xcc0c03,
-0xcc1003,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0xcc2403,
-0xcc2803,
-0x35c41f,
-0x36b01f,
-0x7c704b,
-0x34f01f,
-0x7c704b,
-0x35701f,
-0x7c704b,
-0x7d8881,
-0x7dccc1,
-0x7e5101,
-0x7e9541,
-0x7c9082,
-0x7cd4c2,
-0x7c848b,
-0x9ac003,
-0x7c8c8b,
-0x2c8801,
-0x98809c,
-0xd4006d,
-0x98409a,
-0xd4006e,
-0xcc0847,
-0xcc0c48,
-0xcc1044,
-0xd4801a,
-0xd4c01a,
-0x800104,
-0xd5001a,
-0xcc0832,
-0xd40032,
-0x9482d8,
-0xca0c00,
-0xd4401e,
-0x800002,
-0xd4001e,
-0xe4011e,
-0xd4001e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd4401e,
-0xca1400,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xd5401e,
-0xd54034,
-0x800002,
-0xee001e,
-0x280404,
-0xe2001a,
-0xe2001a,
-0xd4401a,
-0xca3800,
-0xcc0803,
-0xcc0c03,
-0xcc0c03,
-0xcc0c03,
-0x9882bc,
-0x000000,
-0x8401bc,
-0xd7806f,
-0x800002,
-0xee001f,
-0xca0400,
-0xc2ff00,
-0xcc0834,
-0xc13fff,
-0x7c74cb,
-0x7cc90b,
-0x7d010f,
-0x9902af,
-0x7c738b,
-0x8401bc,
-0xd7806f,
-0x800002,
-0xee001f,
-0xca0800,
-0x281900,
-0x7d898b,
-0x958014,
-0x281404,
-0xca0c00,
-0xca1000,
-0xca1c00,
-0xca2400,
-0xe2001f,
-0xd4c01a,
-0xd5001a,
-0xd5401a,
-0xcc1803,
-0xcc2c03,
-0xcc2c03,
-0xcc2c03,
-0x7da58b,
-0x7d9c47,
-0x984296,
-0x000000,
-0x800164,
-0xd4c01a,
-0xd4401e,
-0xd4801e,
-0x800002,
-0xee001e,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0x248c06,
-0x0ccc06,
-0x98c006,
-0xcc1049,
-0x990004,
-0xd40071,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xd4801e,
-0x800002,
-0xee001e,
-0xca0800,
-0xca0c00,
-0x34d018,
-0x251001,
-0x95001f,
-0xc17fff,
-0xca1000,
-0xca1400,
-0xca1800,
-0xd4801d,
-0xd4c01d,
-0x7db18b,
-0xc14202,
-0xc2c001,
-0xd5801d,
-0x34dc0e,
-0x7d5d4c,
-0x7f734c,
-0xd7401e,
-0xd5001e,
-0xd5401e,
-0xc14200,
-0xc2c000,
-0x099c01,
-0x31dc10,
-0x7f5f4c,
-0x7f734c,
-0x7d8380,
-0xd5806f,
-0xd58066,
-0xd7401e,
-0xec005e,
-0xc82402,
-0x8001b9,
-0xd60074,
-0xd4401e,
-0xd4801e,
-0xd4c01e,
-0x800002,
-0xee001e,
-0x800002,
-0xee001f,
-0xd4001f,
-0x800002,
-0xd4001f,
-0xd4001f,
-0x880000,
-0xd4001f,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x010174,
-0x02017b,
-0x030090,
-0x040080,
-0x050005,
-0x060040,
-0x070033,
-0x08012f,
-0x090047,
-0x0a0037,
-0x1001b7,
-0x1700a4,
-0x22013d,
-0x23014c,
-0x2000b5,
-0x240128,
-0x27004e,
-0x28006b,
-0x2a0061,
-0x2b0053,
-0x2f0066,
-0x320088,
-0x340182,
-0x3c0159,
-0x3f0073,
-0x41018f,
-0x440131,
-0x550176,
-0x56017d,
-0x60000c,
-0x610035,
-0x620039,
-0x630039,
-0x640039,
-0x650039,
-0x660039,
-0x670039,
-0x68003b,
-0x690042,
-0x6a0049,
-0x6b0049,
-0x6c0049,
-0x6d0049,
-0x6e0049,
-0x6f0049,
-0x7301b7,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-0x000007,
-};
-
-static const u32 RV610_cp_microcode[][3] = {
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x0000ffff, 0x00284621, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x00000000, 0x00e00000, 0x000 },
-    { 0x00010000, 0xc0294620, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00042004, 0x00604411, 0x68d },
-    { 0x00000000, 0x00600000, 0x631 },
-    { 0x00000000, 0x00600000, 0x645 },
-    { 0x00000000, 0xc0200800, 0x000 },
-    { 0x00000f00, 0x00281622, 0x000 },
-    { 0x00000008, 0x00211625, 0x000 },
-    { 0x00000018, 0x00203625, 0x000 },
-    { 0x8d000000, 0x00204411, 0x000 },
-    { 0x00000004, 0x002f0225, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x018 },
-    { 0x00412000, 0x00404811, 0x019 },
-    { 0x00422000, 0x00204811, 0x000 },
-    { 0x8e000000, 0x00204411, 0x000 },
-    { 0x00000028, 0x00204a2d, 0x000 },
-    { 0x90000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204805, 0x000 },
-    { 0x0000000c, 0x00211622, 0x000 },
-    { 0x00000003, 0x00281625, 0x000 },
-    { 0x00000019, 0x00211a22, 0x000 },
-    { 0x00000004, 0x00281a26, 0x000 },
-    { 0x00000000, 0x002914c5, 0x000 },
-    { 0x00000019, 0x00203625, 0x000 },
-    { 0x00000000, 0x003a1402, 0x000 },
-    { 0x00000016, 0x00211625, 0x000 },
-    { 0x00000003, 0x00281625, 0x000 },
-    { 0x00000017, 0x00200e2d, 0x000 },
-    { 0xfffffffc, 0x00280e23, 0x000 },
-    { 0x00000000, 0x002914a3, 0x000 },
-    { 0x00000017, 0x00203625, 0x000 },
-    { 0x00008000, 0x00280e22, 0x000 },
-    { 0x00000007, 0x00220e23, 0x000 },
-    { 0x00000000, 0x0029386e, 0x000 },
-    { 0x20000000, 0x00280e22, 0x000 },
-    { 0x00000006, 0x00210e23, 0x000 },
-    { 0x00000000, 0x0029386e, 0x000 },
-    { 0x00000000, 0x00220222, 0x000 },
-    { 0x00000000, 0x14e00000, 0x038 },
-    { 0x00000000, 0x2ee00000, 0x035 },
-    { 0x00000000, 0x2ce00000, 0x037 },
-    { 0x00000000, 0x00400e2d, 0x039 },
-    { 0x00000008, 0x00200e2d, 0x000 },
-    { 0x00000009, 0x0040122d, 0x046 },
-    { 0x00000001, 0x00400e2d, 0x039 },
-    { 0x00000000, 0xc0200c00, 0x000 },
-    { 0x003ffffc, 0x00281223, 0x000 },
-    { 0x00000002, 0x00221224, 0x000 },
-    { 0x0000001f, 0x00211e23, 0x000 },
-    { 0x00000000, 0x14e00000, 0x03e },
-    { 0x00000008, 0x00401c11, 0x041 },
-    { 0x0000000d, 0x00201e2d, 0x000 },
-    { 0x0000000f, 0x00281e27, 0x000 },
-    { 0x00000003, 0x00221e27, 0x000 },
-    { 0x7fc00000, 0x00281a23, 0x000 },
-    { 0x00000014, 0x00211a26, 0x000 },
-    { 0x00000001, 0x00331a26, 0x000 },
-    { 0x00000008, 0x00221a26, 0x000 },
-    { 0x00000000, 0x00290cc7, 0x000 },
-    { 0x00000027, 0x00203624, 0x000 },
-    { 0x00007f00, 0x00281221, 0x000 },
-    { 0x00001400, 0x002f0224, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x04b },
-    { 0x00000001, 0x00290e23, 0x000 },
-    { 0x0000000e, 0x00203623, 0x000 },
-    { 0x0000e000, 0x00204411, 0x000 },
-    { 0xfff80000, 0x00294a23, 0x000 },
-    { 0x00000000, 0x003a2c02, 0x000 },
-    { 0x00000002, 0x00220e2b, 0x000 },
-    { 0xfc000000, 0x00280e23, 0x000 },
-    { 0x0000000f, 0x00203623, 0x000 },
-    { 0x00001fff, 0x00294a23, 0x000 },
-    { 0x00000027, 0x00204a2d, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000029, 0x00200e2d, 0x000 },
-    { 0x060a0200, 0x00294a23, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000001, 0x00210222, 0x000 },
-    { 0x00000000, 0x14e00000, 0x061 },
-    { 0x00000000, 0x2ee00000, 0x05f },
-    { 0x00000000, 0x2ce00000, 0x05e },
-    { 0x00000000, 0x00400e2d, 0x062 },
-    { 0x00000001, 0x00400e2d, 0x062 },
-    { 0x0000000a, 0x00200e2d, 0x000 },
-    { 0x0000000b, 0x0040122d, 0x06a },
-    { 0x00000000, 0xc0200c00, 0x000 },
-    { 0x003ffffc, 0x00281223, 0x000 },
-    { 0x00000002, 0x00221224, 0x000 },
-    { 0x7fc00000, 0x00281623, 0x000 },
-    { 0x00000014, 0x00211625, 0x000 },
-    { 0x00000001, 0x00331625, 0x000 },
-    { 0x80000000, 0x00280e23, 0x000 },
-    { 0x00000000, 0x00290ca3, 0x000 },
-    { 0x3ffffc00, 0x00290e23, 0x000 },
-    { 0x0000001f, 0x00211e23, 0x000 },
-    { 0x00000000, 0x14e00000, 0x06d },
-    { 0x00000100, 0x00401c11, 0x070 },
-    { 0x0000000d, 0x00201e2d, 0x000 },
-    { 0x000000f0, 0x00281e27, 0x000 },
-    { 0x00000004, 0x00221e27, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000d, 0x00204811, 0x000 },
-    { 0xfffff0ff, 0x00281a30, 0x000 },
-    { 0x0000a028, 0x00204411, 0x000 },
-    { 0x00000000, 0x002948e6, 0x000 },
-    { 0x0000a018, 0x00204411, 0x000 },
-    { 0x3fffffff, 0x00284a23, 0x000 },
-    { 0x0000a010, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204804, 0x000 },
-    { 0x00000030, 0x0020162d, 0x000 },
-    { 0x00000002, 0x00291625, 0x000 },
-    { 0x00000030, 0x00203625, 0x000 },
-    { 0x00000025, 0x0020162d, 0x000 },
-    { 0x00000000, 0x002f00a3, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x083 },
-    { 0x00000026, 0x0020162d, 0x000 },
-    { 0x00000000, 0x002f00a4, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x084 },
-    { 0x00000000, 0x00400000, 0x08a },
-    { 0x00000025, 0x00203623, 0x000 },
-    { 0x00000026, 0x00203624, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000002, 0x00210227, 0x000 },
-    { 0x00000000, 0x14e00000, 0x08a },
-    { 0x00000000, 0x00600000, 0x668 },
-    { 0x00000000, 0x00600000, 0x65c },
-    { 0x00000002, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x08d },
-    { 0x00000012, 0xc0403620, 0x093 },
-    { 0x00000000, 0x2ee00000, 0x091 },
-    { 0x00000000, 0x2ce00000, 0x090 },
-    { 0x00000002, 0x00400e2d, 0x092 },
-    { 0x00000003, 0x00400e2d, 0x092 },
-    { 0x0000000c, 0x00200e2d, 0x000 },
-    { 0x00000012, 0x00203623, 0x000 },
-    { 0x00000003, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x098 },
-    { 0x0000a00c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0404800, 0x0a0 },
-    { 0x0000a00c, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x2ee00000, 0x09e },
-    { 0x00000000, 0x2ce00000, 0x09d },
-    { 0x00000002, 0x00400e2d, 0x09f },
-    { 0x00000003, 0x00400e2d, 0x09f },
-    { 0x0000000c, 0x00200e2d, 0x000 },
-    { 0x00000000, 0x00204803, 0x000 },
-    { 0x00000000, 0x003a0c02, 0x000 },
-    { 0x003f0000, 0x00280e23, 0x000 },
-    { 0x00000010, 0x00210e23, 0x000 },
-    { 0x00000011, 0x00203623, 0x000 },
-    { 0x0000001e, 0x0021022b, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0a7 },
-    { 0x00000016, 0xc0203620, 0x000 },
-    { 0x0000001f, 0x0021022b, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0aa },
-    { 0x00000015, 0xc0203620, 0x000 },
-    { 0x00000008, 0x00210e2b, 0x000 },
-    { 0x0000007f, 0x00280e23, 0x000 },
-    { 0x00000000, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0e1 },
-    { 0x00000000, 0x27000000, 0x000 },
-    { 0x00000000, 0x00600000, 0x2a3 },
-    { 0x00000001, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ae00000, 0x0b3 },
-    { 0x00000000, 0x00600000, 0x13a },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000006, 0x00204811, 0x000 },
-    { 0x0000000c, 0x00221e30, 0x000 },
-    { 0x99800000, 0x00204411, 0x000 },
-    { 0x00000004, 0x0020122d, 0x000 },
-    { 0x00000008, 0x00221224, 0x000 },
-    { 0x00000010, 0x00201811, 0x000 },
-    { 0x00000000, 0x00291ce4, 0x000 },
-    { 0x00000000, 0x00604807, 0x12f },
-    { 0x9b000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204802, 0x000 },
-    { 0x9c000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x0033146f, 0x000 },
-    { 0x00000001, 0x00333e23, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0x00203c05, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000e, 0x00204811, 0x000 },
-    { 0x00000000, 0x00201010, 0x000 },
-    { 0x0000e007, 0x00204411, 0x000 },
-    { 0x0000000f, 0x0021022b, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0cb },
-    { 0x00f8ff08, 0x00204811, 0x000 },
-    { 0x98000000, 0x00404811, 0x0dc },
-    { 0x000000f0, 0x00280e22, 0x000 },
-    { 0x000000a0, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x0da },
-    { 0x00000011, 0x00200e2d, 0x000 },
-    { 0x00000001, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0d5 },
-    { 0x00000002, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0d4 },
-    { 0x00003f00, 0x00400c11, 0x0d6 },
-    { 0x00001f00, 0x00400c11, 0x0d6 },
-    { 0x00000f00, 0x00200c11, 0x000 },
-    { 0x00380009, 0x00294a23, 0x000 },
-    { 0x3f000000, 0x00280e2b, 0x000 },
-    { 0x00000002, 0x00220e23, 0x000 },
-    { 0x00000007, 0x00494a23, 0x0dc },
-    { 0x00380f09, 0x00204811, 0x000 },
-    { 0x68000007, 0x00204811, 0x000 },
-    { 0x00000008, 0x00214a27, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x060a0200, 0x00294a24, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000a202, 0x00204411, 0x000 },
-    { 0x00ff0000, 0x00280e22, 0x000 },
-    { 0x00000080, 0x00294a23, 0x000 },
-    { 0x00000027, 0x00200e2d, 0x000 },
-    { 0x00000026, 0x0020122d, 0x000 },
-    { 0x00000000, 0x002f0083, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0ea },
-    { 0x00000000, 0x00600000, 0x662 },
-    { 0x00000000, 0x00400000, 0x0eb },
-    { 0x00000000, 0x00600000, 0x665 },
-    { 0x00000007, 0x0020222d, 0x000 },
-    { 0x00000005, 0x00220e22, 0x000 },
-    { 0x00100000, 0x00280e23, 0x000 },
-    { 0x00000000, 0x00292068, 0x000 },
-    { 0x00000000, 0x003a0c02, 0x000 },
-    { 0x000000ef, 0x00280e23, 0x000 },
-    { 0x00000000, 0x00292068, 0x000 },
-    { 0x00000017, 0x00200e2d, 0x000 },
-    { 0x00000003, 0x00210223, 0x000 },
-    { 0x00000000, 0x14e00000, 0x0f8 },
-    { 0x0000000b, 0x00210228, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0f8 },
-    { 0x00000400, 0x00292228, 0x000 },
-    { 0x00000014, 0x00203628, 0x000 },
-    { 0x0000001c, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0fd },
-    { 0x0000a30c, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000001e, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x10b },
-    { 0x0000a30f, 0x00204411, 0x000 },
-    { 0x00000011, 0x00200e2d, 0x000 },
-    { 0x00000001, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x104 },
-    { 0xffffffff, 0x00404811, 0x10b },
-    { 0x00000002, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x107 },
-    { 0x0000ffff, 0x00404811, 0x10b },
-    { 0x00000004, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x10a },
-    { 0x000000ff, 0x00404811, 0x10b },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0002c400, 0x00204411, 0x000 },
-    { 0x0000001f, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x112 },
-    { 0x00000010, 0x40210e20, 0x000 },
-    { 0x00000013, 0x00203623, 0x000 },
-    { 0x00000018, 0x40224a20, 0x000 },
-    { 0x00000010, 0xc0424a20, 0x114 },
-    { 0x00000000, 0x00200c11, 0x000 },
-    { 0x00000013, 0x00203623, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000000a, 0x00201011, 0x000 },
-    { 0x00000000, 0x002f0224, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x11b },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000001, 0x00531224, 0x117 },
-    { 0xffbfffff, 0x00283a2e, 0x000 },
-    { 0x0000001b, 0x00210222, 0x000 },
-    { 0x00000000, 0x14c00000, 0x12e },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000d, 0x00204811, 0x000 },
-    { 0x00000018, 0x00220e30, 0x000 },
-    { 0xfc000000, 0x00280e23, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000e, 0x00204811, 0x000 },
-    { 0x00000000, 0x00201010, 0x000 },
-    { 0x0000e00e, 0x00204411, 0x000 },
-    { 0x07f8ff08, 0x00204811, 0x000 },
-    { 0x00000000, 0x00294a23, 0x000 },
-    { 0x0000001c, 0x00201e2d, 0x000 },
-    { 0x00000008, 0x00214a27, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x060a0200, 0x00294a24, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0000217c, 0x00204411, 0x000 },
-    { 0x00800000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204806, 0x000 },
-    { 0x00000008, 0x00214a27, 0x000 },
-    { 0x00000000, 0x17000000, 0x000 },
-    { 0x0004217f, 0x00604411, 0x68d },
-    { 0x0000001f, 0x00210230, 0x000 },
-    { 0x00000000, 0x14c00000, 0x68c },
-    { 0x00000004, 0x00404c11, 0x135 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x000021f8, 0x00204411, 0x000 },
-    { 0x0000001c, 0x00204811, 0x000 },
-    { 0x000421f9, 0x00604411, 0x68d },
-    { 0x00000011, 0x00210230, 0x000 },
-    { 0x00000000, 0x14e00000, 0x13c },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x00000000, 0x00600000, 0x160 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x00000010, 0xc0211220, 0x000 },
-    { 0x0000ffff, 0x40280620, 0x000 },
-    { 0x00000010, 0xc0210a20, 0x000 },
-    { 0x00000000, 0x00341461, 0x000 },
-    { 0x00000000, 0x00741882, 0x2bb },
-    { 0x0001a1fd, 0x00604411, 0x2e0 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x147 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00600000, 0x160 },
-    { 0x00000010, 0x40210e20, 0x000 },
-    { 0x0000ffff, 0xc0281220, 0x000 },
-    { 0x00000010, 0x40211620, 0x000 },
-    { 0x0000ffff, 0xc0681a20, 0x2bb },
-    { 0x0001a1fd, 0x00604411, 0x2e0 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x158 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000001, 0x00300a2f, 0x000 },
-    { 0x00000001, 0x00210a22, 0x000 },
-    { 0x00000003, 0x00384a22, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001a, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00804811, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600000, 0x18f },
-    { 0x00000000, 0x00600000, 0x1a0 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00202c08, 0x000 },
-    { 0x00000000, 0x00202411, 0x000 },
-    { 0x00000000, 0x00202811, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x00000016, 0x00204811, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x93800000, 0x00204411, 0x000 },
-    { 0x00000002, 0x00221e29, 0x000 },
-    { 0x00000000, 0x007048eb, 0x19c },
-    { 0x00000000, 0x00600000, 0x2bb },
-    { 0x00000001, 0x40330620, 0x000 },
-    { 0x00000000, 0xc0302409, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00600000, 0x2a3 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ae00000, 0x181 },
-    { 0x00000000, 0x00600000, 0x13a },
-    { 0x00000000, 0x00400000, 0x186 },
-    { 0x95000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x186 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000001, 0x00530621, 0x182 },
-    { 0x92000000, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0604800, 0x197 },
-    { 0x0001a1fd, 0x00204411, 0x000 },
-    { 0x00000011, 0x0020062d, 0x000 },
-    { 0x00000000, 0x0078042a, 0x2fb },
-    { 0x00000000, 0x00202809, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x174 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000210, 0x00600411, 0x315 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x194 },
-    { 0x00000015, 0xc0203620, 0x000 },
-    { 0x00000016, 0xc0203620, 0x000 },
-    { 0x3f800000, 0x00200411, 0x000 },
-    { 0x46000000, 0x00600811, 0x1b2 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x19b },
-    { 0x00000001, 0x00804811, 0x000 },
-    { 0x00000021, 0x00804811, 0x000 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x00000010, 0xc0211220, 0x000 },
-    { 0x0000ffff, 0x40281620, 0x000 },
-    { 0x00000010, 0xc0811a20, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000006, 0x00204811, 0x000 },
-    { 0x00000008, 0x00221e30, 0x000 },
-    { 0x00000029, 0x00201a2d, 0x000 },
-    { 0x0000e000, 0x00204411, 0x000 },
-    { 0xfffbff09, 0x00204811, 0x000 },
-    { 0x0000000f, 0x0020222d, 0x000 },
-    { 0x00001fff, 0x00294a28, 0x000 },
-    { 0x00000006, 0x0020222d, 0x000 },
-    { 0x00000000, 0x002920e8, 0x000 },
-    { 0x00000000, 0x00204808, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x060a0200, 0x00294a26, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000100, 0x00201811, 0x000 },
-    { 0x00000008, 0x00621e28, 0x12f },
-    { 0x00000008, 0x00822228, 0x000 },
-    { 0x0002c000, 0x00204411, 0x000 },
-    { 0x00000015, 0x00600e2d, 0x1bd },
-    { 0x00000016, 0x00600e2d, 0x1bd },
-    { 0x0000c008, 0x00204411, 0x000 },
-    { 0x00000017, 0x00200e2d, 0x000 },
-    { 0x00000000, 0x14c00000, 0x1b9 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00204801, 0x000 },
-    { 0x39000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00804802, 0x000 },
-    { 0x00000018, 0x00202e2d, 0x000 },
-    { 0x00000000, 0x003b0d63, 0x000 },
-    { 0x00000008, 0x00224a23, 0x000 },
-    { 0x00000010, 0x00224a23, 0x000 },
-    { 0x00000018, 0x00224a23, 0x000 },
-    { 0x00000000, 0x00804803, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00001000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x00000007, 0x0021062f, 0x000 },
-    { 0x00000013, 0x00200a2d, 0x000 },
-    { 0x00000001, 0x00202c11, 0x000 },
-    { 0x0000ffff, 0x40282220, 0x000 },
-    { 0x0000000f, 0x00262228, 0x000 },
-    { 0x00000010, 0x40212620, 0x000 },
-    { 0x0000000f, 0x00262629, 0x000 },
-    { 0x00000000, 0x00202802, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001b, 0x00204811, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x1e0 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000081, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00000080, 0x00201c11, 0x000 },
-    { 0x00000000, 0x002f0227, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x1dc },
-    { 0x00000000, 0x00600000, 0x1e9 },
-    { 0x00000001, 0x00531e27, 0x1d8 },
-    { 0x00000001, 0x00202c11, 0x000 },
-    { 0x0000001f, 0x00280a22, 0x000 },
-    { 0x0000001f, 0x00282a2a, 0x000 },
-    { 0x00000001, 0x00530621, 0x1d1 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000002, 0x00304a2f, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00000001, 0x00301e2f, 0x000 },
-    { 0x00000000, 0x002f0227, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00600000, 0x1e9 },
-    { 0x00000001, 0x00531e27, 0x1e5 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x0000000f, 0x00260e23, 0x000 },
-    { 0x00000010, 0xc0211220, 0x000 },
-    { 0x0000000f, 0x00261224, 0x000 },
-    { 0x00000000, 0x00201411, 0x000 },
-    { 0x00000000, 0x00601811, 0x2bb },
-    { 0x0001a1fd, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f022b, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x1f8 },
-    { 0x00000010, 0x00221628, 0x000 },
-    { 0xffff0000, 0x00281625, 0x000 },
-    { 0x0000ffff, 0x00281a29, 0x000 },
-    { 0x00000000, 0x002948c5, 0x000 },
-    { 0x00000000, 0x0020480a, 0x000 },
-    { 0x00000000, 0x00202c11, 0x000 },
-    { 0x00000010, 0x00221623, 0x000 },
-    { 0xffff0000, 0x00281625, 0x000 },
-    { 0x0000ffff, 0x00281a24, 0x000 },
-    { 0x00000000, 0x002948c5, 0x000 },
-    { 0x00000000, 0x00731503, 0x205 },
-    { 0x00000000, 0x00201805, 0x000 },
-    { 0x00000000, 0x00731524, 0x205 },
-    { 0x00000000, 0x002d14c5, 0x000 },
-    { 0x00000000, 0x003008a2, 0x000 },
-    { 0x00000000, 0x00204802, 0x000 },
-    { 0x00000000, 0x00202802, 0x000 },
-    { 0x00000000, 0x00202003, 0x000 },
-    { 0x00000000, 0x00802404, 0x000 },
-    { 0x0000000f, 0x00210225, 0x000 },
-    { 0x00000000, 0x14c00000, 0x68c },
-    { 0x00000000, 0x002b1405, 0x000 },
-    { 0x00000001, 0x00901625, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001a, 0x00294a22, 0x000 },
-    { 0x00000000, 0xc0200000, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00384a21, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0000ffff, 0x40281220, 0x000 },
-    { 0x00000010, 0xc0211a20, 0x000 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x00000010, 0xc0211620, 0x000 },
-    { 0x00000000, 0x00741465, 0x2bb },
-    { 0x0001a1fd, 0x00604411, 0x2e0 },
-    { 0x00000001, 0x00330621, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x219 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x212 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000000, 0x00600000, 0x645 },
-    { 0x00000000, 0x0040040f, 0x213 },
-    { 0x00000000, 0x00600000, 0x631 },
-    { 0x00000000, 0x00600000, 0x645 },
-    { 0x00000210, 0x00600411, 0x315 },
-    { 0x00000000, 0x00600000, 0x1a0 },
-    { 0x00000000, 0x00600000, 0x19c },
-    { 0x00000000, 0x00600000, 0x2bb },
-    { 0x00000000, 0x00600000, 0x2a3 },
-    { 0x93800000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204808, 0x000 },
-    { 0x00000000, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ae00000, 0x232 },
-    { 0x00000000, 0x00600000, 0x13a },
-    { 0x00000000, 0x00400000, 0x236 },
-    { 0x95000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x236 },
-    { 0x00000000, 0xc0404800, 0x233 },
-    { 0x92000000, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x00000016, 0x00204811, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0001a1fd, 0x00204411, 0x000 },
-    { 0x00000000, 0x00600411, 0x2fb },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000000, 0x00600000, 0x631 },
-    { 0x0000a00c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0404800, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000018, 0x40210a20, 0x000 },
-    { 0x00000003, 0x002f0222, 0x000 },
-    { 0x00000000, 0x0ae00000, 0x24c },
-    { 0x00000014, 0x0020222d, 0x000 },
-    { 0x00080101, 0x00292228, 0x000 },
-    { 0x00000014, 0x00203628, 0x000 },
-    { 0x0000a30c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0404800, 0x251 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000010, 0x00600411, 0x315 },
-    { 0x3f800000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x00000000, 0x00600000, 0x27c },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000001, 0x00211e27, 0x000 },
-    { 0x00000000, 0x14e00000, 0x26a },
-    { 0x00000012, 0x00201e2d, 0x000 },
-    { 0x0000ffff, 0x00281e27, 0x000 },
-    { 0x00000000, 0x00341c27, 0x000 },
-    { 0x00000000, 0x12c00000, 0x25f },
-    { 0x00000000, 0x00201c11, 0x000 },
-    { 0x00000000, 0x002f00e5, 0x000 },
-    { 0x00000000, 0x08c00000, 0x262 },
-    { 0x00000000, 0x00201407, 0x000 },
-    { 0x00000012, 0x00201e2d, 0x000 },
-    { 0x00000010, 0x00211e27, 0x000 },
-    { 0x00000000, 0x00341c47, 0x000 },
-    { 0x00000000, 0x12c00000, 0x267 },
-    { 0x00000000, 0x00201c11, 0x000 },
-    { 0x00000000, 0x002f00e6, 0x000 },
-    { 0x00000000, 0x08c00000, 0x26a },
-    { 0x00000000, 0x00201807, 0x000 },
-    { 0x00000000, 0x00600000, 0x2c1 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x00000000, 0x00342023, 0x000 },
-    { 0x00000000, 0x12c00000, 0x272 },
-    { 0x00000000, 0x00342044, 0x000 },
-    { 0x00000000, 0x12c00000, 0x271 },
-    { 0x00000016, 0x00404811, 0x276 },
-    { 0x00000018, 0x00404811, 0x276 },
-    { 0x00000000, 0x00342044, 0x000 },
-    { 0x00000000, 0x12c00000, 0x275 },
-    { 0x00000017, 0x00404811, 0x276 },
-    { 0x00000019, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0001a1fd, 0x00604411, 0x2e9 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x256 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000010, 0x40210620, 0x000 },
-    { 0x0000ffff, 0xc0280a20, 0x000 },
-    { 0x00000010, 0x40210e20, 0x000 },
-    { 0x0000ffff, 0xc0281220, 0x000 },
-    { 0x00000010, 0x40211620, 0x000 },
-    { 0x0000ffff, 0xc0881a20, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00042004, 0x00604411, 0x68d },
-    { 0x00000000, 0x00600000, 0x631 },
-    { 0x00000000, 0xc0600000, 0x2a3 },
-    { 0x00000005, 0x00200a2d, 0x000 },
-    { 0x00000008, 0x00220a22, 0x000 },
-    { 0x0000002b, 0x00201a2d, 0x000 },
-    { 0x0000001c, 0x00201e2d, 0x000 },
-    { 0x00007000, 0x00281e27, 0x000 },
-    { 0x00000000, 0x00311ce6, 0x000 },
-    { 0x0000002a, 0x00201a2d, 0x000 },
-    { 0x0000000c, 0x00221a26, 0x000 },
-    { 0x00000000, 0x002f00e6, 0x000 },
-    { 0x00000000, 0x06e00000, 0x292 },
-    { 0x00000000, 0x00201c11, 0x000 },
-    { 0x00000000, 0x00200c11, 0x000 },
-    { 0x0000002b, 0x00203623, 0x000 },
-    { 0x00000010, 0x00201811, 0x000 },
-    { 0x00000000, 0x00691ce2, 0x12f },
-    { 0x93800000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204807, 0x000 },
-    { 0x95000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x29d },
-    { 0x00000001, 0x00333e2f, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x92000000, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x0000001c, 0x00403627, 0x000 },
-    { 0x0000000c, 0xc0220a20, 0x000 },
-    { 0x00000029, 0x00203622, 0x000 },
-    { 0x00000028, 0xc0403620, 0x000 },
-    { 0x0000a2a4, 0x00204411, 0x000 },
-    { 0x00000009, 0x00204811, 0x000 },
-    { 0xa1000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00804811, 0x000 },
-    { 0x00000021, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x002c1ce3, 0x000 },
-    { 0x00000021, 0x00203627, 0x000 },
-    { 0x00000022, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x002c1ce4, 0x000 },
-    { 0x00000022, 0x00203627, 0x000 },
-    { 0x00000023, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x003120a3, 0x000 },
-    { 0x00000000, 0x002d1d07, 0x000 },
-    { 0x00000023, 0x00203627, 0x000 },
-    { 0x00000024, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x003120c4, 0x000 },
-    { 0x00000000, 0x002d1d07, 0x000 },
-    { 0x00000024, 0x00803627, 0x000 },
-    { 0x00000021, 0x00203623, 0x000 },
-    { 0x00000022, 0x00203624, 0x000 },
-    { 0x00000000, 0x00311ca3, 0x000 },
-    { 0x00000023, 0x00203627, 0x000 },
-    { 0x00000000, 0x00311cc4, 0x000 },
-    { 0x00000024, 0x00803627, 0x000 },
-    { 0x0000001a, 0x00203627, 0x000 },
-    { 0x0000001b, 0x00203628, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000002, 0x00210227, 0x000 },
-    { 0x00000000, 0x14c00000, 0x2dc },
-    { 0x00000000, 0x00400000, 0x2d9 },
-    { 0x0000001a, 0x00203627, 0x000 },
-    { 0x0000001b, 0x00203628, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000002, 0x00210227, 0x000 },
-    { 0x00000000, 0x14e00000, 0x2d9 },
-    { 0x00000003, 0x00210227, 0x000 },
-    { 0x00000000, 0x14e00000, 0x2dc },
-    { 0x00000023, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x002e00e1, 0x000 },
-    { 0x00000000, 0x02c00000, 0x2dc },
-    { 0x00000021, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x003120a1, 0x000 },
-    { 0x00000000, 0x002e00e8, 0x000 },
-    { 0x00000000, 0x06c00000, 0x2dc },
-    { 0x00000024, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x002e00e2, 0x000 },
-    { 0x00000000, 0x02c00000, 0x2dc },
-    { 0x00000022, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x003120c2, 0x000 },
-    { 0x00000000, 0x002e00e8, 0x000 },
-    { 0x00000000, 0x06c00000, 0x2dc },
-    { 0x00000000, 0x00600000, 0x668 },
-    { 0x00000000, 0x00600000, 0x2b5 },
-    { 0x00000000, 0x00400000, 0x2de },
-    { 0x00000000, 0x00600000, 0x2b5 },
-    { 0x00000000, 0x00600000, 0x65f },
-    { 0x00000000, 0x00400000, 0x2de },
-    { 0x00000000, 0x00600000, 0x2a7 },
-    { 0x00000000, 0x00400000, 0x2de },
-    { 0x0000001a, 0x00201e2d, 0x000 },
-    { 0x0000001b, 0x0080222d, 0x000 },
-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000000, 0x00311ca3, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x003120c4, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00894907, 0x000 },
-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000010, 0x00221e21, 0x000 },
-    { 0x00000000, 0x00294847, 0x000 },
-    { 0x00000000, 0x00311ca3, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000000, 0x00311ca1, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294847, 0x000 },
-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x003120c4, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000010, 0x00221e21, 0x000 },
-    { 0x00000000, 0x003120c2, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00894907, 0x000 },
-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000001, 0x00220a21, 0x000 },
-    { 0x00000000, 0x003308a2, 0x000 },
-    { 0x00000010, 0x00221e22, 0x000 },
-    { 0x00000010, 0x00212222, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x00311ca3, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000001, 0x00220a21, 0x000 },
-    { 0x00000000, 0x003008a2, 0x000 },
-    { 0x00000010, 0x00221e22, 0x000 },
-    { 0x00000010, 0x00212222, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x003120c4, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x003808c5, 0x000 },
-    { 0x00000000, 0x00300841, 0x000 },
-    { 0x00000001, 0x00220a22, 0x000 },
-    { 0x00000000, 0x003308a2, 0x000 },
-    { 0x00000010, 0x00221e22, 0x000 },
-    { 0x00000010, 0x00212222, 0x000 },
-    { 0x00000000, 0x00894907, 0x000 },
-    { 0x00000017, 0x0020222d, 0x000 },
-    { 0x00000000, 0x14c00000, 0x318 },
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-    { 0x00000000, 0x14c00000, 0x4ac },
-    { 0xa0000000, 0x00204411, 0x000 },
-    { 0xcafebabe, 0x00404811, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000004, 0x00204811, 0x000 },
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-    { 0x00000000, 0xc0204810, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000005, 0x00204811, 0x000 },
-    { 0x0000216c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204810, 0x000 },
-    { 0x00000000, 0x002f0224, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00400000, 0x4aa },
-    { 0x00000000, 0xc0210a20, 0x000 },
-    { 0x00000000, 0x14c00000, 0x4c3 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
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-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0604800, 0x692 },
-    { 0x00000000, 0x00400000, 0x4c7 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00040000, 0xc0294620, 0x000 },
-    { 0x00000000, 0xc0600000, 0x68d },
-    { 0x00000001, 0x00210222, 0x000 },
-    { 0x00000000, 0x14c00000, 0x4ce },
-    { 0x00002169, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0xcafebabe, 0x00404811, 0x000 },
-    { 0x00000000, 0xc0204400, 0x000 },
-    { 0x00000000, 0xc0404810, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x000021f8, 0x00204411, 0x000 },
-    { 0x0000000e, 0x00204811, 0x000 },
-    { 0x000421f9, 0x00604411, 0x68d },
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-    { 0x00000000, 0x14c00000, 0x4d0 },
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-    { 0x00000000, 0xc0200000, 0x000 },
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-    { 0x00000000, 0xc0200000, 0x000 },
-    { 0x00000000, 0xc0404800, 0x000 },
-    { 0x00000003, 0x00333e2f, 0x000 },
-    { 0x00000001, 0x00210221, 0x000 },
-    { 0x00000000, 0x14e00000, 0x500 },
-    { 0x0000002c, 0x00200a2d, 0x000 },
-    { 0x00040000, 0x18e00c11, 0x4ef },
-    { 0x00000001, 0x00333e2f, 0x000 },
-    { 0x00002169, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204802, 0x000 },
-    { 0x00000000, 0x00204803, 0x000 },
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-    { 0x00000000, 0x00204803, 0x000 },
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-    { 0x00000000, 0xc0204800, 0x000 },
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-    { 0x00000000, 0x14c00000, 0x000 },
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-    { 0x0000000f, 0x00210221, 0x000 },
-    { 0x00000000, 0x14c00000, 0x505 },
-    { 0x00000000, 0x00600000, 0x00b },
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-    { 0x00000000, 0xc0400400, 0x001 },
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-    { 0x0000f880, 0x00204811, 0x000 },
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-    { 0x0000e000, 0x00204811, 0x000 },
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-    { 0x00000000, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x519 },
-    { 0x00000000, 0xc0200800, 0x000 },
-    { 0x00000000, 0x14c00000, 0x52e },
-    { 0x00000000, 0x00200c11, 0x000 },
-    { 0x0000001c, 0x00203623, 0x000 },
-    { 0x0000002b, 0x00203623, 0x000 },
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-    { 0x00000028, 0x00203623, 0x000 },
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-    { 0x00000025, 0x00203623, 0x000 },
-    { 0x00000026, 0x00203623, 0x000 },
-    { 0x00000015, 0x00203623, 0x000 },
-    { 0x00000016, 0x00203623, 0x000 },
-    { 0xffffe000, 0x00200c11, 0x000 },
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-    { 0x00000023, 0x00203623, 0x000 },
-    { 0x00000024, 0x00203623, 0x000 },
-    { 0xf1ffffff, 0x00283a2e, 0x000 },
-    { 0x0000001a, 0xc0220e20, 0x000 },
-    { 0x00000000, 0x0029386e, 0x000 },
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-    { 0x00000008, 0x00222223, 0x000 },
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-    { 0x00000000, 0x002920e8, 0x000 },
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-    { 0x00000000, 0x003014a8, 0x000 },
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-    { 0xefffffff, 0x00283a2e, 0x000 },
-    { 0x00000000, 0x004938ce, 0x67b },
-    { 0x00000001, 0x40280a20, 0x000 },
-    { 0x00000006, 0x40280e20, 0x000 },
-    { 0x00000300, 0xc0281220, 0x000 },
-    { 0x00000008, 0x00211224, 0x000 },
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-    { 0x00000000, 0x14c00000, 0x566 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00002258, 0x00300a24, 0x000 },
-    { 0x00040000, 0x00694622, 0x68d },
-    { 0x00002169, 0x00204411, 0x000 },
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-    { 0xcafebabe, 0x00204811, 0x000 },
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-    { 0x00000000, 0x0cc00000, 0x56e },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
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-    { 0x00040000, 0x00694622, 0x68d },
-    { 0x00000000, 0xc0201c10, 0x000 },
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-    { 0x00000000, 0xc0604800, 0x692 },
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-    { 0x00000000, 0x00600000, 0x5c9 },
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-    { 0x00000000, 0x0cc00000, 0x58f },
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-    { 0x00000000, 0x00204807, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0004a2b6, 0x00604411, 0x68d },
-    { 0x0000001a, 0x00212230, 0x000 },
-    { 0x00000006, 0x00222630, 0x000 },
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-    { 0x00000000, 0x00404808, 0x000 },
-    { 0x0000a2d1, 0x00204411, 0x000 },
-    { 0x00000001, 0x00504a28, 0x000 },
-    { 0x00000001, 0x002f0224, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x5a0 },
-    { 0x0000a2bb, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204807, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0004a2ba, 0x00604411, 0x68d },
-    { 0x0000001a, 0x00212230, 0x000 },
-    { 0x00000006, 0x00222630, 0x000 },
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-    { 0x00000000, 0x00e00000, 0x59e },
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-    { 0x00000000, 0x00404808, 0x000 },
-    { 0x0000a2d2, 0x00204411, 0x000 },
-    { 0x00000001, 0x00504a28, 0x000 },
-    { 0x00000002, 0x002f0224, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x5b1 },
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-    { 0x00000000, 0x00204807, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0004a2be, 0x00604411, 0x68d },
-    { 0x0000001a, 0x00212230, 0x000 },
-    { 0x00000006, 0x00222630, 0x000 },
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-    { 0x00000000, 0x003048e9, 0x000 },
-    { 0x00000000, 0x00e00000, 0x5af },
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-    { 0x00000000, 0x00404808, 0x000 },
-    { 0x0000a2d3, 0x00204411, 0x000 },
-    { 0x00000001, 0x00504a28, 0x000 },
-    { 0x0000a2c3, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204807, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0004a2c2, 0x00604411, 0x68d },
-    { 0x0000001a, 0x00212230, 0x000 },
-    { 0x00000006, 0x00222630, 0x000 },
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-    { 0x00000000, 0x003048e9, 0x000 },
-    { 0x00000000, 0x00e00000, 0x5be },
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-    { 0x00000000, 0x00404808, 0x000 },
-    { 0x0000a2d4, 0x00204411, 0x000 },
-    { 0x00000001, 0x00504a28, 0x000 },
-    { 0x85000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204801, 0x000 },
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-    { 0x00000000, 0xc0404800, 0x000 },
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-    { 0x00000000, 0xc0400400, 0x001 },
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-    { 0x00000000, 0x0ce00000, 0x5e3 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0004a092, 0x00604411, 0x68d },
-    { 0x00000031, 0x00203630, 0x000 },
-    { 0x0004a093, 0x00604411, 0x68d },
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-    { 0x00000005, 0x00204811, 0x000 },
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-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x88000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000006, 0x00204811, 0x000 },
-    { 0x00000001, 0x002f0230, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x62c },
-    { 0x00000030, 0x0020062d, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x62c },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00007e00, 0x00280621, 0x000 },
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-    { 0x00000000, 0x0ce00000, 0x605 },
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-    { 0x00000000, 0x00210221, 0x000 },
-    { 0x00000000, 0x14c00000, 0x60e },
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-    { 0x0000a003, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x00000001, 0x00210621, 0x000 },
-    { 0x00000000, 0x14c00000, 0x613 },
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-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x00000001, 0x00210621, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x62b },
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-    { 0x0004a013, 0x00604411, 0x68d },
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-    { 0x00000000, 0x00204810, 0x000 },
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-    { 0x00000000, 0x00204810, 0x000 },
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-    { 0x0004a016, 0x00604411, 0x68d },
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-    { 0x00000000, 0x00204810, 0x000 },
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-    { 0xff000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00000002, 0x00804811, 0x000 },
-    { 0x00000000, 0x0ee00000, 0x63d },
-    { 0x00000030, 0x0020062d, 0x000 },
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-    { 0x00000000, 0x0ce00000, 0x63b },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00042004, 0x00604411, 0x68d },
-    { 0x00001000, 0x00200811, 0x000 },
-    { 0x0000002b, 0x00203622, 0x000 },
-    { 0x00000000, 0x00600000, 0x641 },
-    { 0x00000000, 0x00600000, 0x5c9 },
-    { 0x98000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00804811, 0x000 },
-    { 0x00000000, 0xc0600000, 0x641 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x0000a2a4, 0x00204411, 0x000 },
-    { 0x00000022, 0x00204811, 0x000 },
-    { 0x89000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00404811, 0x62d },
-    { 0x97000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x8a000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00404811, 0x62d },
-    { 0x00000000, 0x00600000, 0x65c },
-    { 0x00002010, 0x00204411, 0x000 },
-    { 0x00008000, 0x00204811, 0x000 },
-    { 0x0001a2a4, 0xc0204411, 0x000 },
-    { 0x00000016, 0x00604811, 0x36e },
-    { 0x00002010, 0x00204411, 0x000 },
-    { 0x00010000, 0x00204811, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0000217c, 0x00204411, 0x000 },
-    { 0x09800000, 0x00204811, 0x000 },
-    { 0xffffffff, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x17000000, 0x000 },
-    { 0x0004217f, 0x00604411, 0x68d },
-    { 0x0000001f, 0x00210230, 0x000 },
-    { 0x00000000, 0x14c00000, 0x000 },
-    { 0x00000004, 0x00404c11, 0x656 },
-    { 0x00000000, 0x00400000, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000004, 0x00291e27, 0x000 },
-    { 0x00000017, 0x00803627, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0xfffffffb, 0x00281e27, 0x000 },
-    { 0x00000017, 0x00803627, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000008, 0x00291e27, 0x000 },
-    { 0x00000017, 0x00803627, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0xfffffff7, 0x00281e27, 0x000 },
-    { 0x00000017, 0x00803627, 0x000 },
-    { 0x00002010, 0x00204411, 0x000 },
-    { 0x00008000, 0x00204811, 0x000 },
-    { 0x0001a2a4, 0x00204411, 0x000 },
-    { 0x00000016, 0x00604811, 0x36e },
-    { 0x00002010, 0x00204411, 0x000 },
-    { 0x00010000, 0x00204811, 0x000 },
-    { 0x0000217c, 0x00204411, 0x000 },
-    { 0x01800000, 0x00204811, 0x000 },
-    { 0xffffffff, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x17000000, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0004217f, 0x00604411, 0x68d },
-    { 0x0000001f, 0x00210230, 0x000 },
-    { 0x00000000, 0x14c00000, 0x68c },
-    { 0x00000010, 0x00404c11, 0x672 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x38c00000, 0x000 },
-    { 0x0000001d, 0x00200a2d, 0x000 },
-    { 0x0000001e, 0x00200e2d, 0x000 },
-    { 0x0000001f, 0x0020122d, 0x000 },
-    { 0x00000020, 0x0020162d, 0x000 },
-    { 0x00002169, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204804, 0x000 },
-    { 0x00000000, 0x00204805, 0x000 },
-    { 0x00000000, 0x00204801, 0x000 },
-    { 0xcafebabe, 0x00204811, 0x000 },
-    { 0x00000004, 0x00301224, 0x000 },
-    { 0x00000000, 0x002f0064, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x68b },
-    { 0x00000003, 0x00281a22, 0x000 },
-    { 0x00000008, 0x00221222, 0x000 },
-    { 0xfffff000, 0x00281224, 0x000 },
-    { 0x00000000, 0x002910c4, 0x000 },
-    { 0x0000001f, 0x00403624, 0x000 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x00000000, 0x1ac00000, 0x68d },
-    { 0x9f000000, 0x00204411, 0x000 },
-    { 0xcafebabe, 0x00204811, 0x000 },
-    { 0x00000000, 0x1ae00000, 0x690 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x00000000, 0x1ac00000, 0x692 },
-    { 0x9e000000, 0x00204411, 0x000 },
-    { 0xcafebabe, 0x00204811, 0x000 },
-    { 0x00000000, 0x1ae00000, 0x695 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00001000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001b, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0001a1fd, 0xc0204411, 0x000 },
-    { 0x00000021, 0x00201e2d, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000024, 0x0020222d, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000022, 0x0020222d, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000023, 0x00201e2d, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x00404811, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x01420502, 0x05c00250, 0x000 },
-    { 0x01c30168, 0x043f05c0, 0x000 },
-    { 0x02250209, 0x02500151, 0x000 },
-    { 0x02230245, 0x02a00241, 0x000 },
-    { 0x03d705c0, 0x05c005c0, 0x000 },
-    { 0x0649064a, 0x031f05c0, 0x000 },
-    { 0x05c005c5, 0x03200340, 0x000 },
-    { 0x032a0282, 0x03420334, 0x000 },
-    { 0x05c005c0, 0x05c005c0, 0x000 },
-    { 0x05c00551, 0x05c005c0, 0x000 },
-    { 0x03ba05c0, 0x04bb0344, 0x000 },
-    { 0x049a0450, 0x043d05c0, 0x000 },
-    { 0x04d005c0, 0x044104dd, 0x000 },
-    { 0x04500507, 0x03510375, 0x000 },
-    { 0x05c005c0, 0x05c005c0, 0x000 },
-    { 0x05c005c0, 0x05c005c0, 0x000 },
-    { 0x05c005c0, 0x063f05c7, 0x000 },
-    { 0x05c005c0, 0x000705c0, 0x000 },
-    { 0x05c005c0, 0x05c005c0, 0x000 },
-    { 0x05c005c0, 0x05c005c0, 0x000 },
-    { 0x03f803ed, 0x04080406, 0x000 },
-    { 0x040e040a, 0x040c0410, 0x000 },
-    { 0x041c0418, 0x04240420, 0x000 },
-    { 0x042c0428, 0x04340430, 0x000 },
-    { 0x05c005c0, 0x043805c0, 0x000 },
-    { 0x05c005c0, 0x05c005c0, 0x000 },
-    { 0x05c005c0, 0x05c005c0, 0x000 },
-    { 0x00020679, 0x06970006, 0x000 },
-};
-
-static const u32 RV610_pfp_microcode[] = {
-0xca0400,
-0xa00000,
-0x7e828b,
-0x7c038b,
-0x8001b8,
-0x7c038b,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xc41838,
-0xca2400,
-0xca2800,
-0x9581a8,
-0xc41c3a,
-0xc3c000,
-0xca0800,
-0xca0c00,
-0x7c744b,
-0xc20005,
-0x99c000,
-0xc41c3a,
-0x7c744c,
-0xc0fff0,
-0x042c04,
-0x309002,
-0x7d2500,
-0x351402,
-0x7d350b,
-0x255403,
-0x7cd580,
-0x259c03,
-0x95c004,
-0xd5001b,
-0x7eddc1,
-0x7d9d80,
-0xd6801b,
-0xd5801b,
-0xd4401e,
-0xd5401e,
-0xd6401e,
-0xd6801e,
-0xd4801e,
-0xd4c01e,
-0x9783d3,
-0xd5c01e,
-0xca0800,
-0x80001a,
-0xca0c00,
-0xe4011e,
-0xd4001e,
-0x80000c,
-0xc41838,
-0xe4013e,
-0xd4001e,
-0x80000c,
-0xc41838,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca1800,
-0xd4401e,
-0xd5801e,
-0x800053,
-0xd40075,
-0xd4401e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd48019,
-0xd4c018,
-0xd50017,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xe2001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0xd48060,
-0xd4401e,
-0x800000,
-0xd4801e,
-0xca0800,
-0xd48061,
-0xd4401e,
-0x800000,
-0xd4801e,
-0xca0800,
-0xca0c00,
-0xd4401e,
-0xd48016,
-0xd4c016,
-0xd4801e,
-0x8001b8,
-0xd4c01e,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x948004,
-0xca1400,
-0xe420f3,
-0xd42013,
-0xd56065,
-0xd4e01c,
-0xd5201c,
-0xd5601c,
-0x800000,
-0x062001,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x9483f7,
-0xca1400,
-0xe420f3,
-0x800079,
-0xd42013,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x9883ef,
-0xca1400,
-0xd40064,
-0x80008d,
-0x000000,
-0xc41432,
-0xc61843,
-0xc4082f,
-0x954005,
-0xc40c30,
-0xd4401e,
-0x800000,
-0xee001e,
-0x9583f5,
-0xc41031,
-0xd44033,
-0xd52065,
-0xd4a01c,
-0xd4e01c,
-0xd5201c,
-0xe4015e,
-0xd4001e,
-0x800000,
-0x062001,
-0xca1800,
-0x0a2001,
-0xd60076,
-0xc40836,
-0x988007,
-0xc61045,
-0x950110,
-0xd4001f,
-0xd46062,
-0x800000,
-0xd42062,
-0xcc3835,
-0xcc1433,
-0x8401bb,
-0xd40072,
-0xd5401e,
-0x800000,
-0xee001e,
-0xe2001a,
-0x8401bb,
-0xe2001a,
-0xcc104b,
-0xcc0447,
-0x2c9401,
-0x7d098b,
-0x984005,
-0x7d15cb,
-0xd4001a,
-0x8001b8,
-0xd4006d,
-0x344401,
-0xcc0c48,
-0x98403a,
-0xcc2c4a,
-0x958004,
-0xcc0449,
-0x8001b8,
-0xd4001a,
-0xd4c01a,
-0x282801,
-0x8400f0,
-0xcc1003,
-0x98801b,
-0x04380c,
-0x8400f0,
-0xcc1003,
-0x988017,
-0x043808,
-0x8400f0,
-0xcc1003,
-0x988013,
-0x043804,
-0x8400f0,
-0xcc1003,
-0x988014,
-0xcc104c,
-0x9a8009,
-0xcc144d,
-0x9840dc,
-0xd4006d,
-0xcc1848,
-0xd5001a,
-0xd5401a,
-0x8000c9,
-0xd5801a,
-0x96c0d5,
-0xd4006d,
-0x8001b8,
-0xd4006e,
-0x9ac003,
-0xd4006d,
-0xd4006e,
-0x800000,
-0xec007f,
-0x9ac0cc,
-0xd4006d,
-0x8001b8,
-0xd4006e,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0x7d9103,
-0x7dd583,
-0x7d190c,
-0x35cc1f,
-0x35701f,
-0x7cf0cb,
-0x7cd08b,
-0x880000,
-0x7e8e8b,
-0x95c004,
-0xd4006e,
-0x8001b8,
-0xd4001a,
-0xd4c01a,
-0xcc0803,
-0xcc0c03,
-0xcc1003,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0xcc2403,
-0xcc2803,
-0x35c41f,
-0x36b01f,
-0x7c704b,
-0x34f01f,
-0x7c704b,
-0x35701f,
-0x7c704b,
-0x7d8881,
-0x7dccc1,
-0x7e5101,
-0x7e9541,
-0x7c9082,
-0x7cd4c2,
-0x7c848b,
-0x9ac003,
-0x7c8c8b,
-0x2c8801,
-0x98809e,
-0xd4006d,
-0x98409c,
-0xd4006e,
-0xcc084c,
-0xcc0c4d,
-0xcc1048,
-0xd4801a,
-0xd4c01a,
-0x800101,
-0xd5001a,
-0xcc0832,
-0xd40032,
-0x9482d9,
-0xca0c00,
-0xd4401e,
-0x800000,
-0xd4001e,
-0xe4011e,
-0xd4001e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd4401e,
-0xca1400,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xd5401e,
-0xd54034,
-0x800000,
-0xee001e,
-0x280404,
-0xe2001a,
-0xe2001a,
-0xd4401a,
-0xca3800,
-0xcc0803,
-0xcc0c03,
-0xcc0c03,
-0xcc0c03,
-0x9882bd,
-0x000000,
-0x8401bb,
-0xd7a06f,
-0x800000,
-0xee001f,
-0xca0400,
-0xc2ff00,
-0xcc0834,
-0xc13fff,
-0x7c74cb,
-0x7cc90b,
-0x7d010f,
-0x9902b0,
-0x7c738b,
-0x8401bb,
-0xd7a06f,
-0x800000,
-0xee001f,
-0xca0800,
-0x281900,
-0x7d898b,
-0x958014,
-0x281404,
-0xca0c00,
-0xca1000,
-0xca1c00,
-0xca2400,
-0xe2001f,
-0xd4c01a,
-0xd5001a,
-0xd5401a,
-0xcc1803,
-0xcc2c03,
-0xcc2c03,
-0xcc2c03,
-0x7da58b,
-0x7d9c47,
-0x984297,
-0x000000,
-0x800161,
-0xd4c01a,
-0xd4401e,
-0xd4801e,
-0x800000,
-0xee001e,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0x248c06,
-0x0ccc06,
-0x98c006,
-0xcc104e,
-0x990004,
-0xd40073,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xd4801e,
-0x800000,
-0xee001e,
-0xca0800,
-0xca0c00,
-0x34d018,
-0x251001,
-0x950021,
-0xc17fff,
-0xca1000,
-0xca1400,
-0xca1800,
-0xd4801d,
-0xd4c01d,
-0x7db18b,
-0xc14202,
-0xc2c001,
-0xd5801d,
-0x34dc0e,
-0x7d5d4c,
-0x7f734c,
-0xd7401e,
-0xd5001e,
-0xd5401e,
-0xc14200,
-0xc2c000,
-0x099c01,
-0x31dc10,
-0x7f5f4c,
-0x7f734c,
-0x042802,
-0x7d8380,
-0xd5a86f,
-0xd58066,
-0xd7401e,
-0xec005e,
-0xc82402,
-0xc82402,
-0x8001b8,
-0xd60076,
-0xd4401e,
-0xd4801e,
-0xd4c01e,
-0x800000,
-0xee001e,
-0x800000,
-0xee001f,
-0xd4001f,
-0x800000,
-0xd4001f,
-0xd4001f,
-0x880000,
-0xd4001f,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x010171,
-0x020178,
-0x03008f,
-0x04007f,
-0x050003,
-0x06003f,
-0x070032,
-0x08012c,
-0x090046,
-0x0a0036,
-0x1001b6,
-0x1700a2,
-0x22013a,
-0x230149,
-0x2000b4,
-0x240125,
-0x27004d,
-0x28006a,
-0x2a0060,
-0x2b0052,
-0x2f0065,
-0x320087,
-0x34017f,
-0x3c0156,
-0x3f0072,
-0x41018c,
-0x44012e,
-0x550173,
-0x56017a,
-0x60000b,
-0x610034,
-0x620038,
-0x630038,
-0x640038,
-0x650038,
-0x660038,
-0x670038,
-0x68003a,
-0x690041,
-0x6a0048,
-0x6b0048,
-0x6c0048,
-0x6d0048,
-0x6e0048,
-0x6f0048,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-};
-
-static const u32 RV620_cp_microcode[][3] = {
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x0000ffff, 0x00284621, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x00000000, 0x00e00000, 0x000 },
-    { 0x00010000, 0xc0294620, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00042004, 0x00604411, 0x68d },
-    { 0x00000000, 0x00600000, 0x631 },
-    { 0x00000000, 0x00600000, 0x645 },
-    { 0x00000000, 0xc0200800, 0x000 },
-    { 0x00000f00, 0x00281622, 0x000 },
-    { 0x00000008, 0x00211625, 0x000 },
-    { 0x00000018, 0x00203625, 0x000 },
-    { 0x8d000000, 0x00204411, 0x000 },
-    { 0x00000004, 0x002f0225, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x018 },
-    { 0x00412000, 0x00404811, 0x019 },
-    { 0x00422000, 0x00204811, 0x000 },
-    { 0x8e000000, 0x00204411, 0x000 },
-    { 0x00000028, 0x00204a2d, 0x000 },
-    { 0x90000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204805, 0x000 },
-    { 0x0000000c, 0x00211622, 0x000 },
-    { 0x00000003, 0x00281625, 0x000 },
-    { 0x00000019, 0x00211a22, 0x000 },
-    { 0x00000004, 0x00281a26, 0x000 },
-    { 0x00000000, 0x002914c5, 0x000 },
-    { 0x00000019, 0x00203625, 0x000 },
-    { 0x00000000, 0x003a1402, 0x000 },
-    { 0x00000016, 0x00211625, 0x000 },
-    { 0x00000003, 0x00281625, 0x000 },
-    { 0x00000017, 0x00200e2d, 0x000 },
-    { 0xfffffffc, 0x00280e23, 0x000 },
-    { 0x00000000, 0x002914a3, 0x000 },
-    { 0x00000017, 0x00203625, 0x000 },
-    { 0x00008000, 0x00280e22, 0x000 },
-    { 0x00000007, 0x00220e23, 0x000 },
-    { 0x00000000, 0x0029386e, 0x000 },
-    { 0x20000000, 0x00280e22, 0x000 },
-    { 0x00000006, 0x00210e23, 0x000 },
-    { 0x00000000, 0x0029386e, 0x000 },
-    { 0x00000000, 0x00220222, 0x000 },
-    { 0x00000000, 0x14e00000, 0x038 },
-    { 0x00000000, 0x2ee00000, 0x035 },
-    { 0x00000000, 0x2ce00000, 0x037 },
-    { 0x00000000, 0x00400e2d, 0x039 },
-    { 0x00000008, 0x00200e2d, 0x000 },
-    { 0x00000009, 0x0040122d, 0x046 },
-    { 0x00000001, 0x00400e2d, 0x039 },
-    { 0x00000000, 0xc0200c00, 0x000 },
-    { 0x003ffffc, 0x00281223, 0x000 },
-    { 0x00000002, 0x00221224, 0x000 },
-    { 0x0000001f, 0x00211e23, 0x000 },
-    { 0x00000000, 0x14e00000, 0x03e },
-    { 0x00000008, 0x00401c11, 0x041 },
-    { 0x0000000d, 0x00201e2d, 0x000 },
-    { 0x0000000f, 0x00281e27, 0x000 },
-    { 0x00000003, 0x00221e27, 0x000 },
-    { 0x7fc00000, 0x00281a23, 0x000 },
-    { 0x00000014, 0x00211a26, 0x000 },
-    { 0x00000001, 0x00331a26, 0x000 },
-    { 0x00000008, 0x00221a26, 0x000 },
-    { 0x00000000, 0x00290cc7, 0x000 },
-    { 0x00000027, 0x00203624, 0x000 },
-    { 0x00007f00, 0x00281221, 0x000 },
-    { 0x00001400, 0x002f0224, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x04b },
-    { 0x00000001, 0x00290e23, 0x000 },
-    { 0x0000000e, 0x00203623, 0x000 },
-    { 0x0000e000, 0x00204411, 0x000 },
-    { 0xfff80000, 0x00294a23, 0x000 },
-    { 0x00000000, 0x003a2c02, 0x000 },
-    { 0x00000002, 0x00220e2b, 0x000 },
-    { 0xfc000000, 0x00280e23, 0x000 },
-    { 0x0000000f, 0x00203623, 0x000 },
-    { 0x00001fff, 0x00294a23, 0x000 },
-    { 0x00000027, 0x00204a2d, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000029, 0x00200e2d, 0x000 },
-    { 0x060a0200, 0x00294a23, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000001, 0x00210222, 0x000 },
-    { 0x00000000, 0x14e00000, 0x061 },
-    { 0x00000000, 0x2ee00000, 0x05f },
-    { 0x00000000, 0x2ce00000, 0x05e },
-    { 0x00000000, 0x00400e2d, 0x062 },
-    { 0x00000001, 0x00400e2d, 0x062 },
-    { 0x0000000a, 0x00200e2d, 0x000 },
-    { 0x0000000b, 0x0040122d, 0x06a },
-    { 0x00000000, 0xc0200c00, 0x000 },
-    { 0x003ffffc, 0x00281223, 0x000 },
-    { 0x00000002, 0x00221224, 0x000 },
-    { 0x7fc00000, 0x00281623, 0x000 },
-    { 0x00000014, 0x00211625, 0x000 },
-    { 0x00000001, 0x00331625, 0x000 },
-    { 0x80000000, 0x00280e23, 0x000 },
-    { 0x00000000, 0x00290ca3, 0x000 },
-    { 0x3ffffc00, 0x00290e23, 0x000 },
-    { 0x0000001f, 0x00211e23, 0x000 },
-    { 0x00000000, 0x14e00000, 0x06d },
-    { 0x00000100, 0x00401c11, 0x070 },
-    { 0x0000000d, 0x00201e2d, 0x000 },
-    { 0x000000f0, 0x00281e27, 0x000 },
-    { 0x00000004, 0x00221e27, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000d, 0x00204811, 0x000 },
-    { 0xfffff0ff, 0x00281a30, 0x000 },
-    { 0x0000a028, 0x00204411, 0x000 },
-    { 0x00000000, 0x002948e6, 0x000 },
-    { 0x0000a018, 0x00204411, 0x000 },
-    { 0x3fffffff, 0x00284a23, 0x000 },
-    { 0x0000a010, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204804, 0x000 },
-    { 0x00000030, 0x0020162d, 0x000 },
-    { 0x00000002, 0x00291625, 0x000 },
-    { 0x00000030, 0x00203625, 0x000 },
-    { 0x00000025, 0x0020162d, 0x000 },
-    { 0x00000000, 0x002f00a3, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x083 },
-    { 0x00000026, 0x0020162d, 0x000 },
-    { 0x00000000, 0x002f00a4, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x084 },
-    { 0x00000000, 0x00400000, 0x08a },
-    { 0x00000025, 0x00203623, 0x000 },
-    { 0x00000026, 0x00203624, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000002, 0x00210227, 0x000 },
-    { 0x00000000, 0x14e00000, 0x08a },
-    { 0x00000000, 0x00600000, 0x668 },
-    { 0x00000000, 0x00600000, 0x65c },
-    { 0x00000002, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x08d },
-    { 0x00000012, 0xc0403620, 0x093 },
-    { 0x00000000, 0x2ee00000, 0x091 },
-    { 0x00000000, 0x2ce00000, 0x090 },
-    { 0x00000002, 0x00400e2d, 0x092 },
-    { 0x00000003, 0x00400e2d, 0x092 },
-    { 0x0000000c, 0x00200e2d, 0x000 },
-    { 0x00000012, 0x00203623, 0x000 },
-    { 0x00000003, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x098 },
-    { 0x0000a00c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0404800, 0x0a0 },
-    { 0x0000a00c, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x2ee00000, 0x09e },
-    { 0x00000000, 0x2ce00000, 0x09d },
-    { 0x00000002, 0x00400e2d, 0x09f },
-    { 0x00000003, 0x00400e2d, 0x09f },
-    { 0x0000000c, 0x00200e2d, 0x000 },
-    { 0x00000000, 0x00204803, 0x000 },
-    { 0x00000000, 0x003a0c02, 0x000 },
-    { 0x003f0000, 0x00280e23, 0x000 },
-    { 0x00000010, 0x00210e23, 0x000 },
-    { 0x00000011, 0x00203623, 0x000 },
-    { 0x0000001e, 0x0021022b, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0a7 },
-    { 0x00000016, 0xc0203620, 0x000 },
-    { 0x0000001f, 0x0021022b, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0aa },
-    { 0x00000015, 0xc0203620, 0x000 },
-    { 0x00000008, 0x00210e2b, 0x000 },
-    { 0x0000007f, 0x00280e23, 0x000 },
-    { 0x00000000, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0e1 },
-    { 0x00000000, 0x27000000, 0x000 },
-    { 0x00000000, 0x00600000, 0x2a3 },
-    { 0x00000001, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ae00000, 0x0b3 },
-    { 0x00000000, 0x00600000, 0x13a },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000006, 0x00204811, 0x000 },
-    { 0x0000000c, 0x00221e30, 0x000 },
-    { 0x99800000, 0x00204411, 0x000 },
-    { 0x00000004, 0x0020122d, 0x000 },
-    { 0x00000008, 0x00221224, 0x000 },
-    { 0x00000010, 0x00201811, 0x000 },
-    { 0x00000000, 0x00291ce4, 0x000 },
-    { 0x00000000, 0x00604807, 0x12f },
-    { 0x9b000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204802, 0x000 },
-    { 0x9c000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x0033146f, 0x000 },
-    { 0x00000001, 0x00333e23, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0x00203c05, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000e, 0x00204811, 0x000 },
-    { 0x00000000, 0x00201010, 0x000 },
-    { 0x0000e007, 0x00204411, 0x000 },
-    { 0x0000000f, 0x0021022b, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0cb },
-    { 0x00f8ff08, 0x00204811, 0x000 },
-    { 0x98000000, 0x00404811, 0x0dc },
-    { 0x000000f0, 0x00280e22, 0x000 },
-    { 0x000000a0, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x0da },
-    { 0x00000011, 0x00200e2d, 0x000 },
-    { 0x00000001, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0d5 },
-    { 0x00000002, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0d4 },
-    { 0x00003f00, 0x00400c11, 0x0d6 },
-    { 0x00001f00, 0x00400c11, 0x0d6 },
-    { 0x00000f00, 0x00200c11, 0x000 },
-    { 0x00380009, 0x00294a23, 0x000 },
-    { 0x3f000000, 0x00280e2b, 0x000 },
-    { 0x00000002, 0x00220e23, 0x000 },
-    { 0x00000007, 0x00494a23, 0x0dc },
-    { 0x00380f09, 0x00204811, 0x000 },
-    { 0x68000007, 0x00204811, 0x000 },
-    { 0x00000008, 0x00214a27, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x060a0200, 0x00294a24, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000a202, 0x00204411, 0x000 },
-    { 0x00ff0000, 0x00280e22, 0x000 },
-    { 0x00000080, 0x00294a23, 0x000 },
-    { 0x00000027, 0x00200e2d, 0x000 },
-    { 0x00000026, 0x0020122d, 0x000 },
-    { 0x00000000, 0x002f0083, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0ea },
-    { 0x00000000, 0x00600000, 0x662 },
-    { 0x00000000, 0x00400000, 0x0eb },
-    { 0x00000000, 0x00600000, 0x665 },
-    { 0x00000007, 0x0020222d, 0x000 },
-    { 0x00000005, 0x00220e22, 0x000 },
-    { 0x00100000, 0x00280e23, 0x000 },
-    { 0x00000000, 0x00292068, 0x000 },
-    { 0x00000000, 0x003a0c02, 0x000 },
-    { 0x000000ef, 0x00280e23, 0x000 },
-    { 0x00000000, 0x00292068, 0x000 },
-    { 0x00000017, 0x00200e2d, 0x000 },
-    { 0x00000003, 0x00210223, 0x000 },
-    { 0x00000000, 0x14e00000, 0x0f8 },
-    { 0x0000000b, 0x00210228, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0f8 },
-    { 0x00000400, 0x00292228, 0x000 },
-    { 0x00000014, 0x00203628, 0x000 },
-    { 0x0000001c, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0fd },
-    { 0x0000a30c, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000001e, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x10b },
-    { 0x0000a30f, 0x00204411, 0x000 },
-    { 0x00000011, 0x00200e2d, 0x000 },
-    { 0x00000001, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x104 },
-    { 0xffffffff, 0x00404811, 0x10b },
-    { 0x00000002, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x107 },
-    { 0x0000ffff, 0x00404811, 0x10b },
-    { 0x00000004, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x10a },
-    { 0x000000ff, 0x00404811, 0x10b },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0002c400, 0x00204411, 0x000 },
-    { 0x0000001f, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x112 },
-    { 0x00000010, 0x40210e20, 0x000 },
-    { 0x00000013, 0x00203623, 0x000 },
-    { 0x00000018, 0x40224a20, 0x000 },
-    { 0x00000010, 0xc0424a20, 0x114 },
-    { 0x00000000, 0x00200c11, 0x000 },
-    { 0x00000013, 0x00203623, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000000a, 0x00201011, 0x000 },
-    { 0x00000000, 0x002f0224, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x11b },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000001, 0x00531224, 0x117 },
-    { 0xffbfffff, 0x00283a2e, 0x000 },
-    { 0x0000001b, 0x00210222, 0x000 },
-    { 0x00000000, 0x14c00000, 0x12e },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000d, 0x00204811, 0x000 },
-    { 0x00000018, 0x00220e30, 0x000 },
-    { 0xfc000000, 0x00280e23, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000e, 0x00204811, 0x000 },
-    { 0x00000000, 0x00201010, 0x000 },
-    { 0x0000e00e, 0x00204411, 0x000 },
-    { 0x07f8ff08, 0x00204811, 0x000 },
-    { 0x00000000, 0x00294a23, 0x000 },
-    { 0x0000001c, 0x00201e2d, 0x000 },
-    { 0x00000008, 0x00214a27, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x060a0200, 0x00294a24, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0000217c, 0x00204411, 0x000 },
-    { 0x00800000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204806, 0x000 },
-    { 0x00000008, 0x00214a27, 0x000 },
-    { 0x00000000, 0x17000000, 0x000 },
-    { 0x0004217f, 0x00604411, 0x68d },
-    { 0x0000001f, 0x00210230, 0x000 },
-    { 0x00000000, 0x14c00000, 0x68c },
-    { 0x00000004, 0x00404c11, 0x135 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x000021f8, 0x00204411, 0x000 },
-    { 0x0000001c, 0x00204811, 0x000 },
-    { 0x000421f9, 0x00604411, 0x68d },
-    { 0x00000011, 0x00210230, 0x000 },
-    { 0x00000000, 0x14e00000, 0x13c },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x00000000, 0x00600000, 0x160 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x00000010, 0xc0211220, 0x000 },
-    { 0x0000ffff, 0x40280620, 0x000 },
-    { 0x00000010, 0xc0210a20, 0x000 },
-    { 0x00000000, 0x00341461, 0x000 },
-    { 0x00000000, 0x00741882, 0x2bb },
-    { 0x0001a1fd, 0x00604411, 0x2e0 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x147 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00600000, 0x160 },
-    { 0x00000010, 0x40210e20, 0x000 },
-    { 0x0000ffff, 0xc0281220, 0x000 },
-    { 0x00000010, 0x40211620, 0x000 },
-    { 0x0000ffff, 0xc0681a20, 0x2bb },
-    { 0x0001a1fd, 0x00604411, 0x2e0 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x158 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000001, 0x00300a2f, 0x000 },
-    { 0x00000001, 0x00210a22, 0x000 },
-    { 0x00000003, 0x00384a22, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001a, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00804811, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600000, 0x18f },
-    { 0x00000000, 0x00600000, 0x1a0 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00202c08, 0x000 },
-    { 0x00000000, 0x00202411, 0x000 },
-    { 0x00000000, 0x00202811, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x00000016, 0x00204811, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x93800000, 0x00204411, 0x000 },
-    { 0x00000002, 0x00221e29, 0x000 },
-    { 0x00000000, 0x007048eb, 0x19c },
-    { 0x00000000, 0x00600000, 0x2bb },
-    { 0x00000001, 0x40330620, 0x000 },
-    { 0x00000000, 0xc0302409, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00600000, 0x2a3 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ae00000, 0x181 },
-    { 0x00000000, 0x00600000, 0x13a },
-    { 0x00000000, 0x00400000, 0x186 },
-    { 0x95000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x186 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000001, 0x00530621, 0x182 },
-    { 0x92000000, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0604800, 0x197 },
-    { 0x0001a1fd, 0x00204411, 0x000 },
-    { 0x00000011, 0x0020062d, 0x000 },
-    { 0x00000000, 0x0078042a, 0x2fb },
-    { 0x00000000, 0x00202809, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x174 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000210, 0x00600411, 0x315 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x194 },
-    { 0x00000015, 0xc0203620, 0x000 },
-    { 0x00000016, 0xc0203620, 0x000 },
-    { 0x3f800000, 0x00200411, 0x000 },
-    { 0x46000000, 0x00600811, 0x1b2 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x19b },
-    { 0x00000001, 0x00804811, 0x000 },
-    { 0x00000021, 0x00804811, 0x000 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x00000010, 0xc0211220, 0x000 },
-    { 0x0000ffff, 0x40281620, 0x000 },
-    { 0x00000010, 0xc0811a20, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000006, 0x00204811, 0x000 },
-    { 0x00000008, 0x00221e30, 0x000 },
-    { 0x00000029, 0x00201a2d, 0x000 },
-    { 0x0000e000, 0x00204411, 0x000 },
-    { 0xfffbff09, 0x00204811, 0x000 },
-    { 0x0000000f, 0x0020222d, 0x000 },
-    { 0x00001fff, 0x00294a28, 0x000 },
-    { 0x00000006, 0x0020222d, 0x000 },
-    { 0x00000000, 0x002920e8, 0x000 },
-    { 0x00000000, 0x00204808, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x060a0200, 0x00294a26, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000100, 0x00201811, 0x000 },
-    { 0x00000008, 0x00621e28, 0x12f },
-    { 0x00000008, 0x00822228, 0x000 },
-    { 0x0002c000, 0x00204411, 0x000 },
-    { 0x00000015, 0x00600e2d, 0x1bd },
-    { 0x00000016, 0x00600e2d, 0x1bd },
-    { 0x0000c008, 0x00204411, 0x000 },
-    { 0x00000017, 0x00200e2d, 0x000 },
-    { 0x00000000, 0x14c00000, 0x1b9 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00204801, 0x000 },
-    { 0x39000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00804802, 0x000 },
-    { 0x00000018, 0x00202e2d, 0x000 },
-    { 0x00000000, 0x003b0d63, 0x000 },
-    { 0x00000008, 0x00224a23, 0x000 },
-    { 0x00000010, 0x00224a23, 0x000 },
-    { 0x00000018, 0x00224a23, 0x000 },
-    { 0x00000000, 0x00804803, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00001000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x00000007, 0x0021062f, 0x000 },
-    { 0x00000013, 0x00200a2d, 0x000 },
-    { 0x00000001, 0x00202c11, 0x000 },
-    { 0x0000ffff, 0x40282220, 0x000 },
-    { 0x0000000f, 0x00262228, 0x000 },
-    { 0x00000010, 0x40212620, 0x000 },
-    { 0x0000000f, 0x00262629, 0x000 },
-    { 0x00000000, 0x00202802, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001b, 0x00204811, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x1e0 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000081, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00000080, 0x00201c11, 0x000 },
-    { 0x00000000, 0x002f0227, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x1dc },
-    { 0x00000000, 0x00600000, 0x1e9 },
-    { 0x00000001, 0x00531e27, 0x1d8 },
-    { 0x00000001, 0x00202c11, 0x000 },
-    { 0x0000001f, 0x00280a22, 0x000 },
-    { 0x0000001f, 0x00282a2a, 0x000 },
-    { 0x00000001, 0x00530621, 0x1d1 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000002, 0x00304a2f, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00000001, 0x00301e2f, 0x000 },
-    { 0x00000000, 0x002f0227, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00600000, 0x1e9 },
-    { 0x00000001, 0x00531e27, 0x1e5 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x0000000f, 0x00260e23, 0x000 },
-    { 0x00000010, 0xc0211220, 0x000 },
-    { 0x0000000f, 0x00261224, 0x000 },
-    { 0x00000000, 0x00201411, 0x000 },
-    { 0x00000000, 0x00601811, 0x2bb },
-    { 0x0001a1fd, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f022b, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x1f8 },
-    { 0x00000010, 0x00221628, 0x000 },
-    { 0xffff0000, 0x00281625, 0x000 },
-    { 0x0000ffff, 0x00281a29, 0x000 },
-    { 0x00000000, 0x002948c5, 0x000 },
-    { 0x00000000, 0x0020480a, 0x000 },
-    { 0x00000000, 0x00202c11, 0x000 },
-    { 0x00000010, 0x00221623, 0x000 },
-    { 0xffff0000, 0x00281625, 0x000 },
-    { 0x0000ffff, 0x00281a24, 0x000 },
-    { 0x00000000, 0x002948c5, 0x000 },
-    { 0x00000000, 0x00731503, 0x205 },
-    { 0x00000000, 0x00201805, 0x000 },
-    { 0x00000000, 0x00731524, 0x205 },
-    { 0x00000000, 0x002d14c5, 0x000 },
-    { 0x00000000, 0x003008a2, 0x000 },
-    { 0x00000000, 0x00204802, 0x000 },
-    { 0x00000000, 0x00202802, 0x000 },
-    { 0x00000000, 0x00202003, 0x000 },
-    { 0x00000000, 0x00802404, 0x000 },
-    { 0x0000000f, 0x00210225, 0x000 },
-    { 0x00000000, 0x14c00000, 0x68c },
-    { 0x00000000, 0x002b1405, 0x000 },
-    { 0x00000001, 0x00901625, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001a, 0x00294a22, 0x000 },
-    { 0x00000000, 0xc0200000, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00384a21, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0000ffff, 0x40281220, 0x000 },
-    { 0x00000010, 0xc0211a20, 0x000 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x00000010, 0xc0211620, 0x000 },
-    { 0x00000000, 0x00741465, 0x2bb },
-    { 0x0001a1fd, 0x00604411, 0x2e0 },
-    { 0x00000001, 0x00330621, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x219 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x212 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000000, 0x00600000, 0x645 },
-    { 0x00000000, 0x0040040f, 0x213 },
-    { 0x00000000, 0x00600000, 0x631 },
-    { 0x00000000, 0x00600000, 0x645 },
-    { 0x00000210, 0x00600411, 0x315 },
-    { 0x00000000, 0x00600000, 0x1a0 },
-    { 0x00000000, 0x00600000, 0x19c },
-    { 0x00000000, 0x00600000, 0x2bb },
-    { 0x00000000, 0x00600000, 0x2a3 },
-    { 0x93800000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204808, 0x000 },
-    { 0x00000000, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ae00000, 0x232 },
-    { 0x00000000, 0x00600000, 0x13a },
-    { 0x00000000, 0x00400000, 0x236 },
-    { 0x95000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x236 },
-    { 0x00000000, 0xc0404800, 0x233 },
-    { 0x92000000, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x00000016, 0x00204811, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0001a1fd, 0x00204411, 0x000 },
-    { 0x00000000, 0x00600411, 0x2fb },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000000, 0x00600000, 0x631 },
-    { 0x0000a00c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0404800, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000018, 0x40210a20, 0x000 },
-    { 0x00000003, 0x002f0222, 0x000 },
-    { 0x00000000, 0x0ae00000, 0x24c },
-    { 0x00000014, 0x0020222d, 0x000 },
-    { 0x00080101, 0x00292228, 0x000 },
-    { 0x00000014, 0x00203628, 0x000 },
-    { 0x0000a30c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0404800, 0x251 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000010, 0x00600411, 0x315 },
-    { 0x3f800000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x00000000, 0x00600000, 0x27c },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000001, 0x00211e27, 0x000 },
-    { 0x00000000, 0x14e00000, 0x26a },
-    { 0x00000012, 0x00201e2d, 0x000 },
-    { 0x0000ffff, 0x00281e27, 0x000 },
-    { 0x00000000, 0x00341c27, 0x000 },
-    { 0x00000000, 0x12c00000, 0x25f },
-    { 0x00000000, 0x00201c11, 0x000 },
-    { 0x00000000, 0x002f00e5, 0x000 },
-    { 0x00000000, 0x08c00000, 0x262 },
-    { 0x00000000, 0x00201407, 0x000 },
-    { 0x00000012, 0x00201e2d, 0x000 },
-    { 0x00000010, 0x00211e27, 0x000 },
-    { 0x00000000, 0x00341c47, 0x000 },
-    { 0x00000000, 0x12c00000, 0x267 },
-    { 0x00000000, 0x00201c11, 0x000 },
-    { 0x00000000, 0x002f00e6, 0x000 },
-    { 0x00000000, 0x08c00000, 0x26a },
-    { 0x00000000, 0x00201807, 0x000 },
-    { 0x00000000, 0x00600000, 0x2c1 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x00000000, 0x00342023, 0x000 },
-    { 0x00000000, 0x12c00000, 0x272 },
-    { 0x00000000, 0x00342044, 0x000 },
-    { 0x00000000, 0x12c00000, 0x271 },
-    { 0x00000016, 0x00404811, 0x276 },
-    { 0x00000018, 0x00404811, 0x276 },
-    { 0x00000000, 0x00342044, 0x000 },
-    { 0x00000000, 0x12c00000, 0x275 },
-    { 0x00000017, 0x00404811, 0x276 },
-    { 0x00000019, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0001a1fd, 0x00604411, 0x2e9 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x256 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000010, 0x40210620, 0x000 },
-    { 0x0000ffff, 0xc0280a20, 0x000 },
-    { 0x00000010, 0x40210e20, 0x000 },
-    { 0x0000ffff, 0xc0281220, 0x000 },
-    { 0x00000010, 0x40211620, 0x000 },
-    { 0x0000ffff, 0xc0881a20, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00042004, 0x00604411, 0x68d },
-    { 0x00000000, 0x00600000, 0x631 },
-    { 0x00000000, 0xc0600000, 0x2a3 },
-    { 0x00000005, 0x00200a2d, 0x000 },
-    { 0x00000008, 0x00220a22, 0x000 },
-    { 0x0000002b, 0x00201a2d, 0x000 },
-    { 0x0000001c, 0x00201e2d, 0x000 },
-    { 0x00007000, 0x00281e27, 0x000 },
-    { 0x00000000, 0x00311ce6, 0x000 },
-    { 0x0000002a, 0x00201a2d, 0x000 },
-    { 0x0000000c, 0x00221a26, 0x000 },
-    { 0x00000000, 0x002f00e6, 0x000 },
-    { 0x00000000, 0x06e00000, 0x292 },
-    { 0x00000000, 0x00201c11, 0x000 },
-    { 0x00000000, 0x00200c11, 0x000 },
-    { 0x0000002b, 0x00203623, 0x000 },
-    { 0x00000010, 0x00201811, 0x000 },
-    { 0x00000000, 0x00691ce2, 0x12f },
-    { 0x93800000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204807, 0x000 },
-    { 0x95000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x29d },
-    { 0x00000001, 0x00333e2f, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x92000000, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x0000001c, 0x00403627, 0x000 },
-    { 0x0000000c, 0xc0220a20, 0x000 },
-    { 0x00000029, 0x00203622, 0x000 },
-    { 0x00000028, 0xc0403620, 0x000 },
-    { 0x0000a2a4, 0x00204411, 0x000 },
-    { 0x00000009, 0x00204811, 0x000 },
-    { 0xa1000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00804811, 0x000 },
-    { 0x00000021, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x002c1ce3, 0x000 },
-    { 0x00000021, 0x00203627, 0x000 },
-    { 0x00000022, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x002c1ce4, 0x000 },
-    { 0x00000022, 0x00203627, 0x000 },
-    { 0x00000023, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x003120a3, 0x000 },
-    { 0x00000000, 0x002d1d07, 0x000 },
-    { 0x00000023, 0x00203627, 0x000 },
-    { 0x00000024, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x003120c4, 0x000 },
-    { 0x00000000, 0x002d1d07, 0x000 },
-    { 0x00000024, 0x00803627, 0x000 },
-    { 0x00000021, 0x00203623, 0x000 },
-    { 0x00000022, 0x00203624, 0x000 },
-    { 0x00000000, 0x00311ca3, 0x000 },
-    { 0x00000023, 0x00203627, 0x000 },
-    { 0x00000000, 0x00311cc4, 0x000 },
-    { 0x00000024, 0x00803627, 0x000 },
-    { 0x0000001a, 0x00203627, 0x000 },
-    { 0x0000001b, 0x00203628, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000002, 0x00210227, 0x000 },
-    { 0x00000000, 0x14c00000, 0x2dc },
-    { 0x00000000, 0x00400000, 0x2d9 },
-    { 0x0000001a, 0x00203627, 0x000 },
-    { 0x0000001b, 0x00203628, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000002, 0x00210227, 0x000 },
-    { 0x00000000, 0x14e00000, 0x2d9 },
-    { 0x00000003, 0x00210227, 0x000 },
-    { 0x00000000, 0x14e00000, 0x2dc },
-    { 0x00000023, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x002e00e1, 0x000 },
-    { 0x00000000, 0x02c00000, 0x2dc },
-    { 0x00000021, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x003120a1, 0x000 },
-    { 0x00000000, 0x002e00e8, 0x000 },
-    { 0x00000000, 0x06c00000, 0x2dc },
-    { 0x00000024, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x002e00e2, 0x000 },
-    { 0x00000000, 0x02c00000, 0x2dc },
-    { 0x00000022, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x003120c2, 0x000 },
-    { 0x00000000, 0x002e00e8, 0x000 },
-    { 0x00000000, 0x06c00000, 0x2dc },
-    { 0x00000000, 0x00600000, 0x668 },
-    { 0x00000000, 0x00600000, 0x2b5 },
-    { 0x00000000, 0x00400000, 0x2de },
-    { 0x00000000, 0x00600000, 0x2b5 },
-    { 0x00000000, 0x00600000, 0x65f },
-    { 0x00000000, 0x00400000, 0x2de },
-    { 0x00000000, 0x00600000, 0x2a7 },
-    { 0x00000000, 0x00400000, 0x2de },
-    { 0x0000001a, 0x00201e2d, 0x000 },
-    { 0x0000001b, 0x0080222d, 0x000 },
-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000000, 0x00311ca3, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x003120c4, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00894907, 0x000 },
-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000010, 0x00221e21, 0x000 },
-    { 0x00000000, 0x00294847, 0x000 },
-    { 0x00000000, 0x00311ca3, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000000, 0x00311ca1, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294847, 0x000 },
-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x003120c4, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
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-    { 0x00000000, 0x003120c2, 0x000 },
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-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000001, 0x00220a21, 0x000 },
-    { 0x00000000, 0x003308a2, 0x000 },
-    { 0x00000010, 0x00221e22, 0x000 },
-    { 0x00000010, 0x00212222, 0x000 },
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-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000001, 0x00220a21, 0x000 },
-    { 0x00000000, 0x003008a2, 0x000 },
-    { 0x00000010, 0x00221e22, 0x000 },
-    { 0x00000010, 0x00212222, 0x000 },
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-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x003808c5, 0x000 },
-    { 0x00000000, 0x00300841, 0x000 },
-    { 0x00000001, 0x00220a22, 0x000 },
-    { 0x00000000, 0x003308a2, 0x000 },
-    { 0x00000010, 0x00221e22, 0x000 },
-    { 0x00000010, 0x00212222, 0x000 },
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-    { 0x0000a1fc, 0x00204411, 0x000 },
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-    { 0x00000000, 0xc0404800, 0x000 },
-    { 0x00000000, 0x00600000, 0x645 },
-    { 0x00000000, 0xc0200800, 0x000 },
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-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x40204800, 0x000 },
-    { 0x00000001, 0x40304a20, 0x000 },
-    { 0x00000002, 0xc0304a20, 0x000 },
-    { 0x00000001, 0x00530a22, 0x34b },
-    { 0x0000003f, 0xc0280a20, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x000021f8, 0x00204411, 0x000 },
-    { 0x00000018, 0x00204811, 0x000 },
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-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0404800, 0x000 },
-    { 0x00000004, 0x002f0222, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x36a },
-    { 0x00002010, 0x00204411, 0x000 },
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-    { 0x0001a2a4, 0x00204411, 0x000 },
-    { 0x00000000, 0x00404802, 0x35f },
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-    { 0x0001a2a4, 0x00204411, 0x000 },
-    { 0x00000000, 0x00404802, 0x35f },
-    { 0x0000002c, 0x00203626, 0x000 },
-    { 0x00000049, 0x00201811, 0x000 },
-    { 0x0000003f, 0x00204811, 0x000 },
-    { 0x00000001, 0x00331a26, 0x000 },
-    { 0x00000000, 0x002f0226, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x370 },
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-    { 0x00000000, 0x00404803, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x000021f8, 0x00204411, 0x000 },
-    { 0x00000016, 0x00204811, 0x000 },
-    { 0x000421f9, 0x00604411, 0x68d },
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-    { 0x00000000, 0x00404802, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
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-    { 0x00000000, 0x14e00000, 0x3ce },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
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-    { 0xcafebabe, 0x00404811, 0x000 },
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-    { 0x00000001, 0x00204811, 0x000 },
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-    { 0x80000000, 0x40280e20, 0x000 },
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-    { 0x00000001, 0x00204811, 0x000 },
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-    { 0x00000001, 0x00204811, 0x000 },
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-    { 0x0000000e, 0x00204811, 0x000 },
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-    { 0x0000002c, 0x00200a2d, 0x000 },
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-    { 0x00000001, 0x40280a20, 0x000 },
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-    { 0x00000001, 0x00204811, 0x000 },
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-    { 0x00000000, 0x0cc00000, 0x5a0 },
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-    { 0x00000001, 0x00204811, 0x000 },
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-    { 0x00000001, 0x00504a28, 0x000 },
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-    { 0x00000000, 0x00404808, 0x000 },
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-    { 0x00000001, 0x00504a28, 0x000 },
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-    { 0x00000000, 0x00204807, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
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-    { 0x00000000, 0x00404808, 0x000 },
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-    { 0x00000001, 0x00504a28, 0x000 },
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-    { 0x00000000, 0x0ce00000, 0x5e3 },
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-    { 0x00000000, 0x00204811, 0x000 },
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-    { 0x00000001, 0x00204811, 0x000 },
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-    { 0x00000006, 0x00204811, 0x000 },
-    { 0x00000001, 0x002f0230, 0x000 },
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-    { 0x00000001, 0x00210621, 0x000 },
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-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x0004a013, 0x00604411, 0x68d },
-    { 0x0000a013, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x0004a014, 0x00604411, 0x68d },
-    { 0x0000a014, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x0004a015, 0x00604411, 0x68d },
-    { 0x0000a015, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x0004a016, 0x00604411, 0x68d },
-    { 0x0000a016, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x0004a017, 0x00604411, 0x68d },
-    { 0x0000a017, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x00042004, 0x00604411, 0x68d },
-    { 0x0000002c, 0x0080062d, 0x000 },
-    { 0xff000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00000002, 0x00804811, 0x000 },
-    { 0x00000000, 0x0ee00000, 0x63d },
-    { 0x00000030, 0x0020062d, 0x000 },
-    { 0x00000002, 0x00280621, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x63b },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00042004, 0x00604411, 0x68d },
-    { 0x00001000, 0x00200811, 0x000 },
-    { 0x0000002b, 0x00203622, 0x000 },
-    { 0x00000000, 0x00600000, 0x641 },
-    { 0x00000000, 0x00600000, 0x5c9 },
-    { 0x98000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00804811, 0x000 },
-    { 0x00000000, 0xc0600000, 0x641 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x0000a2a4, 0x00204411, 0x000 },
-    { 0x00000022, 0x00204811, 0x000 },
-    { 0x89000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00404811, 0x62d },
-    { 0x97000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x8a000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00404811, 0x62d },
-    { 0x00000000, 0x00600000, 0x65c },
-    { 0x00002010, 0x00204411, 0x000 },
-    { 0x00008000, 0x00204811, 0x000 },
-    { 0x0001a2a4, 0xc0204411, 0x000 },
-    { 0x00000016, 0x00604811, 0x36e },
-    { 0x00002010, 0x00204411, 0x000 },
-    { 0x00010000, 0x00204811, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0000217c, 0x00204411, 0x000 },
-    { 0x09800000, 0x00204811, 0x000 },
-    { 0xffffffff, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x17000000, 0x000 },
-    { 0x0004217f, 0x00604411, 0x68d },
-    { 0x0000001f, 0x00210230, 0x000 },
-    { 0x00000000, 0x14c00000, 0x000 },
-    { 0x00000004, 0x00404c11, 0x656 },
-    { 0x00000000, 0x00400000, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000004, 0x00291e27, 0x000 },
-    { 0x00000017, 0x00803627, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0xfffffffb, 0x00281e27, 0x000 },
-    { 0x00000017, 0x00803627, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000008, 0x00291e27, 0x000 },
-    { 0x00000017, 0x00803627, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0xfffffff7, 0x00281e27, 0x000 },
-    { 0x00000017, 0x00803627, 0x000 },
-    { 0x00002010, 0x00204411, 0x000 },
-    { 0x00008000, 0x00204811, 0x000 },
-    { 0x0001a2a4, 0x00204411, 0x000 },
-    { 0x00000016, 0x00604811, 0x36e },
-    { 0x00002010, 0x00204411, 0x000 },
-    { 0x00010000, 0x00204811, 0x000 },
-    { 0x0000217c, 0x00204411, 0x000 },
-    { 0x01800000, 0x00204811, 0x000 },
-    { 0xffffffff, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x17000000, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0004217f, 0x00604411, 0x68d },
-    { 0x0000001f, 0x00210230, 0x000 },
-    { 0x00000000, 0x14c00000, 0x68c },
-    { 0x00000010, 0x00404c11, 0x672 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x38c00000, 0x000 },
-    { 0x0000001d, 0x00200a2d, 0x000 },
-    { 0x0000001e, 0x00200e2d, 0x000 },
-    { 0x0000001f, 0x0020122d, 0x000 },
-    { 0x00000020, 0x0020162d, 0x000 },
-    { 0x00002169, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204804, 0x000 },
-    { 0x00000000, 0x00204805, 0x000 },
-    { 0x00000000, 0x00204801, 0x000 },
-    { 0xcafebabe, 0x00204811, 0x000 },
-    { 0x00000004, 0x00301224, 0x000 },
-    { 0x00000000, 0x002f0064, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x68b },
-    { 0x00000003, 0x00281a22, 0x000 },
-    { 0x00000008, 0x00221222, 0x000 },
-    { 0xfffff000, 0x00281224, 0x000 },
-    { 0x00000000, 0x002910c4, 0x000 },
-    { 0x0000001f, 0x00403624, 0x000 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x00000000, 0x1ac00000, 0x68d },
-    { 0x9f000000, 0x00204411, 0x000 },
-    { 0xcafebabe, 0x00204811, 0x000 },
-    { 0x00000000, 0x1ae00000, 0x690 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x00000000, 0x1ac00000, 0x692 },
-    { 0x9e000000, 0x00204411, 0x000 },
-    { 0xcafebabe, 0x00204811, 0x000 },
-    { 0x00000000, 0x1ae00000, 0x695 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00001000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001b, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0001a1fd, 0xc0204411, 0x000 },
-    { 0x00000021, 0x00201e2d, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000024, 0x0020222d, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000022, 0x0020222d, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000023, 0x00201e2d, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x00404811, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x01420502, 0x05c00250, 0x000 },
-    { 0x01c30168, 0x043f05c0, 0x000 },
-    { 0x02250209, 0x02500151, 0x000 },
-    { 0x02230245, 0x02a00241, 0x000 },
-    { 0x03d705c0, 0x05c005c0, 0x000 },
-    { 0x0649064a, 0x031f05c0, 0x000 },
-    { 0x05c005c5, 0x03200340, 0x000 },
-    { 0x032a0282, 0x03420334, 0x000 },
-    { 0x05c005c0, 0x05c005c0, 0x000 },
-    { 0x05c00551, 0x05c005c0, 0x000 },
-    { 0x03ba05c0, 0x04bb0344, 0x000 },
-    { 0x049a0450, 0x043d05c0, 0x000 },
-    { 0x04d005c0, 0x044104dd, 0x000 },
-    { 0x04500507, 0x03510375, 0x000 },
-    { 0x05c005c0, 0x05c005c0, 0x000 },
-    { 0x05c005c0, 0x05c005c0, 0x000 },
-    { 0x05c005c0, 0x063f05c7, 0x000 },
-    { 0x05c005c0, 0x000705c0, 0x000 },
-    { 0x05c005c0, 0x05c005c0, 0x000 },
-    { 0x05c005c0, 0x05c005c0, 0x000 },
-    { 0x03f803ed, 0x04080406, 0x000 },
-    { 0x040e040a, 0x040c0410, 0x000 },
-    { 0x041c0418, 0x04240420, 0x000 },
-    { 0x042c0428, 0x04340430, 0x000 },
-    { 0x05c005c0, 0x043805c0, 0x000 },
-    { 0x05c005c0, 0x05c005c0, 0x000 },
-    { 0x05c005c0, 0x05c005c0, 0x000 },
-    { 0x00020679, 0x06970006, 0x000 },
-};
-
-static const u32 RV620_pfp_microcode[] = {
-0xca0400,
-0xa00000,
-0x7e828b,
-0x7c038b,
-0x8001b8,
-0x7c038b,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xc41838,
-0xca2400,
-0xca2800,
-0x9581a8,
-0xc41c3a,
-0xc3c000,
-0xca0800,
-0xca0c00,
-0x7c744b,
-0xc20005,
-0x99c000,
-0xc41c3a,
-0x7c744c,
-0xc0fff0,
-0x042c04,
-0x309002,
-0x7d2500,
-0x351402,
-0x7d350b,
-0x255403,
-0x7cd580,
-0x259c03,
-0x95c004,
-0xd5001b,
-0x7eddc1,
-0x7d9d80,
-0xd6801b,
-0xd5801b,
-0xd4401e,
-0xd5401e,
-0xd6401e,
-0xd6801e,
-0xd4801e,
-0xd4c01e,
-0x9783d3,
-0xd5c01e,
-0xca0800,
-0x80001a,
-0xca0c00,
-0xe4011e,
-0xd4001e,
-0x80000c,
-0xc41838,
-0xe4013e,
-0xd4001e,
-0x80000c,
-0xc41838,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca1800,
-0xd4401e,
-0xd5801e,
-0x800053,
-0xd40075,
-0xd4401e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd48019,
-0xd4c018,
-0xd50017,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xe2001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0xd48060,
-0xd4401e,
-0x800000,
-0xd4801e,
-0xca0800,
-0xd48061,
-0xd4401e,
-0x800000,
-0xd4801e,
-0xca0800,
-0xca0c00,
-0xd4401e,
-0xd48016,
-0xd4c016,
-0xd4801e,
-0x8001b8,
-0xd4c01e,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x948004,
-0xca1400,
-0xe420f3,
-0xd42013,
-0xd56065,
-0xd4e01c,
-0xd5201c,
-0xd5601c,
-0x800000,
-0x062001,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x9483f7,
-0xca1400,
-0xe420f3,
-0x800079,
-0xd42013,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x9883ef,
-0xca1400,
-0xd40064,
-0x80008d,
-0x000000,
-0xc41432,
-0xc61843,
-0xc4082f,
-0x954005,
-0xc40c30,
-0xd4401e,
-0x800000,
-0xee001e,
-0x9583f5,
-0xc41031,
-0xd44033,
-0xd52065,
-0xd4a01c,
-0xd4e01c,
-0xd5201c,
-0xe4015e,
-0xd4001e,
-0x800000,
-0x062001,
-0xca1800,
-0x0a2001,
-0xd60076,
-0xc40836,
-0x988007,
-0xc61045,
-0x950110,
-0xd4001f,
-0xd46062,
-0x800000,
-0xd42062,
-0xcc3835,
-0xcc1433,
-0x8401bb,
-0xd40072,
-0xd5401e,
-0x800000,
-0xee001e,
-0xe2001a,
-0x8401bb,
-0xe2001a,
-0xcc104b,
-0xcc0447,
-0x2c9401,
-0x7d098b,
-0x984005,
-0x7d15cb,
-0xd4001a,
-0x8001b8,
-0xd4006d,
-0x344401,
-0xcc0c48,
-0x98403a,
-0xcc2c4a,
-0x958004,
-0xcc0449,
-0x8001b8,
-0xd4001a,
-0xd4c01a,
-0x282801,
-0x8400f0,
-0xcc1003,
-0x98801b,
-0x04380c,
-0x8400f0,
-0xcc1003,
-0x988017,
-0x043808,
-0x8400f0,
-0xcc1003,
-0x988013,
-0x043804,
-0x8400f0,
-0xcc1003,
-0x988014,
-0xcc104c,
-0x9a8009,
-0xcc144d,
-0x9840dc,
-0xd4006d,
-0xcc1848,
-0xd5001a,
-0xd5401a,
-0x8000c9,
-0xd5801a,
-0x96c0d5,
-0xd4006d,
-0x8001b8,
-0xd4006e,
-0x9ac003,
-0xd4006d,
-0xd4006e,
-0x800000,
-0xec007f,
-0x9ac0cc,
-0xd4006d,
-0x8001b8,
-0xd4006e,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0x7d9103,
-0x7dd583,
-0x7d190c,
-0x35cc1f,
-0x35701f,
-0x7cf0cb,
-0x7cd08b,
-0x880000,
-0x7e8e8b,
-0x95c004,
-0xd4006e,
-0x8001b8,
-0xd4001a,
-0xd4c01a,
-0xcc0803,
-0xcc0c03,
-0xcc1003,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0xcc2403,
-0xcc2803,
-0x35c41f,
-0x36b01f,
-0x7c704b,
-0x34f01f,
-0x7c704b,
-0x35701f,
-0x7c704b,
-0x7d8881,
-0x7dccc1,
-0x7e5101,
-0x7e9541,
-0x7c9082,
-0x7cd4c2,
-0x7c848b,
-0x9ac003,
-0x7c8c8b,
-0x2c8801,
-0x98809e,
-0xd4006d,
-0x98409c,
-0xd4006e,
-0xcc084c,
-0xcc0c4d,
-0xcc1048,
-0xd4801a,
-0xd4c01a,
-0x800101,
-0xd5001a,
-0xcc0832,
-0xd40032,
-0x9482d9,
-0xca0c00,
-0xd4401e,
-0x800000,
-0xd4001e,
-0xe4011e,
-0xd4001e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd4401e,
-0xca1400,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xd5401e,
-0xd54034,
-0x800000,
-0xee001e,
-0x280404,
-0xe2001a,
-0xe2001a,
-0xd4401a,
-0xca3800,
-0xcc0803,
-0xcc0c03,
-0xcc0c03,
-0xcc0c03,
-0x9882bd,
-0x000000,
-0x8401bb,
-0xd7a06f,
-0x800000,
-0xee001f,
-0xca0400,
-0xc2ff00,
-0xcc0834,
-0xc13fff,
-0x7c74cb,
-0x7cc90b,
-0x7d010f,
-0x9902b0,
-0x7c738b,
-0x8401bb,
-0xd7a06f,
-0x800000,
-0xee001f,
-0xca0800,
-0x281900,
-0x7d898b,
-0x958014,
-0x281404,
-0xca0c00,
-0xca1000,
-0xca1c00,
-0xca2400,
-0xe2001f,
-0xd4c01a,
-0xd5001a,
-0xd5401a,
-0xcc1803,
-0xcc2c03,
-0xcc2c03,
-0xcc2c03,
-0x7da58b,
-0x7d9c47,
-0x984297,
-0x000000,
-0x800161,
-0xd4c01a,
-0xd4401e,
-0xd4801e,
-0x800000,
-0xee001e,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0x248c06,
-0x0ccc06,
-0x98c006,
-0xcc104e,
-0x990004,
-0xd40073,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xd4801e,
-0x800000,
-0xee001e,
-0xca0800,
-0xca0c00,
-0x34d018,
-0x251001,
-0x950021,
-0xc17fff,
-0xca1000,
-0xca1400,
-0xca1800,
-0xd4801d,
-0xd4c01d,
-0x7db18b,
-0xc14202,
-0xc2c001,
-0xd5801d,
-0x34dc0e,
-0x7d5d4c,
-0x7f734c,
-0xd7401e,
-0xd5001e,
-0xd5401e,
-0xc14200,
-0xc2c000,
-0x099c01,
-0x31dc10,
-0x7f5f4c,
-0x7f734c,
-0x042802,
-0x7d8380,
-0xd5a86f,
-0xd58066,
-0xd7401e,
-0xec005e,
-0xc82402,
-0xc82402,
-0x8001b8,
-0xd60076,
-0xd4401e,
-0xd4801e,
-0xd4c01e,
-0x800000,
-0xee001e,
-0x800000,
-0xee001f,
-0xd4001f,
-0x800000,
-0xd4001f,
-0xd4001f,
-0x880000,
-0xd4001f,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x010171,
-0x020178,
-0x03008f,
-0x04007f,
-0x050003,
-0x06003f,
-0x070032,
-0x08012c,
-0x090046,
-0x0a0036,
-0x1001b6,
-0x1700a2,
-0x22013a,
-0x230149,
-0x2000b4,
-0x240125,
-0x27004d,
-0x28006a,
-0x2a0060,
-0x2b0052,
-0x2f0065,
-0x320087,
-0x34017f,
-0x3c0156,
-0x3f0072,
-0x41018c,
-0x44012e,
-0x550173,
-0x56017a,
-0x60000b,
-0x610034,
-0x620038,
-0x630038,
-0x640038,
-0x650038,
-0x660038,
-0x670038,
-0x68003a,
-0x690041,
-0x6a0048,
-0x6b0048,
-0x6c0048,
-0x6d0048,
-0x6e0048,
-0x6f0048,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-};
-
-static const u32 RV630_cp_microcode[][3] = {
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x0000ffff, 0x00284621, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x00000000, 0x00e00000, 0x000 },
-    { 0x00010000, 0xc0294620, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00042004, 0x00604411, 0x68a },
-    { 0x00000000, 0x00600000, 0x62e },
-    { 0x00000000, 0x00600000, 0x642 },
-    { 0x00000000, 0xc0200800, 0x000 },
-    { 0x00000f00, 0x00281622, 0x000 },
-    { 0x00000008, 0x00211625, 0x000 },
-    { 0x00000018, 0x00203625, 0x000 },
-    { 0x8d000000, 0x00204411, 0x000 },
-    { 0x00000004, 0x002f0225, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x018 },
-    { 0x00412000, 0x00404811, 0x019 },
-    { 0x00422000, 0x00204811, 0x000 },
-    { 0x8e000000, 0x00204411, 0x000 },
-    { 0x00000028, 0x00204a2d, 0x000 },
-    { 0x90000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204805, 0x000 },
-    { 0x0000000c, 0x00211622, 0x000 },
-    { 0x00000003, 0x00281625, 0x000 },
-    { 0x00000019, 0x00211a22, 0x000 },
-    { 0x00000004, 0x00281a26, 0x000 },
-    { 0x00000000, 0x002914c5, 0x000 },
-    { 0x00000019, 0x00203625, 0x000 },
-    { 0x00000000, 0x003a1402, 0x000 },
-    { 0x00000016, 0x00211625, 0x000 },
-    { 0x00000003, 0x00281625, 0x000 },
-    { 0x00000017, 0x00200e2d, 0x000 },
-    { 0xfffffffc, 0x00280e23, 0x000 },
-    { 0x00000000, 0x002914a3, 0x000 },
-    { 0x00000017, 0x00203625, 0x000 },
-    { 0x00008000, 0x00280e22, 0x000 },
-    { 0x00000007, 0x00220e23, 0x000 },
-    { 0x00000000, 0x0029386e, 0x000 },
-    { 0x20000000, 0x00280e22, 0x000 },
-    { 0x00000006, 0x00210e23, 0x000 },
-    { 0x00000000, 0x0029386e, 0x000 },
-    { 0x00000000, 0x00220222, 0x000 },
-    { 0x00000000, 0x14e00000, 0x038 },
-    { 0x00000000, 0x2ee00000, 0x035 },
-    { 0x00000000, 0x2ce00000, 0x037 },
-    { 0x00000000, 0x00400e2d, 0x039 },
-    { 0x00000008, 0x00200e2d, 0x000 },
-    { 0x00000009, 0x0040122d, 0x046 },
-    { 0x00000001, 0x00400e2d, 0x039 },
-    { 0x00000000, 0xc0200c00, 0x000 },
-    { 0x003ffffc, 0x00281223, 0x000 },
-    { 0x00000002, 0x00221224, 0x000 },
-    { 0x0000001f, 0x00211e23, 0x000 },
-    { 0x00000000, 0x14e00000, 0x03e },
-    { 0x00000008, 0x00401c11, 0x041 },
-    { 0x0000000d, 0x00201e2d, 0x000 },
-    { 0x0000000f, 0x00281e27, 0x000 },
-    { 0x00000003, 0x00221e27, 0x000 },
-    { 0x7fc00000, 0x00281a23, 0x000 },
-    { 0x00000014, 0x00211a26, 0x000 },
-    { 0x00000001, 0x00331a26, 0x000 },
-    { 0x00000008, 0x00221a26, 0x000 },
-    { 0x00000000, 0x00290cc7, 0x000 },
-    { 0x00000027, 0x00203624, 0x000 },
-    { 0x00007f00, 0x00281221, 0x000 },
-    { 0x00001400, 0x002f0224, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x04b },
-    { 0x00000001, 0x00290e23, 0x000 },
-    { 0x0000000e, 0x00203623, 0x000 },
-    { 0x0000e000, 0x00204411, 0x000 },
-    { 0xfff80000, 0x00294a23, 0x000 },
-    { 0x00000000, 0x003a2c02, 0x000 },
-    { 0x00000002, 0x00220e2b, 0x000 },
-    { 0xfc000000, 0x00280e23, 0x000 },
-    { 0x0000000f, 0x00203623, 0x000 },
-    { 0x00001fff, 0x00294a23, 0x000 },
-    { 0x00000027, 0x00204a2d, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000029, 0x00200e2d, 0x000 },
-    { 0x060a0200, 0x00294a23, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000001, 0x00210222, 0x000 },
-    { 0x00000000, 0x14e00000, 0x061 },
-    { 0x00000000, 0x2ee00000, 0x05f },
-    { 0x00000000, 0x2ce00000, 0x05e },
-    { 0x00000000, 0x00400e2d, 0x062 },
-    { 0x00000001, 0x00400e2d, 0x062 },
-    { 0x0000000a, 0x00200e2d, 0x000 },
-    { 0x0000000b, 0x0040122d, 0x06a },
-    { 0x00000000, 0xc0200c00, 0x000 },
-    { 0x003ffffc, 0x00281223, 0x000 },
-    { 0x00000002, 0x00221224, 0x000 },
-    { 0x7fc00000, 0x00281623, 0x000 },
-    { 0x00000014, 0x00211625, 0x000 },
-    { 0x00000001, 0x00331625, 0x000 },
-    { 0x80000000, 0x00280e23, 0x000 },
-    { 0x00000000, 0x00290ca3, 0x000 },
-    { 0x3ffffc00, 0x00290e23, 0x000 },
-    { 0x0000001f, 0x00211e23, 0x000 },
-    { 0x00000000, 0x14e00000, 0x06d },
-    { 0x00000100, 0x00401c11, 0x070 },
-    { 0x0000000d, 0x00201e2d, 0x000 },
-    { 0x000000f0, 0x00281e27, 0x000 },
-    { 0x00000004, 0x00221e27, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000d, 0x00204811, 0x000 },
-    { 0xfffff0ff, 0x00281a30, 0x000 },
-    { 0x0000a028, 0x00204411, 0x000 },
-    { 0x00000000, 0x002948e6, 0x000 },
-    { 0x0000a018, 0x00204411, 0x000 },
-    { 0x3fffffff, 0x00284a23, 0x000 },
-    { 0x0000a010, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204804, 0x000 },
-    { 0x00000030, 0x0020162d, 0x000 },
-    { 0x00000002, 0x00291625, 0x000 },
-    { 0x00000030, 0x00203625, 0x000 },
-    { 0x00000025, 0x0020162d, 0x000 },
-    { 0x00000000, 0x002f00a3, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x083 },
-    { 0x00000026, 0x0020162d, 0x000 },
-    { 0x00000000, 0x002f00a4, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x084 },
-    { 0x00000000, 0x00400000, 0x08a },
-    { 0x00000025, 0x00203623, 0x000 },
-    { 0x00000026, 0x00203624, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000002, 0x00210227, 0x000 },
-    { 0x00000000, 0x14e00000, 0x08a },
-    { 0x00000000, 0x00600000, 0x665 },
-    { 0x00000000, 0x00600000, 0x659 },
-    { 0x00000002, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x08d },
-    { 0x00000012, 0xc0403620, 0x093 },
-    { 0x00000000, 0x2ee00000, 0x091 },
-    { 0x00000000, 0x2ce00000, 0x090 },
-    { 0x00000002, 0x00400e2d, 0x092 },
-    { 0x00000003, 0x00400e2d, 0x092 },
-    { 0x0000000c, 0x00200e2d, 0x000 },
-    { 0x00000012, 0x00203623, 0x000 },
-    { 0x00000003, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x098 },
-    { 0x0000a00c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0404800, 0x0a0 },
-    { 0x0000a00c, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x2ee00000, 0x09e },
-    { 0x00000000, 0x2ce00000, 0x09d },
-    { 0x00000002, 0x00400e2d, 0x09f },
-    { 0x00000003, 0x00400e2d, 0x09f },
-    { 0x0000000c, 0x00200e2d, 0x000 },
-    { 0x00000000, 0x00204803, 0x000 },
-    { 0x00000000, 0x003a0c02, 0x000 },
-    { 0x003f0000, 0x00280e23, 0x000 },
-    { 0x00000010, 0x00210e23, 0x000 },
-    { 0x00000011, 0x00203623, 0x000 },
-    { 0x0000001e, 0x0021022b, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0a7 },
-    { 0x00000016, 0xc0203620, 0x000 },
-    { 0x0000001f, 0x0021022b, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0aa },
-    { 0x00000015, 0xc0203620, 0x000 },
-    { 0x00000008, 0x00210e2b, 0x000 },
-    { 0x0000007f, 0x00280e23, 0x000 },
-    { 0x00000000, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0e1 },
-    { 0x00000000, 0x27000000, 0x000 },
-    { 0x00000000, 0x00600000, 0x2a3 },
-    { 0x00000001, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ae00000, 0x0b3 },
-    { 0x00000000, 0x00600000, 0x13a },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000006, 0x00204811, 0x000 },
-    { 0x0000000c, 0x00221e30, 0x000 },
-    { 0x99800000, 0x00204411, 0x000 },
-    { 0x00000004, 0x0020122d, 0x000 },
-    { 0x00000008, 0x00221224, 0x000 },
-    { 0x00000010, 0x00201811, 0x000 },
-    { 0x00000000, 0x00291ce4, 0x000 },
-    { 0x00000000, 0x00604807, 0x12f },
-    { 0x9b000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204802, 0x000 },
-    { 0x9c000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x0033146f, 0x000 },
-    { 0x00000001, 0x00333e23, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0x00203c05, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000e, 0x00204811, 0x000 },
-    { 0x00000000, 0x00201010, 0x000 },
-    { 0x0000e007, 0x00204411, 0x000 },
-    { 0x0000000f, 0x0021022b, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0cb },
-    { 0x00f8ff08, 0x00204811, 0x000 },
-    { 0x98000000, 0x00404811, 0x0dc },
-    { 0x000000f0, 0x00280e22, 0x000 },
-    { 0x000000a0, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x0da },
-    { 0x00000011, 0x00200e2d, 0x000 },
-    { 0x00000001, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0d5 },
-    { 0x00000002, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0d4 },
-    { 0x00003f00, 0x00400c11, 0x0d6 },
-    { 0x00001f00, 0x00400c11, 0x0d6 },
-    { 0x00000f00, 0x00200c11, 0x000 },
-    { 0x00380009, 0x00294a23, 0x000 },
-    { 0x3f000000, 0x00280e2b, 0x000 },
-    { 0x00000002, 0x00220e23, 0x000 },
-    { 0x00000007, 0x00494a23, 0x0dc },
-    { 0x00380f09, 0x00204811, 0x000 },
-    { 0x68000007, 0x00204811, 0x000 },
-    { 0x00000008, 0x00214a27, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x060a0200, 0x00294a24, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000a202, 0x00204411, 0x000 },
-    { 0x00ff0000, 0x00280e22, 0x000 },
-    { 0x00000080, 0x00294a23, 0x000 },
-    { 0x00000027, 0x00200e2d, 0x000 },
-    { 0x00000026, 0x0020122d, 0x000 },
-    { 0x00000000, 0x002f0083, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0ea },
-    { 0x00000000, 0x00600000, 0x65f },
-    { 0x00000000, 0x00400000, 0x0eb },
-    { 0x00000000, 0x00600000, 0x662 },
-    { 0x00000007, 0x0020222d, 0x000 },
-    { 0x00000005, 0x00220e22, 0x000 },
-    { 0x00100000, 0x00280e23, 0x000 },
-    { 0x00000000, 0x00292068, 0x000 },
-    { 0x00000000, 0x003a0c02, 0x000 },
-    { 0x000000ef, 0x00280e23, 0x000 },
-    { 0x00000000, 0x00292068, 0x000 },
-    { 0x00000017, 0x00200e2d, 0x000 },
-    { 0x00000003, 0x00210223, 0x000 },
-    { 0x00000000, 0x14e00000, 0x0f8 },
-    { 0x0000000b, 0x00210228, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0f8 },
-    { 0x00000400, 0x00292228, 0x000 },
-    { 0x00000014, 0x00203628, 0x000 },
-    { 0x0000001c, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0fd },
-    { 0x0000a30c, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000001e, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x10b },
-    { 0x0000a30f, 0x00204411, 0x000 },
-    { 0x00000011, 0x00200e2d, 0x000 },
-    { 0x00000001, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x104 },
-    { 0xffffffff, 0x00404811, 0x10b },
-    { 0x00000002, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x107 },
-    { 0x0000ffff, 0x00404811, 0x10b },
-    { 0x00000004, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x10a },
-    { 0x000000ff, 0x00404811, 0x10b },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0002c400, 0x00204411, 0x000 },
-    { 0x0000001f, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x112 },
-    { 0x00000010, 0x40210e20, 0x000 },
-    { 0x00000013, 0x00203623, 0x000 },
-    { 0x00000018, 0x40224a20, 0x000 },
-    { 0x00000010, 0xc0424a20, 0x114 },
-    { 0x00000000, 0x00200c11, 0x000 },
-    { 0x00000013, 0x00203623, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000000a, 0x00201011, 0x000 },
-    { 0x00000000, 0x002f0224, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x11b },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000001, 0x00531224, 0x117 },
-    { 0xffbfffff, 0x00283a2e, 0x000 },
-    { 0x0000001b, 0x00210222, 0x000 },
-    { 0x00000000, 0x14c00000, 0x12e },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000d, 0x00204811, 0x000 },
-    { 0x00000018, 0x00220e30, 0x000 },
-    { 0xfc000000, 0x00280e23, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000e, 0x00204811, 0x000 },
-    { 0x00000000, 0x00201010, 0x000 },
-    { 0x0000e00e, 0x00204411, 0x000 },
-    { 0x07f8ff08, 0x00204811, 0x000 },
-    { 0x00000000, 0x00294a23, 0x000 },
-    { 0x0000001c, 0x00201e2d, 0x000 },
-    { 0x00000008, 0x00214a27, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x060a0200, 0x00294a24, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0000217c, 0x00204411, 0x000 },
-    { 0x00800000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204806, 0x000 },
-    { 0x00000008, 0x00214a27, 0x000 },
-    { 0x00000000, 0x17000000, 0x000 },
-    { 0x0004217f, 0x00604411, 0x68a },
-    { 0x0000001f, 0x00210230, 0x000 },
-    { 0x00000000, 0x14c00000, 0x689 },
-    { 0x00000004, 0x00404c11, 0x135 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x000021f8, 0x00204411, 0x000 },
-    { 0x0000001c, 0x00204811, 0x000 },
-    { 0x000421f9, 0x00604411, 0x68a },
-    { 0x00000011, 0x00210230, 0x000 },
-    { 0x00000000, 0x14e00000, 0x13c },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x00000000, 0x00600000, 0x160 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x00000010, 0xc0211220, 0x000 },
-    { 0x0000ffff, 0x40280620, 0x000 },
-    { 0x00000010, 0xc0210a20, 0x000 },
-    { 0x00000000, 0x00341461, 0x000 },
-    { 0x00000000, 0x00741882, 0x2bb },
-    { 0x0001a1fd, 0x00604411, 0x2e0 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x147 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00600000, 0x160 },
-    { 0x00000010, 0x40210e20, 0x000 },
-    { 0x0000ffff, 0xc0281220, 0x000 },
-    { 0x00000010, 0x40211620, 0x000 },
-    { 0x0000ffff, 0xc0681a20, 0x2bb },
-    { 0x0001a1fd, 0x00604411, 0x2e0 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x158 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000001, 0x00300a2f, 0x000 },
-    { 0x00000001, 0x00210a22, 0x000 },
-    { 0x00000003, 0x00384a22, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001a, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00804811, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600000, 0x18f },
-    { 0x00000000, 0x00600000, 0x1a0 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00202c08, 0x000 },
-    { 0x00000000, 0x00202411, 0x000 },
-    { 0x00000000, 0x00202811, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x00000016, 0x00204811, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x93800000, 0x00204411, 0x000 },
-    { 0x00000002, 0x00221e29, 0x000 },
-    { 0x00000000, 0x007048eb, 0x19c },
-    { 0x00000000, 0x00600000, 0x2bb },
-    { 0x00000001, 0x40330620, 0x000 },
-    { 0x00000000, 0xc0302409, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00600000, 0x2a3 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ae00000, 0x181 },
-    { 0x00000000, 0x00600000, 0x13a },
-    { 0x00000000, 0x00400000, 0x186 },
-    { 0x95000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x186 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000001, 0x00530621, 0x182 },
-    { 0x92000000, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0604800, 0x197 },
-    { 0x0001a1fd, 0x00204411, 0x000 },
-    { 0x00000011, 0x0020062d, 0x000 },
-    { 0x00000000, 0x0078042a, 0x2fb },
-    { 0x00000000, 0x00202809, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x174 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000210, 0x00600411, 0x315 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x194 },
-    { 0x00000015, 0xc0203620, 0x000 },
-    { 0x00000016, 0xc0203620, 0x000 },
-    { 0x3f800000, 0x00200411, 0x000 },
-    { 0x46000000, 0x00600811, 0x1b2 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x19b },
-    { 0x00000001, 0x00804811, 0x000 },
-    { 0x00000021, 0x00804811, 0x000 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x00000010, 0xc0211220, 0x000 },
-    { 0x0000ffff, 0x40281620, 0x000 },
-    { 0x00000010, 0xc0811a20, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000006, 0x00204811, 0x000 },
-    { 0x00000008, 0x00221e30, 0x000 },
-    { 0x00000029, 0x00201a2d, 0x000 },
-    { 0x0000e000, 0x00204411, 0x000 },
-    { 0xfffbff09, 0x00204811, 0x000 },
-    { 0x0000000f, 0x0020222d, 0x000 },
-    { 0x00001fff, 0x00294a28, 0x000 },
-    { 0x00000006, 0x0020222d, 0x000 },
-    { 0x00000000, 0x002920e8, 0x000 },
-    { 0x00000000, 0x00204808, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x060a0200, 0x00294a26, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000100, 0x00201811, 0x000 },
-    { 0x00000008, 0x00621e28, 0x12f },
-    { 0x00000008, 0x00822228, 0x000 },
-    { 0x0002c000, 0x00204411, 0x000 },
-    { 0x00000015, 0x00600e2d, 0x1bd },
-    { 0x00000016, 0x00600e2d, 0x1bd },
-    { 0x0000c008, 0x00204411, 0x000 },
-    { 0x00000017, 0x00200e2d, 0x000 },
-    { 0x00000000, 0x14c00000, 0x1b9 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00204801, 0x000 },
-    { 0x39000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00804802, 0x000 },
-    { 0x00000018, 0x00202e2d, 0x000 },
-    { 0x00000000, 0x003b0d63, 0x000 },
-    { 0x00000008, 0x00224a23, 0x000 },
-    { 0x00000010, 0x00224a23, 0x000 },
-    { 0x00000018, 0x00224a23, 0x000 },
-    { 0x00000000, 0x00804803, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00001000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x00000007, 0x0021062f, 0x000 },
-    { 0x00000013, 0x00200a2d, 0x000 },
-    { 0x00000001, 0x00202c11, 0x000 },
-    { 0x0000ffff, 0x40282220, 0x000 },
-    { 0x0000000f, 0x00262228, 0x000 },
-    { 0x00000010, 0x40212620, 0x000 },
-    { 0x0000000f, 0x00262629, 0x000 },
-    { 0x00000000, 0x00202802, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001b, 0x00204811, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x1e0 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000081, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00000080, 0x00201c11, 0x000 },
-    { 0x00000000, 0x002f0227, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x1dc },
-    { 0x00000000, 0x00600000, 0x1e9 },
-    { 0x00000001, 0x00531e27, 0x1d8 },
-    { 0x00000001, 0x00202c11, 0x000 },
-    { 0x0000001f, 0x00280a22, 0x000 },
-    { 0x0000001f, 0x00282a2a, 0x000 },
-    { 0x00000001, 0x00530621, 0x1d1 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000002, 0x00304a2f, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00000001, 0x00301e2f, 0x000 },
-    { 0x00000000, 0x002f0227, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00600000, 0x1e9 },
-    { 0x00000001, 0x00531e27, 0x1e5 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x0000000f, 0x00260e23, 0x000 },
-    { 0x00000010, 0xc0211220, 0x000 },
-    { 0x0000000f, 0x00261224, 0x000 },
-    { 0x00000000, 0x00201411, 0x000 },
-    { 0x00000000, 0x00601811, 0x2bb },
-    { 0x0001a1fd, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f022b, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x1f8 },
-    { 0x00000010, 0x00221628, 0x000 },
-    { 0xffff0000, 0x00281625, 0x000 },
-    { 0x0000ffff, 0x00281a29, 0x000 },
-    { 0x00000000, 0x002948c5, 0x000 },
-    { 0x00000000, 0x0020480a, 0x000 },
-    { 0x00000000, 0x00202c11, 0x000 },
-    { 0x00000010, 0x00221623, 0x000 },
-    { 0xffff0000, 0x00281625, 0x000 },
-    { 0x0000ffff, 0x00281a24, 0x000 },
-    { 0x00000000, 0x002948c5, 0x000 },
-    { 0x00000000, 0x00731503, 0x205 },
-    { 0x00000000, 0x00201805, 0x000 },
-    { 0x00000000, 0x00731524, 0x205 },
-    { 0x00000000, 0x002d14c5, 0x000 },
-    { 0x00000000, 0x003008a2, 0x000 },
-    { 0x00000000, 0x00204802, 0x000 },
-    { 0x00000000, 0x00202802, 0x000 },
-    { 0x00000000, 0x00202003, 0x000 },
-    { 0x00000000, 0x00802404, 0x000 },
-    { 0x0000000f, 0x00210225, 0x000 },
-    { 0x00000000, 0x14c00000, 0x689 },
-    { 0x00000000, 0x002b1405, 0x000 },
-    { 0x00000001, 0x00901625, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001a, 0x00294a22, 0x000 },
-    { 0x00000000, 0xc0200000, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00384a21, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0000ffff, 0x40281220, 0x000 },
-    { 0x00000010, 0xc0211a20, 0x000 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x00000010, 0xc0211620, 0x000 },
-    { 0x00000000, 0x00741465, 0x2bb },
-    { 0x0001a1fd, 0x00604411, 0x2e0 },
-    { 0x00000001, 0x00330621, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x219 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x212 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000000, 0x00600000, 0x642 },
-    { 0x00000000, 0x0040040f, 0x213 },
-    { 0x00000000, 0x00600000, 0x62e },
-    { 0x00000000, 0x00600000, 0x642 },
-    { 0x00000210, 0x00600411, 0x315 },
-    { 0x00000000, 0x00600000, 0x1a0 },
-    { 0x00000000, 0x00600000, 0x19c },
-    { 0x00000000, 0x00600000, 0x2bb },
-    { 0x00000000, 0x00600000, 0x2a3 },
-    { 0x93800000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204808, 0x000 },
-    { 0x00000000, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ae00000, 0x232 },
-    { 0x00000000, 0x00600000, 0x13a },
-    { 0x00000000, 0x00400000, 0x236 },
-    { 0x95000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x236 },
-    { 0x00000000, 0xc0404800, 0x233 },
-    { 0x92000000, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x00000016, 0x00204811, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0001a1fd, 0x00204411, 0x000 },
-    { 0x00000000, 0x00600411, 0x2fb },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000000, 0x00600000, 0x62e },
-    { 0x0000a00c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0404800, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000018, 0x40210a20, 0x000 },
-    { 0x00000003, 0x002f0222, 0x000 },
-    { 0x00000000, 0x0ae00000, 0x24c },
-    { 0x00000014, 0x0020222d, 0x000 },
-    { 0x00080101, 0x00292228, 0x000 },
-    { 0x00000014, 0x00203628, 0x000 },
-    { 0x0000a30c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0404800, 0x251 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000010, 0x00600411, 0x315 },
-    { 0x3f800000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x00000000, 0x00600000, 0x27c },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000001, 0x00211e27, 0x000 },
-    { 0x00000000, 0x14e00000, 0x26a },
-    { 0x00000012, 0x00201e2d, 0x000 },
-    { 0x0000ffff, 0x00281e27, 0x000 },
-    { 0x00000000, 0x00341c27, 0x000 },
-    { 0x00000000, 0x12c00000, 0x25f },
-    { 0x00000000, 0x00201c11, 0x000 },
-    { 0x00000000, 0x002f00e5, 0x000 },
-    { 0x00000000, 0x08c00000, 0x262 },
-    { 0x00000000, 0x00201407, 0x000 },
-    { 0x00000012, 0x00201e2d, 0x000 },
-    { 0x00000010, 0x00211e27, 0x000 },
-    { 0x00000000, 0x00341c47, 0x000 },
-    { 0x00000000, 0x12c00000, 0x267 },
-    { 0x00000000, 0x00201c11, 0x000 },
-    { 0x00000000, 0x002f00e6, 0x000 },
-    { 0x00000000, 0x08c00000, 0x26a },
-    { 0x00000000, 0x00201807, 0x000 },
-    { 0x00000000, 0x00600000, 0x2c1 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x00000000, 0x00342023, 0x000 },
-    { 0x00000000, 0x12c00000, 0x272 },
-    { 0x00000000, 0x00342044, 0x000 },
-    { 0x00000000, 0x12c00000, 0x271 },
-    { 0x00000016, 0x00404811, 0x276 },
-    { 0x00000018, 0x00404811, 0x276 },
-    { 0x00000000, 0x00342044, 0x000 },
-    { 0x00000000, 0x12c00000, 0x275 },
-    { 0x00000017, 0x00404811, 0x276 },
-    { 0x00000019, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0001a1fd, 0x00604411, 0x2e9 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x256 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000010, 0x40210620, 0x000 },
-    { 0x0000ffff, 0xc0280a20, 0x000 },
-    { 0x00000010, 0x40210e20, 0x000 },
-    { 0x0000ffff, 0xc0281220, 0x000 },
-    { 0x00000010, 0x40211620, 0x000 },
-    { 0x0000ffff, 0xc0881a20, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00042004, 0x00604411, 0x68a },
-    { 0x00000000, 0x00600000, 0x62e },
-    { 0x00000000, 0xc0600000, 0x2a3 },
-    { 0x00000005, 0x00200a2d, 0x000 },
-    { 0x00000008, 0x00220a22, 0x000 },
-    { 0x0000002b, 0x00201a2d, 0x000 },
-    { 0x0000001c, 0x00201e2d, 0x000 },
-    { 0x00007000, 0x00281e27, 0x000 },
-    { 0x00000000, 0x00311ce6, 0x000 },
-    { 0x0000002a, 0x00201a2d, 0x000 },
-    { 0x0000000c, 0x00221a26, 0x000 },
-    { 0x00000000, 0x002f00e6, 0x000 },
-    { 0x00000000, 0x06e00000, 0x292 },
-    { 0x00000000, 0x00201c11, 0x000 },
-    { 0x00000000, 0x00200c11, 0x000 },
-    { 0x0000002b, 0x00203623, 0x000 },
-    { 0x00000010, 0x00201811, 0x000 },
-    { 0x00000000, 0x00691ce2, 0x12f },
-    { 0x93800000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204807, 0x000 },
-    { 0x95000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x29d },
-    { 0x00000001, 0x00333e2f, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x92000000, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x0000001c, 0x00403627, 0x000 },
-    { 0x0000000c, 0xc0220a20, 0x000 },
-    { 0x00000029, 0x00203622, 0x000 },
-    { 0x00000028, 0xc0403620, 0x000 },
-    { 0x0000a2a4, 0x00204411, 0x000 },
-    { 0x00000009, 0x00204811, 0x000 },
-    { 0xa1000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00804811, 0x000 },
-    { 0x00000021, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x002c1ce3, 0x000 },
-    { 0x00000021, 0x00203627, 0x000 },
-    { 0x00000022, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x002c1ce4, 0x000 },
-    { 0x00000022, 0x00203627, 0x000 },
-    { 0x00000023, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x003120a3, 0x000 },
-    { 0x00000000, 0x002d1d07, 0x000 },
-    { 0x00000023, 0x00203627, 0x000 },
-    { 0x00000024, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x003120c4, 0x000 },
-    { 0x00000000, 0x002d1d07, 0x000 },
-    { 0x00000024, 0x00803627, 0x000 },
-    { 0x00000021, 0x00203623, 0x000 },
-    { 0x00000022, 0x00203624, 0x000 },
-    { 0x00000000, 0x00311ca3, 0x000 },
-    { 0x00000023, 0x00203627, 0x000 },
-    { 0x00000000, 0x00311cc4, 0x000 },
-    { 0x00000024, 0x00803627, 0x000 },
-    { 0x0000001a, 0x00203627, 0x000 },
-    { 0x0000001b, 0x00203628, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000002, 0x00210227, 0x000 },
-    { 0x00000000, 0x14c00000, 0x2dc },
-    { 0x00000000, 0x00400000, 0x2d9 },
-    { 0x0000001a, 0x00203627, 0x000 },
-    { 0x0000001b, 0x00203628, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000002, 0x00210227, 0x000 },
-    { 0x00000000, 0x14e00000, 0x2d9 },
-    { 0x00000003, 0x00210227, 0x000 },
-    { 0x00000000, 0x14e00000, 0x2dc },
-    { 0x00000023, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x002e00e1, 0x000 },
-    { 0x00000000, 0x02c00000, 0x2dc },
-    { 0x00000021, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x003120a1, 0x000 },
-    { 0x00000000, 0x002e00e8, 0x000 },
-    { 0x00000000, 0x06c00000, 0x2dc },
-    { 0x00000024, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x002e00e2, 0x000 },
-    { 0x00000000, 0x02c00000, 0x2dc },
-    { 0x00000022, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x003120c2, 0x000 },
-    { 0x00000000, 0x002e00e8, 0x000 },
-    { 0x00000000, 0x06c00000, 0x2dc },
-    { 0x00000000, 0x00600000, 0x665 },
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-    { 0x00000000, 0x00400000, 0x2de },
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-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000001, 0x00220a21, 0x000 },
-    { 0x00000000, 0x003308a2, 0x000 },
-    { 0x00000010, 0x00221e22, 0x000 },
-    { 0x00000010, 0x00212222, 0x000 },
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-    { 0x00000001, 0x00220a21, 0x000 },
-    { 0x00000000, 0x003008a2, 0x000 },
-    { 0x00000010, 0x00221e22, 0x000 },
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-    { 0x00000001, 0x00220a22, 0x000 },
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-    { 0x00000010, 0x00221e22, 0x000 },
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-    { 0x00000000, 0xc0204800, 0x000 },
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-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x40204800, 0x000 },
-    { 0x00000001, 0x40304a20, 0x000 },
-    { 0x00000002, 0xc0304a20, 0x000 },
-    { 0x00000001, 0x00530a22, 0x34b },
-    { 0x0000003f, 0xc0280a20, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
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-    { 0x00000049, 0x00201811, 0x000 },
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-    { 0x00000001, 0x00331a26, 0x000 },
-    { 0x00000000, 0x002f0226, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x370 },
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-    { 0x00000001, 0x00204811, 0x000 },
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-    { 0x00000001, 0x00204811, 0x000 },
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-    { 0x00000033, 0x00204a2d, 0x000 },
-    { 0x0000a2ba, 0x00204411, 0x000 },
-    { 0x00000034, 0x00204a2d, 0x000 },
-    { 0x0000a2be, 0x00204411, 0x000 },
-    { 0x00000035, 0x00204a2d, 0x000 },
-    { 0x0000a2c2, 0x00204411, 0x000 },
-    { 0x00000036, 0x00204a2d, 0x000 },
-    { 0x00000030, 0x0020062d, 0x000 },
-    { 0x000001ff, 0x00280621, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x628 },
-    { 0x00000000, 0x00210221, 0x000 },
-    { 0x00000000, 0x14c00000, 0x60b },
-    { 0x0004a003, 0x00604411, 0x68a },
-    { 0x0000a003, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x00000001, 0x00210621, 0x000 },
-    { 0x00000000, 0x14c00000, 0x610 },
-    { 0x0004a010, 0x00604411, 0x68a },
-    { 0x0000a010, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x00000001, 0x00210621, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x628 },
-    { 0x0004a011, 0x00604411, 0x68a },
-    { 0x0000a011, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x0004a012, 0x00604411, 0x68a },
-    { 0x0000a012, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x0004a013, 0x00604411, 0x68a },
-    { 0x0000a013, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x0004a014, 0x00604411, 0x68a },
-    { 0x0000a014, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x0004a015, 0x00604411, 0x68a },
-    { 0x0000a015, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x0004a016, 0x00604411, 0x68a },
-    { 0x0000a016, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x0004a017, 0x00604411, 0x68a },
-    { 0x0000a017, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x00042004, 0x00604411, 0x68a },
-    { 0x0000002c, 0x0080062d, 0x000 },
-    { 0xff000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00000002, 0x00804811, 0x000 },
-    { 0x00000000, 0x0ee00000, 0x63a },
-    { 0x00000030, 0x0020062d, 0x000 },
-    { 0x00000002, 0x00280621, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x638 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00042004, 0x00604411, 0x68a },
-    { 0x00001000, 0x00200811, 0x000 },
-    { 0x0000002b, 0x00203622, 0x000 },
-    { 0x00000000, 0x00600000, 0x63e },
-    { 0x00000000, 0x00600000, 0x5c6 },
-    { 0x98000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00804811, 0x000 },
-    { 0x00000000, 0xc0600000, 0x63e },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x0000a2a4, 0x00204411, 0x000 },
-    { 0x00000022, 0x00204811, 0x000 },
-    { 0x89000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00404811, 0x62a },
-    { 0x97000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x8a000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00404811, 0x62a },
-    { 0x00000000, 0x00600000, 0x659 },
-    { 0x00002010, 0x00204411, 0x000 },
-    { 0x00008000, 0x00204811, 0x000 },
-    { 0x0001a2a4, 0xc0204411, 0x000 },
-    { 0x00000016, 0x00604811, 0x36e },
-    { 0x00002010, 0x00204411, 0x000 },
-    { 0x00010000, 0x00204811, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0000217c, 0x00204411, 0x000 },
-    { 0x09800000, 0x00204811, 0x000 },
-    { 0xffffffff, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x17000000, 0x000 },
-    { 0x0004217f, 0x00604411, 0x68a },
-    { 0x0000001f, 0x00210230, 0x000 },
-    { 0x00000000, 0x14c00000, 0x000 },
-    { 0x00000004, 0x00404c11, 0x653 },
-    { 0x00000000, 0x00400000, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000004, 0x00291e27, 0x000 },
-    { 0x00000017, 0x00803627, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0xfffffffb, 0x00281e27, 0x000 },
-    { 0x00000017, 0x00803627, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000008, 0x00291e27, 0x000 },
-    { 0x00000017, 0x00803627, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0xfffffff7, 0x00281e27, 0x000 },
-    { 0x00000017, 0x00803627, 0x000 },
-    { 0x00002010, 0x00204411, 0x000 },
-    { 0x00008000, 0x00204811, 0x000 },
-    { 0x0001a2a4, 0x00204411, 0x000 },
-    { 0x00000016, 0x00604811, 0x36e },
-    { 0x00002010, 0x00204411, 0x000 },
-    { 0x00010000, 0x00204811, 0x000 },
-    { 0x0000217c, 0x00204411, 0x000 },
-    { 0x01800000, 0x00204811, 0x000 },
-    { 0xffffffff, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x17000000, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0004217f, 0x00604411, 0x68a },
-    { 0x0000001f, 0x00210230, 0x000 },
-    { 0x00000000, 0x14c00000, 0x689 },
-    { 0x00000010, 0x00404c11, 0x66f },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x38c00000, 0x000 },
-    { 0x0000001d, 0x00200a2d, 0x000 },
-    { 0x0000001e, 0x00200e2d, 0x000 },
-    { 0x0000001f, 0x0020122d, 0x000 },
-    { 0x00000020, 0x0020162d, 0x000 },
-    { 0x00002169, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204804, 0x000 },
-    { 0x00000000, 0x00204805, 0x000 },
-    { 0x00000000, 0x00204801, 0x000 },
-    { 0xcafebabe, 0x00204811, 0x000 },
-    { 0x00000004, 0x00301224, 0x000 },
-    { 0x00000000, 0x002f0064, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x688 },
-    { 0x00000003, 0x00281a22, 0x000 },
-    { 0x00000008, 0x00221222, 0x000 },
-    { 0xfffff000, 0x00281224, 0x000 },
-    { 0x00000000, 0x002910c4, 0x000 },
-    { 0x0000001f, 0x00403624, 0x000 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x00000000, 0x1ac00000, 0x68a },
-    { 0x9f000000, 0x00204411, 0x000 },
-    { 0xcafebabe, 0x00204811, 0x000 },
-    { 0x00000000, 0x1ae00000, 0x68d },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x00000000, 0x1ac00000, 0x68f },
-    { 0x9e000000, 0x00204411, 0x000 },
-    { 0xcafebabe, 0x00204811, 0x000 },
-    { 0x00000000, 0x1ae00000, 0x692 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00001000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001b, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0001a1fd, 0xc0204411, 0x000 },
-    { 0x00000021, 0x00201e2d, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000024, 0x0020222d, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000022, 0x0020222d, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000023, 0x00201e2d, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x00404811, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x014204ff, 0x05bd0250, 0x000 },
-    { 0x01c30168, 0x043f05bd, 0x000 },
-    { 0x02250209, 0x02500151, 0x000 },
-    { 0x02230245, 0x02a00241, 0x000 },
-    { 0x03d705bd, 0x05bd05bd, 0x000 },
-    { 0x06460647, 0x031f05bd, 0x000 },
-    { 0x05bd05c2, 0x03200340, 0x000 },
-    { 0x032a0282, 0x03420334, 0x000 },
-    { 0x05bd05bd, 0x05bd05bd, 0x000 },
-    { 0x05bd054e, 0x05bd05bd, 0x000 },
-    { 0x03ba05bd, 0x04b80344, 0x000 },
-    { 0x0497044d, 0x043d05bd, 0x000 },
-    { 0x04cd05bd, 0x044104da, 0x000 },
-    { 0x044d0504, 0x03510375, 0x000 },
-    { 0x05bd05bd, 0x05bd05bd, 0x000 },
-    { 0x05bd05bd, 0x05bd05bd, 0x000 },
-    { 0x05bd05bd, 0x063c05c4, 0x000 },
-    { 0x05bd05bd, 0x000705bd, 0x000 },
-    { 0x05bd05bd, 0x05bd05bd, 0x000 },
-    { 0x05bd05bd, 0x05bd05bd, 0x000 },
-    { 0x03f803ed, 0x04080406, 0x000 },
-    { 0x040e040a, 0x040c0410, 0x000 },
-    { 0x041c0418, 0x04240420, 0x000 },
-    { 0x042c0428, 0x04340430, 0x000 },
-    { 0x05bd05bd, 0x043805bd, 0x000 },
-    { 0x05bd05bd, 0x05bd05bd, 0x000 },
-    { 0x05bd05bd, 0x05bd05bd, 0x000 },
-    { 0x00020676, 0x06940006, 0x000 },
-};
-
-static const u32 RV630_pfp_microcode[] = {
-0xca0400,
-0xa00000,
-0x7e828b,
-0x7c038b,
-0x8001b8,
-0x7c038b,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xc41838,
-0xca2400,
-0xca2800,
-0x9581a8,
-0xc41c3a,
-0xc3c000,
-0xca0800,
-0xca0c00,
-0x7c744b,
-0xc20005,
-0x99c000,
-0xc41c3a,
-0x7c744c,
-0xc0fff0,
-0x042c04,
-0x309002,
-0x7d2500,
-0x351402,
-0x7d350b,
-0x255403,
-0x7cd580,
-0x259c03,
-0x95c004,
-0xd5001b,
-0x7eddc1,
-0x7d9d80,
-0xd6801b,
-0xd5801b,
-0xd4401e,
-0xd5401e,
-0xd6401e,
-0xd6801e,
-0xd4801e,
-0xd4c01e,
-0x9783d3,
-0xd5c01e,
-0xca0800,
-0x80001a,
-0xca0c00,
-0xe4011e,
-0xd4001e,
-0x80000c,
-0xc41838,
-0xe4013e,
-0xd4001e,
-0x80000c,
-0xc41838,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca1800,
-0xd4401e,
-0xd5801e,
-0x800053,
-0xd40075,
-0xd4401e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd48019,
-0xd4c018,
-0xd50017,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xe2001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0xd48060,
-0xd4401e,
-0x800000,
-0xd4801e,
-0xca0800,
-0xd48061,
-0xd4401e,
-0x800000,
-0xd4801e,
-0xca0800,
-0xca0c00,
-0xd4401e,
-0xd48016,
-0xd4c016,
-0xd4801e,
-0x8001b8,
-0xd4c01e,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x948004,
-0xca1400,
-0xe420f3,
-0xd42013,
-0xd56065,
-0xd4e01c,
-0xd5201c,
-0xd5601c,
-0x800000,
-0x062001,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x9483f7,
-0xca1400,
-0xe420f3,
-0x800079,
-0xd42013,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x9883ef,
-0xca1400,
-0xd40064,
-0x80008d,
-0x000000,
-0xc41432,
-0xc61843,
-0xc4082f,
-0x954005,
-0xc40c30,
-0xd4401e,
-0x800000,
-0xee001e,
-0x9583f5,
-0xc41031,
-0xd44033,
-0xd52065,
-0xd4a01c,
-0xd4e01c,
-0xd5201c,
-0xe4015e,
-0xd4001e,
-0x800000,
-0x062001,
-0xca1800,
-0x0a2001,
-0xd60076,
-0xc40836,
-0x988007,
-0xc61045,
-0x950110,
-0xd4001f,
-0xd46062,
-0x800000,
-0xd42062,
-0xcc3835,
-0xcc1433,
-0x8401bb,
-0xd40072,
-0xd5401e,
-0x800000,
-0xee001e,
-0xe2001a,
-0x8401bb,
-0xe2001a,
-0xcc104b,
-0xcc0447,
-0x2c9401,
-0x7d098b,
-0x984005,
-0x7d15cb,
-0xd4001a,
-0x8001b8,
-0xd4006d,
-0x344401,
-0xcc0c48,
-0x98403a,
-0xcc2c4a,
-0x958004,
-0xcc0449,
-0x8001b8,
-0xd4001a,
-0xd4c01a,
-0x282801,
-0x8400f0,
-0xcc1003,
-0x98801b,
-0x04380c,
-0x8400f0,
-0xcc1003,
-0x988017,
-0x043808,
-0x8400f0,
-0xcc1003,
-0x988013,
-0x043804,
-0x8400f0,
-0xcc1003,
-0x988014,
-0xcc104c,
-0x9a8009,
-0xcc144d,
-0x9840dc,
-0xd4006d,
-0xcc1848,
-0xd5001a,
-0xd5401a,
-0x8000c9,
-0xd5801a,
-0x96c0d5,
-0xd4006d,
-0x8001b8,
-0xd4006e,
-0x9ac003,
-0xd4006d,
-0xd4006e,
-0x800000,
-0xec007f,
-0x9ac0cc,
-0xd4006d,
-0x8001b8,
-0xd4006e,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0x7d9103,
-0x7dd583,
-0x7d190c,
-0x35cc1f,
-0x35701f,
-0x7cf0cb,
-0x7cd08b,
-0x880000,
-0x7e8e8b,
-0x95c004,
-0xd4006e,
-0x8001b8,
-0xd4001a,
-0xd4c01a,
-0xcc0803,
-0xcc0c03,
-0xcc1003,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0xcc2403,
-0xcc2803,
-0x35c41f,
-0x36b01f,
-0x7c704b,
-0x34f01f,
-0x7c704b,
-0x35701f,
-0x7c704b,
-0x7d8881,
-0x7dccc1,
-0x7e5101,
-0x7e9541,
-0x7c9082,
-0x7cd4c2,
-0x7c848b,
-0x9ac003,
-0x7c8c8b,
-0x2c8801,
-0x98809e,
-0xd4006d,
-0x98409c,
-0xd4006e,
-0xcc084c,
-0xcc0c4d,
-0xcc1048,
-0xd4801a,
-0xd4c01a,
-0x800101,
-0xd5001a,
-0xcc0832,
-0xd40032,
-0x9482d9,
-0xca0c00,
-0xd4401e,
-0x800000,
-0xd4001e,
-0xe4011e,
-0xd4001e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd4401e,
-0xca1400,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xd5401e,
-0xd54034,
-0x800000,
-0xee001e,
-0x280404,
-0xe2001a,
-0xe2001a,
-0xd4401a,
-0xca3800,
-0xcc0803,
-0xcc0c03,
-0xcc0c03,
-0xcc0c03,
-0x9882bd,
-0x000000,
-0x8401bb,
-0xd7a06f,
-0x800000,
-0xee001f,
-0xca0400,
-0xc2ff00,
-0xcc0834,
-0xc13fff,
-0x7c74cb,
-0x7cc90b,
-0x7d010f,
-0x9902b0,
-0x7c738b,
-0x8401bb,
-0xd7a06f,
-0x800000,
-0xee001f,
-0xca0800,
-0x281900,
-0x7d898b,
-0x958014,
-0x281404,
-0xca0c00,
-0xca1000,
-0xca1c00,
-0xca2400,
-0xe2001f,
-0xd4c01a,
-0xd5001a,
-0xd5401a,
-0xcc1803,
-0xcc2c03,
-0xcc2c03,
-0xcc2c03,
-0x7da58b,
-0x7d9c47,
-0x984297,
-0x000000,
-0x800161,
-0xd4c01a,
-0xd4401e,
-0xd4801e,
-0x800000,
-0xee001e,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0x248c06,
-0x0ccc06,
-0x98c006,
-0xcc104e,
-0x990004,
-0xd40073,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xd4801e,
-0x800000,
-0xee001e,
-0xca0800,
-0xca0c00,
-0x34d018,
-0x251001,
-0x950021,
-0xc17fff,
-0xca1000,
-0xca1400,
-0xca1800,
-0xd4801d,
-0xd4c01d,
-0x7db18b,
-0xc14202,
-0xc2c001,
-0xd5801d,
-0x34dc0e,
-0x7d5d4c,
-0x7f734c,
-0xd7401e,
-0xd5001e,
-0xd5401e,
-0xc14200,
-0xc2c000,
-0x099c01,
-0x31dc10,
-0x7f5f4c,
-0x7f734c,
-0x042802,
-0x7d8380,
-0xd5a86f,
-0xd58066,
-0xd7401e,
-0xec005e,
-0xc82402,
-0xc82402,
-0x8001b8,
-0xd60076,
-0xd4401e,
-0xd4801e,
-0xd4c01e,
-0x800000,
-0xee001e,
-0x800000,
-0xee001f,
-0xd4001f,
-0x800000,
-0xd4001f,
-0xd4001f,
-0x880000,
-0xd4001f,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x010171,
-0x020178,
-0x03008f,
-0x04007f,
-0x050003,
-0x06003f,
-0x070032,
-0x08012c,
-0x090046,
-0x0a0036,
-0x1001b6,
-0x1700a2,
-0x22013a,
-0x230149,
-0x2000b4,
-0x240125,
-0x27004d,
-0x28006a,
-0x2a0060,
-0x2b0052,
-0x2f0065,
-0x320087,
-0x34017f,
-0x3c0156,
-0x3f0072,
-0x41018c,
-0x44012e,
-0x550173,
-0x56017a,
-0x60000b,
-0x610034,
-0x620038,
-0x630038,
-0x640038,
-0x650038,
-0x660038,
-0x670038,
-0x68003a,
-0x690041,
-0x6a0048,
-0x6b0048,
-0x6c0048,
-0x6d0048,
-0x6e0048,
-0x6f0048,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-};
-
-static const u32 RV635_cp_microcode[][3] = {
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x0000ffff, 0x00284621, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x00000000, 0x00e00000, 0x000 },
-    { 0x00010000, 0xc0294620, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00042004, 0x00604411, 0x68a },
-    { 0x00000000, 0x00600000, 0x62e },
-    { 0x00000000, 0x00600000, 0x642 },
-    { 0x00000000, 0xc0200800, 0x000 },
-    { 0x00000f00, 0x00281622, 0x000 },
-    { 0x00000008, 0x00211625, 0x000 },
-    { 0x00000018, 0x00203625, 0x000 },
-    { 0x8d000000, 0x00204411, 0x000 },
-    { 0x00000004, 0x002f0225, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x018 },
-    { 0x00412000, 0x00404811, 0x019 },
-    { 0x00422000, 0x00204811, 0x000 },
-    { 0x8e000000, 0x00204411, 0x000 },
-    { 0x00000028, 0x00204a2d, 0x000 },
-    { 0x90000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204805, 0x000 },
-    { 0x0000000c, 0x00211622, 0x000 },
-    { 0x00000003, 0x00281625, 0x000 },
-    { 0x00000019, 0x00211a22, 0x000 },
-    { 0x00000004, 0x00281a26, 0x000 },
-    { 0x00000000, 0x002914c5, 0x000 },
-    { 0x00000019, 0x00203625, 0x000 },
-    { 0x00000000, 0x003a1402, 0x000 },
-    { 0x00000016, 0x00211625, 0x000 },
-    { 0x00000003, 0x00281625, 0x000 },
-    { 0x00000017, 0x00200e2d, 0x000 },
-    { 0xfffffffc, 0x00280e23, 0x000 },
-    { 0x00000000, 0x002914a3, 0x000 },
-    { 0x00000017, 0x00203625, 0x000 },
-    { 0x00008000, 0x00280e22, 0x000 },
-    { 0x00000007, 0x00220e23, 0x000 },
-    { 0x00000000, 0x0029386e, 0x000 },
-    { 0x20000000, 0x00280e22, 0x000 },
-    { 0x00000006, 0x00210e23, 0x000 },
-    { 0x00000000, 0x0029386e, 0x000 },
-    { 0x00000000, 0x00220222, 0x000 },
-    { 0x00000000, 0x14e00000, 0x038 },
-    { 0x00000000, 0x2ee00000, 0x035 },
-    { 0x00000000, 0x2ce00000, 0x037 },
-    { 0x00000000, 0x00400e2d, 0x039 },
-    { 0x00000008, 0x00200e2d, 0x000 },
-    { 0x00000009, 0x0040122d, 0x046 },
-    { 0x00000001, 0x00400e2d, 0x039 },
-    { 0x00000000, 0xc0200c00, 0x000 },
-    { 0x003ffffc, 0x00281223, 0x000 },
-    { 0x00000002, 0x00221224, 0x000 },
-    { 0x0000001f, 0x00211e23, 0x000 },
-    { 0x00000000, 0x14e00000, 0x03e },
-    { 0x00000008, 0x00401c11, 0x041 },
-    { 0x0000000d, 0x00201e2d, 0x000 },
-    { 0x0000000f, 0x00281e27, 0x000 },
-    { 0x00000003, 0x00221e27, 0x000 },
-    { 0x7fc00000, 0x00281a23, 0x000 },
-    { 0x00000014, 0x00211a26, 0x000 },
-    { 0x00000001, 0x00331a26, 0x000 },
-    { 0x00000008, 0x00221a26, 0x000 },
-    { 0x00000000, 0x00290cc7, 0x000 },
-    { 0x00000027, 0x00203624, 0x000 },
-    { 0x00007f00, 0x00281221, 0x000 },
-    { 0x00001400, 0x002f0224, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x04b },
-    { 0x00000001, 0x00290e23, 0x000 },
-    { 0x0000000e, 0x00203623, 0x000 },
-    { 0x0000e000, 0x00204411, 0x000 },
-    { 0xfff80000, 0x00294a23, 0x000 },
-    { 0x00000000, 0x003a2c02, 0x000 },
-    { 0x00000002, 0x00220e2b, 0x000 },
-    { 0xfc000000, 0x00280e23, 0x000 },
-    { 0x0000000f, 0x00203623, 0x000 },
-    { 0x00001fff, 0x00294a23, 0x000 },
-    { 0x00000027, 0x00204a2d, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000029, 0x00200e2d, 0x000 },
-    { 0x060a0200, 0x00294a23, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000001, 0x00210222, 0x000 },
-    { 0x00000000, 0x14e00000, 0x061 },
-    { 0x00000000, 0x2ee00000, 0x05f },
-    { 0x00000000, 0x2ce00000, 0x05e },
-    { 0x00000000, 0x00400e2d, 0x062 },
-    { 0x00000001, 0x00400e2d, 0x062 },
-    { 0x0000000a, 0x00200e2d, 0x000 },
-    { 0x0000000b, 0x0040122d, 0x06a },
-    { 0x00000000, 0xc0200c00, 0x000 },
-    { 0x003ffffc, 0x00281223, 0x000 },
-    { 0x00000002, 0x00221224, 0x000 },
-    { 0x7fc00000, 0x00281623, 0x000 },
-    { 0x00000014, 0x00211625, 0x000 },
-    { 0x00000001, 0x00331625, 0x000 },
-    { 0x80000000, 0x00280e23, 0x000 },
-    { 0x00000000, 0x00290ca3, 0x000 },
-    { 0x3ffffc00, 0x00290e23, 0x000 },
-    { 0x0000001f, 0x00211e23, 0x000 },
-    { 0x00000000, 0x14e00000, 0x06d },
-    { 0x00000100, 0x00401c11, 0x070 },
-    { 0x0000000d, 0x00201e2d, 0x000 },
-    { 0x000000f0, 0x00281e27, 0x000 },
-    { 0x00000004, 0x00221e27, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000d, 0x00204811, 0x000 },
-    { 0xfffff0ff, 0x00281a30, 0x000 },
-    { 0x0000a028, 0x00204411, 0x000 },
-    { 0x00000000, 0x002948e6, 0x000 },
-    { 0x0000a018, 0x00204411, 0x000 },
-    { 0x3fffffff, 0x00284a23, 0x000 },
-    { 0x0000a010, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204804, 0x000 },
-    { 0x00000030, 0x0020162d, 0x000 },
-    { 0x00000002, 0x00291625, 0x000 },
-    { 0x00000030, 0x00203625, 0x000 },
-    { 0x00000025, 0x0020162d, 0x000 },
-    { 0x00000000, 0x002f00a3, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x083 },
-    { 0x00000026, 0x0020162d, 0x000 },
-    { 0x00000000, 0x002f00a4, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x084 },
-    { 0x00000000, 0x00400000, 0x08a },
-    { 0x00000025, 0x00203623, 0x000 },
-    { 0x00000026, 0x00203624, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000002, 0x00210227, 0x000 },
-    { 0x00000000, 0x14e00000, 0x08a },
-    { 0x00000000, 0x00600000, 0x665 },
-    { 0x00000000, 0x00600000, 0x659 },
-    { 0x00000002, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x08d },
-    { 0x00000012, 0xc0403620, 0x093 },
-    { 0x00000000, 0x2ee00000, 0x091 },
-    { 0x00000000, 0x2ce00000, 0x090 },
-    { 0x00000002, 0x00400e2d, 0x092 },
-    { 0x00000003, 0x00400e2d, 0x092 },
-    { 0x0000000c, 0x00200e2d, 0x000 },
-    { 0x00000012, 0x00203623, 0x000 },
-    { 0x00000003, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x098 },
-    { 0x0000a00c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0404800, 0x0a0 },
-    { 0x0000a00c, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x2ee00000, 0x09e },
-    { 0x00000000, 0x2ce00000, 0x09d },
-    { 0x00000002, 0x00400e2d, 0x09f },
-    { 0x00000003, 0x00400e2d, 0x09f },
-    { 0x0000000c, 0x00200e2d, 0x000 },
-    { 0x00000000, 0x00204803, 0x000 },
-    { 0x00000000, 0x003a0c02, 0x000 },
-    { 0x003f0000, 0x00280e23, 0x000 },
-    { 0x00000010, 0x00210e23, 0x000 },
-    { 0x00000011, 0x00203623, 0x000 },
-    { 0x0000001e, 0x0021022b, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0a7 },
-    { 0x00000016, 0xc0203620, 0x000 },
-    { 0x0000001f, 0x0021022b, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0aa },
-    { 0x00000015, 0xc0203620, 0x000 },
-    { 0x00000008, 0x00210e2b, 0x000 },
-    { 0x0000007f, 0x00280e23, 0x000 },
-    { 0x00000000, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0e1 },
-    { 0x00000000, 0x27000000, 0x000 },
-    { 0x00000000, 0x00600000, 0x2a3 },
-    { 0x00000001, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ae00000, 0x0b3 },
-    { 0x00000000, 0x00600000, 0x13a },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000006, 0x00204811, 0x000 },
-    { 0x0000000c, 0x00221e30, 0x000 },
-    { 0x99800000, 0x00204411, 0x000 },
-    { 0x00000004, 0x0020122d, 0x000 },
-    { 0x00000008, 0x00221224, 0x000 },
-    { 0x00000010, 0x00201811, 0x000 },
-    { 0x00000000, 0x00291ce4, 0x000 },
-    { 0x00000000, 0x00604807, 0x12f },
-    { 0x9b000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204802, 0x000 },
-    { 0x9c000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x0033146f, 0x000 },
-    { 0x00000001, 0x00333e23, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0x00203c05, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000e, 0x00204811, 0x000 },
-    { 0x00000000, 0x00201010, 0x000 },
-    { 0x0000e007, 0x00204411, 0x000 },
-    { 0x0000000f, 0x0021022b, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0cb },
-    { 0x00f8ff08, 0x00204811, 0x000 },
-    { 0x98000000, 0x00404811, 0x0dc },
-    { 0x000000f0, 0x00280e22, 0x000 },
-    { 0x000000a0, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x0da },
-    { 0x00000011, 0x00200e2d, 0x000 },
-    { 0x00000001, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0d5 },
-    { 0x00000002, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0d4 },
-    { 0x00003f00, 0x00400c11, 0x0d6 },
-    { 0x00001f00, 0x00400c11, 0x0d6 },
-    { 0x00000f00, 0x00200c11, 0x000 },
-    { 0x00380009, 0x00294a23, 0x000 },
-    { 0x3f000000, 0x00280e2b, 0x000 },
-    { 0x00000002, 0x00220e23, 0x000 },
-    { 0x00000007, 0x00494a23, 0x0dc },
-    { 0x00380f09, 0x00204811, 0x000 },
-    { 0x68000007, 0x00204811, 0x000 },
-    { 0x00000008, 0x00214a27, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x060a0200, 0x00294a24, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000a202, 0x00204411, 0x000 },
-    { 0x00ff0000, 0x00280e22, 0x000 },
-    { 0x00000080, 0x00294a23, 0x000 },
-    { 0x00000027, 0x00200e2d, 0x000 },
-    { 0x00000026, 0x0020122d, 0x000 },
-    { 0x00000000, 0x002f0083, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0ea },
-    { 0x00000000, 0x00600000, 0x65f },
-    { 0x00000000, 0x00400000, 0x0eb },
-    { 0x00000000, 0x00600000, 0x662 },
-    { 0x00000007, 0x0020222d, 0x000 },
-    { 0x00000005, 0x00220e22, 0x000 },
-    { 0x00100000, 0x00280e23, 0x000 },
-    { 0x00000000, 0x00292068, 0x000 },
-    { 0x00000000, 0x003a0c02, 0x000 },
-    { 0x000000ef, 0x00280e23, 0x000 },
-    { 0x00000000, 0x00292068, 0x000 },
-    { 0x00000017, 0x00200e2d, 0x000 },
-    { 0x00000003, 0x00210223, 0x000 },
-    { 0x00000000, 0x14e00000, 0x0f8 },
-    { 0x0000000b, 0x00210228, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0f8 },
-    { 0x00000400, 0x00292228, 0x000 },
-    { 0x00000014, 0x00203628, 0x000 },
-    { 0x0000001c, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0fd },
-    { 0x0000a30c, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000001e, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x10b },
-    { 0x0000a30f, 0x00204411, 0x000 },
-    { 0x00000011, 0x00200e2d, 0x000 },
-    { 0x00000001, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x104 },
-    { 0xffffffff, 0x00404811, 0x10b },
-    { 0x00000002, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x107 },
-    { 0x0000ffff, 0x00404811, 0x10b },
-    { 0x00000004, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x10a },
-    { 0x000000ff, 0x00404811, 0x10b },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0002c400, 0x00204411, 0x000 },
-    { 0x0000001f, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x112 },
-    { 0x00000010, 0x40210e20, 0x000 },
-    { 0x00000013, 0x00203623, 0x000 },
-    { 0x00000018, 0x40224a20, 0x000 },
-    { 0x00000010, 0xc0424a20, 0x114 },
-    { 0x00000000, 0x00200c11, 0x000 },
-    { 0x00000013, 0x00203623, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000000a, 0x00201011, 0x000 },
-    { 0x00000000, 0x002f0224, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x11b },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000001, 0x00531224, 0x117 },
-    { 0xffbfffff, 0x00283a2e, 0x000 },
-    { 0x0000001b, 0x00210222, 0x000 },
-    { 0x00000000, 0x14c00000, 0x12e },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000d, 0x00204811, 0x000 },
-    { 0x00000018, 0x00220e30, 0x000 },
-    { 0xfc000000, 0x00280e23, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000e, 0x00204811, 0x000 },
-    { 0x00000000, 0x00201010, 0x000 },
-    { 0x0000e00e, 0x00204411, 0x000 },
-    { 0x07f8ff08, 0x00204811, 0x000 },
-    { 0x00000000, 0x00294a23, 0x000 },
-    { 0x0000001c, 0x00201e2d, 0x000 },
-    { 0x00000008, 0x00214a27, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x060a0200, 0x00294a24, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0000217c, 0x00204411, 0x000 },
-    { 0x00800000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204806, 0x000 },
-    { 0x00000008, 0x00214a27, 0x000 },
-    { 0x00000000, 0x17000000, 0x000 },
-    { 0x0004217f, 0x00604411, 0x68a },
-    { 0x0000001f, 0x00210230, 0x000 },
-    { 0x00000000, 0x14c00000, 0x689 },
-    { 0x00000004, 0x00404c11, 0x135 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x000021f8, 0x00204411, 0x000 },
-    { 0x0000001c, 0x00204811, 0x000 },
-    { 0x000421f9, 0x00604411, 0x68a },
-    { 0x00000011, 0x00210230, 0x000 },
-    { 0x00000000, 0x14e00000, 0x13c },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x00000000, 0x00600000, 0x160 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x00000010, 0xc0211220, 0x000 },
-    { 0x0000ffff, 0x40280620, 0x000 },
-    { 0x00000010, 0xc0210a20, 0x000 },
-    { 0x00000000, 0x00341461, 0x000 },
-    { 0x00000000, 0x00741882, 0x2bb },
-    { 0x0001a1fd, 0x00604411, 0x2e0 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x147 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00600000, 0x160 },
-    { 0x00000010, 0x40210e20, 0x000 },
-    { 0x0000ffff, 0xc0281220, 0x000 },
-    { 0x00000010, 0x40211620, 0x000 },
-    { 0x0000ffff, 0xc0681a20, 0x2bb },
-    { 0x0001a1fd, 0x00604411, 0x2e0 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x158 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000001, 0x00300a2f, 0x000 },
-    { 0x00000001, 0x00210a22, 0x000 },
-    { 0x00000003, 0x00384a22, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001a, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00804811, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600000, 0x18f },
-    { 0x00000000, 0x00600000, 0x1a0 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00202c08, 0x000 },
-    { 0x00000000, 0x00202411, 0x000 },
-    { 0x00000000, 0x00202811, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x00000016, 0x00204811, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x93800000, 0x00204411, 0x000 },
-    { 0x00000002, 0x00221e29, 0x000 },
-    { 0x00000000, 0x007048eb, 0x19c },
-    { 0x00000000, 0x00600000, 0x2bb },
-    { 0x00000001, 0x40330620, 0x000 },
-    { 0x00000000, 0xc0302409, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00600000, 0x2a3 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ae00000, 0x181 },
-    { 0x00000000, 0x00600000, 0x13a },
-    { 0x00000000, 0x00400000, 0x186 },
-    { 0x95000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x186 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000001, 0x00530621, 0x182 },
-    { 0x92000000, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0604800, 0x197 },
-    { 0x0001a1fd, 0x00204411, 0x000 },
-    { 0x00000011, 0x0020062d, 0x000 },
-    { 0x00000000, 0x0078042a, 0x2fb },
-    { 0x00000000, 0x00202809, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x174 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000210, 0x00600411, 0x315 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x194 },
-    { 0x00000015, 0xc0203620, 0x000 },
-    { 0x00000016, 0xc0203620, 0x000 },
-    { 0x3f800000, 0x00200411, 0x000 },
-    { 0x46000000, 0x00600811, 0x1b2 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x19b },
-    { 0x00000001, 0x00804811, 0x000 },
-    { 0x00000021, 0x00804811, 0x000 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x00000010, 0xc0211220, 0x000 },
-    { 0x0000ffff, 0x40281620, 0x000 },
-    { 0x00000010, 0xc0811a20, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000006, 0x00204811, 0x000 },
-    { 0x00000008, 0x00221e30, 0x000 },
-    { 0x00000029, 0x00201a2d, 0x000 },
-    { 0x0000e000, 0x00204411, 0x000 },
-    { 0xfffbff09, 0x00204811, 0x000 },
-    { 0x0000000f, 0x0020222d, 0x000 },
-    { 0x00001fff, 0x00294a28, 0x000 },
-    { 0x00000006, 0x0020222d, 0x000 },
-    { 0x00000000, 0x002920e8, 0x000 },
-    { 0x00000000, 0x00204808, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x060a0200, 0x00294a26, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000100, 0x00201811, 0x000 },
-    { 0x00000008, 0x00621e28, 0x12f },
-    { 0x00000008, 0x00822228, 0x000 },
-    { 0x0002c000, 0x00204411, 0x000 },
-    { 0x00000015, 0x00600e2d, 0x1bd },
-    { 0x00000016, 0x00600e2d, 0x1bd },
-    { 0x0000c008, 0x00204411, 0x000 },
-    { 0x00000017, 0x00200e2d, 0x000 },
-    { 0x00000000, 0x14c00000, 0x1b9 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00204801, 0x000 },
-    { 0x39000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00804802, 0x000 },
-    { 0x00000018, 0x00202e2d, 0x000 },
-    { 0x00000000, 0x003b0d63, 0x000 },
-    { 0x00000008, 0x00224a23, 0x000 },
-    { 0x00000010, 0x00224a23, 0x000 },
-    { 0x00000018, 0x00224a23, 0x000 },
-    { 0x00000000, 0x00804803, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00001000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x00000007, 0x0021062f, 0x000 },
-    { 0x00000013, 0x00200a2d, 0x000 },
-    { 0x00000001, 0x00202c11, 0x000 },
-    { 0x0000ffff, 0x40282220, 0x000 },
-    { 0x0000000f, 0x00262228, 0x000 },
-    { 0x00000010, 0x40212620, 0x000 },
-    { 0x0000000f, 0x00262629, 0x000 },
-    { 0x00000000, 0x00202802, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001b, 0x00204811, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x1e0 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000081, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00000080, 0x00201c11, 0x000 },
-    { 0x00000000, 0x002f0227, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x1dc },
-    { 0x00000000, 0x00600000, 0x1e9 },
-    { 0x00000001, 0x00531e27, 0x1d8 },
-    { 0x00000001, 0x00202c11, 0x000 },
-    { 0x0000001f, 0x00280a22, 0x000 },
-    { 0x0000001f, 0x00282a2a, 0x000 },
-    { 0x00000001, 0x00530621, 0x1d1 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000002, 0x00304a2f, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00000001, 0x00301e2f, 0x000 },
-    { 0x00000000, 0x002f0227, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00600000, 0x1e9 },
-    { 0x00000001, 0x00531e27, 0x1e5 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x0000000f, 0x00260e23, 0x000 },
-    { 0x00000010, 0xc0211220, 0x000 },
-    { 0x0000000f, 0x00261224, 0x000 },
-    { 0x00000000, 0x00201411, 0x000 },
-    { 0x00000000, 0x00601811, 0x2bb },
-    { 0x0001a1fd, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f022b, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x1f8 },
-    { 0x00000010, 0x00221628, 0x000 },
-    { 0xffff0000, 0x00281625, 0x000 },
-    { 0x0000ffff, 0x00281a29, 0x000 },
-    { 0x00000000, 0x002948c5, 0x000 },
-    { 0x00000000, 0x0020480a, 0x000 },
-    { 0x00000000, 0x00202c11, 0x000 },
-    { 0x00000010, 0x00221623, 0x000 },
-    { 0xffff0000, 0x00281625, 0x000 },
-    { 0x0000ffff, 0x00281a24, 0x000 },
-    { 0x00000000, 0x002948c5, 0x000 },
-    { 0x00000000, 0x00731503, 0x205 },
-    { 0x00000000, 0x00201805, 0x000 },
-    { 0x00000000, 0x00731524, 0x205 },
-    { 0x00000000, 0x002d14c5, 0x000 },
-    { 0x00000000, 0x003008a2, 0x000 },
-    { 0x00000000, 0x00204802, 0x000 },
-    { 0x00000000, 0x00202802, 0x000 },
-    { 0x00000000, 0x00202003, 0x000 },
-    { 0x00000000, 0x00802404, 0x000 },
-    { 0x0000000f, 0x00210225, 0x000 },
-    { 0x00000000, 0x14c00000, 0x689 },
-    { 0x00000000, 0x002b1405, 0x000 },
-    { 0x00000001, 0x00901625, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001a, 0x00294a22, 0x000 },
-    { 0x00000000, 0xc0200000, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00384a21, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0000ffff, 0x40281220, 0x000 },
-    { 0x00000010, 0xc0211a20, 0x000 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x00000010, 0xc0211620, 0x000 },
-    { 0x00000000, 0x00741465, 0x2bb },
-    { 0x0001a1fd, 0x00604411, 0x2e0 },
-    { 0x00000001, 0x00330621, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x219 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x212 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000000, 0x00600000, 0x642 },
-    { 0x00000000, 0x0040040f, 0x213 },
-    { 0x00000000, 0x00600000, 0x62e },
-    { 0x00000000, 0x00600000, 0x642 },
-    { 0x00000210, 0x00600411, 0x315 },
-    { 0x00000000, 0x00600000, 0x1a0 },
-    { 0x00000000, 0x00600000, 0x19c },
-    { 0x00000000, 0x00600000, 0x2bb },
-    { 0x00000000, 0x00600000, 0x2a3 },
-    { 0x93800000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204808, 0x000 },
-    { 0x00000000, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ae00000, 0x232 },
-    { 0x00000000, 0x00600000, 0x13a },
-    { 0x00000000, 0x00400000, 0x236 },
-    { 0x95000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x236 },
-    { 0x00000000, 0xc0404800, 0x233 },
-    { 0x92000000, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x00000016, 0x00204811, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0001a1fd, 0x00204411, 0x000 },
-    { 0x00000000, 0x00600411, 0x2fb },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000000, 0x00600000, 0x62e },
-    { 0x0000a00c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0404800, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000018, 0x40210a20, 0x000 },
-    { 0x00000003, 0x002f0222, 0x000 },
-    { 0x00000000, 0x0ae00000, 0x24c },
-    { 0x00000014, 0x0020222d, 0x000 },
-    { 0x00080101, 0x00292228, 0x000 },
-    { 0x00000014, 0x00203628, 0x000 },
-    { 0x0000a30c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0404800, 0x251 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000010, 0x00600411, 0x315 },
-    { 0x3f800000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x00000000, 0x00600000, 0x27c },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000001, 0x00211e27, 0x000 },
-    { 0x00000000, 0x14e00000, 0x26a },
-    { 0x00000012, 0x00201e2d, 0x000 },
-    { 0x0000ffff, 0x00281e27, 0x000 },
-    { 0x00000000, 0x00341c27, 0x000 },
-    { 0x00000000, 0x12c00000, 0x25f },
-    { 0x00000000, 0x00201c11, 0x000 },
-    { 0x00000000, 0x002f00e5, 0x000 },
-    { 0x00000000, 0x08c00000, 0x262 },
-    { 0x00000000, 0x00201407, 0x000 },
-    { 0x00000012, 0x00201e2d, 0x000 },
-    { 0x00000010, 0x00211e27, 0x000 },
-    { 0x00000000, 0x00341c47, 0x000 },
-    { 0x00000000, 0x12c00000, 0x267 },
-    { 0x00000000, 0x00201c11, 0x000 },
-    { 0x00000000, 0x002f00e6, 0x000 },
-    { 0x00000000, 0x08c00000, 0x26a },
-    { 0x00000000, 0x00201807, 0x000 },
-    { 0x00000000, 0x00600000, 0x2c1 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x00000000, 0x00342023, 0x000 },
-    { 0x00000000, 0x12c00000, 0x272 },
-    { 0x00000000, 0x00342044, 0x000 },
-    { 0x00000000, 0x12c00000, 0x271 },
-    { 0x00000016, 0x00404811, 0x276 },
-    { 0x00000018, 0x00404811, 0x276 },
-    { 0x00000000, 0x00342044, 0x000 },
-    { 0x00000000, 0x12c00000, 0x275 },
-    { 0x00000017, 0x00404811, 0x276 },
-    { 0x00000019, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0001a1fd, 0x00604411, 0x2e9 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x256 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000010, 0x40210620, 0x000 },
-    { 0x0000ffff, 0xc0280a20, 0x000 },
-    { 0x00000010, 0x40210e20, 0x000 },
-    { 0x0000ffff, 0xc0281220, 0x000 },
-    { 0x00000010, 0x40211620, 0x000 },
-    { 0x0000ffff, 0xc0881a20, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00042004, 0x00604411, 0x68a },
-    { 0x00000000, 0x00600000, 0x62e },
-    { 0x00000000, 0xc0600000, 0x2a3 },
-    { 0x00000005, 0x00200a2d, 0x000 },
-    { 0x00000008, 0x00220a22, 0x000 },
-    { 0x0000002b, 0x00201a2d, 0x000 },
-    { 0x0000001c, 0x00201e2d, 0x000 },
-    { 0x00007000, 0x00281e27, 0x000 },
-    { 0x00000000, 0x00311ce6, 0x000 },
-    { 0x0000002a, 0x00201a2d, 0x000 },
-    { 0x0000000c, 0x00221a26, 0x000 },
-    { 0x00000000, 0x002f00e6, 0x000 },
-    { 0x00000000, 0x06e00000, 0x292 },
-    { 0x00000000, 0x00201c11, 0x000 },
-    { 0x00000000, 0x00200c11, 0x000 },
-    { 0x0000002b, 0x00203623, 0x000 },
-    { 0x00000010, 0x00201811, 0x000 },
-    { 0x00000000, 0x00691ce2, 0x12f },
-    { 0x93800000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204807, 0x000 },
-    { 0x95000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x29d },
-    { 0x00000001, 0x00333e2f, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x92000000, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x0000001c, 0x00403627, 0x000 },
-    { 0x0000000c, 0xc0220a20, 0x000 },
-    { 0x00000029, 0x00203622, 0x000 },
-    { 0x00000028, 0xc0403620, 0x000 },
-    { 0x0000a2a4, 0x00204411, 0x000 },
-    { 0x00000009, 0x00204811, 0x000 },
-    { 0xa1000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00804811, 0x000 },
-    { 0x00000021, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x002c1ce3, 0x000 },
-    { 0x00000021, 0x00203627, 0x000 },
-    { 0x00000022, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x002c1ce4, 0x000 },
-    { 0x00000022, 0x00203627, 0x000 },
-    { 0x00000023, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x003120a3, 0x000 },
-    { 0x00000000, 0x002d1d07, 0x000 },
-    { 0x00000023, 0x00203627, 0x000 },
-    { 0x00000024, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x003120c4, 0x000 },
-    { 0x00000000, 0x002d1d07, 0x000 },
-    { 0x00000024, 0x00803627, 0x000 },
-    { 0x00000021, 0x00203623, 0x000 },
-    { 0x00000022, 0x00203624, 0x000 },
-    { 0x00000000, 0x00311ca3, 0x000 },
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-    { 0x00000000, 0x00311cc4, 0x000 },
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-    { 0x00000000, 0x003120c4, 0x000 },
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-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000001, 0x00220a21, 0x000 },
-    { 0x00000000, 0x003308a2, 0x000 },
-    { 0x00000010, 0x00221e22, 0x000 },
-    { 0x00000010, 0x00212222, 0x000 },
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-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000001, 0x00220a21, 0x000 },
-    { 0x00000000, 0x003008a2, 0x000 },
-    { 0x00000010, 0x00221e22, 0x000 },
-    { 0x00000010, 0x00212222, 0x000 },
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-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x003808c5, 0x000 },
-    { 0x00000000, 0x00300841, 0x000 },
-    { 0x00000001, 0x00220a22, 0x000 },
-    { 0x00000000, 0x003308a2, 0x000 },
-    { 0x00000010, 0x00221e22, 0x000 },
-    { 0x00000010, 0x00212222, 0x000 },
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-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x060a0200, 0x00804811, 0x000 },
-    { 0x00000000, 0xc0200000, 0x000 },
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-    { 0x00000000, 0xc0204811, 0x000 },
-    { 0x8a000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x97000000, 0x00204411, 0x000 },
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-    { 0x8a000000, 0x00204411, 0x000 },
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-    { 0x0000a1fc, 0x00204411, 0x000 },
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-    { 0x00000000, 0xc0200400, 0x000 },
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-    { 0x00000001, 0x40304a20, 0x000 },
-    { 0x00000002, 0xc0304a20, 0x000 },
-    { 0x00000001, 0x00530a22, 0x34b },
-    { 0x0000003f, 0xc0280a20, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
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-    { 0x00000018, 0x00204811, 0x000 },
-    { 0x000421f9, 0x00604411, 0x68a },
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-    { 0x00000049, 0x00201811, 0x000 },
-    { 0x0000003f, 0x00204811, 0x000 },
-    { 0x00000001, 0x00331a26, 0x000 },
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-    { 0x00000000, 0x00404803, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x000021f8, 0x00204411, 0x000 },
-    { 0x00000016, 0x00204811, 0x000 },
-    { 0x000421f9, 0x00604411, 0x68a },
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-    { 0x00000000, 0x00404802, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
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-    { 0x000421f9, 0x00604411, 0x68a },
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-    { 0x00000000, 0xc0200800, 0x000 },
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-    { 0x00000000, 0x14e00000, 0x3ce },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
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-    { 0x00000018, 0x00204811, 0x000 },
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-    { 0xcafebabe, 0x00404811, 0x000 },
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-    { 0x00000001, 0x00204811, 0x000 },
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-    { 0x0004a2c2, 0x00604411, 0x68a },
-    { 0x00000036, 0x00203630, 0x000 },
-    { 0x00042004, 0x00604411, 0x68a },
-    { 0x0001a2a4, 0x00204411, 0x000 },
-    { 0x0000003f, 0x00204811, 0x000 },
-    { 0x0000003f, 0x00204811, 0x000 },
-    { 0x0000003f, 0x00204811, 0x000 },
-    { 0x0000003f, 0x00204811, 0x000 },
-    { 0x00000005, 0x00204811, 0x000 },
-    { 0x0000a1f4, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x88000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000006, 0x00204811, 0x000 },
-    { 0x00000001, 0x002f0230, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x629 },
-    { 0x00000030, 0x0020062d, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x629 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00007e00, 0x00280621, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x602 },
-    { 0x0000a092, 0x00204411, 0x000 },
-    { 0x00000031, 0x00204a2d, 0x000 },
-    { 0x0000a093, 0x00204411, 0x000 },
-    { 0x00000032, 0x00204a2d, 0x000 },
-    { 0x0000a2b6, 0x00204411, 0x000 },
-    { 0x00000033, 0x00204a2d, 0x000 },
-    { 0x0000a2ba, 0x00204411, 0x000 },
-    { 0x00000034, 0x00204a2d, 0x000 },
-    { 0x0000a2be, 0x00204411, 0x000 },
-    { 0x00000035, 0x00204a2d, 0x000 },
-    { 0x0000a2c2, 0x00204411, 0x000 },
-    { 0x00000036, 0x00204a2d, 0x000 },
-    { 0x00000030, 0x0020062d, 0x000 },
-    { 0x000001ff, 0x00280621, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x628 },
-    { 0x00000000, 0x00210221, 0x000 },
-    { 0x00000000, 0x14c00000, 0x60b },
-    { 0x0004a003, 0x00604411, 0x68a },
-    { 0x0000a003, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x00000001, 0x00210621, 0x000 },
-    { 0x00000000, 0x14c00000, 0x610 },
-    { 0x0004a010, 0x00604411, 0x68a },
-    { 0x0000a010, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x00000001, 0x00210621, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x628 },
-    { 0x0004a011, 0x00604411, 0x68a },
-    { 0x0000a011, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x0004a012, 0x00604411, 0x68a },
-    { 0x0000a012, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x0004a013, 0x00604411, 0x68a },
-    { 0x0000a013, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x0004a014, 0x00604411, 0x68a },
-    { 0x0000a014, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x0004a015, 0x00604411, 0x68a },
-    { 0x0000a015, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x0004a016, 0x00604411, 0x68a },
-    { 0x0000a016, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x0004a017, 0x00604411, 0x68a },
-    { 0x0000a017, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x00042004, 0x00604411, 0x68a },
-    { 0x0000002c, 0x0080062d, 0x000 },
-    { 0xff000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00000002, 0x00804811, 0x000 },
-    { 0x00000000, 0x0ee00000, 0x63a },
-    { 0x00000030, 0x0020062d, 0x000 },
-    { 0x00000002, 0x00280621, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x638 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00042004, 0x00604411, 0x68a },
-    { 0x00001000, 0x00200811, 0x000 },
-    { 0x0000002b, 0x00203622, 0x000 },
-    { 0x00000000, 0x00600000, 0x63e },
-    { 0x00000000, 0x00600000, 0x5c6 },
-    { 0x98000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00804811, 0x000 },
-    { 0x00000000, 0xc0600000, 0x63e },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x0000a2a4, 0x00204411, 0x000 },
-    { 0x00000022, 0x00204811, 0x000 },
-    { 0x89000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00404811, 0x62a },
-    { 0x97000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x8a000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00404811, 0x62a },
-    { 0x00000000, 0x00600000, 0x659 },
-    { 0x00002010, 0x00204411, 0x000 },
-    { 0x00008000, 0x00204811, 0x000 },
-    { 0x0001a2a4, 0xc0204411, 0x000 },
-    { 0x00000016, 0x00604811, 0x36e },
-    { 0x00002010, 0x00204411, 0x000 },
-    { 0x00010000, 0x00204811, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0000217c, 0x00204411, 0x000 },
-    { 0x09800000, 0x00204811, 0x000 },
-    { 0xffffffff, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x17000000, 0x000 },
-    { 0x0004217f, 0x00604411, 0x68a },
-    { 0x0000001f, 0x00210230, 0x000 },
-    { 0x00000000, 0x14c00000, 0x000 },
-    { 0x00000004, 0x00404c11, 0x653 },
-    { 0x00000000, 0x00400000, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000004, 0x00291e27, 0x000 },
-    { 0x00000017, 0x00803627, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0xfffffffb, 0x00281e27, 0x000 },
-    { 0x00000017, 0x00803627, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000008, 0x00291e27, 0x000 },
-    { 0x00000017, 0x00803627, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0xfffffff7, 0x00281e27, 0x000 },
-    { 0x00000017, 0x00803627, 0x000 },
-    { 0x00002010, 0x00204411, 0x000 },
-    { 0x00008000, 0x00204811, 0x000 },
-    { 0x0001a2a4, 0x00204411, 0x000 },
-    { 0x00000016, 0x00604811, 0x36e },
-    { 0x00002010, 0x00204411, 0x000 },
-    { 0x00010000, 0x00204811, 0x000 },
-    { 0x0000217c, 0x00204411, 0x000 },
-    { 0x01800000, 0x00204811, 0x000 },
-    { 0xffffffff, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x17000000, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0004217f, 0x00604411, 0x68a },
-    { 0x0000001f, 0x00210230, 0x000 },
-    { 0x00000000, 0x14c00000, 0x689 },
-    { 0x00000010, 0x00404c11, 0x66f },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x38c00000, 0x000 },
-    { 0x0000001d, 0x00200a2d, 0x000 },
-    { 0x0000001e, 0x00200e2d, 0x000 },
-    { 0x0000001f, 0x0020122d, 0x000 },
-    { 0x00000020, 0x0020162d, 0x000 },
-    { 0x00002169, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204804, 0x000 },
-    { 0x00000000, 0x00204805, 0x000 },
-    { 0x00000000, 0x00204801, 0x000 },
-    { 0xcafebabe, 0x00204811, 0x000 },
-    { 0x00000004, 0x00301224, 0x000 },
-    { 0x00000000, 0x002f0064, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x688 },
-    { 0x00000003, 0x00281a22, 0x000 },
-    { 0x00000008, 0x00221222, 0x000 },
-    { 0xfffff000, 0x00281224, 0x000 },
-    { 0x00000000, 0x002910c4, 0x000 },
-    { 0x0000001f, 0x00403624, 0x000 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x00000000, 0x1ac00000, 0x68a },
-    { 0x9f000000, 0x00204411, 0x000 },
-    { 0xcafebabe, 0x00204811, 0x000 },
-    { 0x00000000, 0x1ae00000, 0x68d },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x00000000, 0x1ac00000, 0x68f },
-    { 0x9e000000, 0x00204411, 0x000 },
-    { 0xcafebabe, 0x00204811, 0x000 },
-    { 0x00000000, 0x1ae00000, 0x692 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00001000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001b, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0001a1fd, 0xc0204411, 0x000 },
-    { 0x00000021, 0x00201e2d, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000024, 0x0020222d, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000022, 0x0020222d, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000023, 0x00201e2d, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x00404811, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x014204ff, 0x05bd0250, 0x000 },
-    { 0x01c30168, 0x043f05bd, 0x000 },
-    { 0x02250209, 0x02500151, 0x000 },
-    { 0x02230245, 0x02a00241, 0x000 },
-    { 0x03d705bd, 0x05bd05bd, 0x000 },
-    { 0x06460647, 0x031f05bd, 0x000 },
-    { 0x05bd05c2, 0x03200340, 0x000 },
-    { 0x032a0282, 0x03420334, 0x000 },
-    { 0x05bd05bd, 0x05bd05bd, 0x000 },
-    { 0x05bd054e, 0x05bd05bd, 0x000 },
-    { 0x03ba05bd, 0x04b80344, 0x000 },
-    { 0x0497044d, 0x043d05bd, 0x000 },
-    { 0x04cd05bd, 0x044104da, 0x000 },
-    { 0x044d0504, 0x03510375, 0x000 },
-    { 0x05bd05bd, 0x05bd05bd, 0x000 },
-    { 0x05bd05bd, 0x05bd05bd, 0x000 },
-    { 0x05bd05bd, 0x063c05c4, 0x000 },
-    { 0x05bd05bd, 0x000705bd, 0x000 },
-    { 0x05bd05bd, 0x05bd05bd, 0x000 },
-    { 0x05bd05bd, 0x05bd05bd, 0x000 },
-    { 0x03f803ed, 0x04080406, 0x000 },
-    { 0x040e040a, 0x040c0410, 0x000 },
-    { 0x041c0418, 0x04240420, 0x000 },
-    { 0x042c0428, 0x04340430, 0x000 },
-    { 0x05bd05bd, 0x043805bd, 0x000 },
-    { 0x05bd05bd, 0x05bd05bd, 0x000 },
-    { 0x05bd05bd, 0x05bd05bd, 0x000 },
-    { 0x00020676, 0x06940006, 0x000 },
-};
-
-static const u32 RV635_pfp_microcode[] = {
-0xca0400,
-0xa00000,
-0x7e828b,
-0x7c038b,
-0x8001b8,
-0x7c038b,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xc41838,
-0xca2400,
-0xca2800,
-0x9581a8,
-0xc41c3a,
-0xc3c000,
-0xca0800,
-0xca0c00,
-0x7c744b,
-0xc20005,
-0x99c000,
-0xc41c3a,
-0x7c744c,
-0xc0fff0,
-0x042c04,
-0x309002,
-0x7d2500,
-0x351402,
-0x7d350b,
-0x255403,
-0x7cd580,
-0x259c03,
-0x95c004,
-0xd5001b,
-0x7eddc1,
-0x7d9d80,
-0xd6801b,
-0xd5801b,
-0xd4401e,
-0xd5401e,
-0xd6401e,
-0xd6801e,
-0xd4801e,
-0xd4c01e,
-0x9783d3,
-0xd5c01e,
-0xca0800,
-0x80001a,
-0xca0c00,
-0xe4011e,
-0xd4001e,
-0x80000c,
-0xc41838,
-0xe4013e,
-0xd4001e,
-0x80000c,
-0xc41838,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca1800,
-0xd4401e,
-0xd5801e,
-0x800053,
-0xd40075,
-0xd4401e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd48019,
-0xd4c018,
-0xd50017,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xe2001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0xd48060,
-0xd4401e,
-0x800000,
-0xd4801e,
-0xca0800,
-0xd48061,
-0xd4401e,
-0x800000,
-0xd4801e,
-0xca0800,
-0xca0c00,
-0xd4401e,
-0xd48016,
-0xd4c016,
-0xd4801e,
-0x8001b8,
-0xd4c01e,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x948004,
-0xca1400,
-0xe420f3,
-0xd42013,
-0xd56065,
-0xd4e01c,
-0xd5201c,
-0xd5601c,
-0x800000,
-0x062001,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x9483f7,
-0xca1400,
-0xe420f3,
-0x800079,
-0xd42013,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x9883ef,
-0xca1400,
-0xd40064,
-0x80008d,
-0x000000,
-0xc41432,
-0xc61843,
-0xc4082f,
-0x954005,
-0xc40c30,
-0xd4401e,
-0x800000,
-0xee001e,
-0x9583f5,
-0xc41031,
-0xd44033,
-0xd52065,
-0xd4a01c,
-0xd4e01c,
-0xd5201c,
-0xe4015e,
-0xd4001e,
-0x800000,
-0x062001,
-0xca1800,
-0x0a2001,
-0xd60076,
-0xc40836,
-0x988007,
-0xc61045,
-0x950110,
-0xd4001f,
-0xd46062,
-0x800000,
-0xd42062,
-0xcc3835,
-0xcc1433,
-0x8401bb,
-0xd40072,
-0xd5401e,
-0x800000,
-0xee001e,
-0xe2001a,
-0x8401bb,
-0xe2001a,
-0xcc104b,
-0xcc0447,
-0x2c9401,
-0x7d098b,
-0x984005,
-0x7d15cb,
-0xd4001a,
-0x8001b8,
-0xd4006d,
-0x344401,
-0xcc0c48,
-0x98403a,
-0xcc2c4a,
-0x958004,
-0xcc0449,
-0x8001b8,
-0xd4001a,
-0xd4c01a,
-0x282801,
-0x8400f0,
-0xcc1003,
-0x98801b,
-0x04380c,
-0x8400f0,
-0xcc1003,
-0x988017,
-0x043808,
-0x8400f0,
-0xcc1003,
-0x988013,
-0x043804,
-0x8400f0,
-0xcc1003,
-0x988014,
-0xcc104c,
-0x9a8009,
-0xcc144d,
-0x9840dc,
-0xd4006d,
-0xcc1848,
-0xd5001a,
-0xd5401a,
-0x8000c9,
-0xd5801a,
-0x96c0d5,
-0xd4006d,
-0x8001b8,
-0xd4006e,
-0x9ac003,
-0xd4006d,
-0xd4006e,
-0x800000,
-0xec007f,
-0x9ac0cc,
-0xd4006d,
-0x8001b8,
-0xd4006e,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0x7d9103,
-0x7dd583,
-0x7d190c,
-0x35cc1f,
-0x35701f,
-0x7cf0cb,
-0x7cd08b,
-0x880000,
-0x7e8e8b,
-0x95c004,
-0xd4006e,
-0x8001b8,
-0xd4001a,
-0xd4c01a,
-0xcc0803,
-0xcc0c03,
-0xcc1003,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0xcc2403,
-0xcc2803,
-0x35c41f,
-0x36b01f,
-0x7c704b,
-0x34f01f,
-0x7c704b,
-0x35701f,
-0x7c704b,
-0x7d8881,
-0x7dccc1,
-0x7e5101,
-0x7e9541,
-0x7c9082,
-0x7cd4c2,
-0x7c848b,
-0x9ac003,
-0x7c8c8b,
-0x2c8801,
-0x98809e,
-0xd4006d,
-0x98409c,
-0xd4006e,
-0xcc084c,
-0xcc0c4d,
-0xcc1048,
-0xd4801a,
-0xd4c01a,
-0x800101,
-0xd5001a,
-0xcc0832,
-0xd40032,
-0x9482d9,
-0xca0c00,
-0xd4401e,
-0x800000,
-0xd4001e,
-0xe4011e,
-0xd4001e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd4401e,
-0xca1400,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xd5401e,
-0xd54034,
-0x800000,
-0xee001e,
-0x280404,
-0xe2001a,
-0xe2001a,
-0xd4401a,
-0xca3800,
-0xcc0803,
-0xcc0c03,
-0xcc0c03,
-0xcc0c03,
-0x9882bd,
-0x000000,
-0x8401bb,
-0xd7a06f,
-0x800000,
-0xee001f,
-0xca0400,
-0xc2ff00,
-0xcc0834,
-0xc13fff,
-0x7c74cb,
-0x7cc90b,
-0x7d010f,
-0x9902b0,
-0x7c738b,
-0x8401bb,
-0xd7a06f,
-0x800000,
-0xee001f,
-0xca0800,
-0x281900,
-0x7d898b,
-0x958014,
-0x281404,
-0xca0c00,
-0xca1000,
-0xca1c00,
-0xca2400,
-0xe2001f,
-0xd4c01a,
-0xd5001a,
-0xd5401a,
-0xcc1803,
-0xcc2c03,
-0xcc2c03,
-0xcc2c03,
-0x7da58b,
-0x7d9c47,
-0x984297,
-0x000000,
-0x800161,
-0xd4c01a,
-0xd4401e,
-0xd4801e,
-0x800000,
-0xee001e,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0x248c06,
-0x0ccc06,
-0x98c006,
-0xcc104e,
-0x990004,
-0xd40073,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xd4801e,
-0x800000,
-0xee001e,
-0xca0800,
-0xca0c00,
-0x34d018,
-0x251001,
-0x950021,
-0xc17fff,
-0xca1000,
-0xca1400,
-0xca1800,
-0xd4801d,
-0xd4c01d,
-0x7db18b,
-0xc14202,
-0xc2c001,
-0xd5801d,
-0x34dc0e,
-0x7d5d4c,
-0x7f734c,
-0xd7401e,
-0xd5001e,
-0xd5401e,
-0xc14200,
-0xc2c000,
-0x099c01,
-0x31dc10,
-0x7f5f4c,
-0x7f734c,
-0x042802,
-0x7d8380,
-0xd5a86f,
-0xd58066,
-0xd7401e,
-0xec005e,
-0xc82402,
-0xc82402,
-0x8001b8,
-0xd60076,
-0xd4401e,
-0xd4801e,
-0xd4c01e,
-0x800000,
-0xee001e,
-0x800000,
-0xee001f,
-0xd4001f,
-0x800000,
-0xd4001f,
-0xd4001f,
-0x880000,
-0xd4001f,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x010171,
-0x020178,
-0x03008f,
-0x04007f,
-0x050003,
-0x06003f,
-0x070032,
-0x08012c,
-0x090046,
-0x0a0036,
-0x1001b6,
-0x1700a2,
-0x22013a,
-0x230149,
-0x2000b4,
-0x240125,
-0x27004d,
-0x28006a,
-0x2a0060,
-0x2b0052,
-0x2f0065,
-0x320087,
-0x34017f,
-0x3c0156,
-0x3f0072,
-0x41018c,
-0x44012e,
-0x550173,
-0x56017a,
-0x60000b,
-0x610034,
-0x620038,
-0x630038,
-0x640038,
-0x650038,
-0x660038,
-0x670038,
-0x68003a,
-0x690041,
-0x6a0048,
-0x6b0048,
-0x6c0048,
-0x6d0048,
-0x6e0048,
-0x6f0048,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-};
-
-static const u32 RV670_cp_microcode[][3] = {
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x0000ffff, 0x00284621, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x00000000, 0x00e00000, 0x000 },
-    { 0x00010000, 0xc0294620, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00042004, 0x00604411, 0x67c },
-    { 0x00000000, 0x00600000, 0x624 },
-    { 0x00000000, 0x00600000, 0x638 },
-    { 0x00000000, 0xc0200800, 0x000 },
-    { 0x00000f00, 0x00281622, 0x000 },
-    { 0x00000008, 0x00211625, 0x000 },
-    { 0x00000018, 0x00203625, 0x000 },
-    { 0x8d000000, 0x00204411, 0x000 },
-    { 0x00000004, 0x002f0225, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x018 },
-    { 0x00412000, 0x00404811, 0x019 },
-    { 0x00422000, 0x00204811, 0x000 },
-    { 0x8e000000, 0x00204411, 0x000 },
-    { 0x00000028, 0x00204a2d, 0x000 },
-    { 0x90000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204805, 0x000 },
-    { 0x0000000c, 0x00211622, 0x000 },
-    { 0x00000003, 0x00281625, 0x000 },
-    { 0x00000019, 0x00211a22, 0x000 },
-    { 0x00000004, 0x00281a26, 0x000 },
-    { 0x00000000, 0x002914c5, 0x000 },
-    { 0x00000019, 0x00203625, 0x000 },
-    { 0x00000000, 0x003a1402, 0x000 },
-    { 0x00000016, 0x00211625, 0x000 },
-    { 0x00000003, 0x00281625, 0x000 },
-    { 0x00000017, 0x00200e2d, 0x000 },
-    { 0xfffffffc, 0x00280e23, 0x000 },
-    { 0x00000000, 0x002914a3, 0x000 },
-    { 0x00000017, 0x00203625, 0x000 },
-    { 0x00008000, 0x00280e22, 0x000 },
-    { 0x00000007, 0x00220e23, 0x000 },
-    { 0x00000000, 0x0029386e, 0x000 },
-    { 0x20000000, 0x00280e22, 0x000 },
-    { 0x00000006, 0x00210e23, 0x000 },
-    { 0x00000000, 0x0029386e, 0x000 },
-    { 0x00000000, 0x00220222, 0x000 },
-    { 0x00000000, 0x14e00000, 0x038 },
-    { 0x00000000, 0x2ee00000, 0x035 },
-    { 0x00000000, 0x2ce00000, 0x037 },
-    { 0x00000000, 0x00400e2d, 0x039 },
-    { 0x00000008, 0x00200e2d, 0x000 },
-    { 0x00000009, 0x0040122d, 0x046 },
-    { 0x00000001, 0x00400e2d, 0x039 },
-    { 0x00000000, 0xc0200c00, 0x000 },
-    { 0x003ffffc, 0x00281223, 0x000 },
-    { 0x00000002, 0x00221224, 0x000 },
-    { 0x0000001f, 0x00211e23, 0x000 },
-    { 0x00000000, 0x14e00000, 0x03e },
-    { 0x00000008, 0x00401c11, 0x041 },
-    { 0x0000000d, 0x00201e2d, 0x000 },
-    { 0x0000000f, 0x00281e27, 0x000 },
-    { 0x00000003, 0x00221e27, 0x000 },
-    { 0x7fc00000, 0x00281a23, 0x000 },
-    { 0x00000014, 0x00211a26, 0x000 },
-    { 0x00000001, 0x00331a26, 0x000 },
-    { 0x00000008, 0x00221a26, 0x000 },
-    { 0x00000000, 0x00290cc7, 0x000 },
-    { 0x00000027, 0x00203624, 0x000 },
-    { 0x00007f00, 0x00281221, 0x000 },
-    { 0x00001400, 0x002f0224, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x04b },
-    { 0x00000001, 0x00290e23, 0x000 },
-    { 0x0000000e, 0x00203623, 0x000 },
-    { 0x0000e000, 0x00204411, 0x000 },
-    { 0xfff80000, 0x00294a23, 0x000 },
-    { 0x00000000, 0x003a2c02, 0x000 },
-    { 0x00000002, 0x00220e2b, 0x000 },
-    { 0xfc000000, 0x00280e23, 0x000 },
-    { 0x0000000f, 0x00203623, 0x000 },
-    { 0x00001fff, 0x00294a23, 0x000 },
-    { 0x00000027, 0x00204a2d, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000029, 0x00200e2d, 0x000 },
-    { 0x060a0200, 0x00294a23, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000001, 0x00210222, 0x000 },
-    { 0x00000000, 0x14e00000, 0x061 },
-    { 0x00000000, 0x2ee00000, 0x05f },
-    { 0x00000000, 0x2ce00000, 0x05e },
-    { 0x00000000, 0x00400e2d, 0x062 },
-    { 0x00000001, 0x00400e2d, 0x062 },
-    { 0x0000000a, 0x00200e2d, 0x000 },
-    { 0x0000000b, 0x0040122d, 0x06a },
-    { 0x00000000, 0xc0200c00, 0x000 },
-    { 0x003ffffc, 0x00281223, 0x000 },
-    { 0x00000002, 0x00221224, 0x000 },
-    { 0x7fc00000, 0x00281623, 0x000 },
-    { 0x00000014, 0x00211625, 0x000 },
-    { 0x00000001, 0x00331625, 0x000 },
-    { 0x80000000, 0x00280e23, 0x000 },
-    { 0x00000000, 0x00290ca3, 0x000 },
-    { 0x3ffffc00, 0x00290e23, 0x000 },
-    { 0x0000001f, 0x00211e23, 0x000 },
-    { 0x00000000, 0x14e00000, 0x06d },
-    { 0x00000100, 0x00401c11, 0x070 },
-    { 0x0000000d, 0x00201e2d, 0x000 },
-    { 0x000000f0, 0x00281e27, 0x000 },
-    { 0x00000004, 0x00221e27, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000d, 0x00204811, 0x000 },
-    { 0xfffff0ff, 0x00281a30, 0x000 },
-    { 0x0000a028, 0x00204411, 0x000 },
-    { 0x00000000, 0x002948e6, 0x000 },
-    { 0x0000a018, 0x00204411, 0x000 },
-    { 0x3fffffff, 0x00284a23, 0x000 },
-    { 0x0000a010, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204804, 0x000 },
-    { 0x00000030, 0x0020162d, 0x000 },
-    { 0x00000002, 0x00291625, 0x000 },
-    { 0x00000030, 0x00203625, 0x000 },
-    { 0x00000025, 0x0020162d, 0x000 },
-    { 0x00000000, 0x002f00a3, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x083 },
-    { 0x00000026, 0x0020162d, 0x000 },
-    { 0x00000000, 0x002f00a4, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x084 },
-    { 0x00000000, 0x00400000, 0x08a },
-    { 0x00000025, 0x00203623, 0x000 },
-    { 0x00000026, 0x00203624, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000002, 0x00210227, 0x000 },
-    { 0x00000000, 0x14e00000, 0x08a },
-    { 0x00000000, 0x00600000, 0x659 },
-    { 0x00000000, 0x00600000, 0x64d },
-    { 0x00000002, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x08d },
-    { 0x00000012, 0xc0403620, 0x093 },
-    { 0x00000000, 0x2ee00000, 0x091 },
-    { 0x00000000, 0x2ce00000, 0x090 },
-    { 0x00000002, 0x00400e2d, 0x092 },
-    { 0x00000003, 0x00400e2d, 0x092 },
-    { 0x0000000c, 0x00200e2d, 0x000 },
-    { 0x00000012, 0x00203623, 0x000 },
-    { 0x00000003, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x098 },
-    { 0x0000a00c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0404800, 0x0a0 },
-    { 0x0000a00c, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x2ee00000, 0x09e },
-    { 0x00000000, 0x2ce00000, 0x09d },
-    { 0x00000002, 0x00400e2d, 0x09f },
-    { 0x00000003, 0x00400e2d, 0x09f },
-    { 0x0000000c, 0x00200e2d, 0x000 },
-    { 0x00000000, 0x00204803, 0x000 },
-    { 0x00000000, 0x003a0c02, 0x000 },
-    { 0x003f0000, 0x00280e23, 0x000 },
-    { 0x00000010, 0x00210e23, 0x000 },
-    { 0x00000011, 0x00203623, 0x000 },
-    { 0x0000001e, 0x0021022b, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0a7 },
-    { 0x00000016, 0xc0203620, 0x000 },
-    { 0x0000001f, 0x0021022b, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0aa },
-    { 0x00000015, 0xc0203620, 0x000 },
-    { 0x00000008, 0x00210e2b, 0x000 },
-    { 0x0000007f, 0x00280e23, 0x000 },
-    { 0x00000000, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0e1 },
-    { 0x00000000, 0x27000000, 0x000 },
-    { 0x00000000, 0x00600000, 0x2a3 },
-    { 0x00000001, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ae00000, 0x0b3 },
-    { 0x00000000, 0x00600000, 0x13a },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000006, 0x00204811, 0x000 },
-    { 0x0000000c, 0x00221e30, 0x000 },
-    { 0x99800000, 0x00204411, 0x000 },
-    { 0x00000004, 0x0020122d, 0x000 },
-    { 0x00000008, 0x00221224, 0x000 },
-    { 0x00000010, 0x00201811, 0x000 },
-    { 0x00000000, 0x00291ce4, 0x000 },
-    { 0x00000000, 0x00604807, 0x12f },
-    { 0x9b000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204802, 0x000 },
-    { 0x9c000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x0033146f, 0x000 },
-    { 0x00000001, 0x00333e23, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0x00203c05, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000e, 0x00204811, 0x000 },
-    { 0x00000000, 0x00201010, 0x000 },
-    { 0x0000e007, 0x00204411, 0x000 },
-    { 0x0000000f, 0x0021022b, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0cb },
-    { 0x00f8ff08, 0x00204811, 0x000 },
-    { 0x98000000, 0x00404811, 0x0dc },
-    { 0x000000f0, 0x00280e22, 0x000 },
-    { 0x000000a0, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x0da },
-    { 0x00000011, 0x00200e2d, 0x000 },
-    { 0x00000001, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0d5 },
-    { 0x00000002, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0d4 },
-    { 0x00003f00, 0x00400c11, 0x0d6 },
-    { 0x00001f00, 0x00400c11, 0x0d6 },
-    { 0x00000f00, 0x00200c11, 0x000 },
-    { 0x00380009, 0x00294a23, 0x000 },
-    { 0x3f000000, 0x00280e2b, 0x000 },
-    { 0x00000002, 0x00220e23, 0x000 },
-    { 0x00000007, 0x00494a23, 0x0dc },
-    { 0x00380f09, 0x00204811, 0x000 },
-    { 0x68000007, 0x00204811, 0x000 },
-    { 0x00000008, 0x00214a27, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x060a0200, 0x00294a24, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000a202, 0x00204411, 0x000 },
-    { 0x00ff0000, 0x00280e22, 0x000 },
-    { 0x00000080, 0x00294a23, 0x000 },
-    { 0x00000027, 0x00200e2d, 0x000 },
-    { 0x00000026, 0x0020122d, 0x000 },
-    { 0x00000000, 0x002f0083, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0ea },
-    { 0x00000000, 0x00600000, 0x653 },
-    { 0x00000000, 0x00400000, 0x0eb },
-    { 0x00000000, 0x00600000, 0x656 },
-    { 0x00000007, 0x0020222d, 0x000 },
-    { 0x00000005, 0x00220e22, 0x000 },
-    { 0x00100000, 0x00280e23, 0x000 },
-    { 0x00000000, 0x00292068, 0x000 },
-    { 0x00000000, 0x003a0c02, 0x000 },
-    { 0x000000ef, 0x00280e23, 0x000 },
-    { 0x00000000, 0x00292068, 0x000 },
-    { 0x00000017, 0x00200e2d, 0x000 },
-    { 0x00000003, 0x00210223, 0x000 },
-    { 0x00000000, 0x14e00000, 0x0f8 },
-    { 0x0000000b, 0x00210228, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0f8 },
-    { 0x00000400, 0x00292228, 0x000 },
-    { 0x00000014, 0x00203628, 0x000 },
-    { 0x0000001c, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0fd },
-    { 0x0000a30c, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000001e, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x10b },
-    { 0x0000a30f, 0x00204411, 0x000 },
-    { 0x00000011, 0x00200e2d, 0x000 },
-    { 0x00000001, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x104 },
-    { 0xffffffff, 0x00404811, 0x10b },
-    { 0x00000002, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x107 },
-    { 0x0000ffff, 0x00404811, 0x10b },
-    { 0x00000004, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x10a },
-    { 0x000000ff, 0x00404811, 0x10b },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0002c400, 0x00204411, 0x000 },
-    { 0x0000001f, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x112 },
-    { 0x00000010, 0x40210e20, 0x000 },
-    { 0x00000013, 0x00203623, 0x000 },
-    { 0x00000018, 0x40224a20, 0x000 },
-    { 0x00000010, 0xc0424a20, 0x114 },
-    { 0x00000000, 0x00200c11, 0x000 },
-    { 0x00000013, 0x00203623, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000000a, 0x00201011, 0x000 },
-    { 0x00000000, 0x002f0224, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x11b },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000001, 0x00531224, 0x117 },
-    { 0xffbfffff, 0x00283a2e, 0x000 },
-    { 0x0000001b, 0x00210222, 0x000 },
-    { 0x00000000, 0x14c00000, 0x12e },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000d, 0x00204811, 0x000 },
-    { 0x00000018, 0x00220e30, 0x000 },
-    { 0xfc000000, 0x00280e23, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000e, 0x00204811, 0x000 },
-    { 0x00000000, 0x00201010, 0x000 },
-    { 0x0000e00e, 0x00204411, 0x000 },
-    { 0x07f8ff08, 0x00204811, 0x000 },
-    { 0x00000000, 0x00294a23, 0x000 },
-    { 0x0000001c, 0x00201e2d, 0x000 },
-    { 0x00000008, 0x00214a27, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x060a0200, 0x00294a24, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0000217c, 0x00204411, 0x000 },
-    { 0x00800000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204806, 0x000 },
-    { 0x00000008, 0x00214a27, 0x000 },
-    { 0x00000000, 0x17000000, 0x000 },
-    { 0x0004217f, 0x00604411, 0x67c },
-    { 0x0000001f, 0x00210230, 0x000 },
-    { 0x00000000, 0x14c00000, 0x67b },
-    { 0x00000004, 0x00404c11, 0x135 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x000021f8, 0x00204411, 0x000 },
-    { 0x0000001c, 0x00204811, 0x000 },
-    { 0x000421f9, 0x00604411, 0x67c },
-    { 0x00000011, 0x00210230, 0x000 },
-    { 0x00000000, 0x14e00000, 0x13c },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x00000000, 0x00600000, 0x160 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x00000010, 0xc0211220, 0x000 },
-    { 0x0000ffff, 0x40280620, 0x000 },
-    { 0x00000010, 0xc0210a20, 0x000 },
-    { 0x00000000, 0x00341461, 0x000 },
-    { 0x00000000, 0x00741882, 0x2bb },
-    { 0x0001a1fd, 0x00604411, 0x2e0 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x147 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00600000, 0x160 },
-    { 0x00000010, 0x40210e20, 0x000 },
-    { 0x0000ffff, 0xc0281220, 0x000 },
-    { 0x00000010, 0x40211620, 0x000 },
-    { 0x0000ffff, 0xc0681a20, 0x2bb },
-    { 0x0001a1fd, 0x00604411, 0x2e0 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x158 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000001, 0x00300a2f, 0x000 },
-    { 0x00000001, 0x00210a22, 0x000 },
-    { 0x00000003, 0x00384a22, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001a, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00804811, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600000, 0x18f },
-    { 0x00000000, 0x00600000, 0x1a0 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00202c08, 0x000 },
-    { 0x00000000, 0x00202411, 0x000 },
-    { 0x00000000, 0x00202811, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x00000016, 0x00204811, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x93800000, 0x00204411, 0x000 },
-    { 0x00000002, 0x00221e29, 0x000 },
-    { 0x00000000, 0x007048eb, 0x19c },
-    { 0x00000000, 0x00600000, 0x2bb },
-    { 0x00000001, 0x40330620, 0x000 },
-    { 0x00000000, 0xc0302409, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00600000, 0x2a3 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ae00000, 0x181 },
-    { 0x00000000, 0x00600000, 0x13a },
-    { 0x00000000, 0x00400000, 0x186 },
-    { 0x95000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x186 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000001, 0x00530621, 0x182 },
-    { 0x92000000, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0604800, 0x197 },
-    { 0x0001a1fd, 0x00204411, 0x000 },
-    { 0x00000011, 0x0020062d, 0x000 },
-    { 0x00000000, 0x0078042a, 0x2fb },
-    { 0x00000000, 0x00202809, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x174 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000210, 0x00600411, 0x315 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x194 },
-    { 0x00000015, 0xc0203620, 0x000 },
-    { 0x00000016, 0xc0203620, 0x000 },
-    { 0x3f800000, 0x00200411, 0x000 },
-    { 0x46000000, 0x00600811, 0x1b2 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x19b },
-    { 0x00000001, 0x00804811, 0x000 },
-    { 0x00000021, 0x00804811, 0x000 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x00000010, 0xc0211220, 0x000 },
-    { 0x0000ffff, 0x40281620, 0x000 },
-    { 0x00000010, 0xc0811a20, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000006, 0x00204811, 0x000 },
-    { 0x00000008, 0x00221e30, 0x000 },
-    { 0x00000029, 0x00201a2d, 0x000 },
-    { 0x0000e000, 0x00204411, 0x000 },
-    { 0xfffbff09, 0x00204811, 0x000 },
-    { 0x0000000f, 0x0020222d, 0x000 },
-    { 0x00001fff, 0x00294a28, 0x000 },
-    { 0x00000006, 0x0020222d, 0x000 },
-    { 0x00000000, 0x002920e8, 0x000 },
-    { 0x00000000, 0x00204808, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x060a0200, 0x00294a26, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000100, 0x00201811, 0x000 },
-    { 0x00000008, 0x00621e28, 0x12f },
-    { 0x00000008, 0x00822228, 0x000 },
-    { 0x0002c000, 0x00204411, 0x000 },
-    { 0x00000015, 0x00600e2d, 0x1bd },
-    { 0x00000016, 0x00600e2d, 0x1bd },
-    { 0x0000c008, 0x00204411, 0x000 },
-    { 0x00000017, 0x00200e2d, 0x000 },
-    { 0x00000000, 0x14c00000, 0x1b9 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00204801, 0x000 },
-    { 0x39000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00804802, 0x000 },
-    { 0x00000018, 0x00202e2d, 0x000 },
-    { 0x00000000, 0x003b0d63, 0x000 },
-    { 0x00000008, 0x00224a23, 0x000 },
-    { 0x00000010, 0x00224a23, 0x000 },
-    { 0x00000018, 0x00224a23, 0x000 },
-    { 0x00000000, 0x00804803, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00001000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x00000007, 0x0021062f, 0x000 },
-    { 0x00000013, 0x00200a2d, 0x000 },
-    { 0x00000001, 0x00202c11, 0x000 },
-    { 0x0000ffff, 0x40282220, 0x000 },
-    { 0x0000000f, 0x00262228, 0x000 },
-    { 0x00000010, 0x40212620, 0x000 },
-    { 0x0000000f, 0x00262629, 0x000 },
-    { 0x00000000, 0x00202802, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001b, 0x00204811, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x1e0 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000081, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00000080, 0x00201c11, 0x000 },
-    { 0x00000000, 0x002f0227, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x1dc },
-    { 0x00000000, 0x00600000, 0x1e9 },
-    { 0x00000001, 0x00531e27, 0x1d8 },
-    { 0x00000001, 0x00202c11, 0x000 },
-    { 0x0000001f, 0x00280a22, 0x000 },
-    { 0x0000001f, 0x00282a2a, 0x000 },
-    { 0x00000001, 0x00530621, 0x1d1 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000002, 0x00304a2f, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00000001, 0x00301e2f, 0x000 },
-    { 0x00000000, 0x002f0227, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00600000, 0x1e9 },
-    { 0x00000001, 0x00531e27, 0x1e5 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x0000000f, 0x00260e23, 0x000 },
-    { 0x00000010, 0xc0211220, 0x000 },
-    { 0x0000000f, 0x00261224, 0x000 },
-    { 0x00000000, 0x00201411, 0x000 },
-    { 0x00000000, 0x00601811, 0x2bb },
-    { 0x0001a1fd, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f022b, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x1f8 },
-    { 0x00000010, 0x00221628, 0x000 },
-    { 0xffff0000, 0x00281625, 0x000 },
-    { 0x0000ffff, 0x00281a29, 0x000 },
-    { 0x00000000, 0x002948c5, 0x000 },
-    { 0x00000000, 0x0020480a, 0x000 },
-    { 0x00000000, 0x00202c11, 0x000 },
-    { 0x00000010, 0x00221623, 0x000 },
-    { 0xffff0000, 0x00281625, 0x000 },
-    { 0x0000ffff, 0x00281a24, 0x000 },
-    { 0x00000000, 0x002948c5, 0x000 },
-    { 0x00000000, 0x00731503, 0x205 },
-    { 0x00000000, 0x00201805, 0x000 },
-    { 0x00000000, 0x00731524, 0x205 },
-    { 0x00000000, 0x002d14c5, 0x000 },
-    { 0x00000000, 0x003008a2, 0x000 },
-    { 0x00000000, 0x00204802, 0x000 },
-    { 0x00000000, 0x00202802, 0x000 },
-    { 0x00000000, 0x00202003, 0x000 },
-    { 0x00000000, 0x00802404, 0x000 },
-    { 0x0000000f, 0x00210225, 0x000 },
-    { 0x00000000, 0x14c00000, 0x67b },
-    { 0x00000000, 0x002b1405, 0x000 },
-    { 0x00000001, 0x00901625, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001a, 0x00294a22, 0x000 },
-    { 0x00000000, 0xc0200000, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00384a21, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0000ffff, 0x40281220, 0x000 },
-    { 0x00000010, 0xc0211a20, 0x000 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x00000010, 0xc0211620, 0x000 },
-    { 0x00000000, 0x00741465, 0x2bb },
-    { 0x0001a1fd, 0x00604411, 0x2e0 },
-    { 0x00000001, 0x00330621, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x219 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x212 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000000, 0x00600000, 0x638 },
-    { 0x00000000, 0x0040040f, 0x213 },
-    { 0x00000000, 0x00600000, 0x624 },
-    { 0x00000000, 0x00600000, 0x638 },
-    { 0x00000210, 0x00600411, 0x315 },
-    { 0x00000000, 0x00600000, 0x1a0 },
-    { 0x00000000, 0x00600000, 0x19c },
-    { 0x00000000, 0x00600000, 0x2bb },
-    { 0x00000000, 0x00600000, 0x2a3 },
-    { 0x93800000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204808, 0x000 },
-    { 0x00000000, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ae00000, 0x232 },
-    { 0x00000000, 0x00600000, 0x13a },
-    { 0x00000000, 0x00400000, 0x236 },
-    { 0x95000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x236 },
-    { 0x00000000, 0xc0404800, 0x233 },
-    { 0x92000000, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x00000016, 0x00204811, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0001a1fd, 0x00204411, 0x000 },
-    { 0x00000000, 0x00600411, 0x2fb },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000000, 0x00600000, 0x624 },
-    { 0x0000a00c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0404800, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000018, 0x40210a20, 0x000 },
-    { 0x00000003, 0x002f0222, 0x000 },
-    { 0x00000000, 0x0ae00000, 0x24c },
-    { 0x00000014, 0x0020222d, 0x000 },
-    { 0x00080101, 0x00292228, 0x000 },
-    { 0x00000014, 0x00203628, 0x000 },
-    { 0x0000a30c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0404800, 0x251 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000010, 0x00600411, 0x315 },
-    { 0x3f800000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x00000000, 0x00600000, 0x27c },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000001, 0x00211e27, 0x000 },
-    { 0x00000000, 0x14e00000, 0x26a },
-    { 0x00000012, 0x00201e2d, 0x000 },
-    { 0x0000ffff, 0x00281e27, 0x000 },
-    { 0x00000000, 0x00341c27, 0x000 },
-    { 0x00000000, 0x12c00000, 0x25f },
-    { 0x00000000, 0x00201c11, 0x000 },
-    { 0x00000000, 0x002f00e5, 0x000 },
-    { 0x00000000, 0x08c00000, 0x262 },
-    { 0x00000000, 0x00201407, 0x000 },
-    { 0x00000012, 0x00201e2d, 0x000 },
-    { 0x00000010, 0x00211e27, 0x000 },
-    { 0x00000000, 0x00341c47, 0x000 },
-    { 0x00000000, 0x12c00000, 0x267 },
-    { 0x00000000, 0x00201c11, 0x000 },
-    { 0x00000000, 0x002f00e6, 0x000 },
-    { 0x00000000, 0x08c00000, 0x26a },
-    { 0x00000000, 0x00201807, 0x000 },
-    { 0x00000000, 0x00600000, 0x2c1 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x00000000, 0x00342023, 0x000 },
-    { 0x00000000, 0x12c00000, 0x272 },
-    { 0x00000000, 0x00342044, 0x000 },
-    { 0x00000000, 0x12c00000, 0x271 },
-    { 0x00000016, 0x00404811, 0x276 },
-    { 0x00000018, 0x00404811, 0x276 },
-    { 0x00000000, 0x00342044, 0x000 },
-    { 0x00000000, 0x12c00000, 0x275 },
-    { 0x00000017, 0x00404811, 0x276 },
-    { 0x00000019, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0001a1fd, 0x00604411, 0x2e9 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x256 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000010, 0x40210620, 0x000 },
-    { 0x0000ffff, 0xc0280a20, 0x000 },
-    { 0x00000010, 0x40210e20, 0x000 },
-    { 0x0000ffff, 0xc0281220, 0x000 },
-    { 0x00000010, 0x40211620, 0x000 },
-    { 0x0000ffff, 0xc0881a20, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00042004, 0x00604411, 0x67c },
-    { 0x00000000, 0x00600000, 0x624 },
-    { 0x00000000, 0xc0600000, 0x2a3 },
-    { 0x00000005, 0x00200a2d, 0x000 },
-    { 0x00000008, 0x00220a22, 0x000 },
-    { 0x0000002b, 0x00201a2d, 0x000 },
-    { 0x0000001c, 0x00201e2d, 0x000 },
-    { 0x00007000, 0x00281e27, 0x000 },
-    { 0x00000000, 0x00311ce6, 0x000 },
-    { 0x0000002a, 0x00201a2d, 0x000 },
-    { 0x0000000c, 0x00221a26, 0x000 },
-    { 0x00000000, 0x002f00e6, 0x000 },
-    { 0x00000000, 0x06e00000, 0x292 },
-    { 0x00000000, 0x00201c11, 0x000 },
-    { 0x00000000, 0x00200c11, 0x000 },
-    { 0x0000002b, 0x00203623, 0x000 },
-    { 0x00000010, 0x00201811, 0x000 },
-    { 0x00000000, 0x00691ce2, 0x12f },
-    { 0x93800000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204807, 0x000 },
-    { 0x95000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x29d },
-    { 0x00000001, 0x00333e2f, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x92000000, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x0000001c, 0x00403627, 0x000 },
-    { 0x0000000c, 0xc0220a20, 0x000 },
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-    { 0x00000028, 0xc0403620, 0x000 },
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-    { 0x00000009, 0x00204811, 0x000 },
-    { 0xa1000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00804811, 0x000 },
-    { 0x00000021, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x002c1ce3, 0x000 },
-    { 0x00000021, 0x00203627, 0x000 },
-    { 0x00000022, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x002c1ce4, 0x000 },
-    { 0x00000022, 0x00203627, 0x000 },
-    { 0x00000023, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x003120a3, 0x000 },
-    { 0x00000000, 0x002d1d07, 0x000 },
-    { 0x00000023, 0x00203627, 0x000 },
-    { 0x00000024, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x003120c4, 0x000 },
-    { 0x00000000, 0x002d1d07, 0x000 },
-    { 0x00000024, 0x00803627, 0x000 },
-    { 0x00000021, 0x00203623, 0x000 },
-    { 0x00000022, 0x00203624, 0x000 },
-    { 0x00000000, 0x00311ca3, 0x000 },
-    { 0x00000023, 0x00203627, 0x000 },
-    { 0x00000000, 0x00311cc4, 0x000 },
-    { 0x00000024, 0x00803627, 0x000 },
-    { 0x0000001a, 0x00203627, 0x000 },
-    { 0x0000001b, 0x00203628, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000002, 0x00210227, 0x000 },
-    { 0x00000000, 0x14c00000, 0x2dc },
-    { 0x00000000, 0x00400000, 0x2d9 },
-    { 0x0000001a, 0x00203627, 0x000 },
-    { 0x0000001b, 0x00203628, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000002, 0x00210227, 0x000 },
-    { 0x00000000, 0x14e00000, 0x2d9 },
-    { 0x00000003, 0x00210227, 0x000 },
-    { 0x00000000, 0x14e00000, 0x2dc },
-    { 0x00000023, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x002e00e1, 0x000 },
-    { 0x00000000, 0x02c00000, 0x2dc },
-    { 0x00000021, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x003120a1, 0x000 },
-    { 0x00000000, 0x002e00e8, 0x000 },
-    { 0x00000000, 0x06c00000, 0x2dc },
-    { 0x00000024, 0x00201e2d, 0x000 },
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-    { 0x00000000, 0x02c00000, 0x2dc },
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-    { 0x00000000, 0x003120c2, 0x000 },
-    { 0x00000000, 0x002e00e8, 0x000 },
-    { 0x00000000, 0x06c00000, 0x2dc },
-    { 0x00000000, 0x00600000, 0x659 },
-    { 0x00000000, 0x00600000, 0x2b5 },
-    { 0x00000000, 0x00400000, 0x2de },
-    { 0x00000000, 0x00600000, 0x2b5 },
-    { 0x00000000, 0x00600000, 0x650 },
-    { 0x00000000, 0x00400000, 0x2de },
-    { 0x00000000, 0x00600000, 0x2a7 },
-    { 0x00000000, 0x00400000, 0x2de },
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-    { 0x0000001b, 0x0080222d, 0x000 },
-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000000, 0x00311ca3, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x003120c4, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00894907, 0x000 },
-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000010, 0x00221e21, 0x000 },
-    { 0x00000000, 0x00294847, 0x000 },
-    { 0x00000000, 0x00311ca3, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000000, 0x00311ca1, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294847, 0x000 },
-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x003120c4, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000010, 0x00221e21, 0x000 },
-    { 0x00000000, 0x003120c2, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00894907, 0x000 },
-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000001, 0x00220a21, 0x000 },
-    { 0x00000000, 0x003308a2, 0x000 },
-    { 0x00000010, 0x00221e22, 0x000 },
-    { 0x00000010, 0x00212222, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x00311ca3, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000001, 0x00220a21, 0x000 },
-    { 0x00000000, 0x003008a2, 0x000 },
-    { 0x00000010, 0x00221e22, 0x000 },
-    { 0x00000010, 0x00212222, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x003120c4, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x003808c5, 0x000 },
-    { 0x00000000, 0x00300841, 0x000 },
-    { 0x00000001, 0x00220a22, 0x000 },
-    { 0x00000000, 0x003308a2, 0x000 },
-    { 0x00000010, 0x00221e22, 0x000 },
-    { 0x00000010, 0x00212222, 0x000 },
-    { 0x00000000, 0x00894907, 0x000 },
-    { 0x00000017, 0x0020222d, 0x000 },
-    { 0x00000000, 0x14c00000, 0x318 },
-    { 0xffffffef, 0x00280621, 0x000 },
-    { 0x00000014, 0x0020222d, 0x000 },
-    { 0x0000f8e0, 0x00204411, 0x000 },
-    { 0x00000000, 0x00294901, 0x000 },
-    { 0x00000000, 0x00894901, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x060a0200, 0x00804811, 0x000 },
-    { 0x00000000, 0xc0200000, 0x000 },
-    { 0x97000000, 0xc0204411, 0x000 },
-    { 0x00000000, 0xc0204811, 0x000 },
-    { 0x8a000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x97000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x8a000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x97000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x8a000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x0001a1fd, 0x00204411, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x00002257, 0x00204411, 0x000 },
-    { 0x00000003, 0xc0484a20, 0x000 },
-    { 0x0000225d, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0404800, 0x000 },
-    { 0x00000000, 0x00600000, 0x638 },
-    { 0x00000000, 0xc0200800, 0x000 },
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-    { 0x00000003, 0x00384a22, 0x000 },
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-    { 0x00000000, 0x002f0222, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x40204800, 0x000 },
-    { 0x00000001, 0x40304a20, 0x000 },
-    { 0x00000002, 0xc0304a20, 0x000 },
-    { 0x00000001, 0x00530a22, 0x34b },
-    { 0x0000003f, 0xc0280a20, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x000021f8, 0x00204411, 0x000 },
-    { 0x00000018, 0x00204811, 0x000 },
-    { 0x000421f9, 0x00604411, 0x67c },
-    { 0x00000011, 0x00210230, 0x000 },
-    { 0x00000000, 0x14e00000, 0x354 },
-    { 0x00000014, 0x002f0222, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x362 },
-    { 0x0001a2a4, 0x00204411, 0x000 },
-    { 0x00000000, 0x00604802, 0x36a },
-    { 0x00002100, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0404800, 0x000 },
-    { 0x00000004, 0x002f0222, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x366 },
-    { 0x0001a2a4, 0x00204411, 0x000 },
-    { 0x00000000, 0x00404802, 0x35d },
-    { 0x00000028, 0x002f0222, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x5b3 },
-    { 0x0001a2a4, 0x00204411, 0x000 },
-    { 0x00000000, 0x00404802, 0x35d },
-    { 0x0000002c, 0x00203626, 0x000 },
-    { 0x00000049, 0x00201811, 0x000 },
-    { 0x0000003f, 0x00204811, 0x000 },
-    { 0x00000001, 0x00331a26, 0x000 },
-    { 0x00000000, 0x002f0226, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x36c },
-    { 0x0000002c, 0x00801a2d, 0x000 },
-    { 0x0000003f, 0xc0280a20, 0x000 },
-    { 0x00000015, 0x002f0222, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x382 },
-    { 0x00000006, 0x002f0222, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x3ad },
-    { 0x00000016, 0x002f0222, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x3af },
-    { 0x00000020, 0x002f0222, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x398 },
-    { 0x0000000f, 0x002f0222, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x3a4 },
-    { 0x00000010, 0x002f0222, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x3a4 },
-    { 0x0000001e, 0x002f0222, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x38c },
-    { 0x0000a2a4, 0x00204411, 0x000 },
-    { 0x00000000, 0x00404802, 0x000 },
-    { 0x08000000, 0x00290a22, 0x000 },
-    { 0x00000003, 0x40210e20, 0x000 },
-    { 0x0000000c, 0xc0211220, 0x000 },
-    { 0x00080000, 0x00281224, 0x000 },
-    { 0x00000014, 0xc0221620, 0x000 },
-    { 0x00000000, 0x002914a4, 0x000 },
-    { 0x0000a2a4, 0x00204411, 0x000 },
-    { 0x00000000, 0x002948a2, 0x000 },
-    { 0x0000a1fe, 0x00204411, 0x000 },
-    { 0x00000000, 0x00404803, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x000021f8, 0x00204411, 0x000 },
-    { 0x00000016, 0x00204811, 0x000 },
-    { 0x000421f9, 0x00604411, 0x67c },
-    { 0x00000015, 0x00210230, 0x000 },
-    { 0x00000000, 0x14e00000, 0x38e },
-    { 0x0000210e, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x0000a2a4, 0x00204411, 0x000 },
-    { 0x00000000, 0x00404802, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x000021f8, 0x00204411, 0x000 },
-    { 0x00000017, 0x00204811, 0x000 },
-    { 0x000421f9, 0x00604411, 0x67c },
-    { 0x00000003, 0x00210230, 0x000 },
-    { 0x00000000, 0x14e00000, 0x39a },
-    { 0x00002108, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x0000a2a4, 0x00204411, 0x000 },
-    { 0x00000000, 0x00404802, 0x000 },
-    { 0x0000a2a4, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204802, 0x000 },
-    { 0x80000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000010, 0x00204811, 0x000 },
-    { 0x00000000, 0x00200010, 0x000 },
-    { 0x00000000, 0x14c00000, 0x3aa },
-    { 0x00000000, 0x00400000, 0x000 },
-    { 0x0001a2a4, 0x00204411, 0x000 },
-    { 0x00000006, 0x00404811, 0x000 },
-    { 0x0001a2a4, 0x00204411, 0x000 },
-    { 0x00000016, 0x00604811, 0x36a },
-    { 0x00000000, 0x00400000, 0x000 },
-    { 0x00000000, 0xc0200800, 0x000 },
-    { 0x00000000, 0xc0200c00, 0x000 },
-    { 0x0000001d, 0x00210223, 0x000 },
-    { 0x00000000, 0x14e00000, 0x3c4 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x000021f8, 0x00204411, 0x000 },
-    { 0x00000018, 0x00204811, 0x000 },
-    { 0x000421f9, 0x00604411, 0x67c },
-    { 0x00000011, 0x00210230, 0x000 },
-    { 0x00000000, 0x14e00000, 0x3b8 },
-    { 0x00002100, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204802, 0x000 },
-    { 0x00000000, 0x00204803, 0x000 },
-    { 0xbabecafe, 0x00204811, 0x000 },
-    { 0xcafebabe, 0x00204811, 0x000 },
-    { 0x0000a2a4, 0x00204411, 0x000 },
-    { 0x00000004, 0x00404811, 0x000 },
-    { 0x00002170, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204802, 0x000 },
-    { 0x00000000, 0x00204803, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000a, 0x00204811, 0x000 },
-    { 0x00000000, 0x00200010, 0x000 },
-    { 0x00000000, 0x14c00000, 0x3c9 },
-    { 0x8c000000, 0x00204411, 0x000 },
-    { 0xcafebabe, 0x00404811, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00003fff, 0x40280a20, 0x000 },
-    { 0x80000000, 0x40280e20, 0x000 },
-    { 0x40000000, 0xc0281220, 0x000 },
-    { 0x00040000, 0x00694622, 0x67c },
-    { 0x00000000, 0x00201410, 0x000 },
-    { 0x00000000, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x3d7 },
-    { 0x00000000, 0xc0401800, 0x3da },
-    { 0x00003fff, 0xc0281a20, 0x000 },
-    { 0x00040000, 0x00694626, 0x67c },
-    { 0x00000000, 0x00201810, 0x000 },
-    { 0x00000000, 0x002f0224, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x3dd },
-    { 0x00000000, 0xc0401c00, 0x3e0 },
-    { 0x00003fff, 0xc0281e20, 0x000 },
-    { 0x00040000, 0x00694627, 0x67c },
-    { 0x00000000, 0x00201c10, 0x000 },
-    { 0x00000000, 0x00204402, 0x000 },
-    { 0x00000000, 0x002820c5, 0x000 },
-    { 0x00000000, 0x004948e8, 0x000 },
-    { 0xa5800000, 0x00200811, 0x000 },
-    { 0x00002000, 0x00200c11, 0x000 },
-    { 0x83000000, 0x00604411, 0x408 },
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-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0x40204800, 0x000 },
-    { 0x0000001f, 0xc0210220, 0x000 },
-    { 0x00000000, 0x14c00000, 0x3ed },
-    { 0x00002010, 0x00204411, 0x000 },
-    { 0x00008000, 0x00204811, 0x000 },
-    { 0x0000ffff, 0xc0481220, 0x3f5 },
-    { 0xa7800000, 0x00200811, 0x000 },
-    { 0x0000a000, 0x00200c11, 0x000 },
-    { 0x83000000, 0x00604411, 0x408 },
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-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x0000ffff, 0xc0281220, 0x000 },
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-    { 0x00000000, 0x00304883, 0x000 },
-    { 0x84000000, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0x1d000000, 0x000 },
-    { 0x83000000, 0x00604411, 0x408 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0xa9800000, 0x00200811, 0x000 },
-    { 0x0000c000, 0x00400c11, 0x3f0 },
-    { 0xab800000, 0x00200811, 0x000 },
-    { 0x0000f8e0, 0x00400c11, 0x3f0 },
-    { 0xad800000, 0x00200811, 0x000 },
-    { 0x0000f880, 0x00400c11, 0x3f0 },
-    { 0xb3800000, 0x00200811, 0x000 },
-    { 0x0000f3fc, 0x00400c11, 0x3f0 },
-    { 0xaf800000, 0x00200811, 0x000 },
-    { 0x0000e000, 0x00400c11, 0x3f0 },
-    { 0xb1800000, 0x00200811, 0x000 },
-    { 0x0000f000, 0x00400c11, 0x3f0 },
-    { 0x83000000, 0x00204411, 0x000 },
-    { 0x00002148, 0x00204811, 0x000 },
-    { 0x84000000, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0x1d000000, 0x000 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x01182000, 0xc0304620, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x0218a000, 0xc0304620, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x0318c000, 0xc0304620, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x0418f8e0, 0xc0304620, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x0518f880, 0xc0304620, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x0618e000, 0xc0304620, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x0718f000, 0xc0304620, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
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-    { 0x00000000, 0x002f0230, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x5c3 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000030, 0x00403621, 0x5d6 },
-    { 0x00000030, 0x0020062d, 0x000 },
-    { 0x00007e00, 0x00280621, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x5d6 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0004a092, 0x00604411, 0x67c },
-    { 0x00000031, 0x00203630, 0x000 },
-    { 0x0004a093, 0x00604411, 0x67c },
-    { 0x00000032, 0x00203630, 0x000 },
-    { 0x0004a2b6, 0x00604411, 0x67c },
-    { 0x00000033, 0x00203630, 0x000 },
-    { 0x0004a2ba, 0x00604411, 0x67c },
-    { 0x00000034, 0x00203630, 0x000 },
-    { 0x0004a2be, 0x00604411, 0x67c },
-    { 0x00000035, 0x00203630, 0x000 },
-    { 0x0004a2c2, 0x00604411, 0x67c },
-    { 0x00000036, 0x00203630, 0x000 },
-    { 0x00042004, 0x00604411, 0x67c },
-    { 0x0001a2a4, 0x00204411, 0x000 },
-    { 0x0000003f, 0x00204811, 0x000 },
-    { 0x0000003f, 0x00204811, 0x000 },
-    { 0x0000003f, 0x00204811, 0x000 },
-    { 0x0000003f, 0x00204811, 0x000 },
-    { 0x00000005, 0x00204811, 0x000 },
-    { 0x0000a1f4, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x88000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000006, 0x00204811, 0x000 },
-    { 0x00000001, 0x002f0230, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x61f },
-    { 0x00000030, 0x0020062d, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x61f },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00007e00, 0x00280621, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x5f8 },
-    { 0x0000a092, 0x00204411, 0x000 },
-    { 0x00000031, 0x00204a2d, 0x000 },
-    { 0x0000a093, 0x00204411, 0x000 },
-    { 0x00000032, 0x00204a2d, 0x000 },
-    { 0x0000a2b6, 0x00204411, 0x000 },
-    { 0x00000033, 0x00204a2d, 0x000 },
-    { 0x0000a2ba, 0x00204411, 0x000 },
-    { 0x00000034, 0x00204a2d, 0x000 },
-    { 0x0000a2be, 0x00204411, 0x000 },
-    { 0x00000035, 0x00204a2d, 0x000 },
-    { 0x0000a2c2, 0x00204411, 0x000 },
-    { 0x00000036, 0x00204a2d, 0x000 },
-    { 0x00000030, 0x0020062d, 0x000 },
-    { 0x000001ff, 0x00280621, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x61e },
-    { 0x00000000, 0x00210221, 0x000 },
-    { 0x00000000, 0x14c00000, 0x601 },
-    { 0x0004a003, 0x00604411, 0x67c },
-    { 0x0000a003, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x00000001, 0x00210621, 0x000 },
-    { 0x00000000, 0x14c00000, 0x606 },
-    { 0x0004a010, 0x00604411, 0x67c },
-    { 0x0000a010, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x00000001, 0x00210621, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x61e },
-    { 0x0004a011, 0x00604411, 0x67c },
-    { 0x0000a011, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x0004a012, 0x00604411, 0x67c },
-    { 0x0000a012, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x0004a013, 0x00604411, 0x67c },
-    { 0x0000a013, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x0004a014, 0x00604411, 0x67c },
-    { 0x0000a014, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x0004a015, 0x00604411, 0x67c },
-    { 0x0000a015, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x0004a016, 0x00604411, 0x67c },
-    { 0x0000a016, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x0004a017, 0x00604411, 0x67c },
-    { 0x0000a017, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204810, 0x000 },
-    { 0x00042004, 0x00604411, 0x67c },
-    { 0x0000002c, 0x0080062d, 0x000 },
-    { 0xff000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00000002, 0x00804811, 0x000 },
-    { 0x00000000, 0x0ee00000, 0x630 },
-    { 0x00000030, 0x0020062d, 0x000 },
-    { 0x00000002, 0x00280621, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x62e },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00042004, 0x00604411, 0x67c },
-    { 0x00001000, 0x00200811, 0x000 },
-    { 0x0000002b, 0x00203622, 0x000 },
-    { 0x00000000, 0x00600000, 0x634 },
-    { 0x00000000, 0x00600000, 0x5bc },
-    { 0x98000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00804811, 0x000 },
-    { 0x00000000, 0xc0600000, 0x634 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x0000a2a4, 0x00204411, 0x000 },
-    { 0x00000022, 0x00204811, 0x000 },
-    { 0x89000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00404811, 0x620 },
-    { 0x97000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x8a000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00404811, 0x620 },
-    { 0x00000000, 0x00600000, 0x64d },
-    { 0x0001a2a4, 0xc0204411, 0x000 },
-    { 0x00000016, 0x00604811, 0x36a },
-    { 0x00002010, 0x00204411, 0x000 },
-    { 0x00010000, 0x00204811, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0000217c, 0x00204411, 0x000 },
-    { 0x09800000, 0x00204811, 0x000 },
-    { 0xffffffff, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x17000000, 0x000 },
-    { 0x0004217f, 0x00604411, 0x67c },
-    { 0x0000001f, 0x00210230, 0x000 },
-    { 0x00000000, 0x14c00000, 0x000 },
-    { 0x00000004, 0x00404c11, 0x647 },
-    { 0x00000000, 0x00400000, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000004, 0x00291e27, 0x000 },
-    { 0x00000017, 0x00803627, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0xfffffffb, 0x00281e27, 0x000 },
-    { 0x00000017, 0x00803627, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000008, 0x00291e27, 0x000 },
-    { 0x00000017, 0x00803627, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0xfffffff7, 0x00281e27, 0x000 },
-    { 0x00000017, 0x00803627, 0x000 },
-    { 0x0001a2a4, 0x00204411, 0x000 },
-    { 0x00000016, 0x00604811, 0x36a },
-    { 0x00002010, 0x00204411, 0x000 },
-    { 0x00010000, 0x00204811, 0x000 },
-    { 0x0000217c, 0x00204411, 0x000 },
-    { 0x01800000, 0x00204811, 0x000 },
-    { 0xffffffff, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x17000000, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0004217f, 0x00604411, 0x67c },
-    { 0x0000001f, 0x00210230, 0x000 },
-    { 0x00000000, 0x14c00000, 0x67b },
-    { 0x00000010, 0x00404c11, 0x661 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x38c00000, 0x000 },
-    { 0x0000001d, 0x00200a2d, 0x000 },
-    { 0x0000001e, 0x00200e2d, 0x000 },
-    { 0x0000001f, 0x0020122d, 0x000 },
-    { 0x00000020, 0x0020162d, 0x000 },
-    { 0x00002169, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204804, 0x000 },
-    { 0x00000000, 0x00204805, 0x000 },
-    { 0x00000000, 0x00204801, 0x000 },
-    { 0xcafebabe, 0x00204811, 0x000 },
-    { 0x00000004, 0x00301224, 0x000 },
-    { 0x00000000, 0x002f0064, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x67a },
-    { 0x00000003, 0x00281a22, 0x000 },
-    { 0x00000008, 0x00221222, 0x000 },
-    { 0xfffff000, 0x00281224, 0x000 },
-    { 0x00000000, 0x002910c4, 0x000 },
-    { 0x0000001f, 0x00403624, 0x000 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x00000000, 0x1ac00000, 0x67c },
-    { 0x9f000000, 0x00204411, 0x000 },
-    { 0xcafebabe, 0x00204811, 0x000 },
-    { 0x00000000, 0x1ae00000, 0x67f },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x00000000, 0x1ac00000, 0x681 },
-    { 0x9e000000, 0x00204411, 0x000 },
-    { 0xcafebabe, 0x00204811, 0x000 },
-    { 0x00000000, 0x1ae00000, 0x684 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00001000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001b, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0001a1fd, 0xc0204411, 0x000 },
-    { 0x00000021, 0x00201e2d, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000024, 0x0020222d, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000022, 0x0020222d, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000023, 0x00201e2d, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x00404811, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x014204f5, 0x05b30250, 0x000 },
-    { 0x01c30168, 0x043505b3, 0x000 },
-    { 0x02250209, 0x02500151, 0x000 },
-    { 0x02230245, 0x02a00241, 0x000 },
-    { 0x03cd05b3, 0x05b305b3, 0x000 },
-    { 0x063c063d, 0x031f05b3, 0x000 },
-    { 0x05b305b8, 0x03200340, 0x000 },
-    { 0x032a0282, 0x03420334, 0x000 },
-    { 0x05b305b3, 0x05b305b3, 0x000 },
-    { 0x05b30544, 0x05b305b3, 0x000 },
-    { 0x03b205b3, 0x04ae0344, 0x000 },
-    { 0x048d0443, 0x043305b3, 0x000 },
-    { 0x04c305b3, 0x043704d0, 0x000 },
-    { 0x044304fa, 0x03510371, 0x000 },
-    { 0x05b305b3, 0x05b305b3, 0x000 },
-    { 0x05b305b3, 0x05b305b3, 0x000 },
-    { 0x05b305b3, 0x063205ba, 0x000 },
-    { 0x05b305b3, 0x000705b3, 0x000 },
-    { 0x05b305b3, 0x05b305b3, 0x000 },
-    { 0x05b305b3, 0x05b305b3, 0x000 },
-    { 0x03ee03e3, 0x03fe03fc, 0x000 },
-    { 0x04040400, 0x04020406, 0x000 },
-    { 0x0412040e, 0x041a0416, 0x000 },
-    { 0x0422041e, 0x042a0426, 0x000 },
-    { 0x05b305b3, 0x042e05b3, 0x000 },
-    { 0x05b305b3, 0x05b305b3, 0x000 },
-    { 0x05b305b3, 0x05b305b3, 0x000 },
-    { 0x00020668, 0x06860006, 0x000 },
-};
-
-static const u32 RV670_pfp_microcode[] = {
-0xca0400,
-0xa00000,
-0x7e828b,
-0x7c038b,
-0x8001b8,
-0x7c038b,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xc41838,
-0xca2400,
-0xca2800,
-0x9581a8,
-0xc41c3a,
-0xc3c000,
-0xca0800,
-0xca0c00,
-0x7c744b,
-0xc20005,
-0x99c000,
-0xc41c3a,
-0x7c744c,
-0xc0fff0,
-0x042c04,
-0x309002,
-0x7d2500,
-0x351402,
-0x7d350b,
-0x255403,
-0x7cd580,
-0x259c03,
-0x95c004,
-0xd5001b,
-0x7eddc1,
-0x7d9d80,
-0xd6801b,
-0xd5801b,
-0xd4401e,
-0xd5401e,
-0xd6401e,
-0xd6801e,
-0xd4801e,
-0xd4c01e,
-0x9783d3,
-0xd5c01e,
-0xca0800,
-0x80001a,
-0xca0c00,
-0xe4011e,
-0xd4001e,
-0x80000c,
-0xc41838,
-0xe4013e,
-0xd4001e,
-0x80000c,
-0xc41838,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca1800,
-0xd4401e,
-0xd5801e,
-0x800053,
-0xd40075,
-0xd4401e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd48019,
-0xd4c018,
-0xd50017,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xe2001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0xd48060,
-0xd4401e,
-0x800000,
-0xd4801e,
-0xca0800,
-0xd48061,
-0xd4401e,
-0x800000,
-0xd4801e,
-0xca0800,
-0xca0c00,
-0xd4401e,
-0xd48016,
-0xd4c016,
-0xd4801e,
-0x8001b8,
-0xd4c01e,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x948004,
-0xca1400,
-0xe420f3,
-0xd42013,
-0xd56065,
-0xd4e01c,
-0xd5201c,
-0xd5601c,
-0x800000,
-0x062001,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x9483f7,
-0xca1400,
-0xe420f3,
-0x800079,
-0xd42013,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x9883ef,
-0xca1400,
-0xd40064,
-0x80008d,
-0x000000,
-0xc41432,
-0xc61843,
-0xc4082f,
-0x954005,
-0xc40c30,
-0xd4401e,
-0x800000,
-0xee001e,
-0x9583f5,
-0xc41031,
-0xd44033,
-0xd52065,
-0xd4a01c,
-0xd4e01c,
-0xd5201c,
-0xe4015e,
-0xd4001e,
-0x800000,
-0x062001,
-0xca1800,
-0x0a2001,
-0xd60076,
-0xc40836,
-0x988007,
-0xc61045,
-0x950110,
-0xd4001f,
-0xd46062,
-0x800000,
-0xd42062,
-0xcc3835,
-0xcc1433,
-0x8401bb,
-0xd40072,
-0xd5401e,
-0x800000,
-0xee001e,
-0xe2001a,
-0x8401bb,
-0xe2001a,
-0xcc104b,
-0xcc0447,
-0x2c9401,
-0x7d098b,
-0x984005,
-0x7d15cb,
-0xd4001a,
-0x8001b8,
-0xd4006d,
-0x344401,
-0xcc0c48,
-0x98403a,
-0xcc2c4a,
-0x958004,
-0xcc0449,
-0x8001b8,
-0xd4001a,
-0xd4c01a,
-0x282801,
-0x8400f0,
-0xcc1003,
-0x98801b,
-0x04380c,
-0x8400f0,
-0xcc1003,
-0x988017,
-0x043808,
-0x8400f0,
-0xcc1003,
-0x988013,
-0x043804,
-0x8400f0,
-0xcc1003,
-0x988014,
-0xcc104c,
-0x9a8009,
-0xcc144d,
-0x9840dc,
-0xd4006d,
-0xcc1848,
-0xd5001a,
-0xd5401a,
-0x8000c9,
-0xd5801a,
-0x96c0d5,
-0xd4006d,
-0x8001b8,
-0xd4006e,
-0x9ac003,
-0xd4006d,
-0xd4006e,
-0x800000,
-0xec007f,
-0x9ac0cc,
-0xd4006d,
-0x8001b8,
-0xd4006e,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0x7d9103,
-0x7dd583,
-0x7d190c,
-0x35cc1f,
-0x35701f,
-0x7cf0cb,
-0x7cd08b,
-0x880000,
-0x7e8e8b,
-0x95c004,
-0xd4006e,
-0x8001b8,
-0xd4001a,
-0xd4c01a,
-0xcc0803,
-0xcc0c03,
-0xcc1003,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0xcc2403,
-0xcc2803,
-0x35c41f,
-0x36b01f,
-0x7c704b,
-0x34f01f,
-0x7c704b,
-0x35701f,
-0x7c704b,
-0x7d8881,
-0x7dccc1,
-0x7e5101,
-0x7e9541,
-0x7c9082,
-0x7cd4c2,
-0x7c848b,
-0x9ac003,
-0x7c8c8b,
-0x2c8801,
-0x98809e,
-0xd4006d,
-0x98409c,
-0xd4006e,
-0xcc084c,
-0xcc0c4d,
-0xcc1048,
-0xd4801a,
-0xd4c01a,
-0x800101,
-0xd5001a,
-0xcc0832,
-0xd40032,
-0x9482d9,
-0xca0c00,
-0xd4401e,
-0x800000,
-0xd4001e,
-0xe4011e,
-0xd4001e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd4401e,
-0xca1400,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xd5401e,
-0xd54034,
-0x800000,
-0xee001e,
-0x280404,
-0xe2001a,
-0xe2001a,
-0xd4401a,
-0xca3800,
-0xcc0803,
-0xcc0c03,
-0xcc0c03,
-0xcc0c03,
-0x9882bd,
-0x000000,
-0x8401bb,
-0xd7a06f,
-0x800000,
-0xee001f,
-0xca0400,
-0xc2ff00,
-0xcc0834,
-0xc13fff,
-0x7c74cb,
-0x7cc90b,
-0x7d010f,
-0x9902b0,
-0x7c738b,
-0x8401bb,
-0xd7a06f,
-0x800000,
-0xee001f,
-0xca0800,
-0x281900,
-0x7d898b,
-0x958014,
-0x281404,
-0xca0c00,
-0xca1000,
-0xca1c00,
-0xca2400,
-0xe2001f,
-0xd4c01a,
-0xd5001a,
-0xd5401a,
-0xcc1803,
-0xcc2c03,
-0xcc2c03,
-0xcc2c03,
-0x7da58b,
-0x7d9c47,
-0x984297,
-0x000000,
-0x800161,
-0xd4c01a,
-0xd4401e,
-0xd4801e,
-0x800000,
-0xee001e,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0x248c06,
-0x0ccc06,
-0x98c006,
-0xcc104e,
-0x990004,
-0xd40073,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xd4801e,
-0x800000,
-0xee001e,
-0xca0800,
-0xca0c00,
-0x34d018,
-0x251001,
-0x950021,
-0xc17fff,
-0xca1000,
-0xca1400,
-0xca1800,
-0xd4801d,
-0xd4c01d,
-0x7db18b,
-0xc14202,
-0xc2c001,
-0xd5801d,
-0x34dc0e,
-0x7d5d4c,
-0x7f734c,
-0xd7401e,
-0xd5001e,
-0xd5401e,
-0xc14200,
-0xc2c000,
-0x099c01,
-0x31dc10,
-0x7f5f4c,
-0x7f734c,
-0x042802,
-0x7d8380,
-0xd5a86f,
-0xd58066,
-0xd7401e,
-0xec005e,
-0xc82402,
-0xc82402,
-0x8001b8,
-0xd60076,
-0xd4401e,
-0xd4801e,
-0xd4c01e,
-0x800000,
-0xee001e,
-0x800000,
-0xee001f,
-0xd4001f,
-0x800000,
-0xd4001f,
-0xd4001f,
-0x880000,
-0xd4001f,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x010171,
-0x020178,
-0x03008f,
-0x04007f,
-0x050003,
-0x06003f,
-0x070032,
-0x08012c,
-0x090046,
-0x0a0036,
-0x1001b6,
-0x1700a2,
-0x22013a,
-0x230149,
-0x2000b4,
-0x240125,
-0x27004d,
-0x28006a,
-0x2a0060,
-0x2b0052,
-0x2f0065,
-0x320087,
-0x34017f,
-0x3c0156,
-0x3f0072,
-0x41018c,
-0x44012e,
-0x550173,
-0x56017a,
-0x60000b,
-0x610034,
-0x620038,
-0x630038,
-0x640038,
-0x650038,
-0x660038,
-0x670038,
-0x68003a,
-0x690041,
-0x6a0048,
-0x6b0048,
-0x6c0048,
-0x6d0048,
-0x6e0048,
-0x6f0048,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-};
-
-static const u32 RS780_cp_microcode[][3] = {
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x0000ffff, 0x00284621, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x00000000, 0x00e00000, 0x000 },
-    { 0x00010000, 0xc0294620, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x00a0000a, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00042004, 0x00604411, 0x622 },
-    { 0x00000000, 0x00600000, 0x5d1 },
-    { 0x00000000, 0x00600000, 0x5de },
-    { 0x00000000, 0xc0200800, 0x000 },
-    { 0x00000f00, 0x00281622, 0x000 },
-    { 0x00000008, 0x00211625, 0x000 },
-    { 0x00000018, 0x00203625, 0x000 },
-    { 0x8d000000, 0x00204411, 0x000 },
-    { 0x00000004, 0x002f0225, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x018 },
-    { 0x00412000, 0x00404811, 0x019 },
-    { 0x00422000, 0x00204811, 0x000 },
-    { 0x8e000000, 0x00204411, 0x000 },
-    { 0x00000028, 0x00204a2d, 0x000 },
-    { 0x90000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204805, 0x000 },
-    { 0x0000000c, 0x00211622, 0x000 },
-    { 0x00000003, 0x00281625, 0x000 },
-    { 0x00000019, 0x00211a22, 0x000 },
-    { 0x00000004, 0x00281a26, 0x000 },
-    { 0x00000000, 0x002914c5, 0x000 },
-    { 0x00000019, 0x00203625, 0x000 },
-    { 0x00000000, 0x003a1402, 0x000 },
-    { 0x00000016, 0x00211625, 0x000 },
-    { 0x00000003, 0x00281625, 0x000 },
-    { 0x00000017, 0x00200e2d, 0x000 },
-    { 0xfffffffc, 0x00280e23, 0x000 },
-    { 0x00000000, 0x002914a3, 0x000 },
-    { 0x00000017, 0x00203625, 0x000 },
-    { 0x00008000, 0x00280e22, 0x000 },
-    { 0x00000007, 0x00220e23, 0x000 },
-    { 0x00000000, 0x0029386e, 0x000 },
-    { 0x20000000, 0x00280e22, 0x000 },
-    { 0x00000006, 0x00210e23, 0x000 },
-    { 0x00000000, 0x0029386e, 0x000 },
-    { 0x00000000, 0x00220222, 0x000 },
-    { 0x00000000, 0x14e00000, 0x038 },
-    { 0x00000000, 0x2ee00000, 0x035 },
-    { 0x00000000, 0x2ce00000, 0x037 },
-    { 0x00000000, 0x00400e2d, 0x039 },
-    { 0x00000008, 0x00200e2d, 0x000 },
-    { 0x00000009, 0x0040122d, 0x046 },
-    { 0x00000001, 0x00400e2d, 0x039 },
-    { 0x00000000, 0xc0200c00, 0x000 },
-    { 0x003ffffc, 0x00281223, 0x000 },
-    { 0x00000002, 0x00221224, 0x000 },
-    { 0x0000001f, 0x00211e23, 0x000 },
-    { 0x00000000, 0x14e00000, 0x03e },
-    { 0x00000008, 0x00401c11, 0x041 },
-    { 0x0000000d, 0x00201e2d, 0x000 },
-    { 0x0000000f, 0x00281e27, 0x000 },
-    { 0x00000003, 0x00221e27, 0x000 },
-    { 0x7fc00000, 0x00281a23, 0x000 },
-    { 0x00000014, 0x00211a26, 0x000 },
-    { 0x00000001, 0x00331a26, 0x000 },
-    { 0x00000008, 0x00221a26, 0x000 },
-    { 0x00000000, 0x00290cc7, 0x000 },
-    { 0x00000027, 0x00203624, 0x000 },
-    { 0x00007f00, 0x00281221, 0x000 },
-    { 0x00001400, 0x002f0224, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x04b },
-    { 0x00000001, 0x00290e23, 0x000 },
-    { 0x0000000e, 0x00203623, 0x000 },
-    { 0x0000e000, 0x00204411, 0x000 },
-    { 0xfff80000, 0x00294a23, 0x000 },
-    { 0x00000000, 0x003a2c02, 0x000 },
-    { 0x00000002, 0x00220e2b, 0x000 },
-    { 0xfc000000, 0x00280e23, 0x000 },
-    { 0x0000000f, 0x00203623, 0x000 },
-    { 0x00001fff, 0x00294a23, 0x000 },
-    { 0x00000027, 0x00204a2d, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000029, 0x00200e2d, 0x000 },
-    { 0x060a0200, 0x00294a23, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000001, 0x00210222, 0x000 },
-    { 0x00000000, 0x14e00000, 0x061 },
-    { 0x00000000, 0x2ee00000, 0x05f },
-    { 0x00000000, 0x2ce00000, 0x05e },
-    { 0x00000000, 0x00400e2d, 0x062 },
-    { 0x00000001, 0x00400e2d, 0x062 },
-    { 0x0000000a, 0x00200e2d, 0x000 },
-    { 0x0000000b, 0x0040122d, 0x06a },
-    { 0x00000000, 0xc0200c00, 0x000 },
-    { 0x003ffffc, 0x00281223, 0x000 },
-    { 0x00000002, 0x00221224, 0x000 },
-    { 0x7fc00000, 0x00281623, 0x000 },
-    { 0x00000014, 0x00211625, 0x000 },
-    { 0x00000001, 0x00331625, 0x000 },
-    { 0x80000000, 0x00280e23, 0x000 },
-    { 0x00000000, 0x00290ca3, 0x000 },
-    { 0x3ffffc00, 0x00290e23, 0x000 },
-    { 0x0000001f, 0x00211e23, 0x000 },
-    { 0x00000000, 0x14e00000, 0x06d },
-    { 0x00000100, 0x00401c11, 0x070 },
-    { 0x0000000d, 0x00201e2d, 0x000 },
-    { 0x000000f0, 0x00281e27, 0x000 },
-    { 0x00000004, 0x00221e27, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000d, 0x00204811, 0x000 },
-    { 0xfffff0ff, 0x00281a30, 0x000 },
-    { 0x0000a028, 0x00204411, 0x000 },
-    { 0x00000000, 0x002948e6, 0x000 },
-    { 0x0000a018, 0x00204411, 0x000 },
-    { 0x3fffffff, 0x00284a23, 0x000 },
-    { 0x0000a010, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204804, 0x000 },
-    { 0x00000030, 0x0020162d, 0x000 },
-    { 0x00000002, 0x00291625, 0x000 },
-    { 0x00000030, 0x00203625, 0x000 },
-    { 0x00000025, 0x0020162d, 0x000 },
-    { 0x00000000, 0x002f00a3, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x083 },
-    { 0x00000026, 0x0020162d, 0x000 },
-    { 0x00000000, 0x002f00a4, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x084 },
-    { 0x00000000, 0x00400000, 0x08a },
-    { 0x00000025, 0x00203623, 0x000 },
-    { 0x00000026, 0x00203624, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000002, 0x00210227, 0x000 },
-    { 0x00000000, 0x14e00000, 0x08a },
-    { 0x00000000, 0x00600000, 0x5ff },
-    { 0x00000000, 0x00600000, 0x5f3 },
-    { 0x00000002, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x08d },
-    { 0x00000012, 0xc0403620, 0x093 },
-    { 0x00000000, 0x2ee00000, 0x091 },
-    { 0x00000000, 0x2ce00000, 0x090 },
-    { 0x00000002, 0x00400e2d, 0x092 },
-    { 0x00000003, 0x00400e2d, 0x092 },
-    { 0x0000000c, 0x00200e2d, 0x000 },
-    { 0x00000012, 0x00203623, 0x000 },
-    { 0x00000003, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x098 },
-    { 0x0000a00c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0404800, 0x0a0 },
-    { 0x0000a00c, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x2ee00000, 0x09e },
-    { 0x00000000, 0x2ce00000, 0x09d },
-    { 0x00000002, 0x00400e2d, 0x09f },
-    { 0x00000003, 0x00400e2d, 0x09f },
-    { 0x0000000c, 0x00200e2d, 0x000 },
-    { 0x00000000, 0x00204803, 0x000 },
-    { 0x00000000, 0x003a0c02, 0x000 },
-    { 0x003f0000, 0x00280e23, 0x000 },
-    { 0x00000010, 0x00210e23, 0x000 },
-    { 0x00000011, 0x00203623, 0x000 },
-    { 0x0000001e, 0x0021022b, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0a7 },
-    { 0x00000016, 0xc0203620, 0x000 },
-    { 0x0000001f, 0x0021022b, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0aa },
-    { 0x00000015, 0xc0203620, 0x000 },
-    { 0x00000008, 0x00210e2b, 0x000 },
-    { 0x0000007f, 0x00280e23, 0x000 },
-    { 0x00000000, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0e1 },
-    { 0x00000000, 0x27000000, 0x000 },
-    { 0x00000000, 0x00600000, 0x2a3 },
-    { 0x00000001, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ae00000, 0x0b3 },
-    { 0x00000000, 0x00600000, 0x13a },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000006, 0x00204811, 0x000 },
-    { 0x0000000c, 0x00221e30, 0x000 },
-    { 0x99800000, 0x00204411, 0x000 },
-    { 0x00000004, 0x0020122d, 0x000 },
-    { 0x00000008, 0x00221224, 0x000 },
-    { 0x00000010, 0x00201811, 0x000 },
-    { 0x00000000, 0x00291ce4, 0x000 },
-    { 0x00000000, 0x00604807, 0x12f },
-    { 0x9b000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204802, 0x000 },
-    { 0x9c000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x0033146f, 0x000 },
-    { 0x00000001, 0x00333e23, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x00000000, 0x00203c05, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000e, 0x00204811, 0x000 },
-    { 0x00000000, 0x00201010, 0x000 },
-    { 0x0000e007, 0x00204411, 0x000 },
-    { 0x0000000f, 0x0021022b, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0cb },
-    { 0x00f8ff08, 0x00204811, 0x000 },
-    { 0x98000000, 0x00404811, 0x0dc },
-    { 0x000000f0, 0x00280e22, 0x000 },
-    { 0x000000a0, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x0da },
-    { 0x00000011, 0x00200e2d, 0x000 },
-    { 0x00000001, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0d5 },
-    { 0x00000002, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0d4 },
-    { 0x00003f00, 0x00400c11, 0x0d6 },
-    { 0x00001f00, 0x00400c11, 0x0d6 },
-    { 0x00000f00, 0x00200c11, 0x000 },
-    { 0x00380009, 0x00294a23, 0x000 },
-    { 0x3f000000, 0x00280e2b, 0x000 },
-    { 0x00000002, 0x00220e23, 0x000 },
-    { 0x00000007, 0x00494a23, 0x0dc },
-    { 0x00380f09, 0x00204811, 0x000 },
-    { 0x68000007, 0x00204811, 0x000 },
-    { 0x00000008, 0x00214a27, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x060a0200, 0x00294a24, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000a202, 0x00204411, 0x000 },
-    { 0x00ff0000, 0x00280e22, 0x000 },
-    { 0x00000080, 0x00294a23, 0x000 },
-    { 0x00000027, 0x00200e2d, 0x000 },
-    { 0x00000026, 0x0020122d, 0x000 },
-    { 0x00000000, 0x002f0083, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x0ea },
-    { 0x00000000, 0x00600000, 0x5f9 },
-    { 0x00000000, 0x00400000, 0x0eb },
-    { 0x00000000, 0x00600000, 0x5fc },
-    { 0x00000007, 0x0020222d, 0x000 },
-    { 0x00000005, 0x00220e22, 0x000 },
-    { 0x00100000, 0x00280e23, 0x000 },
-    { 0x00000000, 0x00292068, 0x000 },
-    { 0x00000000, 0x003a0c02, 0x000 },
-    { 0x000000ef, 0x00280e23, 0x000 },
-    { 0x00000000, 0x00292068, 0x000 },
-    { 0x00000017, 0x00200e2d, 0x000 },
-    { 0x00000003, 0x00210223, 0x000 },
-    { 0x00000000, 0x14e00000, 0x0f8 },
-    { 0x0000000b, 0x00210228, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0f8 },
-    { 0x00000400, 0x00292228, 0x000 },
-    { 0x00000014, 0x00203628, 0x000 },
-    { 0x0000001c, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x0fd },
-    { 0x0000a30c, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000001e, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x10b },
-    { 0x0000a30f, 0x00204411, 0x000 },
-    { 0x00000011, 0x00200e2d, 0x000 },
-    { 0x00000001, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x104 },
-    { 0xffffffff, 0x00404811, 0x10b },
-    { 0x00000002, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x107 },
-    { 0x0000ffff, 0x00404811, 0x10b },
-    { 0x00000004, 0x002f0223, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x10a },
-    { 0x000000ff, 0x00404811, 0x10b },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0002c400, 0x00204411, 0x000 },
-    { 0x0000001f, 0x00210e22, 0x000 },
-    { 0x00000000, 0x14c00000, 0x112 },
-    { 0x00000010, 0x40210e20, 0x000 },
-    { 0x00000013, 0x00203623, 0x000 },
-    { 0x00000018, 0x40224a20, 0x000 },
-    { 0x00000010, 0xc0424a20, 0x114 },
-    { 0x00000000, 0x00200c11, 0x000 },
-    { 0x00000013, 0x00203623, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x0000000a, 0x00201011, 0x000 },
-    { 0x00000000, 0x002f0224, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x11b },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000001, 0x00531224, 0x117 },
-    { 0xffbfffff, 0x00283a2e, 0x000 },
-    { 0x0000001b, 0x00210222, 0x000 },
-    { 0x00000000, 0x14c00000, 0x12e },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000d, 0x00204811, 0x000 },
-    { 0x00000018, 0x00220e30, 0x000 },
-    { 0xfc000000, 0x00280e23, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x0000000e, 0x00204811, 0x000 },
-    { 0x00000000, 0x00201010, 0x000 },
-    { 0x0000e00e, 0x00204411, 0x000 },
-    { 0x07f8ff08, 0x00204811, 0x000 },
-    { 0x00000000, 0x00294a23, 0x000 },
-    { 0x0000001c, 0x00201e2d, 0x000 },
-    { 0x00000008, 0x00214a27, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x060a0200, 0x00294a24, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0000217c, 0x00204411, 0x000 },
-    { 0x00800000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204806, 0x000 },
-    { 0x00000008, 0x00214a27, 0x000 },
-    { 0x00000000, 0x17000000, 0x000 },
-    { 0x0004217f, 0x00604411, 0x622 },
-    { 0x0000001f, 0x00210230, 0x000 },
-    { 0x00000000, 0x14c00000, 0x621 },
-    { 0x00000004, 0x00404c11, 0x135 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x000021f8, 0x00204411, 0x000 },
-    { 0x0000001c, 0x00204811, 0x000 },
-    { 0x000421f9, 0x00604411, 0x622 },
-    { 0x00000011, 0x00210230, 0x000 },
-    { 0x00000000, 0x14e00000, 0x13c },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x00000000, 0x00600000, 0x160 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x00000010, 0xc0211220, 0x000 },
-    { 0x0000ffff, 0x40280620, 0x000 },
-    { 0x00000010, 0xc0210a20, 0x000 },
-    { 0x00000000, 0x00341461, 0x000 },
-    { 0x00000000, 0x00741882, 0x2bb },
-    { 0x0001a1fd, 0x00604411, 0x2e0 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x147 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00600000, 0x160 },
-    { 0x00000010, 0x40210e20, 0x000 },
-    { 0x0000ffff, 0xc0281220, 0x000 },
-    { 0x00000010, 0x40211620, 0x000 },
-    { 0x0000ffff, 0xc0681a20, 0x2bb },
-    { 0x0001a1fd, 0x00604411, 0x2e0 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x158 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000001, 0x00300a2f, 0x000 },
-    { 0x00000001, 0x00210a22, 0x000 },
-    { 0x00000003, 0x00384a22, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001a, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00804811, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600000, 0x18f },
-    { 0x00000000, 0x00600000, 0x1a0 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00202c08, 0x000 },
-    { 0x00000000, 0x00202411, 0x000 },
-    { 0x00000000, 0x00202811, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x00000016, 0x00204811, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x93800000, 0x00204411, 0x000 },
-    { 0x00000002, 0x00221e29, 0x000 },
-    { 0x00000000, 0x007048eb, 0x19c },
-    { 0x00000000, 0x00600000, 0x2bb },
-    { 0x00000001, 0x40330620, 0x000 },
-    { 0x00000000, 0xc0302409, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00600000, 0x2a3 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ae00000, 0x181 },
-    { 0x00000000, 0x00600000, 0x13a },
-    { 0x00000000, 0x00400000, 0x186 },
-    { 0x95000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x186 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000001, 0x00530621, 0x182 },
-    { 0x92000000, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0604800, 0x197 },
-    { 0x0001a1fd, 0x00204411, 0x000 },
-    { 0x00000011, 0x0020062d, 0x000 },
-    { 0x00000000, 0x0078042a, 0x2fb },
-    { 0x00000000, 0x00202809, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x174 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000210, 0x00600411, 0x315 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x194 },
-    { 0x00000015, 0xc0203620, 0x000 },
-    { 0x00000016, 0xc0203620, 0x000 },
-    { 0x3f800000, 0x00200411, 0x000 },
-    { 0x46000000, 0x00600811, 0x1b2 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x19b },
-    { 0x00000001, 0x00804811, 0x000 },
-    { 0x00000021, 0x00804811, 0x000 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x00000010, 0xc0211220, 0x000 },
-    { 0x0000ffff, 0x40281620, 0x000 },
-    { 0x00000010, 0xc0811a20, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000006, 0x00204811, 0x000 },
-    { 0x00000008, 0x00221e30, 0x000 },
-    { 0x00000029, 0x00201a2d, 0x000 },
-    { 0x0000e000, 0x00204411, 0x000 },
-    { 0xfffbff09, 0x00204811, 0x000 },
-    { 0x0000000f, 0x0020222d, 0x000 },
-    { 0x00001fff, 0x00294a28, 0x000 },
-    { 0x00000006, 0x0020222d, 0x000 },
-    { 0x00000000, 0x002920e8, 0x000 },
-    { 0x00000000, 0x00204808, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x060a0200, 0x00294a26, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000100, 0x00201811, 0x000 },
-    { 0x00000008, 0x00621e28, 0x12f },
-    { 0x00000008, 0x00822228, 0x000 },
-    { 0x0002c000, 0x00204411, 0x000 },
-    { 0x00000015, 0x00600e2d, 0x1bd },
-    { 0x00000016, 0x00600e2d, 0x1bd },
-    { 0x0000c008, 0x00204411, 0x000 },
-    { 0x00000017, 0x00200e2d, 0x000 },
-    { 0x00000000, 0x14c00000, 0x1b9 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00204801, 0x000 },
-    { 0x39000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00804802, 0x000 },
-    { 0x00000018, 0x00202e2d, 0x000 },
-    { 0x00000000, 0x003b0d63, 0x000 },
-    { 0x00000008, 0x00224a23, 0x000 },
-    { 0x00000010, 0x00224a23, 0x000 },
-    { 0x00000018, 0x00224a23, 0x000 },
-    { 0x00000000, 0x00804803, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00001000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x00000007, 0x0021062f, 0x000 },
-    { 0x00000013, 0x00200a2d, 0x000 },
-    { 0x00000001, 0x00202c11, 0x000 },
-    { 0x0000ffff, 0x40282220, 0x000 },
-    { 0x0000000f, 0x00262228, 0x000 },
-    { 0x00000010, 0x40212620, 0x000 },
-    { 0x0000000f, 0x00262629, 0x000 },
-    { 0x00000000, 0x00202802, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001b, 0x00204811, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x1e0 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000081, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00000080, 0x00201c11, 0x000 },
-    { 0x00000000, 0x002f0227, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x1dc },
-    { 0x00000000, 0x00600000, 0x1e9 },
-    { 0x00000001, 0x00531e27, 0x1d8 },
-    { 0x00000001, 0x00202c11, 0x000 },
-    { 0x0000001f, 0x00280a22, 0x000 },
-    { 0x0000001f, 0x00282a2a, 0x000 },
-    { 0x00000001, 0x00530621, 0x1d1 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000002, 0x00304a2f, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00000001, 0x00301e2f, 0x000 },
-    { 0x00000000, 0x002f0227, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x00600000, 0x1e9 },
-    { 0x00000001, 0x00531e27, 0x1e5 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x0000000f, 0x00260e23, 0x000 },
-    { 0x00000010, 0xc0211220, 0x000 },
-    { 0x0000000f, 0x00261224, 0x000 },
-    { 0x00000000, 0x00201411, 0x000 },
-    { 0x00000000, 0x00601811, 0x2bb },
-    { 0x0001a1fd, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f022b, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x1f8 },
-    { 0x00000010, 0x00221628, 0x000 },
-    { 0xffff0000, 0x00281625, 0x000 },
-    { 0x0000ffff, 0x00281a29, 0x000 },
-    { 0x00000000, 0x002948c5, 0x000 },
-    { 0x00000000, 0x0020480a, 0x000 },
-    { 0x00000000, 0x00202c11, 0x000 },
-    { 0x00000010, 0x00221623, 0x000 },
-    { 0xffff0000, 0x00281625, 0x000 },
-    { 0x0000ffff, 0x00281a24, 0x000 },
-    { 0x00000000, 0x002948c5, 0x000 },
-    { 0x00000000, 0x00731503, 0x205 },
-    { 0x00000000, 0x00201805, 0x000 },
-    { 0x00000000, 0x00731524, 0x205 },
-    { 0x00000000, 0x002d14c5, 0x000 },
-    { 0x00000000, 0x003008a2, 0x000 },
-    { 0x00000000, 0x00204802, 0x000 },
-    { 0x00000000, 0x00202802, 0x000 },
-    { 0x00000000, 0x00202003, 0x000 },
-    { 0x00000000, 0x00802404, 0x000 },
-    { 0x0000000f, 0x00210225, 0x000 },
-    { 0x00000000, 0x14c00000, 0x621 },
-    { 0x00000000, 0x002b1405, 0x000 },
-    { 0x00000001, 0x00901625, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001a, 0x00294a22, 0x000 },
-    { 0x00000000, 0xc0200000, 0x000 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00384a21, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0000ffff, 0x40281220, 0x000 },
-    { 0x00000010, 0xc0211a20, 0x000 },
-    { 0x0000ffff, 0x40280e20, 0x000 },
-    { 0x00000010, 0xc0211620, 0x000 },
-    { 0x00000000, 0x00741465, 0x2bb },
-    { 0x0001a1fd, 0x00604411, 0x2e0 },
-    { 0x00000001, 0x00330621, 0x000 },
-    { 0x00000000, 0x002f0221, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x219 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x212 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000000, 0x00600000, 0x5de },
-    { 0x00000000, 0x0040040f, 0x213 },
-    { 0x00000000, 0x00600000, 0x5d1 },
-    { 0x00000000, 0x00600000, 0x5de },
-    { 0x00000210, 0x00600411, 0x315 },
-    { 0x00000000, 0x00600000, 0x1a0 },
-    { 0x00000000, 0x00600000, 0x19c },
-    { 0x00000000, 0x00600000, 0x2bb },
-    { 0x00000000, 0x00600000, 0x2a3 },
-    { 0x93800000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204808, 0x000 },
-    { 0x00000000, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ae00000, 0x232 },
-    { 0x00000000, 0x00600000, 0x13a },
-    { 0x00000000, 0x00400000, 0x236 },
-    { 0x95000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x236 },
-    { 0x00000000, 0xc0404800, 0x233 },
-    { 0x92000000, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x00000016, 0x00204811, 0x000 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0001a1fd, 0x00204411, 0x000 },
-    { 0x00000000, 0x00600411, 0x2fb },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000000, 0x00600000, 0x5d1 },
-    { 0x0000a00c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0404800, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000018, 0x40210a20, 0x000 },
-    { 0x00000003, 0x002f0222, 0x000 },
-    { 0x00000000, 0x0ae00000, 0x24c },
-    { 0x00000014, 0x0020222d, 0x000 },
-    { 0x00080101, 0x00292228, 0x000 },
-    { 0x00000014, 0x00203628, 0x000 },
-    { 0x0000a30c, 0x00204411, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0204800, 0x000 },
-    { 0x00000000, 0xc0404800, 0x251 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00000010, 0x00600411, 0x315 },
-    { 0x3f800000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x00000000, 0x00600000, 0x27c },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000001, 0x00211e27, 0x000 },
-    { 0x00000000, 0x14e00000, 0x26a },
-    { 0x00000012, 0x00201e2d, 0x000 },
-    { 0x0000ffff, 0x00281e27, 0x000 },
-    { 0x00000000, 0x00341c27, 0x000 },
-    { 0x00000000, 0x12c00000, 0x25f },
-    { 0x00000000, 0x00201c11, 0x000 },
-    { 0x00000000, 0x002f00e5, 0x000 },
-    { 0x00000000, 0x08c00000, 0x262 },
-    { 0x00000000, 0x00201407, 0x000 },
-    { 0x00000012, 0x00201e2d, 0x000 },
-    { 0x00000010, 0x00211e27, 0x000 },
-    { 0x00000000, 0x00341c47, 0x000 },
-    { 0x00000000, 0x12c00000, 0x267 },
-    { 0x00000000, 0x00201c11, 0x000 },
-    { 0x00000000, 0x002f00e6, 0x000 },
-    { 0x00000000, 0x08c00000, 0x26a },
-    { 0x00000000, 0x00201807, 0x000 },
-    { 0x00000000, 0x00600000, 0x2c1 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x00000000, 0x00342023, 0x000 },
-    { 0x00000000, 0x12c00000, 0x272 },
-    { 0x00000000, 0x00342044, 0x000 },
-    { 0x00000000, 0x12c00000, 0x271 },
-    { 0x00000016, 0x00404811, 0x276 },
-    { 0x00000018, 0x00404811, 0x276 },
-    { 0x00000000, 0x00342044, 0x000 },
-    { 0x00000000, 0x12c00000, 0x275 },
-    { 0x00000017, 0x00404811, 0x276 },
-    { 0x00000019, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0001a1fd, 0x00604411, 0x2e9 },
-    { 0x00003fff, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x256 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x00000010, 0x40210620, 0x000 },
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-    { 0x0000ffff, 0xc0881a20, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00042004, 0x00604411, 0x622 },
-    { 0x00000000, 0x00600000, 0x5d1 },
-    { 0x00000000, 0xc0600000, 0x2a3 },
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-    { 0x00000000, 0x002f022f, 0x000 },
-    { 0x00000000, 0x0ce00000, 0x29d },
-    { 0x00000001, 0x00333e2f, 0x000 },
-    { 0x00000000, 0xd9004800, 0x000 },
-    { 0x92000000, 0x00204411, 0x000 },
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-    { 0x00000009, 0x00204811, 0x000 },
-    { 0xa1000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00804811, 0x000 },
-    { 0x00000021, 0x00201e2d, 0x000 },
-    { 0x00000000, 0x002c1ce3, 0x000 },
-    { 0x00000021, 0x00203627, 0x000 },
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-    { 0x00000000, 0x14e00000, 0x2dc },
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-    { 0x00000000, 0x002e00e8, 0x000 },
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-    { 0x00000000, 0x02c00000, 0x2dc },
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-    { 0x00000000, 0x003120c2, 0x000 },
-    { 0x00000000, 0x002e00e8, 0x000 },
-    { 0x00000000, 0x06c00000, 0x2dc },
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-    { 0x00000000, 0x00600000, 0x2b5 },
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-    { 0x00000000, 0x00600000, 0x2b5 },
-    { 0x00000000, 0x00600000, 0x5f6 },
-    { 0x00000000, 0x00400000, 0x2de },
-    { 0x00000000, 0x00600000, 0x2a7 },
-    { 0x00000000, 0x00400000, 0x2de },
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-    { 0x0000001b, 0x0080222d, 0x000 },
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-    { 0x00000000, 0x00294887, 0x000 },
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-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x003120c4, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00894907, 0x000 },
-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000010, 0x00221e21, 0x000 },
-    { 0x00000000, 0x00294847, 0x000 },
-    { 0x00000000, 0x00311ca3, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000000, 0x00311ca1, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294847, 0x000 },
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-    { 0x00000000, 0x003120c4, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
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-    { 0x00000000, 0x003120c2, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00894907, 0x000 },
-    { 0x00000010, 0x00221e23, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000001, 0x00220a21, 0x000 },
-    { 0x00000000, 0x003308a2, 0x000 },
-    { 0x00000010, 0x00221e22, 0x000 },
-    { 0x00000010, 0x00212222, 0x000 },
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-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294887, 0x000 },
-    { 0x00000001, 0x00220a21, 0x000 },
-    { 0x00000000, 0x003008a2, 0x000 },
-    { 0x00000010, 0x00221e22, 0x000 },
-    { 0x00000010, 0x00212222, 0x000 },
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-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x003808c5, 0x000 },
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-    { 0x00000001, 0x00220a22, 0x000 },
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-    { 0x00000010, 0x00221e22, 0x000 },
-    { 0x00000010, 0x00212222, 0x000 },
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-    { 0x00000000, 0x0ce00000, 0x000 },
-    { 0x00000000, 0x40204800, 0x000 },
-    { 0x00000001, 0x40304a20, 0x000 },
-    { 0x00000002, 0xc0304a20, 0x000 },
-    { 0x00000001, 0x00530a22, 0x355 },
-    { 0x0000003f, 0xc0280a20, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x000021f8, 0x00204411, 0x000 },
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-    { 0x000421f9, 0x00604411, 0x622 },
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-    { 0x00000000, 0x0cc00000, 0x5ba },
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-    { 0x00000000, 0x00404802, 0x367 },
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-    { 0x00000049, 0x00201811, 0x000 },
-    { 0x0000003f, 0x00204811, 0x000 },
-    { 0x00000001, 0x00331a26, 0x000 },
-    { 0x00000000, 0x002f0226, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x376 },
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-    { 0x00000000, 0x00404803, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
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-    { 0x00000016, 0x00204811, 0x000 },
-    { 0x000421f9, 0x00604411, 0x622 },
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-    { 0x00000000, 0x00404802, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
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-    { 0x00000017, 0x00204811, 0x000 },
-    { 0x000421f9, 0x00604411, 0x622 },
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-    { 0x81000000, 0x00204411, 0x000 },
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-    { 0x00000016, 0x00604811, 0x374 },
-    { 0x00000000, 0x00400000, 0x000 },
-    { 0x00000000, 0xc0200800, 0x000 },
-    { 0x00000000, 0xc0200c00, 0x000 },
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-    { 0x00000000, 0x14e00000, 0x3ce },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x000021f8, 0x00204411, 0x000 },
-    { 0x00000018, 0x00204811, 0x000 },
-    { 0x000421f9, 0x00604411, 0x622 },
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-    { 0x00000000, 0x00204802, 0x000 },
-    { 0x00000000, 0x00204803, 0x000 },
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-    { 0xcafebabe, 0x00404811, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00003fff, 0x40280a20, 0x000 },
-    { 0x80000000, 0x40280e20, 0x000 },
-    { 0x40000000, 0xc0281220, 0x000 },
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-    { 0x00000000, 0x0cc00000, 0x3e1 },
-    { 0x00000000, 0xc0401800, 0x3e4 },
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-    { 0x00000000, 0x00201810, 0x000 },
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-    { 0x0000a2bf, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204807, 0x000 },
-    { 0x00000035, 0x0020262d, 0x000 },
-    { 0x0000001a, 0x00212229, 0x000 },
-    { 0x00000006, 0x00222629, 0x000 },
-    { 0x0000a2c6, 0x00204411, 0x000 },
-    { 0x00000000, 0x003048e9, 0x000 },
-    { 0x00000000, 0x00e00000, 0x5ac },
-    { 0x0000a2d3, 0x00204411, 0x000 },
-    { 0x00000000, 0x00404808, 0x000 },
-    { 0x0000a2d3, 0x00204411, 0x000 },
-    { 0x00000001, 0x00504a28, 0x000 },
-    { 0x0000a2c3, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204807, 0x000 },
-    { 0x00000036, 0x0020262d, 0x000 },
-    { 0x0000001a, 0x00212229, 0x000 },
-    { 0x00000006, 0x00222629, 0x000 },
-    { 0x0000a2c7, 0x00204411, 0x000 },
-    { 0x00000000, 0x003048e9, 0x000 },
-    { 0x00000000, 0x00e00000, 0x5b8 },
-    { 0x0000a2d4, 0x00204411, 0x000 },
-    { 0x00000000, 0x00404808, 0x000 },
-    { 0x0000a2d4, 0x00204411, 0x000 },
-    { 0x00000001, 0x00504a28, 0x000 },
-    { 0x85000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204801, 0x000 },
-    { 0x0000304a, 0x00204411, 0x000 },
-    { 0x01000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x00400000, 0x5be },
-    { 0xa4000000, 0xc0204411, 0x000 },
-    { 0x00000000, 0xc0404800, 0x000 },
-    { 0x00000000, 0xc0600000, 0x5c3 },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x0001a2a4, 0x00204411, 0x000 },
-    { 0x0000003f, 0x00204811, 0x000 },
-    { 0x0000003f, 0x00204811, 0x000 },
-    { 0x0000003f, 0x00204811, 0x000 },
-    { 0x0000003f, 0x00204811, 0x000 },
-    { 0x00000005, 0x00204811, 0x000 },
-    { 0x0000a1f4, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x88000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0xff000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x00000002, 0x00804811, 0x000 },
-    { 0x00000000, 0x0ee00000, 0x5d6 },
-    { 0x00001000, 0x00200811, 0x000 },
-    { 0x0000002b, 0x00203622, 0x000 },
-    { 0x00000000, 0x00600000, 0x5da },
-    { 0x00000000, 0x00600000, 0x5c3 },
-    { 0x98000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00804811, 0x000 },
-    { 0x00000000, 0xc0600000, 0x5da },
-    { 0x00000000, 0xc0400400, 0x001 },
-    { 0x0000a2a4, 0x00204411, 0x000 },
-    { 0x00000022, 0x00204811, 0x000 },
-    { 0x89000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00404811, 0x5cd },
-    { 0x97000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x8a000000, 0x00204411, 0x000 },
-    { 0x00000000, 0x00404811, 0x5cd },
-    { 0x00000000, 0x00600000, 0x5f3 },
-    { 0x0001a2a4, 0xc0204411, 0x000 },
-    { 0x00000016, 0x00604811, 0x374 },
-    { 0x00002010, 0x00204411, 0x000 },
-    { 0x00010000, 0x00204811, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0000217c, 0x00204411, 0x000 },
-    { 0x09800000, 0x00204811, 0x000 },
-    { 0xffffffff, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x17000000, 0x000 },
-    { 0x0004217f, 0x00604411, 0x622 },
-    { 0x0000001f, 0x00210230, 0x000 },
-    { 0x00000000, 0x14c00000, 0x000 },
-    { 0x00000004, 0x00404c11, 0x5ed },
-    { 0x00000000, 0x00400000, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000004, 0x00291e27, 0x000 },
-    { 0x00000017, 0x00803627, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0xfffffffb, 0x00281e27, 0x000 },
-    { 0x00000017, 0x00803627, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0x00000008, 0x00291e27, 0x000 },
-    { 0x00000017, 0x00803627, 0x000 },
-    { 0x00000017, 0x00201e2d, 0x000 },
-    { 0xfffffff7, 0x00281e27, 0x000 },
-    { 0x00000017, 0x00803627, 0x000 },
-    { 0x0001a2a4, 0x00204411, 0x000 },
-    { 0x00000016, 0x00604811, 0x374 },
-    { 0x00002010, 0x00204411, 0x000 },
-    { 0x00010000, 0x00204811, 0x000 },
-    { 0x0000217c, 0x00204411, 0x000 },
-    { 0x01800000, 0x00204811, 0x000 },
-    { 0xffffffff, 0x00204811, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000000, 0x17000000, 0x000 },
-    { 0x81000000, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0004217f, 0x00604411, 0x622 },
-    { 0x0000001f, 0x00210230, 0x000 },
-    { 0x00000000, 0x14c00000, 0x621 },
-    { 0x00000010, 0x00404c11, 0x607 },
-    { 0x00000000, 0xc0200400, 0x000 },
-    { 0x00000000, 0x38c00000, 0x000 },
-    { 0x0000001d, 0x00200a2d, 0x000 },
-    { 0x0000001e, 0x00200e2d, 0x000 },
-    { 0x0000001f, 0x0020122d, 0x000 },
-    { 0x00000020, 0x0020162d, 0x000 },
-    { 0x00002169, 0x00204411, 0x000 },
-    { 0x00000000, 0x00204804, 0x000 },
-    { 0x00000000, 0x00204805, 0x000 },
-    { 0x00000000, 0x00204801, 0x000 },
-    { 0xcafebabe, 0x00204811, 0x000 },
-    { 0x00000004, 0x00301224, 0x000 },
-    { 0x00000000, 0x002f0064, 0x000 },
-    { 0x00000000, 0x0cc00000, 0x620 },
-    { 0x00000003, 0x00281a22, 0x000 },
-    { 0x00000008, 0x00221222, 0x000 },
-    { 0xfffff000, 0x00281224, 0x000 },
-    { 0x00000000, 0x002910c4, 0x000 },
-    { 0x0000001f, 0x00403624, 0x000 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x00000000, 0x1ac00000, 0x622 },
-    { 0x9f000000, 0x00204411, 0x000 },
-    { 0xcafebabe, 0x00204811, 0x000 },
-    { 0x00000000, 0x1ae00000, 0x625 },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x00000000, 0x1ac00000, 0x627 },
-    { 0x9e000000, 0x00204411, 0x000 },
-    { 0xcafebabe, 0x00204811, 0x000 },
-    { 0x00000000, 0x1ae00000, 0x62a },
-    { 0x00000000, 0x00800000, 0x000 },
-    { 0x00000000, 0x00600000, 0x00b },
-    { 0x00001000, 0x00600411, 0x315 },
-    { 0x00000000, 0x00200411, 0x000 },
-    { 0x00000000, 0x00600811, 0x1b2 },
-    { 0x0000225c, 0x00204411, 0x000 },
-    { 0x00000003, 0x00204811, 0x000 },
-    { 0x00002256, 0x00204411, 0x000 },
-    { 0x0000001b, 0x00204811, 0x000 },
-    { 0x0000a1fc, 0x00204411, 0x000 },
-    { 0x00000001, 0x00204811, 0x000 },
-    { 0x0001a1fd, 0xc0204411, 0x000 },
-    { 0x00000021, 0x00201e2d, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000024, 0x0020222d, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000022, 0x0020222d, 0x000 },
-    { 0x0000ffff, 0x00282228, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x00204811, 0x000 },
-    { 0x00000023, 0x00201e2d, 0x000 },
-    { 0x00000010, 0x00221e27, 0x000 },
-    { 0x00000000, 0x00294907, 0x000 },
-    { 0x00000000, 0x00404811, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x00000000, 0x00000000, 0x000 },
-    { 0x0142050a, 0x05ba0250, 0x000 },
-    { 0x01c30168, 0x044105ba, 0x000 },
-    { 0x02250209, 0x02500151, 0x000 },
-    { 0x02230245, 0x02a00241, 0x000 },
-    { 0x03d705ba, 0x05ba05ba, 0x000 },
-    { 0x05e205e3, 0x031f05ba, 0x000 },
-    { 0x032005bf, 0x0320034a, 0x000 },
-    { 0x03340282, 0x034c033e, 0x000 },
-    { 0x05ba05ba, 0x05ba05ba, 0x000 },
-    { 0x05ba0557, 0x05ba032a, 0x000 },
-    { 0x03bc05ba, 0x04c3034e, 0x000 },
-    { 0x04a20455, 0x043f05ba, 0x000 },
-    { 0x04d805ba, 0x044304e5, 0x000 },
-    { 0x0455050f, 0x035b037b, 0x000 },
-    { 0x05ba05ba, 0x05ba05ba, 0x000 },
-    { 0x05ba05ba, 0x05ba05ba, 0x000 },
-    { 0x05ba05ba, 0x05d805c1, 0x000 },
-    { 0x05ba05ba, 0x000705ba, 0x000 },
-    { 0x05ba05ba, 0x05ba05ba, 0x000 },
-    { 0x05ba05ba, 0x05ba05ba, 0x000 },
-    { 0x03f803ed, 0x04080406, 0x000 },
-    { 0x040e040a, 0x040c0410, 0x000 },
-    { 0x041c0418, 0x04240420, 0x000 },
-    { 0x042c0428, 0x04340430, 0x000 },
-    { 0x05ba05ba, 0x043a0438, 0x000 },
-    { 0x05ba05ba, 0x05ba05ba, 0x000 },
-    { 0x05ba05ba, 0x05ba05ba, 0x000 },
-    { 0x0002060e, 0x062c0006, 0x000 },
-};
-
-static const u32 RS780_pfp_microcode[] = {
-0xca0400,
-0xa00000,
-0x7e828b,
-0x7c038b,
-0x8001db,
-0x7c038b,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xc41838,
-0xca2400,
-0xca2800,
-0x9581cb,
-0xc41c3a,
-0xc3c000,
-0xca0800,
-0xca0c00,
-0x7c744b,
-0xc20005,
-0x99c000,
-0xc41c3a,
-0x7c744c,
-0xc0ffe0,
-0x042c08,
-0x309002,
-0x7d2500,
-0x351402,
-0x7d350b,
-0x255407,
-0x7cd580,
-0x259c07,
-0x95c004,
-0xd5001b,
-0x7eddc1,
-0x7d9d80,
-0xd6801b,
-0xd5801b,
-0xd4401e,
-0xd5401e,
-0xd6401e,
-0xd6801e,
-0xd4801e,
-0xd4c01e,
-0x9783d3,
-0xd5c01e,
-0xca0800,
-0x80001a,
-0xca0c00,
-0xe4011e,
-0xd4001e,
-0x80000c,
-0xc41838,
-0xe4013e,
-0xd4001e,
-0x80000c,
-0xc41838,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0xca0c00,
-0x8001db,
-0xd48024,
-0xca0800,
-0x7c00c0,
-0xc81425,
-0xc81824,
-0x7c9488,
-0x7c9880,
-0xc20003,
-0xd40075,
-0x7c744c,
-0x800064,
-0xd4401e,
-0xca1800,
-0xd4401e,
-0xd5801e,
-0x800062,
-0xd40075,
-0xd4401e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd48019,
-0xd4c018,
-0xd50017,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xe2001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xd40075,
-0xd4401e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd48019,
-0xd4c018,
-0xd50017,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0x248c01,
-0xd48060,
-0x94c003,
-0x041001,
-0x041002,
-0xd50025,
-0xd4401e,
-0x800000,
-0xd4801e,
-0xca0800,
-0xd48061,
-0xd4401e,
-0x800000,
-0xd4801e,
-0xca0800,
-0xca0c00,
-0xd4401e,
-0xd48016,
-0xd4c016,
-0xd4801e,
-0x8001db,
-0xd4c01e,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x948004,
-0xca1400,
-0xe420f3,
-0xd42013,
-0xd56065,
-0xd4e01c,
-0xd5201c,
-0xd5601c,
-0x800000,
-0x062001,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x9483f7,
-0xca1400,
-0xe420f3,
-0x80009c,
-0xd42013,
-0xc60843,
-0xca0c00,
-0xca1000,
-0x9883ef,
-0xca1400,
-0xd40064,
-0x8000b0,
-0x000000,
-0xc41432,
-0xc61843,
-0xc4082f,
-0x954005,
-0xc40c30,
-0xd4401e,
-0x800000,
-0xee001e,
-0x9583f5,
-0xc41031,
-0xd44033,
-0xd52065,
-0xd4a01c,
-0xd4e01c,
-0xd5201c,
-0xe4015e,
-0xd4001e,
-0x800000,
-0x062001,
-0xca1800,
-0x0a2001,
-0xd60076,
-0xc40836,
-0x988007,
-0xc61045,
-0x950110,
-0xd4001f,
-0xd46062,
-0x800000,
-0xd42062,
-0xcc3835,
-0xcc1433,
-0x8401de,
-0xd40072,
-0xd5401e,
-0x800000,
-0xee001e,
-0xe2001a,
-0x8401de,
-0xe2001a,
-0xcc104b,
-0xcc0447,
-0x2c9401,
-0x7d098b,
-0x984005,
-0x7d15cb,
-0xd4001a,
-0x8001db,
-0xd4006d,
-0x344401,
-0xcc0c48,
-0x98403a,
-0xcc2c4a,
-0x958004,
-0xcc0449,
-0x8001db,
-0xd4001a,
-0xd4c01a,
-0x282801,
-0x840113,
-0xcc1003,
-0x98801b,
-0x04380c,
-0x840113,
-0xcc1003,
-0x988017,
-0x043808,
-0x840113,
-0xcc1003,
-0x988013,
-0x043804,
-0x840113,
-0xcc1003,
-0x988014,
-0xcc104c,
-0x9a8009,
-0xcc144d,
-0x9840dc,
-0xd4006d,
-0xcc1848,
-0xd5001a,
-0xd5401a,
-0x8000ec,
-0xd5801a,
-0x96c0d5,
-0xd4006d,
-0x8001db,
-0xd4006e,
-0x9ac003,
-0xd4006d,
-0xd4006e,
-0x800000,
-0xec007f,
-0x9ac0cc,
-0xd4006d,
-0x8001db,
-0xd4006e,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0x7d9103,
-0x7dd583,
-0x7d190c,
-0x35cc1f,
-0x35701f,
-0x7cf0cb,
-0x7cd08b,
-0x880000,
-0x7e8e8b,
-0x95c004,
-0xd4006e,
-0x8001db,
-0xd4001a,
-0xd4c01a,
-0xcc0803,
-0xcc0c03,
-0xcc1003,
-0xcc1403,
-0xcc1803,
-0xcc1c03,
-0xcc2403,
-0xcc2803,
-0x35c41f,
-0x36b01f,
-0x7c704b,
-0x34f01f,
-0x7c704b,
-0x35701f,
-0x7c704b,
-0x7d8881,
-0x7dccc1,
-0x7e5101,
-0x7e9541,
-0x7c9082,
-0x7cd4c2,
-0x7c848b,
-0x9ac003,
-0x7c8c8b,
-0x2c8801,
-0x98809e,
-0xd4006d,
-0x98409c,
-0xd4006e,
-0xcc084c,
-0xcc0c4d,
-0xcc1048,
-0xd4801a,
-0xd4c01a,
-0x800124,
-0xd5001a,
-0xcc0832,
-0xd40032,
-0x9482b6,
-0xca0c00,
-0xd4401e,
-0x800000,
-0xd4001e,
-0xe4011e,
-0xd4001e,
-0xca0800,
-0xca0c00,
-0xca1000,
-0xd4401e,
-0xca1400,
-0xd4801e,
-0xd4c01e,
-0xd5001e,
-0xd5401e,
-0xd54034,
-0x800000,
-0xee001e,
-0x280404,
-0xe2001a,
-0xe2001a,
-0xd4401a,
-0xca3800,
-0xcc0803,
-0xcc0c03,
-0xcc0c03,
-0xcc0c03,
-0x98829a,
-0x000000,
-0x8401de,
-0xd7a06f,
-0x800000,
-0xee001f,
-0xca0400,
-0xc2ff00,
-0xcc0834,
-0xc13fff,
-0x7c74cb,
-0x7cc90b,
-0x7d010f,
-0x99028d,
-0x7c738b,
-0x8401de,
-0xd7a06f,
-0x800000,
-0xee001f,
-0xca0800,
-0x281900,
-0x7d898b,
-0x958014,
-0x281404,
-0xca0c00,
-0xca1000,
-0xca1c00,
-0xca2400,
-0xe2001f,
-0xd4c01a,
-0xd5001a,
-0xd5401a,
-0xcc1803,
-0xcc2c03,
-0xcc2c03,
-0xcc2c03,
-0x7da58b,
-0x7d9c47,
-0x984274,
-0x000000,
-0x800184,
-0xd4c01a,
-0xd4401e,
-0xd4801e,
-0x800000,
-0xee001e,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xe4013e,
-0xd4001e,
-0xd4401e,
-0xee001e,
-0xca0400,
-0xa00000,
-0x7e828b,
-0xca0800,
-0x248c06,
-0x0ccc06,
-0x98c006,
-0xcc104e,
-0x990004,
-0xd40073,
-0xe4011e,
-0xd4001e,
-0xd4401e,
-0xd4801e,
-0x800000,
-0xee001e,
-0xca0800,
-0xca0c00,
-0x34d018,
-0x251001,
-0x950021,
-0xc17fff,
-0xca1000,
-0xca1400,
-0xca1800,
-0xd4801d,
-0xd4c01d,
-0x7db18b,
-0xc14202,
-0xc2c001,
-0xd5801d,
-0x34dc0e,
-0x7d5d4c,
-0x7f734c,
-0xd7401e,
-0xd5001e,
-0xd5401e,
-0xc14200,
-0xc2c000,
-0x099c01,
-0x31dc10,
-0x7f5f4c,
-0x7f734c,
-0x042802,
-0x7d8380,
-0xd5a86f,
-0xd58066,
-0xd7401e,
-0xec005e,
-0xc82402,
-0xc82402,
-0x8001db,
-0xd60076,
-0xd4401e,
-0xd4801e,
-0xd4c01e,
-0x800000,
-0xee001e,
-0x800000,
-0xee001f,
-0xd4001f,
-0x800000,
-0xd4001f,
-0xd4001f,
-0x880000,
-0xd4001f,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x000000,
-0x010194,
-0x02019b,
-0x0300b2,
-0x0400a2,
-0x050003,
-0x06003f,
-0x070032,
-0x08014f,
-0x090046,
-0x0a0036,
-0x1001d9,
-0x1700c5,
-0x22015d,
-0x23016c,
-0x2000d7,
-0x240148,
-0x26004d,
-0x27005c,
-0x28008d,
-0x290051,
-0x2a007e,
-0x2b0061,
-0x2f0088,
-0x3200aa,
-0x3401a2,
-0x36006f,
-0x3c0179,
-0x3f0095,
-0x4101af,
-0x440151,
-0x550196,
-0x56019d,
-0x60000b,
-0x610034,
-0x620038,
-0x630038,
-0x640038,
-0x650038,
-0x660038,
-0x670038,
-0x68003a,
-0x690041,
-0x6a0048,
-0x6b0048,
-0x6c0048,
-0x6d0048,
-0x6e0048,
-0x6f0048,
-0x7301d9,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-0x000006,
-};
-
-static const u32 RV770_cp_microcode[] = {
-0xcc0003ea,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x80000001,
-0xd040007f,
-0x80000001,
-0xcc400041,
-0x7c40c000,
-0xc0160004,
-0x30d03fff,
-0x7d15000c,
-0xcc110000,
-0x28d8001e,
-0x31980001,
-0x28dc001f,
-0xc8200004,
-0x95c00006,
-0x7c424000,
-0xcc000062,
-0x7e56800c,
-0xcc290000,
-0xc8240004,
-0x7e26000b,
-0x95800006,
-0x7c42c000,
-0xcc000062,
-0x7ed7000c,
-0xcc310000,
-0xc82c0004,
-0x7e2e000c,
-0xcc000062,
-0x31103fff,
-0x80000001,
-0xce110000,
-0x7c40c000,
-0x80000001,
-0xcc400040,
-0x80000001,
-0xcc412257,
-0x7c418000,
-0xcc400045,
-0xcc400048,
-0xcc41225c,
-0xcc41a1fc,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xcc400045,
-0xcc400048,
-0x7c40c000,
-0xcc41225c,
-0xcc41a1fc,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xcc000045,
-0xcc000048,
-0xcc41225c,
-0xcc41a1fc,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x040ca1fd,
-0xc0120001,
-0xcc000045,
-0xcc000048,
-0x7cd0c00c,
-0xcc41225c,
-0xcc41a1fc,
-0xd04d0000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x80000001,
-0xcc41225d,
-0x7c408000,
-0x7c40c000,
-0xc02a0002,
-0x7c410000,
-0x7d29000c,
-0x30940001,
-0x30980006,
-0x309c0300,
-0x29dc0008,
-0x7c420000,
-0x7c424000,
-0x9540000f,
-0xc02e0004,
-0x05f02258,
-0x7f2f000c,
-0xcc310000,
-0xc8280004,
-0xccc12169,
-0xcd01216a,
-0xce81216b,
-0x0db40002,
-0xcc01216c,
-0x9740000e,
-0x0db40000,
-0x8000007b,
-0xc834000a,
-0x0db40002,
-0x97400009,
-0x0db40000,
-0xc02e0004,
-0x05f02258,
-0x7f2f000c,
-0xcc310000,
-0xc8280004,
-0x8000007b,
-0xc834000a,
-0x97400004,
-0x7e028000,
-0x8000007b,
-0xc834000a,
-0x0db40004,
-0x9740ff8c,
-0x00000000,
-0xce01216d,
-0xce41216e,
-0xc8280003,
-0xc834000a,
-0x9b400004,
-0x043c0005,
-0x8400026d,
-0xcc000062,
-0x0df40000,
-0x9740000b,
-0xc82c03e6,
-0xce81a2b7,
-0xc0300006,
-0x7ef34028,
-0xc0300020,
-0x7f6b8020,
-0x7fb3c029,
-0xcf81a2c4,
-0x80000001,
-0xcfc1a2d1,
-0x0df40001,
-0x9740000b,
-0xc82c03e7,
-0xce81a2bb,
-0xc0300006,
-0x7ef34028,
-0xc0300020,
-0x7f6b8020,
-0x7fb3c029,
-0xcf81a2c5,
-0x80000001,
-0xcfc1a2d2,
-0x0df40002,
-0x9740000b,
-0xc82c03e8,
-0xce81a2bf,
-0xc0300006,
-0x7ef34028,
-0xc0300020,
-0x7f6b8020,
-0x7fb3c029,
-0xcf81a2c6,
-0x80000001,
-0xcfc1a2d3,
-0xc82c03e9,
-0xce81a2c3,
-0xc0300006,
-0x7ef34028,
-0xc0300020,
-0x7f6b8020,
-0x7fb3c029,
-0xcf81a2c7,
-0x80000001,
-0xcfc1a2d4,
-0x80000001,
-0xcc400042,
-0x7c40c000,
-0x7c410000,
-0x2914001d,
-0x31540001,
-0x9940000d,
-0x31181000,
-0xc81c0011,
-0x09dc0001,
-0x95c0ffff,
-0xc81c0011,
-0xccc12100,
-0xcd012101,
-0xccc12102,
-0xcd012103,
-0x04180004,
-0x8000039f,
-0xcd81a2a4,
-0xc02a0004,
-0x95800008,
-0x36a821a3,
-0xcc290000,
-0xc8280004,
-0xc81c0011,
-0x0de40040,
-0x9640ffff,
-0xc81c0011,
-0xccc12170,
-0xcd012171,
-0xc8200012,
-0x96000000,
-0xc8200012,
-0x8000039f,
-0xcc000064,
-0x7c40c000,
-0x7c410000,
-0xcc000045,
-0xcc000048,
-0x40d40003,
-0xcd41225c,
-0xcd01a1fc,
-0xc01a0001,
-0x041ca1fd,
-0x7dd9c00c,
-0x7c420000,
-0x08cc0001,
-0x06240001,
-0x06280002,
-0xce1d0000,
-0xce5d0000,
-0x98c0fffa,
-0xce9d0000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x7c40c000,
-0x30d00001,
-0x28cc0001,
-0x7c414000,
-0x95000006,
-0x7c418000,
-0xcd41216d,
-0xcd81216e,
-0x800000f3,
-0xc81c0003,
-0xc0220004,
-0x7e16000c,
-0xcc210000,
-0xc81c0004,
-0x7c424000,
-0x98c00004,
-0x7c428000,
-0x80000001,
-0xcde50000,
-0xce412169,
-0xce81216a,
-0xcdc1216b,
-0x80000001,
-0xcc01216c,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0x7c41c000,
-0x28a40008,
-0x326400ff,
-0x0e68003c,
-0x9680000a,
-0x7c020000,
-0x7c420000,
-0x1e300003,
-0xcc00006a,
-0x9b000003,
-0x42200005,
-0x04200040,
-0x80000110,
-0x7c024000,
-0x7e024000,
-0x9a400000,
-0x0a640001,
-0x30ec0010,
-0x9ac0000a,
-0xcc000062,
-0xc02a0004,
-0xc82c0021,
-0x7e92800c,
-0xcc000041,
-0xcc290000,
-0xcec00021,
-0x80000120,
-0xc8300004,
-0xcd01216d,
-0xcd41216e,
-0xc8300003,
-0x7f1f000b,
-0x30f40007,
-0x27780001,
-0x9740002a,
-0x07b80125,
-0x9f800000,
-0x00000000,
-0x80000135,
-0x7f1b8004,
-0x80000139,
-0x7f1b8005,
-0x8000013d,
-0x7f1b8002,
-0x80000141,
-0x7f1b8003,
-0x80000145,
-0x7f1b8007,
-0x80000149,
-0x7f1b8006,
-0x8000014e,
-0x28a40008,
-0x9b800019,
-0x28a40008,
-0x8000015e,
-0x326400ff,
-0x9b800015,
-0x28a40008,
-0x8000015e,
-0x326400ff,
-0x9b800011,
-0x28a40008,
-0x8000015e,
-0x326400ff,
-0x9b80000d,
-0x28a40008,
-0x8000015e,
-0x326400ff,
-0x9b800009,
-0x28a40008,
-0x8000015e,
-0x326400ff,
-0x9b800005,
-0x28a40008,
-0x8000015e,
-0x326400ff,
-0x28a40008,
-0x326400ff,
-0x0e68003c,
-0x9a80feb1,
-0x28ec0008,
-0x7c434000,
-0x7c438000,
-0x7c43c000,
-0x96c00007,
-0xcc000062,
-0xcf412169,
-0xcf81216a,
-0xcfc1216b,
-0x80000001,
-0xcc01216c,
-0x80000001,
-0xcff50000,
-0xcc00006b,
-0x840003a2,
-0x0e68003c,
-0x9a800004,
-0xc8280015,
-0x80000001,
-0xd040007f,
-0x9680ffab,
-0x7e024000,
-0x8400023b,
-0xc00e0002,
-0xcc000041,
-0x80000239,
-0xccc1304a,
-0x7c40c000,
-0x7c410000,
-0xc01e0001,
-0x29240012,
-0xc0220002,
-0x96400005,
-0xc0260004,
-0xc027fffb,
-0x7d25000b,
-0xc0260000,
-0x7dd2800b,
-0x7e12c00b,
-0x7d25000c,
-0x7c414000,
-0x7c418000,
-0xccc12169,
-0x9a80000a,
-0xcd01216a,
-0xcd41216b,
-0x96c0fe82,
-0xcd81216c,
-0xc8300018,
-0x97000000,
-0xc8300018,
-0x80000001,
-0xcc000018,
-0x840003a2,
-0xcc00007f,
-0xc8140013,
-0xc8180014,
-0xcd41216b,
-0x96c0fe76,
-0xcd81216c,
-0x80000182,
-0xc8300018,
-0xc80c0008,
-0x98c00000,
-0xc80c0008,
-0x7c410000,
-0x95000002,
-0x00000000,
-0x7c414000,
-0xc8200009,
-0xcc400043,
-0xce01a1f4,
-0xcc400044,
-0xc00e8000,
-0x7c424000,
-0x7c428000,
-0x2aac001f,
-0x96c0fe63,
-0xc035f000,
-0xce4003e2,
-0x32780003,
-0x267c0008,
-0x7ff7c00b,
-0x7ffbc00c,
-0x2a780018,
-0xcfc003e3,
-0xcf8003e4,
-0x26b00002,
-0x7f3f0000,
-0xcf0003e5,
-0x8000031f,
-0x7c80c000,
-0x7c40c000,
-0x28d00008,
-0x3110000f,
-0x9500000f,
-0x25280001,
-0x06a801b3,
-0x9e800000,
-0x00000000,
-0x800001d4,
-0xc0120800,
-0x800001e2,
-0xc814000f,
-0x800001e9,
-0xc8140010,
-0x800001f0,
-0xccc1a2a4,
-0x800001f9,
-0xc8140011,
-0x30d0003f,
-0x0d280015,
-0x9a800012,
-0x0d28001e,
-0x9a80001e,
-0x0d280020,
-0x9a800023,
-0x0d24000f,
-0x0d280010,
-0x7e6a800c,
-0x9a800026,
-0x0d200004,
-0x0d240014,
-0x0d280028,
-0x7e62400c,
-0x7ea6800c,
-0x9a80002a,
-0xc8140011,
-0x80000001,
-0xccc1a2a4,
-0xc0120800,
-0x7c414000,
-0x7d0cc00c,
-0xc0120008,
-0x29580003,
-0x295c000c,
-0x7c420000,
-0x7dd1c00b,
-0x26200014,
-0x7e1e400c,
-0x7e4e800c,
-0xce81a2a4,
-0x80000001,
-0xcd81a1fe,
-0xc814000f,
-0x0410210e,
-0x95400000,
-0xc814000f,
-0xd0510000,
-0x80000001,
-0xccc1a2a4,
-0xc8140010,
-0x04102108,
-0x95400000,
-0xc8140010,
-0xd0510000,
-0x80000001,
-0xccc1a2a4,
-0xccc1a2a4,
-0x04100001,
-0xcd000019,
-0x840003a2,
-0xcc00007f,
-0xc8100019,
-0x99000000,
-0xc8100019,
-0x80000002,
-0x7c408000,
-0x04102100,
-0x09540001,
-0x9540ffff,
-0xc8140011,
-0xd0510000,
-0x8000039f,
-0xccc1a2a4,
-0x7c40c000,
-0xcc40000d,
-0x94c0fdff,
-0xcc40000e,
-0x7c410000,
-0x95000005,
-0x08cc0001,
-0xc8140005,
-0x99400014,
-0x00000000,
-0x98c0fffb,
-0x7c410000,
-0x80000002,
-0x7d008000,
-0xc8140005,
-0x7c40c000,
-0x9940000c,
-0xc818000c,
-0x7c410000,
-0x9580fdee,
-0xc820000e,
-0xc81c000d,
-0x66200020,
-0x7e1e002c,
-0x25240002,
-0x7e624020,
-0x80000001,
-0xcce60000,
-0x7c410000,
-0xcc00006c,
-0xcc00006d,
-0xc818001f,
-0xc81c001e,
-0x65980020,
-0x7dd9c02c,
-0x7cd4c00c,
-0xccde0000,
-0x45dc0004,
-0xc8280017,
-0x9680000f,
-0xc00e0001,
-0x28680008,
-0x2aac0016,
-0x32a800ff,
-0x0eb00049,
-0x7f2f000b,
-0x97000006,
-0x00000000,
-0xc8140005,
-0x7c40c000,
-0x80000223,
-0x7c410000,
-0x80000226,
-0xd040007f,
-0x8400023b,
-0xcc000041,
-0xccc1304a,
-0x94000000,
-0xc83c001a,
-0x043c0005,
-0xcfc1a2a4,
-0xc0361f90,
-0xc0387fff,
-0x7c03c010,
-0x7f7b400c,
-0xcf41217c,
-0xcfc1217d,
-0xcc01217e,
-0xc03a0004,
-0x0434217f,
-0x7f7b400c,
-0xcc350000,
-0xc83c0004,
-0x2bfc001f,
-0x04380020,
-0x97c00005,
-0xcc000062,
-0x9b800000,
-0x0bb80001,
-0x80000247,
-0xcc000071,
-0xcc01a1f4,
-0x04380016,
-0xc0360002,
-0xcf81a2a4,
-0x88000000,
-0xcf412010,
-0x7c40c000,
-0x28d0001c,
-0x95000005,
-0x04d40001,
-0xcd400065,
-0x80000001,
-0xcd400068,
-0x09540002,
-0x80000001,
-0xcd400066,
-0x8400026c,
-0xc81803ea,
-0x7c40c000,
-0x9980fd9d,
-0xc8140016,
-0x08d00001,
-0x9940002b,
-0xcd000068,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x043c0005,
-0xcfc1a2a4,
-0xcc01a1f4,
-0x840003a2,
-0xcc000046,
-0x88000000,
-0xcc00007f,
-0x8400027e,
-0xc81803ea,
-0x7c40c000,
-0x9980fd8b,
-0xc8140016,
-0x08d00001,
-0x99400019,
-0xcd000068,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x043c0022,
-0xcfc1a2a4,
-0x840003a2,
-0xcc000047,
-0x88000000,
-0xcc00007f,
-0xc8100016,
-0x9900000d,
-0xcc400067,
-0x80000002,
-0x7c408000,
-0xc81803ea,
-0x9980fd77,
-0x7c40c000,
-0x94c00003,
-0xc8100016,
-0x99000004,
-0xccc00068,
-0x80000002,
-0x7c408000,
-0x8400023b,
-0xc0148000,
-0xcc000041,
-0xcd41304a,
-0xc0148000,
-0x99000000,
-0xc8100016,
-0x80000002,
-0x7c408000,
-0xc0120001,
-0x7c51400c,
-0x80000001,
-0xd0550000,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0x291c001f,
-0xccc0004a,
-0xcd00004b,
-0x95c00003,
-0xc01c8000,
-0xcdc12010,
-0xdd830000,
-0x055c2000,
-0xcc000062,
-0x80000001,
-0xd81f4100,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0xccc0004c,
-0xcd00004d,
-0xdd830000,
-0x055ca000,
-0x80000001,
-0xd81f4100,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0xccc0004e,
-0xcd00004f,
-0xdd830000,
-0x055cc000,
-0x80000001,
-0xd81f4100,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0xccc00050,
-0xcd000051,
-0xdd830000,
-0x055cf8e0,
-0x80000001,
-0xd81f4100,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0xccc00052,
-0xcd000053,
-0xdd830000,
-0x055cf880,
-0x80000001,
-0xd81f4100,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0xccc00054,
-0xcd000055,
-0xdd830000,
-0x055ce000,
-0x80000001,
-0xd81f4100,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0xccc00056,
-0xcd000057,
-0xdd830000,
-0x055cf000,
-0x80000001,
-0xd81f4100,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0xccc00058,
-0xcd000059,
-0xdd830000,
-0x055cf3fc,
-0x80000001,
-0xd81f4100,
-0xd0432000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xd043a000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xd043c000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xd043f8e0,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xd043f880,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xd043e000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xd043f000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xd043f3fc,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xc81403e0,
-0xcc430000,
-0xcc430000,
-0xcc430000,
-0x7d45c000,
-0xcdc30000,
-0xd0430000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x7c40c000,
-0xc81003e2,
-0xc81403e5,
-0xc81803e3,
-0xc81c03e4,
-0xcd812169,
-0xcdc1216a,
-0xccc1216b,
-0xcc01216c,
-0x04200004,
-0x7da18000,
-0x7d964002,
-0x9640fcd7,
-0xcd8003e3,
-0x31280003,
-0xc02df000,
-0x25180008,
-0x7dad800b,
-0x7da9800c,
-0x80000001,
-0xcd8003e3,
-0x308cffff,
-0xd04d0000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x7c40c000,
-0x7c410000,
-0x29240018,
-0x32640001,
-0x9a400013,
-0xc8140020,
-0x15580002,
-0x9580ffff,
-0xc8140020,
-0xcc00006e,
-0xccc12180,
-0xcd01218d,
-0xcc412181,
-0x2914001f,
-0x34588000,
-0xcd81218c,
-0x9540fcb9,
-0xcc412182,
-0xc8140020,
-0x9940ffff,
-0xc8140020,
-0x80000002,
-0x7c408000,
-0x7c414000,
-0x7c418000,
-0x7c41c000,
-0x65b40020,
-0x7f57402c,
-0xd4378100,
-0x47740004,
-0xd4378100,
-0x47740004,
-0xd4378100,
-0x47740004,
-0x09dc0004,
-0xd4378100,
-0x99c0fff8,
-0x47740004,
-0x2924001f,
-0xc0380019,
-0x9640fca1,
-0xc03e0004,
-0xcf8121f8,
-0x37e021f9,
-0xcc210000,
-0xc8200004,
-0x2a200018,
-0x32200001,
-0x9a00fffb,
-0xcf8121f8,
-0x80000002,
-0x7c408000,
-0x7c40c000,
-0x28d00018,
-0x31100001,
-0xc0160080,
-0x95000003,
-0xc02a0004,
-0x7cd4c00c,
-0xccc1217c,
-0xcc41217d,
-0xcc41217e,
-0x7c418000,
-0x1db00003,
-0x36a0217f,
-0x9b000003,
-0x419c0005,
-0x041c0040,
-0x99c00000,
-0x09dc0001,
-0xcc210000,
-0xc8240004,
-0x2a6c001f,
-0x419c0005,
-0x9ac0fffa,
-0xcc800062,
-0x80000002,
-0x7c408000,
-0x7c40c000,
-0x04d403e6,
-0x80000001,
-0xcc540000,
-0x8000039f,
-0xcc4003ea,
-0xc01c8000,
-0x044ca000,
-0xcdc12010,
-0x7c410000,
-0xc8140009,
-0x04180000,
-0x041c0008,
-0xcd800071,
-0x09dc0001,
-0x05980001,
-0xcd0d0000,
-0x99c0fffc,
-0xcc800062,
-0x8000039f,
-0xcd400071,
-0xc00e0100,
-0xcc000041,
-0xccc1304a,
-0xc83c007f,
-0xcc00007f,
-0x80000001,
-0xcc00007f,
-0xcc00007f,
-0x88000000,
-0xcc00007f,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00010333,
-0x00100004,
-0x00170006,
-0x00210008,
-0x00270028,
-0x00280023,
-0x00290029,
-0x002a0026,
-0x002b0029,
-0x002d0038,
-0x002e003f,
-0x002f004a,
-0x0034004c,
-0x00360030,
-0x003900af,
-0x003a00d0,
-0x003b00e5,
-0x003c00fd,
-0x003d016c,
-0x003f00ad,
-0x00410338,
-0x0043036c,
-0x0044018f,
-0x004500fd,
-0x004601ad,
-0x004701ad,
-0x00480200,
-0x0049020e,
-0x004a0257,
-0x004b0284,
-0x00520261,
-0x00530273,
-0x00540289,
-0x0057029b,
-0x0060029f,
-0x006102ae,
-0x006202b8,
-0x006302c2,
-0x006402cc,
-0x006502d6,
-0x006602e0,
-0x006702ea,
-0x006802f4,
-0x006902f8,
-0x006a02fc,
-0x006b0300,
-0x006c0304,
-0x006d0308,
-0x006e030c,
-0x006f0310,
-0x00700314,
-0x00720386,
-0x0074038c,
-0x0079038a,
-0x007c031e,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-0x000f039b,
-};
-
-static const u32 RV770_pfp_microcode[] = {
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0x80000000,
-0xdc030000,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xc818000e,
-0x31980001,
-0x7c424000,
-0x95800252,
-0x7c428000,
-0xc81c001c,
-0xc037c000,
-0x7c40c000,
-0x7c410000,
-0x7cb4800b,
-0xc0360003,
-0x99c00000,
-0xc81c001c,
-0x7cb4800c,
-0x24d40002,
-0x7d654000,
-0xcd400043,
-0xce800043,
-0xcd000043,
-0xcc800040,
-0xce400040,
-0xce800040,
-0xccc00040,
-0xdc3a0000,
-0x9780ffde,
-0xcd000040,
-0x7c40c000,
-0x80000018,
-0x7c410000,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xc818000e,
-0x8000000c,
-0x31980002,
-0xd40003c0,
-0xd4000fc0,
-0xd4000fa2,
-0xc818000e,
-0x288c0008,
-0x30cc000f,
-0x34100001,
-0x7d0d0008,
-0x8000000c,
-0x7d91800b,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xd40003c0,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xcc4003f9,
-0x80000261,
-0xcc4003f8,
-0xc82003f8,
-0xc81c03f9,
-0xc81803fb,
-0xc037ffff,
-0x7c414000,
-0xcf41a29e,
-0x66200020,
-0x7de1c02c,
-0x7d58c008,
-0x7cdcc020,
-0x68d00020,
-0xc0360003,
-0xcc000054,
-0x7cb4800c,
-0x8000006a,
-0xcc800040,
-0x7c418000,
-0xcd81a29e,
-0xcc800040,
-0xcd800040,
-0x80000068,
-0xcc000054,
-0xc019ffff,
-0xcc800040,
-0xcd81a29e,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0xccc1a1fa,
-0xcd01a1f9,
-0xcd41a29d,
-0xccc00040,
-0xcd000040,
-0xcd400040,
-0xcc400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xcc000054,
-0xcc800040,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0xccc1a1fa,
-0xcd01a1f9,
-0xcd41a29d,
-0xccc00040,
-0xcd000040,
-0xcd400040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0x7c40c000,
-0x30d00001,
-0xccc1a29f,
-0x95000003,
-0x04140001,
-0x04140002,
-0xcd4003fb,
-0xcc800040,
-0x80000000,
-0xccc00040,
-0x7c40c000,
-0xcc800040,
-0xccc1a2a2,
-0x80000000,
-0xccc00040,
-0x7c40c000,
-0x28d4001f,
-0xcc800040,
-0x95400003,
-0x7c410000,
-0xccc00057,
-0x2918001f,
-0xccc00040,
-0x95800003,
-0xcd000040,
-0xcd000058,
-0x80000261,
-0xcc00007f,
-0xc8200017,
-0xc8300022,
-0x9a000006,
-0x0e280001,
-0xc824001e,
-0x0a640001,
-0xd4001240,
-0xce400040,
-0xc036c000,
-0x96800007,
-0x37747900,
-0x041c0001,
-0xcf400040,
-0xcdc00040,
-0xcf0003fa,
-0x7c030000,
-0xca0c0010,
-0x7c410000,
-0x94c00004,
-0x7c414000,
-0xd42002c4,
-0xcde00044,
-0x9b00000b,
-0x7c418000,
-0xcc00004b,
-0xcda00049,
-0xcd200041,
-0xcd600041,
-0xcda00041,
-0x06200001,
-0xce000056,
-0x80000261,
-0xcc00007f,
-0xc8280020,
-0xc82c0021,
-0xcc000063,
-0x7eea4001,
-0x65740020,
-0x7f53402c,
-0x269c0002,
-0x7df5c020,
-0x69f80020,
-0xce80004b,
-0xce600049,
-0xcde00041,
-0xcfa00041,
-0xce600041,
-0x271c0002,
-0x7df5c020,
-0x69f80020,
-0x7db24001,
-0xcf00004b,
-0xce600049,
-0xcde00041,
-0xcfa00041,
-0x800000bd,
-0xce600041,
-0xc8200017,
-0xc8300022,
-0x9a000006,
-0x0e280001,
-0xc824001e,
-0x0a640001,
-0xd4001240,
-0xce400040,
-0xca0c0010,
-0x7c410000,
-0x94c0000b,
-0xc036c000,
-0x96800007,
-0x37747900,
-0x041c0001,
-0xcf400040,
-0xcdc00040,
-0xcf0003fa,
-0x7c030000,
-0x800000b6,
-0x7c414000,
-0xcc000048,
-0x800000ef,
-0x00000000,
-0xc8200017,
-0xc81c0023,
-0x0e240002,
-0x99c00015,
-0x7c418000,
-0x0a200001,
-0xce000056,
-0xd4000440,
-0xcc000040,
-0xc036c000,
-0xca140013,
-0x96400007,
-0x37747900,
-0xcf400040,
-0xcc000040,
-0xc83003fa,
-0x80000104,
-0xcf000022,
-0xcc000022,
-0x9540015d,
-0xcc00007f,
-0xcca00046,
-0x80000000,
-0xcc200046,
-0x80000261,
-0xcc000064,
-0xc8200017,
-0xc810001f,
-0x96000005,
-0x09100001,
-0xd4000440,
-0xcd000040,
-0xcd000022,
-0xcc800040,
-0xd0400040,
-0xc80c0025,
-0x94c0feeb,
-0xc8100008,
-0xcd000040,
-0xd4000fc0,
-0x80000000,
-0xd4000fa2,
-0x7c40c000,
-0x7c410000,
-0xccc003fd,
-0xcd0003fc,
-0xccc00042,
-0xcd000042,
-0x2914001f,
-0x29180010,
-0x31980007,
-0x3b5c0001,
-0x7d76000b,
-0x99800005,
-0x7d5e400b,
-0xcc000042,
-0x80000261,
-0xcc00004d,
-0x29980001,
-0x292c0008,
-0x9980003d,
-0x32ec0001,
-0x96000004,
-0x2930000c,
-0x80000261,
-0xcc000042,
-0x04140010,
-0xcd400042,
-0x33300001,
-0x34280001,
-0x8400015e,
-0xc8140003,
-0x9b40001b,
-0x0438000c,
-0x8400015e,
-0xc8140003,
-0x9b400017,
-0x04380008,
-0x8400015e,
-0xc8140003,
-0x9b400013,
-0x04380004,
-0x8400015e,
-0xc8140003,
-0x9b400015,
-0xc80c03fd,
-0x9a800009,
-0xc81003fc,
-0x9b000118,
-0xcc00004d,
-0x04140010,
-0xccc00042,
-0xcd000042,
-0x80000136,
-0xcd400042,
-0x96c00111,
-0xcc00004d,
-0x80000261,
-0xcc00004e,
-0x9ac00003,
-0xcc00004d,
-0xcc00004e,
-0xdf830000,
-0x80000000,
-0xd80301ff,
-0x9ac00107,
-0xcc00004d,
-0x80000261,
-0xcc00004e,
-0xc8180003,
-0xc81c0003,
-0xc8200003,
-0x7d5d4003,
-0x7da1c003,
-0x7d5d400c,
-0x2a10001f,
-0x299c001f,
-0x7d1d000b,
-0x7d17400b,
-0x88000000,
-0x7e92800b,
-0x96400004,
-0xcc00004e,
-0x80000261,
-0xcc000042,
-0x04380008,
-0xcf800042,
-0xc8080003,
-0xc80c0003,
-0xc8100003,
-0xc8140003,
-0xc8180003,
-0xc81c0003,
-0xc8240003,
-0xc8280003,
-0x29fc001f,
-0x2ab0001f,
-0x7ff3c00b,
-0x28f0001f,
-0x7ff3c00b,
-0x2970001f,
-0x7ff3c00b,
-0x7d888001,
-0x7dccc001,
-0x7e510001,
-0x7e954001,
-0x7c908002,
-0x7cd4c002,
-0x7cbc800b,
-0x9ac00003,
-0x7c8f400b,
-0x38b40001,
-0x9b4000d8,
-0xcc00004d,
-0x9bc000d6,
-0xcc00004e,
-0xc80c03fd,
-0xc81003fc,
-0xccc00042,
-0x8000016f,
-0xcd000042,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xcc400040,
-0xcc400040,
-0xcc400040,
-0x7c40c000,
-0xccc00040,
-0xccc0000d,
-0x80000000,
-0xd0400040,
-0x7c40c000,
-0x7c410000,
-0x65140020,
-0x7d4d402c,
-0x24580002,
-0x7d598020,
-0x7c41c000,
-0xcd800042,
-0x69980020,
-0xcd800042,
-0xcdc00042,
-0xc023c000,
-0x05e40002,
-0x7ca0800b,
-0x26640010,
-0x7ca4800c,
-0xcc800040,
-0xcdc00040,
-0xccc00040,
-0x95c0000e,
-0xcd000040,
-0x09dc0001,
-0xc8280003,
-0x96800008,
-0xce800040,
-0xc834001d,
-0x97400000,
-0xc834001d,
-0x26a80008,
-0x84000264,
-0xcc2b0000,
-0x99c0fff7,
-0x09dc0001,
-0xdc3a0000,
-0x97800004,
-0x7c418000,
-0x800001a3,
-0x25980002,
-0xa0000000,
-0x7d808000,
-0xc818001d,
-0x7c40c000,
-0x64d00008,
-0x95800000,
-0xc818001d,
-0xcc130000,
-0xcc800040,
-0xccc00040,
-0x80000000,
-0xcc400040,
-0xc810001f,
-0x7c40c000,
-0xcc800040,
-0x7cd1400c,
-0xcd400040,
-0x05180001,
-0x80000000,
-0xcd800022,
-0x7c40c000,
-0x64500020,
-0x84000264,
-0xcc000061,
-0x7cd0c02c,
-0xc8200017,
-0xc8d60000,
-0x99400008,
-0x7c438000,
-0xdf830000,
-0xcfa0004f,
-0x84000264,
-0xcc000062,
-0x80000000,
-0xd040007f,
-0x80000261,
-0xcc000062,
-0x84000264,
-0xcc000061,
-0xc8200017,
-0x7c40c000,
-0xc036ff00,
-0xc810000d,
-0xc0303fff,
-0x7cf5400b,
-0x7d51800b,
-0x7d81800f,
-0x99800008,
-0x7cf3800b,
-0xdf830000,
-0xcfa0004f,
-0x84000264,
-0xcc000062,
-0x80000000,
-0xd040007f,
-0x80000261,
-0xcc000062,
-0x84000264,
-0x7c40c000,
-0x28dc0008,
-0x95c00019,
-0x30dc0010,
-0x7c410000,
-0x99c00004,
-0x64540020,
-0x80000209,
-0xc91d0000,
-0x7d15002c,
-0xc91e0000,
-0x7c420000,
-0x7c424000,
-0x7c418000,
-0x7de5c00b,
-0x7de28007,
-0x9a80000e,
-0x41ac0005,
-0x9ac00000,
-0x0aec0001,
-0x30dc0010,
-0x99c00004,
-0x00000000,
-0x8000020c,
-0xc91d0000,
-0x8000020c,
-0xc91e0000,
-0xcc800040,
-0xccc00040,
-0xd0400040,
-0xc80c0025,
-0x94c0fde3,
-0xc8100008,
-0xcd000040,
-0xd4000fc0,
-0x80000000,
-0xd4000fa2,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xd40003c0,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0x7c40c000,
-0x30d00006,
-0x0d100006,
-0x99000007,
-0xc8140015,
-0x99400005,
-0xcc000052,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xccc00040,
-0x80000000,
-0xd0400040,
-0x7c40c000,
-0xcc4d0000,
-0xdc3a0000,
-0x9780fdbc,
-0x04cc0001,
-0x80000243,
-0xcc4d0000,
-0x7c40c000,
-0x7c410000,
-0x29240018,
-0x32640001,
-0x9640000f,
-0xcc800040,
-0x7c414000,
-0x7c418000,
-0x7c41c000,
-0xccc00043,
-0xcd000043,
-0x31dc7fff,
-0xcdc00043,
-0xccc00040,
-0xcd000040,
-0xcd400040,
-0xcd800040,
-0x80000000,
-0xcdc00040,
-0xccc00040,
-0xcd000040,
-0x80000000,
-0xd0400040,
-0x80000000,
-0xd040007f,
-0xcc00007f,
-0x80000000,
-0xcc00007f,
-0xcc00007f,
-0x88000000,
-0xcc00007f,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00030223,
-0x0004022b,
-0x000500a0,
-0x00020003,
-0x0006003c,
-0x00070027,
-0x00080192,
-0x00090044,
-0x000a002d,
-0x0010025f,
-0x001700f1,
-0x002201d8,
-0x002301e9,
-0x0026004c,
-0x0027005f,
-0x0020011b,
-0x00280093,
-0x0029004f,
-0x002a0084,
-0x002b0065,
-0x002f008e,
-0x003200d9,
-0x00340233,
-0x00360075,
-0x0039010b,
-0x003c01fd,
-0x003f00a0,
-0x00410248,
-0x00440195,
-0x0048019e,
-0x004901c6,
-0x004a01d0,
-0x00550226,
-0x0056022e,
-0x0060000a,
-0x0061002a,
-0x00620030,
-0x00630030,
-0x00640030,
-0x00650030,
-0x00660030,
-0x00670030,
-0x00680037,
-0x0069003f,
-0x006a0047,
-0x006b0047,
-0x006c0047,
-0x006d0047,
-0x006e0047,
-0x006f0047,
-0x00700047,
-0x0073025f,
-0x007b0241,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-};
-
-static const u32 RV730_pfp_microcode[] = {
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0x80000000,
-0xdc030000,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xc818000e,
-0x31980001,
-0x7c424000,
-0x9580023a,
-0x7c428000,
-0xc81c001c,
-0xc037c000,
-0x7c40c000,
-0x7c410000,
-0x7cb4800b,
-0xc0360003,
-0x99c00000,
-0xc81c001c,
-0x7cb4800c,
-0x24d40002,
-0x7d654000,
-0xcd400043,
-0xce800043,
-0xcd000043,
-0xcc800040,
-0xce400040,
-0xce800040,
-0xccc00040,
-0xdc3a0000,
-0x9780ffde,
-0xcd000040,
-0x7c40c000,
-0x80000018,
-0x7c410000,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xc818000e,
-0x8000000c,
-0x31980002,
-0xd40003c0,
-0xd4000fc0,
-0xd4000fa2,
-0xc818000e,
-0x288c0008,
-0x30cc000f,
-0x34100001,
-0x7d0d0008,
-0x8000000c,
-0x7d91800b,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xd40003c0,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xcc4003f9,
-0x80000249,
-0xcc4003f8,
-0xc037ffff,
-0x7c414000,
-0xcf41a29e,
-0xc82003f8,
-0xc81c03f9,
-0x66200020,
-0xc81803fb,
-0x7de1c02c,
-0x7d58c008,
-0x7cdcc020,
-0x69100020,
-0xc0360003,
-0xcc000054,
-0x7cb4800c,
-0x80000069,
-0xcc800040,
-0x7c418000,
-0xcd81a29e,
-0xcc800040,
-0x80000067,
-0xcd800040,
-0xc019ffff,
-0xcc800040,
-0xcd81a29e,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0xccc1a1fa,
-0xcd01a1f9,
-0xcd41a29d,
-0xccc00040,
-0xcd000040,
-0xcd400040,
-0xcc400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xcc000054,
-0xcc800040,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0xccc1a1fa,
-0xcd01a1f9,
-0xcd41a29d,
-0xccc00040,
-0xcd000040,
-0xcd400040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0x7c40c000,
-0x30d00001,
-0xccc1a29f,
-0x95000003,
-0x04140001,
-0x04140002,
-0xcd4003fb,
-0xcc800040,
-0x80000000,
-0xccc00040,
-0x7c40c000,
-0xcc800040,
-0xccc1a2a2,
-0x80000000,
-0xccc00040,
-0x7c40c000,
-0x28d4001f,
-0xcc800040,
-0x95400003,
-0x7c410000,
-0xccc00057,
-0x2918001f,
-0xccc00040,
-0x95800003,
-0xcd000040,
-0xcd000058,
-0x80000249,
-0xcc00007f,
-0xc8200017,
-0xc8300022,
-0x9a000006,
-0x0e280001,
-0xc824001e,
-0x0a640001,
-0xd4001240,
-0xce400040,
-0xc036c000,
-0x96800007,
-0x37747900,
-0x041c0001,
-0xcf400040,
-0xcdc00040,
-0xcf0003fa,
-0x7c030000,
-0xca0c0010,
-0x7c410000,
-0x94c00004,
-0x7c414000,
-0xd42002c4,
-0xcde00044,
-0x9b00000b,
-0x7c418000,
-0xcc00004b,
-0xcda00049,
-0xcd200041,
-0xcd600041,
-0xcda00041,
-0x06200001,
-0xce000056,
-0x80000249,
-0xcc00007f,
-0xc8280020,
-0xc82c0021,
-0xcc000063,
-0x7eea4001,
-0x65740020,
-0x7f53402c,
-0x269c0002,
-0x7df5c020,
-0x69f80020,
-0xce80004b,
-0xce600049,
-0xcde00041,
-0xcfa00041,
-0xce600041,
-0x271c0002,
-0x7df5c020,
-0x69f80020,
-0x7db24001,
-0xcf00004b,
-0xce600049,
-0xcde00041,
-0xcfa00041,
-0x800000bc,
-0xce600041,
-0xc8200017,
-0xc8300022,
-0x9a000006,
-0x0e280001,
-0xc824001e,
-0x0a640001,
-0xd4001240,
-0xce400040,
-0xca0c0010,
-0x7c410000,
-0x94c0000b,
-0xc036c000,
-0x96800007,
-0x37747900,
-0x041c0001,
-0xcf400040,
-0xcdc00040,
-0xcf0003fa,
-0x7c030000,
-0x800000b5,
-0x7c414000,
-0xcc000048,
-0x800000ee,
-0x00000000,
-0xc8200017,
-0xc81c0023,
-0x0e240002,
-0x99c00015,
-0x7c418000,
-0x0a200001,
-0xce000056,
-0xd4000440,
-0xcc000040,
-0xc036c000,
-0xca140013,
-0x96400007,
-0x37747900,
-0xcf400040,
-0xcc000040,
-0xc83003fa,
-0x80000103,
-0xcf000022,
-0xcc000022,
-0x95400146,
-0xcc00007f,
-0xcca00046,
-0x80000000,
-0xcc200046,
-0x80000249,
-0xcc000064,
-0xc8200017,
-0xc810001f,
-0x96000005,
-0x09100001,
-0xd4000440,
-0xcd000040,
-0xcd000022,
-0xcc800040,
-0xd0400040,
-0xc80c0025,
-0x94c0feec,
-0xc8100008,
-0xcd000040,
-0xd4000fc0,
-0x80000000,
-0xd4000fa2,
-0x7c40c000,
-0x7c410000,
-0xccc003fd,
-0xcd0003fc,
-0xccc00042,
-0xcd000042,
-0x2914001f,
-0x29180010,
-0x31980007,
-0x3b5c0001,
-0x7d76000b,
-0x99800005,
-0x7d5e400b,
-0xcc000042,
-0x80000249,
-0xcc00004d,
-0x29980001,
-0x292c0008,
-0x9980003d,
-0x32ec0001,
-0x96000004,
-0x2930000c,
-0x80000249,
-0xcc000042,
-0x04140010,
-0xcd400042,
-0x33300001,
-0x34280001,
-0x8400015d,
-0xc8140003,
-0x9b40001b,
-0x0438000c,
-0x8400015d,
-0xc8140003,
-0x9b400017,
-0x04380008,
-0x8400015d,
-0xc8140003,
-0x9b400013,
-0x04380004,
-0x8400015d,
-0xc8140003,
-0x9b400015,
-0xc80c03fd,
-0x9a800009,
-0xc81003fc,
-0x9b000101,
-0xcc00004d,
-0x04140010,
-0xccc00042,
-0xcd000042,
-0x80000135,
-0xcd400042,
-0x96c000fa,
-0xcc00004d,
-0x80000249,
-0xcc00004e,
-0x9ac00003,
-0xcc00004d,
-0xcc00004e,
-0xdf830000,
-0x80000000,
-0xd80301ff,
-0x9ac000f0,
-0xcc00004d,
-0x80000249,
-0xcc00004e,
-0xc8180003,
-0xc81c0003,
-0xc8200003,
-0x7d5d4003,
-0x7da1c003,
-0x7d5d400c,
-0x2a10001f,
-0x299c001f,
-0x7d1d000b,
-0x7d17400b,
-0x88000000,
-0x7e92800b,
-0x96400004,
-0xcc00004e,
-0x80000249,
-0xcc000042,
-0x04380008,
-0xcf800042,
-0xc8080003,
-0xc80c0003,
-0xc8100003,
-0xc8140003,
-0xc8180003,
-0xc81c0003,
-0xc8240003,
-0xc8280003,
-0x29fc001f,
-0x2ab0001f,
-0x7ff3c00b,
-0x28f0001f,
-0x7ff3c00b,
-0x2970001f,
-0x7ff3c00b,
-0x7d888001,
-0x7dccc001,
-0x7e510001,
-0x7e954001,
-0x7c908002,
-0x7cd4c002,
-0x7cbc800b,
-0x9ac00003,
-0x7c8f400b,
-0x38b40001,
-0x9b4000c1,
-0xcc00004d,
-0x9bc000bf,
-0xcc00004e,
-0xc80c03fd,
-0xc81003fc,
-0xccc00042,
-0x8000016e,
-0xcd000042,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xcc400040,
-0xcc400040,
-0xcc400040,
-0x7c40c000,
-0xccc00040,
-0xccc0000d,
-0x80000000,
-0xd0400040,
-0x7c40c000,
-0x7c410000,
-0x65140020,
-0x7d4d402c,
-0x24580002,
-0x7d598020,
-0x7c41c000,
-0xcd800042,
-0x69980020,
-0xcd800042,
-0xcdc00042,
-0xc023c000,
-0x05e40002,
-0x7ca0800b,
-0x26640010,
-0x7ca4800c,
-0xcc800040,
-0xcdc00040,
-0xccc00040,
-0x95c0000e,
-0xcd000040,
-0x09dc0001,
-0xc8280003,
-0x96800008,
-0xce800040,
-0xc834001d,
-0x97400000,
-0xc834001d,
-0x26a80008,
-0x8400024c,
-0xcc2b0000,
-0x99c0fff7,
-0x09dc0001,
-0xdc3a0000,
-0x97800004,
-0x7c418000,
-0x800001a2,
-0x25980002,
-0xa0000000,
-0x7d808000,
-0xc818001d,
-0x7c40c000,
-0x64d00008,
-0x95800000,
-0xc818001d,
-0xcc130000,
-0xcc800040,
-0xccc00040,
-0x80000000,
-0xcc400040,
-0xc810001f,
-0x7c40c000,
-0xcc800040,
-0x7cd1400c,
-0xcd400040,
-0x05180001,
-0x80000000,
-0xcd800022,
-0x7c40c000,
-0x64500020,
-0x8400024c,
-0xcc000061,
-0x7cd0c02c,
-0xc8200017,
-0xc8d60000,
-0x99400008,
-0x7c438000,
-0xdf830000,
-0xcfa0004f,
-0x8400024c,
-0xcc000062,
-0x80000000,
-0xd040007f,
-0x80000249,
-0xcc000062,
-0x8400024c,
-0xcc000061,
-0xc8200017,
-0x7c40c000,
-0xc036ff00,
-0xc810000d,
-0xc0303fff,
-0x7cf5400b,
-0x7d51800b,
-0x7d81800f,
-0x99800008,
-0x7cf3800b,
-0xdf830000,
-0xcfa0004f,
-0x8400024c,
-0xcc000062,
-0x80000000,
-0xd040007f,
-0x80000249,
-0xcc000062,
-0x8400024c,
-0x7c40c000,
-0x28dc0008,
-0x95c00019,
-0x30dc0010,
-0x7c410000,
-0x99c00004,
-0x64540020,
-0x80000208,
-0xc91d0000,
-0x7d15002c,
-0xc91e0000,
-0x7c420000,
-0x7c424000,
-0x7c418000,
-0x7de5c00b,
-0x7de28007,
-0x9a80000e,
-0x41ac0005,
-0x9ac00000,
-0x0aec0001,
-0x30dc0010,
-0x99c00004,
-0x00000000,
-0x8000020b,
-0xc91d0000,
-0x8000020b,
-0xc91e0000,
-0xcc800040,
-0xccc00040,
-0xd0400040,
-0xc80c0025,
-0x94c0fde4,
-0xc8100008,
-0xcd000040,
-0xd4000fc0,
-0x80000000,
-0xd4000fa2,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xd40003c0,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0x7c40c000,
-0x30d00006,
-0x0d100006,
-0x99000007,
-0xc8140015,
-0x99400005,
-0xcc000052,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xccc00040,
-0x80000000,
-0xd0400040,
-0x7c40c000,
-0xcc4d0000,
-0xdc3a0000,
-0x9780fdbd,
-0x04cc0001,
-0x80000242,
-0xcc4d0000,
-0x80000000,
-0xd040007f,
-0xcc00007f,
-0x80000000,
-0xcc00007f,
-0xcc00007f,
-0x88000000,
-0xcc00007f,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00030222,
-0x0004022a,
-0x0005009f,
-0x00020003,
-0x0006003c,
-0x00070027,
-0x00080191,
-0x00090044,
-0x000a002d,
-0x00100247,
-0x001700f0,
-0x002201d7,
-0x002301e8,
-0x0026004c,
-0x0027005f,
-0x0020011a,
-0x00280092,
-0x0029004f,
-0x002a0083,
-0x002b0064,
-0x002f008d,
-0x003200d8,
-0x00340232,
-0x00360074,
-0x0039010a,
-0x003c01fc,
-0x003f009f,
-0x00410005,
-0x00440194,
-0x0048019d,
-0x004901c5,
-0x004a01cf,
-0x00550225,
-0x0056022d,
-0x0060000a,
-0x0061002a,
-0x00620030,
-0x00630030,
-0x00640030,
-0x00650030,
-0x00660030,
-0x00670030,
-0x00680037,
-0x0069003f,
-0x006a0047,
-0x006b0047,
-0x006c0047,
-0x006d0047,
-0x006e0047,
-0x006f0047,
-0x00700047,
-0x00730247,
-0x007b0240,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-};
-
-static const u32 RV730_cp_microcode[] = {
-0xcc0003ea,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x80000001,
-0xd040007f,
-0x80000001,
-0xcc400041,
-0x7c40c000,
-0xc0160004,
-0x30d03fff,
-0x7d15000c,
-0xcc110000,
-0x28d8001e,
-0x31980001,
-0x28dc001f,
-0xc8200004,
-0x95c00006,
-0x7c424000,
-0xcc000062,
-0x7e56800c,
-0xcc290000,
-0xc8240004,
-0x7e26000b,
-0x95800006,
-0x7c42c000,
-0xcc000062,
-0x7ed7000c,
-0xcc310000,
-0xc82c0004,
-0x7e2e000c,
-0xcc000062,
-0x31103fff,
-0x80000001,
-0xce110000,
-0x7c40c000,
-0x80000001,
-0xcc400040,
-0x80000001,
-0xcc412257,
-0x7c418000,
-0xcc400045,
-0xcc400048,
-0xcc41225c,
-0xcc41a1fc,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xcc400045,
-0xcc400048,
-0x7c40c000,
-0xcc41225c,
-0xcc41a1fc,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xcc000045,
-0xcc000048,
-0xcc41225c,
-0xcc41a1fc,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x040ca1fd,
-0xc0120001,
-0xcc000045,
-0xcc000048,
-0x7cd0c00c,
-0xcc41225c,
-0xcc41a1fc,
-0xd04d0000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x80000001,
-0xcc41225d,
-0x7c408000,
-0x7c40c000,
-0xc02a0002,
-0x7c410000,
-0x7d29000c,
-0x30940001,
-0x30980006,
-0x309c0300,
-0x29dc0008,
-0x7c420000,
-0x7c424000,
-0x9540000f,
-0xc02e0004,
-0x05f02258,
-0x7f2f000c,
-0xcc310000,
-0xc8280004,
-0xccc12169,
-0xcd01216a,
-0xce81216b,
-0x0db40002,
-0xcc01216c,
-0x9740000e,
-0x0db40000,
-0x8000007b,
-0xc834000a,
-0x0db40002,
-0x97400009,
-0x0db40000,
-0xc02e0004,
-0x05f02258,
-0x7f2f000c,
-0xcc310000,
-0xc8280004,
-0x8000007b,
-0xc834000a,
-0x97400004,
-0x7e028000,
-0x8000007b,
-0xc834000a,
-0x0db40004,
-0x9740ff8c,
-0x00000000,
-0xce01216d,
-0xce41216e,
-0xc8280003,
-0xc834000a,
-0x9b400004,
-0x043c0005,
-0x8400026b,
-0xcc000062,
-0x0df40000,
-0x9740000b,
-0xc82c03e6,
-0xce81a2b7,
-0xc0300006,
-0x7ef34028,
-0xc0300020,
-0x7f6b8020,
-0x7fb3c029,
-0xcf81a2c4,
-0x80000001,
-0xcfc1a2d1,
-0x0df40001,
-0x9740000b,
-0xc82c03e7,
-0xce81a2bb,
-0xc0300006,
-0x7ef34028,
-0xc0300020,
-0x7f6b8020,
-0x7fb3c029,
-0xcf81a2c5,
-0x80000001,
-0xcfc1a2d2,
-0x0df40002,
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-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00010331,
-0x00100004,
-0x00170006,
-0x00210008,
-0x00270028,
-0x00280023,
-0x00290029,
-0x002a0026,
-0x002b0029,
-0x002d0038,
-0x002e003f,
-0x002f004a,
-0x0034004c,
-0x00360030,
-0x003900af,
-0x003a00cf,
-0x003b00e4,
-0x003c00fc,
-0x003d016b,
-0x003f00ad,
-0x00410336,
-0x00430349,
-0x0044018e,
-0x004500fc,
-0x004601ac,
-0x004701ac,
-0x004801fe,
-0x0049020c,
-0x004a0255,
-0x004b0282,
-0x0052025f,
-0x00530271,
-0x00540287,
-0x00570299,
-0x0060029d,
-0x006102ac,
-0x006202b6,
-0x006302c0,
-0x006402ca,
-0x006502d4,
-0x006602de,
-0x006702e8,
-0x006802f2,
-0x006902f6,
-0x006a02fa,
-0x006b02fe,
-0x006c0302,
-0x006d0306,
-0x006e030a,
-0x006f030e,
-0x00700312,
-0x00720363,
-0x00740369,
-0x00790367,
-0x007c031c,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-0x000f0378,
-};
-
-static const u32 RV710_pfp_microcode[] = {
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0x80000000,
-0xdc030000,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xc818000e,
-0x31980001,
-0x7c424000,
-0x9580023a,
-0x7c428000,
-0xc81c001c,
-0xc037c000,
-0x7c40c000,
-0x7c410000,
-0x7cb4800b,
-0xc0360003,
-0x99c00000,
-0xc81c001c,
-0x7cb4800c,
-0x24d40002,
-0x7d654000,
-0xcd400043,
-0xce800043,
-0xcd000043,
-0xcc800040,
-0xce400040,
-0xce800040,
-0xccc00040,
-0xdc3a0000,
-0x9780ffde,
-0xcd000040,
-0x7c40c000,
-0x80000018,
-0x7c410000,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xc818000e,
-0x8000000c,
-0x31980002,
-0xd40003c0,
-0xd4000fc0,
-0xd4000fa2,
-0xc818000e,
-0x288c0008,
-0x30cc000f,
-0x34100001,
-0x7d0d0008,
-0x8000000c,
-0x7d91800b,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xd40003c0,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xcc4003f9,
-0x80000249,
-0xcc4003f8,
-0xc037ffff,
-0x7c414000,
-0xcf41a29e,
-0xc82003f8,
-0xc81c03f9,
-0x66200020,
-0xc81803fb,
-0x7de1c02c,
-0x7d58c008,
-0x7cdcc020,
-0x69100020,
-0xc0360003,
-0xcc000054,
-0x7cb4800c,
-0x80000069,
-0xcc800040,
-0x7c418000,
-0xcd81a29e,
-0xcc800040,
-0x80000067,
-0xcd800040,
-0xc019ffff,
-0xcc800040,
-0xcd81a29e,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0xccc1a1fa,
-0xcd01a1f9,
-0xcd41a29d,
-0xccc00040,
-0xcd000040,
-0xcd400040,
-0xcc400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xcc000054,
-0xcc800040,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0xccc1a1fa,
-0xcd01a1f9,
-0xcd41a29d,
-0xccc00040,
-0xcd000040,
-0xcd400040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0x7c40c000,
-0x30d00001,
-0xccc1a29f,
-0x95000003,
-0x04140001,
-0x04140002,
-0xcd4003fb,
-0xcc800040,
-0x80000000,
-0xccc00040,
-0x7c40c000,
-0xcc800040,
-0xccc1a2a2,
-0x80000000,
-0xccc00040,
-0x7c40c000,
-0x28d4001f,
-0xcc800040,
-0x95400003,
-0x7c410000,
-0xccc00057,
-0x2918001f,
-0xccc00040,
-0x95800003,
-0xcd000040,
-0xcd000058,
-0x80000249,
-0xcc00007f,
-0xc8200017,
-0xc8300022,
-0x9a000006,
-0x0e280001,
-0xc824001e,
-0x0a640001,
-0xd4001240,
-0xce400040,
-0xc036c000,
-0x96800007,
-0x37747900,
-0x041c0001,
-0xcf400040,
-0xcdc00040,
-0xcf0003fa,
-0x7c030000,
-0xca0c0010,
-0x7c410000,
-0x94c00004,
-0x7c414000,
-0xd42002c4,
-0xcde00044,
-0x9b00000b,
-0x7c418000,
-0xcc00004b,
-0xcda00049,
-0xcd200041,
-0xcd600041,
-0xcda00041,
-0x06200001,
-0xce000056,
-0x80000249,
-0xcc00007f,
-0xc8280020,
-0xc82c0021,
-0xcc000063,
-0x7eea4001,
-0x65740020,
-0x7f53402c,
-0x269c0002,
-0x7df5c020,
-0x69f80020,
-0xce80004b,
-0xce600049,
-0xcde00041,
-0xcfa00041,
-0xce600041,
-0x271c0002,
-0x7df5c020,
-0x69f80020,
-0x7db24001,
-0xcf00004b,
-0xce600049,
-0xcde00041,
-0xcfa00041,
-0x800000bc,
-0xce600041,
-0xc8200017,
-0xc8300022,
-0x9a000006,
-0x0e280001,
-0xc824001e,
-0x0a640001,
-0xd4001240,
-0xce400040,
-0xca0c0010,
-0x7c410000,
-0x94c0000b,
-0xc036c000,
-0x96800007,
-0x37747900,
-0x041c0001,
-0xcf400040,
-0xcdc00040,
-0xcf0003fa,
-0x7c030000,
-0x800000b5,
-0x7c414000,
-0xcc000048,
-0x800000ee,
-0x00000000,
-0xc8200017,
-0xc81c0023,
-0x0e240002,
-0x99c00015,
-0x7c418000,
-0x0a200001,
-0xce000056,
-0xd4000440,
-0xcc000040,
-0xc036c000,
-0xca140013,
-0x96400007,
-0x37747900,
-0xcf400040,
-0xcc000040,
-0xc83003fa,
-0x80000103,
-0xcf000022,
-0xcc000022,
-0x95400146,
-0xcc00007f,
-0xcca00046,
-0x80000000,
-0xcc200046,
-0x80000249,
-0xcc000064,
-0xc8200017,
-0xc810001f,
-0x96000005,
-0x09100001,
-0xd4000440,
-0xcd000040,
-0xcd000022,
-0xcc800040,
-0xd0400040,
-0xc80c0025,
-0x94c0feec,
-0xc8100008,
-0xcd000040,
-0xd4000fc0,
-0x80000000,
-0xd4000fa2,
-0x7c40c000,
-0x7c410000,
-0xccc003fd,
-0xcd0003fc,
-0xccc00042,
-0xcd000042,
-0x2914001f,
-0x29180010,
-0x31980007,
-0x3b5c0001,
-0x7d76000b,
-0x99800005,
-0x7d5e400b,
-0xcc000042,
-0x80000249,
-0xcc00004d,
-0x29980001,
-0x292c0008,
-0x9980003d,
-0x32ec0001,
-0x96000004,
-0x2930000c,
-0x80000249,
-0xcc000042,
-0x04140010,
-0xcd400042,
-0x33300001,
-0x34280001,
-0x8400015d,
-0xc8140003,
-0x9b40001b,
-0x0438000c,
-0x8400015d,
-0xc8140003,
-0x9b400017,
-0x04380008,
-0x8400015d,
-0xc8140003,
-0x9b400013,
-0x04380004,
-0x8400015d,
-0xc8140003,
-0x9b400015,
-0xc80c03fd,
-0x9a800009,
-0xc81003fc,
-0x9b000101,
-0xcc00004d,
-0x04140010,
-0xccc00042,
-0xcd000042,
-0x80000135,
-0xcd400042,
-0x96c000fa,
-0xcc00004d,
-0x80000249,
-0xcc00004e,
-0x9ac00003,
-0xcc00004d,
-0xcc00004e,
-0xdf830000,
-0x80000000,
-0xd80301ff,
-0x9ac000f0,
-0xcc00004d,
-0x80000249,
-0xcc00004e,
-0xc8180003,
-0xc81c0003,
-0xc8200003,
-0x7d5d4003,
-0x7da1c003,
-0x7d5d400c,
-0x2a10001f,
-0x299c001f,
-0x7d1d000b,
-0x7d17400b,
-0x88000000,
-0x7e92800b,
-0x96400004,
-0xcc00004e,
-0x80000249,
-0xcc000042,
-0x04380008,
-0xcf800042,
-0xc8080003,
-0xc80c0003,
-0xc8100003,
-0xc8140003,
-0xc8180003,
-0xc81c0003,
-0xc8240003,
-0xc8280003,
-0x29fc001f,
-0x2ab0001f,
-0x7ff3c00b,
-0x28f0001f,
-0x7ff3c00b,
-0x2970001f,
-0x7ff3c00b,
-0x7d888001,
-0x7dccc001,
-0x7e510001,
-0x7e954001,
-0x7c908002,
-0x7cd4c002,
-0x7cbc800b,
-0x9ac00003,
-0x7c8f400b,
-0x38b40001,
-0x9b4000c1,
-0xcc00004d,
-0x9bc000bf,
-0xcc00004e,
-0xc80c03fd,
-0xc81003fc,
-0xccc00042,
-0x8000016e,
-0xcd000042,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xcc400040,
-0xcc400040,
-0xcc400040,
-0x7c40c000,
-0xccc00040,
-0xccc0000d,
-0x80000000,
-0xd0400040,
-0x7c40c000,
-0x7c410000,
-0x65140020,
-0x7d4d402c,
-0x24580002,
-0x7d598020,
-0x7c41c000,
-0xcd800042,
-0x69980020,
-0xcd800042,
-0xcdc00042,
-0xc023c000,
-0x05e40002,
-0x7ca0800b,
-0x26640010,
-0x7ca4800c,
-0xcc800040,
-0xcdc00040,
-0xccc00040,
-0x95c0000e,
-0xcd000040,
-0x09dc0001,
-0xc8280003,
-0x96800008,
-0xce800040,
-0xc834001d,
-0x97400000,
-0xc834001d,
-0x26a80008,
-0x8400024c,
-0xcc2b0000,
-0x99c0fff7,
-0x09dc0001,
-0xdc3a0000,
-0x97800004,
-0x7c418000,
-0x800001a2,
-0x25980002,
-0xa0000000,
-0x7d808000,
-0xc818001d,
-0x7c40c000,
-0x64d00008,
-0x95800000,
-0xc818001d,
-0xcc130000,
-0xcc800040,
-0xccc00040,
-0x80000000,
-0xcc400040,
-0xc810001f,
-0x7c40c000,
-0xcc800040,
-0x7cd1400c,
-0xcd400040,
-0x05180001,
-0x80000000,
-0xcd800022,
-0x7c40c000,
-0x64500020,
-0x8400024c,
-0xcc000061,
-0x7cd0c02c,
-0xc8200017,
-0xc8d60000,
-0x99400008,
-0x7c438000,
-0xdf830000,
-0xcfa0004f,
-0x8400024c,
-0xcc000062,
-0x80000000,
-0xd040007f,
-0x80000249,
-0xcc000062,
-0x8400024c,
-0xcc000061,
-0xc8200017,
-0x7c40c000,
-0xc036ff00,
-0xc810000d,
-0xc0303fff,
-0x7cf5400b,
-0x7d51800b,
-0x7d81800f,
-0x99800008,
-0x7cf3800b,
-0xdf830000,
-0xcfa0004f,
-0x8400024c,
-0xcc000062,
-0x80000000,
-0xd040007f,
-0x80000249,
-0xcc000062,
-0x8400024c,
-0x7c40c000,
-0x28dc0008,
-0x95c00019,
-0x30dc0010,
-0x7c410000,
-0x99c00004,
-0x64540020,
-0x80000208,
-0xc91d0000,
-0x7d15002c,
-0xc91e0000,
-0x7c420000,
-0x7c424000,
-0x7c418000,
-0x7de5c00b,
-0x7de28007,
-0x9a80000e,
-0x41ac0005,
-0x9ac00000,
-0x0aec0001,
-0x30dc0010,
-0x99c00004,
-0x00000000,
-0x8000020b,
-0xc91d0000,
-0x8000020b,
-0xc91e0000,
-0xcc800040,
-0xccc00040,
-0xd0400040,
-0xc80c0025,
-0x94c0fde4,
-0xc8100008,
-0xcd000040,
-0xd4000fc0,
-0x80000000,
-0xd4000fa2,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0xd40003c0,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xd0400040,
-0x7c408000,
-0xa0000000,
-0x7e82800b,
-0x7c40c000,
-0x30d00006,
-0x0d100006,
-0x99000007,
-0xc8140015,
-0x99400005,
-0xcc000052,
-0xd4000340,
-0xd4000fc0,
-0xd4000fa2,
-0xcc800040,
-0xccc00040,
-0x80000000,
-0xd0400040,
-0x7c40c000,
-0xcc4d0000,
-0xdc3a0000,
-0x9780fdbd,
-0x04cc0001,
-0x80000242,
-0xcc4d0000,
-0x80000000,
-0xd040007f,
-0xcc00007f,
-0x80000000,
-0xcc00007f,
-0xcc00007f,
-0x88000000,
-0xcc00007f,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00030222,
-0x0004022a,
-0x0005009f,
-0x00020003,
-0x0006003c,
-0x00070027,
-0x00080191,
-0x00090044,
-0x000a002d,
-0x00100247,
-0x001700f0,
-0x002201d7,
-0x002301e8,
-0x0026004c,
-0x0027005f,
-0x0020011a,
-0x00280092,
-0x0029004f,
-0x002a0083,
-0x002b0064,
-0x002f008d,
-0x003200d8,
-0x00340232,
-0x00360074,
-0x0039010a,
-0x003c01fc,
-0x003f009f,
-0x00410005,
-0x00440194,
-0x0048019d,
-0x004901c5,
-0x004a01cf,
-0x00550225,
-0x0056022d,
-0x0060000a,
-0x0061002a,
-0x00620030,
-0x00630030,
-0x00640030,
-0x00650030,
-0x00660030,
-0x00670030,
-0x00680037,
-0x0069003f,
-0x006a0047,
-0x006b0047,
-0x006c0047,
-0x006d0047,
-0x006e0047,
-0x006f0047,
-0x00700047,
-0x00730247,
-0x007b0240,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-0x00000005,
-};
-
-static const u32 RV710_cp_microcode[] = {
-0xcc0003ea,
-0x04080003,
-0xcc800043,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x80000003,
-0xd040007f,
-0x80000003,
-0xcc400041,
-0x7c40c000,
-0xc0160004,
-0x30d03fff,
-0x7d15000c,
-0xcc110000,
-0x28d8001e,
-0x31980001,
-0x28dc001f,
-0xc8200004,
-0x95c00006,
-0x7c424000,
-0xcc000062,
-0x7e56800c,
-0xcc290000,
-0xc8240004,
-0x7e26000b,
-0x95800006,
-0x7c42c000,
-0xcc000062,
-0x7ed7000c,
-0xcc310000,
-0xc82c0004,
-0x7e2e000c,
-0xcc000062,
-0x31103fff,
-0x80000003,
-0xce110000,
-0x7c40c000,
-0x80000003,
-0xcc400040,
-0x80000003,
-0xcc412257,
-0x7c418000,
-0xcc400045,
-0xcc400048,
-0xcc41225c,
-0xcc41a1fc,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xcc400045,
-0xcc400048,
-0x7c40c000,
-0xcc41225c,
-0xcc41a1fc,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xcc000045,
-0xcc000048,
-0xcc41225c,
-0xcc41a1fc,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x040ca1fd,
-0xc0120001,
-0xcc000045,
-0xcc000048,
-0x7cd0c00c,
-0xcc41225c,
-0xcc41a1fc,
-0xd04d0000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x80000003,
-0xcc41225d,
-0x7c408000,
-0x7c40c000,
-0xc02a0002,
-0x7c410000,
-0x7d29000c,
-0x30940001,
-0x30980006,
-0x309c0300,
-0x29dc0008,
-0x7c420000,
-0x7c424000,
-0x9540000f,
-0xc02e0004,
-0x05f02258,
-0x7f2f000c,
-0xcc310000,
-0xc8280004,
-0xccc12169,
-0xcd01216a,
-0xce81216b,
-0x0db40002,
-0xcc01216c,
-0x9740000e,
-0x0db40000,
-0x8000007d,
-0xc834000a,
-0x0db40002,
-0x97400009,
-0x0db40000,
-0xc02e0004,
-0x05f02258,
-0x7f2f000c,
-0xcc310000,
-0xc8280004,
-0x8000007d,
-0xc834000a,
-0x97400004,
-0x7e028000,
-0x8000007d,
-0xc834000a,
-0x0db40004,
-0x9740ff8c,
-0x00000000,
-0xce01216d,
-0xce41216e,
-0xc8280003,
-0xc834000a,
-0x9b400004,
-0x043c0005,
-0x8400026d,
-0xcc000062,
-0x0df40000,
-0x9740000b,
-0xc82c03e6,
-0xce81a2b7,
-0xc0300006,
-0x7ef34028,
-0xc0300020,
-0x7f6b8020,
-0x7fb3c029,
-0xcf81a2c4,
-0x80000003,
-0xcfc1a2d1,
-0x0df40001,
-0x9740000b,
-0xc82c03e7,
-0xce81a2bb,
-0xc0300006,
-0x7ef34028,
-0xc0300020,
-0x7f6b8020,
-0x7fb3c029,
-0xcf81a2c5,
-0x80000003,
-0xcfc1a2d2,
-0x0df40002,
-0x9740000b,
-0xc82c03e8,
-0xce81a2bf,
-0xc0300006,
-0x7ef34028,
-0xc0300020,
-0x7f6b8020,
-0x7fb3c029,
-0xcf81a2c6,
-0x80000003,
-0xcfc1a2d3,
-0xc82c03e9,
-0xce81a2c3,
-0xc0300006,
-0x7ef34028,
-0xc0300020,
-0x7f6b8020,
-0x7fb3c029,
-0xcf81a2c7,
-0x80000003,
-0xcfc1a2d4,
-0x80000003,
-0xcc400042,
-0x7c40c000,
-0x7c410000,
-0x2914001d,
-0x31540001,
-0x9940000c,
-0x31181000,
-0xc81c0011,
-0x95c00000,
-0xc81c0011,
-0xccc12100,
-0xcd012101,
-0xccc12102,
-0xcd012103,
-0x04180004,
-0x8000037e,
-0xcd81a2a4,
-0xc02a0004,
-0x95800008,
-0x36a821a3,
-0xcc290000,
-0xc8280004,
-0xc81c0011,
-0x0de40040,
-0x9640ffff,
-0xc81c0011,
-0xccc12170,
-0xcd012171,
-0xc8200012,
-0x96000000,
-0xc8200012,
-0x8000037e,
-0xcc000064,
-0x7c40c000,
-0x7c410000,
-0xcc000045,
-0xcc000048,
-0x40d40003,
-0xcd41225c,
-0xcd01a1fc,
-0xc01a0001,
-0x041ca1fd,
-0x7dd9c00c,
-0x7c420000,
-0x08cc0001,
-0x06240001,
-0x06280002,
-0xce1d0000,
-0xce5d0000,
-0x98c0fffa,
-0xce9d0000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x7c40c000,
-0x30d00001,
-0x28cc0001,
-0x7c414000,
-0x95000006,
-0x7c418000,
-0xcd41216d,
-0xcd81216e,
-0x800000f4,
-0xc81c0003,
-0xc0220004,
-0x7e16000c,
-0xcc210000,
-0xc81c0004,
-0x7c424000,
-0x98c00004,
-0x7c428000,
-0x80000003,
-0xcde50000,
-0xce412169,
-0xce81216a,
-0xcdc1216b,
-0x80000003,
-0xcc01216c,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0x7c41c000,
-0x28a40008,
-0x326400ff,
-0x0e68003c,
-0x9680000a,
-0x7c020000,
-0x7c420000,
-0x1e300003,
-0xcc00006a,
-0x9b000003,
-0x42200005,
-0x04200040,
-0x80000111,
-0x7c024000,
-0x7e024000,
-0x9a400000,
-0x0a640001,
-0x30ec0010,
-0x9ac0000a,
-0xcc000062,
-0xc02a0004,
-0xc82c0021,
-0x7e92800c,
-0xcc000041,
-0xcc290000,
-0xcec00021,
-0x80000121,
-0xc8300004,
-0xcd01216d,
-0xcd41216e,
-0xc8300003,
-0x7f1f000b,
-0x30f40007,
-0x27780001,
-0x9740002a,
-0x07b80126,
-0x9f800000,
-0x00000000,
-0x80000136,
-0x7f1b8004,
-0x8000013a,
-0x7f1b8005,
-0x8000013e,
-0x7f1b8002,
-0x80000142,
-0x7f1b8003,
-0x80000146,
-0x7f1b8007,
-0x8000014a,
-0x7f1b8006,
-0x8000014f,
-0x28a40008,
-0x9b800019,
-0x28a40008,
-0x8000015f,
-0x326400ff,
-0x9b800015,
-0x28a40008,
-0x8000015f,
-0x326400ff,
-0x9b800011,
-0x28a40008,
-0x8000015f,
-0x326400ff,
-0x9b80000d,
-0x28a40008,
-0x8000015f,
-0x326400ff,
-0x9b800009,
-0x28a40008,
-0x8000015f,
-0x326400ff,
-0x9b800005,
-0x28a40008,
-0x8000015f,
-0x326400ff,
-0x28a40008,
-0x326400ff,
-0x0e68003c,
-0x9a80feb2,
-0x28ec0008,
-0x7c434000,
-0x7c438000,
-0x7c43c000,
-0x96c00007,
-0xcc000062,
-0xcf412169,
-0xcf81216a,
-0xcfc1216b,
-0x80000003,
-0xcc01216c,
-0x80000003,
-0xcff50000,
-0xcc00006b,
-0x84000381,
-0x0e68003c,
-0x9a800004,
-0xc8280015,
-0x80000003,
-0xd040007f,
-0x9680ffab,
-0x7e024000,
-0x8400023b,
-0xc00e0002,
-0xcc000041,
-0x80000239,
-0xccc1304a,
-0x7c40c000,
-0x7c410000,
-0xc01e0001,
-0x29240012,
-0xc0220002,
-0x96400005,
-0xc0260004,
-0xc027fffb,
-0x7d25000b,
-0xc0260000,
-0x7dd2800b,
-0x7e12c00b,
-0x7d25000c,
-0x7c414000,
-0x7c418000,
-0xccc12169,
-0x9a80000a,
-0xcd01216a,
-0xcd41216b,
-0x96c0fe83,
-0xcd81216c,
-0xc8300018,
-0x97000000,
-0xc8300018,
-0x80000003,
-0xcc000018,
-0x84000381,
-0xcc00007f,
-0xc8140013,
-0xc8180014,
-0xcd41216b,
-0x96c0fe77,
-0xcd81216c,
-0x80000183,
-0xc8300018,
-0xc80c0008,
-0x98c00000,
-0xc80c0008,
-0x7c410000,
-0x95000002,
-0x00000000,
-0x7c414000,
-0xc8200009,
-0xcc400043,
-0xce01a1f4,
-0xcc400044,
-0xc00e8000,
-0x7c424000,
-0x7c428000,
-0x2aac001f,
-0x96c0fe64,
-0xc035f000,
-0xce4003e2,
-0x32780003,
-0x267c0008,
-0x7ff7c00b,
-0x7ffbc00c,
-0x2a780018,
-0xcfc003e3,
-0xcf8003e4,
-0x26b00002,
-0x7f3f0000,
-0xcf0003e5,
-0x8000031f,
-0x7c80c000,
-0x7c40c000,
-0x28d00008,
-0x3110000f,
-0x9500000f,
-0x25280001,
-0x06a801b4,
-0x9e800000,
-0x00000000,
-0x800001d5,
-0xc0120800,
-0x800001e3,
-0xc814000f,
-0x800001ea,
-0xc8140010,
-0x800001f1,
-0xccc1a2a4,
-0x800001fa,
-0xc8140011,
-0x30d0003f,
-0x0d280015,
-0x9a800012,
-0x0d28001e,
-0x9a80001e,
-0x0d280020,
-0x9a800023,
-0x0d24000f,
-0x0d280010,
-0x7e6a800c,
-0x9a800026,
-0x0d200004,
-0x0d240014,
-0x0d280028,
-0x7e62400c,
-0x7ea6800c,
-0x9a80002a,
-0xc8140011,
-0x80000003,
-0xccc1a2a4,
-0xc0120800,
-0x7c414000,
-0x7d0cc00c,
-0xc0120008,
-0x29580003,
-0x295c000c,
-0x7c420000,
-0x7dd1c00b,
-0x26200014,
-0x7e1e400c,
-0x7e4e800c,
-0xce81a2a4,
-0x80000003,
-0xcd81a1fe,
-0xc814000f,
-0x0410210e,
-0x95400000,
-0xc814000f,
-0xd0510000,
-0x80000003,
-0xccc1a2a4,
-0xc8140010,
-0x04102108,
-0x95400000,
-0xc8140010,
-0xd0510000,
-0x80000003,
-0xccc1a2a4,
-0xccc1a2a4,
-0x04100001,
-0xcd000019,
-0x84000381,
-0xcc00007f,
-0xc8100019,
-0x99000000,
-0xc8100019,
-0x80000004,
-0x7c408000,
-0x04102100,
-0x95400000,
-0xc8140011,
-0xd0510000,
-0x8000037e,
-0xccc1a2a4,
-0x7c40c000,
-0xcc40000d,
-0x94c0fe01,
-0xcc40000e,
-0x7c410000,
-0x95000005,
-0x08cc0001,
-0xc8140005,
-0x99400014,
-0x00000000,
-0x98c0fffb,
-0x7c410000,
-0x80000004,
-0x7d008000,
-0xc8140005,
-0x7c40c000,
-0x9940000c,
-0xc818000c,
-0x7c410000,
-0x9580fdf0,
-0xc820000e,
-0xc81c000d,
-0x66200020,
-0x7e1e002c,
-0x25240002,
-0x7e624020,
-0x80000003,
-0xcce60000,
-0x7c410000,
-0xcc00006c,
-0xcc00006d,
-0xc818001f,
-0xc81c001e,
-0x65980020,
-0x7dd9c02c,
-0x7cd4c00c,
-0xccde0000,
-0x45dc0004,
-0xc8280017,
-0x9680000f,
-0xc00e0001,
-0x28680008,
-0x2aac0016,
-0x32a800ff,
-0x0eb00049,
-0x7f2f000b,
-0x97000006,
-0x00000000,
-0xc8140005,
-0x7c40c000,
-0x80000223,
-0x7c410000,
-0x80000226,
-0xd040007f,
-0x8400023b,
-0xcc000041,
-0xccc1304a,
-0x94000000,
-0xc83c001a,
-0x043c0005,
-0xcfc1a2a4,
-0xc0361f90,
-0xc0387fff,
-0x7c03c010,
-0x7f7b400c,
-0xcf41217c,
-0xcfc1217d,
-0xcc01217e,
-0xc03a0004,
-0x0434217f,
-0x7f7b400c,
-0xcc350000,
-0xc83c0004,
-0x2bfc001f,
-0x04380020,
-0x97c00005,
-0xcc000062,
-0x9b800000,
-0x0bb80001,
-0x80000247,
-0xcc000071,
-0xcc01a1f4,
-0x04380016,
-0xc0360002,
-0xcf81a2a4,
-0x88000000,
-0xcf412010,
-0x7c40c000,
-0x28d0001c,
-0x95000005,
-0x04d40001,
-0xcd400065,
-0x80000003,
-0xcd400068,
-0x09540002,
-0x80000003,
-0xcd400066,
-0x8400026c,
-0xc81803ea,
-0x7c40c000,
-0x9980fd9f,
-0xc8140016,
-0x08d00001,
-0x9940002b,
-0xcd000068,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x043c0005,
-0xcfc1a2a4,
-0xcc01a1f4,
-0x84000381,
-0xcc000046,
-0x88000000,
-0xcc00007f,
-0x8400027e,
-0xc81803ea,
-0x7c40c000,
-0x9980fd8d,
-0xc8140016,
-0x08d00001,
-0x99400019,
-0xcd000068,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x043c0022,
-0xcfc1a2a4,
-0x84000381,
-0xcc000047,
-0x88000000,
-0xcc00007f,
-0xc8100016,
-0x9900000d,
-0xcc400067,
-0x80000004,
-0x7c408000,
-0xc81803ea,
-0x9980fd79,
-0x7c40c000,
-0x94c00003,
-0xc8100016,
-0x99000004,
-0xccc00068,
-0x80000004,
-0x7c408000,
-0x8400023b,
-0xc0148000,
-0xcc000041,
-0xcd41304a,
-0xc0148000,
-0x99000000,
-0xc8100016,
-0x80000004,
-0x7c408000,
-0xc0120001,
-0x7c51400c,
-0x80000003,
-0xd0550000,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0x291c001f,
-0xccc0004a,
-0xcd00004b,
-0x95c00003,
-0xc01c8000,
-0xcdc12010,
-0xdd830000,
-0x055c2000,
-0xcc000062,
-0x80000003,
-0xd81f4100,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0xccc0004c,
-0xcd00004d,
-0xdd830000,
-0x055ca000,
-0x80000003,
-0xd81f4100,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0xccc0004e,
-0xcd00004f,
-0xdd830000,
-0x055cc000,
-0x80000003,
-0xd81f4100,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0xccc00050,
-0xcd000051,
-0xdd830000,
-0x055cf8e0,
-0x80000003,
-0xd81f4100,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0xccc00052,
-0xcd000053,
-0xdd830000,
-0x055cf880,
-0x80000003,
-0xd81f4100,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0xccc00054,
-0xcd000055,
-0xdd830000,
-0x055ce000,
-0x80000003,
-0xd81f4100,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0xccc00056,
-0xcd000057,
-0xdd830000,
-0x055cf000,
-0x80000003,
-0xd81f4100,
-0x7c40c000,
-0x7c410000,
-0x7c414000,
-0x7c418000,
-0xccc00058,
-0xcd000059,
-0xdd830000,
-0x055cf3fc,
-0x80000003,
-0xd81f4100,
-0xd0432000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xd043a000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xd043c000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xd043f8e0,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xd043f880,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xd043e000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xd043f000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xd043f3fc,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xc81403e0,
-0xcc430000,
-0xcc430000,
-0xcc430000,
-0x7d45c000,
-0xcdc30000,
-0xd0430000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0x7c40c000,
-0xc81003e2,
-0xc81403e5,
-0xc81803e3,
-0xc81c03e4,
-0xcd812169,
-0xcdc1216a,
-0xccc1216b,
-0xcc01216c,
-0x04200004,
-0x7da18000,
-0x7d964002,
-0x9640fcd9,
-0xcd8003e3,
-0x31280003,
-0xc02df000,
-0x25180008,
-0x7dad800b,
-0x7da9800c,
-0x80000003,
-0xcd8003e3,
-0x308cffff,
-0xd04d0000,
-0x7c408000,
-0xa0000000,
-0xcc800062,
-0xc8140020,
-0x15580002,
-0x9580ffff,
-0xc8140020,
-0xcc00006e,
-0xcc412180,
-0x7c40c000,
-0xccc1218d,
-0xcc412181,
-0x28d0001f,
-0x34588000,
-0xcd81218c,
-0x9500fcbf,
-0xcc412182,
-0xc8140020,
-0x9940ffff,
-0xc8140020,
-0x80000004,
-0x7c408000,
-0x7c40c000,
-0x28d00018,
-0x31100001,
-0xc0160080,
-0x95000003,
-0xc02a0004,
-0x7cd4c00c,
-0xccc1217c,
-0xcc41217d,
-0xcc41217e,
-0x7c418000,
-0x1db00003,
-0x36a0217f,
-0x9b000003,
-0x419c0005,
-0x041c0040,
-0x99c00000,
-0x09dc0001,
-0xcc210000,
-0xc8240004,
-0x2a6c001f,
-0x419c0005,
-0x9ac0fffa,
-0xcc800062,
-0x80000004,
-0x7c408000,
-0x7c40c000,
-0x04d403e6,
-0x80000003,
-0xcc540000,
-0x8000037e,
-0xcc4003ea,
-0xc01c8000,
-0x044ca000,
-0xcdc12010,
-0x7c410000,
-0xc8140009,
-0x04180000,
-0x041c0008,
-0xcd800071,
-0x09dc0001,
-0x05980001,
-0xcd0d0000,
-0x99c0fffc,
-0xcc800062,
-0x8000037e,
-0xcd400071,
-0xc00e0100,
-0xcc000041,
-0xccc1304a,
-0xc83c007f,
-0xcc00007f,
-0x80000003,
-0xcc00007f,
-0xcc00007f,
-0x88000000,
-0xcc00007f,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
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-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00000000,
-0x00010333,
-0x00100006,
-0x00170008,
-0x0021000a,
-0x0027002a,
-0x00280025,
-0x0029002b,
-0x002a0028,
-0x002b002b,
-0x002d003a,
-0x002e0041,
-0x002f004c,
-0x0034004e,
-0x00360032,
-0x003900b1,
-0x003a00d1,
-0x003b00e6,
-0x003c00fe,
-0x003d016d,
-0x003f00af,
-0x00410338,
-0x0043034b,
-0x00440190,
-0x004500fe,
-0x004601ae,
-0x004701ae,
-0x00480200,
-0x0049020e,
-0x004a0257,
-0x004b0284,
-0x00520261,
-0x00530273,
-0x00540289,
-0x0057029b,
-0x0060029f,
-0x006102ae,
-0x006202b8,
-0x006302c2,
-0x006402cc,
-0x006502d6,
-0x006602e0,
-0x006702ea,
-0x006802f4,
-0x006902f8,
-0x006a02fc,
-0x006b0300,
-0x006c0304,
-0x006d0308,
-0x006e030c,
-0x006f0310,
-0x00700314,
-0x00720365,
-0x0074036b,
-0x00790369,
-0x007c031e,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-0x000f037a,
-};
-
-#endif
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 79ad98264e3..1041a7c2805 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -695,6 +695,7 @@ struct radeon_device {
 	bool				suspend;
 	bool				need_dma32;
 	struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
+	const struct firmware *fw;	/* firmware */
 };
 
 int radeon_device_init(struct radeon_device *rdev,
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
index d8356827ef1..6b6cc8434d3 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -36,10 +36,25 @@
 #include "radeon_drv.h"
 #include "r300_reg.h"
 
-#include "radeon_microcode.h"
-
 #define RADEON_FIFO_DEBUG	0
 
+/* Firmware Names */
+#define FIRMWARE_R100		"radeon/R100_cp.bin"
+#define FIRMWARE_R200		"radeon/R200_cp.bin"
+#define FIRMWARE_R300		"radeon/R300_cp.bin"
+#define FIRMWARE_R420		"radeon/R420_cp.bin"
+#define FIRMWARE_RS690		"radeon/RS690_cp.bin"
+#define FIRMWARE_RS600		"radeon/RS600_cp.bin"
+#define FIRMWARE_R520		"radeon/R520_cp.bin"
+
+MODULE_FIRMWARE(FIRMWARE_R100);
+MODULE_FIRMWARE(FIRMWARE_R200);
+MODULE_FIRMWARE(FIRMWARE_R300);
+MODULE_FIRMWARE(FIRMWARE_R420);
+MODULE_FIRMWARE(FIRMWARE_RS690);
+MODULE_FIRMWARE(FIRMWARE_RS600);
+MODULE_FIRMWARE(FIRMWARE_R520);
+
 static int radeon_do_cleanup_cp(struct drm_device * dev);
 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
 
@@ -451,37 +466,34 @@ static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
  */
 
 /* Load the microcode for the CP */
-static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
+static int radeon_cp_init_microcode(drm_radeon_private_t *dev_priv)
 {
-	int i;
+	struct platform_device *pdev;
+	const char *fw_name = NULL;
+	int err;
+
 	DRM_DEBUG("\n");
 
-	radeon_do_wait_for_idle(dev_priv);
+	pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
+	err = IS_ERR(pdev);
+	if (err) {
+		printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
+		return -EINVAL;
+	}
 
-	RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 	if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
 	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
 	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
 	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
 	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
 		DRM_INFO("Loading R100 Microcode\n");
-		for (i = 0; i < 256; i++) {
-			RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
-				     R100_cp_microcode[i][1]);
-			RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
-				     R100_cp_microcode[i][0]);
-		}
+		fw_name = FIRMWARE_R100;
 	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
 		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
 		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
 		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
 		DRM_INFO("Loading R200 Microcode\n");
-		for (i = 0; i < 256; i++) {
-			RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
-				     R200_cp_microcode[i][1]);
-			RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
-				     R200_cp_microcode[i][0]);
-		}
+		fw_name = FIRMWARE_R200;
 	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
 		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
@@ -489,39 +501,19 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 		DRM_INFO("Loading R300 Microcode\n");
-		for (i = 0; i < 256; i++) {
-			RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
-				     R300_cp_microcode[i][1]);
-			RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
-				     R300_cp_microcode[i][0]);
-		}
+		fw_name = FIRMWARE_R300;
 	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
 		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
 		DRM_INFO("Loading R400 Microcode\n");
-		for (i = 0; i < 256; i++) {
-			RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
-				     R420_cp_microcode[i][1]);
-			RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
-				     R420_cp_microcode[i][0]);
-		}
+		fw_name = FIRMWARE_R420;
 	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 		DRM_INFO("Loading RS690/RS740 Microcode\n");
-		for (i = 0; i < 256; i++) {
-			RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
-				     RS690_cp_microcode[i][1]);
-			RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
-				     RS690_cp_microcode[i][0]);
-		}
+		fw_name = FIRMWARE_RS690;
 	} else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
 		DRM_INFO("Loading RS600 Microcode\n");
-		for (i = 0; i < 256; i++) {
-			RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
-				     RS600_cp_microcode[i][1]);
-			RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
-				     RS600_cp_microcode[i][0]);
-		}
+		fw_name = FIRMWARE_RS600;
 	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
 		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
 		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
@@ -529,11 +521,41 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
 		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
 		DRM_INFO("Loading R500 Microcode\n");
-		for (i = 0; i < 256; i++) {
+		fw_name = FIRMWARE_R520;
+	}
+
+	err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev);
+	platform_device_unregister(pdev);
+	if (err) {
+		printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
+		       fw_name);
+	} else if (dev_priv->me_fw->size % 8) {
+		printk(KERN_ERR
+		       "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
+		       dev_priv->me_fw->size, fw_name);
+		err = -EINVAL;
+		release_firmware(dev_priv->me_fw);
+		dev_priv->me_fw = NULL;
+	}
+	return err;
+}
+
+static void radeon_cp_load_microcode(drm_radeon_private_t *dev_priv)
+{
+	const __be32 *fw_data;
+	int i, size;
+
+	radeon_do_wait_for_idle(dev_priv);
+
+	if (dev_priv->me_fw) {
+		size = dev_priv->me_fw->size / 4;
+		fw_data = (const __be32 *)&dev_priv->me_fw->data[0];
+		RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
+		for (i = 0; i < size; i += 2) {
 			RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
-				     R520_cp_microcode[i][1]);
+				     be32_to_cpup(&fw_data[i]));
 			RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
-				     R520_cp_microcode[i][0]);
+				     be32_to_cpup(&fw_data[i + 1]));
 		}
 	}
 }
@@ -1486,6 +1508,14 @@ static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
 		radeon_set_pcigart(dev_priv, 1);
 	}
 
+	if (!dev_priv->me_fw) {
+		int err = radeon_cp_init_microcode(dev_priv);
+		if (err) {
+			DRM_ERROR("Failed to load firmware!\n");
+			radeon_do_cleanup_cp(dev);
+			return err;
+		}
+	}
 	radeon_cp_load_microcode(dev_priv);
 	radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
 
@@ -1755,6 +1785,14 @@ void radeon_do_release(struct drm_device * dev)
 			r600_do_cleanup_cp(dev);
 		else
 			radeon_do_cleanup_cp(dev);
+		if (dev_priv->me_fw) {
+			release_firmware(dev_priv->me_fw);
+			dev_priv->me_fw = NULL;
+		}
+		if (dev_priv->pfp_fw) {
+			release_firmware(dev_priv->pfp_fw);
+			dev_priv->pfp_fw = NULL;
+		}
 	}
 }
 
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index 3933f8216a3..45a6ad997f5 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -31,6 +31,9 @@
 #ifndef __RADEON_DRV_H__
 #define __RADEON_DRV_H__
 
+#include <linux/firmware.h>
+#include <linux/platform_device.h>
+
 /* General customization:
  */
 
@@ -351,6 +354,8 @@ typedef struct drm_radeon_private {
 	int r700_sc_hiz_tile_fifo_size;
 	int r700_sc_earlyz_tile_fifo_fize;
 
+	/* firmware */
+	const struct firmware *me_fw, *pfp_fw;
 } drm_radeon_private_t;
 
 typedef struct drm_radeon_buf_priv {
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index 9805e4b6ca1..1841145a7c4 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -28,7 +28,6 @@
 #include "drmP.h"
 #include "radeon_drm.h"
 #include "radeon_reg.h"
-#include "radeon_microcode.h"
 #include "radeon.h"
 #include "atom.h"
 
diff --git a/drivers/gpu/drm/radeon/radeon_microcode.h b/drivers/gpu/drm/radeon/radeon_microcode.h
deleted file mode 100644
index a348c9e7db1..00000000000
--- a/drivers/gpu/drm/radeon/radeon_microcode.h
+++ /dev/null
@@ -1,1844 +0,0 @@
-/*
- * Copyright 2007 Advanced Micro Devices, Inc.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef RADEON_MICROCODE_H
-#define RADEON_MICROCODE_H
-
-/* production radeon ucode r1xx-r6xx */
-static const u32 R100_cp_microcode[][2] = {
-    { 0x21007000, 0000000000 },
-    { 0x20007000, 0000000000 },
-    { 0x000000b4, 0x00000004 },
-    { 0x000000b8, 0x00000004 },
-    { 0x6f5b4d4c, 0000000000 },
-    { 0x4c4c427f, 0000000000 },
-    { 0x5b568a92, 0000000000 },
-    { 0x4ca09c6d, 0000000000 },
-    { 0xad4c4c4c, 0000000000 },
-    { 0x4ce1af3d, 0000000000 },
-    { 0xd8afafaf, 0000000000 },
-    { 0xd64c4cdc, 0000000000 },
-    { 0x4cd10d10, 0000000000 },
-    { 0x000f0000, 0x00000016 },
-    { 0x362f242d, 0000000000 },
-    { 0x00000012, 0x00000004 },
-    { 0x000f0000, 0x00000016 },
-    { 0x362f282d, 0000000000 },
-    { 0x000380e7, 0x00000002 },
-    { 0x04002c97, 0x00000002 },
-    { 0x000f0001, 0x00000016 },
-    { 0x333a3730, 0000000000 },
-    { 0x000077ef, 0x00000002 },
-    { 0x00061000, 0x00000002 },
-    { 0x00000021, 0x0000001a },
-    { 0x00004000, 0x0000001e },
-    { 0x00061000, 0x00000002 },
-    { 0x00000021, 0x0000001a },
-    { 0x00004000, 0x0000001e },
-    { 0x00061000, 0x00000002 },
-    { 0x00000021, 0x0000001a },
-    { 0x00004000, 0x0000001e },
-    { 0x00000017, 0x00000004 },
-    { 0x0003802b, 0x00000002 },
-    { 0x040067e0, 0x00000002 },
-    { 0x00000017, 0x00000004 },
-    { 0x000077e0, 0x00000002 },
-    { 0x00065000, 0x00000002 },
-    { 0x000037e1, 0x00000002 },
-    { 0x040067e1, 0x00000006 },
-    { 0x000077e0, 0x00000002 },
-    { 0x000077e1, 0x00000002 },
-    { 0x000077e1, 0x00000006 },
-    { 0xffffffff, 0000000000 },
-    { 0x10000000, 0000000000 },
-    { 0x0003802b, 0x00000002 },
-    { 0x040067e0, 0x00000006 },
-    { 0x00007675, 0x00000002 },
-    { 0x00007676, 0x00000002 },
-    { 0x00007677, 0x00000002 },
-    { 0x00007678, 0x00000006 },
-    { 0x0003802c, 0x00000002 },
-    { 0x04002676, 0x00000002 },
-    { 0x00007677, 0x00000002 },
-    { 0x00007678, 0x00000006 },
-    { 0x0000002f, 0x00000018 },
-    { 0x0000002f, 0x00000018 },
-    { 0000000000, 0x00000006 },
-    { 0x00000030, 0x00000018 },
-    { 0x00000030, 0x00000018 },
-    { 0000000000, 0x00000006 },
-    { 0x01605000, 0x00000002 },
-    { 0x00065000, 0x00000002 },
-    { 0x00098000, 0x00000002 },
-    { 0x00061000, 0x00000002 },
-    { 0x64c0603e, 0x00000004 },
-    { 0x000380e6, 0x00000002 },
-    { 0x040025c5, 0x00000002 },
-    { 0x00080000, 0x00000016 },
-    { 0000000000, 0000000000 },
-    { 0x0400251d, 0x00000002 },
-    { 0x00007580, 0x00000002 },
-    { 0x00067581, 0x00000002 },
-    { 0x04002580, 0x00000002 },
-    { 0x00067581, 0x00000002 },
-    { 0x00000049, 0x00000004 },
-    { 0x00005000, 0000000000 },
-    { 0x000380e6, 0x00000002 },
-    { 0x040025c5, 0x00000002 },
-    { 0x00061000, 0x00000002 },
-    { 0x0000750e, 0x00000002 },
-    { 0x00019000, 0x00000002 },
-    { 0x00011055, 0x00000014 },
-    { 0x00000055, 0x00000012 },
-    { 0x0400250f, 0x00000002 },
-    { 0x0000504f, 0x00000004 },
-    { 0x000380e6, 0x00000002 },
-    { 0x040025c5, 0x00000002 },
-    { 0x00007565, 0x00000002 },
-    { 0x00007566, 0x00000002 },
-    { 0x00000058, 0x00000004 },
-    { 0x000380e6, 0x00000002 },
-    { 0x040025c5, 0x00000002 },
-    { 0x01e655b4, 0x00000002 },
-    { 0x4401b0e4, 0x00000002 },
-    { 0x01c110e4, 0x00000002 },
-    { 0x26667066, 0x00000018 },
-    { 0x040c2565, 0x00000002 },
-    { 0x00000066, 0x00000018 },
-    { 0x04002564, 0x00000002 },
-    { 0x00007566, 0x00000002 },
-    { 0x0000005d, 0x00000004 },
-    { 0x00401069, 0x00000008 },
-    { 0x00101000, 0x00000002 },
-    { 0x000d80ff, 0x00000002 },
-    { 0x0080006c, 0x00000008 },
-    { 0x000f9000, 0x00000002 },
-    { 0x000e00ff, 0x00000002 },
-    { 0000000000, 0x00000006 },
-    { 0x0000008f, 0x00000018 },
-    { 0x0000005b, 0x00000004 },
-    { 0x000380e6, 0x00000002 },
-    { 0x040025c5, 0x00000002 },
-    { 0x00007576, 0x00000002 },
-    { 0x00065000, 0x00000002 },
-    { 0x00009000, 0x00000002 },
-    { 0x00041000, 0x00000002 },
-    { 0x0c00350e, 0x00000002 },
-    { 0x00049000, 0x00000002 },
-    { 0x00051000, 0x00000002 },
-    { 0x01e785f8, 0x00000002 },
-    { 0x00200000, 0x00000002 },
-    { 0x0060007e, 0x0000000c },
-    { 0x00007563, 0x00000002 },
-    { 0x006075f0, 0x00000021 },
-    { 0x20007073, 0x00000004 },
-    { 0x00005073, 0x00000004 },
-    { 0x000380e6, 0x00000002 },
-    { 0x040025c5, 0x00000002 },
-    { 0x00007576, 0x00000002 },
-    { 0x00007577, 0x00000002 },
-    { 0x0000750e, 0x00000002 },
-    { 0x0000750f, 0x00000002 },
-    { 0x00a05000, 0x00000002 },
-    { 0x00600083, 0x0000000c },
-    { 0x006075f0, 0x00000021 },
-    { 0x000075f8, 0x00000002 },
-    { 0x00000083, 0x00000004 },
-    { 0x000a750e, 0x00000002 },
-    { 0x000380e6, 0x00000002 },
-    { 0x040025c5, 0x00000002 },
-    { 0x0020750f, 0x00000002 },
-    { 0x00600086, 0x00000004 },
-    { 0x00007570, 0x00000002 },
-    { 0x00007571, 0x00000002 },
-    { 0x00007572, 0x00000006 },
-    { 0x000380e6, 0x00000002 },
-    { 0x040025c5, 0x00000002 },
-    { 0x00005000, 0x00000002 },
-    { 0x00a05000, 0x00000002 },
-    { 0x00007568, 0x00000002 },
-    { 0x00061000, 0x00000002 },
-    { 0x00000095, 0x0000000c },
-    { 0x00058000, 0x00000002 },
-    { 0x0c607562, 0x00000002 },
-    { 0x00000097, 0x00000004 },
-    { 0x000380e6, 0x00000002 },
-    { 0x040025c5, 0x00000002 },
-    { 0x00600096, 0x00000004 },
-    { 0x400070e5, 0000000000 },
-    { 0x000380e6, 0x00000002 },
-    { 0x040025c5, 0x00000002 },
-    { 0x000380e5, 0x00000002 },
-    { 0x000000a8, 0x0000001c },
-    { 0x000650aa, 0x00000018 },
-    { 0x040025bb, 0x00000002 },
-    { 0x000610ab, 0x00000018 },
-    { 0x040075bc, 0000000000 },
-    { 0x000075bb, 0x00000002 },
-    { 0x000075bc, 0000000000 },
-    { 0x00090000, 0x00000006 },
-    { 0x00090000, 0x00000002 },
-    { 0x000d8002, 0x00000006 },
-    { 0x00007832, 0x00000002 },
-    { 0x00005000, 0x00000002 },
-    { 0x000380e7, 0x00000002 },
-    { 0x04002c97, 0x00000002 },
-    { 0x00007820, 0x00000002 },
-    { 0x00007821, 0x00000002 },
-    { 0x00007800, 0000000000 },
-    { 0x01200000, 0x00000002 },
-    { 0x20077000, 0x00000002 },
-    { 0x01200000, 0x00000002 },
-    { 0x20007000, 0x00000002 },
-    { 0x00061000, 0x00000002 },
-    { 0x0120751b, 0x00000002 },
-    { 0x8040750a, 0x00000002 },
-    { 0x8040750b, 0x00000002 },
-    { 0x00110000, 0x00000002 },
-    { 0x000380e5, 0x00000002 },
-    { 0x000000c6, 0x0000001c },
-    { 0x000610ab, 0x00000018 },
-    { 0x844075bd, 0x00000002 },
-    { 0x000610aa, 0x00000018 },
-    { 0x840075bb, 0x00000002 },
-    { 0x000610ab, 0x00000018 },
-    { 0x844075bc, 0x00000002 },
-    { 0x000000c9, 0x00000004 },
-    { 0x804075bd, 0x00000002 },
-    { 0x800075bb, 0x00000002 },
-    { 0x804075bc, 0x00000002 },
-    { 0x00108000, 0x00000002 },
-    { 0x01400000, 0x00000002 },
-    { 0x006000cd, 0x0000000c },
-    { 0x20c07000, 0x00000020 },
-    { 0x000000cf, 0x00000012 },
-    { 0x00800000, 0x00000006 },
-    { 0x0080751d, 0x00000006 },
-    { 0000000000, 0000000000 },
-    { 0x0000775c, 0x00000002 },
-    { 0x00a05000, 0x00000002 },
-    { 0x00661000, 0x00000002 },
-    { 0x0460275d, 0x00000020 },
-    { 0x00004000, 0000000000 },
-    { 0x01e00830, 0x00000002 },
-    { 0x21007000, 0000000000 },
-    { 0x6464614d, 0000000000 },
-    { 0x69687420, 0000000000 },
-    { 0x00000073, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0x00005000, 0x00000002 },
-    { 0x000380d0, 0x00000002 },
-    { 0x040025e0, 0x00000002 },
-    { 0x000075e1, 0000000000 },
-    { 0x00000001, 0000000000 },
-    { 0x000380e0, 0x00000002 },
-    { 0x04002394, 0x00000002 },
-    { 0x00005000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0x00000008, 0000000000 },
-    { 0x00000004, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-};
-
-static const u32 R200_cp_microcode[][2] = {
-    { 0x21007000, 0000000000 },
-    { 0x20007000, 0000000000 },
-    { 0x000000bf, 0x00000004 },
-    { 0x000000c3, 0x00000004 },
-    { 0x7a685e5d, 0000000000 },
-    { 0x5d5d5588, 0000000000 },
-    { 0x68659197, 0000000000 },
-    { 0x5da19f78, 0000000000 },
-    { 0x5d5d5d5d, 0000000000 },
-    { 0x5dee5d50, 0000000000 },
-    { 0xf2acacac, 0000000000 },
-    { 0xe75df9e9, 0000000000 },
-    { 0xb1dd0e11, 0000000000 },
-    { 0xe2afafaf, 0000000000 },
-    { 0x000f0000, 0x00000016 },
-    { 0x452f232d, 0000000000 },
-    { 0x00000013, 0x00000004 },
-    { 0x000f0000, 0x00000016 },
-    { 0x452f272d, 0000000000 },
-    { 0x000f0001, 0x00000016 },
-    { 0x3e4d4a37, 0000000000 },
-    { 0x000077ef, 0x00000002 },
-    { 0x00061000, 0x00000002 },
-    { 0x00000020, 0x0000001a },
-    { 0x00004000, 0x0000001e },
-    { 0x00061000, 0x00000002 },
-    { 0x00000020, 0x0000001a },
-    { 0x00004000, 0x0000001e },
-    { 0x00061000, 0x00000002 },
-    { 0x00000020, 0x0000001a },
-    { 0x00004000, 0x0000001e },
-    { 0x00000016, 0x00000004 },
-    { 0x0003802a, 0x00000002 },
-    { 0x040067e0, 0x00000002 },
-    { 0x00000016, 0x00000004 },
-    { 0x000077e0, 0x00000002 },
-    { 0x00065000, 0x00000002 },
-    { 0x000037e1, 0x00000002 },
-    { 0x040067e1, 0x00000006 },
-    { 0x000077e0, 0x00000002 },
-    { 0x000077e1, 0x00000002 },
-    { 0x000077e1, 0x00000006 },
-    { 0xffffffff, 0000000000 },
-    { 0x10000000, 0000000000 },
-    { 0x07f007f0, 0000000000 },
-    { 0x0003802a, 0x00000002 },
-    { 0x040067e0, 0x00000006 },
-    { 0x0003802c, 0x00000002 },
-    { 0x04002741, 0x00000002 },
-    { 0x04002741, 0x00000002 },
-    { 0x04002743, 0x00000002 },
-    { 0x00007675, 0x00000002 },
-    { 0x00007676, 0x00000002 },
-    { 0x00007677, 0x00000002 },
-    { 0x00007678, 0x00000006 },
-    { 0x0003802c, 0x00000002 },
-    { 0x04002741, 0x00000002 },
-    { 0x04002741, 0x00000002 },
-    { 0x04002743, 0x00000002 },
-    { 0x00007676, 0x00000002 },
-    { 0x00007677, 0x00000002 },
-    { 0x00007678, 0x00000006 },
-    { 0x0003802b, 0x00000002 },
-    { 0x04002676, 0x00000002 },
-    { 0x00007677, 0x00000002 },
-    { 0x0003802c, 0x00000002 },
-    { 0x04002741, 0x00000002 },
-    { 0x04002743, 0x00000002 },
-    { 0x00007678, 0x00000006 },
-    { 0x0003802c, 0x00000002 },
-    { 0x04002741, 0x00000002 },
-    { 0x04002741, 0x00000002 },
-    { 0x04002743, 0x00000002 },
-    { 0x00007678, 0x00000006 },
-    { 0x0000002f, 0x00000018 },
-    { 0x0000002f, 0x00000018 },
-    { 0000000000, 0x00000006 },
-    { 0x00000037, 0x00000018 },
-    { 0x00000037, 0x00000018 },
-    { 0000000000, 0x00000006 },
-    { 0x01605000, 0x00000002 },
-    { 0x00065000, 0x00000002 },
-    { 0x00098000, 0x00000002 },
-    { 0x00061000, 0x00000002 },
-    { 0x64c06051, 0x00000004 },
-    { 0x00080000, 0x00000016 },
-    { 0000000000, 0000000000 },
-    { 0x0400251d, 0x00000002 },
-    { 0x00007580, 0x00000002 },
-    { 0x00067581, 0x00000002 },
-    { 0x04002580, 0x00000002 },
-    { 0x00067581, 0x00000002 },
-    { 0x0000005a, 0x00000004 },
-    { 0x00005000, 0000000000 },
-    { 0x00061000, 0x00000002 },
-    { 0x0000750e, 0x00000002 },
-    { 0x00019000, 0x00000002 },
-    { 0x00011064, 0x00000014 },
-    { 0x00000064, 0x00000012 },
-    { 0x0400250f, 0x00000002 },
-    { 0x0000505e, 0x00000004 },
-    { 0x00007565, 0x00000002 },
-    { 0x00007566, 0x00000002 },
-    { 0x00000065, 0x00000004 },
-    { 0x01e655b4, 0x00000002 },
-    { 0x4401b0f0, 0x00000002 },
-    { 0x01c110f0, 0x00000002 },
-    { 0x26667071, 0x00000018 },
-    { 0x040c2565, 0x00000002 },
-    { 0x00000071, 0x00000018 },
-    { 0x04002564, 0x00000002 },
-    { 0x00007566, 0x00000002 },
-    { 0x00000068, 0x00000004 },
-    { 0x00401074, 0x00000008 },
-    { 0x00101000, 0x00000002 },
-    { 0x000d80ff, 0x00000002 },
-    { 0x00800077, 0x00000008 },
-    { 0x000f9000, 0x00000002 },
-    { 0x000e00ff, 0x00000002 },
-    { 0000000000, 0x00000006 },
-    { 0x00000094, 0x00000018 },
-    { 0x00000068, 0x00000004 },
-    { 0x00007576, 0x00000002 },
-    { 0x00065000, 0x00000002 },
-    { 0x00009000, 0x00000002 },
-    { 0x00041000, 0x00000002 },
-    { 0x0c00350e, 0x00000002 },
-    { 0x00049000, 0x00000002 },
-    { 0x00051000, 0x00000002 },
-    { 0x01e785f8, 0x00000002 },
-    { 0x00200000, 0x00000002 },
-    { 0x00600087, 0x0000000c },
-    { 0x00007563, 0x00000002 },
-    { 0x006075f0, 0x00000021 },
-    { 0x2000707c, 0x00000004 },
-    { 0x0000507c, 0x00000004 },
-    { 0x00007576, 0x00000002 },
-    { 0x00007577, 0x00000002 },
-    { 0x0000750e, 0x00000002 },
-    { 0x0000750f, 0x00000002 },
-    { 0x00a05000, 0x00000002 },
-    { 0x0060008a, 0x0000000c },
-    { 0x006075f0, 0x00000021 },
-    { 0x000075f8, 0x00000002 },
-    { 0x0000008a, 0x00000004 },
-    { 0x000a750e, 0x00000002 },
-    { 0x0020750f, 0x00000002 },
-    { 0x0060008d, 0x00000004 },
-    { 0x00007570, 0x00000002 },
-    { 0x00007571, 0x00000002 },
-    { 0x00007572, 0x00000006 },
-    { 0x00005000, 0x00000002 },
-    { 0x00a05000, 0x00000002 },
-    { 0x00007568, 0x00000002 },
-    { 0x00061000, 0x00000002 },
-    { 0x00000098, 0x0000000c },
-    { 0x00058000, 0x00000002 },
-    { 0x0c607562, 0x00000002 },
-    { 0x0000009a, 0x00000004 },
-    { 0x00600099, 0x00000004 },
-    { 0x400070f1, 0000000000 },
-    { 0x000380f1, 0x00000002 },
-    { 0x000000a7, 0x0000001c },
-    { 0x000650a9, 0x00000018 },
-    { 0x040025bb, 0x00000002 },
-    { 0x000610aa, 0x00000018 },
-    { 0x040075bc, 0000000000 },
-    { 0x000075bb, 0x00000002 },
-    { 0x000075bc, 0000000000 },
-    { 0x00090000, 0x00000006 },
-    { 0x00090000, 0x00000002 },
-    { 0x000d8002, 0x00000006 },
-    { 0x00005000, 0x00000002 },
-    { 0x00007821, 0x00000002 },
-    { 0x00007800, 0000000000 },
-    { 0x00007821, 0x00000002 },
-    { 0x00007800, 0000000000 },
-    { 0x01665000, 0x00000002 },
-    { 0x000a0000, 0x00000002 },
-    { 0x000671cc, 0x00000002 },
-    { 0x0286f1cd, 0x00000002 },
-    { 0x000000b7, 0x00000010 },
-    { 0x21007000, 0000000000 },
-    { 0x000000be, 0x0000001c },
-    { 0x00065000, 0x00000002 },
-    { 0x000a0000, 0x00000002 },
-    { 0x00061000, 0x00000002 },
-    { 0x000b0000, 0x00000002 },
-    { 0x38067000, 0x00000002 },
-    { 0x000a00ba, 0x00000004 },
-    { 0x20007000, 0000000000 },
-    { 0x01200000, 0x00000002 },
-    { 0x20077000, 0x00000002 },
-    { 0x01200000, 0x00000002 },
-    { 0x20007000, 0000000000 },
-    { 0x00061000, 0x00000002 },
-    { 0x0120751b, 0x00000002 },
-    { 0x8040750a, 0x00000002 },
-    { 0x8040750b, 0x00000002 },
-    { 0x00110000, 0x00000002 },
-    { 0x000380f1, 0x00000002 },
-    { 0x000000d1, 0x0000001c },
-    { 0x000610aa, 0x00000018 },
-    { 0x844075bd, 0x00000002 },
-    { 0x000610a9, 0x00000018 },
-    { 0x840075bb, 0x00000002 },
-    { 0x000610aa, 0x00000018 },
-    { 0x844075bc, 0x00000002 },
-    { 0x000000d4, 0x00000004 },
-    { 0x804075bd, 0x00000002 },
-    { 0x800075bb, 0x00000002 },
-    { 0x804075bc, 0x00000002 },
-    { 0x00108000, 0x00000002 },
-    { 0x01400000, 0x00000002 },
-    { 0x006000d8, 0x0000000c },
-    { 0x20c07000, 0x00000020 },
-    { 0x000000da, 0x00000012 },
-    { 0x00800000, 0x00000006 },
-    { 0x0080751d, 0x00000006 },
-    { 0x000025bb, 0x00000002 },
-    { 0x000040d4, 0x00000004 },
-    { 0x0000775c, 0x00000002 },
-    { 0x00a05000, 0x00000002 },
-    { 0x00661000, 0x00000002 },
-    { 0x0460275d, 0x00000020 },
-    { 0x00004000, 0000000000 },
-    { 0x00007999, 0x00000002 },
-    { 0x00a05000, 0x00000002 },
-    { 0x00661000, 0x00000002 },
-    { 0x0460299b, 0x00000020 },
-    { 0x00004000, 0000000000 },
-    { 0x01e00830, 0x00000002 },
-    { 0x21007000, 0000000000 },
-    { 0x00005000, 0x00000002 },
-    { 0x00038056, 0x00000002 },
-    { 0x040025e0, 0x00000002 },
-    { 0x000075e1, 0000000000 },
-    { 0x00000001, 0000000000 },
-    { 0x000380ed, 0x00000002 },
-    { 0x04007394, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0x000078c4, 0x00000002 },
-    { 0x000078c5, 0x00000002 },
-    { 0x000078c6, 0x00000002 },
-    { 0x00007924, 0x00000002 },
-    { 0x00007925, 0x00000002 },
-    { 0x00007926, 0x00000002 },
-    { 0x000000f2, 0x00000004 },
-    { 0x00007924, 0x00000002 },
-    { 0x00007925, 0x00000002 },
-    { 0x00007926, 0x00000002 },
-    { 0x000000f9, 0x00000004 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-};
-
-static const u32 R300_cp_microcode[][2] = {
-    { 0x4200e000, 0000000000 },
-    { 0x4000e000, 0000000000 },
-    { 0x000000ae, 0x00000008 },
-    { 0x000000b2, 0x00000008 },
-    { 0x67554b4a, 0000000000 },
-    { 0x4a4a4475, 0000000000 },
-    { 0x55527d83, 0000000000 },
-    { 0x4a8c8b65, 0000000000 },
-    { 0x4aef4af6, 0000000000 },
-    { 0x4ae14a4a, 0000000000 },
-    { 0xe4979797, 0000000000 },
-    { 0xdb4aebdd, 0000000000 },
-    { 0x9ccc4a4a, 0000000000 },
-    { 0xd1989898, 0000000000 },
-    { 0x4a0f9ad6, 0000000000 },
-    { 0x000ca000, 0x00000004 },
-    { 0x000d0012, 0x00000038 },
-    { 0x0000e8b4, 0x00000004 },
-    { 0x000d0014, 0x00000038 },
-    { 0x0000e8b6, 0x00000004 },
-    { 0x000d0016, 0x00000038 },
-    { 0x0000e854, 0x00000004 },
-    { 0x000d0018, 0x00000038 },
-    { 0x0000e855, 0x00000004 },
-    { 0x000d001a, 0x00000038 },
-    { 0x0000e856, 0x00000004 },
-    { 0x000d001c, 0x00000038 },
-    { 0x0000e857, 0x00000004 },
-    { 0x000d001e, 0x00000038 },
-    { 0x0000e824, 0x00000004 },
-    { 0x000d0020, 0x00000038 },
-    { 0x0000e825, 0x00000004 },
-    { 0x000d0022, 0x00000038 },
-    { 0x0000e830, 0x00000004 },
-    { 0x000d0024, 0x00000038 },
-    { 0x0000f0c0, 0x00000004 },
-    { 0x000d0026, 0x00000038 },
-    { 0x0000f0c1, 0x00000004 },
-    { 0x000d0028, 0x00000038 },
-    { 0x0000f041, 0x00000004 },
-    { 0x000d002a, 0x00000038 },
-    { 0x0000f184, 0x00000004 },
-    { 0x000d002c, 0x00000038 },
-    { 0x0000f185, 0x00000004 },
-    { 0x000d002e, 0x00000038 },
-    { 0x0000f186, 0x00000004 },
-    { 0x000d0030, 0x00000038 },
-    { 0x0000f187, 0x00000004 },
-    { 0x000d0032, 0x00000038 },
-    { 0x0000f180, 0x00000004 },
-    { 0x000d0034, 0x00000038 },
-    { 0x0000f393, 0x00000004 },
-    { 0x000d0036, 0x00000038 },
-    { 0x0000f38a, 0x00000004 },
-    { 0x000d0038, 0x00000038 },
-    { 0x0000f38e, 0x00000004 },
-    { 0x0000e821, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x00000043, 0x00000018 },
-    { 0x00cce800, 0x00000004 },
-    { 0x001b0001, 0x00000004 },
-    { 0x08004800, 0x00000004 },
-    { 0x001b0001, 0x00000004 },
-    { 0x08004800, 0x00000004 },
-    { 0x001b0001, 0x00000004 },
-    { 0x08004800, 0x00000004 },
-    { 0x0000003a, 0x00000008 },
-    { 0x0000a000, 0000000000 },
-    { 0x2000451d, 0x00000004 },
-    { 0x0000e580, 0x00000004 },
-    { 0x000ce581, 0x00000004 },
-    { 0x08004580, 0x00000004 },
-    { 0x000ce581, 0x00000004 },
-    { 0x00000047, 0x00000008 },
-    { 0x0000a000, 0000000000 },
-    { 0x000c2000, 0x00000004 },
-    { 0x0000e50e, 0x00000004 },
-    { 0x00032000, 0x00000004 },
-    { 0x00022051, 0x00000028 },
-    { 0x00000051, 0x00000024 },
-    { 0x0800450f, 0x00000004 },
-    { 0x0000a04b, 0x00000008 },
-    { 0x0000e565, 0x00000004 },
-    { 0x0000e566, 0x00000004 },
-    { 0x00000052, 0x00000008 },
-    { 0x03cca5b4, 0x00000004 },
-    { 0x05432000, 0x00000004 },
-    { 0x00022000, 0x00000004 },
-    { 0x4ccce05e, 0x00000030 },
-    { 0x08274565, 0x00000004 },
-    { 0x0000005e, 0x00000030 },
-    { 0x08004564, 0x00000004 },
-    { 0x0000e566, 0x00000004 },
-    { 0x00000055, 0x00000008 },
-    { 0x00802061, 0x00000010 },
-    { 0x00202000, 0x00000004 },
-    { 0x001b00ff, 0x00000004 },
-    { 0x01000064, 0x00000010 },
-    { 0x001f2000, 0x00000004 },
-    { 0x001c00ff, 0x00000004 },
-    { 0000000000, 0x0000000c },
-    { 0x00000080, 0x00000030 },
-    { 0x00000055, 0x00000008 },
-    { 0x0000e576, 0x00000004 },
-    { 0x000ca000, 0x00000004 },
-    { 0x00012000, 0x00000004 },
-    { 0x00082000, 0x00000004 },
-    { 0x1800650e, 0x00000004 },
-    { 0x00092000, 0x00000004 },
-    { 0x000a2000, 0x00000004 },
-    { 0x000f0000, 0x00000004 },
-    { 0x00400000, 0x00000004 },
-    { 0x00000074, 0x00000018 },
-    { 0x0000e563, 0x00000004 },
-    { 0x00c0e5f9, 0x000000c2 },
-    { 0x00000069, 0x00000008 },
-    { 0x0000a069, 0x00000008 },
-    { 0x0000e576, 0x00000004 },
-    { 0x0000e577, 0x00000004 },
-    { 0x0000e50e, 0x00000004 },
-    { 0x0000e50f, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x00000077, 0x00000018 },
-    { 0x00c0e5f9, 0x000000c2 },
-    { 0x00000077, 0x00000008 },
-    { 0x0014e50e, 0x00000004 },
-    { 0x0040e50f, 0x00000004 },
-    { 0x00c0007a, 0x00000008 },
-    { 0x0000e570, 0x00000004 },
-    { 0x0000e571, 0x00000004 },
-    { 0x0000e572, 0x0000000c },
-    { 0x0000a000, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x0000e568, 0x00000004 },
-    { 0x000c2000, 0x00000004 },
-    { 0x00000084, 0x00000018 },
-    { 0x000b0000, 0x00000004 },
-    { 0x18c0e562, 0x00000004 },
-    { 0x00000086, 0x00000008 },
-    { 0x00c00085, 0x00000008 },
-    { 0x000700e3, 0x00000004 },
-    { 0x00000092, 0x00000038 },
-    { 0x000ca094, 0x00000030 },
-    { 0x080045bb, 0x00000004 },
-    { 0x000c2095, 0x00000030 },
-    { 0x0800e5bc, 0000000000 },
-    { 0x0000e5bb, 0x00000004 },
-    { 0x0000e5bc, 0000000000 },
-    { 0x00120000, 0x0000000c },
-    { 0x00120000, 0x00000004 },
-    { 0x001b0002, 0x0000000c },
-    { 0x0000a000, 0x00000004 },
-    { 0x0000e821, 0x00000004 },
-    { 0x0000e800, 0000000000 },
-    { 0x0000e821, 0x00000004 },
-    { 0x0000e82e, 0000000000 },
-    { 0x02cca000, 0x00000004 },
-    { 0x00140000, 0x00000004 },
-    { 0x000ce1cc, 0x00000004 },
-    { 0x050de1cd, 0x00000004 },
-    { 0x00400000, 0x00000004 },
-    { 0x000000a4, 0x00000018 },
-    { 0x00c0a000, 0x00000004 },
-    { 0x000000a1, 0x00000008 },
-    { 0x000000a6, 0x00000020 },
-    { 0x4200e000, 0000000000 },
-    { 0x000000ad, 0x00000038 },
-    { 0x000ca000, 0x00000004 },
-    { 0x00140000, 0x00000004 },
-    { 0x000c2000, 0x00000004 },
-    { 0x00160000, 0x00000004 },
-    { 0x700ce000, 0x00000004 },
-    { 0x001400a9, 0x00000008 },
-    { 0x4000e000, 0000000000 },
-    { 0x02400000, 0x00000004 },
-    { 0x400ee000, 0x00000004 },
-    { 0x02400000, 0x00000004 },
-    { 0x4000e000, 0000000000 },
-    { 0x000c2000, 0x00000004 },
-    { 0x0240e51b, 0x00000004 },
-    { 0x0080e50a, 0x00000005 },
-    { 0x0080e50b, 0x00000005 },
-    { 0x00220000, 0x00000004 },
-    { 0x000700e3, 0x00000004 },
-    { 0x000000c0, 0x00000038 },
-    { 0x000c2095, 0x00000030 },
-    { 0x0880e5bd, 0x00000005 },
-    { 0x000c2094, 0x00000030 },
-    { 0x0800e5bb, 0x00000005 },
-    { 0x000c2095, 0x00000030 },
-    { 0x0880e5bc, 0x00000005 },
-    { 0x000000c3, 0x00000008 },
-    { 0x0080e5bd, 0x00000005 },
-    { 0x0000e5bb, 0x00000005 },
-    { 0x0080e5bc, 0x00000005 },
-    { 0x00210000, 0x00000004 },
-    { 0x02800000, 0x00000004 },
-    { 0x00c000c7, 0x00000018 },
-    { 0x4180e000, 0x00000040 },
-    { 0x000000c9, 0x00000024 },
-    { 0x01000000, 0x0000000c },
-    { 0x0100e51d, 0x0000000c },
-    { 0x000045bb, 0x00000004 },
-    { 0x000080c3, 0x00000008 },
-    { 0x0000f3ce, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x00cc2000, 0x00000004 },
-    { 0x08c053cf, 0x00000040 },
-    { 0x00008000, 0000000000 },
-    { 0x0000f3d2, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x00cc2000, 0x00000004 },
-    { 0x08c053d3, 0x00000040 },
-    { 0x00008000, 0000000000 },
-    { 0x0000f39d, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x00cc2000, 0x00000004 },
-    { 0x08c0539e, 0x00000040 },
-    { 0x00008000, 0000000000 },
-    { 0x03c00830, 0x00000004 },
-    { 0x4200e000, 0000000000 },
-    { 0x0000a000, 0x00000004 },
-    { 0x200045e0, 0x00000004 },
-    { 0x0000e5e1, 0000000000 },
-    { 0x00000001, 0000000000 },
-    { 0x000700e0, 0x00000004 },
-    { 0x0800e394, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0x0000e8c4, 0x00000004 },
-    { 0x0000e8c5, 0x00000004 },
-    { 0x0000e8c6, 0x00000004 },
-    { 0x0000e928, 0x00000004 },
-    { 0x0000e929, 0x00000004 },
-    { 0x0000e92a, 0x00000004 },
-    { 0x000000e4, 0x00000008 },
-    { 0x0000e928, 0x00000004 },
-    { 0x0000e929, 0x00000004 },
-    { 0x0000e92a, 0x00000004 },
-    { 0x000000eb, 0x00000008 },
-    { 0x02c02000, 0x00000004 },
-    { 0x00060000, 0x00000004 },
-    { 0x000000f3, 0x00000034 },
-    { 0x000000f0, 0x00000008 },
-    { 0x00008000, 0x00000004 },
-    { 0xc000e000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0x000c2000, 0x00000004 },
-    { 0x001d0018, 0x00000004 },
-    { 0x001a0001, 0x00000004 },
-    { 0x000000fb, 0x00000034 },
-    { 0x0000004a, 0x00000008 },
-    { 0x0500a04a, 0x00000008 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-};
-
-static const u32 R420_cp_microcode[][2] = {
-    { 0x4200e000, 0000000000 },
-    { 0x4000e000, 0000000000 },
-    { 0x00000099, 0x00000008 },
-    { 0x0000009d, 0x00000008 },
-    { 0x4a554b4a, 0000000000 },
-    { 0x4a4a4467, 0000000000 },
-    { 0x55526f75, 0000000000 },
-    { 0x4a7e7d65, 0000000000 },
-    { 0xd9d3dff6, 0000000000 },
-    { 0x4ac54a4a, 0000000000 },
-    { 0xc8828282, 0000000000 },
-    { 0xbf4acfc1, 0000000000 },
-    { 0x87b04a4a, 0000000000 },
-    { 0xb5838383, 0000000000 },
-    { 0x4a0f85ba, 0000000000 },
-    { 0x000ca000, 0x00000004 },
-    { 0x000d0012, 0x00000038 },
-    { 0x0000e8b4, 0x00000004 },
-    { 0x000d0014, 0x00000038 },
-    { 0x0000e8b6, 0x00000004 },
-    { 0x000d0016, 0x00000038 },
-    { 0x0000e854, 0x00000004 },
-    { 0x000d0018, 0x00000038 },
-    { 0x0000e855, 0x00000004 },
-    { 0x000d001a, 0x00000038 },
-    { 0x0000e856, 0x00000004 },
-    { 0x000d001c, 0x00000038 },
-    { 0x0000e857, 0x00000004 },
-    { 0x000d001e, 0x00000038 },
-    { 0x0000e824, 0x00000004 },
-    { 0x000d0020, 0x00000038 },
-    { 0x0000e825, 0x00000004 },
-    { 0x000d0022, 0x00000038 },
-    { 0x0000e830, 0x00000004 },
-    { 0x000d0024, 0x00000038 },
-    { 0x0000f0c0, 0x00000004 },
-    { 0x000d0026, 0x00000038 },
-    { 0x0000f0c1, 0x00000004 },
-    { 0x000d0028, 0x00000038 },
-    { 0x0000f041, 0x00000004 },
-    { 0x000d002a, 0x00000038 },
-    { 0x0000f184, 0x00000004 },
-    { 0x000d002c, 0x00000038 },
-    { 0x0000f185, 0x00000004 },
-    { 0x000d002e, 0x00000038 },
-    { 0x0000f186, 0x00000004 },
-    { 0x000d0030, 0x00000038 },
-    { 0x0000f187, 0x00000004 },
-    { 0x000d0032, 0x00000038 },
-    { 0x0000f180, 0x00000004 },
-    { 0x000d0034, 0x00000038 },
-    { 0x0000f393, 0x00000004 },
-    { 0x000d0036, 0x00000038 },
-    { 0x0000f38a, 0x00000004 },
-    { 0x000d0038, 0x00000038 },
-    { 0x0000f38e, 0x00000004 },
-    { 0x0000e821, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x00000043, 0x00000018 },
-    { 0x00cce800, 0x00000004 },
-    { 0x001b0001, 0x00000004 },
-    { 0x08004800, 0x00000004 },
-    { 0x001b0001, 0x00000004 },
-    { 0x08004800, 0x00000004 },
-    { 0x001b0001, 0x00000004 },
-    { 0x08004800, 0x00000004 },
-    { 0x0000003a, 0x00000008 },
-    { 0x0000a000, 0000000000 },
-    { 0x2000451d, 0x00000004 },
-    { 0x0000e580, 0x00000004 },
-    { 0x000ce581, 0x00000004 },
-    { 0x08004580, 0x00000004 },
-    { 0x000ce581, 0x00000004 },
-    { 0x00000047, 0x00000008 },
-    { 0x0000a000, 0000000000 },
-    { 0x000c2000, 0x00000004 },
-    { 0x0000e50e, 0x00000004 },
-    { 0x00032000, 0x00000004 },
-    { 0x00022051, 0x00000028 },
-    { 0x00000051, 0x00000024 },
-    { 0x0800450f, 0x00000004 },
-    { 0x0000a04b, 0x00000008 },
-    { 0x0000e565, 0x00000004 },
-    { 0x0000e566, 0x00000004 },
-    { 0x00000052, 0x00000008 },
-    { 0x03cca5b4, 0x00000004 },
-    { 0x05432000, 0x00000004 },
-    { 0x00022000, 0x00000004 },
-    { 0x4ccce05e, 0x00000030 },
-    { 0x08274565, 0x00000004 },
-    { 0x0000005e, 0x00000030 },
-    { 0x08004564, 0x00000004 },
-    { 0x0000e566, 0x00000004 },
-    { 0x00000055, 0x00000008 },
-    { 0x00802061, 0x00000010 },
-    { 0x00202000, 0x00000004 },
-    { 0x001b00ff, 0x00000004 },
-    { 0x01000064, 0x00000010 },
-    { 0x001f2000, 0x00000004 },
-    { 0x001c00ff, 0x00000004 },
-    { 0000000000, 0x0000000c },
-    { 0x00000072, 0x00000030 },
-    { 0x00000055, 0x00000008 },
-    { 0x0000e576, 0x00000004 },
-    { 0x0000e577, 0x00000004 },
-    { 0x0000e50e, 0x00000004 },
-    { 0x0000e50f, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x00000069, 0x00000018 },
-    { 0x00c0e5f9, 0x000000c2 },
-    { 0x00000069, 0x00000008 },
-    { 0x0014e50e, 0x00000004 },
-    { 0x0040e50f, 0x00000004 },
-    { 0x00c0006c, 0x00000008 },
-    { 0x0000e570, 0x00000004 },
-    { 0x0000e571, 0x00000004 },
-    { 0x0000e572, 0x0000000c },
-    { 0x0000a000, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x0000e568, 0x00000004 },
-    { 0x000c2000, 0x00000004 },
-    { 0x00000076, 0x00000018 },
-    { 0x000b0000, 0x00000004 },
-    { 0x18c0e562, 0x00000004 },
-    { 0x00000078, 0x00000008 },
-    { 0x00c00077, 0x00000008 },
-    { 0x000700c7, 0x00000004 },
-    { 0x00000080, 0x00000038 },
-    { 0x0000e5bb, 0x00000004 },
-    { 0x0000e5bc, 0000000000 },
-    { 0x0000a000, 0x00000004 },
-    { 0x0000e821, 0x00000004 },
-    { 0x0000e800, 0000000000 },
-    { 0x0000e821, 0x00000004 },
-    { 0x0000e82e, 0000000000 },
-    { 0x02cca000, 0x00000004 },
-    { 0x00140000, 0x00000004 },
-    { 0x000ce1cc, 0x00000004 },
-    { 0x050de1cd, 0x00000004 },
-    { 0x00400000, 0x00000004 },
-    { 0x0000008f, 0x00000018 },
-    { 0x00c0a000, 0x00000004 },
-    { 0x0000008c, 0x00000008 },
-    { 0x00000091, 0x00000020 },
-    { 0x4200e000, 0000000000 },
-    { 0x00000098, 0x00000038 },
-    { 0x000ca000, 0x00000004 },
-    { 0x00140000, 0x00000004 },
-    { 0x000c2000, 0x00000004 },
-    { 0x00160000, 0x00000004 },
-    { 0x700ce000, 0x00000004 },
-    { 0x00140094, 0x00000008 },
-    { 0x4000e000, 0000000000 },
-    { 0x02400000, 0x00000004 },
-    { 0x400ee000, 0x00000004 },
-    { 0x02400000, 0x00000004 },
-    { 0x4000e000, 0000000000 },
-    { 0x000c2000, 0x00000004 },
-    { 0x0240e51b, 0x00000004 },
-    { 0x0080e50a, 0x00000005 },
-    { 0x0080e50b, 0x00000005 },
-    { 0x00220000, 0x00000004 },
-    { 0x000700c7, 0x00000004 },
-    { 0x000000a4, 0x00000038 },
-    { 0x0080e5bd, 0x00000005 },
-    { 0x0000e5bb, 0x00000005 },
-    { 0x0080e5bc, 0x00000005 },
-    { 0x00210000, 0x00000004 },
-    { 0x02800000, 0x00000004 },
-    { 0x00c000ab, 0x00000018 },
-    { 0x4180e000, 0x00000040 },
-    { 0x000000ad, 0x00000024 },
-    { 0x01000000, 0x0000000c },
-    { 0x0100e51d, 0x0000000c },
-    { 0x000045bb, 0x00000004 },
-    { 0x000080a7, 0x00000008 },
-    { 0x0000f3ce, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x00cc2000, 0x00000004 },
-    { 0x08c053cf, 0x00000040 },
-    { 0x00008000, 0000000000 },
-    { 0x0000f3d2, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x00cc2000, 0x00000004 },
-    { 0x08c053d3, 0x00000040 },
-    { 0x00008000, 0000000000 },
-    { 0x0000f39d, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x00cc2000, 0x00000004 },
-    { 0x08c0539e, 0x00000040 },
-    { 0x00008000, 0000000000 },
-    { 0x03c00830, 0x00000004 },
-    { 0x4200e000, 0000000000 },
-    { 0x0000a000, 0x00000004 },
-    { 0x200045e0, 0x00000004 },
-    { 0x0000e5e1, 0000000000 },
-    { 0x00000001, 0000000000 },
-    { 0x000700c4, 0x00000004 },
-    { 0x0800e394, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0x0000e8c4, 0x00000004 },
-    { 0x0000e8c5, 0x00000004 },
-    { 0x0000e8c6, 0x00000004 },
-    { 0x0000e928, 0x00000004 },
-    { 0x0000e929, 0x00000004 },
-    { 0x0000e92a, 0x00000004 },
-    { 0x000000c8, 0x00000008 },
-    { 0x0000e928, 0x00000004 },
-    { 0x0000e929, 0x00000004 },
-    { 0x0000e92a, 0x00000004 },
-    { 0x000000cf, 0x00000008 },
-    { 0x02c02000, 0x00000004 },
-    { 0x00060000, 0x00000004 },
-    { 0x000000d7, 0x00000034 },
-    { 0x000000d4, 0x00000008 },
-    { 0x00008000, 0x00000004 },
-    { 0xc000e000, 0000000000 },
-    { 0x0000e1cc, 0x00000004 },
-    { 0x0500e1cd, 0x00000004 },
-    { 0x000ca000, 0x00000004 },
-    { 0x000000de, 0x00000034 },
-    { 0x000000da, 0x00000008 },
-    { 0x0000a000, 0000000000 },
-    { 0x0019e1cc, 0x00000004 },
-    { 0x001b0001, 0x00000004 },
-    { 0x0500a000, 0x00000004 },
-    { 0x080041cd, 0x00000004 },
-    { 0x000ca000, 0x00000004 },
-    { 0x000000fb, 0x00000034 },
-    { 0x0000004a, 0x00000008 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0x000c2000, 0x00000004 },
-    { 0x001d0018, 0x00000004 },
-    { 0x001a0001, 0x00000004 },
-    { 0x000000fb, 0x00000034 },
-    { 0x0000004a, 0x00000008 },
-    { 0x0500a04a, 0x00000008 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-};
-
-static const u32 RS600_cp_microcode[][2] = {
-    { 0x4200e000, 0000000000 },
-    { 0x4000e000, 0000000000 },
-    { 0x000000a0, 0x00000008 },
-    { 0x000000a4, 0x00000008 },
-    { 0x4a554b4a, 0000000000 },
-    { 0x4a4a4467, 0000000000 },
-    { 0x55526f75, 0000000000 },
-    { 0x4a7e7d65, 0000000000 },
-    { 0x4ae74af6, 0000000000 },
-    { 0x4ad34a4a, 0000000000 },
-    { 0xd6898989, 0000000000 },
-    { 0xcd4addcf, 0000000000 },
-    { 0x8ebe4ae2, 0000000000 },
-    { 0xc38a8a8a, 0000000000 },
-    { 0x4a0f8cc8, 0000000000 },
-    { 0x000ca000, 0x00000004 },
-    { 0x000d0012, 0x00000038 },
-    { 0x0000e8b4, 0x00000004 },
-    { 0x000d0014, 0x00000038 },
-    { 0x0000e8b6, 0x00000004 },
-    { 0x000d0016, 0x00000038 },
-    { 0x0000e854, 0x00000004 },
-    { 0x000d0018, 0x00000038 },
-    { 0x0000e855, 0x00000004 },
-    { 0x000d001a, 0x00000038 },
-    { 0x0000e856, 0x00000004 },
-    { 0x000d001c, 0x00000038 },
-    { 0x0000e857, 0x00000004 },
-    { 0x000d001e, 0x00000038 },
-    { 0x0000e824, 0x00000004 },
-    { 0x000d0020, 0x00000038 },
-    { 0x0000e825, 0x00000004 },
-    { 0x000d0022, 0x00000038 },
-    { 0x0000e830, 0x00000004 },
-    { 0x000d0024, 0x00000038 },
-    { 0x0000f0c0, 0x00000004 },
-    { 0x000d0026, 0x00000038 },
-    { 0x0000f0c1, 0x00000004 },
-    { 0x000d0028, 0x00000038 },
-    { 0x0000f041, 0x00000004 },
-    { 0x000d002a, 0x00000038 },
-    { 0x0000f184, 0x00000004 },
-    { 0x000d002c, 0x00000038 },
-    { 0x0000f185, 0x00000004 },
-    { 0x000d002e, 0x00000038 },
-    { 0x0000f186, 0x00000004 },
-    { 0x000d0030, 0x00000038 },
-    { 0x0000f187, 0x00000004 },
-    { 0x000d0032, 0x00000038 },
-    { 0x0000f180, 0x00000004 },
-    { 0x000d0034, 0x00000038 },
-    { 0x0000f393, 0x00000004 },
-    { 0x000d0036, 0x00000038 },
-    { 0x0000f38a, 0x00000004 },
-    { 0x000d0038, 0x00000038 },
-    { 0x0000f38e, 0x00000004 },
-    { 0x0000e821, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x00000043, 0x00000018 },
-    { 0x00cce800, 0x00000004 },
-    { 0x001b0001, 0x00000004 },
-    { 0x08004800, 0x00000004 },
-    { 0x001b0001, 0x00000004 },
-    { 0x08004800, 0x00000004 },
-    { 0x001b0001, 0x00000004 },
-    { 0x08004800, 0x00000004 },
-    { 0x0000003a, 0x00000008 },
-    { 0x0000a000, 0000000000 },
-    { 0x2000451d, 0x00000004 },
-    { 0x0000e580, 0x00000004 },
-    { 0x000ce581, 0x00000004 },
-    { 0x08004580, 0x00000004 },
-    { 0x000ce581, 0x00000004 },
-    { 0x00000047, 0x00000008 },
-    { 0x0000a000, 0000000000 },
-    { 0x000c2000, 0x00000004 },
-    { 0x0000e50e, 0x00000004 },
-    { 0x00032000, 0x00000004 },
-    { 0x00022051, 0x00000028 },
-    { 0x00000051, 0x00000024 },
-    { 0x0800450f, 0x00000004 },
-    { 0x0000a04b, 0x00000008 },
-    { 0x0000e565, 0x00000004 },
-    { 0x0000e566, 0x00000004 },
-    { 0x00000052, 0x00000008 },
-    { 0x03cca5b4, 0x00000004 },
-    { 0x05432000, 0x00000004 },
-    { 0x00022000, 0x00000004 },
-    { 0x4ccce05e, 0x00000030 },
-    { 0x08274565, 0x00000004 },
-    { 0x0000005e, 0x00000030 },
-    { 0x08004564, 0x00000004 },
-    { 0x0000e566, 0x00000004 },
-    { 0x00000055, 0x00000008 },
-    { 0x00802061, 0x00000010 },
-    { 0x00202000, 0x00000004 },
-    { 0x001b00ff, 0x00000004 },
-    { 0x01000064, 0x00000010 },
-    { 0x001f2000, 0x00000004 },
-    { 0x001c00ff, 0x00000004 },
-    { 0000000000, 0x0000000c },
-    { 0x00000072, 0x00000030 },
-    { 0x00000055, 0x00000008 },
-    { 0x0000e576, 0x00000004 },
-    { 0x0000e577, 0x00000004 },
-    { 0x0000e50e, 0x00000004 },
-    { 0x0000e50f, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x00000069, 0x00000018 },
-    { 0x00c0e5f9, 0x000000c2 },
-    { 0x00000069, 0x00000008 },
-    { 0x0014e50e, 0x00000004 },
-    { 0x0040e50f, 0x00000004 },
-    { 0x00c0006c, 0x00000008 },
-    { 0x0000e570, 0x00000004 },
-    { 0x0000e571, 0x00000004 },
-    { 0x0000e572, 0x0000000c },
-    { 0x0000a000, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x0000e568, 0x00000004 },
-    { 0x000c2000, 0x00000004 },
-    { 0x00000076, 0x00000018 },
-    { 0x000b0000, 0x00000004 },
-    { 0x18c0e562, 0x00000004 },
-    { 0x00000078, 0x00000008 },
-    { 0x00c00077, 0x00000008 },
-    { 0x000700d5, 0x00000004 },
-    { 0x00000084, 0x00000038 },
-    { 0x000ca086, 0x00000030 },
-    { 0x080045bb, 0x00000004 },
-    { 0x000c2087, 0x00000030 },
-    { 0x0800e5bc, 0000000000 },
-    { 0x0000e5bb, 0x00000004 },
-    { 0x0000e5bc, 0000000000 },
-    { 0x00120000, 0x0000000c },
-    { 0x00120000, 0x00000004 },
-    { 0x001b0002, 0x0000000c },
-    { 0x0000a000, 0x00000004 },
-    { 0x0000e821, 0x00000004 },
-    { 0x0000e800, 0000000000 },
-    { 0x0000e821, 0x00000004 },
-    { 0x0000e82e, 0000000000 },
-    { 0x02cca000, 0x00000004 },
-    { 0x00140000, 0x00000004 },
-    { 0x000ce1cc, 0x00000004 },
-    { 0x050de1cd, 0x00000004 },
-    { 0x00400000, 0x00000004 },
-    { 0x00000096, 0x00000018 },
-    { 0x00c0a000, 0x00000004 },
-    { 0x00000093, 0x00000008 },
-    { 0x00000098, 0x00000020 },
-    { 0x4200e000, 0000000000 },
-    { 0x0000009f, 0x00000038 },
-    { 0x000ca000, 0x00000004 },
-    { 0x00140000, 0x00000004 },
-    { 0x000c2000, 0x00000004 },
-    { 0x00160000, 0x00000004 },
-    { 0x700ce000, 0x00000004 },
-    { 0x0014009b, 0x00000008 },
-    { 0x4000e000, 0000000000 },
-    { 0x02400000, 0x00000004 },
-    { 0x400ee000, 0x00000004 },
-    { 0x02400000, 0x00000004 },
-    { 0x4000e000, 0000000000 },
-    { 0x000c2000, 0x00000004 },
-    { 0x0240e51b, 0x00000004 },
-    { 0x0080e50a, 0x00000005 },
-    { 0x0080e50b, 0x00000005 },
-    { 0x00220000, 0x00000004 },
-    { 0x000700d5, 0x00000004 },
-    { 0x000000b2, 0x00000038 },
-    { 0x000c2087, 0x00000030 },
-    { 0x0880e5bd, 0x00000005 },
-    { 0x000c2086, 0x00000030 },
-    { 0x0800e5bb, 0x00000005 },
-    { 0x000c2087, 0x00000030 },
-    { 0x0880e5bc, 0x00000005 },
-    { 0x000000b5, 0x00000008 },
-    { 0x0080e5bd, 0x00000005 },
-    { 0x0000e5bb, 0x00000005 },
-    { 0x0080e5bc, 0x00000005 },
-    { 0x00210000, 0x00000004 },
-    { 0x02800000, 0x00000004 },
-    { 0x00c000b9, 0x00000018 },
-    { 0x4180e000, 0x00000040 },
-    { 0x000000bb, 0x00000024 },
-    { 0x01000000, 0x0000000c },
-    { 0x0100e51d, 0x0000000c },
-    { 0x000045bb, 0x00000004 },
-    { 0x000080b5, 0x00000008 },
-    { 0x0000f3ce, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x00cc2000, 0x00000004 },
-    { 0x08c053cf, 0x00000040 },
-    { 0x00008000, 0000000000 },
-    { 0x0000f3d2, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x00cc2000, 0x00000004 },
-    { 0x08c053d3, 0x00000040 },
-    { 0x00008000, 0000000000 },
-    { 0x0000f39d, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x00cc2000, 0x00000004 },
-    { 0x08c0539e, 0x00000040 },
-    { 0x00008000, 0000000000 },
-    { 0x03c00830, 0x00000004 },
-    { 0x4200e000, 0000000000 },
-    { 0x0000a000, 0x00000004 },
-    { 0x200045e0, 0x00000004 },
-    { 0x0000e5e1, 0000000000 },
-    { 0x00000001, 0000000000 },
-    { 0x000700d2, 0x00000004 },
-    { 0x0800e394, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0x0000e8c4, 0x00000004 },
-    { 0x0000e8c5, 0x00000004 },
-    { 0x0000e8c6, 0x00000004 },
-    { 0x0000e928, 0x00000004 },
-    { 0x0000e929, 0x00000004 },
-    { 0x0000e92a, 0x00000004 },
-    { 0x000000d6, 0x00000008 },
-    { 0x0000e928, 0x00000004 },
-    { 0x0000e929, 0x00000004 },
-    { 0x0000e92a, 0x00000004 },
-    { 0x000000dd, 0x00000008 },
-    { 0x00e00116, 0000000000 },
-    { 0x000700e1, 0x00000004 },
-    { 0x0800401c, 0x00000004 },
-    { 0x200050e7, 0x00000004 },
-    { 0x0000e01d, 0x00000004 },
-    { 0x000000e4, 0x00000008 },
-    { 0x02c02000, 0x00000004 },
-    { 0x00060000, 0x00000004 },
-    { 0x000000eb, 0x00000034 },
-    { 0x000000e8, 0x00000008 },
-    { 0x00008000, 0x00000004 },
-    { 0xc000e000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0x000c2000, 0x00000004 },
-    { 0x001d0018, 0x00000004 },
-    { 0x001a0001, 0x00000004 },
-    { 0x000000fb, 0x00000034 },
-    { 0x0000004a, 0x00000008 },
-    { 0x0500a04a, 0x00000008 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-};
-
-static const u32 RS690_cp_microcode[][2] = {
-    { 0x000000dd, 0x00000008 },
-    { 0x000000df, 0x00000008 },
-    { 0x000000a0, 0x00000008 },
-    { 0x000000a4, 0x00000008 },
-    { 0x4a554b4a, 0000000000 },
-    { 0x4a4a4467, 0000000000 },
-    { 0x55526f75, 0000000000 },
-    { 0x4a7e7d65, 0000000000 },
-    { 0x4ad74af6, 0000000000 },
-    { 0x4ac94a4a, 0000000000 },
-    { 0xcc898989, 0000000000 },
-    { 0xc34ad3c5, 0000000000 },
-    { 0x8e4a4a4a, 0000000000 },
-    { 0x4a8a8a8a, 0000000000 },
-    { 0x4a0f8c4a, 0000000000 },
-    { 0x000ca000, 0x00000004 },
-    { 0x000d0012, 0x00000038 },
-    { 0x0000e8b4, 0x00000004 },
-    { 0x000d0014, 0x00000038 },
-    { 0x0000e8b6, 0x00000004 },
-    { 0x000d0016, 0x00000038 },
-    { 0x0000e854, 0x00000004 },
-    { 0x000d0018, 0x00000038 },
-    { 0x0000e855, 0x00000004 },
-    { 0x000d001a, 0x00000038 },
-    { 0x0000e856, 0x00000004 },
-    { 0x000d001c, 0x00000038 },
-    { 0x0000e857, 0x00000004 },
-    { 0x000d001e, 0x00000038 },
-    { 0x0000e824, 0x00000004 },
-    { 0x000d0020, 0x00000038 },
-    { 0x0000e825, 0x00000004 },
-    { 0x000d0022, 0x00000038 },
-    { 0x0000e830, 0x00000004 },
-    { 0x000d0024, 0x00000038 },
-    { 0x0000f0c0, 0x00000004 },
-    { 0x000d0026, 0x00000038 },
-    { 0x0000f0c1, 0x00000004 },
-    { 0x000d0028, 0x00000038 },
-    { 0x0000f041, 0x00000004 },
-    { 0x000d002a, 0x00000038 },
-    { 0x0000f184, 0x00000004 },
-    { 0x000d002c, 0x00000038 },
-    { 0x0000f185, 0x00000004 },
-    { 0x000d002e, 0x00000038 },
-    { 0x0000f186, 0x00000004 },
-    { 0x000d0030, 0x00000038 },
-    { 0x0000f187, 0x00000004 },
-    { 0x000d0032, 0x00000038 },
-    { 0x0000f180, 0x00000004 },
-    { 0x000d0034, 0x00000038 },
-    { 0x0000f393, 0x00000004 },
-    { 0x000d0036, 0x00000038 },
-    { 0x0000f38a, 0x00000004 },
-    { 0x000d0038, 0x00000038 },
-    { 0x0000f38e, 0x00000004 },
-    { 0x0000e821, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x00000043, 0x00000018 },
-    { 0x00cce800, 0x00000004 },
-    { 0x001b0001, 0x00000004 },
-    { 0x08004800, 0x00000004 },
-    { 0x001b0001, 0x00000004 },
-    { 0x08004800, 0x00000004 },
-    { 0x001b0001, 0x00000004 },
-    { 0x08004800, 0x00000004 },
-    { 0x0000003a, 0x00000008 },
-    { 0x0000a000, 0000000000 },
-    { 0x2000451d, 0x00000004 },
-    { 0x0000e580, 0x00000004 },
-    { 0x000ce581, 0x00000004 },
-    { 0x08004580, 0x00000004 },
-    { 0x000ce581, 0x00000004 },
-    { 0x00000047, 0x00000008 },
-    { 0x0000a000, 0000000000 },
-    { 0x000c2000, 0x00000004 },
-    { 0x0000e50e, 0x00000004 },
-    { 0x00032000, 0x00000004 },
-    { 0x00022051, 0x00000028 },
-    { 0x00000051, 0x00000024 },
-    { 0x0800450f, 0x00000004 },
-    { 0x0000a04b, 0x00000008 },
-    { 0x0000e565, 0x00000004 },
-    { 0x0000e566, 0x00000004 },
-    { 0x00000052, 0x00000008 },
-    { 0x03cca5b4, 0x00000004 },
-    { 0x05432000, 0x00000004 },
-    { 0x00022000, 0x00000004 },
-    { 0x4ccce05e, 0x00000030 },
-    { 0x08274565, 0x00000004 },
-    { 0x0000005e, 0x00000030 },
-    { 0x08004564, 0x00000004 },
-    { 0x0000e566, 0x00000004 },
-    { 0x00000055, 0x00000008 },
-    { 0x00802061, 0x00000010 },
-    { 0x00202000, 0x00000004 },
-    { 0x001b00ff, 0x00000004 },
-    { 0x01000064, 0x00000010 },
-    { 0x001f2000, 0x00000004 },
-    { 0x001c00ff, 0x00000004 },
-    { 0000000000, 0x0000000c },
-    { 0x00000072, 0x00000030 },
-    { 0x00000055, 0x00000008 },
-    { 0x0000e576, 0x00000004 },
-    { 0x0000e577, 0x00000004 },
-    { 0x0000e50e, 0x00000004 },
-    { 0x0000e50f, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x00000069, 0x00000018 },
-    { 0x00c0e5f9, 0x000000c2 },
-    { 0x00000069, 0x00000008 },
-    { 0x0014e50e, 0x00000004 },
-    { 0x0040e50f, 0x00000004 },
-    { 0x00c0006c, 0x00000008 },
-    { 0x0000e570, 0x00000004 },
-    { 0x0000e571, 0x00000004 },
-    { 0x0000e572, 0x0000000c },
-    { 0x0000a000, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x0000e568, 0x00000004 },
-    { 0x000c2000, 0x00000004 },
-    { 0x00000076, 0x00000018 },
-    { 0x000b0000, 0x00000004 },
-    { 0x18c0e562, 0x00000004 },
-    { 0x00000078, 0x00000008 },
-    { 0x00c00077, 0x00000008 },
-    { 0x000700cb, 0x00000004 },
-    { 0x00000084, 0x00000038 },
-    { 0x000ca086, 0x00000030 },
-    { 0x080045bb, 0x00000004 },
-    { 0x000c2087, 0x00000030 },
-    { 0x0800e5bc, 0000000000 },
-    { 0x0000e5bb, 0x00000004 },
-    { 0x0000e5bc, 0000000000 },
-    { 0x00120000, 0x0000000c },
-    { 0x00120000, 0x00000004 },
-    { 0x001b0002, 0x0000000c },
-    { 0x0000a000, 0x00000004 },
-    { 0x0000e821, 0x00000004 },
-    { 0x0000e800, 0000000000 },
-    { 0x0000e821, 0x00000004 },
-    { 0x0000e82e, 0000000000 },
-    { 0x02cca000, 0x00000004 },
-    { 0x00140000, 0x00000004 },
-    { 0x000ce1cc, 0x00000004 },
-    { 0x050de1cd, 0x00000004 },
-    { 0x00400000, 0x00000004 },
-    { 0x00000096, 0x00000018 },
-    { 0x00c0a000, 0x00000004 },
-    { 0x00000093, 0x00000008 },
-    { 0x00000098, 0x00000020 },
-    { 0x4200e000, 0000000000 },
-    { 0x0000009f, 0x00000038 },
-    { 0x000ca000, 0x00000004 },
-    { 0x00140000, 0x00000004 },
-    { 0x000c2000, 0x00000004 },
-    { 0x00160000, 0x00000004 },
-    { 0x700ce000, 0x00000004 },
-    { 0x0014009b, 0x00000008 },
-    { 0x4000e000, 0000000000 },
-    { 0x02400000, 0x00000004 },
-    { 0x400ee000, 0x00000004 },
-    { 0x02400000, 0x00000004 },
-    { 0x4000e000, 0000000000 },
-    { 0x00100000, 0x0000002c },
-    { 0x00004000, 0000000000 },
-    { 0x080045c8, 0x00000004 },
-    { 0x00240005, 0x00000004 },
-    { 0x08004d0b, 0x00000004 },
-    { 0x000c2000, 0x00000004 },
-    { 0x0240e51b, 0x00000004 },
-    { 0x0080e50a, 0x00000005 },
-    { 0x0080e50b, 0x00000005 },
-    { 0x00220000, 0x00000004 },
-    { 0x000700cb, 0x00000004 },
-    { 0x000000b7, 0x00000038 },
-    { 0x000c2087, 0x00000030 },
-    { 0x0880e5bd, 0x00000005 },
-    { 0x000c2086, 0x00000030 },
-    { 0x0800e5bb, 0x00000005 },
-    { 0x000c2087, 0x00000030 },
-    { 0x0880e5bc, 0x00000005 },
-    { 0x000000ba, 0x00000008 },
-    { 0x0080e5bd, 0x00000005 },
-    { 0x0000e5bb, 0x00000005 },
-    { 0x0080e5bc, 0x00000005 },
-    { 0x00210000, 0x00000004 },
-    { 0x02800000, 0x00000004 },
-    { 0x00c000be, 0x00000018 },
-    { 0x4180e000, 0x00000040 },
-    { 0x000000c0, 0x00000024 },
-    { 0x01000000, 0x0000000c },
-    { 0x0100e51d, 0x0000000c },
-    { 0x000045bb, 0x00000004 },
-    { 0x000080ba, 0x00000008 },
-    { 0x03c00830, 0x00000004 },
-    { 0x4200e000, 0000000000 },
-    { 0x0000a000, 0x00000004 },
-    { 0x200045e0, 0x00000004 },
-    { 0x0000e5e1, 0000000000 },
-    { 0x00000001, 0000000000 },
-    { 0x000700c8, 0x00000004 },
-    { 0x0800e394, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0x0000e8c4, 0x00000004 },
-    { 0x0000e8c5, 0x00000004 },
-    { 0x0000e8c6, 0x00000004 },
-    { 0x0000e928, 0x00000004 },
-    { 0x0000e929, 0x00000004 },
-    { 0x0000e92a, 0x00000004 },
-    { 0x000000cc, 0x00000008 },
-    { 0x0000e928, 0x00000004 },
-    { 0x0000e929, 0x00000004 },
-    { 0x0000e92a, 0x00000004 },
-    { 0x000000d3, 0x00000008 },
-    { 0x02c02000, 0x00000004 },
-    { 0x00060000, 0x00000004 },
-    { 0x000000db, 0x00000034 },
-    { 0x000000d8, 0x00000008 },
-    { 0x00008000, 0x00000004 },
-    { 0xc000e000, 0000000000 },
-    { 0x000000e1, 0x00000030 },
-    { 0x4200e000, 0000000000 },
-    { 0x000000e1, 0x00000030 },
-    { 0x4000e000, 0000000000 },
-    { 0x0025001b, 0x00000004 },
-    { 0x00230000, 0x00000004 },
-    { 0x00250005, 0x00000004 },
-    { 0x000000e6, 0x00000034 },
-    { 0000000000, 0x0000000c },
-    { 0x00244000, 0x00000004 },
-    { 0x080045c8, 0x00000004 },
-    { 0x00240005, 0x00000004 },
-    { 0x08004d0b, 0x0000000c },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0x000c2000, 0x00000004 },
-    { 0x001d0018, 0x00000004 },
-    { 0x001a0001, 0x00000004 },
-    { 0x000000fb, 0x00000034 },
-    { 0x0000004a, 0x00000008 },
-    { 0x0500a04a, 0x00000008 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-};
-
-static const u32 R520_cp_microcode[][2] = {
-    { 0x4200e000, 0000000000 },
-    { 0x4000e000, 0000000000 },
-    { 0x00000099, 0x00000008 },
-    { 0x0000009d, 0x00000008 },
-    { 0x4a554b4a, 0000000000 },
-    { 0x4a4a4467, 0000000000 },
-    { 0x55526f75, 0000000000 },
-    { 0x4a7e7d65, 0000000000 },
-    { 0xe0dae6f6, 0000000000 },
-    { 0x4ac54a4a, 0000000000 },
-    { 0xc8828282, 0000000000 },
-    { 0xbf4acfc1, 0000000000 },
-    { 0x87b04ad5, 0000000000 },
-    { 0xb5838383, 0000000000 },
-    { 0x4a0f85ba, 0000000000 },
-    { 0x000ca000, 0x00000004 },
-    { 0x000d0012, 0x00000038 },
-    { 0x0000e8b4, 0x00000004 },
-    { 0x000d0014, 0x00000038 },
-    { 0x0000e8b6, 0x00000004 },
-    { 0x000d0016, 0x00000038 },
-    { 0x0000e854, 0x00000004 },
-    { 0x000d0018, 0x00000038 },
-    { 0x0000e855, 0x00000004 },
-    { 0x000d001a, 0x00000038 },
-    { 0x0000e856, 0x00000004 },
-    { 0x000d001c, 0x00000038 },
-    { 0x0000e857, 0x00000004 },
-    { 0x000d001e, 0x00000038 },
-    { 0x0000e824, 0x00000004 },
-    { 0x000d0020, 0x00000038 },
-    { 0x0000e825, 0x00000004 },
-    { 0x000d0022, 0x00000038 },
-    { 0x0000e830, 0x00000004 },
-    { 0x000d0024, 0x00000038 },
-    { 0x0000f0c0, 0x00000004 },
-    { 0x000d0026, 0x00000038 },
-    { 0x0000f0c1, 0x00000004 },
-    { 0x000d0028, 0x00000038 },
-    { 0x0000e000, 0x00000004 },
-    { 0x000d002a, 0x00000038 },
-    { 0x0000e000, 0x00000004 },
-    { 0x000d002c, 0x00000038 },
-    { 0x0000e000, 0x00000004 },
-    { 0x000d002e, 0x00000038 },
-    { 0x0000e000, 0x00000004 },
-    { 0x000d0030, 0x00000038 },
-    { 0x0000e000, 0x00000004 },
-    { 0x000d0032, 0x00000038 },
-    { 0x0000f180, 0x00000004 },
-    { 0x000d0034, 0x00000038 },
-    { 0x0000f393, 0x00000004 },
-    { 0x000d0036, 0x00000038 },
-    { 0x0000f38a, 0x00000004 },
-    { 0x000d0038, 0x00000038 },
-    { 0x0000f38e, 0x00000004 },
-    { 0x0000e821, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x00000043, 0x00000018 },
-    { 0x00cce800, 0x00000004 },
-    { 0x001b0001, 0x00000004 },
-    { 0x08004800, 0x00000004 },
-    { 0x001b0001, 0x00000004 },
-    { 0x08004800, 0x00000004 },
-    { 0x001b0001, 0x00000004 },
-    { 0x08004800, 0x00000004 },
-    { 0x0000003a, 0x00000008 },
-    { 0x0000a000, 0000000000 },
-    { 0x2000451d, 0x00000004 },
-    { 0x0000e580, 0x00000004 },
-    { 0x000ce581, 0x00000004 },
-    { 0x08004580, 0x00000004 },
-    { 0x000ce581, 0x00000004 },
-    { 0x00000047, 0x00000008 },
-    { 0x0000a000, 0000000000 },
-    { 0x000c2000, 0x00000004 },
-    { 0x0000e50e, 0x00000004 },
-    { 0x00032000, 0x00000004 },
-    { 0x00022051, 0x00000028 },
-    { 0x00000051, 0x00000024 },
-    { 0x0800450f, 0x00000004 },
-    { 0x0000a04b, 0x00000008 },
-    { 0x0000e565, 0x00000004 },
-    { 0x0000e566, 0x00000004 },
-    { 0x00000052, 0x00000008 },
-    { 0x03cca5b4, 0x00000004 },
-    { 0x05432000, 0x00000004 },
-    { 0x00022000, 0x00000004 },
-    { 0x4ccce05e, 0x00000030 },
-    { 0x08274565, 0x00000004 },
-    { 0x0000005e, 0x00000030 },
-    { 0x08004564, 0x00000004 },
-    { 0x0000e566, 0x00000004 },
-    { 0x00000055, 0x00000008 },
-    { 0x00802061, 0x00000010 },
-    { 0x00202000, 0x00000004 },
-    { 0x001b00ff, 0x00000004 },
-    { 0x01000064, 0x00000010 },
-    { 0x001f2000, 0x00000004 },
-    { 0x001c00ff, 0x00000004 },
-    { 0000000000, 0x0000000c },
-    { 0x00000072, 0x00000030 },
-    { 0x00000055, 0x00000008 },
-    { 0x0000e576, 0x00000004 },
-    { 0x0000e577, 0x00000004 },
-    { 0x0000e50e, 0x00000004 },
-    { 0x0000e50f, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x00000069, 0x00000018 },
-    { 0x00c0e5f9, 0x000000c2 },
-    { 0x00000069, 0x00000008 },
-    { 0x0014e50e, 0x00000004 },
-    { 0x0040e50f, 0x00000004 },
-    { 0x00c0006c, 0x00000008 },
-    { 0x0000e570, 0x00000004 },
-    { 0x0000e571, 0x00000004 },
-    { 0x0000e572, 0x0000000c },
-    { 0x0000a000, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x0000e568, 0x00000004 },
-    { 0x000c2000, 0x00000004 },
-    { 0x00000076, 0x00000018 },
-    { 0x000b0000, 0x00000004 },
-    { 0x18c0e562, 0x00000004 },
-    { 0x00000078, 0x00000008 },
-    { 0x00c00077, 0x00000008 },
-    { 0x000700c7, 0x00000004 },
-    { 0x00000080, 0x00000038 },
-    { 0x0000e5bb, 0x00000004 },
-    { 0x0000e5bc, 0000000000 },
-    { 0x0000a000, 0x00000004 },
-    { 0x0000e821, 0x00000004 },
-    { 0x0000e800, 0000000000 },
-    { 0x0000e821, 0x00000004 },
-    { 0x0000e82e, 0000000000 },
-    { 0x02cca000, 0x00000004 },
-    { 0x00140000, 0x00000004 },
-    { 0x000ce1cc, 0x00000004 },
-    { 0x050de1cd, 0x00000004 },
-    { 0x00400000, 0x00000004 },
-    { 0x0000008f, 0x00000018 },
-    { 0x00c0a000, 0x00000004 },
-    { 0x0000008c, 0x00000008 },
-    { 0x00000091, 0x00000020 },
-    { 0x4200e000, 0000000000 },
-    { 0x00000098, 0x00000038 },
-    { 0x000ca000, 0x00000004 },
-    { 0x00140000, 0x00000004 },
-    { 0x000c2000, 0x00000004 },
-    { 0x00160000, 0x00000004 },
-    { 0x700ce000, 0x00000004 },
-    { 0x00140094, 0x00000008 },
-    { 0x4000e000, 0000000000 },
-    { 0x02400000, 0x00000004 },
-    { 0x400ee000, 0x00000004 },
-    { 0x02400000, 0x00000004 },
-    { 0x4000e000, 0000000000 },
-    { 0x000c2000, 0x00000004 },
-    { 0x0240e51b, 0x00000004 },
-    { 0x0080e50a, 0x00000005 },
-    { 0x0080e50b, 0x00000005 },
-    { 0x00220000, 0x00000004 },
-    { 0x000700c7, 0x00000004 },
-    { 0x000000a4, 0x00000038 },
-    { 0x0080e5bd, 0x00000005 },
-    { 0x0000e5bb, 0x00000005 },
-    { 0x0080e5bc, 0x00000005 },
-    { 0x00210000, 0x00000004 },
-    { 0x02800000, 0x00000004 },
-    { 0x00c000ab, 0x00000018 },
-    { 0x4180e000, 0x00000040 },
-    { 0x000000ad, 0x00000024 },
-    { 0x01000000, 0x0000000c },
-    { 0x0100e51d, 0x0000000c },
-    { 0x000045bb, 0x00000004 },
-    { 0x000080a7, 0x00000008 },
-    { 0x0000f3ce, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x00cc2000, 0x00000004 },
-    { 0x08c053cf, 0x00000040 },
-    { 0x00008000, 0000000000 },
-    { 0x0000f3d2, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x00cc2000, 0x00000004 },
-    { 0x08c053d3, 0x00000040 },
-    { 0x00008000, 0000000000 },
-    { 0x0000f39d, 0x00000004 },
-    { 0x0140a000, 0x00000004 },
-    { 0x00cc2000, 0x00000004 },
-    { 0x08c0539e, 0x00000040 },
-    { 0x00008000, 0000000000 },
-    { 0x03c00830, 0x00000004 },
-    { 0x4200e000, 0000000000 },
-    { 0x0000a000, 0x00000004 },
-    { 0x200045e0, 0x00000004 },
-    { 0x0000e5e1, 0000000000 },
-    { 0x00000001, 0000000000 },
-    { 0x000700c4, 0x00000004 },
-    { 0x0800e394, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0x0000e8c4, 0x00000004 },
-    { 0x0000e8c5, 0x00000004 },
-    { 0x0000e8c6, 0x00000004 },
-    { 0x0000e928, 0x00000004 },
-    { 0x0000e929, 0x00000004 },
-    { 0x0000e92a, 0x00000004 },
-    { 0x000000c8, 0x00000008 },
-    { 0x0000e928, 0x00000004 },
-    { 0x0000e929, 0x00000004 },
-    { 0x0000e92a, 0x00000004 },
-    { 0x000000cf, 0x00000008 },
-    { 0xdeadbeef, 0000000000 },
-    { 0x00000116, 0000000000 },
-    { 0x000700d3, 0x00000004 },
-    { 0x080050e7, 0x00000004 },
-    { 0x000700d4, 0x00000004 },
-    { 0x0800401c, 0x00000004 },
-    { 0x0000e01d, 0000000000 },
-    { 0x02c02000, 0x00000004 },
-    { 0x00060000, 0x00000004 },
-    { 0x000000de, 0x00000034 },
-    { 0x000000db, 0x00000008 },
-    { 0x00008000, 0x00000004 },
-    { 0xc000e000, 0000000000 },
-    { 0x0000e1cc, 0x00000004 },
-    { 0x0500e1cd, 0x00000004 },
-    { 0x000ca000, 0x00000004 },
-    { 0x000000e5, 0x00000034 },
-    { 0x000000e1, 0x00000008 },
-    { 0x0000a000, 0000000000 },
-    { 0x0019e1cc, 0x00000004 },
-    { 0x001b0001, 0x00000004 },
-    { 0x0500a000, 0x00000004 },
-    { 0x080041cd, 0x00000004 },
-    { 0x000ca000, 0x00000004 },
-    { 0x000000fb, 0x00000034 },
-    { 0x0000004a, 0x00000008 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0x000c2000, 0x00000004 },
-    { 0x001d0018, 0x00000004 },
-    { 0x001a0001, 0x00000004 },
-    { 0x000000fb, 0x00000034 },
-    { 0x0000004a, 0x00000008 },
-    { 0x0500a04a, 0x00000008 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-    { 0000000000, 0000000000 },
-};
-
-
-#endif
diff --git a/firmware/Makefile b/firmware/Makefile
index 6ea4e3d9f05..d166a7f767e 100644
--- a/firmware/Makefile
+++ b/firmware/Makefile
@@ -44,6 +44,20 @@ fw-shipped-$(CONFIG_CHELSIO_T3) += cxgb3/t3b_psram-1.1.0.bin \
 				   cxgb3/t3fw-7.4.0.bin
 fw-shipped-$(CONFIG_DRM_MGA) += matrox/g200_warp.fw matrox/g400_warp.fw
 fw-shipped-$(CONFIG_DRM_R128) += r128/r128_cce.bin
+fw-shipped-$(CONFIG_DRM_RADEON) += radeon/R100_cp.bin radeon/R200_cp.bin \
+				   radeon/R300_cp.bin radeon/R420_cp.bin \
+				   radeon/RS690_cp.bin radeon/RS600_cp.bin \
+				   radeon/R520_cp.bin \
+				   radeon/R600_pfp.bin radeon/R600_me.bin \
+				   radeon/RV610_pfp.bin radeon/RV610_me.bin \
+				   radeon/RV630_pfp.bin radeon/RV630_me.bin \
+				   radeon/RV620_pfp.bin radeon/RV620_me.bin \
+				   radeon/RV635_pfp.bin radeon/RV635_me.bin \
+				   radeon/RV670_pfp.bin radeon/RV670_me.bin \
+				   radeon/RS780_pfp.bin radeon/RS780_me.bin \
+				   radeon/RV770_pfp.bin radeon/RV770_me.bin \
+				   radeon/RV730_pfp.bin radeon/RV730_me.bin \
+				   radeon/RV710_pfp.bin radeon/RV710_me.bin
 fw-shipped-$(CONFIG_DVB_AV7110) += av7110/bootcode.bin
 fw-shipped-$(CONFIG_DVB_TTUSB_BUDGET) += ttusb-budget/dspbootcode.bin
 fw-shipped-$(CONFIG_E100) += e100/d101m_ucode.bin e100/d101s_ucode.bin \
diff --git a/firmware/WHENCE b/firmware/WHENCE
index 578d859c41f..00378ee2b75 100644
--- a/firmware/WHENCE
+++ b/firmware/WHENCE
@@ -761,3 +761,61 @@ Copyright 2000 Advanced Micro Devices, Inc.
 Found in decimal form in kernel source.
 
 --------------------------------------------------------------------------
+
+Driver: radeon - ATI Radeon
+
+File: radeon/R100_cp.bin
+File: radeon/R200_cp.bin
+File: radeon/R300_cp.bin
+File: radeon/R420_cp.bin
+File: radeon/RS600_cp.bin
+File: radeon/RS690_cp.bin
+File: radeon/R520_cp.bin
+File: radeon/R600_pfp.bin
+File: radeon/R600_me.bin
+File: radeon/RV610_pfp.bin
+File: radeon/RV610_me.bin
+File: radeon/RV630_pfp.bin
+File: radeon/RV630_me.bin
+File: radeon/RV620_pfp.bin
+File: radeon/RV620_me.bin
+File: radeon/RV635_pfp.bin
+File: radeon/RV635_me.bin
+File: radeon/RV670_pfp.bin
+File: radeon/RV670_me.bin
+File: radeon/RS780_pfp.bin
+File: radeon/RS780_me.bin
+File: radeon/RV770_pfp.bin
+File: radeon/RV770_me.bin
+File: radeon/RV730_pfp.bin
+File: radeon/RV730_me.bin
+File: radeon/RV710_pfp.bin
+File: radeon/RV710_me.bin
+
+Licence:
+
+ * Copyright 2007-2009 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+Found in hex form in kernel source.
+
+--------------------------------------------------------------------------
diff --git a/firmware/radeon/R100_cp.bin.ihex b/firmware/radeon/R100_cp.bin.ihex
new file mode 100644
index 00000000000..151647b04fc
--- /dev/null
+++ b/firmware/radeon/R100_cp.bin.ihex
@@ -0,0 +1,130 @@
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diff --git a/firmware/radeon/R200_cp.bin.ihex b/firmware/radeon/R200_cp.bin.ihex
new file mode 100644
index 00000000000..3a0bd73111c
--- /dev/null
+++ b/firmware/radeon/R200_cp.bin.ihex
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+/* production radeon ucode r1xx-r6xx */
diff --git a/firmware/radeon/R300_cp.bin.ihex b/firmware/radeon/R300_cp.bin.ihex
new file mode 100644
index 00000000000..d307d56882c
--- /dev/null
+++ b/firmware/radeon/R300_cp.bin.ihex
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diff --git a/firmware/radeon/R420_cp.bin.ihex b/firmware/radeon/R420_cp.bin.ihex
new file mode 100644
index 00000000000..3815891275f
--- /dev/null
+++ b/firmware/radeon/R420_cp.bin.ihex
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diff --git a/firmware/radeon/R600_pfp.bin.ihex b/firmware/radeon/R600_pfp.bin.ihex
new file mode 100644
index 00000000000..52361086c28
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diff --git a/firmware/radeon/RS600_cp.bin.ihex b/firmware/radeon/RS600_cp.bin.ihex
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diff --git a/firmware/radeon/RS780_me.bin.ihex b/firmware/radeon/RS780_me.bin.ihex
new file mode 100644
index 00000000000..6479c106b91
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diff --git a/firmware/radeon/RS780_pfp.bin.ihex b/firmware/radeon/RS780_pfp.bin.ihex
new file mode 100644
index 00000000000..40880411e78
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new file mode 100644
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new file mode 100644
index 00000000000..ba19ed89292
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new file mode 100644
index 00000000000..f55292c97b7
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diff --git a/firmware/radeon/RV630_me.bin.ihex b/firmware/radeon/RV630_me.bin.ihex
new file mode 100644
index 00000000000..ba3a7e632d9
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diff --git a/firmware/radeon/RV710_pfp.bin.ihex b/firmware/radeon/RV710_pfp.bin.ihex
new file mode 100644
index 00000000000..3d811ff0a1a
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diff --git a/firmware/radeon/RV770_me.bin.ihex b/firmware/radeon/RV770_me.bin.ihex
new file mode 100644
index 00000000000..a0e16990a20
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diff --git a/firmware/radeon/RV770_pfp.bin.ihex b/firmware/radeon/RV770_pfp.bin.ihex
new file mode 100644
index 00000000000..a2d1619107d
--- /dev/null
+++ b/firmware/radeon/RV770_pfp.bin.ihex
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-- 
cgit v1.2.3


From 7dc482dfeeeefcfd000d4271c4626937406756d7 Mon Sep 17 00:00:00 2001
From: Ben Hutchings <ben@decadent.org.uk>
Date: Sun, 23 Aug 2009 16:59:04 +0100
Subject: drm/r128: Add test for initialisation to all ioctls that require it

Almost all r128's private ioctls require that the CCE state has
already been initialised.  However, most do not test that this has
been done, and will proceed to dereference a null pointer.  This may
result in a security vulnerability, since some ioctls are
unprivileged.

This adds a macro for the common initialisation test and changes all
ioctl implementations that require prior initialisation to use that
macro.

Also, r128_do_init_cce() does not test that the CCE state has not
been initialised already.  Repeated initialisation may lead to a crash
or resource leak.  This adds that test.

Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/r128/r128_cce.c   | 18 ++++++++++++++----
 drivers/gpu/drm/r128/r128_drv.h   |  8 ++++++++
 drivers/gpu/drm/r128/r128_state.c | 36 +++++++++++++++++++-----------------
 3 files changed, 41 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/r128/r128_cce.c b/drivers/gpu/drm/r128/r128_cce.c
index 15252f60bbd..4c39a407aa4 100644
--- a/drivers/gpu/drm/r128/r128_cce.c
+++ b/drivers/gpu/drm/r128/r128_cce.c
@@ -346,6 +346,11 @@ static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init)
 
 	DRM_DEBUG("\n");
 
+	if (dev->dev_private) {
+		DRM_DEBUG("called when already initialized\n");
+		return -EINVAL;
+	}
+
 	dev_priv = kzalloc(sizeof(drm_r128_private_t), GFP_KERNEL);
 	if (dev_priv == NULL)
 		return -ENOMEM;
@@ -647,6 +652,8 @@ int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_pri
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
+
 	if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) {
 		DRM_DEBUG("while CCE running\n");
 		return 0;
@@ -669,6 +676,8 @@ int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
+
 	/* Flush any pending CCE commands.  This ensures any outstanding
 	 * commands are exectuted by the engine before we turn it off.
 	 */
@@ -706,10 +715,7 @@ int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_pri
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
-	if (!dev_priv) {
-		DRM_DEBUG("called before init done\n");
-		return -EINVAL;
-	}
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
 
 	r128_do_cce_reset(dev_priv);
 
@@ -726,6 +732,8 @@ int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
+
 	if (dev_priv->cce_running) {
 		r128_do_cce_flush(dev_priv);
 	}
@@ -739,6 +747,8 @@ int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
+	DEV_INIT_TEST_WITH_RETURN(dev->dev_private);
+
 	return r128_do_engine_reset(dev);
 }
 
diff --git a/drivers/gpu/drm/r128/r128_drv.h b/drivers/gpu/drm/r128/r128_drv.h
index 797a26c42da..3c60829d82e 100644
--- a/drivers/gpu/drm/r128/r128_drv.h
+++ b/drivers/gpu/drm/r128/r128_drv.h
@@ -422,6 +422,14 @@ static __inline__ void r128_update_ring_snapshot(drm_r128_private_t * dev_priv)
  * Misc helper macros
  */
 
+#define DEV_INIT_TEST_WITH_RETURN(_dev_priv)				\
+do {									\
+	if (!_dev_priv) {						\
+		DRM_ERROR("called with no initialization\n");		\
+		return -EINVAL;						\
+	}								\
+} while (0)
+
 #define RING_SPACE_TEST_WITH_RETURN( dev_priv )				\
 do {									\
 	drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i;		\
diff --git a/drivers/gpu/drm/r128/r128_state.c b/drivers/gpu/drm/r128/r128_state.c
index 026a48c95c8..af2665cf471 100644
--- a/drivers/gpu/drm/r128/r128_state.c
+++ b/drivers/gpu/drm/r128/r128_state.c
@@ -1244,14 +1244,18 @@ static void r128_cce_dispatch_stipple(struct drm_device * dev, u32 * stipple)
 static int r128_cce_clear(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
 	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
+	drm_r128_sarea_t *sarea_priv;
 	drm_r128_clear_t *clear = data;
 	DRM_DEBUG("\n");
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
+
 	RING_SPACE_TEST_WITH_RETURN(dev_priv);
 
+	sarea_priv = dev_priv->sarea_priv;
+
 	if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS)
 		sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
 
@@ -1312,6 +1316,8 @@ static int r128_cce_flip(struct drm_device *dev, void *data, struct drm_file *fi
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
+
 	RING_SPACE_TEST_WITH_RETURN(dev_priv);
 
 	if (!dev_priv->page_flipping)
@@ -1331,6 +1337,8 @@ static int r128_cce_swap(struct drm_device *dev, void *data, struct drm_file *fi
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
+
 	RING_SPACE_TEST_WITH_RETURN(dev_priv);
 
 	if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS)
@@ -1354,10 +1362,7 @@ static int r128_cce_vertex(struct drm_device *dev, void *data, struct drm_file *
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
-	if (!dev_priv) {
-		DRM_ERROR("called with no initialization\n");
-		return -EINVAL;
-	}
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
 
 	DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
 		  DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard);
@@ -1410,10 +1415,7 @@ static int r128_cce_indices(struct drm_device *dev, void *data, struct drm_file
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
-	if (!dev_priv) {
-		DRM_ERROR("called with no initialization\n");
-		return -EINVAL;
-	}
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
 
 	DRM_DEBUG("pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID,
 		  elts->idx, elts->start, elts->end, elts->discard);
@@ -1476,6 +1478,8 @@ static int r128_cce_blit(struct drm_device *dev, void *data, struct drm_file *fi
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
+
 	DRM_DEBUG("pid=%d index=%d\n", DRM_CURRENTPID, blit->idx);
 
 	if (blit->idx < 0 || blit->idx >= dma->buf_count) {
@@ -1501,6 +1505,8 @@ static int r128_cce_depth(struct drm_device *dev, void *data, struct drm_file *f
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
+
 	RING_SPACE_TEST_WITH_RETURN(dev_priv);
 
 	ret = -EINVAL;
@@ -1531,6 +1537,8 @@ static int r128_cce_stipple(struct drm_device *dev, void *data, struct drm_file
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
+
 	if (DRM_COPY_FROM_USER(&mask, stipple->mask, 32 * sizeof(u32)))
 		return -EFAULT;
 
@@ -1555,10 +1563,7 @@ static int r128_cce_indirect(struct drm_device *dev, void *data, struct drm_file
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
-	if (!dev_priv) {
-		DRM_ERROR("called with no initialization\n");
-		return -EINVAL;
-	}
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
 
 	DRM_DEBUG("idx=%d s=%d e=%d d=%d\n",
 		  indirect->idx, indirect->start, indirect->end,
@@ -1620,10 +1625,7 @@ static int r128_getparam(struct drm_device *dev, void *data, struct drm_file *fi
 	drm_r128_getparam_t *param = data;
 	int value;
 
-	if (!dev_priv) {
-		DRM_ERROR("called with no initialization\n");
-		return -EINVAL;
-	}
+	DEV_INIT_TEST_WITH_RETURN(dev_priv);
 
 	DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
 
-- 
cgit v1.2.3


From 785b93ef8c309730c2de84ce9c229e40e2d01480 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Fri, 28 Aug 2009 15:46:53 +1000
Subject: drm/kms: move driver specific fb common code to helper functions (v2)

Initially I always meant this code to be shared, but things
ran away from me before I got to it.

This refactors the i915 and radeon kms fbdev interaction layers
out into generic helpers + driver specific pieces.

It moves all the panic/sysrq enhancements to the core file,
and stores a linked list of kernel fbs. This could possibly be
improved to only store the fb which has fbcon on it for panics
etc.

radeon retains some specific codes used for a big endian
workaround.

changes:
fix oops in v1
fix freeing path for crtc_info

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/Makefile                |   3 +-
 drivers/gpu/drm/drm_fb_helper.c         | 697 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_dma.c         |   3 +-
 drivers/gpu/drm/i915/intel_display.c    |  12 -
 drivers/gpu/drm/i915/intel_drv.h        |   3 -
 drivers/gpu/drm/i915/intel_fb.c         | 737 ++------------------------------
 drivers/gpu/drm/radeon/radeon_display.c |   5 +-
 drivers/gpu/drm/radeon/radeon_fb.c      | 670 ++++-------------------------
 drivers/gpu/drm/radeon/radeon_mode.h    |   2 -
 include/drm/drm_crtc.h                  |   2 +
 include/drm/drm_fb_helper.h             |  82 ++++
 11 files changed, 907 insertions(+), 1309 deletions(-)
 create mode 100644 drivers/gpu/drm/drm_fb_helper.c
 create mode 100644 include/drm/drm_fb_helper.h

diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 5f0aec4f082..99071684de2 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -11,7 +11,8 @@ drm-y       :=	drm_auth.o drm_bufs.o drm_cache.o \
 		drm_agpsupport.o drm_scatter.o ati_pcigart.o drm_pci.o \
 		drm_sysfs.o drm_hashtab.o drm_sman.o drm_mm.o \
 		drm_crtc.o drm_crtc_helper.o drm_modes.o drm_edid.o \
-		drm_info.o drm_debugfs.o drm_encoder_slave.o
+		drm_info.o drm_debugfs.o drm_encoder_slave.o \
+		drm_fb_helper.o
 
 drm-$(CONFIG_COMPAT) += drm_ioc32.o
 
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
new file mode 100644
index 00000000000..d6ffea74a50
--- /dev/null
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -0,0 +1,697 @@
+/*
+ * Copyright (c) 2006-2009 Red Hat Inc.
+ * Copyright (c) 2006-2008 Intel Corporation
+ * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
+ *
+ * DRM framebuffer helper functions
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission.  The copyright holders make no representations
+ * about the suitability of this software for any purpose.  It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ *
+ * Authors:
+ *      Dave Airlie <airlied@linux.ie>
+ *      Jesse Barnes <jesse.barnes@intel.com>
+ */
+#include <linux/sysrq.h>
+#include <linux/fb.h>
+#include "drmP.h"
+#include "drm_crtc.h"
+#include "drm_fb_helper.h"
+#include "drm_crtc_helper.h"
+
+static LIST_HEAD(kernel_fb_helper_list);
+
+bool drm_fb_helper_force_kernel_mode(void)
+{
+	int i = 0;
+	bool ret, error = false;
+	struct drm_fb_helper *helper;
+
+	if (list_empty(&kernel_fb_helper_list))
+		return false;
+
+	list_for_each_entry(helper, &kernel_fb_helper_list, kernel_fb_list) {
+		for (i = 0; i < helper->crtc_count; i++) {
+			struct drm_mode_set *mode_set = &helper->crtc_info[i].mode_set;
+			ret = drm_crtc_helper_set_config(mode_set);
+			if (ret)
+				error = true;
+		}
+	}
+	return error;
+}
+
+int drm_fb_helper_panic(struct notifier_block *n, unsigned long ununsed,
+			void *panic_str)
+{
+	DRM_ERROR("panic occurred, switching back to text console\n");
+	return drm_fb_helper_force_kernel_mode();
+	return 0;
+}
+EXPORT_SYMBOL(drm_fb_helper_panic);
+
+static struct notifier_block paniced = {
+	.notifier_call = drm_fb_helper_panic,
+};
+
+/**
+ * drm_fb_helper_restore - restore the framebuffer console (kernel) config
+ *
+ * Restore's the kernel's fbcon mode, used for lastclose & panic paths.
+ */
+void drm_fb_helper_restore(void)
+{
+	bool ret;
+	ret = drm_fb_helper_force_kernel_mode();
+	if (ret == true)
+		DRM_ERROR("Failed to restore crtc configuration\n");
+}
+EXPORT_SYMBOL(drm_fb_helper_restore);
+
+static void drm_fb_helper_restore_work_fn(struct work_struct *ignored)
+{
+	drm_fb_helper_restore();
+}
+static DECLARE_WORK(drm_fb_helper_restore_work, drm_fb_helper_restore_work_fn);
+
+static void drm_fb_helper_sysrq(int dummy1, struct tty_struct *dummy3)
+{
+	schedule_work(&drm_fb_helper_restore_work);
+}
+
+static struct sysrq_key_op sysrq_drm_fb_helper_restore_op = {
+	.handler = drm_fb_helper_sysrq,
+	.help_msg = "force-fb(V)",
+	.action_msg = "Restore framebuffer console",
+};
+
+static void drm_fb_helper_on(struct fb_info *info)
+{
+	struct drm_fb_helper *fb_helper = info->par;
+	struct drm_device *dev = fb_helper->dev;
+	struct drm_crtc *crtc;
+	struct drm_encoder *encoder;
+	int i;
+
+	/*
+	 * For each CRTC in this fb, turn the crtc on then,
+	 * find all associated encoders and turn them on.
+	 */
+	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+		struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+
+		for (i = 0; i < fb_helper->crtc_count; i++) {
+			if (crtc->base.id == fb_helper->crtc_info[i].crtc_id)
+				break;
+		}
+
+		mutex_lock(&dev->mode_config.mutex);
+		crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
+		mutex_unlock(&dev->mode_config.mutex);
+
+		/* Found a CRTC on this fb, now find encoders */
+		list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+			if (encoder->crtc == crtc) {
+				struct drm_encoder_helper_funcs *encoder_funcs;
+
+				encoder_funcs = encoder->helper_private;
+				mutex_lock(&dev->mode_config.mutex);
+				encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
+				mutex_unlock(&dev->mode_config.mutex);
+			}
+		}
+	}
+}
+
+static void drm_fb_helper_off(struct fb_info *info, int dpms_mode)
+{
+	struct drm_fb_helper *fb_helper = info->par;
+	struct drm_device *dev = fb_helper->dev;
+	struct drm_crtc *crtc;
+	struct drm_encoder *encoder;
+	int i;
+
+	/*
+	 * For each CRTC in this fb, find all associated encoders
+	 * and turn them off, then turn off the CRTC.
+	 */
+	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+		struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+
+		for (i = 0; i < fb_helper->crtc_count; i++) {
+			if (crtc->base.id == fb_helper->crtc_info[i].crtc_id)
+				break;
+		}
+
+		/* Found a CRTC on this fb, now find encoders */
+		list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+			if (encoder->crtc == crtc) {
+				struct drm_encoder_helper_funcs *encoder_funcs;
+
+				encoder_funcs = encoder->helper_private;
+				mutex_lock(&dev->mode_config.mutex);
+				encoder_funcs->dpms(encoder, dpms_mode);
+				mutex_unlock(&dev->mode_config.mutex);
+			}
+		}
+		if (dpms_mode == DRM_MODE_DPMS_OFF) {
+			mutex_lock(&dev->mode_config.mutex);
+			crtc_funcs->dpms(crtc, dpms_mode);
+			mutex_unlock(&dev->mode_config.mutex);
+		}
+	}
+}
+
+int drm_fb_helper_blank(int blank, struct fb_info *info)
+{
+	switch (blank) {
+	case FB_BLANK_UNBLANK:
+		drm_fb_helper_on(info);
+		break;
+	case FB_BLANK_NORMAL:
+		drm_fb_helper_off(info, DRM_MODE_DPMS_STANDBY);
+		break;
+	case FB_BLANK_HSYNC_SUSPEND:
+		drm_fb_helper_off(info, DRM_MODE_DPMS_STANDBY);
+		break;
+	case FB_BLANK_VSYNC_SUSPEND:
+		drm_fb_helper_off(info, DRM_MODE_DPMS_SUSPEND);
+		break;
+	case FB_BLANK_POWERDOWN:
+		drm_fb_helper_off(info, DRM_MODE_DPMS_OFF);
+		break;
+	}
+	return 0;
+}
+EXPORT_SYMBOL(drm_fb_helper_blank);
+
+static void drm_fb_helper_crtc_free(struct drm_fb_helper *helper)
+{
+	int i;
+
+	for (i = 0; i < helper->crtc_count; i++)
+		kfree(helper->crtc_info[i].mode_set.connectors);
+	kfree(helper->crtc_info);
+}
+
+int drm_fb_helper_init_crtc_count(struct drm_fb_helper *helper, int crtc_count, int max_conn_count)
+{
+	struct drm_device *dev = helper->dev;
+	struct drm_crtc *crtc;
+	int ret = 0;
+	int i;
+
+	helper->crtc_info = kcalloc(crtc_count, sizeof(struct drm_fb_helper_crtc), GFP_KERNEL);
+	if (!helper->crtc_info)
+		return -ENOMEM;
+
+	helper->crtc_count = crtc_count;
+
+	for (i = 0; i < crtc_count; i++) {
+		helper->crtc_info[i].mode_set.connectors =
+			kcalloc(max_conn_count,
+				sizeof(struct drm_connector *),
+				GFP_KERNEL);
+
+		if (!helper->crtc_info[i].mode_set.connectors) {
+			ret = -ENOMEM;
+			goto out_free;
+		}
+		helper->crtc_info[i].mode_set.num_connectors = 0;
+	}
+
+	i = 0;
+	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+		helper->crtc_info[i].crtc_id = crtc->base.id;
+		helper->crtc_info[i].mode_set.crtc = crtc;
+		i++;
+	}
+	helper->conn_limit = max_conn_count;
+	return 0;
+out_free:
+	drm_fb_helper_crtc_free(helper);
+	return -ENOMEM;
+}
+EXPORT_SYMBOL(drm_fb_helper_init_crtc_count);
+
+int drm_fb_helper_setcolreg(unsigned regno,
+			    unsigned red,
+			    unsigned green,
+			    unsigned blue,
+			    unsigned transp,
+			    struct fb_info *info)
+{
+	struct drm_fb_helper *fb_helper = info->par;
+	struct drm_device *dev = fb_helper->dev;
+	struct drm_crtc *crtc;
+	int i;
+
+	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+		struct drm_framebuffer *fb = fb_helper->fb;
+
+		for (i = 0; i < fb_helper->crtc_count; i++) {
+			if (crtc->base.id == fb_helper->crtc_info[i].crtc_id)
+				break;
+		}
+		if (i == fb_helper->crtc_count)
+			continue;
+
+		if (regno > 255)
+			return 1;
+
+		if (fb->depth == 8) {
+			fb_helper->funcs->gamma_set(crtc, red, green, blue, regno);
+			return 0;
+		}
+
+		if (regno < 16) {
+			switch (fb->depth) {
+			case 15:
+				fb->pseudo_palette[regno] = ((red & 0xf800) >> 1) |
+					((green & 0xf800) >>  6) |
+					((blue & 0xf800) >> 11);
+				break;
+			case 16:
+				fb->pseudo_palette[regno] = (red & 0xf800) |
+					((green & 0xfc00) >>  5) |
+					((blue  & 0xf800) >> 11);
+				break;
+			case 24:
+			case 32:
+				fb->pseudo_palette[regno] =
+					(((red >> 8) & 0xff) << info->var.red.offset) |
+					(((green >> 8) & 0xff) << info->var.green.offset) |
+					(((blue >> 8) & 0xff) << info->var.blue.offset);
+				break;
+			}
+		}
+	}
+	return 0;
+}
+EXPORT_SYMBOL(drm_fb_helper_setcolreg);
+
+int drm_fb_helper_check_var(struct fb_var_screeninfo *var,
+			    struct fb_info *info)
+{
+	struct drm_fb_helper *fb_helper = info->par;
+	struct drm_framebuffer *fb = fb_helper->fb;
+	int depth;
+
+	if (var->pixclock == -1 || !var->pixclock)
+		return -EINVAL;
+
+	/* Need to resize the fb object !!! */
+	if (var->xres > fb->width || var->yres > fb->height) {
+		DRM_ERROR("Requested width/height is greater than current fb "
+			   "object %dx%d > %dx%d\n", var->xres, var->yres,
+			   fb->width, fb->height);
+		DRM_ERROR("Need resizing code.\n");
+		return -EINVAL;
+	}
+
+	switch (var->bits_per_pixel) {
+	case 16:
+		depth = (var->green.length == 6) ? 16 : 15;
+		break;
+	case 32:
+		depth = (var->transp.length > 0) ? 32 : 24;
+		break;
+	default:
+		depth = var->bits_per_pixel;
+		break;
+	}
+
+	switch (depth) {
+	case 8:
+		var->red.offset = 0;
+		var->green.offset = 0;
+		var->blue.offset = 0;
+		var->red.length = 8;
+		var->green.length = 8;
+		var->blue.length = 8;
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		break;
+	case 15:
+		var->red.offset = 10;
+		var->green.offset = 5;
+		var->blue.offset = 0;
+		var->red.length = 5;
+		var->green.length = 5;
+		var->blue.length = 5;
+		var->transp.length = 1;
+		var->transp.offset = 15;
+		break;
+	case 16:
+		var->red.offset = 11;
+		var->green.offset = 5;
+		var->blue.offset = 0;
+		var->red.length = 5;
+		var->green.length = 6;
+		var->blue.length = 5;
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		break;
+	case 24:
+		var->red.offset = 16;
+		var->green.offset = 8;
+		var->blue.offset = 0;
+		var->red.length = 8;
+		var->green.length = 8;
+		var->blue.length = 8;
+		var->transp.length = 0;
+		var->transp.offset = 0;
+		break;
+	case 32:
+		var->red.offset = 16;
+		var->green.offset = 8;
+		var->blue.offset = 0;
+		var->red.length = 8;
+		var->green.length = 8;
+		var->blue.length = 8;
+		var->transp.length = 8;
+		var->transp.offset = 24;
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+EXPORT_SYMBOL(drm_fb_helper_check_var);
+
+/* this will let fbcon do the mode init */
+int drm_fb_helper_set_par(struct fb_info *info)
+{
+	struct drm_fb_helper *fb_helper = info->par;
+	struct drm_device *dev = fb_helper->dev;
+	struct fb_var_screeninfo *var = &info->var;
+	struct drm_crtc *crtc;
+	int ret;
+	int i;
+
+	if (var->pixclock != -1) {
+		DRM_ERROR("PIXEL CLCOK SET\n");
+		return -EINVAL;
+	}
+
+	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+
+		for (i = 0; i < fb_helper->crtc_count; i++) {
+			if (crtc->base.id == fb_helper->crtc_info[i].crtc_id)
+				break;
+		}
+		if (i == fb_helper->crtc_count)
+			continue;
+
+		if (crtc->fb == fb_helper->crtc_info[i].mode_set.fb) {
+			mutex_lock(&dev->mode_config.mutex);
+			ret = crtc->funcs->set_config(&fb_helper->crtc_info->mode_set);
+			mutex_unlock(&dev->mode_config.mutex);
+			if (ret)
+				return ret;
+		}
+	}
+	return 0;
+}
+EXPORT_SYMBOL(drm_fb_helper_set_par);
+
+int drm_fb_helper_pan_display(struct fb_var_screeninfo *var,
+			      struct fb_info *info)
+{
+	struct drm_fb_helper *fb_helper = info->par;
+	struct drm_device *dev = fb_helper->dev;
+	struct drm_mode_set *modeset;
+	struct drm_crtc *crtc;
+	int ret = 0;
+	int i;
+
+	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+		for (i = 0; i < fb_helper->crtc_count; i++) {
+			if (crtc->base.id == fb_helper->crtc_info[i].crtc_id)
+				break;
+		}
+
+		if (i == fb_helper->crtc_count)
+			continue;
+
+		modeset = &fb_helper->crtc_info[i].mode_set;
+
+		modeset->x = var->xoffset;
+		modeset->y = var->yoffset;
+
+		if (modeset->num_connectors) {
+			mutex_lock(&dev->mode_config.mutex);
+			ret = crtc->funcs->set_config(modeset);
+			mutex_unlock(&dev->mode_config.mutex);
+			if (!ret) {
+				info->var.xoffset = var->xoffset;
+				info->var.yoffset = var->yoffset;
+			}
+		}
+	}
+	return ret;
+}
+EXPORT_SYMBOL(drm_fb_helper_pan_display);
+
+int drm_fb_helper_single_fb_probe(struct drm_device *dev,
+				  int (*fb_create)(struct drm_device *dev,
+						   uint32_t fb_width,
+						   uint32_t fb_height,
+						   uint32_t surface_width,
+						   uint32_t surface_height,
+						   struct drm_framebuffer **fb_ptr))
+{
+	struct drm_crtc *crtc;
+	struct drm_connector *connector;
+	unsigned int fb_width = (unsigned)-1, fb_height = (unsigned)-1;
+	unsigned int surface_width = 0, surface_height = 0;
+	int new_fb = 0;
+	int crtc_count = 0;
+	int ret, i, conn_count = 0;
+	struct fb_info *info;
+	struct drm_framebuffer *fb;
+	struct drm_mode_set *modeset = NULL;
+	struct drm_fb_helper *fb_helper;
+
+	/* first up get a count of crtcs now in use and new min/maxes width/heights */
+	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+		if (drm_helper_crtc_in_use(crtc)) {
+			if (crtc->desired_mode) {
+				if (crtc->desired_mode->hdisplay < fb_width)
+					fb_width = crtc->desired_mode->hdisplay;
+
+				if (crtc->desired_mode->vdisplay < fb_height)
+					fb_height = crtc->desired_mode->vdisplay;
+
+				if (crtc->desired_mode->hdisplay > surface_width)
+					surface_width = crtc->desired_mode->hdisplay;
+
+				if (crtc->desired_mode->vdisplay > surface_height)
+					surface_height = crtc->desired_mode->vdisplay;
+			}
+			crtc_count++;
+		}
+	}
+
+	if (crtc_count == 0 || fb_width == -1 || fb_height == -1) {
+		/* hmm everyone went away - assume VGA cable just fell out
+		   and will come back later. */
+		return 0;
+	}
+
+	/* do we have an fb already? */
+	if (list_empty(&dev->mode_config.fb_kernel_list)) {
+		ret = (*fb_create)(dev, fb_width, fb_height, surface_width,
+				   surface_height, &fb);
+		if (ret)
+			return -EINVAL;
+		new_fb = 1;
+	} else {
+		fb = list_first_entry(&dev->mode_config.fb_kernel_list,
+				      struct drm_framebuffer, filp_head);
+
+		/* if someone hotplugs something bigger than we have already allocated, we are pwned.
+		   As really we can't resize an fbdev that is in the wild currently due to fbdev
+		   not really being designed for the lower layers moving stuff around under it.
+		   - so in the grand style of things - punt. */
+		if ((fb->width < surface_width) ||
+		    (fb->height < surface_height)) {
+			DRM_ERROR("Framebuffer not large enough to scale console onto.\n");
+			return -EINVAL;
+		}
+	}
+
+	info = fb->fbdev;
+	fb_helper = info->par;
+
+	crtc_count = 0;
+	/* okay we need to setup new connector sets in the crtcs */
+	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+		modeset = &fb_helper->crtc_info[crtc_count].mode_set;
+		modeset->fb = fb;
+		conn_count = 0;
+		list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+			if (connector->encoder)
+				if (connector->encoder->crtc == modeset->crtc) {
+					modeset->connectors[conn_count] = connector;
+					conn_count++;
+					if (conn_count > fb_helper->conn_limit)
+						BUG();
+				}
+		}
+
+		for (i = conn_count; i < fb_helper->conn_limit; i++)
+			modeset->connectors[i] = NULL;
+
+		modeset->crtc = crtc;
+		crtc_count++;
+
+		modeset->num_connectors = conn_count;
+		if (modeset->crtc->desired_mode) {
+			if (modeset->mode)
+				drm_mode_destroy(dev, modeset->mode);
+			modeset->mode = drm_mode_duplicate(dev,
+							   modeset->crtc->desired_mode);
+		}
+	}
+	fb_helper->crtc_count = crtc_count;
+	fb_helper->fb = fb;
+
+	if (new_fb) {
+		info->var.pixclock = -1;
+		if (register_framebuffer(info) < 0)
+			return -EINVAL;
+	} else {
+		drm_fb_helper_set_par(info);
+	}
+	printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node,
+	       info->fix.id);
+
+	/* Switch back to kernel console on panic */
+	/* multi card linked list maybe */
+	if (list_empty(&kernel_fb_helper_list)) {
+		printk(KERN_INFO "registered panic notifier\n");
+		atomic_notifier_chain_register(&panic_notifier_list,
+					       &paniced);
+		register_sysrq_key('v', &sysrq_drm_fb_helper_restore_op);
+	}
+	list_add(&fb_helper->kernel_fb_list, &kernel_fb_helper_list);
+	return 0;
+}
+EXPORT_SYMBOL(drm_fb_helper_single_fb_probe);
+
+void drm_fb_helper_free(struct drm_fb_helper *helper)
+{
+	list_del(&helper->kernel_fb_list);
+	if (list_empty(&kernel_fb_helper_list)) {
+		printk(KERN_INFO "unregistered panic notifier\n");
+		atomic_notifier_chain_unregister(&panic_notifier_list,
+						 &paniced);
+		unregister_sysrq_key('v', &sysrq_drm_fb_helper_restore_op);
+	}
+	drm_fb_helper_crtc_free(helper);
+}
+EXPORT_SYMBOL(drm_fb_helper_free);
+
+void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch)
+{
+	info->fix.type = FB_TYPE_PACKED_PIXELS;
+	info->fix.visual = FB_VISUAL_TRUECOLOR;
+	info->fix.type_aux = 0;
+	info->fix.xpanstep = 1; /* doing it in hw */
+	info->fix.ypanstep = 1; /* doing it in hw */
+	info->fix.ywrapstep = 0;
+	info->fix.accel = FB_ACCEL_I830;
+	info->fix.type_aux = 0;
+
+	info->fix.line_length = pitch;
+	return;
+}
+EXPORT_SYMBOL(drm_fb_helper_fill_fix);
+
+void drm_fb_helper_fill_var(struct fb_info *info, struct drm_framebuffer *fb,
+			    uint32_t fb_width, uint32_t fb_height)
+{
+	info->pseudo_palette = fb->pseudo_palette;
+	info->var.xres_virtual = fb->width;
+	info->var.yres_virtual = fb->height;
+	info->var.bits_per_pixel = fb->bits_per_pixel;
+	info->var.xoffset = 0;
+	info->var.yoffset = 0;
+	info->var.activate = FB_ACTIVATE_NOW;
+	info->var.height = -1;
+	info->var.width = -1;
+
+	switch (fb->depth) {
+	case 8:
+		info->var.red.offset = 0;
+		info->var.green.offset = 0;
+		info->var.blue.offset = 0;
+		info->var.red.length = 8; /* 8bit DAC */
+		info->var.green.length = 8;
+		info->var.blue.length = 8;
+		info->var.transp.offset = 0;
+		info->var.transp.length = 0;
+		break;
+	case 15:
+		info->var.red.offset = 10;
+		info->var.green.offset = 5;
+		info->var.blue.offset = 0;
+		info->var.red.length = 5;
+		info->var.green.length = 5;
+		info->var.blue.length = 5;
+		info->var.transp.offset = 15;
+		info->var.transp.length = 1;
+		break;
+	case 16:
+		info->var.red.offset = 11;
+		info->var.green.offset = 5;
+		info->var.blue.offset = 0;
+		info->var.red.length = 5;
+		info->var.green.length = 6;
+		info->var.blue.length = 5;
+		info->var.transp.offset = 0;
+		break;
+	case 24:
+		info->var.red.offset = 16;
+		info->var.green.offset = 8;
+		info->var.blue.offset = 0;
+		info->var.red.length = 8;
+		info->var.green.length = 8;
+		info->var.blue.length = 8;
+		info->var.transp.offset = 0;
+		info->var.transp.length = 0;
+		break;
+	case 32:
+		info->var.red.offset = 16;
+		info->var.green.offset = 8;
+		info->var.blue.offset = 0;
+		info->var.red.length = 8;
+		info->var.green.length = 8;
+		info->var.blue.length = 8;
+		info->var.transp.offset = 24;
+		info->var.transp.length = 8;
+		break;
+	default:
+		break;
+	}
+
+	info->var.xres = fb_width;
+	info->var.yres = fb_height;
+}
+EXPORT_SYMBOL(drm_fb_helper_fill_var);
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 544d889b9b1..c628c367139 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -29,6 +29,7 @@
 #include "drmP.h"
 #include "drm.h"
 #include "drm_crtc_helper.h"
+#include "drm_fb_helper.h"
 #include "intel_drv.h"
 #include "i915_drm.h"
 #include "i915_drv.h"
@@ -1347,7 +1348,7 @@ void i915_driver_lastclose(struct drm_device * dev)
 	drm_i915_private_t *dev_priv = dev->dev_private;
 
 	if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
-		intelfb_restore();
+		drm_fb_helper_restore();
 		return;
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d6fce213341..5fb7a4f4a42 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3060,8 +3060,6 @@ static void intel_crtc_destroy(struct drm_crtc *crtc)
 {
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 
-	if (intel_crtc->mode_set.mode)
-		drm_mode_destroy(crtc->dev, intel_crtc->mode_set.mode);
 	drm_crtc_cleanup(crtc);
 	kfree(intel_crtc);
 }
@@ -3107,16 +3105,6 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
 	intel_crtc->cursor_addr = 0;
 	intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
 	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
-
-	intel_crtc->mode_set.crtc = &intel_crtc->base;
-	intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1);
-	intel_crtc->mode_set.num_connectors = 0;
-
-	if (i915_fbpercrtc) {
-
-
-
-	}
 }
 
 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d6f92ea1b55..38910f8f30e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -96,9 +96,6 @@ struct intel_crtc {
 	uint32_t cursor_addr;
 	u8 lut_r[256], lut_g[256], lut_b[256];
 	int dpms_mode;
-	struct intel_framebuffer *fbdev_fb;
-	/* a mode_set for fbdev users on this crtc */
-	struct drm_mode_set mode_set;
 };
 
 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index 1d30802e773..3041530c367 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -39,339 +39,34 @@
 #include "drmP.h"
 #include "drm.h"
 #include "drm_crtc.h"
+#include "drm_fb_helper.h"
 #include "intel_drv.h"
 #include "i915_drm.h"
 #include "i915_drv.h"
 
 struct intelfb_par {
-	struct drm_device *dev;
-	struct drm_display_mode *our_mode;
+	struct drm_fb_helper helper;
 	struct intel_framebuffer *intel_fb;
-	int crtc_count;
-	/* crtc currently bound to this */
-	uint32_t crtc_ids[2];
+	struct drm_display_mode *our_mode;
 };
 
-static int intelfb_setcolreg(unsigned regno, unsigned red, unsigned green,
-			unsigned blue, unsigned transp,
-			struct fb_info *info)
-{
-	struct intelfb_par *par = info->par;
-	struct drm_device *dev = par->dev;
-	struct drm_crtc *crtc;
-	int i;
-
-	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-		struct drm_mode_set *modeset = &intel_crtc->mode_set;
-		struct drm_framebuffer *fb = modeset->fb;
-
-		for (i = 0; i < par->crtc_count; i++)
-			if (crtc->base.id == par->crtc_ids[i])
-				break;
-
-		if (i == par->crtc_count)
-			continue;
-
-
-		if (regno > 255)
-			return 1;
-
-		if (fb->depth == 8) {
-			intel_crtc_fb_gamma_set(crtc, red, green, blue, regno);
-			return 0;
-		}
-
-		if (regno < 16) {
-			switch (fb->depth) {
-			case 15:
-				fb->pseudo_palette[regno] = ((red & 0xf800) >> 1) |
-					((green & 0xf800) >>  6) |
-					((blue & 0xf800) >> 11);
-				break;
-			case 16:
-				fb->pseudo_palette[regno] = (red & 0xf800) |
-					((green & 0xfc00) >>  5) |
-					((blue  & 0xf800) >> 11);
-				break;
-			case 24:
-			case 32:
-				fb->pseudo_palette[regno] = ((red & 0xff00) << 8) |
-					(green & 0xff00) |
-					((blue  & 0xff00) >> 8);
-				break;
-			}
-		}
-	}
-	return 0;
-}
-
-static int intelfb_check_var(struct fb_var_screeninfo *var,
-			struct fb_info *info)
-{
-	struct intelfb_par *par = info->par;
-	struct intel_framebuffer *intel_fb = par->intel_fb;
-	struct drm_framebuffer *fb = &intel_fb->base;
-	int depth;
-
-	if (var->pixclock == -1 || !var->pixclock)
-		return -EINVAL;
-
-	/* Need to resize the fb object !!! */
-	if (var->xres > fb->width || var->yres > fb->height) {
-		DRM_ERROR("Requested width/height is greater than current fb object %dx%d > %dx%d\n",var->xres,var->yres,fb->width,fb->height);
-		DRM_ERROR("Need resizing code.\n");
-		return -EINVAL;
-	}
-
-	switch (var->bits_per_pixel) {
-	case 16:
-		depth = (var->green.length == 6) ? 16 : 15;
-		break;
-	case 32:
-		depth = (var->transp.length > 0) ? 32 : 24;
-		break;
-	default:
-		depth = var->bits_per_pixel;
-		break;
-	}
-
-	switch (depth) {
-	case 8:
-		var->red.offset = 0;
-		var->green.offset = 0;
-		var->blue.offset = 0;
-		var->red.length = 8;
-		var->green.length = 8;
-		var->blue.length = 8;
-		var->transp.length = 0;
-		var->transp.offset = 0;
-		break;
-	case 15:
-		var->red.offset = 10;
-		var->green.offset = 5;
-		var->blue.offset = 0;
-		var->red.length = 5;
-		var->green.length = 5;
-		var->blue.length = 5;
-		var->transp.length = 1;
-		var->transp.offset = 15;
-		break;
-	case 16:
-		var->red.offset = 11;
-		var->green.offset = 5;
-		var->blue.offset = 0;
-		var->red.length = 5;
-		var->green.length = 6;
-		var->blue.length = 5;
-		var->transp.length = 0;
-		var->transp.offset = 0;
-		break;
-	case 24:
-		var->red.offset = 16;
-		var->green.offset = 8;
-		var->blue.offset = 0;
-		var->red.length = 8;
-		var->green.length = 8;
-		var->blue.length = 8;
-		var->transp.length = 0;
-		var->transp.offset = 0;
-		break;
-	case 32:
-		var->red.offset = 16;
-		var->green.offset = 8;
-		var->blue.offset = 0;
-		var->red.length = 8;
-		var->green.length = 8;
-		var->blue.length = 8;
-		var->transp.length = 8;
-		var->transp.offset = 24;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-/* this will let fbcon do the mode init */
-/* FIXME: take mode config lock? */
-static int intelfb_set_par(struct fb_info *info)
-{
-	struct intelfb_par *par = info->par;
-	struct drm_device *dev = par->dev;
-	struct fb_var_screeninfo *var = &info->var;
-	int i;
-
-	DRM_DEBUG("%d %d\n", var->xres, var->pixclock);
-
-	if (var->pixclock != -1) {
-
-		DRM_ERROR("PIXEL CLOCK SET\n");
-		return -EINVAL;
-	} else {
-		struct drm_crtc *crtc;
-		int ret;
-
-		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-			struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
-			for (i = 0; i < par->crtc_count; i++)
-				if (crtc->base.id == par->crtc_ids[i])
-					break;
-
-			if (i == par->crtc_count)
-				continue;
-
-			if (crtc->fb == intel_crtc->mode_set.fb) {
-				mutex_lock(&dev->mode_config.mutex);
-				ret = crtc->funcs->set_config(&intel_crtc->mode_set);
-				mutex_unlock(&dev->mode_config.mutex);
-				if (ret)
-					return ret;
-			}
-		}
-		return 0;
-	}
-}
-
-static int intelfb_pan_display(struct fb_var_screeninfo *var,
-				struct fb_info *info)
-{
-	struct intelfb_par *par = info->par;
-	struct drm_device *dev = par->dev;
-	struct drm_mode_set *modeset;
-	struct drm_crtc *crtc;
-	struct intel_crtc *intel_crtc;
-	int ret = 0;
-	int i;
-
-	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-		for (i = 0; i < par->crtc_count; i++)
-			if (crtc->base.id == par->crtc_ids[i])
-				break;
-
-		if (i == par->crtc_count)
-			continue;
-
-		intel_crtc = to_intel_crtc(crtc);
-		modeset = &intel_crtc->mode_set;
-
-		modeset->x = var->xoffset;
-		modeset->y = var->yoffset;
-
-		if (modeset->num_connectors) {
-			mutex_lock(&dev->mode_config.mutex);
-			ret = crtc->funcs->set_config(modeset);
-			mutex_unlock(&dev->mode_config.mutex);
-			if (!ret) {
-				info->var.xoffset = var->xoffset;
-				info->var.yoffset = var->yoffset;
-			}
-		}
-	}
-
-	return ret;
-}
-
-static void intelfb_on(struct fb_info *info)
-{
-	struct intelfb_par *par = info->par;
-	struct drm_device *dev = par->dev;
-	struct drm_crtc *crtc;
-	struct drm_encoder *encoder;
-	int i;
-
-	/*
-	 * For each CRTC in this fb, find all associated encoders
-	 * and turn them off, then turn off the CRTC.
-	 */
-	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-		struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
-
-		for (i = 0; i < par->crtc_count; i++)
-			if (crtc->base.id == par->crtc_ids[i])
-				break;
-
-		crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
-
-		/* Found a CRTC on this fb, now find encoders */
-		list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
-			if (encoder->crtc == crtc) {
-				struct drm_encoder_helper_funcs *encoder_funcs;
-				encoder_funcs = encoder->helper_private;
-				encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
-			}
-		}
-	}
-}
-
-static void intelfb_off(struct fb_info *info, int dpms_mode)
-{
-	struct intelfb_par *par = info->par;
-	struct drm_device *dev = par->dev;
-	struct drm_crtc *crtc;
-	struct drm_encoder *encoder;
-	int i;
-
-	/*
-	 * For each CRTC in this fb, find all associated encoders
-	 * and turn them off, then turn off the CRTC.
-	 */
-	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-		struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
-
-		for (i = 0; i < par->crtc_count; i++)
-			if (crtc->base.id == par->crtc_ids[i])
-				break;
-
-		/* Found a CRTC on this fb, now find encoders */
-		list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
-			if (encoder->crtc == crtc) {
-				struct drm_encoder_helper_funcs *encoder_funcs;
-				encoder_funcs = encoder->helper_private;
-				encoder_funcs->dpms(encoder, dpms_mode);
-			}
-		}
-		if (dpms_mode == DRM_MODE_DPMS_OFF)
-			crtc_funcs->dpms(crtc, dpms_mode);
-	}
-}
-
-static int intelfb_blank(int blank, struct fb_info *info)
-{
-	switch (blank) {
-	case FB_BLANK_UNBLANK:
-		intelfb_on(info);
-		break;
-	case FB_BLANK_NORMAL:
-		intelfb_off(info, DRM_MODE_DPMS_STANDBY);
-		break;
-	case FB_BLANK_HSYNC_SUSPEND:
-		intelfb_off(info, DRM_MODE_DPMS_STANDBY);
-		break;
-	case FB_BLANK_VSYNC_SUSPEND:
-		intelfb_off(info, DRM_MODE_DPMS_SUSPEND);
-		break;
-	case FB_BLANK_POWERDOWN:
-		intelfb_off(info, DRM_MODE_DPMS_OFF);
-		break;
-	}
-	return 0;
-}
-
 static struct fb_ops intelfb_ops = {
 	.owner = THIS_MODULE,
-	.fb_check_var = intelfb_check_var,
-	.fb_set_par = intelfb_set_par,
-	.fb_setcolreg = intelfb_setcolreg,
+	.fb_check_var = drm_fb_helper_check_var,
+	.fb_set_par = drm_fb_helper_set_par,
+	.fb_setcolreg = drm_fb_helper_setcolreg,
 	.fb_fillrect = cfb_fillrect,
 	.fb_copyarea = cfb_copyarea,
 	.fb_imageblit = cfb_imageblit,
-	.fb_pan_display = intelfb_pan_display,
-	.fb_blank = intelfb_blank,
+	.fb_pan_display = drm_fb_helper_pan_display,
+	.fb_blank = drm_fb_helper_blank,
 };
 
+static struct drm_fb_helper_funcs intel_fb_helper_funcs = {
+	.gamma_set = intel_crtc_fb_gamma_set,
+};
+
+
 /**
  * Curretly it is assumed that the old framebuffer is reused.
  *
@@ -412,25 +107,10 @@ int intelfb_resize(struct drm_device *dev, struct drm_crtc *crtc)
 }
 EXPORT_SYMBOL(intelfb_resize);
 
-static struct drm_mode_set kernelfb_mode;
-
-static int intelfb_panic(struct notifier_block *n, unsigned long ununsed,
-			 void *panic_str)
-{
-	DRM_ERROR("panic occurred, switching back to text console\n");
-
-	intelfb_restore();
-	return 0;
-}
-
-static struct notifier_block paniced = {
-	.notifier_call = intelfb_panic,
-};
-
 static int intelfb_create(struct drm_device *dev, uint32_t fb_width,
 			  uint32_t fb_height, uint32_t surface_width,
 			  uint32_t surface_height,
-			  struct intel_framebuffer **intel_fb_p)
+			  struct drm_framebuffer **fb_p)
 {
 	struct fb_info *info;
 	struct intelfb_par *par;
@@ -479,7 +159,7 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width,
 	list_add(&fb->filp_head, &dev->mode_config.fb_kernel_list);
 
 	intel_fb = to_intel_framebuffer(fb);
-	*intel_fb_p = intel_fb;
+	*fb_p = fb;
 
 	info = framebuffer_alloc(sizeof(struct intelfb_par), device);
 	if (!info) {
@@ -489,21 +169,19 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width,
 
 	par = info->par;
 
+	par->helper.funcs = &intel_fb_helper_funcs;
+	par->helper.dev = dev;
+	ret = drm_fb_helper_init_crtc_count(&par->helper, 2,
+					    INTELFB_CONN_LIMIT);
+	if (ret)
+		goto out_unref;
+
 	strcpy(info->fix.id, "inteldrmfb");
-	info->fix.type = FB_TYPE_PACKED_PIXELS;
-	info->fix.visual = FB_VISUAL_TRUECOLOR;
-	info->fix.type_aux = 0;
-	info->fix.xpanstep = 1; /* doing it in hw */
-	info->fix.ypanstep = 1; /* doing it in hw */
-	info->fix.ywrapstep = 0;
-	info->fix.accel = FB_ACCEL_I830;
-	info->fix.type_aux = 0;
 
 	info->flags = FBINFO_DEFAULT;
 
 	info->fbops = &intelfb_ops;
 
-	info->fix.line_length = fb->pitch;
 
 	/* setup aperture base/size for vesafb takeover */
 	info->aperture_base = dev->mode_config.fb_base;
@@ -527,18 +205,8 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width,
 
 //	memset(info->screen_base, 0, size);
 
-	info->pseudo_palette = fb->pseudo_palette;
-	info->var.xres_virtual = fb->width;
-	info->var.yres_virtual = fb->height;
-	info->var.bits_per_pixel = fb->bits_per_pixel;
-	info->var.xoffset = 0;
-	info->var.yoffset = 0;
-	info->var.activate = FB_ACTIVATE_NOW;
-	info->var.height = -1;
-	info->var.width = -1;
-
-	info->var.xres = fb_width;
-	info->var.yres = fb_height;
+	drm_fb_helper_fill_fix(info, fb->depth);
+	drm_fb_helper_fill_var(info, fb, fb_width, fb_height);
 
 	/* FIXME: we really shouldn't expose mmio space at all */
 	info->fix.mmio_start = pci_resource_start(dev->pdev, mmio_bar);
@@ -550,64 +218,9 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width,
 	info->pixmap.flags = FB_PIXMAP_SYSTEM;
 	info->pixmap.scan_align = 1;
 
-	switch(fb->depth) {
-	case 8:
-		info->var.red.offset = 0;
-		info->var.green.offset = 0;
-		info->var.blue.offset = 0;
-		info->var.red.length = 8; /* 8bit DAC */
-		info->var.green.length = 8;
-		info->var.blue.length = 8;
-		info->var.transp.offset = 0;
-		info->var.transp.length = 0;
-		break;
-	case 15:
-		info->var.red.offset = 10;
-		info->var.green.offset = 5;
-		info->var.blue.offset = 0;
-		info->var.red.length = 5;
-		info->var.green.length = 5;
-		info->var.blue.length = 5;
-		info->var.transp.offset = 15;
-		info->var.transp.length = 1;
-		break;
-	case 16:
-		info->var.red.offset = 11;
-		info->var.green.offset = 5;
-		info->var.blue.offset = 0;
-		info->var.red.length = 5;
-		info->var.green.length = 6;
-		info->var.blue.length = 5;
-		info->var.transp.offset = 0;
-		break;
-	case 24:
-		info->var.red.offset = 16;
-		info->var.green.offset = 8;
-		info->var.blue.offset = 0;
-		info->var.red.length = 8;
-		info->var.green.length = 8;
-		info->var.blue.length = 8;
-		info->var.transp.offset = 0;
-		info->var.transp.length = 0;
-		break;
-	case 32:
-		info->var.red.offset = 16;
-		info->var.green.offset = 8;
-		info->var.blue.offset = 0;
-		info->var.red.length = 8;
-		info->var.green.length = 8;
-		info->var.blue.length = 8;
-		info->var.transp.offset = 24;
-		info->var.transp.length = 8;
-		break;
-	default:
-		break;
-	}
-
 	fb->fbdev = info;
 
 	par->intel_fb = intel_fb;
-	par->dev = dev;
 
 	/* To allow resizeing without swapping buffers */
 	DRM_DEBUG("allocated %dx%d fb: 0x%08x, bo %p\n", intel_fb->base.width,
@@ -625,307 +238,12 @@ out:
 	return ret;
 }
 
-static int intelfb_multi_fb_probe_crtc(struct drm_device *dev, struct drm_crtc *crtc)
-{
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	struct intel_framebuffer *intel_fb;
-	struct drm_framebuffer *fb;
-	struct drm_connector *connector;
-	struct fb_info *info;
-	struct intelfb_par *par;
-	struct drm_mode_set *modeset;
-	unsigned int width, height;
-	int new_fb = 0;
-	int ret, i, conn_count;
-
-	if (!drm_helper_crtc_in_use(crtc))
-		return 0;
-
-	if (!crtc->desired_mode)
-		return 0;
-
-	width = crtc->desired_mode->hdisplay;
-	height = crtc->desired_mode->vdisplay;
-
-	/* is there an fb bound to this crtc already */
-	if (!intel_crtc->mode_set.fb) {
-		ret = intelfb_create(dev, width, height, width, height, &intel_fb);
-		if (ret)
-			return -EINVAL;
-		new_fb = 1;
-	} else {
-		fb = intel_crtc->mode_set.fb;
-		intel_fb = to_intel_framebuffer(fb);
-		if ((intel_fb->base.width < width) || (intel_fb->base.height < height))
-			return -EINVAL;
-	}
-
-	info = intel_fb->base.fbdev;
-	par = info->par;
-
-	modeset = &intel_crtc->mode_set;
-	modeset->fb = &intel_fb->base;
-	conn_count = 0;
-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-		if (connector->encoder)
-			if (connector->encoder->crtc == modeset->crtc) {
-				modeset->connectors[conn_count] = connector;
-				conn_count++;
-				if (conn_count > INTELFB_CONN_LIMIT)
-					BUG();
-			}
-	}
-
-	for (i = conn_count; i < INTELFB_CONN_LIMIT; i++)
-		modeset->connectors[i] = NULL;
-
-	par->crtc_ids[0] = crtc->base.id;
-
-	modeset->num_connectors = conn_count;
-	if (modeset->crtc->desired_mode) {
-		if (modeset->mode)
-			drm_mode_destroy(dev, modeset->mode);
-		modeset->mode = drm_mode_duplicate(dev,
-						   modeset->crtc->desired_mode);
-	}
-
-	par->crtc_count = 1;
-
-	if (new_fb) {
-		info->var.pixclock = -1;
-		if (register_framebuffer(info) < 0)
-			return -EINVAL;
-	} else
-		intelfb_set_par(info);
-
-	DRM_INFO("fb%d: %s frame buffer device\n", info->node,
-	       info->fix.id);
-
-	/* Switch back to kernel console on panic */
-	kernelfb_mode = *modeset;
-	atomic_notifier_chain_register(&panic_notifier_list, &paniced);
-	DRM_DEBUG("registered panic notifier\n");
-
-	return 0;
-}
-
-static int intelfb_multi_fb_probe(struct drm_device *dev)
-{
-
-	struct drm_crtc *crtc;
-	int ret = 0;
-
-	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-		ret = intelfb_multi_fb_probe_crtc(dev, crtc);
-		if (ret)
-			return ret;
-	}
-	return ret;
-}
-
-static int intelfb_single_fb_probe(struct drm_device *dev)
-{
-	struct drm_crtc *crtc;
-	struct drm_connector *connector;
-	unsigned int fb_width = (unsigned)-1, fb_height = (unsigned)-1;
-	unsigned int surface_width = 0, surface_height = 0;
-	int new_fb = 0;
-	int crtc_count = 0;
-	int ret, i, conn_count = 0;
-	struct intel_framebuffer *intel_fb;
-	struct fb_info *info;
-	struct intelfb_par *par;
-	struct drm_mode_set *modeset = NULL;
-
-	DRM_DEBUG("\n");
-
-	/* Get a count of crtcs now in use and new min/maxes width/heights */
-	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-		if (!drm_helper_crtc_in_use(crtc))
-			continue;
-
-		crtc_count++;
-		if (!crtc->desired_mode)
-			continue;
-
-		/* Smallest mode determines console size... */
-		if (crtc->desired_mode->hdisplay < fb_width)
-			fb_width = crtc->desired_mode->hdisplay;
-
-		if (crtc->desired_mode->vdisplay < fb_height)
-			fb_height = crtc->desired_mode->vdisplay;
-
-		/* ... but largest for memory allocation dimensions */
-		if (crtc->desired_mode->hdisplay > surface_width)
-			surface_width = crtc->desired_mode->hdisplay;
-
-		if (crtc->desired_mode->vdisplay > surface_height)
-			surface_height = crtc->desired_mode->vdisplay;
-	}
-
-	if (crtc_count == 0 || fb_width == -1 || fb_height == -1) {
-		/* hmm everyone went away - assume VGA cable just fell out
-		   and will come back later. */
-		DRM_DEBUG("no CRTCs available?\n");
-		return 0;
-	}
-
-//fail
-	/* Find the fb for our new config */
-	if (list_empty(&dev->mode_config.fb_kernel_list)) {
-		DRM_DEBUG("creating new fb (console size %dx%d, "
-			  "buffer size %dx%d)\n", fb_width, fb_height,
-			  surface_width, surface_height);
-		ret = intelfb_create(dev, fb_width, fb_height, surface_width,
-				     surface_height, &intel_fb);
-		if (ret)
-			return -EINVAL;
-		new_fb = 1;
-	} else {
-		struct drm_framebuffer *fb;
-
-		fb = list_first_entry(&dev->mode_config.fb_kernel_list,
-				      struct drm_framebuffer, filp_head);
-		intel_fb = to_intel_framebuffer(fb);
-
-		/* if someone hotplugs something bigger than we have already
-		 * allocated, we are pwned.  As really we can't resize an
-		 * fbdev that is in the wild currently due to fbdev not really
-		 * being designed for the lower layers moving stuff around
-		 * under it.
-		 * - so in the grand style of things - punt.
-		 */
-		if ((fb->width < surface_width) ||
-		    (fb->height < surface_height)) {
-			DRM_ERROR("fb not large enough for console\n");
-			return -EINVAL;
-		}
-	}
-// fail
-
-	info = intel_fb->base.fbdev;
-	par = info->par;
-
-	crtc_count = 0;
-	/*
-	 * For each CRTC, set up the connector list for the CRTC's mode
-	 * set configuration.
-	 */
-	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
-		modeset = &intel_crtc->mode_set;
-		modeset->fb = &intel_fb->base;
-		conn_count = 0;
-		list_for_each_entry(connector, &dev->mode_config.connector_list,
-				    head) {
-			if (!connector->encoder)
-				continue;
-
-			if(connector->encoder->crtc == modeset->crtc) {
-				modeset->connectors[conn_count++] = connector;
-				if (conn_count > INTELFB_CONN_LIMIT)
-					BUG();
-			}
-		}
-
-		/* Zero out remaining connector pointers */
-		for (i = conn_count; i < INTELFB_CONN_LIMIT; i++)
-			modeset->connectors[i] = NULL;
-
-		par->crtc_ids[crtc_count++] = crtc->base.id;
-
-		modeset->num_connectors = conn_count;
-		if (modeset->crtc->desired_mode) {
-			if (modeset->mode)
-				drm_mode_destroy(dev, modeset->mode);
-			modeset->mode = drm_mode_duplicate(dev,
-							   modeset->crtc->desired_mode);
-		}
-	}
-	par->crtc_count = crtc_count;
-
-	if (new_fb) {
-		info->var.pixclock = -1;
-		if (register_framebuffer(info) < 0)
-			return -EINVAL;
-	} else
-		intelfb_set_par(info);
-
-	DRM_INFO("fb%d: %s frame buffer device\n", info->node,
-	       info->fix.id);
-
-	/* Switch back to kernel console on panic */
-	kernelfb_mode = *modeset;
-	atomic_notifier_chain_register(&panic_notifier_list, &paniced);
-	DRM_DEBUG("registered panic notifier\n");
-
-	return 0;
-}
-
-/**
- * intelfb_restore - restore the framebuffer console (kernel) config
- *
- * Restore's the kernel's fbcon mode, used for lastclose & panic paths.
- */
-void intelfb_restore(void)
-{
-	int ret;
-	if ((ret = drm_crtc_helper_set_config(&kernelfb_mode)) != 0) {
-		DRM_ERROR("Failed to restore crtc configuration: %d\n",
-			  ret);
-	}
-}
-
-static void intelfb_restore_work_fn(struct work_struct *ignored)
-{
-	intelfb_restore();
-}
-static DECLARE_WORK(intelfb_restore_work, intelfb_restore_work_fn);
-
-static void intelfb_sysrq(int dummy1, struct tty_struct *dummy3)
-{
-        schedule_work(&intelfb_restore_work);
-}
-
-static struct sysrq_key_op sysrq_intelfb_restore_op = {
-        .handler = intelfb_sysrq,
-        .help_msg = "force-fb(V)",
-        .action_msg = "Restore framebuffer console",
-};
-
 int intelfb_probe(struct drm_device *dev)
 {
 	int ret;
 
 	DRM_DEBUG("\n");
-
-	/* something has changed in the lower levels of hell - deal with it
-	   here */
-
-	/* two modes : a) 1 fb to rule all crtcs.
-	               b) one fb per crtc.
-	   two actions 1) new connected device
-	               2) device removed.
-	   case a/1 : if the fb surface isn't big enough - resize the surface fb.
-	              if the fb size isn't big enough - resize fb into surface.
-		      if everything big enough configure the new crtc/etc.
-	   case a/2 : undo the configuration
-	              possibly resize down the fb to fit the new configuration.
-           case b/1 : see if it is on a new crtc - setup a new fb and add it.
-	   case b/2 : teardown the new fb.
-	*/
-
-	/* mode a first */
-	/* search for an fb */
-	if (i915_fbpercrtc == 1) {
-		ret = intelfb_multi_fb_probe(dev);
-	} else {
-		ret = intelfb_single_fb_probe(dev);
-	}
-
-	register_sysrq_key('v', &sysrq_intelfb_restore_op);
-
+	ret = drm_fb_helper_single_fb_probe(dev, intelfb_create);
 	return ret;
 }
 EXPORT_SYMBOL(intelfb_probe);
@@ -940,13 +258,14 @@ int intelfb_remove(struct drm_device *dev, struct drm_framebuffer *fb)
 	info = fb->fbdev;
 
 	if (info) {
+		struct intelfb_par *par = info->par;
 		unregister_framebuffer(info);
 		iounmap(info->screen_base);
+		if (info->par)
+			drm_fb_helper_free(&par->helper);
 		framebuffer_release(info);
 	}
 
-	atomic_notifier_chain_unregister(&panic_notifier_list, &paniced);
-	memset(&kernelfb_mode, 0, sizeof(struct drm_mode_set));
 	return 0;
 }
 EXPORT_SYMBOL(intelfb_remove);
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index a8fa1bb84cf..af035605d14 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -158,9 +158,6 @@ static void radeon_crtc_destroy(struct drm_crtc *crtc)
 {
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 
-	if (radeon_crtc->mode_set.mode) {
-		drm_mode_destroy(crtc->dev, radeon_crtc->mode_set.mode);
-	}
 	drm_crtc_cleanup(crtc);
 	kfree(radeon_crtc);
 }
@@ -189,9 +186,11 @@ static void radeon_crtc_init(struct drm_device *dev, int index)
 	radeon_crtc->crtc_id = index;
 	rdev->mode_info.crtcs[index] = radeon_crtc;
 
+#if 0
 	radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 	radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 	radeon_crtc->mode_set.num_connectors = 0;
+#endif
 
 	for (i = 0; i < 256; i++) {
 		radeon_crtc->lut_r[i] = i << 2;
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index ec383edf5f3..ebb58959f41 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -28,15 +28,7 @@
      */
 
 #include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/tty.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
 #include <linux/fb.h>
-#include <linux/init.h>
 
 #include "drmP.h"
 #include "drm.h"
@@ -45,375 +37,86 @@
 #include "radeon_drm.h"
 #include "radeon.h"
 
+#include "drm_fb_helper.h"
+
 struct radeon_fb_device {
-	struct radeon_device		*rdev;
-	struct drm_display_mode		*mode;
+	struct drm_fb_helper helper;
 	struct radeon_framebuffer	*rfb;
-	int				crtc_count;
-	/* crtc currently bound to this */
-	uint32_t			crtc_ids[2];
+	struct radeon_device		*rdev;
 };
 
-static int radeonfb_setcolreg(unsigned regno,
-			      unsigned red,
-			      unsigned green,
-			      unsigned blue,
-			      unsigned transp,
-			      struct fb_info *info)
-{
-	struct radeon_fb_device *rfbdev = info->par;
-	struct drm_device *dev = rfbdev->rdev->ddev;
-	struct drm_crtc *crtc;
-	int i;
-
-	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-		struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
-		struct drm_mode_set *modeset = &radeon_crtc->mode_set;
-		struct drm_framebuffer *fb = modeset->fb;
-
-		for (i = 0; i < rfbdev->crtc_count; i++) {
-			if (crtc->base.id == rfbdev->crtc_ids[i]) {
-				break;
-			}
-		}
-		if (i == rfbdev->crtc_count) {
-			continue;
-		}
-		if (regno > 255) {
-			return 1;
-		}
-		if (fb->depth == 8) {
-			radeon_crtc_fb_gamma_set(crtc, red, green, blue, regno);
-			return 0;
-		}
-
-		if (regno < 16) {
-			switch (fb->depth) {
-			case 15:
-				fb->pseudo_palette[regno] = ((red & 0xf800) >> 1) |
-					((green & 0xf800) >>  6) |
-					((blue & 0xf800) >> 11);
-				break;
-			case 16:
-				fb->pseudo_palette[regno] = (red & 0xf800) |
-					((green & 0xfc00) >>  5) |
-					((blue  & 0xf800) >> 11);
-				break;
-			case 24:
-			case 32:
-				fb->pseudo_palette[regno] =
-					(((red >> 8) & 0xff) << info->var.red.offset) |
-					(((green >> 8) & 0xff) << info->var.green.offset) |
-					(((blue >> 8) & 0xff) << info->var.blue.offset);
-				break;
-			}
-		}
-	}
-	return 0;
-}
-
-static int radeonfb_check_var(struct fb_var_screeninfo *var,
-			      struct fb_info *info)
+static int radeon_fb_check_var(struct fb_var_screeninfo *var,
+			       struct fb_info *info)
 {
-	struct radeon_fb_device *rfbdev = info->par;
-	struct radeon_framebuffer *rfb = rfbdev->rfb;
-	struct drm_framebuffer *fb = &rfb->base;
-	int depth;
-
-	if (var->pixclock == -1 || !var->pixclock) {
-		return -EINVAL;
-	}
-	/* Need to resize the fb object !!! */
-	if (var->xres > fb->width || var->yres > fb->height) {
-		DRM_ERROR("Requested width/height is greater than current fb "
-			   "object %dx%d > %dx%d\n", var->xres, var->yres,
-			   fb->width, fb->height);
-		DRM_ERROR("Need resizing code.\n");
-		return -EINVAL;
-	}
-
-	switch (var->bits_per_pixel) {
-	case 16:
-		depth = (var->green.length == 6) ? 16 : 15;
-		break;
-	case 32:
-		depth = (var->transp.length > 0) ? 32 : 24;
-		break;
-	default:
-		depth = var->bits_per_pixel;
-		break;
-	}
-
-	switch (depth) {
-	case 8:
-		var->red.offset = 0;
-		var->green.offset = 0;
-		var->blue.offset = 0;
-		var->red.length = 8;
-		var->green.length = 8;
-		var->blue.length = 8;
-		var->transp.length = 0;
-		var->transp.offset = 0;
-		break;
-#ifdef __LITTLE_ENDIAN
-	case 15:
-		var->red.offset = 10;
-		var->green.offset = 5;
-		var->blue.offset = 0;
-		var->red.length = 5;
-		var->green.length = 5;
-		var->blue.length = 5;
-		var->transp.length = 1;
-		var->transp.offset = 15;
-		break;
-	case 16:
-		var->red.offset = 11;
-		var->green.offset = 5;
-		var->blue.offset = 0;
-		var->red.length = 5;
-		var->green.length = 6;
-		var->blue.length = 5;
-		var->transp.length = 0;
-		var->transp.offset = 0;
-		break;
-	case 24:
-		var->red.offset = 16;
-		var->green.offset = 8;
-		var->blue.offset = 0;
-		var->red.length = 8;
-		var->green.length = 8;
-		var->blue.length = 8;
-		var->transp.length = 0;
-		var->transp.offset = 0;
-		break;
-	case 32:
-		var->red.offset = 16;
-		var->green.offset = 8;
-		var->blue.offset = 0;
-		var->red.length = 8;
-		var->green.length = 8;
-		var->blue.length = 8;
-		var->transp.length = 8;
-		var->transp.offset = 24;
-		break;
-#else
-	case 24:
-		var->red.offset = 8;
-		var->green.offset = 16;
-		var->blue.offset = 24;
-		var->red.length = 8;
-		var->green.length = 8;
-		var->blue.length = 8;
-		var->transp.length = 0;
-		var->transp.offset = 0;
-		break;
-	case 32:
-		var->red.offset = 8;
-		var->green.offset = 16;
-		var->blue.offset = 24;
-		var->red.length = 8;
-		var->green.length = 8;
-		var->blue.length = 8;
-		var->transp.length = 8;
-		var->transp.offset = 0;
-		break;
-#endif
-	default:
-		return -EINVAL;
-	}
-	return 0;
-}
-
-/* this will let fbcon do the mode init */
-static int radeonfb_set_par(struct fb_info *info)
-{
-	struct radeon_fb_device *rfbdev = info->par;
-	struct drm_device *dev = rfbdev->rdev->ddev;
-	struct fb_var_screeninfo *var = &info->var;
-	struct drm_crtc *crtc;
 	int ret;
-	int i;
-
-	if (var->pixclock != -1) {
-		DRM_ERROR("PIXEL CLCOK SET\n");
-		return -EINVAL;
-	}
-
-	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-		struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
-
-		for (i = 0; i < rfbdev->crtc_count; i++) {
-			if (crtc->base.id == rfbdev->crtc_ids[i]) {
-				break;
-			}
-		}
-		if (i == rfbdev->crtc_count) {
-			continue;
-		}
-		if (crtc->fb == radeon_crtc->mode_set.fb) {
-			mutex_lock(&dev->mode_config.mutex);
-			ret = crtc->funcs->set_config(&radeon_crtc->mode_set);
-			mutex_unlock(&dev->mode_config.mutex);
-			if (ret) {
-				return ret;
-			}
-		}
-	}
-	return 0;
-}
-
-static int radeonfb_pan_display(struct fb_var_screeninfo *var,
-				struct fb_info *info)
-{
-	struct radeon_fb_device *rfbdev = info->par;
-	struct drm_device *dev = rfbdev->rdev->ddev;
-	struct drm_mode_set *modeset;
-	struct drm_crtc *crtc;
-	struct radeon_crtc *radeon_crtc;
-	int ret = 0;
-	int i;
-
-	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-		for (i = 0; i < rfbdev->crtc_count; i++) {
-			if (crtc->base.id == rfbdev->crtc_ids[i]) {
-				break;
-			}
-		}
-
-		if (i == rfbdev->crtc_count) {
-			continue;
-		}
-
-		radeon_crtc = to_radeon_crtc(crtc);
-		modeset = &radeon_crtc->mode_set;
-
-		modeset->x = var->xoffset;
-		modeset->y = var->yoffset;
-
-		if (modeset->num_connectors) {
-			mutex_lock(&dev->mode_config.mutex);
-			ret = crtc->funcs->set_config(modeset);
-			mutex_unlock(&dev->mode_config.mutex);
-			if (!ret) {
-				info->var.xoffset = var->xoffset;
-				info->var.yoffset = var->yoffset;
-			}
+	ret = drm_fb_helper_check_var(var, info);
+	if (ret)
+		return ret;
+
+	/* big endian override for radeon endian workaround */
+#ifdef __BIG_ENDIAN
+	{
+		int depth;
+		switch (var->bits_per_pixel) {
+		case 16:
+			depth = (var->green.length == 6) ? 16 : 15;
+			break;
+		case 32:
+			depth = (var->transp.length > 0) ? 32 : 24;
+			break;
+		default:
+			depth = var->bits_per_pixel;
+			break;
 		}
-	}
-	return ret;
-}
-
-static void radeonfb_on(struct fb_info *info)
-{
-	struct radeon_fb_device *rfbdev = info->par;
-	struct drm_device *dev = rfbdev->rdev->ddev;
-	struct drm_crtc *crtc;
-	struct drm_encoder *encoder;
-	int i;
-
-	/*
-	 * For each CRTC in this fb, find all associated encoders
-	 * and turn them off, then turn off the CRTC.
-	 */
-	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-		struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
-
-		for (i = 0; i < rfbdev->crtc_count; i++) {
-			if (crtc->base.id == rfbdev->crtc_ids[i]) {
-				break;
-			}
-		}
-
-		mutex_lock(&dev->mode_config.mutex);
-		crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
-		mutex_unlock(&dev->mode_config.mutex);
-
-		/* Found a CRTC on this fb, now find encoders */
-		list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
-			if (encoder->crtc == crtc) {
-				struct drm_encoder_helper_funcs *encoder_funcs;
-
-				encoder_funcs = encoder->helper_private;
-				mutex_lock(&dev->mode_config.mutex);
-				encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
-				mutex_unlock(&dev->mode_config.mutex);
-			}
-		}
-	}
-}
-
-static void radeonfb_off(struct fb_info *info, int dpms_mode)
-{
-	struct radeon_fb_device *rfbdev = info->par;
-	struct drm_device *dev = rfbdev->rdev->ddev;
-	struct drm_crtc *crtc;
-	struct drm_encoder *encoder;
-	int i;
-
-	/*
-	 * For each CRTC in this fb, find all associated encoders
-	 * and turn them off, then turn off the CRTC.
-	 */
-	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-		struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
-
-		for (i = 0; i < rfbdev->crtc_count; i++) {
-			if (crtc->base.id == rfbdev->crtc_ids[i]) {
-				break;
-			}
-		}
-
-		/* Found a CRTC on this fb, now find encoders */
-		list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
-			if (encoder->crtc == crtc) {
-				struct drm_encoder_helper_funcs *encoder_funcs;
-
-				encoder_funcs = encoder->helper_private;
-				mutex_lock(&dev->mode_config.mutex);
-				encoder_funcs->dpms(encoder, dpms_mode);
-				mutex_unlock(&dev->mode_config.mutex);
-			}
-		}
-		if (dpms_mode == DRM_MODE_DPMS_OFF) {
-			mutex_lock(&dev->mode_config.mutex);
-			crtc_funcs->dpms(crtc, dpms_mode);
-			mutex_unlock(&dev->mode_config.mutex);
+		switch (depth) {
+		case 8:
+			var->red.offset = 0;
+			var->green.offset = 0;
+			var->blue.offset = 0;
+			var->red.length = 8;
+			var->green.length = 8;
+			var->blue.length = 8;
+			var->transp.length = 0;
+			var->transp.offset = 0;
+			break;
+		case 24:
+			var->red.offset = 8;
+			var->green.offset = 16;
+			var->blue.offset = 24;
+			var->red.length = 8;
+			var->green.length = 8;
+			var->blue.length = 8;
+			var->transp.length = 0;
+			var->transp.offset = 0;
+			break;
+		case 32:
+			var->red.offset = 8;
+			var->green.offset = 16;
+			var->blue.offset = 24;
+			var->red.length = 8;
+			var->green.length = 8;
+			var->blue.length = 8;
+			var->transp.length = 8;
+			var->transp.offset = 0;
+			break;
+		default:
+			return -EINVAL;
 		}
 	}
-}
-
-int radeonfb_blank(int blank, struct fb_info *info)
-{
-	switch (blank) {
-	case FB_BLANK_UNBLANK:
-		radeonfb_on(info);
-		break;
-	case FB_BLANK_NORMAL:
-		radeonfb_off(info, DRM_MODE_DPMS_STANDBY);
-		break;
-	case FB_BLANK_HSYNC_SUSPEND:
-		radeonfb_off(info, DRM_MODE_DPMS_STANDBY);
-		break;
-	case FB_BLANK_VSYNC_SUSPEND:
-		radeonfb_off(info, DRM_MODE_DPMS_SUSPEND);
-		break;
-	case FB_BLANK_POWERDOWN:
-		radeonfb_off(info, DRM_MODE_DPMS_OFF);
-		break;
-	}
+#endif
 	return 0;
 }
 
 static struct fb_ops radeonfb_ops = {
 	.owner = THIS_MODULE,
-	.fb_check_var = radeonfb_check_var,
-	.fb_set_par = radeonfb_set_par,
-	.fb_setcolreg = radeonfb_setcolreg,
+	.fb_check_var = radeon_fb_check_var,
+	.fb_set_par = drm_fb_helper_set_par,
+	.fb_setcolreg = drm_fb_helper_setcolreg,
 	.fb_fillrect = cfb_fillrect,
 	.fb_copyarea = cfb_copyarea,
 	.fb_imageblit = cfb_imageblit,
-	.fb_pan_display = radeonfb_pan_display,
-	.fb_blank = radeonfb_blank,
+	.fb_pan_display = drm_fb_helper_pan_display,
+	.fb_blank = drm_fb_helper_blank,
 };
 
 /**
@@ -456,21 +159,6 @@ int radeonfb_resize(struct drm_device *dev, struct drm_crtc *crtc)
 }
 EXPORT_SYMBOL(radeonfb_resize);
 
-static struct drm_mode_set panic_mode;
-
-int radeonfb_panic(struct notifier_block *n, unsigned long ununsed,
-		  void *panic_str)
-{
-	DRM_ERROR("panic occurred, switching back to text console\n");
-	drm_crtc_helper_set_config(&panic_mode);
-	return 0;
-}
-EXPORT_SYMBOL(radeonfb_panic);
-
-static struct notifier_block paniced = {
-	.notifier_call = radeonfb_panic,
-};
-
 static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
 {
 	int aligned = width;
@@ -495,11 +183,16 @@ static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bo
 	return aligned;
 }
 
-int radeonfb_create(struct radeon_device *rdev,
+static struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
+	.gamma_set = radeon_crtc_fb_gamma_set,
+};
+
+int radeonfb_create(struct drm_device *dev,
 		    uint32_t fb_width, uint32_t fb_height,
 		    uint32_t surface_width, uint32_t surface_height,
-		    struct radeon_framebuffer **rfb_p)
+		    struct drm_framebuffer **fb_p)
 {
+	struct radeon_device *rdev = dev->dev_private;
 	struct fb_info *info;
 	struct radeon_fb_device *rfbdev;
 	struct drm_framebuffer *fb = NULL;
@@ -554,8 +247,8 @@ int radeonfb_create(struct radeon_device *rdev,
 
 	list_add(&fb->filp_head, &rdev->ddev->mode_config.fb_kernel_list);
 
+	*fb_p = fb;
 	rfb = to_radeon_framebuffer(fb);
-	*rfb_p = rfb;
 	rdev->fbdev_rfb = rfb;
 	rdev->fbdev_robj = robj;
 
@@ -564,7 +257,14 @@ int radeonfb_create(struct radeon_device *rdev,
 		ret = -ENOMEM;
 		goto out_unref;
 	}
+
 	rfbdev = info->par;
+	rfbdev->helper.funcs = &radeon_fb_helper_funcs;
+	rfbdev->helper.dev = dev;
+	ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, 2,
+					    RADEONFB_CONN_LIMIT);
+	if (ret)
+		goto out_unref;
 
 	if (fb_tiled)
 		radeon_object_check_tiling(robj, 0, 0);
@@ -577,33 +277,19 @@ int radeonfb_create(struct radeon_device *rdev,
 	memset_io(fbptr, 0, aligned_size);
 
 	strcpy(info->fix.id, "radeondrmfb");
-	info->fix.type = FB_TYPE_PACKED_PIXELS;
-	info->fix.visual = FB_VISUAL_TRUECOLOR;
-	info->fix.type_aux = 0;
-	info->fix.xpanstep = 1; /* doing it in hw */
-	info->fix.ypanstep = 1; /* doing it in hw */
-	info->fix.ywrapstep = 0;
-	info->fix.accel = FB_ACCEL_NONE;
-	info->fix.type_aux = 0;
+
+	drm_fb_helper_fill_fix(info, fb->pitch);
+
 	info->flags = FBINFO_DEFAULT;
 	info->fbops = &radeonfb_ops;
-	info->fix.line_length = fb->pitch;
+
 	tmp = fb_gpuaddr - rdev->mc.vram_location;
 	info->fix.smem_start = rdev->mc.aper_base + tmp;
 	info->fix.smem_len = size;
 	info->screen_base = fbptr;
 	info->screen_size = size;
-	info->pseudo_palette = fb->pseudo_palette;
-	info->var.xres_virtual = fb->width;
-	info->var.yres_virtual = fb->height;
-	info->var.bits_per_pixel = fb->bits_per_pixel;
-	info->var.xoffset = 0;
-	info->var.yoffset = 0;
-	info->var.activate = FB_ACTIVATE_NOW;
-	info->var.height = -1;
-	info->var.width = -1;
-	info->var.xres = fb_width;
-	info->var.yres = fb_height;
+
+	drm_fb_helper_fill_var(info, fb, fb_width, fb_height);
 
 	/* setup aperture base/size for vesafb takeover */
 	info->aperture_base = rdev->ddev->mode_config.fb_base;
@@ -626,6 +312,9 @@ int radeonfb_create(struct radeon_device *rdev,
 	DRM_INFO("fb depth is %d\n", fb->depth);
 	DRM_INFO("   pitch is %d\n", fb->pitch);
 
+#ifdef __BIG_ENDIAN
+	/* fill var sets defaults for this stuff - override
+	   on big endian */
 	switch (fb->depth) {
 	case 8:
 		info->var.red.offset = 0;
@@ -637,47 +326,6 @@ int radeonfb_create(struct radeon_device *rdev,
 		info->var.transp.offset = 0;
 		info->var.transp.length = 0;
 		break;
-#ifdef __LITTLE_ENDIAN
-	case 15:
-		info->var.red.offset = 10;
-		info->var.green.offset = 5;
-		info->var.blue.offset = 0;
-		info->var.red.length = 5;
-		info->var.green.length = 5;
-		info->var.blue.length = 5;
-		info->var.transp.offset = 15;
-		info->var.transp.length = 1;
-		break;
-	case 16:
-		info->var.red.offset = 11;
-		info->var.green.offset = 5;
-		info->var.blue.offset = 0;
-		info->var.red.length = 5;
-		info->var.green.length = 6;
-		info->var.blue.length = 5;
-		info->var.transp.offset = 0;
-		break;
-	case 24:
-		info->var.red.offset = 16;
-		info->var.green.offset = 8;
-		info->var.blue.offset = 0;
-		info->var.red.length = 8;
-		info->var.green.length = 8;
-		info->var.blue.length = 8;
-		info->var.transp.offset = 0;
-		info->var.transp.length = 0;
-		break;
-	case 32:
-		info->var.red.offset = 16;
-		info->var.green.offset = 8;
-		info->var.blue.offset = 0;
-		info->var.red.length = 8;
-		info->var.green.length = 8;
-		info->var.blue.length = 8;
-		info->var.transp.offset = 24;
-		info->var.transp.length = 8;
-		break;
-#else
 	case 24:
 		info->var.red.offset = 8;
 		info->var.green.offset = 16;
@@ -699,9 +347,9 @@ int radeonfb_create(struct radeon_device *rdev,
 		info->var.transp.length = 8;
 		break;
 	default:
-#endif
 		break;
 	}
+#endif
 
 	fb->fbdev = info;
 	rfbdev->rfb = rfb;
@@ -726,145 +374,10 @@ out:
 	return ret;
 }
 
-static int radeonfb_single_fb_probe(struct radeon_device *rdev)
-{
-	struct drm_crtc *crtc;
-	struct drm_connector *connector;
-	unsigned int fb_width = (unsigned)-1, fb_height = (unsigned)-1;
-	unsigned int surface_width = 0, surface_height = 0;
-	int new_fb = 0;
-	int crtc_count = 0;
-	int ret, i, conn_count = 0;
-	struct radeon_framebuffer *rfb;
-	struct fb_info *info;
-	struct radeon_fb_device *rfbdev;
-	struct drm_mode_set *modeset = NULL;
-
-	/* first up get a count of crtcs now in use and new min/maxes width/heights */
-	list_for_each_entry(crtc, &rdev->ddev->mode_config.crtc_list, head) {
-		if (drm_helper_crtc_in_use(crtc)) {
-			if (crtc->desired_mode) {
-				if (crtc->desired_mode->hdisplay < fb_width)
-					fb_width = crtc->desired_mode->hdisplay;
-
-				if (crtc->desired_mode->vdisplay < fb_height)
-					fb_height = crtc->desired_mode->vdisplay;
-
-				if (crtc->desired_mode->hdisplay > surface_width)
-					surface_width = crtc->desired_mode->hdisplay;
-
-				if (crtc->desired_mode->vdisplay > surface_height)
-					surface_height = crtc->desired_mode->vdisplay;
-			}
-			crtc_count++;
-		}
-	}
-
-	if (crtc_count == 0 || fb_width == -1 || fb_height == -1) {
-		/* hmm everyone went away - assume VGA cable just fell out
-		   and will come back later. */
-		return 0;
-	}
-
-	/* do we have an fb already? */
-	if (list_empty(&rdev->ddev->mode_config.fb_kernel_list)) {
-		/* create an fb if we don't have one */
-		ret = radeonfb_create(rdev, fb_width, fb_height, surface_width, surface_height, &rfb);
-		if (ret) {
-			return -EINVAL;
-		}
-		new_fb = 1;
-	} else {
-		struct drm_framebuffer *fb;
-		fb = list_first_entry(&rdev->ddev->mode_config.fb_kernel_list, struct drm_framebuffer, filp_head);
-		rfb = to_radeon_framebuffer(fb);
-
-		/* if someone hotplugs something bigger than we have already allocated, we are pwned.
-		   As really we can't resize an fbdev that is in the wild currently due to fbdev
-		   not really being designed for the lower layers moving stuff around under it.
-		   - so in the grand style of things - punt. */
-		if ((fb->width < surface_width) || (fb->height < surface_height)) {
-			DRM_ERROR("Framebuffer not large enough to scale console onto.\n");
-			return -EINVAL;
-		}
-	}
-
-	info = rfb->base.fbdev;
-	rdev->fbdev_info = info;
-	rfbdev = info->par;
-
-	crtc_count = 0;
-	/* okay we need to setup new connector sets in the crtcs */
-	list_for_each_entry(crtc, &rdev->ddev->mode_config.crtc_list, head) {
-		struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
-		modeset = &radeon_crtc->mode_set;
-		modeset->fb = &rfb->base;
-		conn_count = 0;
-		list_for_each_entry(connector, &rdev->ddev->mode_config.connector_list, head) {
-			if (connector->encoder)
-				if (connector->encoder->crtc == modeset->crtc) {
-					modeset->connectors[conn_count] = connector;
-					conn_count++;
-					if (conn_count > RADEONFB_CONN_LIMIT)
-						BUG();
-				}
-		}
-
-		for (i = conn_count; i < RADEONFB_CONN_LIMIT; i++)
-			modeset->connectors[i] = NULL;
-
-
-		rfbdev->crtc_ids[crtc_count++] = crtc->base.id;
-
-		modeset->num_connectors = conn_count;
-		if (modeset->crtc->desired_mode) {
-			if (modeset->mode) {
-				drm_mode_destroy(rdev->ddev, modeset->mode);
-			}
-			modeset->mode = drm_mode_duplicate(rdev->ddev,
-							   modeset->crtc->desired_mode);
-		}
-	}
-	rfbdev->crtc_count = crtc_count;
-
-	if (new_fb) {
-		info->var.pixclock = -1;
-		if (register_framebuffer(info) < 0)
-			return -EINVAL;
-	} else {
-		radeonfb_set_par(info);
-	}
-	printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node,
-	       info->fix.id);
-
-	/* Switch back to kernel console on panic */
-	panic_mode = *modeset;
-	atomic_notifier_chain_register(&panic_notifier_list, &paniced);
-	printk(KERN_INFO "registered panic notifier\n");
-
-	return 0;
-}
-
 int radeonfb_probe(struct drm_device *dev)
 {
 	int ret;
-
-	/* something has changed in the lower levels of hell - deal with it
-	   here */
-
-	/* two modes : a) 1 fb to rule all crtcs.
-	               b) one fb per crtc.
-	   two actions 1) new connected device
-	               2) device removed.
-	   case a/1 : if the fb surface isn't big enough - resize the surface fb.
-	              if the fb size isn't big enough - resize fb into surface.
-		      if everything big enough configure the new crtc/etc.
-	   case a/2 : undo the configuration
-	              possibly resize down the fb to fit the new configuration.
-           case b/1 : see if it is on a new crtc - setup a new fb and add it.
-	   case b/2 : teardown the new fb.
-	*/
-	ret = radeonfb_single_fb_probe(dev->dev_private);
+	ret = drm_fb_helper_single_fb_probe(dev, &radeonfb_create);
 	return ret;
 }
 EXPORT_SYMBOL(radeonfb_probe);
@@ -880,16 +393,17 @@ int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb)
 	}
 	info = fb->fbdev;
 	if (info) {
+		struct radeon_fb_device *rfbdev = info->par;
 		robj = rfb->obj->driver_private;
 		unregister_framebuffer(info);
 		radeon_object_kunmap(robj);
 		radeon_object_unpin(robj);
+		drm_fb_helper_free(&rfbdev->helper);
 		framebuffer_release(info);
 	}
 
 	printk(KERN_INFO "unregistered panic notifier\n");
-	atomic_notifier_chain_unregister(&panic_notifier_list, &paniced);
-	memset(&panic_mode, 0, sizeof(struct drm_mode_set));
+
 	return 0;
 }
 EXPORT_SYMBOL(radeonfb_remove);
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 3b09a1f2d8f..20e9509a713 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -195,8 +195,6 @@ struct radeon_crtc {
 	bool enabled;
 	bool can_tile;
 	uint32_t crtc_offset;
-	struct radeon_framebuffer *fbdev_fb;
-	struct drm_mode_set mode_set;
 	struct drm_gem_object *cursor_bo;
 	uint64_t cursor_addr;
 	int cursor_width;
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index db92a83f8ca..b0427a70fcb 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -259,6 +259,8 @@ struct drm_framebuffer {
 	void *fbdev;
 	u32 pseudo_palette[17];
 	struct list_head filp_head;
+	/* if you are using the helper */
+	void *helper_private;
 };
 
 struct drm_property_blob {
diff --git a/include/drm/drm_fb_helper.h b/include/drm/drm_fb_helper.h
new file mode 100644
index 00000000000..88fffbdfa26
--- /dev/null
+++ b/include/drm/drm_fb_helper.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2006-2009 Red Hat Inc.
+ * Copyright (c) 2006-2008 Intel Corporation
+ * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
+ *
+ * DRM framebuffer helper functions
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission.  The copyright holders make no representations
+ * about the suitability of this software for any purpose.  It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ *
+ * Authors:
+ *      Dave Airlie <airlied@linux.ie>
+ *      Jesse Barnes <jesse.barnes@intel.com>
+ */
+#ifndef DRM_FB_HELPER_H
+#define DRM_FB_HELPER_H
+
+struct drm_fb_helper_crtc {
+	uint32_t crtc_id;
+	struct drm_mode_set mode_set;
+};
+
+struct drm_fb_helper_funcs {
+	void (*gamma_set)(struct drm_crtc *crtc, u16 red, u16 green,
+			  u16 blue, int regno);
+};
+
+struct drm_fb_helper {
+	struct drm_framebuffer *fb;
+	struct drm_device *dev;
+	struct drm_display_mode *mode;
+	int crtc_count;
+	struct drm_fb_helper_crtc *crtc_info;
+	struct drm_fb_helper_funcs *funcs;
+	int conn_limit;
+	struct list_head kernel_fb_list;
+};
+
+int drm_fb_helper_single_fb_probe(struct drm_device *dev,
+				  int (*fb_create)(struct drm_device *dev,
+						   uint32_t fb_width,
+						   uint32_t fb_height,
+						   uint32_t surface_width,
+						   uint32_t surface_height,
+						   struct drm_framebuffer **fb_ptr));
+int drm_fb_helper_init_crtc_count(struct drm_fb_helper *helper, int crtc_count,
+				  int max_conn);
+void drm_fb_helper_free(struct drm_fb_helper *helper);
+int drm_fb_helper_blank(int blank, struct fb_info *info);
+int drm_fb_helper_pan_display(struct fb_var_screeninfo *var,
+			      struct fb_info *info);
+int drm_fb_helper_set_par(struct fb_info *info);
+int drm_fb_helper_check_var(struct fb_var_screeninfo *var,
+			    struct fb_info *info);
+int drm_fb_helper_setcolreg(unsigned regno,
+			    unsigned red,
+			    unsigned green,
+			    unsigned blue,
+			    unsigned transp,
+			    struct fb_info *info);
+
+void drm_fb_helper_restore(void);
+void drm_fb_helper_fill_var(struct fb_info *info, struct drm_framebuffer *fb,
+			    uint32_t fb_width, uint32_t fb_height);
+void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch);
+
+#endif
-- 
cgit v1.2.3


From 882f0219518196a94cd2772004e87b178467139a Mon Sep 17 00:00:00 2001
From: Zhao Yakui <yakui.zhao@intel.com>
Date: Wed, 26 Aug 2009 18:20:49 +0800
Subject: drm/kms: Parse the detailed time info in CEA-EDID

Sometimes we can obtain the EDID with multiple blocks from the display device.
For example: HDMI monitor.
When the CEA-EDID block is detected, we should also parse the detailed timing
info from it. Otherwise we will lose some modes for the display device.

The first step is check whether the CEA EDID block is found. If it exists,
it will skip the CEA-data block and parse the detailed timing info.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_edid.c | 120 ++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 119 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index a1cab5de2f4..e4f1cb5fa60 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -60,6 +60,8 @@
 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED	(1 << 5)
 /* use +hsync +vsync for detailed mode */
 #define EDID_QUIRK_DETAILED_SYNC_PP		(1 << 6)
+/* define the number of Extension EDID block */
+#define MAX_EDID_EXT_NUM 4
 
 #define LEVEL_DMT	0
 #define LEVEL_GTF	1
@@ -597,6 +599,122 @@ static int add_detailed_info(struct drm_connector *connector,
 
 	return modes;
 }
+/**
+ * add_detailed_mode_eedid - get detailed mode info from addtional timing
+ * 			EDID block
+ * @connector: attached connector
+ * @edid: EDID block to scan(It is only to get addtional timing EDID block)
+ * @quirks: quirks to apply
+ *
+ * Some of the detailed timing sections may contain mode information.  Grab
+ * it and add it to the list.
+ */
+static int add_detailed_info_eedid(struct drm_connector *connector,
+			     struct edid *edid, u32 quirks)
+{
+	struct drm_device *dev = connector->dev;
+	int i, j, modes = 0;
+	char *edid_ext = NULL;
+	struct detailed_timing *timing;
+	struct detailed_non_pixel *data;
+	struct drm_display_mode *newmode;
+	int edid_ext_num;
+	int start_offset, end_offset;
+	int timing_level;
+
+	if (edid->version == 1 && edid->revision < 3) {
+		/* If the EDID version is less than 1.3, there is no
+		 * extension EDID.
+		 */
+		return 0;
+	}
+	if (!edid->extensions) {
+		/* if there is no extension EDID, it is unnecessary to
+		 * parse the E-EDID to get detailed info
+		 */
+		return 0;
+	}
+
+	/* Chose real EDID extension number */
+	edid_ext_num = edid->extensions > MAX_EDID_EXT_NUM ?
+		       MAX_EDID_EXT_NUM : edid->extensions;
+
+	/* Find CEA extension */
+	for (i = 0; i < edid_ext_num; i++) {
+		edid_ext = (char *)edid + EDID_LENGTH * (i + 1);
+		/* This block is CEA extension */
+		if (edid_ext[0] == 0x02)
+			break;
+	}
+
+	if (i == edid_ext_num) {
+		/* if there is no additional timing EDID block, return */
+		return 0;
+	}
+
+	/* Get the start offset of detailed timing block */
+	start_offset = edid_ext[2];
+	if (start_offset == 0) {
+		/* If the start_offset is zero, it means that neither detailed
+		 * info nor data block exist. In such case it is also
+		 * unnecessary to parse the detailed timing info.
+		 */
+		return 0;
+	}
+
+	timing_level = standard_timing_level(edid);
+	end_offset = EDID_LENGTH;
+	end_offset -= sizeof(struct detailed_timing);
+	for (i = start_offset; i < end_offset;
+			i += sizeof(struct detailed_timing)) {
+		timing = (struct detailed_timing *)(edid_ext + i);
+		data = &timing->data.other_data;
+		/* Detailed mode timing */
+		if (timing->pixel_clock) {
+			newmode = drm_mode_detailed(dev, edid, timing, quirks);
+			if (!newmode)
+				continue;
+
+			drm_mode_probed_add(connector, newmode);
+
+			modes++;
+			continue;
+		}
+
+		/* Other timing or info */
+		switch (data->type) {
+		case EDID_DETAIL_MONITOR_SERIAL:
+			break;
+		case EDID_DETAIL_MONITOR_STRING:
+			break;
+		case EDID_DETAIL_MONITOR_RANGE:
+			/* Get monitor range data */
+			break;
+		case EDID_DETAIL_MONITOR_NAME:
+			break;
+		case EDID_DETAIL_MONITOR_CPDATA:
+			break;
+		case EDID_DETAIL_STD_MODES:
+			/* Five modes per detailed section */
+			for (j = 0; j < 5; i++) {
+				struct std_timing *std;
+				struct drm_display_mode *newmode;
+
+				std = &data->data.timings[j];
+				newmode = drm_mode_std(dev, std, timing_level);
+				if (newmode) {
+					drm_mode_probed_add(connector, newmode);
+					modes++;
+				}
+			}
+			break;
+		default:
+			break;
+		}
+	}
+
+	return modes;
+}
 
 #define DDC_ADDR 0x50
 /**
@@ -656,7 +774,6 @@ end:
 	return ret;
 }
 
-#define MAX_EDID_EXT_NUM 4
 /**
  * drm_get_edid - get EDID data, if available
  * @connector: connector we're probing
@@ -809,6 +926,7 @@ int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
 	num_modes += add_established_modes(connector, edid);
 	num_modes += add_standard_modes(connector, edid);
 	num_modes += add_detailed_info(connector, edid, quirks);
+	num_modes += add_detailed_info_eedid(connector, edid, quirks);
 
 	if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
 		edid_fixup_preferred(connector, quirks);
-- 
cgit v1.2.3


From 3b51096f95633e6ab47675984e8e38fc37b09eeb Mon Sep 17 00:00:00 2001
From: Alexey Dobriyan <adobriyan@gmail.com>
Date: Fri, 28 Aug 2009 22:58:07 +0400
Subject: drm: use proc_create_data()

airlied: fixup race against drm info by filling out
tmp before adding it to proc.

Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_proc.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/drm_proc.c b/drivers/gpu/drm/drm_proc.c
index dc967af7a33..d379c4f2892 100644
--- a/drivers/gpu/drm/drm_proc.c
+++ b/drivers/gpu/drm/drm_proc.c
@@ -110,20 +110,21 @@ int drm_proc_create_files(struct drm_info_list *files, int count,
 			ret = -1;
 			goto fail;
 		}
-		ent = create_proc_entry(files[i].name, S_IFREG | S_IRUGO, root);
+		tmp->minor = minor;
+		tmp->info_ent = &files[i];
+		list_add(&tmp->list, &minor->proc_nodes.list);
+
+		ent = proc_create_data(files[i].name, S_IRUGO, root,
+				       &drm_proc_fops, tmp);
 		if (!ent) {
 			DRM_ERROR("Cannot create /proc/dri/%s/%s\n",
 				  name, files[i].name);
+			list_del(&tmp->list);
 			kfree(tmp);
 			ret = -1;
 			goto fail;
 		}
 
-		ent->proc_fops = &drm_proc_fops;
-		ent->data = tmp;
-		tmp->minor = minor;
-		tmp->info_ent = &files[i];
-		list_add(&(tmp->list), &(minor->proc_nodes.list));
 	}
 	return 0;
 
-- 
cgit v1.2.3


From 3420e74262a7d6496d0ac433d6f61c9972f015f6 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 31 Aug 2009 10:33:29 +1000
Subject: drm: fix two issues with fb consolidation.

Set accel to none, we really don't want anyone thinking
fb is an accel interface.
Pass pitch not depth to function for intel.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_fb_helper.c | 2 +-
 drivers/gpu/drm/i915/intel_fb.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index d6ffea74a50..41086e98059 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -616,7 +616,7 @@ void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch)
 	info->fix.xpanstep = 1; /* doing it in hw */
 	info->fix.ypanstep = 1; /* doing it in hw */
 	info->fix.ywrapstep = 0;
-	info->fix.accel = FB_ACCEL_I830;
+	info->fix.accel = FB_ACCEL_NONE;
 	info->fix.type_aux = 0;
 
 	info->fix.line_length = pitch;
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index 3041530c367..7ba4a232a97 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -205,7 +205,7 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width,
 
 //	memset(info->screen_base, 0, size);
 
-	drm_fb_helper_fill_fix(info, fb->depth);
+	drm_fb_helper_fill_fix(info, fb->pitch);
 	drm_fb_helper_fill_var(info, fb, fb_width, fb_height);
 
 	/* FIXME: we really shouldn't expose mmio space at all */
-- 
cgit v1.2.3


From fa8a123855e20068204982596b8fafceb1a67f0b Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Wed, 26 Aug 2009 13:13:37 +1000
Subject: drm/mm: add ability to dump mm lists via debugfs

This adds code to the drm_mm to talk to debugfs, and adds
support to radeon to add the VRAM and GTT mm lists to debugfs.

I tested with spinlock debugging and it doesn't give out.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_mm.c            | 21 ++++++++++++++
 drivers/gpu/drm/radeon/radeon_ttm.c | 56 +++++++++++++++++++++++++++++++++++++
 include/drm/drm_mm.h                |  4 +++
 3 files changed, 81 insertions(+)

diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c
index 3e47869d6da..c861d80fd77 100644
--- a/drivers/gpu/drm/drm_mm.c
+++ b/drivers/gpu/drm/drm_mm.c
@@ -44,6 +44,7 @@
 #include "drmP.h"
 #include "drm_mm.h"
 #include <linux/slab.h>
+#include <linux/seq_file.h>
 
 #define MM_UNUSED_TARGET 4
 
@@ -370,3 +371,23 @@ void drm_mm_takedown(struct drm_mm * mm)
 	BUG_ON(mm->num_unused != 0);
 }
 EXPORT_SYMBOL(drm_mm_takedown);
+
+#if defined(CONFIG_DEBUG_FS)
+int drm_mm_dump_table(struct seq_file *m, struct drm_mm *mm)
+{
+	struct drm_mm_node *entry;
+	int total_used = 0, total_free = 0, total = 0;
+
+	list_for_each_entry(entry, &mm->ml_entry, ml_entry) {
+		seq_printf(m, "0x%08lx-0x%08lx: 0x%08lx: %s\n", entry->start, entry->start + entry->size, entry->size, entry->free ? "free" : "used");
+		total += entry->size;
+		if (entry->free)
+			total_free += entry->size;
+		else
+			total_used += entry->size;
+	}
+	seq_printf(m, "total: %d, used %d free %d\n", total, total_free, total_used);
+	return 0;
+}
+EXPORT_SYMBOL(drm_mm_dump_table);
+#endif
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index 0a85e7b5d59..dc7a44274ea 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -35,11 +35,14 @@
 #include <ttm/ttm_module.h>
 #include <drm/drmP.h>
 #include <drm/radeon_drm.h>
+#include <linux/seq_file.h>
 #include "radeon_reg.h"
 #include "radeon.h"
 
 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
 
+static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
+
 static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
 {
 	struct radeon_mman *mman;
@@ -504,6 +507,12 @@ int radeon_ttm_init(struct radeon_device *rdev)
 	if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
 		rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
 	}
+
+	r = radeon_ttm_debugfs_init(rdev);
+	if (r) {
+		DRM_ERROR("Failed to init debugfs\n");
+		return r;
+	}
 	return 0;
 }
 
@@ -678,3 +687,50 @@ struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev)
 	gtt->bound = false;
 	return &gtt->backend;
 }
+
+#define RADEON_DEBUGFS_MEM_TYPES 2
+
+static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES];
+static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES][32];
+
+#if defined(CONFIG_DEBUG_FS)
+static int radeon_mm_dump_table(struct seq_file *m, void *data)
+{
+	struct drm_info_node *node = (struct drm_info_node *)m->private;
+	struct drm_mm *mm = (struct drm_mm *)node->info_ent->data;
+	struct drm_device *dev = node->minor->dev;
+	struct radeon_device *rdev = dev->dev_private;
+	int ret;
+	struct ttm_bo_global *glob = rdev->mman.bdev.glob;
+
+	spin_lock(&glob->lru_lock);
+	ret = drm_mm_dump_table(m, mm);
+	spin_unlock(&glob->lru_lock);
+	return ret;
+}
+#endif
+
+static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
+{
+	unsigned i;
+
+#if defined(CONFIG_DEBUG_FS)
+	for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) {
+		if (i == 0)
+			sprintf(radeon_mem_types_names[i], "radeon_vram_mm");
+		else
+			sprintf(radeon_mem_types_names[i], "radeon_gtt_mm");
+		radeon_mem_types_list[i].name = radeon_mem_types_names[i];
+		radeon_mem_types_list[i].show = &radeon_mm_dump_table;
+		radeon_mem_types_list[i].driver_features = 0;
+		if (i == 0)
+			radeon_mem_types_list[i].data = &rdev->mman.bdev.man[TTM_PL_VRAM].manager;
+		else
+			radeon_mem_types_list[i].data = &rdev->mman.bdev.man[TTM_PL_TT].manager;
+
+	}
+	return radeon_debugfs_add_files(rdev, radeon_mem_types_list, RADEON_DEBUGFS_MEM_TYPES);
+
+#endif
+	return 0;
+}
diff --git a/include/drm/drm_mm.h b/include/drm/drm_mm.h
index f8332073d27..bc5a87e8aee 100644
--- a/include/drm/drm_mm.h
+++ b/include/drm/drm_mm.h
@@ -96,4 +96,8 @@ static inline struct drm_mm *drm_get_mm(struct drm_mm_node *block)
 	return block->mm;
 }
 
+#ifdef CONFIG_DEBUG_FS
+int drm_mm_dump_table(struct seq_file *m, struct drm_mm *mm);
+#endif
+
 #endif
-- 
cgit v1.2.3


From ed017d9fb17af3162f5acf922eb5731c541e1f3a Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Wed, 2 Sep 2009 09:41:13 +1000
Subject: drm: fix drm_cache.c for arch with no support.

This produces a warn on for architectures where this gets called
but we don't have a cache flushing implementation suitable.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_cache.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
index 3a5575e638d..0e3bd5b54b7 100644
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu/drm/drm_cache.c
@@ -62,11 +62,8 @@ drm_clflush_ipi_handler(void *null)
 {
 	wbinvd();
 }
-#elif !defined(__powerpc__)
-static void drm_cache_ipi_handler(void *dummy)
-{
-}
 #endif
+
 void
 drm_clflush_pages(struct page *pages[], unsigned long num_pages)
 {
@@ -95,8 +92,8 @@ drm_clflush_pages(struct page *pages[], unsigned long num_pages)
 		kunmap_atomic(page_virtual, KM_USER0);
 	}
 #else
-	if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0)
-		printk(KERN_ERR "Timed out waiting for drm cache flush\n");
+	printk(KERN_ERR "Architecture has no drm_cache.c support\n");
+	WARN_ON_ONCE(1);
 #endif
 }
 EXPORT_SYMBOL(drm_clflush_pages);
-- 
cgit v1.2.3


From a3a0544b2c84e1d7a2022b558ecf66d8c6a8dd93 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 31 Aug 2009 15:16:30 +1000
Subject: drm/kms: add explicit encoder disable function and detach harder.

For shared tv-out and VGA encoders, we really need to know if
the encoder is just being switched off temporarily in blanking
or if we are really disabling it hard.

Also we need to try harder to disconnect encoders from unused
connectors so we can share more efficently.

(shared encoders stuff is coming in radeon tv-out support)

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_crtc_helper.c | 24 ++++++++++++++++++++----
 include/drm/drm_crtc_helper.h     |  2 ++
 2 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index 205349ea107..eea5e6c4099 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -260,13 +260,27 @@ EXPORT_SYMBOL(drm_helper_crtc_in_use);
 void drm_helper_disable_unused_functions(struct drm_device *dev)
 {
 	struct drm_encoder *encoder;
+	struct drm_connector *connector;
 	struct drm_encoder_helper_funcs *encoder_funcs;
 	struct drm_crtc *crtc;
 
+	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+		if (!connector->encoder)
+			continue;
+		if (connector->status == connector_status_disconnected)
+			connector->encoder = NULL;
+	}
+
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 		encoder_funcs = encoder->helper_private;
-		if (!drm_helper_encoder_in_use(encoder))
-			(*encoder_funcs->dpms)(encoder, DRM_MODE_DPMS_OFF);
+		if (!drm_helper_encoder_in_use(encoder)) {
+			if (encoder_funcs->disable)
+				(*encoder_funcs->disable)(encoder);
+			else
+				(*encoder_funcs->dpms)(encoder, DRM_MODE_DPMS_OFF);
+		}
+		/* disconnector encoder from any connector */
+		encoder->crtc = NULL;
 	}
 
 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
@@ -411,7 +425,7 @@ static int drm_pick_crtcs(struct drm_device *dev,
 	c = 0;
 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 
-		if ((connector->encoder->possible_crtcs & (1 << c)) == 0) {
+		if ((encoder->possible_crtcs & (1 << c)) == 0) {
 			c++;
 			continue;
 		}
@@ -496,8 +510,10 @@ static void drm_setup_crtcs(struct drm_device *dev)
 				  mode->name, crtc->base.id);
 			crtc->desired_mode = mode;
 			connector->encoder->crtc = crtc;
-		} else
+		} else {
 			connector->encoder->crtc = NULL;
+			connector->encoder = NULL;
+		}
 		i++;
 	}
 
diff --git a/include/drm/drm_crtc_helper.h b/include/drm/drm_crtc_helper.h
index e44a4f87303..4c8dacaf4f5 100644
--- a/include/drm/drm_crtc_helper.h
+++ b/include/drm/drm_crtc_helper.h
@@ -79,6 +79,8 @@ struct drm_encoder_helper_funcs {
 	/* detect for DAC style encoders */
 	enum drm_connector_status (*detect)(struct drm_encoder *encoder,
 					    struct drm_connector *connector);
+	/* disable encoder when not in use - more explicit than dpms off */
+	void (*disable)(struct drm_encoder *encoder);
 };
 
 struct drm_connector_helper_funcs {
-- 
cgit v1.2.3


From 9c552dd79346f86a3b53e41255c92c6f560b80fb Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Wed, 2 Sep 2009 14:00:11 +1000
Subject: drm/crtc: fix mismerge of last patch.

We only want to NULL encoder->crtc when it is off.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_crtc_helper.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index eea5e6c4099..db0237dec6c 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -278,9 +278,9 @@ void drm_helper_disable_unused_functions(struct drm_device *dev)
 				(*encoder_funcs->disable)(encoder);
 			else
 				(*encoder_funcs->dpms)(encoder, DRM_MODE_DPMS_OFF);
+			/* disconnector encoder from any connector */
+			encoder->crtc = NULL;
 		}
-		/* disconnector encoder from any connector */
-		encoder->crtc = NULL;
 	}
 
 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-- 
cgit v1.2.3


From ff6fdbed8f465f796da7ab32cde67e2dfb9e1f8f Mon Sep 17 00:00:00 2001
From: Maarten Maathuis <madman2003@gmail.com>
Date: Tue, 1 Sep 2009 03:39:04 +0200
Subject: drm/crtc_helper: avoid NULL-pointer dereference when encoder is NULL

Signed-off-by: Maarten Maathuis <madman2003@gmail.com>
Signed-off-by: Dave Airlie <airlied@linux.ie>
---
 drivers/gpu/drm/drm_crtc_helper.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index db0237dec6c..e7e6c25b560 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -842,7 +842,8 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
 			/* If the encoder is reused for another connector, then
 			 * the appropriate crtc will be set later.
 			 */
-			connector->encoder->crtc = NULL;
+			if (connector->encoder)
+				connector->encoder->crtc = NULL;
 			connector->encoder = new_encoder;
 		}
 	}
-- 
cgit v1.2.3


From 27c202ad7f141d4efa9c64e30bf4a4d3bcd799ae Mon Sep 17 00:00:00 2001
From: Ben Gamari <bgamari.foss@gmail.com>
Date: Wed, 1 Jul 2009 22:26:52 -0400
Subject: drm/i915: Move i915_gem_debugfs.c to i915_debugfs.c

Signed-off-by: Ben Gamari <bgamari.foss@gmail.com>
[anholt: hand-applied for conflicts]
Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/Makefile           |   2 +-
 drivers/gpu/drm/i915/i915_debugfs.c     | 396 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.c         |   4 +-
 drivers/gpu/drm/i915/i915_drv.h         |   4 +-
 drivers/gpu/drm/i915/i915_gem_debugfs.c | 396 --------------------------------
 5 files changed, 401 insertions(+), 401 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_debugfs.c
 delete mode 100644 drivers/gpu/drm/i915/i915_gem_debugfs.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 30d6b99fb30..5269dfa5f62 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -4,10 +4,10 @@
 
 ccflags-y := -Iinclude/drm
 i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \
+	  i915_debugfs.o \
           i915_suspend.o \
 	  i915_gem.o \
 	  i915_gem_debug.o \
-	  i915_gem_debugfs.o \
 	  i915_gem_tiling.o \
 	  intel_display.o \
 	  intel_crt.o \
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
new file mode 100644
index 00000000000..b4f2d6bce15
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -0,0 +1,396 @@
+/*
+ * Copyright © 2008 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Eric Anholt <eric@anholt.net>
+ *    Keith Packard <keithp@keithp.com>
+ *
+ */
+
+#include <linux/seq_file.h>
+#include "drmP.h"
+#include "drm.h"
+#include "i915_drm.h"
+#include "i915_drv.h"
+
+#define DRM_I915_RING_DEBUG 1
+
+
+#if defined(CONFIG_DEBUG_FS)
+
+#define ACTIVE_LIST	1
+#define FLUSHING_LIST	2
+#define INACTIVE_LIST	3
+
+static const char *get_pin_flag(struct drm_i915_gem_object *obj_priv)
+{
+	if (obj_priv->user_pin_count > 0)
+		return "P";
+	else if (obj_priv->pin_count > 0)
+		return "p";
+	else
+		return " ";
+}
+
+static const char *get_tiling_flag(struct drm_i915_gem_object *obj_priv)
+{
+    switch (obj_priv->tiling_mode) {
+    default:
+    case I915_TILING_NONE: return " ";
+    case I915_TILING_X: return "X";
+    case I915_TILING_Y: return "Y";
+    }
+}
+
+static int i915_gem_object_list_info(struct seq_file *m, void *data)
+{
+	struct drm_info_node *node = (struct drm_info_node *) m->private;
+	uintptr_t list = (uintptr_t) node->info_ent->data;
+	struct list_head *head;
+	struct drm_device *dev = node->minor->dev;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	struct drm_i915_gem_object *obj_priv;
+	spinlock_t *lock = NULL;
+
+	switch (list) {
+	case ACTIVE_LIST:
+		seq_printf(m, "Active:\n");
+		lock = &dev_priv->mm.active_list_lock;
+		head = &dev_priv->mm.active_list;
+		break;
+	case INACTIVE_LIST:
+		seq_printf(m, "Inactive:\n");
+		head = &dev_priv->mm.inactive_list;
+		break;
+	case FLUSHING_LIST:
+		seq_printf(m, "Flushing:\n");
+		head = &dev_priv->mm.flushing_list;
+		break;
+	default:
+		DRM_INFO("Ooops, unexpected list\n");
+		return 0;
+	}
+
+	if (lock)
+		spin_lock(lock);
+	list_for_each_entry(obj_priv, head, list)
+	{
+		struct drm_gem_object *obj = obj_priv->obj;
+
+		seq_printf(m, "    %p: %s %08x %08x %d",
+			   obj,
+			   get_pin_flag(obj_priv),
+			   obj->read_domains, obj->write_domain,
+			   obj_priv->last_rendering_seqno);
+
+		if (obj->name)
+			seq_printf(m, " (name: %d)", obj->name);
+		if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
+			seq_printf(m, " (fence: %d)", obj_priv->fence_reg);
+		if (obj_priv->gtt_space != NULL)
+			seq_printf(m, " (gtt_offset: %08x)", obj_priv->gtt_offset);
+
+		seq_printf(m, "\n");
+	}
+
+	if (lock)
+	    spin_unlock(lock);
+	return 0;
+}
+
+static int i915_gem_request_info(struct seq_file *m, void *data)
+{
+	struct drm_info_node *node = (struct drm_info_node *) m->private;
+	struct drm_device *dev = node->minor->dev;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	struct drm_i915_gem_request *gem_request;
+
+	seq_printf(m, "Request:\n");
+	list_for_each_entry(gem_request, &dev_priv->mm.request_list, list) {
+		seq_printf(m, "    %d @ %d\n",
+			   gem_request->seqno,
+			   (int) (jiffies - gem_request->emitted_jiffies));
+	}
+	return 0;
+}
+
+static int i915_gem_seqno_info(struct seq_file *m, void *data)
+{
+	struct drm_info_node *node = (struct drm_info_node *) m->private;
+	struct drm_device *dev = node->minor->dev;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+
+	if (dev_priv->hw_status_page != NULL) {
+		seq_printf(m, "Current sequence: %d\n",
+			   i915_get_gem_seqno(dev));
+	} else {
+		seq_printf(m, "Current sequence: hws uninitialized\n");
+	}
+	seq_printf(m, "Waiter sequence:  %d\n",
+			dev_priv->mm.waiting_gem_seqno);
+	seq_printf(m, "IRQ sequence:     %d\n", dev_priv->mm.irq_gem_seqno);
+	return 0;
+}
+
+
+static int i915_interrupt_info(struct seq_file *m, void *data)
+{
+	struct drm_info_node *node = (struct drm_info_node *) m->private;
+	struct drm_device *dev = node->minor->dev;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+
+	seq_printf(m, "Interrupt enable:    %08x\n",
+		   I915_READ(IER));
+	seq_printf(m, "Interrupt identity:  %08x\n",
+		   I915_READ(IIR));
+	seq_printf(m, "Interrupt mask:      %08x\n",
+		   I915_READ(IMR));
+	seq_printf(m, "Pipe A stat:         %08x\n",
+		   I915_READ(PIPEASTAT));
+	seq_printf(m, "Pipe B stat:         %08x\n",
+		   I915_READ(PIPEBSTAT));
+	seq_printf(m, "Interrupts received: %d\n",
+		   atomic_read(&dev_priv->irq_received));
+	if (dev_priv->hw_status_page != NULL) {
+		seq_printf(m, "Current sequence:    %d\n",
+			   i915_get_gem_seqno(dev));
+	} else {
+		seq_printf(m, "Current sequence:    hws uninitialized\n");
+	}
+	seq_printf(m, "Waiter sequence:     %d\n",
+		   dev_priv->mm.waiting_gem_seqno);
+	seq_printf(m, "IRQ sequence:        %d\n",
+		   dev_priv->mm.irq_gem_seqno);
+	return 0;
+}
+
+static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
+{
+	struct drm_info_node *node = (struct drm_info_node *) m->private;
+	struct drm_device *dev = node->minor->dev;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	int i;
+
+	seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
+	seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
+	for (i = 0; i < dev_priv->num_fence_regs; i++) {
+		struct drm_gem_object *obj = dev_priv->fence_regs[i].obj;
+
+		if (obj == NULL) {
+			seq_printf(m, "Fenced object[%2d] = unused\n", i);
+		} else {
+			struct drm_i915_gem_object *obj_priv;
+
+			obj_priv = obj->driver_private;
+			seq_printf(m, "Fenced object[%2d] = %p: %s "
+				   "%08x %08zx %08x %s %08x %08x %d",
+				   i, obj, get_pin_flag(obj_priv),
+				   obj_priv->gtt_offset,
+				   obj->size, obj_priv->stride,
+				   get_tiling_flag(obj_priv),
+				   obj->read_domains, obj->write_domain,
+				   obj_priv->last_rendering_seqno);
+			if (obj->name)
+				seq_printf(m, " (name: %d)", obj->name);
+			seq_printf(m, "\n");
+		}
+	}
+
+	return 0;
+}
+
+static int i915_hws_info(struct seq_file *m, void *data)
+{
+	struct drm_info_node *node = (struct drm_info_node *) m->private;
+	struct drm_device *dev = node->minor->dev;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	int i;
+	volatile u32 *hws;
+
+	hws = (volatile u32 *)dev_priv->hw_status_page;
+	if (hws == NULL)
+		return 0;
+
+	for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
+		seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
+			   i * 4,
+			   hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
+	}
+	return 0;
+}
+
+static void i915_dump_pages(struct seq_file *m, struct page **pages, int page_count)
+{
+	int page, i;
+	uint32_t *mem;
+
+	for (page = 0; page < page_count; page++) {
+		mem = kmap(pages[page]);
+		for (i = 0; i < PAGE_SIZE; i += 4)
+			seq_printf(m, "%08x :  %08x\n", i, mem[i / 4]);
+		kunmap(pages[page]);
+	}
+}
+
+static int i915_batchbuffer_info(struct seq_file *m, void *data)
+{
+	struct drm_info_node *node = (struct drm_info_node *) m->private;
+	struct drm_device *dev = node->minor->dev;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	struct drm_gem_object *obj;
+	struct drm_i915_gem_object *obj_priv;
+	int ret;
+
+	spin_lock(&dev_priv->mm.active_list_lock);
+
+	list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
+		obj = obj_priv->obj;
+		if (obj->read_domains & I915_GEM_DOMAIN_COMMAND) {
+		    ret = i915_gem_object_get_pages(obj);
+		    if (ret) {
+			    DRM_ERROR("Failed to get pages: %d\n", ret);
+			    spin_unlock(&dev_priv->mm.active_list_lock);
+			    return ret;
+		    }
+
+		    seq_printf(m, "--- gtt_offset = 0x%08x\n", obj_priv->gtt_offset);
+		    i915_dump_pages(m, obj_priv->pages, obj->size / PAGE_SIZE);
+
+		    i915_gem_object_put_pages(obj);
+		}
+	}
+
+	spin_unlock(&dev_priv->mm.active_list_lock);
+
+	return 0;
+}
+
+static int i915_ringbuffer_data(struct seq_file *m, void *data)
+{
+	struct drm_info_node *node = (struct drm_info_node *) m->private;
+	struct drm_device *dev = node->minor->dev;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	u8 *virt;
+	uint32_t *ptr, off;
+
+	if (!dev_priv->ring.ring_obj) {
+		seq_printf(m, "No ringbuffer setup\n");
+		return 0;
+	}
+
+	virt = dev_priv->ring.virtual_start;
+
+	for (off = 0; off < dev_priv->ring.Size; off += 4) {
+		ptr = (uint32_t *)(virt + off);
+		seq_printf(m, "%08x :  %08x\n", off, *ptr);
+	}
+
+	return 0;
+}
+
+static int i915_ringbuffer_info(struct seq_file *m, void *data)
+{
+	struct drm_info_node *node = (struct drm_info_node *) m->private;
+	struct drm_device *dev = node->minor->dev;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	unsigned int head, tail, mask;
+
+	head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
+	tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
+	mask = dev_priv->ring.tail_mask;
+
+	seq_printf(m, "RingHead :  %08x\n", head);
+	seq_printf(m, "RingTail :  %08x\n", tail);
+	seq_printf(m, "RingMask :  %08x\n", mask);
+	seq_printf(m, "RingSize :  %08lx\n", dev_priv->ring.Size);
+	seq_printf(m, "Acthd :     %08x\n", I915_READ(IS_I965G(dev) ? ACTHD_I965 : ACTHD));
+
+	return 0;
+}
+
+static int i915_error_state(struct seq_file *m, void *unused)
+{
+	struct drm_info_node *node = (struct drm_info_node *) m->private;
+	struct drm_device *dev = node->minor->dev;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	struct drm_i915_error_state *error;
+	unsigned long flags;
+
+	spin_lock_irqsave(&dev_priv->error_lock, flags);
+	if (!dev_priv->first_error) {
+		seq_printf(m, "no error state collected\n");
+		goto out;
+	}
+
+	error = dev_priv->first_error;
+
+	seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
+		   error->time.tv_usec);
+	seq_printf(m, "EIR: 0x%08x\n", error->eir);
+	seq_printf(m, "  PGTBL_ER: 0x%08x\n", error->pgtbl_er);
+	seq_printf(m, "  INSTPM: 0x%08x\n", error->instpm);
+	seq_printf(m, "  IPEIR: 0x%08x\n", error->ipeir);
+	seq_printf(m, "  IPEHR: 0x%08x\n", error->ipehr);
+	seq_printf(m, "  INSTDONE: 0x%08x\n", error->instdone);
+	seq_printf(m, "  ACTHD: 0x%08x\n", error->acthd);
+	if (IS_I965G(dev)) {
+		seq_printf(m, "  INSTPS: 0x%08x\n", error->instps);
+		seq_printf(m, "  INSTDONE1: 0x%08x\n", error->instdone1);
+	}
+
+out:
+	spin_unlock_irqrestore(&dev_priv->error_lock, flags);
+
+	return 0;
+}
+
+static struct drm_info_list i915_debugfs_list[] = {
+	{"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
+	{"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
+	{"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
+	{"i915_gem_request", i915_gem_request_info, 0},
+	{"i915_gem_seqno", i915_gem_seqno_info, 0},
+	{"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
+	{"i915_gem_interrupt", i915_interrupt_info, 0},
+	{"i915_gem_hws", i915_hws_info, 0},
+	{"i915_ringbuffer_data", i915_ringbuffer_data, 0},
+	{"i915_ringbuffer_info", i915_ringbuffer_info, 0},
+	{"i915_batchbuffers", i915_batchbuffer_info, 0},
+	{"i915_error_state", i915_error_state, 0},
+};
+#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
+
+int i915_debugfs_init(struct drm_minor *minor)
+{
+	return drm_debugfs_create_files(i915_debugfs_list,
+					I915_DEBUGFS_ENTRIES,
+					minor->debugfs_root, minor);
+}
+
+void i915_debugfs_cleanup(struct drm_minor *minor)
+{
+	drm_debugfs_remove_files(i915_debugfs_list,
+				 I915_DEBUGFS_ENTRIES, minor);
+}
+
+#endif /* CONFIG_DEBUG_FS */
+
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index fc4b68aa2d0..263636e77e6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -188,8 +188,8 @@ static struct drm_driver driver = {
 	.master_create = i915_master_create,
 	.master_destroy = i915_master_destroy,
 #if defined(CONFIG_DEBUG_FS)
-	.debugfs_init = i915_gem_debugfs_init,
-	.debugfs_cleanup = i915_gem_debugfs_cleanup,
+	.debugfs_init = i915_debugfs_init,
+	.debugfs_cleanup = i915_debugfs_cleanup,
 #endif
 	.gem_init_object = i915_gem_init_object,
 	.gem_free_object = i915_gem_free_object,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5b4f87e5562..e286f4e13bd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -730,8 +730,8 @@ void i915_gem_dump_object(struct drm_gem_object *obj, int len,
 void i915_dump_lru(struct drm_device *dev, const char *where);
 
 /* i915_debugfs.c */
-int i915_gem_debugfs_init(struct drm_minor *minor);
-void i915_gem_debugfs_cleanup(struct drm_minor *minor);
+int i915_debugfs_init(struct drm_minor *minor);
+void i915_debugfs_cleanup(struct drm_minor *minor);
 
 /* i915_suspend.c */
 extern int i915_save_state(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_gem_debugfs.c b/drivers/gpu/drm/i915/i915_gem_debugfs.c
deleted file mode 100644
index cb3b97405fb..00000000000
--- a/drivers/gpu/drm/i915/i915_gem_debugfs.c
+++ /dev/null
@@ -1,396 +0,0 @@
-/*
- * Copyright © 2008 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- *    Eric Anholt <eric@anholt.net>
- *    Keith Packard <keithp@keithp.com>
- *
- */
-
-#include <linux/seq_file.h>
-#include "drmP.h"
-#include "drm.h"
-#include "i915_drm.h"
-#include "i915_drv.h"
-
-#define DRM_I915_RING_DEBUG 1
-
-
-#if defined(CONFIG_DEBUG_FS)
-
-#define ACTIVE_LIST	1
-#define FLUSHING_LIST	2
-#define INACTIVE_LIST	3
-
-static const char *get_pin_flag(struct drm_i915_gem_object *obj_priv)
-{
-	if (obj_priv->user_pin_count > 0)
-		return "P";
-	else if (obj_priv->pin_count > 0)
-		return "p";
-	else
-		return " ";
-}
-
-static const char *get_tiling_flag(struct drm_i915_gem_object *obj_priv)
-{
-    switch (obj_priv->tiling_mode) {
-    default:
-    case I915_TILING_NONE: return " ";
-    case I915_TILING_X: return "X";
-    case I915_TILING_Y: return "Y";
-    }
-}
-
-static int i915_gem_object_list_info(struct seq_file *m, void *data)
-{
-	struct drm_info_node *node = (struct drm_info_node *) m->private;
-	uintptr_t list = (uintptr_t) node->info_ent->data;
-	struct list_head *head;
-	struct drm_device *dev = node->minor->dev;
-	drm_i915_private_t *dev_priv = dev->dev_private;
-	struct drm_i915_gem_object *obj_priv;
-	spinlock_t *lock = NULL;
-
-	switch (list) {
-	case ACTIVE_LIST:
-		seq_printf(m, "Active:\n");
-		lock = &dev_priv->mm.active_list_lock;
-		head = &dev_priv->mm.active_list;
-		break;
-	case INACTIVE_LIST:
-		seq_printf(m, "Inactive:\n");
-		head = &dev_priv->mm.inactive_list;
-		break;
-	case FLUSHING_LIST:
-		seq_printf(m, "Flushing:\n");
-		head = &dev_priv->mm.flushing_list;
-		break;
-	default:
-		DRM_INFO("Ooops, unexpected list\n");
-		return 0;
-	}
-
-	if (lock)
-		spin_lock(lock);
-	list_for_each_entry(obj_priv, head, list)
-	{
-		struct drm_gem_object *obj = obj_priv->obj;
-
-		seq_printf(m, "    %p: %s %08x %08x %d",
-			   obj,
-			   get_pin_flag(obj_priv),
-			   obj->read_domains, obj->write_domain,
-			   obj_priv->last_rendering_seqno);
-
-		if (obj->name)
-			seq_printf(m, " (name: %d)", obj->name);
-		if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
-			seq_printf(m, " (fence: %d)", obj_priv->fence_reg);
-		if (obj_priv->gtt_space != NULL)
-			seq_printf(m, " (gtt_offset: %08x)", obj_priv->gtt_offset);
-
-		seq_printf(m, "\n");
-	}
-
-	if (lock)
-	    spin_unlock(lock);
-	return 0;
-}
-
-static int i915_gem_request_info(struct seq_file *m, void *data)
-{
-	struct drm_info_node *node = (struct drm_info_node *) m->private;
-	struct drm_device *dev = node->minor->dev;
-	drm_i915_private_t *dev_priv = dev->dev_private;
-	struct drm_i915_gem_request *gem_request;
-
-	seq_printf(m, "Request:\n");
-	list_for_each_entry(gem_request, &dev_priv->mm.request_list, list) {
-		seq_printf(m, "    %d @ %d\n",
-			   gem_request->seqno,
-			   (int) (jiffies - gem_request->emitted_jiffies));
-	}
-	return 0;
-}
-
-static int i915_gem_seqno_info(struct seq_file *m, void *data)
-{
-	struct drm_info_node *node = (struct drm_info_node *) m->private;
-	struct drm_device *dev = node->minor->dev;
-	drm_i915_private_t *dev_priv = dev->dev_private;
-
-	if (dev_priv->hw_status_page != NULL) {
-		seq_printf(m, "Current sequence: %d\n",
-			   i915_get_gem_seqno(dev));
-	} else {
-		seq_printf(m, "Current sequence: hws uninitialized\n");
-	}
-	seq_printf(m, "Waiter sequence:  %d\n",
-			dev_priv->mm.waiting_gem_seqno);
-	seq_printf(m, "IRQ sequence:     %d\n", dev_priv->mm.irq_gem_seqno);
-	return 0;
-}
-
-
-static int i915_interrupt_info(struct seq_file *m, void *data)
-{
-	struct drm_info_node *node = (struct drm_info_node *) m->private;
-	struct drm_device *dev = node->minor->dev;
-	drm_i915_private_t *dev_priv = dev->dev_private;
-
-	seq_printf(m, "Interrupt enable:    %08x\n",
-		   I915_READ(IER));
-	seq_printf(m, "Interrupt identity:  %08x\n",
-		   I915_READ(IIR));
-	seq_printf(m, "Interrupt mask:      %08x\n",
-		   I915_READ(IMR));
-	seq_printf(m, "Pipe A stat:         %08x\n",
-		   I915_READ(PIPEASTAT));
-	seq_printf(m, "Pipe B stat:         %08x\n",
-		   I915_READ(PIPEBSTAT));
-	seq_printf(m, "Interrupts received: %d\n",
-		   atomic_read(&dev_priv->irq_received));
-	if (dev_priv->hw_status_page != NULL) {
-		seq_printf(m, "Current sequence:    %d\n",
-			   i915_get_gem_seqno(dev));
-	} else {
-		seq_printf(m, "Current sequence:    hws uninitialized\n");
-	}
-	seq_printf(m, "Waiter sequence:     %d\n",
-		   dev_priv->mm.waiting_gem_seqno);
-	seq_printf(m, "IRQ sequence:        %d\n",
-		   dev_priv->mm.irq_gem_seqno);
-	return 0;
-}
-
-static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
-{
-	struct drm_info_node *node = (struct drm_info_node *) m->private;
-	struct drm_device *dev = node->minor->dev;
-	drm_i915_private_t *dev_priv = dev->dev_private;
-	int i;
-
-	seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
-	seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
-	for (i = 0; i < dev_priv->num_fence_regs; i++) {
-		struct drm_gem_object *obj = dev_priv->fence_regs[i].obj;
-
-		if (obj == NULL) {
-			seq_printf(m, "Fenced object[%2d] = unused\n", i);
-		} else {
-			struct drm_i915_gem_object *obj_priv;
-
-			obj_priv = obj->driver_private;
-			seq_printf(m, "Fenced object[%2d] = %p: %s "
-				   "%08x %08zx %08x %s %08x %08x %d",
-				   i, obj, get_pin_flag(obj_priv),
-				   obj_priv->gtt_offset,
-				   obj->size, obj_priv->stride,
-				   get_tiling_flag(obj_priv),
-				   obj->read_domains, obj->write_domain,
-				   obj_priv->last_rendering_seqno);
-			if (obj->name)
-				seq_printf(m, " (name: %d)", obj->name);
-			seq_printf(m, "\n");
-		}
-	}
-
-	return 0;
-}
-
-static int i915_hws_info(struct seq_file *m, void *data)
-{
-	struct drm_info_node *node = (struct drm_info_node *) m->private;
-	struct drm_device *dev = node->minor->dev;
-	drm_i915_private_t *dev_priv = dev->dev_private;
-	int i;
-	volatile u32 *hws;
-
-	hws = (volatile u32 *)dev_priv->hw_status_page;
-	if (hws == NULL)
-		return 0;
-
-	for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
-		seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
-			   i * 4,
-			   hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
-	}
-	return 0;
-}
-
-static void i915_dump_pages(struct seq_file *m, struct page **pages, int page_count)
-{
-	int page, i;
-	uint32_t *mem;
-
-	for (page = 0; page < page_count; page++) {
-		mem = kmap(pages[page]);
-		for (i = 0; i < PAGE_SIZE; i += 4)
-			seq_printf(m, "%08x :  %08x\n", i, mem[i / 4]);
-		kunmap(pages[page]);
-	}
-}
-
-static int i915_batchbuffer_info(struct seq_file *m, void *data)
-{
-	struct drm_info_node *node = (struct drm_info_node *) m->private;
-	struct drm_device *dev = node->minor->dev;
-	drm_i915_private_t *dev_priv = dev->dev_private;
-	struct drm_gem_object *obj;
-	struct drm_i915_gem_object *obj_priv;
-	int ret;
-
-	spin_lock(&dev_priv->mm.active_list_lock);
-
-	list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
-		obj = obj_priv->obj;
-		if (obj->read_domains & I915_GEM_DOMAIN_COMMAND) {
-		    ret = i915_gem_object_get_pages(obj);
-		    if (ret) {
-			    DRM_ERROR("Failed to get pages: %d\n", ret);
-			    spin_unlock(&dev_priv->mm.active_list_lock);
-			    return ret;
-		    }
-
-		    seq_printf(m, "--- gtt_offset = 0x%08x\n", obj_priv->gtt_offset);
-		    i915_dump_pages(m, obj_priv->pages, obj->size / PAGE_SIZE);
-
-		    i915_gem_object_put_pages(obj);
-		}
-	}
-
-	spin_unlock(&dev_priv->mm.active_list_lock);
-
-	return 0;
-}
-
-static int i915_ringbuffer_data(struct seq_file *m, void *data)
-{
-	struct drm_info_node *node = (struct drm_info_node *) m->private;
-	struct drm_device *dev = node->minor->dev;
-	drm_i915_private_t *dev_priv = dev->dev_private;
-	u8 *virt;
-	uint32_t *ptr, off;
-
-	if (!dev_priv->ring.ring_obj) {
-		seq_printf(m, "No ringbuffer setup\n");
-		return 0;
-	}
-
-	virt = dev_priv->ring.virtual_start;
-
-	for (off = 0; off < dev_priv->ring.Size; off += 4) {
-		ptr = (uint32_t *)(virt + off);
-		seq_printf(m, "%08x :  %08x\n", off, *ptr);
-	}
-
-	return 0;
-}
-
-static int i915_ringbuffer_info(struct seq_file *m, void *data)
-{
-	struct drm_info_node *node = (struct drm_info_node *) m->private;
-	struct drm_device *dev = node->minor->dev;
-	drm_i915_private_t *dev_priv = dev->dev_private;
-	unsigned int head, tail, mask;
-
-	head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
-	tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
-	mask = dev_priv->ring.tail_mask;
-
-	seq_printf(m, "RingHead :  %08x\n", head);
-	seq_printf(m, "RingTail :  %08x\n", tail);
-	seq_printf(m, "RingMask :  %08x\n", mask);
-	seq_printf(m, "RingSize :  %08lx\n", dev_priv->ring.Size);
-	seq_printf(m, "Acthd :     %08x\n", I915_READ(IS_I965G(dev) ? ACTHD_I965 : ACTHD));
-
-	return 0;
-}
-
-static int i915_error_state(struct seq_file *m, void *unused)
-{
-	struct drm_info_node *node = (struct drm_info_node *) m->private;
-	struct drm_device *dev = node->minor->dev;
-	drm_i915_private_t *dev_priv = dev->dev_private;
-	struct drm_i915_error_state *error;
-	unsigned long flags;
-
-	spin_lock_irqsave(&dev_priv->error_lock, flags);
-	if (!dev_priv->first_error) {
-		seq_printf(m, "no error state collected\n");
-		goto out;
-	}
-
-	error = dev_priv->first_error;
-
-	seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
-		   error->time.tv_usec);
-	seq_printf(m, "EIR: 0x%08x\n", error->eir);
-	seq_printf(m, "  PGTBL_ER: 0x%08x\n", error->pgtbl_er);
-	seq_printf(m, "  INSTPM: 0x%08x\n", error->instpm);
-	seq_printf(m, "  IPEIR: 0x%08x\n", error->ipeir);
-	seq_printf(m, "  IPEHR: 0x%08x\n", error->ipehr);
-	seq_printf(m, "  INSTDONE: 0x%08x\n", error->instdone);
-	seq_printf(m, "  ACTHD: 0x%08x\n", error->acthd);
-	if (IS_I965G(dev)) {
-		seq_printf(m, "  INSTPS: 0x%08x\n", error->instps);
-		seq_printf(m, "  INSTDONE1: 0x%08x\n", error->instdone1);
-	}
-
-out:
-	spin_unlock_irqrestore(&dev_priv->error_lock, flags);
-
-	return 0;
-}
-
-static struct drm_info_list i915_gem_debugfs_list[] = {
-	{"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
-	{"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
-	{"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
-	{"i915_gem_request", i915_gem_request_info, 0},
-	{"i915_gem_seqno", i915_gem_seqno_info, 0},
-	{"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
-	{"i915_gem_interrupt", i915_interrupt_info, 0},
-	{"i915_gem_hws", i915_hws_info, 0},
-	{"i915_ringbuffer_data", i915_ringbuffer_data, 0},
-	{"i915_ringbuffer_info", i915_ringbuffer_info, 0},
-	{"i915_batchbuffers", i915_batchbuffer_info, 0},
-	{"i915_error_state", i915_error_state, 0},
-};
-#define I915_GEM_DEBUGFS_ENTRIES ARRAY_SIZE(i915_gem_debugfs_list)
-
-int i915_gem_debugfs_init(struct drm_minor *minor)
-{
-	return drm_debugfs_create_files(i915_gem_debugfs_list,
-					I915_GEM_DEBUGFS_ENTRIES,
-					minor->debugfs_root, minor);
-}
-
-void i915_gem_debugfs_cleanup(struct drm_minor *minor)
-{
-	drm_debugfs_remove_files(i915_gem_debugfs_list,
-				 I915_GEM_DEBUGFS_ENTRIES, minor);
-}
-
-#endif /* CONFIG_DEBUG_FS */
-
-- 
cgit v1.2.3


From 9e3a6d155ed0a7636b926a798dd7221ea107b274 Mon Sep 17 00:00:00 2001
From: Ben Gamari <bgamari.foss@gmail.com>
Date: Wed, 1 Jul 2009 22:26:53 -0400
Subject: drm/i915: Add i915 register dumping debugfs file

Add a debugfs file to dump the entire register range. Here we
assume that reading write-only/reserved registers won't make the chip
angry. Seems to hold true, thankfully.

Signed-off-by: Ben Gamari <bgamari.foss@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b4f2d6bce15..49e0d870f49 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -363,7 +363,37 @@ out:
 	return 0;
 }
 
+static int i915_registers_info(struct seq_file *m, void *data) {
+	struct drm_info_node *node = (struct drm_info_node *) m->private;
+	struct drm_device *dev = node->minor->dev;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	uint32_t reg;
+
+#define DUMP_RANGE(start, end) \
+	for (reg=start; reg < end; reg += 4) \
+	seq_printf(m, "%08x\t%08x\n", reg, I915_READ(reg));
+
+	DUMP_RANGE(0x00000, 0x00fff);   /* VGA registers */
+	DUMP_RANGE(0x02000, 0x02fff);   /* instruction, memory, interrupt control registers */
+	DUMP_RANGE(0x03000, 0x031ff);   /* FENCE and PPGTT control registers */
+	DUMP_RANGE(0x03200, 0x03fff);   /* frame buffer compression registers */
+	DUMP_RANGE(0x05000, 0x05fff);   /* I/O control registers */
+	DUMP_RANGE(0x06000, 0x06fff);   /* clock control registers */
+	DUMP_RANGE(0x07000, 0x07fff);   /* 3D internal debug registers */
+	DUMP_RANGE(0x07400, 0x088ff);   /* GPE debug registers */
+	DUMP_RANGE(0x0a000, 0x0afff);   /* display palette registers */
+	DUMP_RANGE(0x10000, 0x13fff);   /* MMIO MCHBAR */
+	DUMP_RANGE(0x30000, 0x3ffff);   /* overlay registers */
+	DUMP_RANGE(0x60000, 0x6ffff);   /* display engine pipeline registers */
+	DUMP_RANGE(0x70000, 0x72fff);   /* display and cursor registers */
+	DUMP_RANGE(0x73000, 0x73fff);   /* performance counters */
+
+	return 0;
+}
+
+
 static struct drm_info_list i915_debugfs_list[] = {
+	{"i915_regs", i915_registers_info, 0},
 	{"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
 	{"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
 	{"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
-- 
cgit v1.2.3


From 5f6a169598938d9e5703f06b64c4f4f972561ce5 Mon Sep 17 00:00:00 2001
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Date: Mon, 10 Aug 2009 21:37:24 +0800
Subject: drm/i915: update debugfs interrupt info on IGDNG

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 41 ++++++++++++++++++++++++++++---------
 1 file changed, 31 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 49e0d870f49..8f28325bc5e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -158,16 +158,37 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
 	struct drm_device *dev = node->minor->dev;
 	drm_i915_private_t *dev_priv = dev->dev_private;
 
-	seq_printf(m, "Interrupt enable:    %08x\n",
-		   I915_READ(IER));
-	seq_printf(m, "Interrupt identity:  %08x\n",
-		   I915_READ(IIR));
-	seq_printf(m, "Interrupt mask:      %08x\n",
-		   I915_READ(IMR));
-	seq_printf(m, "Pipe A stat:         %08x\n",
-		   I915_READ(PIPEASTAT));
-	seq_printf(m, "Pipe B stat:         %08x\n",
-		   I915_READ(PIPEBSTAT));
+	if (!IS_IGDNG(dev)) {
+		seq_printf(m, "Interrupt enable:    %08x\n",
+			   I915_READ(IER));
+		seq_printf(m, "Interrupt identity:  %08x\n",
+			   I915_READ(IIR));
+		seq_printf(m, "Interrupt mask:      %08x\n",
+			   I915_READ(IMR));
+		seq_printf(m, "Pipe A stat:         %08x\n",
+			   I915_READ(PIPEASTAT));
+		seq_printf(m, "Pipe B stat:         %08x\n",
+			   I915_READ(PIPEBSTAT));
+	} else {
+		seq_printf(m, "North Display Interrupt enable:		%08x\n",
+			   I915_READ(DEIER));
+		seq_printf(m, "North Display Interrupt identity:	%08x\n",
+			   I915_READ(DEIIR));
+		seq_printf(m, "North Display Interrupt mask:		%08x\n",
+			   I915_READ(DEIMR));
+		seq_printf(m, "South Display Interrupt enable:		%08x\n",
+			   I915_READ(SDEIER));
+		seq_printf(m, "South Display Interrupt identity:	%08x\n",
+			   I915_READ(SDEIIR));
+		seq_printf(m, "South Display Interrupt mask:		%08x\n",
+			   I915_READ(SDEIMR));
+		seq_printf(m, "Graphics Interrupt enable:		%08x\n",
+			   I915_READ(GTIER));
+		seq_printf(m, "Graphics Interrupt identity:		%08x\n",
+			   I915_READ(GTIIR));
+		seq_printf(m, "Graphics Interrupt mask:		%08x\n",
+			   I915_READ(GTIMR));
+	}
 	seq_printf(m, "Interrupts received: %d\n",
 		   atomic_read(&dev_priv->irq_received));
 	if (dev_priv->hw_status_page != NULL) {
-- 
cgit v1.2.3


From 213c2e643145fc7d8a67f2d5d54ee0f6d7193e2e Mon Sep 17 00:00:00 2001
From: Ma Ling <ling.ma@intel.com>
Date: Mon, 24 Aug 2009 13:50:25 +0800
Subject: drm/i915: select TV format according to connector type

For integrated TV there are 3 connector types: S-VIDEO, Composite and
Component(YprPb). Those tv formats whose component flag is true should
be assigned to Component connector, others are for S-VIDEO and Composite.
The patch intends to find appropriate tv format for each connector.
In such case it will return the correct modeline to user space. Otherwise
it will return the incorrect modeline when S-video/composite is connected.

Signed-off-by: Ma Ling <ling.ma@intel.com>
reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/intel_tv.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 2fbe13a0de8..a6c686cded5 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1437,6 +1437,35 @@ intel_tv_detect_type (struct drm_crtc *crtc, struct intel_output *intel_output)
 	return type;
 }
 
+/*
+ * Here we set accurate tv format according to connector type
+ * i.e Component TV should not be assigned by NTSC or PAL
+ */
+static void intel_tv_find_better_format(struct drm_connector *connector)
+{
+	struct intel_output *intel_output = to_intel_output(connector);
+	struct intel_tv_priv *tv_priv = intel_output->dev_priv;
+	const struct tv_mode *tv_mode = intel_tv_mode_find(intel_output);
+	int i;
+
+	if ((tv_priv->type == DRM_MODE_CONNECTOR_Component) ==
+		tv_mode->component_only)
+		return;
+
+
+	for (i = 0; i < sizeof(tv_modes) / sizeof(*tv_modes); i++) {
+		tv_mode = tv_modes + i;
+
+		if ((tv_priv->type == DRM_MODE_CONNECTOR_Component) ==
+			tv_mode->component_only)
+			break;
+	}
+
+	tv_priv->tv_format = tv_mode->name;
+	drm_connector_property_set_value(connector,
+		connector->dev->mode_config.tv_mode_property, i);
+}
+
 /**
  * Detect the TV connection.
  *
@@ -1473,6 +1502,7 @@ intel_tv_detect(struct drm_connector *connector)
 	if (type < 0)
 		return connector_status_disconnected;
 
+	intel_tv_find_better_format(connector);
 	return connector_status_connected;
 }
 
-- 
cgit v1.2.3


From ce6feabd1b38f9adf4a962d71bc4762047e8f889 Mon Sep 17 00:00:00 2001
From: Zhao Yakui <yakui.zhao@intel.com>
Date: Mon, 24 Aug 2009 13:50:26 +0800
Subject: drm/i915: Enable PAL and SECAM format and add the propery for SDVO-TV

Currently SDVO TV only support NTSC-M format. In this patch
we introduce PAL and SECAM formats available and create seting-format
property at init time. When user dynamically chose preferred
format by xrandr command, it will refine all modelines
provided by SDVO device, then instruct SDVO device to execute.
At the same time the property is added for SDVO-TV so that the SDVO-TV mode can be changed
by using xrandr.

https://bugs.freedesktop.org/show_bug.cgi?id=22891

Signed-off-by: Ma Ling <ling.ma@intel.com>
review-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/intel_sdvo.c | 201 +++++++++++++++++++++++++++++---------
 1 file changed, 153 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index d3b74ba62b4..cabe32df7cd 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -38,6 +38,18 @@
 
 #undef SDVO_DEBUG
 #define I915_SDVO	"i915_sdvo"
+static char *tv_format_names[] = {
+	"NTSC_M"   , "NTSC_J"  , "NTSC_443",
+	"PAL_B"    , "PAL_D"   , "PAL_G"   ,
+	"PAL_H"    , "PAL_I"   , "PAL_M"   ,
+	"PAL_N"    , "PAL_NC"  , "PAL_60"  ,
+	"SECAM_B"  , "SECAM_D" , "SECAM_G" ,
+	"SECAM_K"  , "SECAM_K1", "SECAM_L" ,
+	"SECAM_60"
+};
+
+#define TV_FORMAT_NUM  (sizeof(tv_format_names) / sizeof(*tv_format_names))
+
 struct intel_sdvo_priv {
 	u8 slave_addr;
 
@@ -71,6 +83,15 @@ struct intel_sdvo_priv {
 	 */
 	bool is_tv;
 
+	/* This is for current tv format name */
+	char *tv_format_name;
+
+	/* This contains all current supported TV format */
+	char *tv_format_supported[TV_FORMAT_NUM];
+	int   format_supported_num;
+	struct drm_property *tv_format_property;
+	struct drm_property *tv_format_name_property[TV_FORMAT_NUM];
+
 	/**
 	 * This is set if we treat the device as HDMI, instead of DVI.
 	 */
@@ -97,14 +118,6 @@ struct intel_sdvo_priv {
 	 */
 	struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
 
-	/**
-	 * Current selected TV format.
-	 *
-	 * This is stored in the same structure that's passed to the device, for
-	 * convenience.
-	 */
-	struct intel_sdvo_tv_format tv_format;
-
 	/*
 	 * supported encoding mode, used to determine whether HDMI is
 	 * supported
@@ -945,23 +958,28 @@ static void intel_sdvo_set_avi_infoframe(struct intel_output *output,
 
 static void intel_sdvo_set_tv_format(struct intel_output *output)
 {
+
+	struct intel_sdvo_tv_format format;
 	struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
-	struct intel_sdvo_tv_format *format, unset;
-	u8 status;
+	uint32_t format_map, i;
+	uint8_t status;
 
-	format = &sdvo_priv->tv_format;
-	memset(&unset, 0, sizeof(unset));
-	if (memcmp(format, &unset, sizeof(*format))) {
-		DRM_DEBUG("%s: Choosing default TV format of NTSC-M\n",
-				SDVO_NAME(sdvo_priv));
-		format->ntsc_m = 1;
-		intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, format,
-				sizeof(*format));
-		status = intel_sdvo_read_response(output, NULL, 0);
-		if (status != SDVO_CMD_STATUS_SUCCESS)
-			DRM_DEBUG("%s: Failed to set TV format\n",
-					SDVO_NAME(sdvo_priv));
-	}
+	for (i = 0; i < TV_FORMAT_NUM; i++)
+		if (tv_format_names[i] == sdvo_priv->tv_format_name)
+			break;
+
+	format_map = 1 << i;
+	memset(&format, 0, sizeof(format));
+	memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ?
+			sizeof(format) : sizeof(format_map));
+
+	intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, &format_map,
+			     sizeof(format));
+
+	status = intel_sdvo_read_response(output, NULL, 0);
+	if (status != SDVO_CMD_STATUS_SUCCESS)
+		DRM_DEBUG("%s: Failed to set TV format\n",
+			  SDVO_NAME(sdvo_priv));
 }
 
 static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
@@ -1516,7 +1534,8 @@ static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connect
 	struct intel_output *intel_output = to_intel_output(connector);
 	struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
 
-	intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
+	intel_sdvo_write_cmd(intel_output,
+			     SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
 	status = intel_sdvo_read_response(intel_output, &response, 2);
 
 	DRM_DEBUG("SDVO response %d %d\n", response & 0xff, response >> 8);
@@ -1567,25 +1586,6 @@ static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
 #endif
 }
 
-/**
- * This function checks the current TV format, and chooses a default if
- * it hasn't been set.
- */
-static void
-intel_sdvo_check_tv_format(struct intel_output *output)
-{
-	struct intel_sdvo_priv *dev_priv = output->dev_priv;
-	struct intel_sdvo_tv_format format;
-	uint8_t status;
-
-	intel_sdvo_write_cmd(output, SDVO_CMD_GET_TV_FORMAT, NULL, 0);
-	status = intel_sdvo_read_response(output, &format, sizeof(format));
-	if (status != SDVO_CMD_STATUS_SUCCESS)
-		return;
-
-	memcpy(&dev_priv->tv_format, &format, sizeof(format));
-}
-
 /*
  * Set of SDVO TV modes.
  * Note!  This is in reply order (see loop in get_tv_modes).
@@ -1656,17 +1656,26 @@ static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
 	struct intel_output *output = to_intel_output(connector);
 	struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
 	struct intel_sdvo_sdtv_resolution_request tv_res;
-	uint32_t reply = 0;
+	uint32_t reply = 0, format_map = 0;
+	int i;
 	uint8_t status;
-	int i = 0;
 
-	intel_sdvo_check_tv_format(output);
 
 	/* Read the list of supported input resolutions for the selected TV
 	 * format.
 	 */
-	memset(&tv_res, 0, sizeof(tv_res));
-	memcpy(&tv_res, &sdvo_priv->tv_format, sizeof(tv_res));
+	for (i = 0; i < TV_FORMAT_NUM; i++)
+		if (tv_format_names[i] ==  sdvo_priv->tv_format_name)
+			break;
+
+	format_map = (1 << i);
+	memcpy(&tv_res, &format_map,
+	       sizeof(struct intel_sdvo_sdtv_resolution_request) >
+	       sizeof(format_map) ? sizeof(format_map) :
+	       sizeof(struct intel_sdvo_sdtv_resolution_request));
+
+	intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
+
 	intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
 			     &tv_res, sizeof(tv_res));
 	status = intel_sdvo_read_response(output, &reply, 3);
@@ -1681,6 +1690,7 @@ static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
 			if (nmode)
 				drm_mode_probed_add(connector, nmode);
 		}
+
 }
 
 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
@@ -1753,12 +1763,55 @@ static void intel_sdvo_destroy(struct drm_connector *connector)
 		drm_mode_destroy(connector->dev,
 				 sdvo_priv->sdvo_lvds_fixed_mode);
 
+	if (sdvo_priv->tv_format_property)
+		drm_property_destroy(connector->dev,
+				     sdvo_priv->tv_format_property);
+
 	drm_sysfs_connector_remove(connector);
 	drm_connector_cleanup(connector);
 
 	kfree(intel_output);
 }
 
+static int
+intel_sdvo_set_property(struct drm_connector *connector,
+			struct drm_property *property,
+			uint64_t val)
+{
+	struct intel_output *intel_output = to_intel_output(connector);
+	struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
+	struct drm_encoder *encoder = &intel_output->enc;
+	struct drm_crtc *crtc = encoder->crtc;
+	int ret = 0;
+	bool changed = false;
+
+	ret = drm_connector_property_set_value(connector, property, val);
+	if (ret < 0)
+		goto out;
+
+	if (property == sdvo_priv->tv_format_property) {
+		if (val >= TV_FORMAT_NUM) {
+			ret = -EINVAL;
+			goto out;
+		}
+		if (sdvo_priv->tv_format_name ==
+		    sdvo_priv->tv_format_supported[val])
+			goto out;
+
+		sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[val];
+		changed = true;
+	} else {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	if (changed && crtc)
+		drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
+				crtc->y, crtc->fb);
+out:
+	return ret;
+}
+
 static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
 	.dpms = intel_sdvo_dpms,
 	.mode_fixup = intel_sdvo_mode_fixup,
@@ -1773,6 +1826,7 @@ static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
 	.restore = intel_sdvo_restore,
 	.detect = intel_sdvo_detect,
 	.fill_modes = drm_helper_probe_single_connector_modes,
+	.set_property = intel_sdvo_set_property,
 	.destroy = intel_sdvo_destroy,
 };
 
@@ -2029,6 +2083,55 @@ intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags)
 
 }
 
+static void intel_sdvo_tv_create_property(struct drm_connector *connector)
+{
+      struct intel_output *intel_output = to_intel_output(connector);
+	struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
+	struct intel_sdvo_tv_format format;
+	uint32_t format_map, i;
+	uint8_t status;
+
+	intel_sdvo_set_target_output(intel_output,
+				     sdvo_priv->controlled_output);
+
+	intel_sdvo_write_cmd(intel_output,
+			     SDVO_CMD_GET_SUPPORTED_TV_FORMATS, NULL, 0);
+	status = intel_sdvo_read_response(intel_output,
+					  &format, sizeof(format));
+	if (status != SDVO_CMD_STATUS_SUCCESS)
+		return;
+
+	memcpy(&format_map, &format, sizeof(format) > sizeof(format_map) ?
+	       sizeof(format_map) : sizeof(format));
+
+	if (format_map == 0)
+		return;
+
+	sdvo_priv->format_supported_num = 0;
+	for (i = 0 ; i < TV_FORMAT_NUM; i++)
+		if (format_map & (1 << i)) {
+			sdvo_priv->tv_format_supported
+			[sdvo_priv->format_supported_num++] =
+			tv_format_names[i];
+		}
+
+
+	sdvo_priv->tv_format_property =
+			drm_property_create(
+				connector->dev, DRM_MODE_PROP_ENUM,
+				"mode", sdvo_priv->format_supported_num);
+
+	for (i = 0; i < sdvo_priv->format_supported_num; i++)
+		drm_property_add_enum(
+				sdvo_priv->tv_format_property, i,
+				i, sdvo_priv->tv_format_supported[i]);
+
+	sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[0];
+	drm_connector_attach_property(
+			connector, sdvo_priv->tv_format_property, 0);
+
+}
+
 bool intel_sdvo_init(struct drm_device *dev, int output_device)
 {
 	struct drm_connector *connector;
@@ -2111,6 +2214,8 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
 	drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs);
 
 	drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
+	if (sdvo_priv->is_tv)
+		intel_sdvo_tv_create_property(connector);
 	drm_sysfs_connector_add(connector);
 
 	intel_sdvo_select_ddc_bus(sdvo_priv);
-- 
cgit v1.2.3


From 043029655816ed4cfc2ed247020ef97e5d637392 Mon Sep 17 00:00:00 2001
From: Shaohua Li <shaohua.li@intel.com>
Date: Mon, 24 Aug 2009 10:25:23 +0800
Subject: drm/i915: Support IGD EOS

In the event that any one of the DAC analog outputs (R,G,B) were driven
at full-scale (white video) or some analog level close to full-scale
voltage, and if the video cable were then disconnected, the analog video
voltage level would exceed the maximum electrical overstress limit of the
native (thin-oxide) transistors thus causing a long-term reliability concern.
The electrical overstress condition occurs in this particular case.

This patch address the IGD EOS (electrical overstress condition) issue.
When the EOS interrupt occurs, OS should disable DAC and then disable EOS,
then the normal hotplug operation follows.

TODO: it appears the normal unplug interrupt is missed as reported by Li Peng,
need more checks here.

Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/i915_irq.c  | 21 +++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h  |  2 ++
 drivers/gpu/drm/i915/intel_crt.c | 28 ++++++++++++++++++++++++++++
 3 files changed, 51 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7ebc84c2881..6c89f2ff249 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -565,6 +565,27 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 
 			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 			I915_READ(PORT_HOTPLUG_STAT);
+
+			/* EOS interrupts occurs */
+			if (IS_IGD(dev) &&
+				(hotplug_status & CRT_EOS_INT_STATUS)) {
+				u32 temp;
+
+				DRM_DEBUG("EOS interrupt occurs\n");
+				/* status is already cleared */
+				temp = I915_READ(ADPA);
+				temp &= ~ADPA_DAC_ENABLE;
+				I915_WRITE(ADPA, temp);
+
+				temp = I915_READ(PORT_HOTPLUG_EN);
+				temp &= ~CRT_EOS_INT_EN;
+				I915_WRITE(PORT_HOTPLUG_EN, temp);
+
+				temp = I915_READ(PORT_HOTPLUG_STAT);
+				if (temp & CRT_EOS_INT_STATUS)
+					I915_WRITE(PORT_HOTPLUG_STAT,
+						CRT_EOS_INT_STATUS);
+			}
 		}
 
 		I915_WRITE(IIR, iir);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2955083aa47..87a737ff3d7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -683,6 +683,7 @@
 #define   SDVOB_HOTPLUG_INT_EN			(1 << 26)
 #define   SDVOC_HOTPLUG_INT_EN			(1 << 25)
 #define   TV_HOTPLUG_INT_EN			(1 << 18)
+#define   CRT_EOS_INT_EN			(1 << 10)
 #define   CRT_HOTPLUG_INT_EN			(1 << 9)
 #define   CRT_HOTPLUG_FORCE_DETECT		(1 << 3)
 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32	(0 << 8)
@@ -717,6 +718,7 @@
 #define   DPC_HOTPLUG_INT_STATUS		(1 << 28)
 #define   HDMID_HOTPLUG_INT_STATUS		(1 << 27)
 #define   DPD_HOTPLUG_INT_STATUS		(1 << 27)
+#define   CRT_EOS_INT_STATUS			(1 << 12)
 #define   CRT_HOTPLUG_INT_STATUS		(1 << 11)
 #define   TV_HOTPLUG_INT_STATUS			(1 << 10)
 #define   CRT_HOTPLUG_MONITOR_MASK		(3 << 8)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 590f81c8f59..88814fa2dfd 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -64,6 +64,34 @@ static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
 	}
 
 	I915_WRITE(reg, temp);
+
+	if (IS_IGD(dev)) {
+		if (mode == DRM_MODE_DPMS_OFF) {
+			/* turn off DAC */
+			temp = I915_READ(PORT_HOTPLUG_EN);
+			temp &= ~CRT_EOS_INT_EN;
+			I915_WRITE(PORT_HOTPLUG_EN, temp);
+
+			temp = I915_READ(PORT_HOTPLUG_STAT);
+			if (temp & CRT_EOS_INT_STATUS)
+				I915_WRITE(PORT_HOTPLUG_STAT,
+					CRT_EOS_INT_STATUS);
+		} else {
+			/* turn on DAC. EOS interrupt must be enabled after DAC
+			 * is enabled, so it sounds not good to enable it in
+			 * i915_driver_irq_postinstall()
+			 * wait 12.5ms after DAC is enabled
+			 */
+			msleep(13);
+			temp = I915_READ(PORT_HOTPLUG_STAT);
+			if (temp & CRT_EOS_INT_STATUS)
+				I915_WRITE(PORT_HOTPLUG_STAT,
+					CRT_EOS_INT_STATUS);
+			temp = I915_READ(PORT_HOTPLUG_EN);
+			temp |= CRT_EOS_INT_EN;
+			I915_WRITE(PORT_HOTPLUG_EN, temp);
+		}
+	}
 }
 
 static int intel_crt_mode_valid(struct drm_connector *connector,
-- 
cgit v1.2.3


From 652c393a3368af84359da37c45afc35a91144960 Mon Sep 17 00:00:00 2001
From: Jesse Barnes <jbarnes@virtuousgeek.org>
Date: Mon, 17 Aug 2009 13:31:43 -0700
Subject: drm/i915: add dynamic clock frequency control

There are several sources of unnecessary power consumption on Intel
graphics systems. The first is the LVDS clock. TFTs don't suffer from
persistence issues like CRTs, and so we can reduce the LVDS refresh rate
when the screen is idle. It will be automatically upclocked when
userspace triggers graphical activity. Beyond that, we can enable memory
self refresh. This allows the memory to go into a lower power state when
the graphics are idle. Finally, we can drop some clocks on the gpu
itself. All of these things can be reenabled between frames when GPU
activity is triggered, and so there should be no user visible graphical
changes.

Signed-off-by: Jesse Barnes <jesse.barnes@intel.com>
Signed-off-by: Matthew Garrett <mjg@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/i915_drv.c      |   3 +
 drivers/gpu/drm/i915/i915_drv.h      |  14 +-
 drivers/gpu/drm/i915/i915_gem.c      |  10 +-
 drivers/gpu/drm/i915/i915_reg.h      | 137 ++++++++-
 drivers/gpu/drm/i915/i915_suspend.c  |   4 +-
 drivers/gpu/drm/i915/intel_bios.c    |   8 +-
 drivers/gpu/drm/i915/intel_display.c | 561 +++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_drv.h     |   4 +
 drivers/gpu/drm/i915/intel_i2c.c     |   8 +-
 9 files changed, 704 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 263636e77e6..81ab4883d89 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -43,6 +43,9 @@ module_param_named(modeset, i915_modeset, int, 0400);
 unsigned int i915_fbpercrtc = 0;
 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
 
+unsigned int i915_powersave = 1;
+module_param_named(powersave, i915_powersave, int, 0400);
+
 static struct drm_driver driver;
 
 static struct pci_device_id pciidlist[] = {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e286f4e13bd..76914ae65c3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -311,7 +311,7 @@ typedef struct drm_i915_private {
 	u32 saveIMR;
 	u32 saveCACHE_MODE_0;
 	u32 saveD_STATE;
-	u32 saveCG_2D_DIS;
+	u32 saveDSPCLK_GATE_D;
 	u32 saveMI_ARB_STATE;
 	u32 saveSWF0[16];
 	u32 saveSWF1[16];
@@ -443,6 +443,14 @@ typedef struct drm_i915_private {
 		struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
 	} mm;
 	struct sdvo_device_mapping sdvo_mappings[2];
+
+	/* Reclocking support */
+	bool render_reclock_avail;
+	bool lvds_downclock_avail;
+	struct work_struct idle_work;
+	struct timer_list idle_timer;
+	bool busy;
+	u16 orig_clock;
 } drm_i915_private_t;
 
 /** driver private structure attached to each drm_gem_object */
@@ -575,6 +583,7 @@ enum intel_chip_family {
 extern struct drm_ioctl_desc i915_ioctls[];
 extern int i915_max_ioctl;
 extern unsigned int i915_fbpercrtc;
+extern unsigned int i915_powersave;
 
 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
@@ -903,6 +912,9 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 /* dsparb controlled by hw only */
 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev))
 
+#define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev))
+#define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev))
+
 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)
 
 #endif
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7edb5b9d579..73b58193afe 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -29,6 +29,7 @@
 #include "drm.h"
 #include "i915_drm.h"
 #include "i915_drv.h"
+#include "intel_drv.h"
 #include <linux/swap.h>
 #include <linux/pci.h>
 
@@ -981,6 +982,7 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_gem_set_domain *args = data;
 	struct drm_gem_object *obj;
+	struct drm_i915_gem_object *obj_priv;
 	uint32_t read_domains = args->read_domains;
 	uint32_t write_domain = args->write_domain;
 	int ret;
@@ -1004,15 +1006,17 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 	obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 	if (obj == NULL)
 		return -EBADF;
+	obj_priv = obj->driver_private;
 
 	mutex_lock(&dev->struct_mutex);
+
+	intel_mark_busy(dev, obj);
+
 #if WATCH_BUF
 	DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
 		 obj, obj->size, read_domains, write_domain);
 #endif
 	if (read_domains & I915_GEM_DOMAIN_GTT) {
-		struct drm_i915_gem_object *obj_priv = obj->driver_private;
-
 		ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
 
 		/* Update the LRU on the fence for the CPU access that's
@@ -2776,6 +2780,8 @@ i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
 	BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
 	BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
 
+	intel_mark_busy(dev, obj);
+
 #if WATCH_BUF
 	DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
 		 __func__, obj,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 87a737ff3d7..884757ce5b6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -55,7 +55,7 @@
 /* PCI config space */
 
 #define HPLLCC	0xc0 /* 855 only */
-#define   GC_CLOCK_CONTROL_MASK		(3 << 0)
+#define   GC_CLOCK_CONTROL_MASK		(0xf << 0)
 #define   GC_CLOCK_133_200		(0 << 0)
 #define   GC_CLOCK_100_200		(1 << 0)
 #define   GC_CLOCK_100_133		(2 << 0)
@@ -65,6 +65,25 @@
 #define   GC_DISPLAY_CLOCK_190_200_MHZ	(0 << 4)
 #define   GC_DISPLAY_CLOCK_333_MHZ	(4 << 4)
 #define   GC_DISPLAY_CLOCK_MASK		(7 << 4)
+#define   GM45_GC_RENDER_CLOCK_MASK	(0xf << 0)
+#define   GM45_GC_RENDER_CLOCK_266_MHZ	(8 << 0)
+#define   GM45_GC_RENDER_CLOCK_320_MHZ	(9 << 0)
+#define   GM45_GC_RENDER_CLOCK_400_MHZ	(0xb << 0)
+#define   GM45_GC_RENDER_CLOCK_533_MHZ	(0xc << 0)
+#define   I965_GC_RENDER_CLOCK_MASK	(0xf << 0)
+#define   I965_GC_RENDER_CLOCK_267_MHZ	(2 << 0)
+#define   I965_GC_RENDER_CLOCK_333_MHZ	(3 << 0)
+#define   I965_GC_RENDER_CLOCK_444_MHZ	(4 << 0)
+#define   I965_GC_RENDER_CLOCK_533_MHZ	(5 << 0)
+#define   I945_GC_RENDER_CLOCK_MASK	(7 << 0)
+#define   I945_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
+#define   I945_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
+#define   I945_GC_RENDER_CLOCK_250_MHZ	(3 << 0)
+#define   I945_GC_RENDER_CLOCK_400_MHZ	(5 << 0)
+#define   I915_GC_RENDER_CLOCK_MASK	(7 << 0)
+#define   I915_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
+#define   I915_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
+#define   I915_GC_RENDER_CLOCK_333_MHZ	(4 << 0)
 #define LBB	0xf4
 
 /* VGA stuff */
@@ -553,9 +572,118 @@
 #define   DPLLA_TEST_M_BYPASS		(1 << 2)
 #define   DPLLA_INPUT_BUFFER_ENABLE	(1 << 0)
 #define D_STATE		0x6104
-#define CG_2D_DIS	0x6200
-#define DPCUNIT_CLOCK_GATE_DISABLE	(1 << 24)
-#define CG_3D_DIS	0x6204
+#define  DSTATE_PLL_D3_OFF			(1<<3)
+#define  DSTATE_GFX_CLOCK_GATING		(1<<1)
+#define  DSTATE_DOT_CLOCK_GATING		(1<<0)
+#define DSPCLK_GATE_D		0x6200
+# define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
+# define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
+# define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
+# define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
+# define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
+# define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
+# define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
+# define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
+# define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
+# define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
+# define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
+# define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
+# define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
+# define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
+# define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
+# define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
+# define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
+# define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
+# define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
+# define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
+# define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
+# define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
+# define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
+# define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
+# define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
+# define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
+# define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
+# define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
+/**
+ * This bit must be set on the 830 to prevent hangs when turning off the
+ * overlay scaler.
+ */
+# define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)
+# define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)
+# define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)
+# define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
+# define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
+
+#define RENCLK_GATE_D1		0x6204
+# define BLITTER_CLOCK_GATE_DISABLE		(1 << 13) /* 945GM only */
+# define MPEG_CLOCK_GATE_DISABLE		(1 << 12) /* 945GM only */
+# define PC_FE_CLOCK_GATE_DISABLE		(1 << 11)
+# define PC_BE_CLOCK_GATE_DISABLE		(1 << 10)
+# define WINDOWER_CLOCK_GATE_DISABLE		(1 << 9)
+# define INTERPOLATOR_CLOCK_GATE_DISABLE	(1 << 8)
+# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE	(1 << 7)
+# define MOTION_COMP_CLOCK_GATE_DISABLE		(1 << 6)
+# define MAG_CLOCK_GATE_DISABLE			(1 << 5)
+/** This bit must be unset on 855,865 */
+# define MECI_CLOCK_GATE_DISABLE		(1 << 4)
+# define DCMP_CLOCK_GATE_DISABLE		(1 << 3)
+# define MEC_CLOCK_GATE_DISABLE			(1 << 2)
+# define MECO_CLOCK_GATE_DISABLE		(1 << 1)
+/** This bit must be set on 855,865. */
+# define SV_CLOCK_GATE_DISABLE			(1 << 0)
+# define I915_MPEG_CLOCK_GATE_DISABLE		(1 << 16)
+# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE	(1 << 15)
+# define I915_MOTION_COMP_CLOCK_GATE_DISABLE	(1 << 14)
+# define I915_BD_BF_CLOCK_GATE_DISABLE		(1 << 13)
+# define I915_SF_SE_CLOCK_GATE_DISABLE		(1 << 12)
+# define I915_WM_CLOCK_GATE_DISABLE		(1 << 11)
+# define I915_IZ_CLOCK_GATE_DISABLE		(1 << 10)
+# define I915_PI_CLOCK_GATE_DISABLE		(1 << 9)
+# define I915_DI_CLOCK_GATE_DISABLE		(1 << 8)
+# define I915_SH_SV_CLOCK_GATE_DISABLE		(1 << 7)
+# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE	(1 << 6)
+# define I915_SC_CLOCK_GATE_DISABLE		(1 << 5)
+# define I915_FL_CLOCK_GATE_DISABLE		(1 << 4)
+# define I915_DM_CLOCK_GATE_DISABLE		(1 << 3)
+# define I915_PS_CLOCK_GATE_DISABLE		(1 << 2)
+# define I915_CC_CLOCK_GATE_DISABLE		(1 << 1)
+# define I915_BY_CLOCK_GATE_DISABLE		(1 << 0)
+
+# define I965_RCZ_CLOCK_GATE_DISABLE		(1 << 30)
+/** This bit must always be set on 965G/965GM */
+# define I965_RCC_CLOCK_GATE_DISABLE		(1 << 29)
+# define I965_RCPB_CLOCK_GATE_DISABLE		(1 << 28)
+# define I965_DAP_CLOCK_GATE_DISABLE		(1 << 27)
+# define I965_ROC_CLOCK_GATE_DISABLE		(1 << 26)
+# define I965_GW_CLOCK_GATE_DISABLE		(1 << 25)
+# define I965_TD_CLOCK_GATE_DISABLE		(1 << 24)
+/** This bit must always be set on 965G */
+# define I965_ISC_CLOCK_GATE_DISABLE		(1 << 23)
+# define I965_IC_CLOCK_GATE_DISABLE		(1 << 22)
+# define I965_EU_CLOCK_GATE_DISABLE		(1 << 21)
+# define I965_IF_CLOCK_GATE_DISABLE		(1 << 20)
+# define I965_TC_CLOCK_GATE_DISABLE		(1 << 19)
+# define I965_SO_CLOCK_GATE_DISABLE		(1 << 17)
+# define I965_FBC_CLOCK_GATE_DISABLE		(1 << 16)
+# define I965_MARI_CLOCK_GATE_DISABLE		(1 << 15)
+# define I965_MASF_CLOCK_GATE_DISABLE		(1 << 14)
+# define I965_MAWB_CLOCK_GATE_DISABLE		(1 << 13)
+# define I965_EM_CLOCK_GATE_DISABLE		(1 << 12)
+# define I965_UC_CLOCK_GATE_DISABLE		(1 << 11)
+# define I965_SI_CLOCK_GATE_DISABLE		(1 << 6)
+# define I965_MT_CLOCK_GATE_DISABLE		(1 << 5)
+# define I965_PL_CLOCK_GATE_DISABLE		(1 << 4)
+# define I965_DG_CLOCK_GATE_DISABLE		(1 << 3)
+# define I965_QC_CLOCK_GATE_DISABLE		(1 << 2)
+# define I965_FT_CLOCK_GATE_DISABLE		(1 << 1)
+# define I965_DM_CLOCK_GATE_DISABLE		(1 << 0)
+
+#define RENCLK_GATE_D2		0x6208
+#define VF_UNIT_CLOCK_GATE_DISABLE		(1 << 9)
+#define GS_UNIT_CLOCK_GATE_DISABLE		(1 << 7)
+#define CL_UNIT_CLOCK_GATE_DISABLE		(1 << 6)
+#define RAMCLK_GATE_D		0x6210		/* CRL only */
+#define DEUC			0x6214          /* CRL only */
 
 /*
  * Palette regs
@@ -1588,6 +1716,7 @@
 #define   PIPECONF_PROGRESSIVE	(0 << 21)
 #define   PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)
 #define   PIPECONF_INTERLACE_FIELD_0_ONLY		(7 << 21)
+#define   PIPECONF_CXSR_DOWNCLOCK	(1<<16)
 #define PIPEASTAT		0x70024
 #define   PIPE_FIFO_UNDERRUN_STATUS		(1UL<<31)
 #define   PIPE_CRC_ERROR_ENABLE			(1UL<<29)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 1d04e1904ac..20d4d19f556 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -461,7 +461,7 @@ int i915_save_state(struct drm_device *dev)
 
 	/* Clock gating state */
 	dev_priv->saveD_STATE = I915_READ(D_STATE);
-	dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS);
+	dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);
 
 	/* Cache mode state */
 	dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
@@ -588,7 +588,7 @@ int i915_restore_state(struct drm_device *dev)
 
 	/* Clock gating state */
 	I915_WRITE (D_STATE, dev_priv->saveD_STATE);
-	I915_WRITE (CG_2D_DIS, dev_priv->saveCG_2D_DIS);
+	I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
 
 	/* Cache mode state */
 	I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index f806fcc54e0..1e28c1652fd 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -355,8 +355,14 @@ parse_driver_features(struct drm_i915_private *dev_priv,
 	}
 
 	driver = find_section(bdb, BDB_DRIVER_FEATURES);
-	if (driver && driver->lvds_config == BDB_DRIVER_FEATURE_EDP)
+	if (!driver)
+		return;
+
+	if (driver->lvds_config == BDB_DRIVER_FEATURE_EDP)
 		dev_priv->edp_support = 1;
+
+	if (driver->dual_frequency)
+		dev_priv->render_reclock_avail = true;
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 748ed50c55c..3c9445193e3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -38,6 +38,7 @@
 
 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
 static void intel_update_watermarks(struct drm_device *dev);
+static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
 
 typedef struct {
     /* given values */
@@ -67,6 +68,8 @@ struct intel_limit {
     intel_p2_t	    p2;
     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
 		      int, int, intel_clock_t *);
+    bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
+			      int, int, intel_clock_t *);
 };
 
 #define I8XX_DOT_MIN		  25000
@@ -261,6 +264,9 @@ static bool
 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 		    int target, int refclk, intel_clock_t *best_clock);
 static bool
+intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
+			    int target, int refclk, intel_clock_t *best_clock);
+static bool
 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 			int target, int refclk, intel_clock_t *best_clock);
 static bool
@@ -286,6 +292,7 @@ static const intel_limit_t intel_limits_i8xx_dvo = {
 	.p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 		 .p2_slow = I8XX_P2_SLOW,	.p2_fast = I8XX_P2_FAST },
 	.find_pll = intel_find_best_PLL,
+	.find_reduced_pll = intel_find_best_reduced_PLL,
 };
 
 static const intel_limit_t intel_limits_i8xx_lvds = {
@@ -300,6 +307,7 @@ static const intel_limit_t intel_limits_i8xx_lvds = {
 	.p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 		 .p2_slow = I8XX_P2_LVDS_SLOW,	.p2_fast = I8XX_P2_LVDS_FAST },
 	.find_pll = intel_find_best_PLL,
+	.find_reduced_pll = intel_find_best_reduced_PLL,
 };
 	
 static const intel_limit_t intel_limits_i9xx_sdvo = {
@@ -314,6 +322,7 @@ static const intel_limit_t intel_limits_i9xx_sdvo = {
 	.p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 		 .p2_slow = I9XX_P2_SDVO_DAC_SLOW,	.p2_fast = I9XX_P2_SDVO_DAC_FAST },
 	.find_pll = intel_find_best_PLL,
+	.find_reduced_pll = intel_find_best_reduced_PLL,
 };
 
 static const intel_limit_t intel_limits_i9xx_lvds = {
@@ -331,6 +340,7 @@ static const intel_limit_t intel_limits_i9xx_lvds = {
 	.p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 		 .p2_slow = I9XX_P2_LVDS_SLOW,	.p2_fast = I9XX_P2_LVDS_FAST },
 	.find_pll = intel_find_best_PLL,
+	.find_reduced_pll = intel_find_best_reduced_PLL,
 };
 
     /* below parameter and function is for G4X Chipset Family*/
@@ -348,6 +358,7 @@ static const intel_limit_t intel_limits_g4x_sdvo = {
 		 .p2_fast = G4X_P2_SDVO_FAST
 	},
 	.find_pll = intel_g4x_find_best_PLL,
+	.find_reduced_pll = intel_g4x_find_best_PLL,
 };
 
 static const intel_limit_t intel_limits_g4x_hdmi = {
@@ -364,6 +375,7 @@ static const intel_limit_t intel_limits_g4x_hdmi = {
 		 .p2_fast = G4X_P2_HDMI_DAC_FAST
 	},
 	.find_pll = intel_g4x_find_best_PLL,
+	.find_reduced_pll = intel_g4x_find_best_PLL,
 };
 
 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
@@ -388,6 +400,7 @@ static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 		 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 	},
 	.find_pll = intel_g4x_find_best_PLL,
+	.find_reduced_pll = intel_g4x_find_best_PLL,
 };
 
 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
@@ -412,6 +425,7 @@ static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 		 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 	},
 	.find_pll = intel_g4x_find_best_PLL,
+	.find_reduced_pll = intel_g4x_find_best_PLL,
 };
 
 static const intel_limit_t intel_limits_g4x_display_port = {
@@ -449,6 +463,7 @@ static const intel_limit_t intel_limits_igd_sdvo = {
 	.p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 		 .p2_slow = I9XX_P2_SDVO_DAC_SLOW,	.p2_fast = I9XX_P2_SDVO_DAC_FAST },
 	.find_pll = intel_find_best_PLL,
+	.find_reduced_pll = intel_find_best_reduced_PLL,
 };
 
 static const intel_limit_t intel_limits_igd_lvds = {
@@ -464,6 +479,7 @@ static const intel_limit_t intel_limits_igd_lvds = {
 	.p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 		 .p2_slow = I9XX_P2_LVDS_SLOW,	.p2_fast = I9XX_P2_LVDS_SLOW },
 	.find_pll = intel_find_best_PLL,
+	.find_reduced_pll = intel_find_best_reduced_PLL,
 };
 
 static const intel_limit_t intel_limits_igdng_sdvo = {
@@ -688,15 +704,16 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 
 	memset (best_clock, 0, sizeof (*best_clock));
 
-	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
-		for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
-			/* m1 is always 0 in IGD */
-			if (clock.m2 >= clock.m1 && !IS_IGD(dev))
-				break;
-			for (clock.n = limit->n.min; clock.n <= limit->n.max;
-			     clock.n++) {
-				for (clock.p1 = limit->p1.min;
-				     clock.p1 <= limit->p1.max; clock.p1++) {
+	for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
+		for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
+		     clock.m1++) {
+			for (clock.m2 = limit->m2.min;
+			     clock.m2 <= limit->m2.max; clock.m2++) {
+				/* m1 is always 0 in IGD */
+				if (clock.m2 >= clock.m1 && !IS_IGD(dev))
+					break;
+				for (clock.n = limit->n.min;
+				     clock.n <= limit->n.max; clock.n++) {
 					int this_err;
 
 					intel_clock(dev, refclk, &clock);
@@ -717,6 +734,46 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 	return (err != target);
 }
 
+
+static bool
+intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
+			    int target, int refclk, intel_clock_t *best_clock)
+
+{
+	struct drm_device *dev = crtc->dev;
+	intel_clock_t clock;
+	int err = target;
+	bool found = false;
+
+	memcpy(&clock, best_clock, sizeof(intel_clock_t));
+
+	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
+		for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
+			/* m1 is always 0 in IGD */
+			if (clock.m2 >= clock.m1 && !IS_IGD(dev))
+				break;
+			for (clock.n = limit->n.min; clock.n <= limit->n.max;
+			     clock.n++) {
+				int this_err;
+
+				intel_clock(dev, refclk, &clock);
+
+				if (!intel_PLL_is_valid(crtc, &clock))
+					continue;
+
+				this_err = abs(clock.dot - target);
+				if (this_err < err) {
+					*best_clock = clock;
+					err = this_err;
+					found = true;
+				}
+			}
+		}
+	}
+
+	return found;
+}
+
 static bool
 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 			int target, int refclk, intel_clock_t *best_clock)
@@ -747,7 +804,7 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 	max_n = limit->n.max;
 	/* based on hardware requriment prefer smaller n to precision */
 	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
-		/* based on hardware requirment prefere larger m1,m2, p1 */
+		/* based on hardware requirment prefere larger m1,m2 */
 		for (clock.m1 = limit->m1.max;
 		     clock.m1 >= limit->m1.min; clock.m1--) {
 			for (clock.m2 = limit->m2.max;
@@ -832,15 +889,14 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 
 	memset(best_clock, 0, sizeof(*best_clock));
 	max_n = limit->n.max;
-	/* based on hardware requriment prefer smaller n to precision */
-	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
-		/* based on hardware requirment prefere larger m1,m2, p1 */
-		for (clock.m1 = limit->m1.max;
-		     clock.m1 >= limit->m1.min; clock.m1--) {
-			for (clock.m2 = limit->m2.max;
-			     clock.m2 >= limit->m2.min; clock.m2--) {
-				for (clock.p1 = limit->p1.max;
-				     clock.p1 >= limit->p1.min; clock.p1--) {
+	for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
+		/* based on hardware requriment prefer smaller n to precision */
+		for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
+			/* based on hardware requirment prefere larger m1,m2 */
+			for (clock.m1 = limit->m1.max;
+			     clock.m1 >= limit->m1.min; clock.m1--) {
+				for (clock.m2 = limit->m2.max;
+				     clock.m2 >= limit->m2.min; clock.m2--) {
 					int this_err;
 
 					intel_clock(dev, refclk, &clock);
@@ -1030,8 +1086,11 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
 
 	if (old_fb) {
 		intel_fb = to_intel_framebuffer(old_fb);
+		obj_priv = intel_fb->obj->driver_private;
 		i915_gem_object_unpin(intel_fb->obj);
 	}
+	intel_increase_pllclock(crtc, true);
+
 	mutex_unlock(&dev->struct_mutex);
 
 	if (!dev->primary->master)
@@ -2054,6 +2113,18 @@ static int intel_get_fifo_size(struct drm_device *dev, int plane)
 	return size;
 }
 
+static void g4x_update_wm(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 fw_blc_self = I915_READ(FW_BLC_SELF);
+
+	if (i915_powersave)
+		fw_blc_self |= FW_BLC_SELF_EN;
+	else
+		fw_blc_self &= ~FW_BLC_SELF_EN;
+	I915_WRITE(FW_BLC_SELF, fw_blc_self);
+}
+
 static void i965_update_wm(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2105,7 +2176,8 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
 	cwm = 2;
 
 	/* Calc sr entries for one plane configs */
-	if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
+	if (HAS_FW_BLC(dev) && sr_hdisplay &&
+	    (!planea_clock || !planeb_clock)) {
 		/* self-refresh has much higher latency */
 		const static int sr_latency_ns = 6000;
 
@@ -2120,8 +2192,7 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
 		srwm = total_size - sr_entries;
 		if (srwm < 0)
 			srwm = 1;
-		if (IS_I9XX(dev))
-			I915_WRITE(FW_BLC_SELF, (srwm & 0x3f));
+		I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
 	}
 
 	DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
@@ -2195,9 +2266,6 @@ static void intel_update_watermarks(struct drm_device *dev)
 	unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
 	int enabled = 0, pixel_size = 0;
 
-	if (DSPARB_HWCONTROL(dev))
-		return;
-
 	/* Get the clock config from both planes */
 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 		intel_crtc = to_intel_crtc(crtc);
@@ -2230,7 +2298,9 @@ static void intel_update_watermarks(struct drm_device *dev)
 	else if (IS_IGD(dev))
 		igd_disable_cxsr(dev);
 
-	if (IS_I965G(dev))
+	if (IS_G4X(dev))
+		g4x_update_wm(dev);
+	else if (IS_I965G(dev))
 		i965_update_wm(dev);
 	else if (IS_I9XX(dev) || IS_MOBILE(dev))
 		i9xx_update_wm(dev, planea_clock, planeb_clock, sr_hdisplay,
@@ -2264,9 +2334,9 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
 	int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
 	int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
 	int refclk, num_outputs = 0;
-	intel_clock_t clock;
-	u32 dpll = 0, fp = 0, dspcntr, pipeconf;
-	bool ok, is_sdvo = false, is_dvo = false;
+	intel_clock_t clock, reduced_clock;
+	u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
+	bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
 	bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
 	bool is_edp = false;
 	struct drm_mode_config *mode_config = &dev->mode_config;
@@ -2349,6 +2419,14 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
 		return -EINVAL;
 	}
 
+	if (limit->find_reduced_pll && dev_priv->lvds_downclock_avail) {
+		memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
+		has_reduced_clock = limit->find_reduced_pll(limit, crtc,
+							    (adjusted_mode->clock*3/4),
+							    refclk,
+							    &reduced_clock);
+	}
+
 	/* SDVO TV has fixed PLL values depend on its clock range,
 	   this mirrors vbios setting. */
 	if (is_sdvo && is_tv) {
@@ -2394,10 +2472,17 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
 				  link_bw, &m_n);
 	}
 
-	if (IS_IGD(dev))
+	if (IS_IGD(dev)) {
 		fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
-	else
+		if (has_reduced_clock)
+			fp2 = (1 << reduced_clock.n) << 16 |
+				reduced_clock.m1 << 8 | reduced_clock.m2;
+	} else {
 		fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
+		if (has_reduced_clock)
+			fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
+				reduced_clock.m2;
+	}
 
 	if (!IS_IGDNG(dev))
 		dpll = DPLL_VGA_MODE_DIS;
@@ -2426,6 +2511,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
 			/* also FPA1 */
 			if (IS_IGDNG(dev))
 				dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
+			if (IS_G4X(dev) && has_reduced_clock)
+				dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
 		}
 		switch (clock.p2) {
 		case 5:
@@ -2573,6 +2660,22 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
 		udelay(150);
 	}
 
+	if (is_lvds && has_reduced_clock && i915_powersave) {
+		I915_WRITE(fp_reg + 4, fp2);
+		intel_crtc->lowfreq_avail = true;
+		if (HAS_PIPE_CXSR(dev)) {
+			DRM_DEBUG("enabling CxSR downclocking\n");
+			pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
+		}
+	} else {
+		I915_WRITE(fp_reg + 4, fp);
+		intel_crtc->lowfreq_avail = false;
+		if (HAS_PIPE_CXSR(dev)) {
+			DRM_DEBUG("disabling CxSR downclocking\n");
+			pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
+		}
+	}
+
 	I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
 		   ((adjusted_mode->crtc_htotal - 1) << 16));
 	I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
@@ -2769,10 +2872,16 @@ static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	struct intel_framebuffer *intel_fb;
 	int pipe = intel_crtc->pipe;
 	uint32_t temp = 0;
 	uint32_t adder;
 
+	if (crtc->fb) {
+		intel_fb = to_intel_framebuffer(crtc->fb);
+		intel_mark_busy(dev, intel_fb->obj);
+	}
+
 	if (x < 0) {
 		temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
 		x = -x;
@@ -3070,6 +3179,312 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 	return mode;
 }
 
+#define GPU_IDLE_TIMEOUT 500 /* ms */
+
+/* When this timer fires, we've been idle for awhile */
+static void intel_gpu_idle_timer(unsigned long arg)
+{
+	struct drm_device *dev = (struct drm_device *)arg;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+
+	DRM_DEBUG("idle timer fired, downclocking\n");
+
+	dev_priv->busy = false;
+
+	schedule_work(&dev_priv->idle_work);
+}
+
+void intel_increase_renderclock(struct drm_device *dev, bool schedule)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+
+	if (IS_IGDNG(dev))
+		return;
+
+	if (!dev_priv->render_reclock_avail) {
+		DRM_ERROR("not reclocking render clock\n");
+		return;
+	}
+
+	/* Restore render clock frequency to original value */
+	if (IS_G4X(dev) || IS_I9XX(dev))
+		pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
+	else if (IS_I85X(dev))
+		pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
+	DRM_DEBUG("increasing render clock frequency\n");
+
+	/* Schedule downclock */
+	if (schedule)
+		mod_timer(&dev_priv->idle_timer, jiffies +
+			  msecs_to_jiffies(GPU_IDLE_TIMEOUT));
+}
+
+void intel_decrease_renderclock(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+
+	if (IS_IGDNG(dev))
+		return;
+
+	if (!dev_priv->render_reclock_avail) {
+		DRM_ERROR("not reclocking render clock\n");
+		return;
+	}
+
+	if (IS_G4X(dev)) {
+		u16 gcfgc;
+
+		/* Adjust render clock... */
+		pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
+
+		/* Down to minimum... */
+		gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
+		gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
+
+		pci_write_config_word(dev->pdev, GCFGC, gcfgc);
+	} else if (IS_I965G(dev)) {
+		u16 gcfgc;
+
+		/* Adjust render clock... */
+		pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
+
+		/* Down to minimum... */
+		gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
+		gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
+
+		pci_write_config_word(dev->pdev, GCFGC, gcfgc);
+	} else if (IS_I945G(dev) || IS_I945GM(dev)) {
+		u16 gcfgc;
+
+		/* Adjust render clock... */
+		pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
+
+		/* Down to minimum... */
+		gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
+		gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
+
+		pci_write_config_word(dev->pdev, GCFGC, gcfgc);
+	} else if (IS_I915G(dev)) {
+		u16 gcfgc;
+
+		/* Adjust render clock... */
+		pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
+
+		/* Down to minimum... */
+		gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
+		gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
+
+		pci_write_config_word(dev->pdev, GCFGC, gcfgc);
+	} else if (IS_I85X(dev)) {
+		u16 hpllcc;
+
+		/* Adjust render clock... */
+		pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
+
+		/* Up to maximum... */
+		hpllcc &= ~GC_CLOCK_CONTROL_MASK;
+		hpllcc |= GC_CLOCK_133_200;
+
+		pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
+	}
+	DRM_DEBUG("decreasing render clock frequency\n");
+}
+
+/* Note that no increase function is needed for this - increase_renderclock()
+ *  will also rewrite these bits
+ */
+void intel_decrease_displayclock(struct drm_device *dev)
+{
+	if (IS_IGDNG(dev))
+		return;
+
+	if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
+	    IS_I915GM(dev)) {
+		u16 gcfgc;
+
+		/* Adjust render clock... */
+		pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
+
+		/* Down to minimum... */
+		gcfgc &= ~0xf0;
+		gcfgc |= 0x80;
+
+		pci_write_config_word(dev->pdev, GCFGC, gcfgc);
+	}
+}
+
+#define CRTC_IDLE_TIMEOUT 1000 /* ms */
+
+static void intel_crtc_idle_timer(unsigned long arg)
+{
+	struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
+	struct drm_crtc *crtc = &intel_crtc->base;
+	drm_i915_private_t *dev_priv = crtc->dev->dev_private;
+
+	DRM_DEBUG("idle timer fired, downclocking\n");
+
+	intel_crtc->busy = false;
+
+	schedule_work(&dev_priv->idle_work);
+}
+
+static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
+{
+	struct drm_device *dev = crtc->dev;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int pipe = intel_crtc->pipe;
+	int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
+	int dpll = I915_READ(dpll_reg);
+
+	if (IS_IGDNG(dev))
+		return;
+
+	if (!dev_priv->lvds_downclock_avail)
+		return;
+
+	if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
+		DRM_DEBUG("upclocking LVDS\n");
+
+		/* Unlock panel regs */
+		I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
+
+		dpll &= ~DISPLAY_RATE_SELECT_FPA1;
+		I915_WRITE(dpll_reg, dpll);
+		dpll = I915_READ(dpll_reg);
+		intel_wait_for_vblank(dev);
+		dpll = I915_READ(dpll_reg);
+		if (dpll & DISPLAY_RATE_SELECT_FPA1)
+			DRM_DEBUG("failed to upclock LVDS!\n");
+
+		/* ...and lock them again */
+		I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
+	}
+
+	/* Schedule downclock */
+	if (schedule)
+		mod_timer(&intel_crtc->idle_timer, jiffies +
+			  msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
+}
+
+static void intel_decrease_pllclock(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int pipe = intel_crtc->pipe;
+	int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
+	int dpll = I915_READ(dpll_reg);
+
+	if (IS_IGDNG(dev))
+		return;
+
+	if (!dev_priv->lvds_downclock_avail)
+		return;
+
+	/*
+	 * Since this is called by a timer, we should never get here in
+	 * the manual case.
+	 */
+	if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
+		DRM_DEBUG("downclocking LVDS\n");
+
+		/* Unlock panel regs */
+		I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
+
+		dpll |= DISPLAY_RATE_SELECT_FPA1;
+		I915_WRITE(dpll_reg, dpll);
+		dpll = I915_READ(dpll_reg);
+		intel_wait_for_vblank(dev);
+		dpll = I915_READ(dpll_reg);
+		if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
+			DRM_DEBUG("failed to downclock LVDS!\n");
+
+		/* ...and lock them again */
+		I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
+	}
+
+}
+
+/**
+ * intel_idle_update - adjust clocks for idleness
+ * @work: work struct
+ *
+ * Either the GPU or display (or both) went idle.  Check the busy status
+ * here and adjust the CRTC and GPU clocks as necessary.
+ */
+static void intel_idle_update(struct work_struct *work)
+{
+	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
+						    idle_work);
+	struct drm_device *dev = dev_priv->dev;
+	struct drm_crtc *crtc;
+	struct intel_crtc *intel_crtc;
+
+	if (!i915_powersave)
+		return;
+
+	mutex_lock(&dev->struct_mutex);
+
+	/* GPU isn't processing, downclock it. */
+	if (!dev_priv->busy) {
+		intel_decrease_renderclock(dev);
+		intel_decrease_displayclock(dev);
+	}
+
+	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+		/* Skip inactive CRTCs */
+		if (!crtc->fb)
+			continue;
+
+		intel_crtc = to_intel_crtc(crtc);
+		if (!intel_crtc->busy)
+			intel_decrease_pllclock(crtc);
+	}
+
+	mutex_unlock(&dev->struct_mutex);
+}
+
+/**
+ * intel_mark_busy - mark the GPU and possibly the display busy
+ * @dev: drm device
+ * @obj: object we're operating on
+ *
+ * Callers can use this function to indicate that the GPU is busy processing
+ * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
+ * buffer), we'll also mark the display as busy, so we know to increase its
+ * clock frequency.
+ */
+void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	struct drm_crtc *crtc = NULL;
+	struct intel_framebuffer *intel_fb;
+	struct intel_crtc *intel_crtc;
+
+	dev_priv->busy = true;
+	intel_increase_renderclock(dev, true);
+
+	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+		if (!crtc->fb)
+			continue;
+
+		intel_crtc = to_intel_crtc(crtc);
+		intel_fb = to_intel_framebuffer(crtc->fb);
+		if (intel_fb->obj == obj) {
+			if (!intel_crtc->busy) {
+				/* Non-busy -> busy, upclock */
+				intel_increase_pllclock(crtc, true);
+				intel_crtc->busy = true;
+			} else {
+				/* Busy -> busy, put off timer */
+				mod_timer(&intel_crtc->idle_timer, jiffies +
+					  msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
+			}
+		}
+	}
+}
+
 static void intel_crtc_destroy(struct drm_crtc *crtc)
 {
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -3125,6 +3540,10 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
 	intel_crtc->mode_set.crtc = &intel_crtc->base;
 	intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1);
 	intel_crtc->mode_set.num_connectors = 0;
+	intel_crtc->busy = false;
+
+	setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
+		    (unsigned long)intel_crtc);
 
 	if (i915_fbpercrtc) {
 
@@ -3362,8 +3781,56 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
 	.fb_changed = intelfb_probe,
 };
 
+void intel_init_clock_gating(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	/*
+	 * Disable clock gating reported to work incorrectly according to the
+	 * specs, but enable as much else as we can.
+	 */
+	if (IS_G4X(dev)) {
+		uint32_t dspclk_gate;
+		I915_WRITE(RENCLK_GATE_D1, 0);
+		I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
+		       GS_UNIT_CLOCK_GATE_DISABLE |
+		       CL_UNIT_CLOCK_GATE_DISABLE);
+		I915_WRITE(RAMCLK_GATE_D, 0);
+		dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
+			OVRUNIT_CLOCK_GATE_DISABLE |
+			OVCUNIT_CLOCK_GATE_DISABLE;
+		if (IS_GM45(dev))
+			dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
+		I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
+	} else if (IS_I965GM(dev)) {
+		I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
+		I915_WRITE(RENCLK_GATE_D2, 0);
+		I915_WRITE(DSPCLK_GATE_D, 0);
+		I915_WRITE(RAMCLK_GATE_D, 0);
+		I915_WRITE16(DEUC, 0);
+	} else if (IS_I965G(dev)) {
+		I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
+		       I965_RCC_CLOCK_GATE_DISABLE |
+		       I965_RCPB_CLOCK_GATE_DISABLE |
+		       I965_ISC_CLOCK_GATE_DISABLE |
+		       I965_FBC_CLOCK_GATE_DISABLE);
+		I915_WRITE(RENCLK_GATE_D2, 0);
+	} else if (IS_I9XX(dev)) {
+		u32 dstate = I915_READ(D_STATE);
+
+		dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
+			DSTATE_DOT_CLOCK_GATING;
+		I915_WRITE(D_STATE, dstate);
+	} else if (IS_I855(dev) || IS_I865G(dev)) {
+		I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
+	} else if (IS_I830(dev)) {
+		I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
+	}
+}
+
 void intel_modeset_init(struct drm_device *dev)
 {
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	int num_pipe;
 	int i;
 
@@ -3398,15 +3865,47 @@ void intel_modeset_init(struct drm_device *dev)
 	DRM_DEBUG("%d display pipe%s available.\n",
 		  num_pipe, num_pipe > 1 ? "s" : "");
 
+	if (IS_I85X(dev))
+		pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
+	else if (IS_I9XX(dev) || IS_G4X(dev))
+		pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
+
 	for (i = 0; i < num_pipe; i++) {
 		intel_crtc_init(dev, i);
 	}
 
 	intel_setup_outputs(dev);
+
+	intel_init_clock_gating(dev);
+
+	INIT_WORK(&dev_priv->idle_work, intel_idle_update);
+	setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
+		    (unsigned long)dev);
 }
 
 void intel_modeset_cleanup(struct drm_device *dev)
 {
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_crtc *crtc;
+	struct intel_crtc *intel_crtc;
+
+	mutex_lock(&dev->struct_mutex);
+
+	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+		/* Skip inactive CRTCs */
+		if (!crtc->fb)
+			continue;
+
+		intel_crtc = to_intel_crtc(crtc);
+		intel_increase_pllclock(crtc, false);
+		del_timer_sync(&intel_crtc->idle_timer);
+	}
+
+	intel_increase_renderclock(dev, false);
+	del_timer_sync(&dev_priv->idle_timer);
+
+	mutex_unlock(&dev->struct_mutex);
+
 	drm_mode_config_cleanup(dev);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 25aa6facc12..495dc955d04 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -119,6 +119,9 @@ struct intel_crtc {
 	struct intel_framebuffer *fbdev_fb;
 	/* a mode_set for fbdev users on this crtc */
 	struct drm_mode_set mode_set;
+	bool busy; /* is scanout buffer being updated frequently? */
+	struct timer_list idle_timer;
+	bool lowfreq_avail;
 };
 
 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
@@ -137,6 +140,7 @@ extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg);
 extern bool intel_sdvo_init(struct drm_device *dev, int output_device);
 extern void intel_dvo_init(struct drm_device *dev);
 extern void intel_tv_init(struct drm_device *dev);
+extern void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj);
 extern void intel_lvds_init(struct drm_device *dev);
 extern void intel_dp_init(struct drm_device *dev, int dp_reg);
 void
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 62b8bead765..c7eab724c41 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -42,11 +42,11 @@ void intel_i2c_quirk_set(struct drm_device *dev, bool enable)
 	if (!IS_IGD(dev))
 		return;
 	if (enable)
-		I915_WRITE(CG_2D_DIS,
-			I915_READ(CG_2D_DIS) | DPCUNIT_CLOCK_GATE_DISABLE);
+		I915_WRITE(DSPCLK_GATE_D,
+			I915_READ(DSPCLK_GATE_D) | DPCUNIT_CLOCK_GATE_DISABLE);
 	else
-		I915_WRITE(CG_2D_DIS,
-			I915_READ(CG_2D_DIS) & (~DPCUNIT_CLOCK_GATE_DISABLE));
+		I915_WRITE(DSPCLK_GATE_D,
+			I915_READ(DSPCLK_GATE_D) & (~DPCUNIT_CLOCK_GATE_DISABLE));
 }
 
 /*
-- 
cgit v1.2.3


From d6073d775c4b26107351cb8d5e21cec4391f6314 Mon Sep 17 00:00:00 2001
From: Kyle McMartin <kyle@redhat.com>
Date: Tue, 26 May 2009 12:27:34 -0400
Subject: drm/i915: i915_modeset is signed

Signed-off-by: Kyle McMartin <kyle@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/i915_drv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 81ab4883d89..dbe568c9327 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -37,7 +37,7 @@
 #include <linux/console.h>
 #include "drm_crtc_helper.h"
 
-static unsigned int i915_modeset = -1;
+static int i915_modeset = -1;
 module_param_named(modeset, i915_modeset, int, 0400);
 
 unsigned int i915_fbpercrtc = 0;
-- 
cgit v1.2.3


From 67cf781bea52d461b7c8b63b23be19e87c33d7bf Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 31 Aug 2009 08:52:02 -0700
Subject: drm/i915: Make the downclocking debug code be under DRM_DEBUG not
 DRM_ERROR.

Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3c9445193e3..35e86196c06 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3202,7 +3202,7 @@ void intel_increase_renderclock(struct drm_device *dev, bool schedule)
 		return;
 
 	if (!dev_priv->render_reclock_avail) {
-		DRM_ERROR("not reclocking render clock\n");
+		DRM_DEBUG("not reclocking render clock\n");
 		return;
 	}
 
@@ -3227,7 +3227,7 @@ void intel_decrease_renderclock(struct drm_device *dev)
 		return;
 
 	if (!dev_priv->render_reclock_avail) {
-		DRM_ERROR("not reclocking render clock\n");
+		DRM_DEBUG("not reclocking render clock\n");
 		return;
 	}
 
-- 
cgit v1.2.3


From c05422d52ee6b4cff8b63eab1a7351780518fc5e Mon Sep 17 00:00:00 2001
From: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Tue, 11 Aug 2009 16:05:30 +0200
Subject: drm/i915: remove open-coded drm_mode_object_find

And clean up a small whitespace goof-up in the same function, while
I was looking at it.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/intel_display.c | 20 ++++++++------------
 1 file changed, 8 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 35e86196c06..f0f38f5e752 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3557,30 +3557,26 @@ int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
-	struct drm_crtc *crtc = NULL;
-	int pipe = -1;
+	struct drm_mode_object *drmmode_obj;
+	struct intel_crtc *crtc;
 
 	if (!dev_priv) {
 		DRM_ERROR("called with no initialization\n");
 		return -EINVAL;
 	}
 
-	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-		if (crtc->base.id == pipe_from_crtc_id->crtc_id) {
-			pipe = intel_crtc->pipe;
-			break;
-		}
-	}
+	drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
+			DRM_MODE_OBJECT_CRTC);
 
-	if (pipe == -1) {
+	if (!drmmode_obj) {
 		DRM_ERROR("no such CRTC id\n");
 		return -EINVAL;
 	}
 
-	pipe_from_crtc_id->pipe = pipe;
+	crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
+	pipe_from_crtc_id->pipe = crtc->pipe;
 
-       return 0;
+	return 0;
 }
 
 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
-- 
cgit v1.2.3


From 65655d4ab72456c4c3e503fead55fabf8211a79d Mon Sep 17 00:00:00 2001
From: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Tue, 11 Aug 2009 16:05:31 +0200
Subject: drm/i915: modeset: always set intel_crtc->dpms_mode by moving the
 assignment up.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/intel_display.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f0f38f5e752..867a969980e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1640,6 +1640,8 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
 	else
 		i9xx_crtc_dpms(crtc, mode);
 
+	intel_crtc->dpms_mode = mode;
+
 	if (!dev->primary->master)
 		return;
 
@@ -1662,8 +1664,6 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
 		DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
 		break;
 	}
-
-	intel_crtc->dpms_mode = mode;
 }
 
 static void intel_crtc_prepare (struct drm_crtc *crtc)
-- 
cgit v1.2.3


From 553bd149bb2de7848b2b84642876f27202421368 Mon Sep 17 00:00:00 2001
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Date: Wed, 2 Sep 2009 10:57:52 +0800
Subject: drm/i915: fix tiling on IGDNG

It seems that on IGDNG the same swizzling setup always applys.
And front buffer tiling needs to set address swizzle in display
arb control too.

Fix plane tricle feed setting in v1 which should be disable bit,
and always setup address swizzle to let hardware care for buffer
tiling in all cases.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/i915_gem_tiling.c | 15 +++++++--------
 drivers/gpu/drm/i915/i915_reg.h        |  4 ++++
 drivers/gpu/drm/i915/intel_display.c   | 10 ++++++++++
 3 files changed, 21 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index a2d527b22ec..e774a4a1a50 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -234,7 +234,13 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
 	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 	bool need_disable;
 
-	if (!IS_I9XX(dev)) {
+	if (IS_IGDNG(dev)) {
+		/* On IGDNG whatever DRAM config, GPU always do
+		 * same swizzling setup.
+		 */
+		swizzle_x = I915_BIT_6_SWIZZLE_9_10;
+		swizzle_y = I915_BIT_6_SWIZZLE_9;
+	} else if (!IS_I9XX(dev)) {
 		/* As far as we know, the 865 doesn't have these bit 6
 		 * swizzling issues.
 		 */
@@ -317,13 +323,6 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
 		}
 	}
 
-	/* FIXME: check with memory config on IGDNG */
-	if (IS_IGDNG(dev)) {
-		DRM_ERROR("disable tiling on IGDNG...\n");
-		swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
-		swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
-	}
-
 	dev_priv->mm.bit_6_swizzle_x = swizzle_x;
 	dev_priv->mm.bit_6_swizzle_y = swizzle_y;
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 884757ce5b6..e38cd21161c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1864,6 +1864,7 @@
 #define   DISPPLANE_NO_LINE_DOUBLE		0
 #define   DISPPLANE_STEREO_POLARITY_FIRST	0
 #define   DISPPLANE_STEREO_POLARITY_SECOND	(1<<18)
+#define   DISPPLANE_TRICKLE_FEED_DISABLE	(1<<14) /* IGDNG */
 #define   DISPPLANE_TILED			(1<<10)
 #define DSPAADDR		0x70184
 #define DSPASTRIDE		0x70188
@@ -2044,6 +2045,9 @@
 #define GTIIR   0x44018
 #define GTIER   0x4401c
 
+#define DISP_ARB_CTL	0x45000
+#define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
+
 /* PCH */
 
 /* south display engine interrupt */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 867a969980e..d7c7fa48987 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1064,6 +1064,10 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
 			dspcntr &= ~DISPPLANE_TILED;
 	}
 
+	if (IS_IGDNG(dev))
+		/* must disable */
+		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
+
 	I915_WRITE(dspcntr_reg, dspcntr);
 
 	Start = obj_priv->gtt_offset;
@@ -2719,6 +2723,12 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
 
 	intel_wait_for_vblank(dev);
 
+	if (IS_IGDNG(dev)) {
+		/* enable address swizzle for tiling buffer */
+		temp = I915_READ(DISP_ARB_CTL);
+		I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
+	}
+
 	I915_WRITE(dspcntr_reg, dspcntr);
 
 	/* Flush the plane changes */
-- 
cgit v1.2.3


From 57cdaf90f5f607eb029356074fefb66c9b1c0659 Mon Sep 17 00:00:00 2001
From: Keith Packard <keithp@keithp.com>
Date: Fri, 4 Sep 2009 13:07:54 +0800
Subject: drm/I915: Use the CRT DDC to get the EDID for DVI-connector on Mac

mac Mini's have a single DDC line on the DVI connector, shared between the
analog link and the digital link. So, if DDC isn't detected on GPIOE (the
usual SDVO DDC link), try GPIOA (the usual VGA DDC link) when there isn't a
VGA monitor connected.

Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/intel_sdvo.c | 96 ++++++++++++++++++++++++++++++---------
 1 file changed, 74 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index cabe32df7cd..c585da8d662 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -127,6 +127,9 @@ struct intel_sdvo_priv {
 	/* DDC bus used by this SDVO output */
 	uint8_t ddc_bus;
 
+	/* Mac mini hack -- use the same DDC as the analog connector */
+	struct i2c_adapter *analog_ddc_bus;
+
 	int save_sdvo_mult;
 	u16 save_active_outputs;
 	struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2;
@@ -1496,6 +1499,36 @@ intel_sdvo_multifunc_encoder(struct intel_output *intel_output)
 	return (caps > 1);
 }
 
+static struct drm_connector *
+intel_find_analog_connector(struct drm_device *dev)
+{
+	struct drm_connector *connector;
+	struct intel_output *intel_output;
+
+	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+		intel_output = to_intel_output(connector);
+		if (intel_output->type == INTEL_OUTPUT_ANALOG)
+			return connector;
+	}
+	return NULL;
+}
+
+static int
+intel_analog_is_connected(struct drm_device *dev)
+{
+	struct drm_connector *analog_connector;
+	analog_connector = intel_find_analog_connector(dev);
+
+	if (!analog_connector)
+		return false;
+
+	if (analog_connector->funcs->detect(analog_connector) ==
+			connector_status_disconnected)
+		return false;
+
+	return true;
+}
+
 enum drm_connector_status
 intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response)
 {
@@ -1506,6 +1539,15 @@ intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response)
 
 	edid = drm_get_edid(&intel_output->base,
 			    intel_output->ddc_bus);
+
+	/* when there is no edid and no monitor is connected with VGA
+	 * port, try to use the CRT ddc to read the EDID for DVI-connector
+	 */
+	if (edid == NULL &&
+	    sdvo_priv->analog_ddc_bus &&
+	    !intel_analog_is_connected(intel_output->base.dev))
+		edid = drm_get_edid(&intel_output->base,
+				    sdvo_priv->analog_ddc_bus);
 	if (edid != NULL) {
 		/* Don't report the output as connected if it's a DVI-I
 		 * connector with a non-digital EDID coming out.
@@ -1559,31 +1601,32 @@ static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connect
 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
 {
 	struct intel_output *intel_output = to_intel_output(connector);
+	struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
+	int num_modes;
 
 	/* set the bus switch and get the modes */
-	intel_ddc_get_modes(intel_output);
+	num_modes = intel_ddc_get_modes(intel_output);
 
-#if 0
-	struct drm_device *dev = encoder->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	/* Mac mini hack.  On this device, I get DDC through the analog, which
-	 * load-detects as disconnected.  I fail to DDC through the SDVO DDC,
-	 * but it does load-detect as connected.  So, just steal the DDC bits
-	 * from analog when we fail at finding it the right way.
+	/*
+	 * Mac mini hack.  On this device, the DVI-I connector shares one DDC
+	 * link between analog and digital outputs. So, if the regular SDVO
+	 * DDC fails, check to see if the analog output is disconnected, in
+	 * which case we'll look there for the digital DDC data.
 	 */
-	crt = xf86_config->output[0];
-	intel_output = crt->driver_private;
-	if (intel_output->type == I830_OUTPUT_ANALOG &&
-	    crt->funcs->detect(crt) == XF86OutputStatusDisconnected) {
-		I830I2CInit(pScrn, &intel_output->pDDCBus, GPIOA, "CRTDDC_A");
-		edid_mon = xf86OutputGetEDID(crt, intel_output->pDDCBus);
-		xf86DestroyI2CBusRec(intel_output->pDDCBus, true, true);
-	}
-	if (edid_mon) {
-		xf86OutputSetEDID(output, edid_mon);
-		modes = xf86OutputGetEDIDModes(output);
+	if (num_modes == 0 &&
+	    sdvo_priv->analog_ddc_bus &&
+	    !intel_analog_is_connected(intel_output->base.dev)) {
+		struct i2c_adapter *digital_ddc_bus;
+
+		/* Switch to the analog ddc bus and try that
+		 */
+		digital_ddc_bus = intel_output->ddc_bus;
+		intel_output->ddc_bus = sdvo_priv->analog_ddc_bus;
+
+		(void) intel_ddc_get_modes(intel_output);
+
+		intel_output->ddc_bus = digital_ddc_bus;
 	}
-#endif
 }
 
 /*
@@ -1758,6 +1801,8 @@ static void intel_sdvo_destroy(struct drm_connector *connector)
 		intel_i2c_destroy(intel_output->i2c_bus);
 	if (intel_output->ddc_bus)
 		intel_i2c_destroy(intel_output->ddc_bus);
+	if (sdvo_priv->analog_ddc_bus)
+		intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
 
 	if (sdvo_priv->sdvo_lvds_fixed_mode != NULL)
 		drm_mode_destroy(connector->dev,
@@ -2177,10 +2222,15 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
 	}
 
 	/* setup the DDC bus. */
-	if (output_device == SDVOB)
+	if (output_device == SDVOB) {
 		intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");
-	else
+		sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
+						"SDVOB/VGA DDC BUS");
+	} else {
 		intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS");
+		sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
+						"SDVOC/VGA DDC BUS");
+	}
 
 	if (intel_output->ddc_bus == NULL)
 		goto err_i2c;
@@ -2248,6 +2298,8 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
 	return true;
 
 err_i2c:
+	if (sdvo_priv->analog_ddc_bus != NULL)
+		intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
 	if (intel_output->ddc_bus != NULL)
 		intel_i2c_destroy(intel_output->ddc_bus);
 	if (intel_output->i2c_bus != NULL)
-- 
cgit v1.2.3


From 5e17ee74b541b56b5d4cfab6502a5116f224e32c Mon Sep 17 00:00:00 2001
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Date: Thu, 3 Sep 2009 09:30:06 +0800
Subject: drm/i915: do dynamic clock freq control only in kernel modesetting

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/intel_display.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d7c7fa48987..9aa1d2de8a8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3472,6 +3472,9 @@ void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
 	struct intel_framebuffer *intel_fb;
 	struct intel_crtc *intel_crtc;
 
+	if (!drm_core_check_feature(dev, DRIVER_MODESET))
+		return;
+
 	dev_priv->busy = true;
 	intel_increase_renderclock(dev, true);
 
-- 
cgit v1.2.3


From 0ef82af7253c1929a3995f271b8b0db462d1a0c3 Mon Sep 17 00:00:00 2001
From: Chris Wilson <chris@chris-wilson.co.uk>
Date: Sat, 5 Sep 2009 18:07:06 +0100
Subject: drm/i915: Pad ringbuffer with NOOPs before wrapping
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

According to the docs, the ringbuffer is not allowed to wrap in the middle
of an instruction.

G45 PRM, Vol 1b, p101:
  While the “free space” wrap may allow commands to be wrapped around the
  end of the Ring Buffer, the wrap should only occur between commands.
  Padding (with NOP) may be required to follow this restriction.

Do as commanded.

[Having seen bug reports where there is evidence of split commands, but
apparently the GPU has continued on merrily before a bizarre and untimely
death, this may or may not fix a few random hangs.]

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
CC: Eric Anholt <eric@anholt.net>
Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/i915_debugfs.c |  4 +---
 drivers/gpu/drm/i915/i915_dma.c     | 29 ++++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_drv.h     | 43 ++++++++++++++++++-------------------
 drivers/gpu/drm/i915/i915_gem.c     |  1 -
 4 files changed, 50 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 8f28325bc5e..1e3bdcee863 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -333,15 +333,13 @@ static int i915_ringbuffer_info(struct seq_file *m, void *data)
 	struct drm_info_node *node = (struct drm_info_node *) m->private;
 	struct drm_device *dev = node->minor->dev;
 	drm_i915_private_t *dev_priv = dev->dev_private;
-	unsigned int head, tail, mask;
+	unsigned int head, tail;
 
 	head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 	tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
-	mask = dev_priv->ring.tail_mask;
 
 	seq_printf(m, "RingHead :  %08x\n", head);
 	seq_printf(m, "RingTail :  %08x\n", tail);
-	seq_printf(m, "RingMask :  %08x\n", mask);
 	seq_printf(m, "RingSize :  %08lx\n", dev_priv->ring.Size);
 	seq_printf(m, "Acthd :     %08x\n", I915_READ(IS_I965G(dev) ? ACTHD_I965 : ACTHD));
 
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 50d1f782768..f135bdcc6d5 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -80,6 +80,34 @@ int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
 	return -EBUSY;
 }
 
+/* As a ringbuffer is only allowed to wrap between instructions, fill
+ * the tail with NOOPs.
+ */
+int i915_wrap_ring(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	volatile unsigned int *virt;
+	int rem;
+
+	rem = dev_priv->ring.Size - dev_priv->ring.tail;
+	if (dev_priv->ring.space < rem) {
+		int ret = i915_wait_ring(dev, rem, __func__);
+		if (ret)
+			return ret;
+	}
+	dev_priv->ring.space -= rem;
+
+	virt = (unsigned int *)
+		(dev_priv->ring.virtual_start + dev_priv->ring.tail);
+	rem /= 4;
+	while (rem--)
+		*virt++ = MI_NOOP;
+
+	dev_priv->ring.tail = 0;
+
+	return 0;
+}
+
 /**
  * Sets up the hardware status page for devices that need a physical address
  * in the register.
@@ -200,7 +228,6 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 		}
 
 		dev_priv->ring.Size = init->ring_size;
-		dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 
 		dev_priv->ring.map.offset = init->ring_start;
 		dev_priv->ring.map.size = init->ring_size;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 76914ae65c3..2d5bce643e6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -85,7 +85,6 @@ struct drm_i915_gem_phys_object {
 };
 
 typedef struct _drm_i915_ring_buffer {
-	int tail_mask;
 	unsigned long Size;
 	u8 *virtual_start;
 	int head;
@@ -790,33 +789,32 @@ extern void intel_modeset_cleanup(struct drm_device *dev);
 
 #define I915_VERBOSE 0
 
-#define RING_LOCALS	unsigned int outring, ringmask, outcount; \
-                        volatile char *virt;
-
-#define BEGIN_LP_RING(n) do {				\
-	if (I915_VERBOSE)				\
-		DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n));	\
-	if (dev_priv->ring.space < (n)*4)		\
-		i915_wait_ring(dev, (n)*4, __func__);		\
-	outcount = 0;					\
-	outring = dev_priv->ring.tail;			\
-	ringmask = dev_priv->ring.tail_mask;		\
-	virt = dev_priv->ring.virtual_start;		\
+#define RING_LOCALS	volatile unsigned int *ring_virt__;
+
+#define BEGIN_LP_RING(n) do {						\
+	int bytes__ = 4*(n);						\
+	if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n));	\
+	/* a wrap must occur between instructions so pad beforehand */	\
+	if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \
+		i915_wrap_ring(dev);					\
+	if (unlikely (dev_priv->ring.space < bytes__))			\
+		i915_wait_ring(dev, bytes__, __func__);			\
+	ring_virt__ = (unsigned int *)					\
+	        (dev_priv->ring.virtual_start + dev_priv->ring.tail);	\
+	dev_priv->ring.tail += bytes__;					\
+	dev_priv->ring.tail &= dev_priv->ring.Size - 1;			\
+	dev_priv->ring.space -= bytes__;				\
 } while (0)
 
-#define OUT_RING(n) do {					\
+#define OUT_RING(n) do {						\
 	if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));	\
-	*(volatile unsigned int *)(virt + outring) = (n);	\
-        outcount++;						\
-	outring += 4;						\
-	outring &= ringmask;					\
+	*ring_virt__++ = (n);						\
 } while (0)
 
 #define ADVANCE_LP_RING() do {						\
-	if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);	\
-	dev_priv->ring.tail = outring;					\
-	dev_priv->ring.space -= outcount * 4;				\
-	I915_WRITE(PRB0_TAIL, outring);			\
+	if (I915_VERBOSE)						\
+		DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail);	\
+	I915_WRITE(PRB0_TAIL, dev_priv->ring.tail);			\
 } while(0)
 
 /**
@@ -839,6 +837,7 @@ extern void intel_modeset_cleanup(struct drm_device *dev);
 #define I915_GEM_HWS_INDEX		0x20
 #define I915_BREADCRUMB_INDEX		0x21
 
+extern int i915_wrap_ring(struct drm_device * dev);
 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 
 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 73b58193afe..076752112a3 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4099,7 +4099,6 @@ i915_gem_init_ringbuffer(struct drm_device *dev)
 
 	/* Set up the kernel mapping for the ring. */
 	ring->Size = obj->size;
-	ring->tail_mask = obj->size - 1;
 
 	ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
 	ring->map.size = obj->size;
-- 
cgit v1.2.3


From 01dfba93d9dfcf6d7abfc55ff5d9d6e76fa01ba0 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Sun, 6 Sep 2009 15:18:53 -0700
Subject: drm/i915: Put the idle reclocking work on our private workqueue as
 well.

Fixes (again) whole-system lockups due to GPU lockups.

Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/intel_display.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9aa1d2de8a8..f6741032c60 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3201,7 +3201,7 @@ static void intel_gpu_idle_timer(unsigned long arg)
 
 	dev_priv->busy = false;
 
-	schedule_work(&dev_priv->idle_work);
+	queue_work(dev_priv->wq, &dev_priv->idle_work);
 }
 
 void intel_increase_renderclock(struct drm_device *dev, bool schedule)
@@ -3335,7 +3335,7 @@ static void intel_crtc_idle_timer(unsigned long arg)
 
 	intel_crtc->busy = false;
 
-	schedule_work(&dev_priv->idle_work);
+	queue_work(dev_priv->wq, &dev_priv->idle_work);
 }
 
 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
-- 
cgit v1.2.3


From a498b8210f2f6ee0529c28048b5c4cecc17937c2 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 1 Sep 2009 14:40:41 +1000
Subject: drm/radeon/kms: block depthxy offset from use from userspace.

This could be used to bypass CS checks.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/reg_srcs/r300  | 1 -
 drivers/gpu/drm/radeon/reg_srcs/rs600 | 1 -
 drivers/gpu/drm/radeon/reg_srcs/rv515 | 1 -
 3 files changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/radeon/reg_srcs/r300 b/drivers/gpu/drm/radeon/reg_srcs/r300
index 16f8f38264f..d927005c6fa 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/r300
+++ b/drivers/gpu/drm/radeon/reg_srcs/r300
@@ -725,4 +725,3 @@ r300 0x4f60
 0x4F50 ZB_HIZ_RDINDEX
 0x4F54 ZB_HIZ_PITCH
 0x4F58 ZB_ZPASS_DATA
-0x4F60 ZB_DEPTHXY_OFFSET
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rs600 b/drivers/gpu/drm/radeon/reg_srcs/rs600
index 498c581a328..344405a44df 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/rs600
+++ b/drivers/gpu/drm/radeon/reg_srcs/rs600
@@ -725,4 +725,3 @@ rs600 0x6d40
 0x4F50 ZB_HIZ_RDINDEX
 0x4F54 ZB_HIZ_PITCH
 0x4F58 ZB_ZPASS_DATA
-0x4F60 ZB_DEPTHXY_OFFSET
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rv515 b/drivers/gpu/drm/radeon/reg_srcs/rv515
index 7432df7f1c1..9602026ff9f 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/rv515
+++ b/drivers/gpu/drm/radeon/reg_srcs/rv515
@@ -483,4 +483,3 @@ rv515 0x6d40
 0x4F50 ZB_HIZ_RDINDEX
 0x4F54 ZB_HIZ_PITCH
 0x4F58 ZB_ZPASS_DATA
-0x4F60 ZB_DEPTHXY_OFFSET
-- 
cgit v1.2.3


From adf551bb25bfb83b79ce3c3887557ed817e26cc9 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 7 Sep 2009 13:49:07 +1000
Subject: drm/radeon/kms: add updated registers from drm-fixes.

Fixes up the DISCARD + 2 sided stencil in the new generator scripts.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/reg_srcs/r300  | 2 ++
 drivers/gpu/drm/radeon/reg_srcs/rs600 | 2 ++
 drivers/gpu/drm/radeon/reg_srcs/rv515 | 1 +
 3 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/radeon/reg_srcs/r300 b/drivers/gpu/drm/radeon/reg_srcs/r300
index d927005c6fa..19c4663fa9c 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/r300
+++ b/drivers/gpu/drm/radeon/reg_srcs/r300
@@ -708,6 +708,8 @@ r300 0x4f60
 0x4E80 RB3D_AARESOLVE_OFFSET
 0x4E84 RB3D_AARESOLVE_PITCH
 0x4E88 RB3D_AARESOLVE_CTL
+0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
+0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD
 0x4F04 ZB_ZSTENCILCNTL
 0x4F08 ZB_STENCILREFMASK
 0x4F14 ZB_ZTOP
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rs600 b/drivers/gpu/drm/radeon/reg_srcs/rs600
index 344405a44df..8e3c0b807ad 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/rs600
+++ b/drivers/gpu/drm/radeon/reg_srcs/rs600
@@ -708,6 +708,8 @@ rs600 0x6d40
 0x4E80 RB3D_AARESOLVE_OFFSET
 0x4E84 RB3D_AARESOLVE_PITCH
 0x4E88 RB3D_AARESOLVE_CTL
+0x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
+0x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD
 0x4F04 ZB_ZSTENCILCNTL
 0x4F08 ZB_STENCILREFMASK
 0x4F14 ZB_ZTOP
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rv515 b/drivers/gpu/drm/radeon/reg_srcs/rv515
index 9602026ff9f..0102a0d5735 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/rv515
+++ b/drivers/gpu/drm/radeon/reg_srcs/rv515
@@ -483,3 +483,4 @@ rv515 0x6d40
 0x4F50 ZB_HIZ_RDINDEX
 0x4F54 ZB_HIZ_PITCH
 0x4F58 ZB_ZPASS_DATA
+0x4FD4 ZB_STENCILREFMASK_BF
-- 
cgit v1.2.3


From 13a8195b148615b15a4f4385f695f2a232095414 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 7 Sep 2009 15:45:33 +1000
Subject: drm: split crtc/fb helpers into a separate module

I really don't want to have core drm module rely on CONFIG_FB,
so this is the easiest answer.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/Kconfig        | 10 ++++++++--
 drivers/gpu/drm/Makefile       |  9 ++++++---
 drivers/gpu/drm/drm_crtc.c     |  1 +
 drivers/gpu/drm/radeon/Kconfig |  1 +
 4 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index ebafad18e31..8c7309177c0 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -18,6 +18,13 @@ menuconfig DRM
 	  details.  You should also select and configure AGP
 	  (/dev/agpgart) support.
 
+config DRM_MODE_HELPER
+	tristate
+	depends on DRM
+	select FB
+	help
+	  FB and CRTC helpers for kms drivers.
+
 config DRM_TTM
 	tristate
 	depends on DRM
@@ -48,7 +55,6 @@ config DRM_RADEON
 	select FB_CFB_FILLRECT
 	select FB_CFB_COPYAREA
 	select FB_CFB_IMAGEBLIT
-	select FB
 	select FRAMEBUFFER_CONSOLE if !EMBEDDED
 	select FW_LOADER
 	help
@@ -84,10 +90,10 @@ config DRM_I830
 config DRM_I915
 	tristate "i915 driver"
 	depends on AGP_INTEL
+	select DRM_MODE_HELPER
 	select FB_CFB_FILLRECT
 	select FB_CFB_COPYAREA
 	select FB_CFB_IMAGEBLIT
-	select FB
 	select FRAMEBUFFER_CONSOLE if !EMBEDDED
 	# i915 depends on ACPI_VIDEO when ACPI is enabled
 	# but for select to work, need to select ACPI_VIDEO's dependencies, ick
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 99071684de2..7e96d74242f 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -10,12 +10,15 @@ drm-y       :=	drm_auth.o drm_bufs.o drm_cache.o \
 		drm_lock.o drm_memory.o drm_proc.o drm_stub.o drm_vm.o \
 		drm_agpsupport.o drm_scatter.o ati_pcigart.o drm_pci.o \
 		drm_sysfs.o drm_hashtab.o drm_sman.o drm_mm.o \
-		drm_crtc.o drm_crtc_helper.o drm_modes.o drm_edid.o \
-		drm_info.o drm_debugfs.o drm_encoder_slave.o \
-		drm_fb_helper.o
+		drm_crtc.o drm_modes.o drm_edid.o \
+		drm_info.o drm_debugfs.o drm_encoder_slave.o
 
 drm-$(CONFIG_COMPAT) += drm_ioc32.o
 
+drm_helper-y := drm_fb_helper.o drm_crtc_helper.o
+
+obj-$(CONFIG_DRM_MODE_HELPER) += drm_helper.o
+
 obj-$(CONFIG_DRM)	+= drm.o
 obj-$(CONFIG_DRM_TTM)	+= ttm/
 obj-$(CONFIG_DRM_TDFX)	+= tdfx/
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index c20fcdc6549..ba728ad77f2 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -168,6 +168,7 @@ char *drm_get_encoder_name(struct drm_encoder *encoder)
 		 encoder->base.id);
 	return buf;
 }
+EXPORT_SYMBOL(drm_get_encoder_name);
 
 char *drm_get_connector_name(struct drm_connector *connector)
 {
diff --git a/drivers/gpu/drm/radeon/Kconfig b/drivers/gpu/drm/radeon/Kconfig
index 2168d67f09a..fdd9c894992 100644
--- a/drivers/gpu/drm/radeon/Kconfig
+++ b/drivers/gpu/drm/radeon/Kconfig
@@ -1,6 +1,7 @@
 config DRM_RADEON_KMS
 	bool "Enable modesetting on radeon by default"
 	depends on DRM_RADEON
+	select DRM_MODE_HELPER
 	select DRM_TTM
 	help
 	  Choose this option if you want kernel modesetting enabled by default,
-- 
cgit v1.2.3


From aa9eaa1f0962152d0bde821149d82fe7b70a6f92 Mon Sep 17 00:00:00 2001
From: Zhao Yakui <yakui.zhao@intel.com>
Date: Thu, 3 Sep 2009 09:33:46 +0800
Subject: drm/kms: Add the default mode table

When we add a standard timing mode in UMS, we will first check whether it can
be found in default mode table. If it can't be found, then we will use cvt/gtf
to add the standard timing mode.
Add the default mode table so that we can check whether the given mode
can be found in the default mode table as what we have done in UMS mode.

If the status of one output device is connected but there is no EDID, it will
have no correct mode. In such case we can add some default modes for it. Of
course we only add the modes in the default modes list that visible part is not
greater than 1024x768.

The default mode is autogenerated from the DMT spec. And it is copied from
xserver/hw/xfree86/modes/xf86EdidModes.c. But the mode with reduced blank
feature is removed.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_edid.c | 237 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 237 insertions(+)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index e4f1cb5fa60..e64eb6bbce1 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -243,6 +243,243 @@ static void edid_fixup_preferred(struct drm_connector *connector,
 	preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
 }
 
+/*
+ * Add the Autogenerated from the DMT spec.
+ * This table is copied from xfree86/modes/xf86EdidModes.c.
+ * But the mode with Reduced blank feature is deleted.
+ */
+static struct drm_display_mode drm_dmt_modes[] = {
+	/* 640x350@85Hz */
+	{ DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
+		   736, 832, 0, 350, 382, 385, 445, 0,
+		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+	/* 640x400@85Hz */
+	{ DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
+		   736, 832, 0, 400, 401, 404, 445, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 720x400@85Hz */
+	{ DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
+		   828, 936, 0, 400, 401, 404, 446, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 640x480@60Hz */
+	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
+		   752, 800, 0, 480, 489, 492, 525, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
+	/* 640x480@72Hz */
+	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
+		   704, 832, 0, 480, 489, 492, 520, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
+	/* 640x480@75Hz */
+	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
+		   720, 840, 0, 480, 481, 484, 500, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
+	/* 640x480@85Hz */
+	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
+		   752, 832, 0, 480, 481, 484, 509, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
+	/* 800x600@56Hz */
+	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
+		   896, 1024, 0, 600, 601, 603, 625, 0,
+		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 800x600@60Hz */
+	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
+		   968, 1056, 0, 600, 601, 605, 628, 0,
+		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 800x600@72Hz */
+	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
+		   976, 1040, 0, 600, 637, 643, 666, 0,
+		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 800x600@75Hz */
+	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
+		   896, 1056, 0, 600, 601, 604, 625, 0,
+		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 800x600@85Hz */
+	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
+		   896, 1048, 0, 600, 601, 604, 631, 0,
+		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 848x480@60Hz */
+	{ DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
+		   976, 1088, 0, 480, 486, 494, 517, 0,
+		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1024x768@43Hz, interlace */
+	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
+		   1208, 1264, 0, 768, 768, 772, 817, 0,
+		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
+			DRM_MODE_FLAG_INTERLACE) },
+	/* 1024x768@60Hz */
+	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
+		   1184, 1344, 0, 768, 771, 777, 806, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
+	/* 1024x768@70Hz */
+	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
+		   1184, 1328, 0, 768, 771, 777, 806, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
+	/* 1024x768@75Hz */
+	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
+		   1136, 1312, 0, 768, 769, 772, 800, 0,
+		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1024x768@85Hz */
+	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
+		   1072, 1376, 0, 768, 769, 772, 808, 0,
+		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1152x864@75Hz */
+	{ DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
+		   1344, 1600, 0, 864, 865, 868, 900, 0,
+		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1280x768@60Hz */
+	{ DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
+		   1472, 1664, 0, 768, 771, 778, 798, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1280x768@75Hz */
+	{ DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
+		   1488, 1696, 0, 768, 771, 778, 805, 0,
+		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+	/* 1280x768@85Hz */
+	{ DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
+		   1496, 1712, 0, 768, 771, 778, 809, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1280x800@60Hz */
+	{ DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
+		   1480, 1680, 0, 800, 803, 809, 831, 0,
+		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
+	/* 1280x800@75Hz */
+	{ DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
+		   1488, 1696, 0, 800, 803, 809, 838, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1280x800@85Hz */
+	{ DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
+		   1496, 1712, 0, 800, 803, 809, 843, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1280x960@60Hz */
+	{ DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
+		   1488, 1800, 0, 960, 961, 964, 1000, 0,
+		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1280x960@85Hz */
+	{ DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
+		   1504, 1728, 0, 960, 961, 964, 1011, 0,
+		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1280x1024@60Hz */
+	{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
+		   1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
+		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1280x1024@75Hz */
+	{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
+		   1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
+		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1280x1024@85Hz */
+	{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
+		   1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
+		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1360x768@60Hz */
+	{ DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
+		   1536, 1792, 0, 768, 771, 777, 795, 0,
+		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1440x1050@60Hz */
+	{ DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
+		   1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1440x1050@75Hz */
+	{ DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
+		   1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1440x1050@85Hz */
+	{ DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
+		   1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1440x900@60Hz */
+	{ DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
+		   1672, 1904, 0, 900, 903, 909, 934, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1440x900@75Hz */
+	{ DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
+		   1688, 1936, 0, 900, 903, 909, 942, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1440x900@85Hz */
+	{ DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
+		   1696, 1952, 0, 900, 903, 909, 948, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1600x1200@60Hz */
+	{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
+		   1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
+		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1600x1200@65Hz */
+	{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
+		   1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
+		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1600x1200@70Hz */
+	{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
+		   1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
+		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1600x1200@75Hz */
+	{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 2025000, 1600, 1664,
+		   1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
+		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1600x1200@85Hz */
+	{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
+		   1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
+		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1680x1050@60Hz */
+	{ DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
+		   1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1680x1050@75Hz */
+	{ DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
+		   1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1680x1050@85Hz */
+	{ DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
+		   1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1792x1344@60Hz */
+	{ DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
+		   2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1729x1344@75Hz */
+	{ DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
+		   2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1853x1392@60Hz */
+	{ DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
+		   2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1856x1392@75Hz */
+	{ DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
+		   2208, 2560, 0, 1392, 1395, 1399, 1500, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1920x1200@60Hz */
+	{ DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
+		   2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1920x1200@75Hz */
+	{ DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
+		   2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1920x1200@85Hz */
+	{ DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
+		   2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1920x1440@60Hz */
+	{ DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
+		   2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 1920x1440@75Hz */
+	{ DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
+		   2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 2560x1600@60Hz */
+	{ DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
+		   3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 2560x1600@75HZ */
+	{ DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
+		   3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+	/* 2560x1600@85HZ */
+	{ DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
+		   3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
+		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
+};
+
 /**
  * drm_mode_std - convert standard mode info (width, height, refresh) into mode
  * @t: standard timing params
-- 
cgit v1.2.3


From 559ee21d261a54c42594ef9405d27e9008eedf44 Mon Sep 17 00:00:00 2001
From: Zhao Yakui <yakui.zhao@intel.com>
Date: Thu, 3 Sep 2009 09:33:47 +0800
Subject: drm/kms: try to find the std mode in DMT table

When we need to add the standard timing mode, we will firstly check whether it
can be found in DMT table by comparing the hdisplay/vdisplay/vfresh_rate.
If it can't be found, then we will use the cvt/gtf to add the required mode.
If it can be found, it will be returned.

At the same time the function of drm_mode_vrefresh is also fixed. It will
return the result of actual refresh_rate plus 0.5.
For example:
When the calculated value is 84.9, then the fresh_rate is 85.
When the calculated value is 70.02, then the fresh_rate is 70.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_edid.c  | 40 +++++++++++++++++++++++++++++++++-------
 drivers/gpu/drm/drm_modes.c | 11 ++++++-----
 2 files changed, 39 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index e64eb6bbce1..f84a98f2e37 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -480,6 +480,26 @@ static struct drm_display_mode drm_dmt_modes[] = {
 		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 };
 
+static struct drm_display_mode *drm_find_dmt(struct drm_device *dev,
+			int hsize, int vsize, int fresh)
+{
+	int i, count;
+	struct drm_display_mode *ptr, *mode;
+
+	count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode);
+	mode = NULL;
+	for (i = 0; i < count; i++) {
+		ptr = &drm_dmt_modes[i];
+		if (hsize == ptr->hdisplay &&
+			vsize == ptr->vdisplay &&
+			fresh == drm_mode_vrefresh(ptr)) {
+			/* get the expected default mode */
+			mode = drm_mode_duplicate(dev, ptr);
+			break;
+		}
+	}
+	return mode;
+}
 /**
  * drm_mode_std - convert standard mode info (width, height, refresh) into mode
  * @t: standard timing params
@@ -516,16 +536,22 @@ struct drm_display_mode *drm_mode_std(struct drm_device *dev,
 		vsize = (hsize * 4) / 5;
 	else
 		vsize = (hsize * 9) / 16;
-
+	/* HDTV hack */
+	if (hsize == 1360 && vsize == 765 && vrefresh_rate == 60) {
+		mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
+		mode->hdisplay = 1366;
+		mode->vsync_start = mode->vsync_start - 1;
+		mode->vsync_end = mode->vsync_end - 1;
+		return mode;
+	}
 	mode = NULL;
+	/* check whether it can be found in default mode table */
+	mode = drm_find_dmt(dev, hsize, vsize, vrefresh_rate);
+	if (mode)
+		return mode;
+
 	switch (timing_level) {
 	case LEVEL_DMT:
-		mode = drm_mode_create(dev);
-		if (mode) {
-			mode->hdisplay = hsize;
-			mode->vdisplay = vsize;
-			drm_mode_set_name(mode);
-		}
 		break;
 	case LEVEL_GTF:
 		mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index ab6e70eadc5..49404ce1666 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -566,7 +566,9 @@ EXPORT_SYMBOL(drm_mode_height);
  * FIXME: why is this needed?  shouldn't vrefresh be set already?
  *
  * RETURNS:
- * Vertical refresh rate of @mode x 1000. For precision reasons.
+ * Vertical refresh rate. It will be the result of actual value plus 0.5.
+ * If it is 70.288, it will return 70Hz.
+ * If it is 59.6, it will return 60Hz.
  */
 int drm_mode_vrefresh(struct drm_display_mode *mode)
 {
@@ -576,14 +578,13 @@ int drm_mode_vrefresh(struct drm_display_mode *mode)
 	if (mode->vrefresh > 0)
 		refresh = mode->vrefresh;
 	else if (mode->htotal > 0 && mode->vtotal > 0) {
+		int vtotal;
+		vtotal = mode->vtotal;
 		/* work out vrefresh the value will be x1000 */
 		calc_val = (mode->clock * 1000);
-
 		calc_val /= mode->htotal;
-		calc_val *= 1000;
-		calc_val /= mode->vtotal;
+		refresh = (calc_val + vtotal / 2) / vtotal;
 
-		refresh = calc_val;
 		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 			refresh *= 2;
 		if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
-- 
cgit v1.2.3


From f0fda0a47b26aba986fe65897891956c1792b526 Mon Sep 17 00:00:00 2001
From: Zhao Yakui <yakui.zhao@intel.com>
Date: Thu, 3 Sep 2009 09:33:48 +0800
Subject: drm/kms: add a function that can add the mode for the output device
 without EDID

Add a function that can be used to add the default mode for the output device
without EDID.
It will add the default mode that meets with the requirements of given
hdisplay/vdisplay limit.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_edid.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++
 include/drm/drm_crtc.h     |  2 ++
 2 files changed, 48 insertions(+)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index f84a98f2e37..e2d5f515f7b 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1215,3 +1215,49 @@ int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
 	return num_modes;
 }
 EXPORT_SYMBOL(drm_add_edid_modes);
+
+/**
+ * drm_add_modes_noedid - add modes for the connectors without EDID
+ * @connector: connector we're probing
+ * @hdisplay: the horizontal display limit
+ * @vdisplay: the vertical display limit
+ *
+ * Add the specified modes to the connector's mode list. Only when the
+ * hdisplay/vdisplay is not beyond the given limit, it will be added.
+ *
+ * Return number of modes added or 0 if we couldn't find any.
+ */
+int drm_add_modes_noedid(struct drm_connector *connector,
+			int hdisplay, int vdisplay)
+{
+	int i, count, num_modes = 0;
+	struct drm_display_mode *mode, *ptr;
+	struct drm_device *dev = connector->dev;
+
+	count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode);
+	if (hdisplay < 0)
+		hdisplay = 0;
+	if (vdisplay < 0)
+		vdisplay = 0;
+
+	for (i = 0; i < count; i++) {
+		ptr = &drm_dmt_modes[i];
+		if (hdisplay && vdisplay) {
+			/*
+			 * Only when two are valid, they will be used to check
+			 * whether the mode should be added to the mode list of
+			 * the connector.
+			 */
+			if (ptr->hdisplay > hdisplay ||
+					ptr->vdisplay > vdisplay)
+				continue;
+		}
+		mode = drm_mode_duplicate(dev, ptr);
+		if (mode) {
+			drm_mode_probed_add(connector, mode);
+			num_modes++;
+		}
+	}
+	return num_modes;
+}
+EXPORT_SYMBOL(drm_add_modes_noedid);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index b0427a70fcb..ae1e9e16695 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -750,4 +750,6 @@ extern struct drm_display_mode *drm_cvt_mode(struct drm_device *dev,
 extern struct drm_display_mode *drm_gtf_mode(struct drm_device *dev,
 				int hdisplay, int vdisplay, int vrefresh,
 				bool interlaced, int margins);
+extern int drm_add_modes_noedid(struct drm_connector *connector,
+				int hdisplay, int vdisplay);
 #endif /* __DRM_CRTC_H__ */
-- 
cgit v1.2.3


From 50fe4cfdc759fb3c0cffc3b90281efb139631fb7 Mon Sep 17 00:00:00 2001
From: ykzhao <yakui.zhao@intel.com>
Date: Thu, 3 Sep 2009 14:30:04 +0800
Subject: drm/kms/i915: Add the default mode for CRT output without EDID

Add the default mode for every output device when there
is no mode for it.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_crtc_helper.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index e7e6c25b560..6f4b4446fcd 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -109,8 +109,11 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector,
 	}
 
 	count = (*connector_funcs->get_modes)(connector);
-	if (!count)
-		return 0;
+	if (!count) {
+		count = drm_add_modes_noedid(connector, 800, 600);
+		if (!count)
+			return 0;
+	}
 
 	drm_mode_connector_list_update(connector);
 
-- 
cgit v1.2.3


From 575dc34ee0de867ba83abf25998e0963bff451fa Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 7 Sep 2009 18:43:26 +1000
Subject: drm/kms: remove old std mode fallback code.

The new code adds modes in the helper, which makes more sense
I disliked the non-driver code adding modes.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_crtc_helper.c | 56 ++-------------------------------------
 1 file changed, 2 insertions(+), 54 deletions(-)

diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index 6f4b4446fcd..c9a50c72933 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -33,15 +33,6 @@
 #include "drm_crtc.h"
 #include "drm_crtc_helper.h"
 
-/*
- * Detailed mode info for 800x600@60Hz
- */
-static struct drm_display_mode std_modes[] = {
-	{ DRM_MODE("800x600", DRM_MODE_TYPE_DEFAULT, 40000, 800, 840,
-		   968, 1056, 0, 600, 601, 605, 628, 0,
-		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
-};
-
 static void drm_mode_validate_flag(struct drm_connector *connector,
 				   int flags)
 {
@@ -133,7 +124,6 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector,
 								   mode);
 	}
 
-
 	drm_mode_prune_invalid(dev, &connector->modes, true);
 
 	if (list_empty(&connector->modes))
@@ -169,40 +159,6 @@ int drm_helper_probe_connector_modes(struct drm_device *dev, uint32_t maxX,
 }
 EXPORT_SYMBOL(drm_helper_probe_connector_modes);
 
-static void drm_helper_add_std_modes(struct drm_device *dev,
-				     struct drm_connector *connector)
-{
-	struct drm_display_mode *mode, *t;
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(std_modes); i++) {
-		struct drm_display_mode *stdmode;
-
-		/*
-		 * When no valid EDID modes are available we end up
-		 * here and bailed in the past, now we add some standard
-		 * modes and move on.
-		 */
-		stdmode = drm_mode_duplicate(dev, &std_modes[i]);
-		drm_mode_probed_add(connector, stdmode);
-		drm_mode_list_concat(&connector->probed_modes,
-				     &connector->modes);
-
-		DRM_DEBUG_KMS("Adding mode %s to %s\n", stdmode->name,
-			  drm_get_connector_name(connector));
-	}
-	drm_mode_sort(&connector->modes);
-
-	DRM_DEBUG_KMS("Added std modes on %s\n",
-			drm_get_connector_name(connector));
-	list_for_each_entry_safe(mode, t, &connector->modes, head) {
-		mode->vrefresh = drm_mode_vrefresh(mode);
-
-		drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
-		drm_mode_debug_printmodeline(mode);
-	}
-}
-
 /**
  * drm_helper_encoder_in_use - check if a given encoder is in use
  * @encoder: encoder to check
@@ -982,7 +938,6 @@ bool drm_helper_plugged_event(struct drm_device *dev)
  */
 bool drm_helper_initial_config(struct drm_device *dev)
 {
-	struct drm_connector *connector;
 	int count = 0;
 
 	count = drm_helper_probe_connector_modes(dev,
@@ -990,16 +945,9 @@ bool drm_helper_initial_config(struct drm_device *dev)
 						 dev->mode_config.max_height);
 
 	/*
-	 * None of the available connectors had any modes, so add some
-	 * and try to light them up anyway
+	 * we shouldn't end up with no modes here.
 	 */
-	if (!count) {
-		DRM_ERROR("connectors have no modes, using standard modes\n");
-		list_for_each_entry(connector,
-				    &dev->mode_config.connector_list,
-				    head)
-			drm_helper_add_std_modes(dev, connector);
-	}
+	WARN(!count, "Connected connector with 0 modes\n");
 
 	drm_setup_crtcs(dev);
 
-- 
cgit v1.2.3


From 551ebd837c75fc75df81811a18b7136c39cab487 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 1 Sep 2009 15:25:57 +1000
Subject: drm/radeon/kms: add rn50/r100/r200 CS tracker.

This adds the command stream checker for the RN50, R100 and R200 cards.

It stops any access to 3D registers on RN50, and does checks
on buffer sizes on the r100/r200 cards. It also fixes some texture
sizing checks on r300.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/Makefile      |  15 +-
 drivers/gpu/drm/radeon/r100.c        | 811 +++++++++++++++++++++++++++++------
 drivers/gpu/drm/radeon/r100_track.h  | 124 ++++++
 drivers/gpu/drm/radeon/r200.c        | 456 ++++++++++++++++++++
 drivers/gpu/drm/radeon/r300.c        | 363 ++--------------
 drivers/gpu/drm/radeon/radeon.h      |   6 +
 drivers/gpu/drm/radeon/radeon_asic.h |   1 +
 drivers/gpu/drm/radeon/radeon_reg.h  |  57 ++-
 drivers/gpu/drm/radeon/reg_srcs/r100 | 105 +++++
 drivers/gpu/drm/radeon/reg_srcs/r200 | 184 ++++++++
 drivers/gpu/drm/radeon/reg_srcs/rn50 |  30 ++
 11 files changed, 1712 insertions(+), 440 deletions(-)
 create mode 100644 drivers/gpu/drm/radeon/r100_track.h
 create mode 100644 drivers/gpu/drm/radeon/r200.c
 create mode 100644 drivers/gpu/drm/radeon/reg_srcs/r100
 create mode 100644 drivers/gpu/drm/radeon/reg_srcs/r200
 create mode 100644 drivers/gpu/drm/radeon/reg_srcs/rn50

diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index b2213a576a8..6fb84296249 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -11,6 +11,15 @@ hostprogs-y := mkregtable
 quiet_cmd_mkregtable = MKREGTABLE $@
       cmd_mkregtable = $(obj)/mkregtable $< > $@
 
+$(obj)/rn50_reg_safe.h: $(src)/reg_srcs/rn50 $(obj)/mkregtable
+	$(call if_changed,mkregtable)
+
+$(obj)/r100_reg_safe.h: $(src)/reg_srcs/r100 $(obj)/mkregtable
+	$(call if_changed,mkregtable)
+
+$(obj)/r200_reg_safe.h: $(src)/reg_srcs/r200 $(obj)/mkregtable
+	$(call if_changed,mkregtable)
+
 $(obj)/rv515_reg_safe.h: $(src)/reg_srcs/rv515 $(obj)/mkregtable
 	$(call if_changed,mkregtable)
 
@@ -20,6 +29,10 @@ $(obj)/r300_reg_safe.h: $(src)/reg_srcs/r300 $(obj)/mkregtable
 $(obj)/rs600_reg_safe.h: $(src)/reg_srcs/rs600 $(obj)/mkregtable
 	$(call if_changed,mkregtable)
 
+$(obj)/r100.o: $(obj)/r100_reg_safe.h $(obj)/rn50_reg_safe.h
+
+$(obj)/r200.o: $(obj)/r200_reg_safe.h
+
 $(obj)/rv515.o: $(obj)/rv515_reg_safe.h
 
 $(obj)/r300.o: $(obj)/r300_reg_safe.h
@@ -34,7 +47,7 @@ radeon-$(CONFIG_DRM_RADEON_KMS) += radeon_device.o radeon_kms.o \
 	radeon_clocks.o radeon_fb.o radeon_gem.o radeon_ring.o radeon_irq_kms.o \
 	radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \
 	rs400.o rs600.o rs690.o rv515.o r520.o r600.o rs780.o rv770.o \
-	radeon_test.o
+	radeon_test.o r200.o
 
 radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
 
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 44f34f8e2b3..ee3ab62417e 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -34,6 +34,9 @@
 #include <linux/firmware.h>
 #include <linux/platform_device.h>
 
+#include "r100_reg_safe.h"
+#include "rn50_reg_safe.h"
+
 /* Firmware Names */
 #define FIRMWARE_R100		"radeon/R100_cp.bin"
 #define FIRMWARE_R200		"radeon/R200_cp.bin"
@@ -51,11 +54,14 @@ MODULE_FIRMWARE(FIRMWARE_RS690);
 MODULE_FIRMWARE(FIRMWARE_RS600);
 MODULE_FIRMWARE(FIRMWARE_R520);
 
+#include "r100_track.h"
+
 /* This files gather functions specifics to:
  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  *
  * Some of these functions might be used by newer ASICs.
  */
+int r200_init(struct radeon_device *rdev);
 void r100_hdp_reset(struct radeon_device *rdev);
 void r100_gpu_init(struct radeon_device *rdev);
 int r100_gui_wait_for_idle(struct radeon_device *rdev);
@@ -1017,147 +1023,356 @@ int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
 	return 0;
 }
 
+static int r100_get_vtx_size(uint32_t vtx_fmt)
+{
+	int vtx_size;
+	vtx_size = 2;
+	/* ordered according to bits in spec */
+	if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
+		vtx_size++;
+	if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
+		vtx_size += 3;
+	if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
+		vtx_size++;
+	if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
+		vtx_size++;
+	if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
+		vtx_size += 3;
+	if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
+		vtx_size++;
+	if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
+		vtx_size++;
+	if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
+		vtx_size += 2;
+	if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
+		vtx_size += 2;
+	if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
+		vtx_size++;
+	if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
+		vtx_size += 2;
+	if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
+		vtx_size++;
+	if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
+		vtx_size += 2;
+	if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
+		vtx_size++;
+	if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
+		vtx_size++;
+	/* blend weight */
+	if (vtx_fmt & (0x7 << 15))
+		vtx_size += (vtx_fmt >> 15) & 0x7;
+	if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
+		vtx_size += 3;
+	if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
+		vtx_size += 2;
+	if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
+		vtx_size++;
+	if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
+		vtx_size++;
+	if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
+		vtx_size++;
+	if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
+		vtx_size++;
+	return vtx_size;
+}
+
 static int r100_packet0_check(struct radeon_cs_parser *p,
-			      struct radeon_cs_packet *pkt)
+			      struct radeon_cs_packet *pkt,
+			      unsigned idx, unsigned reg)
 {
 	struct radeon_cs_chunk *ib_chunk;
 	struct radeon_cs_reloc *reloc;
+	struct r100_cs_track *track;
 	volatile uint32_t *ib;
 	uint32_t tmp;
-	unsigned reg;
-	unsigned i;
-	unsigned idx;
-	bool onereg;
 	int r;
+	int i, face;
 	u32 tile_flags = 0;
 
 	ib = p->ib->ptr;
 	ib_chunk = &p->chunks[p->chunk_ib_idx];
-	idx = pkt->idx + 1;
-	reg = pkt->reg;
-	onereg = false;
-	if (CP_PACKET0_GET_ONE_REG_WR(ib_chunk->kdata[pkt->idx])) {
-		onereg = true;
-	}
-	for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
-		switch (reg) {
-		case RADEON_CRTC_GUI_TRIG_VLINE:
-			r = r100_cs_packet_parse_vline(p);
-			if (r) {
-				DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
-						idx, reg);
-				r100_cs_dump_packet(p, pkt);
-				return r;
-			}
-			break;
+	track = (struct r100_cs_track *)p->track;
+
+	switch (reg) {
+	case RADEON_CRTC_GUI_TRIG_VLINE:
+		r = r100_cs_packet_parse_vline(p);
+		if (r) {
+			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+				  idx, reg);
+			r100_cs_dump_packet(p, pkt);
+			return r;
+		}
+		break;
 		/* FIXME: only allow PACKET3 blit? easier to check for out of
 		 * range access */
-		case RADEON_DST_PITCH_OFFSET:
-		case RADEON_SRC_PITCH_OFFSET:
-			r = r100_cs_packet_next_reloc(p, &reloc);
-			if (r) {
-				DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
-					  idx, reg);
-				r100_cs_dump_packet(p, pkt);
-				return r;
-			}
-			tmp = ib_chunk->kdata[idx] & 0x003fffff;
-			tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
-
-			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
-				tile_flags |= RADEON_DST_TILE_MACRO;
-			if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
-				if (reg == RADEON_SRC_PITCH_OFFSET) {
-					DRM_ERROR("Cannot src blit from microtiled surface\n");
-					r100_cs_dump_packet(p, pkt);
-					return -EINVAL;
-				}
-				tile_flags |= RADEON_DST_TILE_MICRO;
-			}
+	case RADEON_DST_PITCH_OFFSET:
+	case RADEON_SRC_PITCH_OFFSET:
+		r = r100_reloc_pitch_offset(p, pkt, idx, reg);
+		if (r)
+			return r;
+		break;
+	case RADEON_RB3D_DEPTHOFFSET:
+		r = r100_cs_packet_next_reloc(p, &reloc);
+		if (r) {
+			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+				  idx, reg);
+			r100_cs_dump_packet(p, pkt);
+			return r;
+		}
+		track->zb.robj = reloc->robj;
+		track->zb.offset = ib_chunk->kdata[idx];
+		ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+		break;
+	case RADEON_RB3D_COLOROFFSET:
+		r = r100_cs_packet_next_reloc(p, &reloc);
+		if (r) {
+			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+				  idx, reg);
+			r100_cs_dump_packet(p, pkt);
+			return r;
+		}
+		track->cb[0].robj = reloc->robj;
+		track->cb[0].offset = ib_chunk->kdata[idx];
+		ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+		break;
+	case RADEON_PP_TXOFFSET_0:
+	case RADEON_PP_TXOFFSET_1:
+	case RADEON_PP_TXOFFSET_2:
+		i = (reg - RADEON_PP_TXOFFSET_0) / 24;
+		r = r100_cs_packet_next_reloc(p, &reloc);
+		if (r) {
+			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+				  idx, reg);
+			r100_cs_dump_packet(p, pkt);
+			return r;
+		}
+		ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+		track->textures[i].robj = reloc->robj;
+		break;
+	case RADEON_PP_CUBIC_OFFSET_T0_0:
+	case RADEON_PP_CUBIC_OFFSET_T0_1:
+	case RADEON_PP_CUBIC_OFFSET_T0_2:
+	case RADEON_PP_CUBIC_OFFSET_T0_3:
+	case RADEON_PP_CUBIC_OFFSET_T0_4:
+		i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
+		r = r100_cs_packet_next_reloc(p, &reloc);
+		if (r) {
+			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+				  idx, reg);
+			r100_cs_dump_packet(p, pkt);
+			return r;
+		}
+		track->textures[0].cube_info[i].offset = ib_chunk->kdata[idx];
+		ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+		track->textures[0].cube_info[i].robj = reloc->robj;
+		break;
+	case RADEON_PP_CUBIC_OFFSET_T1_0:
+	case RADEON_PP_CUBIC_OFFSET_T1_1:
+	case RADEON_PP_CUBIC_OFFSET_T1_2:
+	case RADEON_PP_CUBIC_OFFSET_T1_3:
+	case RADEON_PP_CUBIC_OFFSET_T1_4:
+		i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
+		r = r100_cs_packet_next_reloc(p, &reloc);
+		if (r) {
+			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+				  idx, reg);
+			r100_cs_dump_packet(p, pkt);
+			return r;
+		}
+		track->textures[1].cube_info[i].offset = ib_chunk->kdata[idx];
+		ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+		track->textures[1].cube_info[i].robj = reloc->robj;
+		break;
+	case RADEON_PP_CUBIC_OFFSET_T2_0:
+	case RADEON_PP_CUBIC_OFFSET_T2_1:
+	case RADEON_PP_CUBIC_OFFSET_T2_2:
+	case RADEON_PP_CUBIC_OFFSET_T2_3:
+	case RADEON_PP_CUBIC_OFFSET_T2_4:
+		i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
+		r = r100_cs_packet_next_reloc(p, &reloc);
+		if (r) {
+			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+				  idx, reg);
+			r100_cs_dump_packet(p, pkt);
+			return r;
+		}
+		track->textures[2].cube_info[i].offset = ib_chunk->kdata[idx];
+		ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+		track->textures[2].cube_info[i].robj = reloc->robj;
+		break;
+	case RADEON_RE_WIDTH_HEIGHT:
+		track->maxy = ((ib_chunk->kdata[idx] >> 16) & 0x7FF);
+		break;
+	case RADEON_RB3D_COLORPITCH:
+		r = r100_cs_packet_next_reloc(p, &reloc);
+		if (r) {
+			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+				  idx, reg);
+			r100_cs_dump_packet(p, pkt);
+			return r;
+		}
 
-			tmp |= tile_flags;
-			ib[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp;
-			break;
-		case RADEON_RB3D_DEPTHOFFSET:
-		case RADEON_RB3D_COLOROFFSET:
-		case R300_RB3D_COLOROFFSET0:
-		case R300_ZB_DEPTHOFFSET:
-		case R200_PP_TXOFFSET_0:
-		case R200_PP_TXOFFSET_1:
-		case R200_PP_TXOFFSET_2:
-		case R200_PP_TXOFFSET_3:
-		case R200_PP_TXOFFSET_4:
-		case R200_PP_TXOFFSET_5:
-		case RADEON_PP_TXOFFSET_0:
-		case RADEON_PP_TXOFFSET_1:
-		case RADEON_PP_TXOFFSET_2:
-		case R300_TX_OFFSET_0:
-		case R300_TX_OFFSET_0+4:
-		case R300_TX_OFFSET_0+8:
-		case R300_TX_OFFSET_0+12:
-		case R300_TX_OFFSET_0+16:
-		case R300_TX_OFFSET_0+20:
-		case R300_TX_OFFSET_0+24:
-		case R300_TX_OFFSET_0+28:
-		case R300_TX_OFFSET_0+32:
-		case R300_TX_OFFSET_0+36:
-		case R300_TX_OFFSET_0+40:
-		case R300_TX_OFFSET_0+44:
-		case R300_TX_OFFSET_0+48:
-		case R300_TX_OFFSET_0+52:
-		case R300_TX_OFFSET_0+56:
-		case R300_TX_OFFSET_0+60:
-			/* rn50 has no 3D engine so fail on any 3d setup */
-			if (ASIC_IS_RN50(p->rdev)) {
-				DRM_ERROR("attempt to use RN50 3D engine failed\n");
-				return -EINVAL;
-			}
-			r = r100_cs_packet_next_reloc(p, &reloc);
-			if (r) {
-				DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
-					  idx, reg);
-				r100_cs_dump_packet(p, pkt);
-				return r;
-			}
-			ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
-			break;
-		case R300_RB3D_COLORPITCH0:
-		case RADEON_RB3D_COLORPITCH:
-			r = r100_cs_packet_next_reloc(p, &reloc);
-			if (r) {
-				DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
-					  idx, reg);
-				r100_cs_dump_packet(p, pkt);
-				return r;
-			}
+		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+			tile_flags |= RADEON_COLOR_TILE_ENABLE;
+		if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
+			tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
 
-			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
-				tile_flags |= RADEON_COLOR_TILE_ENABLE;
-			if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
-				tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
+		tmp = ib_chunk->kdata[idx] & ~(0x7 << 16);
+		tmp |= tile_flags;
+		ib[idx] = tmp;
 
-			tmp = ib_chunk->kdata[idx] & ~(0x7 << 16);
-			tmp |= tile_flags;
-			ib[idx] = tmp;
+		track->cb[0].pitch = ib_chunk->kdata[idx] & RADEON_COLORPITCH_MASK;
+		break;
+	case RADEON_RB3D_DEPTHPITCH:
+		track->zb.pitch = ib_chunk->kdata[idx] & RADEON_DEPTHPITCH_MASK;
+		break;
+	case RADEON_RB3D_CNTL:
+		switch ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
+		case 7:
+		case 8:
+		case 9:
+		case 11:
+		case 12:
+			track->cb[0].cpp = 1;
 			break;
-		case RADEON_RB3D_ZPASS_ADDR:
-			r = r100_cs_packet_next_reloc(p, &reloc);
-			if (r) {
-				DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
-					  idx, reg);
-				r100_cs_dump_packet(p, pkt);
-				return r;
-			}
-			ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+		case 3:
+		case 4:
+		case 15:
+			track->cb[0].cpp = 2;
+			break;
+		case 6:
+			track->cb[0].cpp = 4;
+			break;
+		default:
+			DRM_ERROR("Invalid color buffer format (%d) !\n",
+				  ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
+			return -EINVAL;
+		}
+		track->z_enabled = !!(ib_chunk->kdata[idx] & RADEON_Z_ENABLE);
+		break;
+	case RADEON_RB3D_ZSTENCILCNTL:
+		switch (ib_chunk->kdata[idx] & 0xf) {
+		case 0:
+			track->zb.cpp = 2;
+			break;
+		case 2:
+		case 3:
+		case 4:
+		case 5:
+		case 9:
+		case 11:
+			track->zb.cpp = 4;
 			break;
 		default:
-			/* FIXME: we don't want to allow anyothers packet */
 			break;
 		}
-		if (onereg) {
-			/* FIXME: forbid onereg write to register on relocate */
+		break;
+	case RADEON_RB3D_ZPASS_ADDR:
+		r = r100_cs_packet_next_reloc(p, &reloc);
+		if (r) {
+			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+				  idx, reg);
+			r100_cs_dump_packet(p, pkt);
+			return r;
+		}
+		ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+		break;
+	case RADEON_PP_CNTL:
+		{
+			uint32_t temp = ib_chunk->kdata[idx] >> 4;
+			for (i = 0; i < track->num_texture; i++)
+				track->textures[i].enabled = !!(temp & (1 << i));
+		}
+		break;
+	case RADEON_SE_VF_CNTL:
+		track->vap_vf_cntl = ib_chunk->kdata[idx];
+		break;
+	case RADEON_SE_VTX_FMT:
+		track->vtx_size = r100_get_vtx_size(ib_chunk->kdata[idx]);
+		break;
+	case RADEON_PP_TEX_SIZE_0:
+	case RADEON_PP_TEX_SIZE_1:
+	case RADEON_PP_TEX_SIZE_2:
+		i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
+		track->textures[i].width = (ib_chunk->kdata[idx] & RADEON_TEX_USIZE_MASK) + 1;
+		track->textures[i].height = ((ib_chunk->kdata[idx] & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
+		break;
+	case RADEON_PP_TEX_PITCH_0:
+	case RADEON_PP_TEX_PITCH_1:
+	case RADEON_PP_TEX_PITCH_2:
+		i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
+		track->textures[i].pitch = ib_chunk->kdata[idx] + 32;
+		break;
+	case RADEON_PP_TXFILTER_0:
+	case RADEON_PP_TXFILTER_1:
+	case RADEON_PP_TXFILTER_2:
+		i = (reg - RADEON_PP_TXFILTER_0) / 24;
+		track->textures[i].num_levels = ((ib_chunk->kdata[idx] & RADEON_MAX_MIP_LEVEL_MASK)
+						 >> RADEON_MAX_MIP_LEVEL_SHIFT);
+		tmp = (ib_chunk->kdata[idx] >> 23) & 0x7;
+		if (tmp == 2 || tmp == 6)
+			track->textures[i].roundup_w = false;
+		tmp = (ib_chunk->kdata[idx] >> 27) & 0x7;
+		if (tmp == 2 || tmp == 6)
+			track->textures[i].roundup_h = false;
+		break;
+	case RADEON_PP_TXFORMAT_0:
+	case RADEON_PP_TXFORMAT_1:
+	case RADEON_PP_TXFORMAT_2:
+		i = (reg - RADEON_PP_TXFORMAT_0) / 24;
+		if (ib_chunk->kdata[idx] & RADEON_TXFORMAT_NON_POWER2) {
+			track->textures[i].use_pitch = 1;
+		} else {
+			track->textures[i].use_pitch = 0;
+			track->textures[i].width = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
+			track->textures[i].height = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
+		}
+		if (ib_chunk->kdata[idx] & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
+			track->textures[i].tex_coord_type = 2;
+		switch ((ib_chunk->kdata[idx] & RADEON_TXFORMAT_FORMAT_MASK)) {
+		case RADEON_TXFORMAT_I8:
+		case RADEON_TXFORMAT_RGB332:
+		case RADEON_TXFORMAT_Y8:
+			track->textures[i].cpp = 1;
+			break;
+		case RADEON_TXFORMAT_AI88:
+		case RADEON_TXFORMAT_ARGB1555:
+		case RADEON_TXFORMAT_RGB565:
+		case RADEON_TXFORMAT_ARGB4444:
+		case RADEON_TXFORMAT_VYUY422:
+		case RADEON_TXFORMAT_YVYU422:
+		case RADEON_TXFORMAT_DXT1:
+		case RADEON_TXFORMAT_SHADOW16:
+		case RADEON_TXFORMAT_LDUDV655:
+		case RADEON_TXFORMAT_DUDV88:
+			track->textures[i].cpp = 2;
 			break;
+		case RADEON_TXFORMAT_ARGB8888:
+		case RADEON_TXFORMAT_RGBA8888:
+		case RADEON_TXFORMAT_DXT23:
+		case RADEON_TXFORMAT_DXT45:
+		case RADEON_TXFORMAT_SHADOW32:
+		case RADEON_TXFORMAT_LDUDUV8888:
+			track->textures[i].cpp = 4;
+			break;
+		}
+		track->textures[i].cube_info[4].width = 1 << ((ib_chunk->kdata[idx] >> 16) & 0xf);
+		track->textures[i].cube_info[4].height = 1 << ((ib_chunk->kdata[idx] >> 20) & 0xf);
+		break;
+	case RADEON_PP_CUBIC_FACES_0:
+	case RADEON_PP_CUBIC_FACES_1:
+	case RADEON_PP_CUBIC_FACES_2:
+		tmp = ib_chunk->kdata[idx];
+		i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
+		for (face = 0; face < 4; face++) {
+			track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
+			track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
 		}
+		break;
+	default:
+		printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
+		       reg, idx);
+		return -EINVAL;
 	}
 	return 0;
 }
@@ -1186,6 +1401,7 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
 {
 	struct radeon_cs_chunk *ib_chunk;
 	struct radeon_cs_reloc *reloc;
+	struct r100_cs_track *track;
 	unsigned idx;
 	unsigned i, c;
 	volatile uint32_t *ib;
@@ -1194,9 +1410,11 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
 	ib = p->ib->ptr;
 	ib_chunk = &p->chunks[p->chunk_ib_idx];
 	idx = pkt->idx + 1;
+	track = (struct r100_cs_track *)p->track;
 	switch (pkt->opcode) {
 	case PACKET3_3D_LOAD_VBPNTR:
 		c = ib_chunk->kdata[idx++];
+		track->num_arrays = c;
 		for (i = 0; i < (c - 1); i += 2, idx += 3) {
 			r = r100_cs_packet_next_reloc(p, &reloc);
 			if (r) {
@@ -1206,6 +1424,9 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
 				return r;
 			}
 			ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
+			track->arrays[i + 0].robj = reloc->robj;
+			track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8;
+			track->arrays[i + 0].esize &= 0x7F;
 			r = r100_cs_packet_next_reloc(p, &reloc);
 			if (r) {
 				DRM_ERROR("No reloc for packet3 %d\n",
@@ -1214,6 +1435,9 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
 				return r;
 			}
 			ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset);
+			track->arrays[i + 1].robj = reloc->robj;
+			track->arrays[i + 1].esize = ib_chunk->kdata[idx] >> 24;
+			track->arrays[i + 1].esize &= 0x7F;
 		}
 		if (c & 1) {
 			r = r100_cs_packet_next_reloc(p, &reloc);
@@ -1224,6 +1448,9 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
 				return r;
 			}
 			ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
+			track->arrays[i + 0].robj = reloc->robj;
+			track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8;
+			track->arrays[i + 0].esize &= 0x7F;
 		}
 		break;
 	case PACKET3_INDX_BUFFER:
@@ -1240,7 +1467,6 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
 		}
 		break;
 	case 0x23:
-		/* FIXME: cleanup */
 		/* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
 		r = r100_cs_packet_next_reloc(p, &reloc);
 		if (r) {
@@ -1249,18 +1475,71 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
 			return r;
 		}
 		ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+		track->num_arrays = 1;
+		track->vtx_size = r100_get_vtx_size(ib_chunk->kdata[idx+2]);
+
+		track->arrays[0].robj = reloc->robj;
+		track->arrays[0].esize = track->vtx_size;
+
+		track->max_indx = ib_chunk->kdata[idx+1];
+
+		track->vap_vf_cntl = ib_chunk->kdata[idx+3];
+		track->immd_dwords = pkt->count - 1;
+		r = r100_cs_track_check(p->rdev, track);
+		if (r)
+			return r;
 		break;
 	case PACKET3_3D_DRAW_IMMD:
+		if (((ib_chunk->kdata[idx+1] >> 4) & 0x3) != 3) {
+			DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
+			return -EINVAL;
+		}
+		track->vap_vf_cntl = ib_chunk->kdata[idx+1];
+		track->immd_dwords = pkt->count - 1;
+		r = r100_cs_track_check(p->rdev, track);
+		if (r)
+			return r;
+		break;
 		/* triggers drawing using in-packet vertex data */
 	case PACKET3_3D_DRAW_IMMD_2:
+		if (((ib_chunk->kdata[idx] >> 4) & 0x3) != 3) {
+			DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
+			return -EINVAL;
+		}
+		track->vap_vf_cntl = ib_chunk->kdata[idx];
+		track->immd_dwords = pkt->count;
+		r = r100_cs_track_check(p->rdev, track);
+		if (r)
+			return r;
+		break;
 		/* triggers drawing using in-packet vertex data */
 	case PACKET3_3D_DRAW_VBUF_2:
+		track->vap_vf_cntl = ib_chunk->kdata[idx];
+		r = r100_cs_track_check(p->rdev, track);
+		if (r)
+			return r;
+		break;
 		/* triggers drawing of vertex buffers setup elsewhere */
 	case PACKET3_3D_DRAW_INDX_2:
+		track->vap_vf_cntl = ib_chunk->kdata[idx];
+		r = r100_cs_track_check(p->rdev, track);
+		if (r)
+			return r;
+		break;
 		/* triggers drawing using indices to vertex buffer */
 	case PACKET3_3D_DRAW_VBUF:
+		track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
+		r = r100_cs_track_check(p->rdev, track);
+		if (r)
+			return r;
+		break;
 		/* triggers drawing of vertex buffers setup elsewhere */
 	case PACKET3_3D_DRAW_INDX:
+		track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
+		r = r100_cs_track_check(p->rdev, track);
+		if (r)
+			return r;
+		break;
 		/* triggers drawing using indices to vertex buffer */
 	case PACKET3_NOP:
 		break;
@@ -1274,8 +1553,11 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
 int r100_cs_parse(struct radeon_cs_parser *p)
 {
 	struct radeon_cs_packet pkt;
+	struct r100_cs_track track;
 	int r;
 
+	r100_cs_track_clear(p->rdev, &track);
+	p->track = &track;
 	do {
 		r = r100_cs_packet_parse(p, &pkt, p->idx);
 		if (r) {
@@ -1284,7 +1566,16 @@ int r100_cs_parse(struct radeon_cs_parser *p)
 		p->idx += pkt.count + 2;
 		switch (pkt.type) {
 			case PACKET_TYPE0:
-				r = r100_packet0_check(p, &pkt);
+				if (p->rdev->family >= CHIP_R200)
+					r = r100_cs_parse_packet0(p, &pkt,
+								  p->rdev->config.r100.reg_safe_bm,
+								  p->rdev->config.r100.reg_safe_bm_size,
+								  &r200_packet0_check);
+				else
+					r = r100_cs_parse_packet0(p, &pkt,
+								  p->rdev->config.r100.reg_safe_bm,
+								  p->rdev->config.r100.reg_safe_bm_size,
+								  &r100_packet0_check);
 				break;
 			case PACKET_TYPE2:
 				break;
@@ -1683,6 +1974,15 @@ void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 
 int r100_init(struct radeon_device *rdev)
 {
+	if (ASIC_IS_RN50(rdev)) {
+		rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
+		rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
+	} else if (rdev->family < CHIP_R200) {
+		rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
+		rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
+	} else {
+		return r200_init(rdev);
+	}
 	return 0;
 }
 
@@ -2383,3 +2683,274 @@ void r100_bandwidth_update(struct radeon_device *rdev)
 			  (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
 	}
 }
+
+static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
+{
+	DRM_ERROR("pitch                      %d\n", t->pitch);
+	DRM_ERROR("width                      %d\n", t->width);
+	DRM_ERROR("height                     %d\n", t->height);
+	DRM_ERROR("num levels                 %d\n", t->num_levels);
+	DRM_ERROR("depth                      %d\n", t->txdepth);
+	DRM_ERROR("bpp                        %d\n", t->cpp);
+	DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
+	DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
+	DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
+}
+
+static int r100_cs_track_cube(struct radeon_device *rdev,
+			      struct r100_cs_track *track, unsigned idx)
+{
+	unsigned face, w, h;
+	struct radeon_object *cube_robj;
+	unsigned long size;
+
+	for (face = 0; face < 5; face++) {
+		cube_robj = track->textures[idx].cube_info[face].robj;
+		w = track->textures[idx].cube_info[face].width;
+		h = track->textures[idx].cube_info[face].height;
+
+		size = w * h;
+		size *= track->textures[idx].cpp;
+
+		size += track->textures[idx].cube_info[face].offset;
+
+		if (size > radeon_object_size(cube_robj)) {
+			DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
+				  size, radeon_object_size(cube_robj));
+			r100_cs_track_texture_print(&track->textures[idx]);
+			return -1;
+		}
+	}
+	return 0;
+}
+
+static int r100_cs_track_texture_check(struct radeon_device *rdev,
+				       struct r100_cs_track *track)
+{
+	struct radeon_object *robj;
+	unsigned long size;
+	unsigned u, i, w, h;
+	int ret;
+
+	for (u = 0; u < track->num_texture; u++) {
+		if (!track->textures[u].enabled)
+			continue;
+		robj = track->textures[u].robj;
+		if (robj == NULL) {
+			DRM_ERROR("No texture bound to unit %u\n", u);
+			return -EINVAL;
+		}
+		size = 0;
+		for (i = 0; i <= track->textures[u].num_levels; i++) {
+			if (track->textures[u].use_pitch) {
+				if (rdev->family < CHIP_R300)
+					w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
+				else
+					w = track->textures[u].pitch / (1 << i);
+			} else {
+				w = track->textures[u].width / (1 << i);
+				if (rdev->family >= CHIP_RV515)
+					w |= track->textures[u].width_11;
+				if (track->textures[u].roundup_w)
+					w = roundup_pow_of_two(w);
+			}
+			h = track->textures[u].height / (1 << i);
+			if (rdev->family >= CHIP_RV515)
+				h |= track->textures[u].height_11;
+			if (track->textures[u].roundup_h)
+				h = roundup_pow_of_two(h);
+			size += w * h;
+		}
+		size *= track->textures[u].cpp;
+		switch (track->textures[u].tex_coord_type) {
+		case 0:
+			break;
+		case 1:
+			size *= (1 << track->textures[u].txdepth);
+			break;
+		case 2:
+			if (track->separate_cube) {
+				ret = r100_cs_track_cube(rdev, track, u);
+				if (ret)
+					return ret;
+			} else
+				size *= 6;
+			break;
+		default:
+			DRM_ERROR("Invalid texture coordinate type %u for unit "
+				  "%u\n", track->textures[u].tex_coord_type, u);
+			return -EINVAL;
+		}
+		if (size > radeon_object_size(robj)) {
+			DRM_ERROR("Texture of unit %u needs %lu bytes but is "
+				  "%lu\n", u, size, radeon_object_size(robj));
+			r100_cs_track_texture_print(&track->textures[u]);
+			return -EINVAL;
+		}
+	}
+	return 0;
+}
+
+int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
+{
+	unsigned i;
+	unsigned long size;
+	unsigned prim_walk;
+	unsigned nverts;
+
+	for (i = 0; i < track->num_cb; i++) {
+		if (track->cb[i].robj == NULL) {
+			DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
+			return -EINVAL;
+		}
+		size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
+		size += track->cb[i].offset;
+		if (size > radeon_object_size(track->cb[i].robj)) {
+			DRM_ERROR("[drm] Buffer too small for color buffer %d "
+				  "(need %lu have %lu) !\n", i, size,
+				  radeon_object_size(track->cb[i].robj));
+			DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
+				  i, track->cb[i].pitch, track->cb[i].cpp,
+				  track->cb[i].offset, track->maxy);
+			return -EINVAL;
+		}
+	}
+	if (track->z_enabled) {
+		if (track->zb.robj == NULL) {
+			DRM_ERROR("[drm] No buffer for z buffer !\n");
+			return -EINVAL;
+		}
+		size = track->zb.pitch * track->zb.cpp * track->maxy;
+		size += track->zb.offset;
+		if (size > radeon_object_size(track->zb.robj)) {
+			DRM_ERROR("[drm] Buffer too small for z buffer "
+				  "(need %lu have %lu) !\n", size,
+				  radeon_object_size(track->zb.robj));
+			DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
+				  track->zb.pitch, track->zb.cpp,
+				  track->zb.offset, track->maxy);
+			return -EINVAL;
+		}
+	}
+	prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
+	nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
+	switch (prim_walk) {
+	case 1:
+		for (i = 0; i < track->num_arrays; i++) {
+			size = track->arrays[i].esize * track->max_indx * 4;
+			if (track->arrays[i].robj == NULL) {
+				DRM_ERROR("(PW %u) Vertex array %u no buffer "
+					  "bound\n", prim_walk, i);
+				return -EINVAL;
+			}
+			if (size > radeon_object_size(track->arrays[i].robj)) {
+				DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
+					   "have %lu dwords\n", prim_walk, i,
+					   size >> 2,
+					   radeon_object_size(track->arrays[i].robj) >> 2);
+				DRM_ERROR("Max indices %u\n", track->max_indx);
+				return -EINVAL;
+			}
+		}
+		break;
+	case 2:
+		for (i = 0; i < track->num_arrays; i++) {
+			size = track->arrays[i].esize * (nverts - 1) * 4;
+			if (track->arrays[i].robj == NULL) {
+				DRM_ERROR("(PW %u) Vertex array %u no buffer "
+					  "bound\n", prim_walk, i);
+				return -EINVAL;
+			}
+			if (size > radeon_object_size(track->arrays[i].robj)) {
+				DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
+					   "have %lu dwords\n", prim_walk, i, size >> 2,
+					   radeon_object_size(track->arrays[i].robj) >> 2);
+				return -EINVAL;
+			}
+		}
+		break;
+	case 3:
+		size = track->vtx_size * nverts;
+		if (size != track->immd_dwords) {
+			DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
+				  track->immd_dwords, size);
+			DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
+				  nverts, track->vtx_size);
+			return -EINVAL;
+		}
+		break;
+	default:
+		DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
+			  prim_walk);
+		return -EINVAL;
+	}
+	return r100_cs_track_texture_check(rdev, track);
+}
+
+void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
+{
+	unsigned i, face;
+
+	if (rdev->family < CHIP_R300) {
+		track->num_cb = 1;
+		if (rdev->family <= CHIP_RS200)
+			track->num_texture = 3;
+		else
+			track->num_texture = 6;
+		track->maxy = 2048;
+		track->separate_cube = 1;
+	} else {
+		track->num_cb = 4;
+		track->num_texture = 16;
+		track->maxy = 4096;
+		track->separate_cube = 0;
+	}
+
+	for (i = 0; i < track->num_cb; i++) {
+		track->cb[i].robj = NULL;
+		track->cb[i].pitch = 8192;
+		track->cb[i].cpp = 16;
+		track->cb[i].offset = 0;
+	}
+	track->z_enabled = true;
+	track->zb.robj = NULL;
+	track->zb.pitch = 8192;
+	track->zb.cpp = 4;
+	track->zb.offset = 0;
+	track->vtx_size = 0x7F;
+	track->immd_dwords = 0xFFFFFFFFUL;
+	track->num_arrays = 11;
+	track->max_indx = 0x00FFFFFFUL;
+	for (i = 0; i < track->num_arrays; i++) {
+		track->arrays[i].robj = NULL;
+		track->arrays[i].esize = 0x7F;
+	}
+	for (i = 0; i < track->num_texture; i++) {
+		track->textures[i].pitch = 16536;
+		track->textures[i].width = 16536;
+		track->textures[i].height = 16536;
+		track->textures[i].width_11 = 1 << 11;
+		track->textures[i].height_11 = 1 << 11;
+		track->textures[i].num_levels = 12;
+		if (rdev->family <= CHIP_RS200) {
+			track->textures[i].tex_coord_type = 0;
+			track->textures[i].txdepth = 0;
+		} else {
+			track->textures[i].txdepth = 16;
+			track->textures[i].tex_coord_type = 1;
+		}
+		track->textures[i].cpp = 64;
+		track->textures[i].robj = NULL;
+		/* CS IB emission code makes sure texture unit are disabled */
+		track->textures[i].enabled = false;
+		track->textures[i].roundup_w = true;
+		track->textures[i].roundup_h = true;
+		if (track->separate_cube)
+			for (face = 0; face < 5; face++) {
+				track->textures[i].cube_info[face].robj = NULL;
+				track->textures[i].cube_info[face].width = 16536;
+				track->textures[i].cube_info[face].height = 16536;
+				track->textures[i].cube_info[face].offset = 0;
+			}
+	}
+}
diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h
new file mode 100644
index 00000000000..70a82eda394
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r100_track.h
@@ -0,0 +1,124 @@
+
+#define R100_TRACK_MAX_TEXTURE 3
+#define R200_TRACK_MAX_TEXTURE 6
+#define R300_TRACK_MAX_TEXTURE 16
+
+#define R100_MAX_CB 1
+#define R300_MAX_CB 4
+
+/*
+ * CS functions
+ */
+struct r100_cs_track_cb {
+	struct radeon_object	*robj;
+	unsigned		pitch;
+	unsigned		cpp;
+	unsigned		offset;
+};
+
+struct r100_cs_track_array {
+	struct radeon_object	*robj;
+	unsigned		esize;
+};
+
+struct r100_cs_cube_info {
+	struct radeon_object	*robj;
+	unsigned                offset;
+	unsigned		width;
+	unsigned		height;
+};
+
+struct r100_cs_track_texture {
+	struct radeon_object	*robj;
+	struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */
+	unsigned		pitch;
+	unsigned		width;
+	unsigned		height;
+	unsigned		num_levels;
+	unsigned		cpp;
+	unsigned		tex_coord_type;
+	unsigned		txdepth;
+	unsigned		width_11;
+	unsigned		height_11;
+	bool			use_pitch;
+	bool			enabled;
+	bool			roundup_w;
+	bool			roundup_h;
+};
+
+struct r100_cs_track_limits {
+	unsigned num_cb;
+	unsigned num_texture;
+	unsigned max_levels;
+};
+
+struct r100_cs_track {
+	struct radeon_device *rdev;
+	unsigned			num_cb;
+	unsigned                        num_texture;
+	unsigned			maxy;
+	unsigned			vtx_size;
+	unsigned			vap_vf_cntl;
+	unsigned			immd_dwords;
+	unsigned			num_arrays;
+	unsigned			max_indx;
+	struct r100_cs_track_array	arrays[11];
+	struct r100_cs_track_cb 	cb[R300_MAX_CB];
+	struct r100_cs_track_cb 	zb;
+	struct r100_cs_track_texture	textures[R300_TRACK_MAX_TEXTURE];
+	bool				z_enabled;
+	bool                            separate_cube;
+
+};
+
+int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
+void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track);
+int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
+			      struct radeon_cs_reloc **cs_reloc);
+void r100_cs_dump_packet(struct radeon_cs_parser *p,
+			 struct radeon_cs_packet *pkt);
+
+int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
+
+int r200_packet0_check(struct radeon_cs_parser *p,
+		       struct radeon_cs_packet *pkt,
+		       unsigned idx, unsigned reg);
+
+static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
+					  struct radeon_cs_packet *pkt,
+					  unsigned idx,
+					  unsigned reg)
+{
+	int r;
+	u32 tile_flags = 0;
+	u32 tmp;
+	struct radeon_cs_reloc *reloc;
+	struct radeon_cs_chunk *ib_chunk;
+
+	ib_chunk = &p->chunks[p->chunk_ib_idx];
+
+	r = r100_cs_packet_next_reloc(p, &reloc);
+	if (r) {
+		DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+			  idx, reg);
+		r100_cs_dump_packet(p, pkt);
+		return r;
+	}
+	tmp = ib_chunk->kdata[idx] & 0x003fffff;
+	tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
+
+	if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+		tile_flags |= RADEON_DST_TILE_MACRO;
+	if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
+		if (reg == RADEON_SRC_PITCH_OFFSET) {
+			DRM_ERROR("Cannot src blit from microtiled surface\n");
+			r100_cs_dump_packet(p, pkt);
+			return -EINVAL;
+		}
+		tile_flags |= RADEON_DST_TILE_MICRO;
+	}
+
+	tmp |= tile_flags;
+	p->ib->ptr[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp;
+	return 0;
+}
diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c
new file mode 100644
index 00000000000..568c74bfba3
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r200.c
@@ -0,0 +1,456 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#include "drmP.h"
+#include "drm.h"
+#include "radeon_drm.h"
+#include "radeon_reg.h"
+#include "radeon.h"
+
+#include "r200_reg_safe.h"
+
+#include "r100_track.h"
+
+static int r200_get_vtx_size_0(uint32_t vtx_fmt_0)
+{
+	int vtx_size, i;
+	vtx_size = 2;
+
+	if (vtx_fmt_0 & R200_VTX_Z0)
+		vtx_size++;
+	if (vtx_fmt_0 & R200_VTX_W0)
+		vtx_size++;
+	/* blend weight */
+	if (vtx_fmt_0 & (0x7 << R200_VTX_WEIGHT_COUNT_SHIFT))
+		vtx_size += (vtx_fmt_0 >> R200_VTX_WEIGHT_COUNT_SHIFT) & 0x7;
+	if (vtx_fmt_0 & R200_VTX_PV_MATRIX_SEL)
+		vtx_size++;
+	if (vtx_fmt_0 & R200_VTX_N0)
+		vtx_size += 3;
+	if (vtx_fmt_0 & R200_VTX_POINT_SIZE)
+		vtx_size++;
+	if (vtx_fmt_0 & R200_VTX_DISCRETE_FOG)
+		vtx_size++;
+	if (vtx_fmt_0 & R200_VTX_SHININESS_0)
+		vtx_size++;
+	if (vtx_fmt_0 & R200_VTX_SHININESS_1)
+		vtx_size++;
+	for (i = 0; i < 8; i++) {
+		int color_size = (vtx_fmt_0 >> (11 + 2*i)) & 0x3;
+		switch (color_size) {
+		case 0: break;
+		case 1: vtx_size++; break;
+		case 2: vtx_size += 3; break;
+		case 3: vtx_size += 4; break;
+		}
+	}
+	if (vtx_fmt_0 & R200_VTX_XY1)
+		vtx_size += 2;
+	if (vtx_fmt_0 & R200_VTX_Z1)
+		vtx_size++;
+	if (vtx_fmt_0 & R200_VTX_W1)
+		vtx_size++;
+	if (vtx_fmt_0 & R200_VTX_N1)
+		vtx_size += 3;
+	return vtx_size;
+}
+
+static int r200_get_vtx_size_1(uint32_t vtx_fmt_1)
+{
+	int vtx_size, i, tex_size;
+	vtx_size = 0;
+	for (i = 0; i < 6; i++) {
+		tex_size = (vtx_fmt_1 >> (i * 3)) & 0x7;
+		if (tex_size > 4)
+			continue;
+		vtx_size += tex_size;
+	}
+	return vtx_size;
+}
+
+int r200_packet0_check(struct radeon_cs_parser *p,
+		       struct radeon_cs_packet *pkt,
+		       unsigned idx, unsigned reg)
+{
+	struct radeon_cs_chunk *ib_chunk;
+	struct radeon_cs_reloc *reloc;
+	struct r100_cs_track *track;
+	volatile uint32_t *ib;
+	uint32_t tmp;
+	int r;
+	int i;
+	int face;
+	u32 tile_flags = 0;
+
+	ib = p->ib->ptr;
+	ib_chunk = &p->chunks[p->chunk_ib_idx];
+	track = (struct r100_cs_track *)p->track;
+
+	switch (reg) {
+	case RADEON_CRTC_GUI_TRIG_VLINE:
+		r = r100_cs_packet_parse_vline(p);
+		if (r) {
+			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+				  idx, reg);
+			r100_cs_dump_packet(p, pkt);
+			return r;
+		}
+		break;
+		/* FIXME: only allow PACKET3 blit? easier to check for out of
+		 * range access */
+	case RADEON_DST_PITCH_OFFSET:
+	case RADEON_SRC_PITCH_OFFSET:
+		r = r100_reloc_pitch_offset(p, pkt, idx, reg);
+		if (r)
+			return r;
+		break;
+	case RADEON_RB3D_DEPTHOFFSET:
+		r = r100_cs_packet_next_reloc(p, &reloc);
+		if (r) {
+			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+				  idx, reg);
+			r100_cs_dump_packet(p, pkt);
+			return r;
+		}
+		track->zb.robj = reloc->robj;
+		track->zb.offset = ib_chunk->kdata[idx];
+		ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+		break;
+	case RADEON_RB3D_COLOROFFSET:
+		r = r100_cs_packet_next_reloc(p, &reloc);
+		if (r) {
+			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+				  idx, reg);
+			r100_cs_dump_packet(p, pkt);
+			return r;
+		}
+		track->cb[0].robj = reloc->robj;
+		track->cb[0].offset = ib_chunk->kdata[idx];
+		ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+		break;
+	case R200_PP_TXOFFSET_0:
+	case R200_PP_TXOFFSET_1:
+	case R200_PP_TXOFFSET_2:
+	case R200_PP_TXOFFSET_3:
+	case R200_PP_TXOFFSET_4:
+	case R200_PP_TXOFFSET_5:
+		i = (reg - R200_PP_TXOFFSET_0) / 24;
+		r = r100_cs_packet_next_reloc(p, &reloc);
+		if (r) {
+			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+				  idx, reg);
+			r100_cs_dump_packet(p, pkt);
+			return r;
+		}
+		ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+		track->textures[i].robj = reloc->robj;
+		break;
+	case R200_PP_CUBIC_OFFSET_F1_0:
+	case R200_PP_CUBIC_OFFSET_F2_0:
+	case R200_PP_CUBIC_OFFSET_F3_0:
+	case R200_PP_CUBIC_OFFSET_F4_0:
+	case R200_PP_CUBIC_OFFSET_F5_0:
+	case R200_PP_CUBIC_OFFSET_F1_1:
+	case R200_PP_CUBIC_OFFSET_F2_1:
+	case R200_PP_CUBIC_OFFSET_F3_1:
+	case R200_PP_CUBIC_OFFSET_F4_1:
+	case R200_PP_CUBIC_OFFSET_F5_1:
+	case R200_PP_CUBIC_OFFSET_F1_2:
+	case R200_PP_CUBIC_OFFSET_F2_2:
+	case R200_PP_CUBIC_OFFSET_F3_2:
+	case R200_PP_CUBIC_OFFSET_F4_2:
+	case R200_PP_CUBIC_OFFSET_F5_2:
+	case R200_PP_CUBIC_OFFSET_F1_3:
+	case R200_PP_CUBIC_OFFSET_F2_3:
+	case R200_PP_CUBIC_OFFSET_F3_3:
+	case R200_PP_CUBIC_OFFSET_F4_3:
+	case R200_PP_CUBIC_OFFSET_F5_3:
+	case R200_PP_CUBIC_OFFSET_F1_4:
+	case R200_PP_CUBIC_OFFSET_F2_4:
+	case R200_PP_CUBIC_OFFSET_F3_4:
+	case R200_PP_CUBIC_OFFSET_F4_4:
+	case R200_PP_CUBIC_OFFSET_F5_4:
+	case R200_PP_CUBIC_OFFSET_F1_5:
+	case R200_PP_CUBIC_OFFSET_F2_5:
+	case R200_PP_CUBIC_OFFSET_F3_5:
+	case R200_PP_CUBIC_OFFSET_F4_5:
+	case R200_PP_CUBIC_OFFSET_F5_5:
+		i = (reg - R200_PP_TXOFFSET_0) / 24;
+		face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4;
+		r = r100_cs_packet_next_reloc(p, &reloc);
+		if (r) {
+			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+				  idx, reg);
+			r100_cs_dump_packet(p, pkt);
+			return r;
+		}
+		track->textures[i].cube_info[face - 1].offset = ib_chunk->kdata[idx];
+		ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+		track->textures[i].cube_info[face - 1].robj = reloc->robj;
+		break;
+	case RADEON_RE_WIDTH_HEIGHT:
+		track->maxy = ((ib_chunk->kdata[idx] >> 16) & 0x7FF);
+		break;
+	case RADEON_RB3D_COLORPITCH:
+		r = r100_cs_packet_next_reloc(p, &reloc);
+		if (r) {
+			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+				  idx, reg);
+			r100_cs_dump_packet(p, pkt);
+			return r;
+		}
+
+		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
+			tile_flags |= RADEON_COLOR_TILE_ENABLE;
+		if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
+			tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
+
+		tmp = ib_chunk->kdata[idx] & ~(0x7 << 16);
+		tmp |= tile_flags;
+		ib[idx] = tmp;
+
+		track->cb[0].pitch = ib_chunk->kdata[idx] & RADEON_COLORPITCH_MASK;
+		break;
+	case RADEON_RB3D_DEPTHPITCH:
+		track->zb.pitch = ib_chunk->kdata[idx] & RADEON_DEPTHPITCH_MASK;
+		break;
+	case RADEON_RB3D_CNTL:
+		switch ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
+		case 7:
+		case 8:
+		case 9:
+		case 11:
+		case 12:
+			track->cb[0].cpp = 1;
+			break;
+		case 3:
+		case 4:
+		case 15:
+			track->cb[0].cpp = 2;
+			break;
+		case 6:
+			track->cb[0].cpp = 4;
+			break;
+		default:
+			DRM_ERROR("Invalid color buffer format (%d) !\n",
+				  ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
+			return -EINVAL;
+		}
+		if (ib_chunk->kdata[idx] & RADEON_DEPTHXY_OFFSET_ENABLE) {
+			DRM_ERROR("No support for depth xy offset in kms\n");
+			return -EINVAL;
+		}
+
+		track->z_enabled = !!(ib_chunk->kdata[idx] & RADEON_Z_ENABLE);
+		break;
+	case RADEON_RB3D_ZSTENCILCNTL:
+		switch (ib_chunk->kdata[idx] & 0xf) {
+		case 0:
+			track->zb.cpp = 2;
+			break;
+		case 2:
+		case 3:
+		case 4:
+		case 5:
+		case 9:
+		case 11:
+			track->zb.cpp = 4;
+			break;
+		default:
+			break;
+		}
+		break;
+	case RADEON_RB3D_ZPASS_ADDR:
+		r = r100_cs_packet_next_reloc(p, &reloc);
+		if (r) {
+			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+				  idx, reg);
+			r100_cs_dump_packet(p, pkt);
+			return r;
+		}
+		ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+		break;
+	case RADEON_PP_CNTL:
+		{
+			uint32_t temp = ib_chunk->kdata[idx] >> 4;
+			for (i = 0; i < track->num_texture; i++)
+				track->textures[i].enabled = !!(temp & (1 << i));
+		}
+		break;
+	case RADEON_SE_VF_CNTL:
+		track->vap_vf_cntl = ib_chunk->kdata[idx];
+		break;
+	case 0x210c:
+		/* VAP_VF_MAX_VTX_INDX */
+		track->max_indx = ib_chunk->kdata[idx] & 0x00FFFFFFUL;
+		break;
+	case R200_SE_VTX_FMT_0:
+		track->vtx_size = r200_get_vtx_size_0(ib_chunk->kdata[idx]);
+		break;
+	case R200_SE_VTX_FMT_1:
+		track->vtx_size += r200_get_vtx_size_1(ib_chunk->kdata[idx]);
+		break;
+	case R200_PP_TXSIZE_0:
+	case R200_PP_TXSIZE_1:
+	case R200_PP_TXSIZE_2:
+	case R200_PP_TXSIZE_3:
+	case R200_PP_TXSIZE_4:
+	case R200_PP_TXSIZE_5:
+		i = (reg - R200_PP_TXSIZE_0) / 32;
+		track->textures[i].width = (ib_chunk->kdata[idx] & RADEON_TEX_USIZE_MASK) + 1;
+		track->textures[i].height = ((ib_chunk->kdata[idx] & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
+		break;
+	case R200_PP_TXPITCH_0:
+	case R200_PP_TXPITCH_1:
+	case R200_PP_TXPITCH_2:
+	case R200_PP_TXPITCH_3:
+	case R200_PP_TXPITCH_4:
+	case R200_PP_TXPITCH_5:
+		i = (reg - R200_PP_TXPITCH_0) / 32;
+		track->textures[i].pitch = ib_chunk->kdata[idx] + 32;
+		break;
+	case R200_PP_TXFILTER_0:
+	case R200_PP_TXFILTER_1:
+	case R200_PP_TXFILTER_2:
+	case R200_PP_TXFILTER_3:
+	case R200_PP_TXFILTER_4:
+	case R200_PP_TXFILTER_5:
+		i = (reg - R200_PP_TXFILTER_0) / 32;
+		track->textures[i].num_levels = ((ib_chunk->kdata[idx] & R200_MAX_MIP_LEVEL_MASK)
+						 >> R200_MAX_MIP_LEVEL_SHIFT);
+		tmp = (ib_chunk->kdata[idx] >> 23) & 0x7;
+		if (tmp == 2 || tmp == 6)
+			track->textures[i].roundup_w = false;
+		tmp = (ib_chunk->kdata[idx] >> 27) & 0x7;
+		if (tmp == 2 || tmp == 6)
+			track->textures[i].roundup_h = false;
+		break;
+	case R200_PP_TXMULTI_CTL_0:
+	case R200_PP_TXMULTI_CTL_1:
+	case R200_PP_TXMULTI_CTL_2:
+	case R200_PP_TXMULTI_CTL_3:
+	case R200_PP_TXMULTI_CTL_4:
+	case R200_PP_TXMULTI_CTL_5:
+		i = (reg - R200_PP_TXMULTI_CTL_0) / 32;
+		break;
+	case R200_PP_TXFORMAT_X_0:
+	case R200_PP_TXFORMAT_X_1:
+	case R200_PP_TXFORMAT_X_2:
+	case R200_PP_TXFORMAT_X_3:
+	case R200_PP_TXFORMAT_X_4:
+	case R200_PP_TXFORMAT_X_5:
+		i = (reg - R200_PP_TXFORMAT_X_0) / 32;
+		track->textures[i].txdepth = ib_chunk->kdata[idx] & 0x7;
+		tmp = (ib_chunk->kdata[idx] >> 16) & 0x3;
+		/* 2D, 3D, CUBE */
+		switch (tmp) {
+		case 0:
+		case 5:
+		case 6:
+		case 7:
+			track->textures[i].tex_coord_type = 0;
+			break;
+		case 1:
+			track->textures[i].tex_coord_type = 1;
+			break;
+		case 2:
+			track->textures[i].tex_coord_type = 2;
+			break;
+		}
+		break;
+	case R200_PP_TXFORMAT_0:
+	case R200_PP_TXFORMAT_1:
+	case R200_PP_TXFORMAT_2:
+	case R200_PP_TXFORMAT_3:
+	case R200_PP_TXFORMAT_4:
+	case R200_PP_TXFORMAT_5:
+		i = (reg - R200_PP_TXFORMAT_0) / 32;
+		if (ib_chunk->kdata[idx] & R200_TXFORMAT_NON_POWER2) {
+			track->textures[i].use_pitch = 1;
+		} else {
+			track->textures[i].use_pitch = 0;
+			track->textures[i].width = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
+			track->textures[i].height = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
+		}
+		switch ((ib_chunk->kdata[idx] & RADEON_TXFORMAT_FORMAT_MASK)) {
+		case R200_TXFORMAT_I8:
+		case R200_TXFORMAT_RGB332:
+		case R200_TXFORMAT_Y8:
+			track->textures[i].cpp = 1;
+			break;
+		case R200_TXFORMAT_DXT1:
+		case R200_TXFORMAT_AI88:
+		case R200_TXFORMAT_ARGB1555:
+		case R200_TXFORMAT_RGB565:
+		case R200_TXFORMAT_ARGB4444:
+		case R200_TXFORMAT_VYUY422:
+		case R200_TXFORMAT_YVYU422:
+		case R200_TXFORMAT_LDVDU655:
+		case R200_TXFORMAT_DVDU88:
+		case R200_TXFORMAT_AVYU4444:
+			track->textures[i].cpp = 2;
+			break;
+		case R200_TXFORMAT_ARGB8888:
+		case R200_TXFORMAT_RGBA8888:
+		case R200_TXFORMAT_ABGR8888:
+		case R200_TXFORMAT_BGR111110:
+		case R200_TXFORMAT_LDVDU8888:
+		case R200_TXFORMAT_DXT23:
+		case R200_TXFORMAT_DXT45:
+			track->textures[i].cpp = 4;
+			break;
+		}
+		track->textures[i].cube_info[4].width = 1 << ((ib_chunk->kdata[idx] >> 16) & 0xf);
+		track->textures[i].cube_info[4].height = 1 << ((ib_chunk->kdata[idx] >> 20) & 0xf);
+		break;
+	case R200_PP_CUBIC_FACES_0:
+	case R200_PP_CUBIC_FACES_1:
+	case R200_PP_CUBIC_FACES_2:
+	case R200_PP_CUBIC_FACES_3:
+	case R200_PP_CUBIC_FACES_4:
+	case R200_PP_CUBIC_FACES_5:
+		tmp = ib_chunk->kdata[idx];
+		i = (reg - R200_PP_CUBIC_FACES_0) / 32;
+		for (face = 0; face < 4; face++) {
+			track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
+			track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
+		}
+		break;
+	default:
+		printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
+		       reg, idx);
+		return -EINVAL;
+	}
+	return 0;
+}
+
+int r200_init(struct radeon_device *rdev)
+{
+	rdev->config.r100.reg_safe_bm = r200_reg_safe_bm;
+	rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm);
+	return 0;
+}
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 9f2460cf9db..33a2c557eac 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -32,6 +32,7 @@
 #include "radeon.h"
 #include "radeon_drm.h"
 #include "radeon_share.h"
+#include "r100_track.h"
 
 #include "r300_reg_safe.h"
 
@@ -49,14 +50,10 @@ int r100_cs_packet_parse(struct radeon_cs_parser *p,
 			 struct radeon_cs_packet *pkt,
 			 unsigned idx);
 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
-int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
-			      struct radeon_cs_reloc **cs_reloc);
 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
 			  struct radeon_cs_packet *pkt,
 			  const unsigned *auth, unsigned n,
 			  radeon_packet0_check_t check);
-void r100_cs_dump_packet(struct radeon_cs_parser *p,
-			 struct radeon_cs_packet *pkt);
 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
 					 struct radeon_cs_packet *pkt,
 					 struct radeon_object *robj);
@@ -706,264 +703,13 @@ int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
 /*
  * CS functions
  */
-struct r300_cs_track_cb {
-	struct radeon_object	*robj;
-	unsigned		pitch;
-	unsigned		cpp;
-	unsigned		offset;
-};
-
-struct r300_cs_track_array {
-	struct radeon_object	*robj;
-	unsigned		esize;
-};
-
-struct r300_cs_track_texture {
-	struct radeon_object	*robj;
-	unsigned		pitch;
-	unsigned		width;
-	unsigned		height;
-	unsigned		num_levels;
-	unsigned		cpp;
-	unsigned		tex_coord_type;
-	unsigned		txdepth;
-	unsigned		width_11;
-	unsigned		height_11;
-	bool			use_pitch;
-	bool			enabled;
-	bool			roundup_w;
-	bool			roundup_h;
-};
-
-struct r300_cs_track {
-	unsigned			num_cb;
-	unsigned			maxy;
-	unsigned			vtx_size;
-	unsigned			vap_vf_cntl;
-	unsigned			immd_dwords;
-	unsigned			num_arrays;
-	unsigned			max_indx;
-	struct r300_cs_track_array	arrays[11];
-	struct r300_cs_track_cb 	cb[4];
-	struct r300_cs_track_cb 	zb;
-	struct r300_cs_track_texture	textures[16];
-	bool				z_enabled;
-};
-
-static inline void r300_cs_track_texture_print(struct r300_cs_track_texture *t)
-{
-	DRM_ERROR("pitch                      %d\n", t->pitch);
-	DRM_ERROR("width                      %d\n", t->width);
-	DRM_ERROR("height                     %d\n", t->height);
-	DRM_ERROR("num levels                 %d\n", t->num_levels);
-	DRM_ERROR("depth                      %d\n", t->txdepth);
-	DRM_ERROR("bpp                        %d\n", t->cpp);
-	DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
-	DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
-	DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
-}
-
-static inline int r300_cs_track_texture_check(struct radeon_device *rdev,
-					      struct r300_cs_track *track)
-{
-	struct radeon_object *robj;
-	unsigned long size;
-	unsigned u, i, w, h;
-
-	for (u = 0; u < 16; u++) {
-		if (!track->textures[u].enabled)
-			continue;
-		robj = track->textures[u].robj;
-		if (robj == NULL) {
-			DRM_ERROR("No texture bound to unit %u\n", u);
-			return -EINVAL;
-		}
-		size = 0;
-		for (i = 0; i <= track->textures[u].num_levels; i++) {
-			if (track->textures[u].use_pitch) {
-				w = track->textures[u].pitch / (1 << i);
-			} else {
-				w = track->textures[u].width / (1 << i);
-				if (rdev->family >= CHIP_RV515)
-					w |= track->textures[u].width_11;
-				if (track->textures[u].roundup_w)
-					w = roundup_pow_of_two(w);
-			}
-			h = track->textures[u].height / (1 << i);
-			if (rdev->family >= CHIP_RV515)
-				h |= track->textures[u].height_11;
-			if (track->textures[u].roundup_h)
-				h = roundup_pow_of_two(h);
-			size += w * h;
-		}
-		size *= track->textures[u].cpp;
-		switch (track->textures[u].tex_coord_type) {
-		case 0:
-			break;
-		case 1:
-			size *= (1 << track->textures[u].txdepth);
-			break;
-		case 2:
-			size *= 6;
-			break;
-		default:
-			DRM_ERROR("Invalid texture coordinate type %u for unit "
-				  "%u\n", track->textures[u].tex_coord_type, u);
-			return -EINVAL;
-		}
-		if (size > radeon_object_size(robj)) {
-			DRM_ERROR("Texture of unit %u needs %lu bytes but is "
-				  "%lu\n", u, size, radeon_object_size(robj));
-			r300_cs_track_texture_print(&track->textures[u]);
-			return -EINVAL;
-		}
-	}
-	return 0;
-}
-
-int r300_cs_track_check(struct radeon_device *rdev, struct r300_cs_track *track)
-{
-	unsigned i;
-	unsigned long size;
-	unsigned prim_walk;
-	unsigned nverts;
-
-	for (i = 0; i < track->num_cb; i++) {
-		if (track->cb[i].robj == NULL) {
-			DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
-			return -EINVAL;
-		}
-		size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
-		size += track->cb[i].offset;
-		if (size > radeon_object_size(track->cb[i].robj)) {
-			DRM_ERROR("[drm] Buffer too small for color buffer %d "
-				  "(need %lu have %lu) !\n", i, size,
-				  radeon_object_size(track->cb[i].robj));
-			DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
-				  i, track->cb[i].pitch, track->cb[i].cpp,
-				  track->cb[i].offset, track->maxy);
-			return -EINVAL;
-		}
-	}
-	if (track->z_enabled) {
-		if (track->zb.robj == NULL) {
-			DRM_ERROR("[drm] No buffer for z buffer !\n");
-			return -EINVAL;
-		}
-		size = track->zb.pitch * track->zb.cpp * track->maxy;
-		size += track->zb.offset;
-		if (size > radeon_object_size(track->zb.robj)) {
-			DRM_ERROR("[drm] Buffer too small for z buffer "
-				  "(need %lu have %lu) !\n", size,
-				  radeon_object_size(track->zb.robj));
-			return -EINVAL;
-		}
-	}
-	prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
-	nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
-	switch (prim_walk) {
-	case 1:
-		for (i = 0; i < track->num_arrays; i++) {
-			size = track->arrays[i].esize * track->max_indx * 4;
-			if (track->arrays[i].robj == NULL) {
-				DRM_ERROR("(PW %u) Vertex array %u no buffer "
-					  "bound\n", prim_walk, i);
-				return -EINVAL;
-			}
-			if (size > radeon_object_size(track->arrays[i].robj)) {
-				DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
-					   "have %lu dwords\n", prim_walk, i,
-					   size >> 2,
-					   radeon_object_size(track->arrays[i].robj) >> 2);
-				DRM_ERROR("Max indices %u\n", track->max_indx);
-				return -EINVAL;
-			}
-		}
-		break;
-	case 2:
-		for (i = 0; i < track->num_arrays; i++) {
-			size = track->arrays[i].esize * (nverts - 1) * 4;
-			if (track->arrays[i].robj == NULL) {
-				DRM_ERROR("(PW %u) Vertex array %u no buffer "
-					  "bound\n", prim_walk, i);
-				return -EINVAL;
-			}
-			if (size > radeon_object_size(track->arrays[i].robj)) {
-				DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
-					   "have %lu dwords\n", prim_walk, i, size >> 2,
-					   radeon_object_size(track->arrays[i].robj) >> 2);
-				return -EINVAL;
-			}
-		}
-		break;
-	case 3:
-		size = track->vtx_size * nverts;
-		if (size != track->immd_dwords) {
-			DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
-				  track->immd_dwords, size);
-			DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
-				  nverts, track->vtx_size);
-			return -EINVAL;
-		}
-		break;
-	default:
-		DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
-			  prim_walk);
-		return -EINVAL;
-	}
-	return r300_cs_track_texture_check(rdev, track);
-}
-
-static inline void r300_cs_track_clear(struct r300_cs_track *track)
-{
-	unsigned i;
-
-	track->num_cb = 4;
-	track->maxy = 4096;
-	for (i = 0; i < track->num_cb; i++) {
-		track->cb[i].robj = NULL;
-		track->cb[i].pitch = 8192;
-		track->cb[i].cpp = 16;
-		track->cb[i].offset = 0;
-	}
-	track->z_enabled = true;
-	track->zb.robj = NULL;
-	track->zb.pitch = 8192;
-	track->zb.cpp = 4;
-	track->zb.offset = 0;
-	track->vtx_size = 0x7F;
-	track->immd_dwords = 0xFFFFFFFFUL;
-	track->num_arrays = 11;
-	track->max_indx = 0x00FFFFFFUL;
-	for (i = 0; i < track->num_arrays; i++) {
-		track->arrays[i].robj = NULL;
-		track->arrays[i].esize = 0x7F;
-	}
-	for (i = 0; i < 16; i++) {
-		track->textures[i].pitch = 16536;
-		track->textures[i].width = 16536;
-		track->textures[i].height = 16536;
-		track->textures[i].width_11 = 1 << 11;
-		track->textures[i].height_11 = 1 << 11;
-		track->textures[i].num_levels = 12;
-		track->textures[i].txdepth = 16;
-		track->textures[i].cpp = 64;
-		track->textures[i].tex_coord_type = 1;
-		track->textures[i].robj = NULL;
-		/* CS IB emission code makes sure texture unit are disabled */
-		track->textures[i].enabled = false;
-		track->textures[i].roundup_w = true;
-		track->textures[i].roundup_h = true;
-	}
-}
-
 static int r300_packet0_check(struct radeon_cs_parser *p,
 		struct radeon_cs_packet *pkt,
 		unsigned idx, unsigned reg)
 {
 	struct radeon_cs_chunk *ib_chunk;
 	struct radeon_cs_reloc *reloc;
-	struct r300_cs_track *track;
+	struct r100_cs_track *track;
 	volatile uint32_t *ib;
 	uint32_t tmp, tile_flags = 0;
 	unsigned i;
@@ -971,7 +717,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
 
 	ib = p->ib->ptr;
 	ib_chunk = &p->chunks[p->chunk_ib_idx];
-	track = (struct r300_cs_track*)p->track;
+	track = (struct r100_cs_track *)p->track;
 	switch(reg) {
 	case AVIVO_D1MODE_VLINE_START_END:
 	case RADEON_CRTC_GUI_TRIG_VLINE:
@@ -985,28 +731,9 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
 		break;
 	case RADEON_DST_PITCH_OFFSET:
 	case RADEON_SRC_PITCH_OFFSET:
-		r = r100_cs_packet_next_reloc(p, &reloc);
-		if (r) {
-			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
-					idx, reg);
-			r100_cs_dump_packet(p, pkt);
+		r = r100_reloc_pitch_offset(p, pkt, idx, reg);
+		if (r)
 			return r;
-		}
-		tmp = ib_chunk->kdata[idx] & 0x003fffff;
-		tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
-
-		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
-			tile_flags |= RADEON_DST_TILE_MACRO;
-		if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
-			if (reg == RADEON_SRC_PITCH_OFFSET) {
-				DRM_ERROR("Cannot src blit from microtiled surface\n");
-				r100_cs_dump_packet(p, pkt);
-				return -EINVAL;
-			}
-			tile_flags |= RADEON_DST_TILE_MICRO;
-		}
-		tmp |= tile_flags;
-		ib[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp;
 		break;
 	case R300_RB3D_COLOROFFSET0:
 	case R300_RB3D_COLOROFFSET1:
@@ -1215,42 +942,41 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
 		tmp = (ib_chunk->kdata[idx] >> 25) & 0x3;
 		track->textures[i].tex_coord_type = tmp;
 		switch ((ib_chunk->kdata[idx] & 0x1F)) {
-		case 0:
-		case 2:
-		case 5:
-		case 18:
-		case 20:
-		case 21:
+		case R300_TX_FORMAT_X8:
+		case R300_TX_FORMAT_Y4X4:
+		case R300_TX_FORMAT_Z3Y3X2:
 			track->textures[i].cpp = 1;
 			break;
-		case 1:
-		case 3:
-		case 6:
-		case 7:
-		case 10:
-		case 11:
-		case 19:
-		case 22:
-		case 24:
+		case R300_TX_FORMAT_X16:
+		case R300_TX_FORMAT_Y8X8:
+		case R300_TX_FORMAT_Z5Y6X5:
+		case R300_TX_FORMAT_Z6Y5X5:
+		case R300_TX_FORMAT_W4Z4Y4X4:
+		case R300_TX_FORMAT_W1Z5Y5X5:
+		case R300_TX_FORMAT_DXT1:
+		case R300_TX_FORMAT_D3DMFT_CxV8U8:
+		case R300_TX_FORMAT_B8G8_B8G8:
+		case R300_TX_FORMAT_G8R8_G8B8:
 			track->textures[i].cpp = 2;
 			break;
-		case 4:
-		case 8:
-		case 9:
-		case 12:
-		case 13:
-		case 23:
-		case 25:
-		case 27:
-		case 30:
+		case R300_TX_FORMAT_Y16X16:
+		case R300_TX_FORMAT_Z11Y11X10:
+		case R300_TX_FORMAT_Z10Y11X11:
+		case R300_TX_FORMAT_W8Z8Y8X8:
+		case R300_TX_FORMAT_W2Z10Y10X10:
+		case 0x17:
+		case R300_TX_FORMAT_FL_I32:
+		case 0x1e:
+		case R300_TX_FORMAT_DXT3:
+		case R300_TX_FORMAT_DXT5:
 			track->textures[i].cpp = 4;
 			break;
-		case 14:
-		case 26:
-		case 28:
+		case R300_TX_FORMAT_W16Z16Y16X16:
+		case R300_TX_FORMAT_FL_R16G16B16A16:
+		case R300_TX_FORMAT_FL_I32A32:
 			track->textures[i].cpp = 8;
 			break;
-		case 29:
+		case R300_TX_FORMAT_FL_R32G32B32A32:
 			track->textures[i].cpp = 16;
 			break;
 		default:
@@ -1278,11 +1004,11 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
 	case 0x443C:
 		/* TX_FILTER0_[0-15] */
 		i = (reg - 0x4400) >> 2;
-		tmp = ib_chunk->kdata[idx] & 0x7;;
+		tmp = ib_chunk->kdata[idx] & 0x7;
 		if (tmp == 2 || tmp == 4 || tmp == 6) {
 			track->textures[i].roundup_w = false;
 		}
-		tmp = (ib_chunk->kdata[idx] >> 3) & 0x7;;
+		tmp = (ib_chunk->kdata[idx] >> 3) & 0x7;
 		if (tmp == 2 || tmp == 4 || tmp == 6) {
 			track->textures[i].roundup_h = false;
 		}
@@ -1370,8 +1096,9 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
 			      struct radeon_cs_packet *pkt)
 {
 	struct radeon_cs_chunk *ib_chunk;
+
 	struct radeon_cs_reloc *reloc;
-	struct r300_cs_track *track;
+	struct r100_cs_track *track;
 	volatile uint32_t *ib;
 	unsigned idx;
 	unsigned i, c;
@@ -1380,7 +1107,7 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
 	ib = p->ib->ptr;
 	ib_chunk = &p->chunks[p->chunk_ib_idx];
 	idx = pkt->idx + 1;
-	track = (struct r300_cs_track*)p->track;
+	track = (struct r100_cs_track *)p->track;
 	switch(pkt->opcode) {
 	case PACKET3_3D_LOAD_VBPNTR:
 		c = ib_chunk->kdata[idx++] & 0x1F;
@@ -1447,7 +1174,7 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
 		}
 		track->vap_vf_cntl = ib_chunk->kdata[idx+1];
 		track->immd_dwords = pkt->count - 1;
-		r = r300_cs_track_check(p->rdev, track);
+		r = r100_cs_track_check(p->rdev, track);
 		if (r) {
 			return r;
 		}
@@ -1462,35 +1189,35 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
 		}
 		track->vap_vf_cntl = ib_chunk->kdata[idx];
 		track->immd_dwords = pkt->count;
-		r = r300_cs_track_check(p->rdev, track);
+		r = r100_cs_track_check(p->rdev, track);
 		if (r) {
 			return r;
 		}
 		break;
 	case PACKET3_3D_DRAW_VBUF:
 		track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
-		r = r300_cs_track_check(p->rdev, track);
+		r = r100_cs_track_check(p->rdev, track);
 		if (r) {
 			return r;
 		}
 		break;
 	case PACKET3_3D_DRAW_VBUF_2:
 		track->vap_vf_cntl = ib_chunk->kdata[idx];
-		r = r300_cs_track_check(p->rdev, track);
+		r = r100_cs_track_check(p->rdev, track);
 		if (r) {
 			return r;
 		}
 		break;
 	case PACKET3_3D_DRAW_INDX:
 		track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
-		r = r300_cs_track_check(p->rdev, track);
+		r = r100_cs_track_check(p->rdev, track);
 		if (r) {
 			return r;
 		}
 		break;
 	case PACKET3_3D_DRAW_INDX_2:
 		track->vap_vf_cntl = ib_chunk->kdata[idx];
-		r = r300_cs_track_check(p->rdev, track);
+		r = r100_cs_track_check(p->rdev, track);
 		if (r) {
 			return r;
 		}
@@ -1507,10 +1234,10 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
 int r300_cs_parse(struct radeon_cs_parser *p)
 {
 	struct radeon_cs_packet pkt;
-	struct r300_cs_track track;
+	struct r100_cs_track track;
 	int r;
 
-	r300_cs_track_clear(&track);
+	r100_cs_track_clear(p->rdev, &track);
 	p->track = &track;
 	do {
 		r = r100_cs_packet_parse(p, &pkt, p->idx);
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 149974d13aa..6c35c3c2919 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -604,8 +604,14 @@ struct radeon_asic {
 	void (*bandwidth_update)(struct radeon_device *rdev);
 };
 
+struct r100_asic {
+	const unsigned	*reg_safe_bm;
+	unsigned	reg_safe_bm_size;
+};
+
 union radeon_asic_config {
 	struct r300_asic	r300;
+	struct r100_asic	r100;
 };
 
 
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 8ace15156c4..c9cbd8ae1f9 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -42,6 +42,7 @@ void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  */
 int r100_init(struct radeon_device *rdev);
+int r200_init(struct radeon_device *rdev);
 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 void r100_errata(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
index 4df43f62c67..404b39bf343 100644
--- a/drivers/gpu/drm/radeon/radeon_reg.h
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -1945,6 +1945,11 @@
 #       define RADEON_TXFORMAT_DXT1               (12 <<  0)
 #       define RADEON_TXFORMAT_DXT23              (14 <<  0)
 #       define RADEON_TXFORMAT_DXT45              (15 <<  0)
+#	define RADEON_TXFORMAT_SHADOW16           (16 <<  0)
+#	define RADEON_TXFORMAT_SHADOW32           (17 <<  0)
+#       define RADEON_TXFORMAT_DUDV88             (18 <<  0)
+#       define RADEON_TXFORMAT_LDUDV655           (19 <<  0)
+#       define RADEON_TXFORMAT_LDUDUV8888         (20 <<  0)
 #       define RADEON_TXFORMAT_FORMAT_MASK        (31 <<  0)
 #       define RADEON_TXFORMAT_FORMAT_SHIFT       0
 #       define RADEON_TXFORMAT_APPLE_YUV_MODE     (1  <<  5)
@@ -2203,7 +2208,7 @@
 #       define RADEON_ROP_ENABLE               (1  <<  6)
 #       define RADEON_STENCIL_ENABLE           (1  <<  7)
 #       define RADEON_Z_ENABLE                 (1  <<  8)
-#       define RADEON_DEPTH_XZ_OFFEST_ENABLE   (1  <<  9)
+#       define RADEON_DEPTHXY_OFFSET_ENABLE    (1  <<  9)
 #       define RADEON_RB3D_COLOR_FORMAT_SHIFT  10
 
 #       define RADEON_COLOR_FORMAT_ARGB1555    3
@@ -2773,7 +2778,12 @@
 #       define R200_TXFORMAT_DXT1		(12 << 0)
 #       define R200_TXFORMAT_DXT23		(14 << 0)
 #       define R200_TXFORMAT_DXT45		(15 << 0)
+#       define R200_TXFORMAT_DVDU88		(18 << 0)
+#       define R200_TXFORMAT_LDVDU655		(19 << 0)
+#       define R200_TXFORMAT_LDVDU8888		(20 << 0)
+#       define R200_TXFORMAT_GR1616		(21 << 0)
 #       define R200_TXFORMAT_ABGR8888		(22 << 0)
+#       define R200_TXFORMAT_BGR111110		(23 << 0)
 #       define R200_TXFORMAT_FORMAT_MASK	(31 <<	0)
 #       define R200_TXFORMAT_FORMAT_SHIFT	0
 #       define R200_TXFORMAT_ALPHA_IN_MAP	(1 << 6)
@@ -2818,6 +2828,13 @@
 #define R200_PP_TXPITCH_4			0x2c90 /* NPOT only */
 #define R200_PP_TXPITCH_5			0x2cb0 /* NPOT only */
 
+#define R200_PP_CUBIC_FACES_0			0x2c18
+#define R200_PP_CUBIC_FACES_1			0x2c38
+#define R200_PP_CUBIC_FACES_2			0x2c58
+#define R200_PP_CUBIC_FACES_3			0x2c78
+#define R200_PP_CUBIC_FACES_4			0x2c98
+#define R200_PP_CUBIC_FACES_5			0x2cb8
+
 #define R200_PP_TXOFFSET_0			0x2d00
 #       define R200_TXO_ENDIAN_NO_SWAP		(0 << 0)
 #       define R200_TXO_ENDIAN_BYTE_SWAP	(1 << 0)
@@ -2829,11 +2846,44 @@
 #       define R200_TXO_MICRO_TILE		(1 << 3)
 #       define R200_TXO_OFFSET_MASK		0xffffffe0
 #       define R200_TXO_OFFSET_SHIFT		5
+#define R200_PP_CUBIC_OFFSET_F1_0         0x2d04
+#define R200_PP_CUBIC_OFFSET_F2_0         0x2d08
+#define R200_PP_CUBIC_OFFSET_F3_0         0x2d0c
+#define R200_PP_CUBIC_OFFSET_F4_0         0x2d10
+#define R200_PP_CUBIC_OFFSET_F5_0         0x2d14
+
 #define R200_PP_TXOFFSET_1			0x2d18
+#define R200_PP_CUBIC_OFFSET_F1_1         0x2d1c
+#define R200_PP_CUBIC_OFFSET_F2_1         0x2d20
+#define R200_PP_CUBIC_OFFSET_F3_1         0x2d24
+#define R200_PP_CUBIC_OFFSET_F4_1         0x2d28
+#define R200_PP_CUBIC_OFFSET_F5_1         0x2d2c
+
 #define R200_PP_TXOFFSET_2			0x2d30
+#define R200_PP_CUBIC_OFFSET_F1_2         0x2d34
+#define R200_PP_CUBIC_OFFSET_F2_2         0x2d38
+#define R200_PP_CUBIC_OFFSET_F3_2         0x2d3c
+#define R200_PP_CUBIC_OFFSET_F4_2         0x2d40
+#define R200_PP_CUBIC_OFFSET_F5_2         0x2d44
+
 #define R200_PP_TXOFFSET_3			0x2d48
+#define R200_PP_CUBIC_OFFSET_F1_3         0x2d4c
+#define R200_PP_CUBIC_OFFSET_F2_3         0x2d50
+#define R200_PP_CUBIC_OFFSET_F3_3         0x2d54
+#define R200_PP_CUBIC_OFFSET_F4_3         0x2d58
+#define R200_PP_CUBIC_OFFSET_F5_3         0x2d5c
 #define R200_PP_TXOFFSET_4			0x2d60
+#define R200_PP_CUBIC_OFFSET_F1_4         0x2d64
+#define R200_PP_CUBIC_OFFSET_F2_4         0x2d68
+#define R200_PP_CUBIC_OFFSET_F3_4         0x2d6c
+#define R200_PP_CUBIC_OFFSET_F4_4         0x2d70
+#define R200_PP_CUBIC_OFFSET_F5_4         0x2d74
 #define R200_PP_TXOFFSET_5			0x2d78
+#define R200_PP_CUBIC_OFFSET_F1_5         0x2d7c
+#define R200_PP_CUBIC_OFFSET_F2_5         0x2d80
+#define R200_PP_CUBIC_OFFSET_F3_5         0x2d84
+#define R200_PP_CUBIC_OFFSET_F4_5         0x2d88
+#define R200_PP_CUBIC_OFFSET_F5_5         0x2d8c
 
 #define R200_PP_TFACTOR_0			0x2ee0
 #define R200_PP_TFACTOR_1			0x2ee4
@@ -3175,6 +3225,11 @@
 #       define R200_FORCE_INORDER_PROC		(1<<31)
 #define R200_PP_CNTL_X				0x2cc4
 #define R200_PP_TXMULTI_CTL_0			0x2c1c
+#define R200_PP_TXMULTI_CTL_1			0x2c3c
+#define R200_PP_TXMULTI_CTL_2			0x2c5c
+#define R200_PP_TXMULTI_CTL_3			0x2c7c
+#define R200_PP_TXMULTI_CTL_4			0x2c9c
+#define R200_PP_TXMULTI_CTL_5			0x2cbc
 #define R200_SE_VTX_STATE_CNTL			0x2180
 #       define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16)
 
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r100 b/drivers/gpu/drm/radeon/reg_srcs/r100
new file mode 100644
index 00000000000..f7ee062f118
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/r100
@@ -0,0 +1,105 @@
+r100 0x3294
+0x1434 SRC_Y_X
+0x1438 DST_Y_X
+0x143C DST_HEIGHT_WIDTH
+0x146C DP_GUI_MASTER_CNTL
+0x1474 BRUSH_Y_X
+0x1478 DP_BRUSH_BKGD_CLR
+0x147C DP_BRUSH_FRGD_CLR
+0x1480 BRUSH_DATA0
+0x1484 BRUSH_DATA1
+0x1598 DST_WIDTH_HEIGHT
+0x15C0 CLR_CMP_CNTL
+0x15C4 CLR_CMP_CLR_SRC
+0x15C8 CLR_CMP_CLR_DST
+0x15CC CLR_CMP_MSK
+0x15D8 DP_SRC_FRGD_CLR
+0x15DC DP_SRC_BKGD_CLR
+0x1600 DST_LINE_START
+0x1604 DST_LINE_END
+0x1608 DST_LINE_PATCOUNT
+0x16C0 DP_CNTL
+0x16CC DP_WRITE_MSK
+0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
+0x16E8 DEFAULT_SC_BOTTOM_RIGHT
+0x16EC SC_TOP_LEFT
+0x16F0 SC_BOTTOM_RIGHT
+0x16F4 SRC_SC_BOTTOM_RIGHT
+0x1714 DSTCACHE_CTLSTAT
+0x1720 WAIT_UNTIL
+0x172C RBBM_GUICNTL
+0x1810 FOG_3D_TABLE_START
+0x1814 FOG_3D_TABLE_END
+0x1a14 FOG_TABLE_INDEX
+0x1a18 FOG_TABLE_DATA
+0x1c14 PP_MISC
+0x1c18 PP_FOG_COLOR
+0x1c1c RE_SOLID_COLOR
+0x1c20 RB3D_BLENDCNTL
+0x1c4c SE_CNTL
+0x1c50 SE_COORD_FMT
+0x1c60 PP_TXCBLEND_0
+0x1c64 PP_TXABLEND_0
+0x1c68 PP_TFACTOR_0
+0x1c78 PP_TXCBLEND_1
+0x1c7c PP_TXABLEND_1
+0x1c80 PP_TFACTOR_1
+0x1c90 PP_TXCBLEND_2
+0x1c94 PP_TXABLEND_2
+0x1c98 PP_TFACTOR_2
+0x1cc8 RE_STIPPLE_ADDR
+0x1ccc RE_STIPPLE_DATA
+0x1cd0 RE_LINE_PATTERN
+0x1cd4 RE_LINE_STATE
+0x1d40 PP_BORDER_COLOR0
+0x1d44 PP_BORDER_COLOR1
+0x1d48 PP_BORDER_COLOR2
+0x1d7c RB3D_STENCILREFMASK
+0x1d80 RB3D_ROPCNTL
+0x1d84 RB3D_PLANEMASK
+0x1d98 VAP_VPORT_XSCALE
+0x1d9C VAP_VPORT_XOFFSET
+0x1da0 VAP_VPORT_YSCALE
+0x1da4 VAP_VPORT_YOFFSET
+0x1da8 VAP_VPORT_ZSCALE
+0x1dac VAP_VPORT_ZOFFSET
+0x1db0 SE_ZBIAS_FACTOR
+0x1db4 SE_ZBIAS_CONSTANT
+0x1db8 SE_LINE_WIDTH
+0x2140 SE_CNTL_STATUS
+0x2200 SE_TCL_VECTOR_INDX_REG
+0x2204 SE_TCL_VECTOR_DATA_REG
+0x2208 SE_TCL_SCALAR_INDX_REG
+0x220c SE_TCL_SCALAR_DATA_REG
+0x2210 SE_TCL_MATERIAL_EMISSIVE_RED
+0x2214 SE_TCL_MATERIAL_EMISSIVE_GREEN
+0x2218 SE_TCL_MATERIAL_EMISSIVE_BLUE
+0x221c SE_TCL_MATERIAL_EMISSIVE_ALPHA
+0x2220 SE_TCL_MATERIAL_AMBIENT_RED
+0x2224 SE_TCL_MATERIAL_AMBIENT_GREEN
+0x2228 SE_TCL_MATERIAL_AMBIENT_BLUE
+0x222c SE_TCL_MATERIAL_AMBIENT_ALPHA
+0x2230 SE_TCL_MATERIAL_DIFFUSE_RED
+0x2234 SE_TCL_MATERIAL_DIFFUSE_GREEN
+0x2238 SE_TCL_MATERIAL_DIFFUSE_BLUE
+0x223c SE_TCL_MATERIAL_DIFFUSE_ALPHA
+0x2240 SE_TCL_MATERIAL_SPECULAR_RED
+0x2244 SE_TCL_MATERIAL_SPECULAR_GREEN
+0x2248 SE_TCL_MATERIAL_SPECULAR_BLUE
+0x224c SE_TCL_MATERIAL_SPECULAR_ALPHA
+0x2250 SE_TCL_SHININESS
+0x2254 SE_TCL_OUTPUT_VTX_FMT
+0x2258 SE_TCL_OUTPUT_VTX_SEL
+0x225c SE_TCL_MATRIX_SELECT_0
+0x2260 SE_TCL_MATRIX_SELECT_1
+0x2264 SE_TCL_UCP_VERT_BLEND_CNTL
+0x2268 SE_TCL_TEXTURE_PROC_CTL
+0x226c SE_TCL_LIGHT_MODEL_CTL
+0x2270 SE_TCL_PER_LIGHT_CTL_0
+0x2274 SE_TCL_PER_LIGHT_CTL_1
+0x2278 SE_TCL_PER_LIGHT_CTL_2
+0x227c SE_TCL_PER_LIGHT_CTL_3
+0x2284 SE_TCL_STATE_FLUSH
+0x26c0 RE_TOP_LEFT
+0x26c4 RE_MISC
+0x3290 RB3D_ZPASS_DATA
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r200 b/drivers/gpu/drm/radeon/reg_srcs/r200
new file mode 100644
index 00000000000..6021c8849a1
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/r200
@@ -0,0 +1,184 @@
+r200 0x3294
+0x1434 SRC_Y_X
+0x1438 DST_Y_X
+0x143C DST_HEIGHT_WIDTH
+0x146C DP_GUI_MASTER_CNTL
+0x1474 BRUSH_Y_X
+0x1478 DP_BRUSH_BKGD_CLR
+0x147C DP_BRUSH_FRGD_CLR
+0x1480 BRUSH_DATA0
+0x1484 BRUSH_DATA1
+0x1598 DST_WIDTH_HEIGHT
+0x15C0 CLR_CMP_CNTL
+0x15C4 CLR_CMP_CLR_SRC
+0x15C8 CLR_CMP_CLR_DST
+0x15CC CLR_CMP_MSK
+0x15D8 DP_SRC_FRGD_CLR
+0x15DC DP_SRC_BKGD_CLR
+0x1600 DST_LINE_START
+0x1604 DST_LINE_END
+0x1608 DST_LINE_PATCOUNT
+0x16C0 DP_CNTL
+0x16CC DP_WRITE_MSK
+0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
+0x16E8 DEFAULT_SC_BOTTOM_RIGHT
+0x16EC SC_TOP_LEFT
+0x16F0 SC_BOTTOM_RIGHT
+0x16F4 SRC_SC_BOTTOM_RIGHT
+0x1714 DSTCACHE_CTLSTAT
+0x1720 WAIT_UNTIL
+0x172C RBBM_GUICNTL
+0x1c14 PP_MISC
+0x1c18 PP_FOG_COLOR
+0x1c1c RE_SOLID_COLOR
+0x1c20 RB3D_BLENDCNTL
+0x1c4c SE_CNTL
+0x1c50 RE_CNTL
+0x1cc8 RE_STIPPLE_ADDR
+0x1ccc RE_STIPPLE_DATA
+0x1cd0 RE_LINE_PATTERN
+0x1cd4 RE_LINE_STATE
+0x1cd8 RE_SCISSOR_TL_0
+0x1cdc RE_SCISSOR_BR_0
+0x1ce0 RE_SCISSOR_TL_1
+0x1ce4 RE_SCISSOR_BR_1
+0x1ce8 RE_SCISSOR_TL_2
+0x1cec RE_SCISSOR_BR_2
+0x1d60 RB3D_DEPTHXY_OFFSET
+0x1d7c RB3D_STENCILREFMASK
+0x1d80 RB3D_ROPCNTL
+0x1d84 RB3D_PLANEMASK
+0x1d98 VAP_VPORT_XSCALE
+0x1d9c VAP_VPORT_XOFFSET
+0x1da0 VAP_VPORT_YSCALE
+0x1da4 VAP_VPORT_YOFFSET
+0x1da8 VAP_VPORT_ZSCALE
+0x1dac VAP_VPORT_ZOFFSET
+0x1db0 SE_ZBIAS_FACTOR
+0x1db4 SE_ZBIAS_CONSTANT
+0x1db8 SE_LINE_WIDTH
+0x2080 SE_VAP_CNTL
+0x2090 SE_TCL_OUTPUT_VTX_FMT_0
+0x2094 SE_TCL_OUTPUT_VTX_FMT_1
+0x20b0 SE_VTE_CNTL
+0x2140 SE_CNTL_STATUS
+0x2180 SE_VTX_STATE_CNTL
+0x2200 SE_TCL_VECTOR_INDX_REG
+0x2204 SE_TCL_VECTOR_DATA_REG
+0x2208 SE_TCL_SCALAR_INDX_REG
+0x220c SE_TCL_SCALAR_DATA_REG
+0x2230 SE_TCL_MATRIX_SEL_0
+0x2234 SE_TCL_MATRIX_SEL_1
+0x2238 SE_TCL_MATRIX_SEL_2
+0x223c SE_TCL_MATRIX_SEL_3
+0x2240 SE_TCL_MATRIX_SEL_4
+0x2250 SE_TCL_OUTPUT_VTX_COMP_SEL
+0x2254 SE_TCL_INPUT_VTX_VECTOR_ADDR_0
+0x2258 SE_TCL_INPUT_VTX_VECTOR_ADDR_1
+0x225c SE_TCL_INPUT_VTX_VECTOR_ADDR_2
+0x2260 SE_TCL_INPUT_VTX_VECTOR_ADDR_3
+0x2268 SE_TCL_LIGHT_MODEL_CTL_0
+0x226c SE_TCL_LIGHT_MODEL_CTL_1
+0x2270 SE_TCL_PER_LIGHT_CTL_0
+0x2274 SE_TCL_PER_LIGHT_CTL_1
+0x2278 SE_TCL_PER_LIGHT_CTL_2
+0x227c SE_TCL_PER_LIGHT_CTL_3
+0x2284 VAP_PVS_STATE_FLUSH_REG
+0x22a8 SE_TCL_TEX_PROC_CTL_2
+0x22ac SE_TCL_TEX_PROC_CTL_3
+0x22b0 SE_TCL_TEX_PROC_CTL_0
+0x22b4 SE_TCL_TEX_PROC_CTL_1
+0x22b8 SE_TCL_TEX_CYL_WRAP_CTL
+0x22c0 SE_TCL_UCP_VERT_BLEND_CNTL
+0x22c4 SE_TCL_POINT_SPRITE_CNTL
+0x2648 RE_POINTSIZE
+0x26c0 RE_TOP_LEFT
+0x26c4 RE_MISC
+0x26f0 RE_AUX_SCISSOR_CNTL
+0x2c14 PP_BORDER_COLOR_0
+0x2c34 PP_BORDER_COLOR_1
+0x2c54 PP_BORDER_COLOR_2
+0x2c74 PP_BORDER_COLOR_3
+0x2c94 PP_BORDER_COLOR_4
+0x2cb4 PP_BORDER_COLOR_5
+0x2cc4 PP_CNTL_X
+0x2cf8 PP_TRI_PERF
+0x2cfc PP_PERF_CNTL
+0x2d9c PP_TAM_DEBUG3
+0x2ee0 PP_TFACTOR_0
+0x2ee4 PP_TFACTOR_1
+0x2ee8 PP_TFACTOR_2
+0x2eec PP_TFACTOR_3
+0x2ef0 PP_TFACTOR_4
+0x2ef4 PP_TFACTOR_5
+0x2ef8 PP_TFACTOR_6
+0x2efc PP_TFACTOR_7
+0x2f00 PP_TXCBLEND_0
+0x2f04 PP_TXCBLEND2_0
+0x2f08 PP_TXABLEND_0
+0x2f0c PP_TXABLEND2_0
+0x2f10 PP_TXCBLEND_1
+0x2f14 PP_TXCBLEND2_1
+0x2f18 PP_TXABLEND_1
+0x2f1c PP_TXABLEND2_1
+0x2f20 PP_TXCBLEND_2
+0x2f24 PP_TXCBLEND2_2
+0x2f28 PP_TXABLEND_2
+0x2f2c PP_TXABLEND2_2
+0x2f30 PP_TXCBLEND_3
+0x2f34 PP_TXCBLEND2_3
+0x2f38 PP_TXABLEND_3
+0x2f3c PP_TXABLEND2_3
+0x2f40 PP_TXCBLEND_4
+0x2f44 PP_TXCBLEND2_4
+0x2f48 PP_TXABLEND_4
+0x2f4c PP_TXABLEND2_4
+0x2f50 PP_TXCBLEND_5
+0x2f54 PP_TXCBLEND2_5
+0x2f58 PP_TXABLEND_5
+0x2f5c PP_TXABLEND2_5
+0x2f60 PP_TXCBLEND_6
+0x2f64 PP_TXCBLEND2_6
+0x2f68 PP_TXABLEND_6
+0x2f6c PP_TXABLEND2_6
+0x2f70 PP_TXCBLEND_7
+0x2f74 PP_TXCBLEND2_7
+0x2f78 PP_TXABLEND_7
+0x2f7c PP_TXABLEND2_7
+0x2f80 PP_TXCBLEND_8
+0x2f84 PP_TXCBLEND2_8
+0x2f88 PP_TXABLEND_8
+0x2f8c PP_TXABLEND2_8
+0x2f90 PP_TXCBLEND_9
+0x2f94 PP_TXCBLEND2_9
+0x2f98 PP_TXABLEND_9
+0x2f9c PP_TXABLEND2_9
+0x2fa0 PP_TXCBLEND_10
+0x2fa4 PP_TXCBLEND2_10
+0x2fa8 PP_TXABLEND_10
+0x2fac PP_TXABLEND2_10
+0x2fb0 PP_TXCBLEND_11
+0x2fb4 PP_TXCBLEND2_11
+0x2fb8 PP_TXABLEND_11
+0x2fbc PP_TXABLEND2_11
+0x2fc0 PP_TXCBLEND_12
+0x2fc4 PP_TXCBLEND2_12
+0x2fc8 PP_TXABLEND_12
+0x2fcc PP_TXABLEND2_12
+0x2fd0 PP_TXCBLEND_13
+0x2fd4 PP_TXCBLEND2_13
+0x2fd8 PP_TXABLEND_13
+0x2fdc PP_TXABLEND2_13
+0x2fe0 PP_TXCBLEND_14
+0x2fe4 PP_TXCBLEND2_14
+0x2fe8 PP_TXABLEND_14
+0x2fec PP_TXABLEND2_14
+0x2ff0 PP_TXCBLEND_15
+0x2ff4 PP_TXCBLEND2_15
+0x2ff8 PP_TXABLEND_15
+0x2ffc PP_TXABLEND2_15
+0x3218 RB3D_BLENCOLOR
+0x321c RB3D_ABLENDCNTL
+0x3220 RB3D_CBLENDCNTL
+0x3290 RB3D_ZPASS_DATA
+
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rn50 b/drivers/gpu/drm/radeon/reg_srcs/rn50
new file mode 100644
index 00000000000..2687b630726
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/rn50
@@ -0,0 +1,30 @@
+rn50 0x3294
+0x1434 SRC_Y_X
+0x1438 DST_Y_X
+0x143C DST_HEIGHT_WIDTH
+0x146C DP_GUI_MASTER_CNTL
+0x1474 BRUSH_Y_X
+0x1478 DP_BRUSH_BKGD_CLR
+0x147C DP_BRUSH_FRGD_CLR
+0x1480 BRUSH_DATA0
+0x1484 BRUSH_DATA1
+0x1598 DST_WIDTH_HEIGHT
+0x15C0 CLR_CMP_CNTL
+0x15C4 CLR_CMP_CLR_SRC
+0x15C8 CLR_CMP_CLR_DST
+0x15CC CLR_CMP_MSK
+0x15D8 DP_SRC_FRGD_CLR
+0x15DC DP_SRC_BKGD_CLR
+0x1600 DST_LINE_START
+0x1604 DST_LINE_END
+0x1608 DST_LINE_PATCOUNT
+0x16C0 DP_CNTL
+0x16CC DP_WRITE_MSK
+0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
+0x16E8 DEFAULT_SC_BOTTOM_RIGHT
+0x16EC SC_TOP_LEFT
+0x16F0 SC_BOTTOM_RIGHT
+0x16F4 SRC_SC_BOTTOM_RIGHT
+0x1714 DSTCACHE_CTLSTAT
+0x1720 WAIT_UNTIL
+0x172C RBBM_GUICNTL
-- 
cgit v1.2.3


From 4ce001abafafe77e5dd943d1480fc9f87894e96f Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 13 Aug 2009 16:32:14 +1000
Subject: drm/radeon/kms: add initial radeon tv-out support.

This ports the tv-out code from the DDX to KMS.

adds a radeon.tv module option, radeon.tv=0 to disable tv

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/Makefile                 |   2 +-
 drivers/gpu/drm/radeon/atombios.h               |  11 +
 drivers/gpu/drm/radeon/atombios_crtc.c          |  99 ++-
 drivers/gpu/drm/radeon/radeon.h                 |   1 +
 drivers/gpu/drm/radeon/radeon_atombios.c        |  75 +-
 drivers/gpu/drm/radeon/radeon_connectors.c      | 215 +++++-
 drivers/gpu/drm/radeon/radeon_display.c         |  13 +-
 drivers/gpu/drm/radeon/radeon_drv.c             |   4 +
 drivers/gpu/drm/radeon/radeon_encoders.c        | 116 ++-
 drivers/gpu/drm/radeon/radeon_legacy_crtc.c     |  44 +-
 drivers/gpu/drm/radeon/radeon_legacy_encoders.c | 339 +++++++--
 drivers/gpu/drm/radeon/radeon_legacy_tv.c       | 904 ++++++++++++++++++++++++
 drivers/gpu/drm/radeon/radeon_mode.h            |  50 +-
 drivers/gpu/drm/radeon/radeon_reg.h             |   4 +-
 drivers/gpu/drm/radeon/rv515.c                  | 452 ++++++------
 15 files changed, 1941 insertions(+), 388 deletions(-)
 create mode 100644 drivers/gpu/drm/radeon/radeon_legacy_tv.c

diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index 6fb84296249..c5db0c4fe78 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -47,7 +47,7 @@ radeon-$(CONFIG_DRM_RADEON_KMS) += radeon_device.o radeon_kms.o \
 	radeon_clocks.o radeon_fb.o radeon_gem.o radeon_ring.o radeon_irq_kms.o \
 	radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \
 	rs400.o rs600.o rs690.o rv515.o r520.o r600.o rs780.o rv770.o \
-	radeon_test.o r200.o
+	radeon_test.o r200.o radeon_legacy_tv.o
 
 radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
 
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h
index cf67928abbc..5d402086bc4 100644
--- a/drivers/gpu/drm/radeon/atombios.h
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -2374,6 +2374,17 @@ typedef struct _ATOM_ANALOG_TV_INFO {
 	ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING];
 } ATOM_ANALOG_TV_INFO;
 
+#define MAX_SUPPORTED_TV_TIMING_V1_2    3
+
+typedef struct _ATOM_ANALOG_TV_INFO_V1_2 {
+	ATOM_COMMON_TABLE_HEADER sHeader;
+	UCHAR                    ucTV_SupportedStandard;
+	UCHAR                    ucTV_BootUpDefaultStandard;
+	UCHAR                    ucExt_TV_ASIC_ID;
+	UCHAR                    ucExt_TV_ASIC_SlaveAddr;
+	ATOM_DTD_FORMAT          aModeTimings[MAX_SUPPORTED_TV_TIMING];
+} ATOM_ANALOG_TV_INFO_V1_2;
+
 /**************************************************************************/
 /*  VRAM usage and their defintions */
 
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 74d034f77c6..8e31e992ec5 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -31,6 +31,10 @@
 #include "atom.h"
 #include "atom-bits.h"
 
+/* evil but including atombios.h is much worse */
+bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
+				SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing,
+				int32_t *pixel_clock);
 static void atombios_overscan_setup(struct drm_crtc *crtc,
 				    struct drm_display_mode *mode,
 				    struct drm_display_mode *adjusted_mode)
@@ -89,17 +93,32 @@ static void atombios_scaler_setup(struct drm_crtc *crtc)
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 	ENABLE_SCALER_PS_ALLOCATION args;
 	int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
+
 	/* fixme - fill in enc_priv for atom dac */
 	enum radeon_tv_std tv_std = TV_STD_NTSC;
+	bool is_tv = false, is_cv = false;
+	struct drm_encoder *encoder;
 
 	if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
 		return;
 
+	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+		/* find tv std */
+		if (encoder->crtc == crtc) {
+			struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+			if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
+				struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
+				tv_std = tv_dac->tv_std;
+				is_tv = true;
+			}
+		}
+	}
+
 	memset(&args, 0, sizeof(args));
 
 	args.ucScaler = radeon_crtc->crtc_id;
 
-	if (radeon_crtc->devices & (ATOM_DEVICE_TV_SUPPORT)) {
+	if (is_tv) {
 		switch (tv_std) {
 		case TV_STD_NTSC:
 		default:
@@ -128,7 +147,7 @@ static void atombios_scaler_setup(struct drm_crtc *crtc)
 			break;
 		}
 		args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
-	} else if (radeon_crtc->devices & (ATOM_DEVICE_CV_SUPPORT)) {
+	} else if (is_cv) {
 		args.ucTVStandard = ATOM_TV_CV;
 		args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 	} else {
@@ -151,9 +170,9 @@ static void atombios_scaler_setup(struct drm_crtc *crtc)
 		}
 	}
 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
-	if (radeon_crtc->devices & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)
-	    && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_RV570) {
-		atom_rv515_force_tv_scaler(rdev);
+	if ((is_tv || is_cv)
+	    && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
+		atom_rv515_force_tv_scaler(rdev, radeon_crtc);
 	}
 }
 
@@ -551,42 +570,68 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
 	struct radeon_device *rdev = dev->dev_private;
 	struct drm_encoder *encoder;
 	SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;
+	int need_tv_timings = 0;
+	bool ret;
 
 	/* TODO color tiling */
 	memset(&crtc_timing, 0, sizeof(crtc_timing));
 
-	/* TODO tv */
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
-
+		/* find tv std */
+		if (encoder->crtc == crtc) {
+			struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+
+			if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
+				struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
+				if (tv_dac) {
+					if (tv_dac->tv_std == TV_STD_NTSC ||
+					    tv_dac->tv_std == TV_STD_NTSC_J ||
+					    tv_dac->tv_std == TV_STD_PAL_M)
+						need_tv_timings = 1;
+					else
+						need_tv_timings = 2;
+					break;
+				}
+			}
+		}
 	}
 
 	crtc_timing.ucCRTC = radeon_crtc->crtc_id;
-	crtc_timing.usH_Total = adjusted_mode->crtc_htotal;
-	crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay;
-	crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start;
-	crtc_timing.usH_SyncWidth =
-	    adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
+	if (need_tv_timings) {
+		ret = radeon_atom_get_tv_timings(rdev, need_tv_timings - 1,
+						 &crtc_timing, &adjusted_mode->clock);
+		if (ret == false)
+			need_tv_timings = 0;
+	}
+
+	if (!need_tv_timings) {
+		crtc_timing.usH_Total = adjusted_mode->crtc_htotal;
+		crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay;
+		crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start;
+		crtc_timing.usH_SyncWidth =
+			adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
 
-	crtc_timing.usV_Total = adjusted_mode->crtc_vtotal;
-	crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay;
-	crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start;
-	crtc_timing.usV_SyncWidth =
-	    adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
+		crtc_timing.usV_Total = adjusted_mode->crtc_vtotal;
+		crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay;
+		crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start;
+		crtc_timing.usV_SyncWidth =
+			adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
 
-	if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
-		crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY;
+		if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
+			crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY;
 
-	if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
-		crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY;
+		if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
+			crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY;
 
-	if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
-		crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC;
+		if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
+			crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC;
 
-	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
-		crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE;
+		if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
+			crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE;
 
-	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
-		crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE;
+		if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
+			crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE;
+	}
 
 	atombios_crtc_set_pll(crtc, adjusted_mode);
 	atombios_crtc_set_timing(crtc, &crtc_timing);
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 6c35c3c2919..e47f2fc294c 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -66,6 +66,7 @@ extern int radeon_gart_size;
 extern int radeon_benchmarking;
 extern int radeon_testing;
 extern int radeon_connector_table;
+extern int radeon_tv;
 
 /*
  * Copy from radeon_drv.h so we don't have to include both and have conflicting
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index fcfe5c02d74..bba9b4bd8f5 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -471,11 +471,6 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 			continue;
 		}
 
-		if (i == ATOM_DEVICE_TV1_INDEX) {
-			DRM_DEBUG("Skipping TV Out\n");
-			continue;
-		}
-
 		bios_connectors[i].connector_type =
 		    supported_devices_connector_convert[ci.sucConnectorInfo.
 							sbfAccess.
@@ -858,6 +853,72 @@ radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
 	return p_dac;
 }
 
+bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
+				SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing,
+				int32_t *pixel_clock)
+{
+	struct radeon_mode_info *mode_info = &rdev->mode_info;
+	ATOM_ANALOG_TV_INFO *tv_info;
+	ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
+	ATOM_DTD_FORMAT *dtd_timings;
+	int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
+	u8 frev, crev;
+	uint16_t data_offset;
+
+	atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
+
+	switch (crev) {
+	case 1:
+		tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
+		if (index > MAX_SUPPORTED_TV_TIMING)
+			return false;
+
+		crtc_timing->usH_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
+		crtc_timing->usH_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
+		crtc_timing->usH_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
+		crtc_timing->usH_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
+
+		crtc_timing->usV_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
+		crtc_timing->usV_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
+		crtc_timing->usV_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
+		crtc_timing->usV_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
+
+		crtc_timing->susModeMiscInfo = tv_info->aModeTimings[index].susModeMiscInfo;
+
+		crtc_timing->ucOverscanRight = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanRight);
+		crtc_timing->ucOverscanLeft = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanLeft);
+		crtc_timing->ucOverscanBottom = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanBottom);
+		crtc_timing->ucOverscanTop = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanTop);
+		*pixel_clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
+
+		if (index == 1) {
+			/* PAL timings appear to have wrong values for totals */
+			crtc_timing->usH_Total -= 1;
+			crtc_timing->usV_Total -= 1;
+		}
+		break;
+	case 2:
+		tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
+		if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
+			return false;
+
+		dtd_timings = &tv_info_v1_2->aModeTimings[index];
+		crtc_timing->usH_Total = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHBlanking_Time);
+		crtc_timing->usH_Disp = le16_to_cpu(dtd_timings->usHActive);
+		crtc_timing->usH_SyncStart = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHSyncOffset);
+		crtc_timing->usH_SyncWidth = le16_to_cpu(dtd_timings->usHSyncWidth);
+		crtc_timing->usV_Total = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVBlanking_Time);
+		crtc_timing->usV_Disp = le16_to_cpu(dtd_timings->usVActive);
+		crtc_timing->usV_SyncStart = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVSyncOffset);
+		crtc_timing->usV_SyncWidth = le16_to_cpu(dtd_timings->usVSyncWidth);
+
+		crtc_timing->susModeMiscInfo.usAccess = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
+		*pixel_clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
+		break;
+	}
+	return true;
+}
+
 struct radeon_encoder_tv_dac *
 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
 {
@@ -948,10 +1009,10 @@ void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
 	uint32_t bios_2_scratch, bios_6_scratch;
 
 	if (rdev->family >= CHIP_R600) {
-		bios_2_scratch = RREG32(R600_BIOS_0_SCRATCH);
+		bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
 		bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
 	} else {
-		bios_2_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
+		bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
 		bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
 	}
 
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 70ede6a52d4..6a2b0296adf 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -94,6 +94,54 @@ struct drm_encoder *radeon_best_single_encoder(struct drm_connector *connector)
 	return NULL;
 }
 
+
+/*
+ * radeon_connector_analog_encoder_conflict_solve
+ * - search for other connectors sharing this encoder
+ *   if priority is true, then set them disconnected if this is connected
+ *   if priority is false, set us disconnected if they are connected
+ */
+static enum drm_connector_status
+radeon_connector_analog_encoder_conflict_solve(struct drm_connector *connector,
+					       struct drm_encoder *encoder,
+					       enum drm_connector_status current_status,
+					       bool priority)
+{
+	struct drm_device *dev = connector->dev;
+	struct drm_connector *conflict;
+	int i;
+
+	list_for_each_entry(conflict, &dev->mode_config.connector_list, head) {
+		if (conflict == connector)
+			continue;
+
+		for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
+			if (conflict->encoder_ids[i] == 0)
+				break;
+
+			/* if the IDs match */
+			if (conflict->encoder_ids[i] == encoder->base.id) {
+				if (conflict->status != connector_status_connected)
+					continue;
+
+				if (priority == true) {
+					DRM_INFO("1: conflicting encoders switching off %s\n", drm_get_connector_name(conflict));
+					DRM_INFO("in favor of %s\n", drm_get_connector_name(connector));
+					conflict->status = connector_status_disconnected;
+					radeon_connector_update_scratch_regs(conflict, connector_status_disconnected);
+				} else {
+					DRM_INFO("2: conflicting encoders switching off %s\n", drm_get_connector_name(connector));
+					DRM_INFO("in favor of %s\n", drm_get_connector_name(conflict));
+					current_status = connector_status_disconnected;
+				}
+				break;
+			}
+		}
+	}
+	return current_status;
+
+}
+
 static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encoder)
 {
 	struct drm_device *dev = encoder->dev;
@@ -213,7 +261,6 @@ static int radeon_vga_get_modes(struct drm_connector *connector)
 static int radeon_vga_mode_valid(struct drm_connector *connector,
 				  struct drm_display_mode *mode)
 {
-
 	return MODE_OK;
 }
 
@@ -225,22 +272,22 @@ static enum drm_connector_status radeon_vga_detect(struct drm_connector *connect
 	bool dret;
 	enum drm_connector_status ret = connector_status_disconnected;
 
+	encoder = radeon_best_single_encoder(connector);
+	if (!encoder)
+		ret = connector_status_disconnected;
+
 	radeon_i2c_do_lock(radeon_connector, 1);
 	dret = radeon_ddc_probe(radeon_connector);
 	radeon_i2c_do_lock(radeon_connector, 0);
 	if (dret)
 		ret = connector_status_connected;
 	else {
-		/* if EDID fails to a load detect */
-		encoder = radeon_best_single_encoder(connector);
-		if (!encoder)
-			ret = connector_status_disconnected;
-		else {
-			encoder_funcs = encoder->helper_private;
-			ret = encoder_funcs->detect(encoder, connector);
-		}
+		encoder_funcs = encoder->helper_private;
+		ret = encoder_funcs->detect(encoder, connector);
 	}
 
+	if (ret == connector_status_connected)
+		ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, true);
 	radeon_connector_update_scratch_regs(connector, ret);
 	return ret;
 }
@@ -259,21 +306,87 @@ struct drm_connector_funcs radeon_vga_connector_funcs = {
 	.set_property = radeon_connector_set_property,
 };
 
+static struct drm_display_mode tv_fixed_mode = {
+	DRM_MODE("800x600", DRM_MODE_TYPE_DEFAULT, 38250, 800, 832,
+		 912, 1024, 0, 600, 603, 607, 624, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC),
+};
+
+static int radeon_tv_get_modes(struct drm_connector *connector)
+{
+	struct drm_device *dev = connector->dev;
+	struct drm_display_mode *tv_mode;
+
+	tv_mode = drm_mode_duplicate(dev, &tv_fixed_mode);
+	tv_mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+
+	drm_mode_probed_add(connector, tv_mode);
+
+	return 1;
+}
+
+static int radeon_tv_mode_valid(struct drm_connector *connector,
+				struct drm_display_mode *mode)
+{
+	return MODE_OK;
+}
+
+static enum drm_connector_status radeon_tv_detect(struct drm_connector *connector)
+{
+	struct drm_encoder *encoder;
+	struct drm_encoder_helper_funcs *encoder_funcs;
+	int ret;
+
+	encoder = radeon_best_single_encoder(connector);
+	if (!encoder)
+		ret = connector_status_disconnected;
+	else {
+		encoder_funcs = encoder->helper_private;
+		ret = encoder_funcs->detect(encoder, connector);
+	}
+	if (ret == connector_status_connected)
+		ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, false);
+	radeon_connector_update_scratch_regs(connector, ret);
+	return ret;
+}
+
+struct drm_connector_helper_funcs radeon_tv_connector_helper_funcs = {
+	.get_modes = radeon_tv_get_modes,
+	.mode_valid = radeon_tv_mode_valid,
+	.best_encoder = radeon_best_single_encoder,
+};
+
+struct drm_connector_funcs radeon_tv_connector_funcs = {
+	.dpms = drm_helper_connector_dpms,
+	.detect = radeon_tv_detect,
+	.fill_modes = drm_helper_probe_single_connector_modes,
+	.destroy = radeon_connector_destroy,
+	.set_property = radeon_connector_set_property,
+};
+
 static int radeon_dvi_get_modes(struct drm_connector *connector)
 {
 	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 	int ret;
 
 	ret = radeon_ddc_get_modes(radeon_connector);
-	/* reset scratch regs here since radeon_dvi_detect doesn't check digital bit */
-	radeon_connector_update_scratch_regs(connector, connector_status_connected);
 	return ret;
 }
 
+/*
+ * DVI is complicated
+ * Do a DDC probe, if DDC probe passes, get the full EDID so
+ * we can do analog/digital monitor detection at this point.
+ * If the monitor is an analog monitor or we got no DDC,
+ * we need to find the DAC encoder object for this connector.
+ * If we got no DDC, we do load detection on the DAC encoder object.
+ * If we got analog DDC or load detection passes on the DAC encoder
+ * we have to check if this analog encoder is shared with anyone else (TV)
+ * if its shared we have to set the other connector to disconnected.
+ */
 static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connector)
 {
 	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
-	struct drm_encoder *encoder;
+	struct drm_encoder *encoder = NULL;
 	struct drm_encoder_helper_funcs *encoder_funcs;
 	struct drm_mode_object *obj;
 	int i;
@@ -283,32 +396,58 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect
 	radeon_i2c_do_lock(radeon_connector, 1);
 	dret = radeon_ddc_probe(radeon_connector);
 	radeon_i2c_do_lock(radeon_connector, 0);
-	if (dret)
-		ret = connector_status_connected;
-	else {
-		for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
-			if (connector->encoder_ids[i] == 0)
-				break;
+	if (dret) {
+		radeon_i2c_do_lock(radeon_connector, 1);
+		radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
+		radeon_i2c_do_lock(radeon_connector, 0);
+
+		if (!radeon_connector->edid) {
+			DRM_ERROR("DDC responded but not EDID found for %s\n",
+				  drm_get_connector_name(connector));
+		} else {
+			radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
+
+			/* if this isn't a digital monitor
+			   then we need to make sure we don't have any
+			   TV conflicts */
+			ret = connector_status_connected;
+		}
+	}
+
+	if ((ret == connector_status_connected) && (radeon_connector->use_digital == true))
+		goto out;
+
+	/* find analog encoder */
+	for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
+		if (connector->encoder_ids[i] == 0)
+			break;
 
-			obj = drm_mode_object_find(connector->dev,
-						   connector->encoder_ids[i],
-						   DRM_MODE_OBJECT_ENCODER);
-			if (!obj)
-				continue;
+		obj = drm_mode_object_find(connector->dev,
+					   connector->encoder_ids[i],
+					   DRM_MODE_OBJECT_ENCODER);
+		if (!obj)
+			continue;
 
-			encoder = obj_to_encoder(obj);
+		encoder = obj_to_encoder(obj);
 
-			encoder_funcs = encoder->helper_private;
-			if (encoder_funcs->detect) {
+		encoder_funcs = encoder->helper_private;
+		if (encoder_funcs->detect) {
+			if (ret != connector_status_connected) {
 				ret = encoder_funcs->detect(encoder, connector);
 				if (ret == connector_status_connected) {
-					radeon_connector->use_digital = 0;
-					break;
+					radeon_connector->use_digital = false;
 				}
 			}
+			break;
 		}
 	}
 
+	if ((ret == connector_status_connected) && (radeon_connector->use_digital == false) &&
+	    encoder) {
+		ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, true);
+	}
+
+out:
 	/* updated in get modes as well since we need to know if it's analog or digital */
 	radeon_connector_update_scratch_regs(connector, ret);
 	return ret;
@@ -332,7 +471,7 @@ struct drm_encoder *radeon_dvi_encoder(struct drm_connector *connector)
 
 		encoder = obj_to_encoder(obj);
 
-		if (radeon_connector->use_digital) {
+		if (radeon_connector->use_digital == true) {
 			if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
 				return encoder;
 		} else {
@@ -385,10 +524,7 @@ radeon_add_atom_connector(struct drm_device *dev,
 	uint32_t subpixel_order = SubPixelNone;
 
 	/* fixme - tv/cv/din */
-	if ((connector_type == DRM_MODE_CONNECTOR_Unknown) ||
-	    (connector_type == DRM_MODE_CONNECTOR_SVIDEO) ||
-	    (connector_type == DRM_MODE_CONNECTOR_Composite) ||
-	    (connector_type == DRM_MODE_CONNECTOR_9PinDIN))
+	if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 		return;
 
 	/* see if we already added it */
@@ -480,6 +616,10 @@ radeon_add_atom_connector(struct drm_device *dev,
 	case DRM_MODE_CONNECTOR_SVIDEO:
 	case DRM_MODE_CONNECTOR_Composite:
 	case DRM_MODE_CONNECTOR_9PinDIN:
+		if (radeon_tv == 1) {
+			drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type);
+			drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs);
+		}
 		break;
 	case DRM_MODE_CONNECTOR_LVDS:
 		radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
@@ -522,10 +662,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
 	uint32_t subpixel_order = SubPixelNone;
 
 	/* fixme - tv/cv/din */
-	if ((connector_type == DRM_MODE_CONNECTOR_Unknown) ||
-	    (connector_type == DRM_MODE_CONNECTOR_SVIDEO) ||
-	    (connector_type == DRM_MODE_CONNECTOR_Composite) ||
-	    (connector_type == DRM_MODE_CONNECTOR_9PinDIN))
+	if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 		return;
 
 	/* see if we already added it */
@@ -578,6 +715,10 @@ radeon_add_legacy_connector(struct drm_device *dev,
 	case DRM_MODE_CONNECTOR_SVIDEO:
 	case DRM_MODE_CONNECTOR_Composite:
 	case DRM_MODE_CONNECTOR_9PinDIN:
+		if (radeon_tv == 1) {
+			drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type);
+			drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs);
+		}
 		break;
 	case DRM_MODE_CONNECTOR_LVDS:
 		drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type);
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index af035605d14..9d817a62e7f 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -312,7 +312,7 @@ static void radeon_print_display_setup(struct drm_device *dev)
 	}
 }
 
-bool radeon_setup_enc_conn(struct drm_device *dev)
+static bool radeon_setup_enc_conn(struct drm_device *dev)
 {
 	struct radeon_device *rdev = dev->dev_private;
 	struct drm_connector *drm_connector;
@@ -346,9 +346,13 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 
 	if (!radeon_connector->ddc_bus)
 		return -1;
-	radeon_i2c_do_lock(radeon_connector, 1);
-	edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
-	radeon_i2c_do_lock(radeon_connector, 0);
+	if (!radeon_connector->edid) {
+		radeon_i2c_do_lock(radeon_connector, 1);
+		edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
+		radeon_i2c_do_lock(radeon_connector, 0);
+	} else
+		edid = radeon_connector->edid;
+
 	if (edid) {
 		/* update digital bits here */
 		if (edid->input & DRM_EDID_INPUT_DIGITAL)
@@ -677,7 +681,6 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
 			continue;
 		if (first) {
 			radeon_crtc->rmx_type = radeon_encoder->rmx_type;
-			radeon_crtc->devices = radeon_encoder->devices;
 			memcpy(&radeon_crtc->native_mode,
 				&radeon_encoder->native_mode,
 				sizeof(struct radeon_native_mode));
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 0bd5879a495..133e975dbf0 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -91,6 +91,7 @@ int radeon_gart_size = 512; /* default gart size */
 int radeon_benchmarking = 0;
 int radeon_testing = 0;
 int radeon_connector_table = 0;
+int radeon_tv = 1;
 #endif
 
 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
@@ -123,6 +124,9 @@ module_param_named(test, radeon_testing, int, 0444);
 
 MODULE_PARM_DESC(connector_table, "Force connector table");
 module_param_named(connector_table, radeon_connector_table, int, 0444);
+
+MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
+module_param_named(tv, radeon_tv, int, 0444);
 #endif
 
 static int radeon_suspend(struct drm_device *dev, pm_message_t state)
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 0a92706eac1..5c4ede7c990 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -126,6 +126,23 @@ radeon_link_encoder_connector(struct drm_device *dev)
 	}
 }
 
+void radeon_encoder_set_active_device(struct drm_encoder *encoder)
+{
+	struct drm_device *dev = encoder->dev;
+	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+	struct drm_connector *connector;
+
+	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+		if (connector->encoder == encoder) {
+			struct radeon_connector *radeon_connector = to_radeon_connector(connector);
+			radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
+			DRM_INFO("setting active device to %08x from %08x %08x for encoder %d\n",
+				 radeon_encoder->active_device, radeon_encoder->devices,
+				 radeon_connector->devices, encoder->encoder_type);
+		}
+	}
+}
+
 static struct drm_connector *
 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
 {
@@ -244,9 +261,9 @@ atombios_dac_setup(struct drm_encoder *encoder, int action)
 
 	args.ucAction = action;
 
-	if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
+	if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 		args.ucDacStandard = ATOM_DAC1_PS2;
-	else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 		args.ucDacStandard = ATOM_DAC1_CV;
 	else {
 		switch (tv_std) {
@@ -288,7 +305,7 @@ atombios_tv_setup(struct drm_encoder *encoder, int action)
 
 	args.sTVEncoder.ucAction = action;
 
-	if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+	if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 		args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 	else {
 		switch (tv_std) {
@@ -825,10 +842,10 @@ atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
 
 	/* XXX: fix up scratch reg handling */
 	temp = RREG32(reg);
-	if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
+	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 		WREG32(reg, (ATOM_S3_TV1_ACTIVE |
 			     (radeon_crtc->crtc_id << 18)));
-	else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 		WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
 	else
 		WREG32(reg, 0);
@@ -851,9 +868,19 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
 	DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
 	int index = 0;
 	bool is_dig = false;
+	int devices;
 
 	memset(&args, 0, sizeof(args));
 
+	/* on DPMS off we have no idea if active device is meaningful */
+	if (mode != DRM_MODE_DPMS_ON && !radeon_encoder->active_device)
+		devices = radeon_encoder->devices;
+	else
+		devices = radeon_encoder->active_device;
+
+	DRM_INFO("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
+		 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
+		radeon_encoder->active_device);
 	switch (radeon_encoder->encoder_id) {
 	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
@@ -881,18 +908,18 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
 		break;
 	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
-		if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
+		if (devices & (ATOM_DEVICE_TV_SUPPORT))
 			index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
-		else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+		else if (devices & (ATOM_DEVICE_CV_SUPPORT))
 			index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
 		else
 			index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
 		break;
 	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
-		if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
+		if (devices & (ATOM_DEVICE_TV_SUPPORT))
 			index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
-		else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+		else if (devices & (ATOM_DEVICE_CV_SUPPORT))
 			index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
 		else
 			index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
@@ -979,18 +1006,18 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
 				break;
 			case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
-				if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
+				if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 					args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
-				else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+				else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 					args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
 				else
 					args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
 				break;
 			case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
-				if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
+				if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 					args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
-				else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+				else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 					args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
 				else
 					args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
@@ -1019,17 +1046,17 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
 				args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
 				break;
 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
-				if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
+				if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 					args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
-				else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+				else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 					args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
 				else
 					args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
 				break;
 			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
-				if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
+				if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 					args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
-				else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+				else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 					args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
 				else
 					args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
@@ -1097,7 +1124,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
 	atombios_set_encoder_crtc_source(encoder);
 
 	if (ASIC_IS_AVIVO(rdev)) {
-		if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
+		if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
 			atombios_yuv_setup(encoder, true);
 		else
 			atombios_yuv_setup(encoder, false);
@@ -1135,7 +1162,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
 	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 		atombios_dac_setup(encoder, ATOM_ENABLE);
-		if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
+		if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
 			atombios_tv_setup(encoder, ATOM_ENABLE);
 		break;
 	}
@@ -1143,11 +1170,12 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
 }
 
 static bool
-atombios_dac_load_detect(struct drm_encoder *encoder)
+atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 {
 	struct drm_device *dev = encoder->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 
 	if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
 				       ATOM_DEVICE_CV_SUPPORT |
@@ -1168,15 +1196,15 @@ atombios_dac_load_detect(struct drm_encoder *encoder)
 		else
 			args.sDacload.ucDacType = ATOM_DAC_B;
 
-		if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT)
+		if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
 			args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
-		else if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT)
+		else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
 			args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
-		else if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
+		else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
 			args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
 			if (crev >= 3)
 				args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
-		} else if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
+		} else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
 			args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
 			if (crev >= 3)
 				args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
@@ -1195,9 +1223,10 @@ radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connec
 	struct drm_device *dev = encoder->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 	uint32_t bios_0_scratch;
 
-	if (!atombios_dac_load_detect(encoder)) {
+	if (!atombios_dac_load_detect(encoder, connector)) {
 		DRM_DEBUG("detect returned false \n");
 		return connector_status_unknown;
 	}
@@ -1207,17 +1236,20 @@ radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connec
 	else
 		bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
 
-	DRM_DEBUG("Bios 0 scratch %x\n", bios_0_scratch);
-	if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
+	DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
+	if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
 		if (bios_0_scratch & ATOM_S0_CRT1_MASK)
 			return connector_status_connected;
-	} else if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
+	}
+	if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
 		if (bios_0_scratch & ATOM_S0_CRT2_MASK)
 			return connector_status_connected;
-	} else if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
+	}
+	if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
 		if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
 			return connector_status_connected;
-	} else if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
+	}
+	if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
 		if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
 			return connector_status_connected; /* CTV */
 		else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
@@ -1230,6 +1262,8 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
 {
 	radeon_atom_output_lock(encoder, true);
 	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
+
+	radeon_encoder_set_active_device(encoder);
 }
 
 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
@@ -1238,12 +1272,21 @@ static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
 	radeon_atom_output_lock(encoder, false);
 }
 
+static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
+{
+	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
+	DRM_INFO("setting active device to 0 for encoder %d\n", encoder->encoder_type);
+	radeon_encoder->active_device = 0;
+}
+
 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
 	.dpms = radeon_atom_encoder_dpms,
 	.mode_fixup = radeon_atom_mode_fixup,
 	.prepare = radeon_atom_encoder_prepare,
 	.mode_set = radeon_atom_encoder_mode_set,
 	.commit = radeon_atom_encoder_commit,
+	.disable = radeon_atom_encoder_disable,
 	/* no detect for TMDS/LVDS yet */
 };
 
@@ -1268,6 +1311,18 @@ static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
 	.destroy = radeon_enc_destroy,
 };
 
+struct radeon_encoder_atom_dac *
+radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
+{
+	struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
+
+	if (!dac)
+		return NULL;
+
+	dac->tv_std = TV_STD_NTSC;
+	return dac;
+}
+
 struct radeon_encoder_atom_dig *
 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
 {
@@ -1336,6 +1391,7 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su
 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 		drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
+		radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
 		drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
 		break;
 	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index 0da72f18fd3..0d29d15aa62 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -28,6 +28,7 @@
 #include <drm/radeon_drm.h>
 #include "radeon_fixed.h"
 #include "radeon.h"
+#include "atom.h"
 
 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
 				       struct drm_display_mode *mode,
@@ -501,6 +502,7 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
 	struct drm_device *dev = crtc->dev;
 	struct radeon_device *rdev = dev->dev_private;
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+	struct drm_encoder *encoder;
 	int format;
 	int hsync_start;
 	int hsync_wid;
@@ -509,8 +511,19 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
 	uint32_t crtc_h_sync_strt_wid;
 	uint32_t crtc_v_total_disp;
 	uint32_t crtc_v_sync_strt_wid;
+	bool is_tv = false;
 
 	DRM_DEBUG("\n");
+	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+		if (encoder->crtc == crtc) {
+			struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+			if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
+				is_tv = true;
+				DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
+				break;
+			}
+		}
+	}
 
 	switch (crtc->fb->bits_per_pixel) {
 	case 15:      /*  555 */
@@ -642,6 +655,11 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
 		WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 	}
 
+	if (is_tv)
+		radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
+						 &crtc_h_sync_strt_wid, &crtc_v_total_disp,
+						 &crtc_v_sync_strt_wid);
+
 	WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
 	WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
 	WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
@@ -668,7 +686,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 	uint32_t pll_ref_div = 0;
 	uint32_t pll_fb_post_div = 0;
 	uint32_t htotal_cntl = 0;
-
+	bool is_tv = false;
 	struct radeon_pll *pll;
 
 	struct {
@@ -703,6 +721,13 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 		if (encoder->crtc == crtc) {
+			struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+
+			if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
+				is_tv = true;
+				break;
+			}
+
 			if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 				pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
 			if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
@@ -766,6 +791,12 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 					  ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
 					 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
 
+		if (is_tv) {
+			radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
+						     &pll_ref_div, &pll_fb_post_div,
+						     &pixclks_cntl);
+		}
+
 		WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
 			     RADEON_PIX2CLK_SRC_SEL_CPUCLK,
 			     ~(RADEON_PIX2CLK_SRC_SEL_MASK));
@@ -820,6 +851,15 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 
 		WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
 	} else {
+		uint32_t pixclks_cntl;
+
+
+		if (is_tv) {
+			pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
+			radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
+						     &pll_fb_post_div, &pixclks_cntl);
+		}
+
 		if (rdev->flags & RADEON_IS_MOBILITY) {
 			/* A temporal workaround for the occational blanking on certain laptop panels.
 			   This appears to related to the PLL divider registers (fail to lock?).
@@ -914,6 +954,8 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 			     RADEON_VCLK_SRC_SEL_PPLLCLK,
 			     ~(RADEON_VCLK_SRC_SEL_MASK));
 
+		if (is_tv)
+			WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
 	}
 }
 
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index 9322675ef6d..0aaafcd2089 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -29,6 +29,15 @@
 #include "radeon.h"
 #include "atom.h"
 
+static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
+{
+	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+	struct drm_encoder_helper_funcs *encoder_funcs;
+
+	encoder_funcs = encoder->helper_private;
+	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
+	radeon_encoder->active_device = 0;
+}
 
 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
 {
@@ -98,6 +107,8 @@ static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
 	else
 		radeon_combios_output_lock(encoder, true);
 	radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
+
+	radeon_encoder_set_active_device(encoder);
 }
 
 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
@@ -195,6 +206,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
 	.prepare = radeon_legacy_lvds_prepare,
 	.mode_set = radeon_legacy_lvds_mode_set,
 	.commit = radeon_legacy_lvds_commit,
+	.disable = radeon_legacy_encoder_disable,
 };
 
 
@@ -260,6 +272,7 @@ static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
 	else
 		radeon_combios_output_lock(encoder, true);
 	radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
+	radeon_encoder_set_active_device(encoder);
 }
 
 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
@@ -402,6 +415,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_fu
 	.mode_set = radeon_legacy_primary_dac_mode_set,
 	.commit = radeon_legacy_primary_dac_commit,
 	.detect = radeon_legacy_primary_dac_detect,
+	.disable = radeon_legacy_encoder_disable,
 };
 
 
@@ -454,6 +468,7 @@ static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
 	else
 		radeon_combios_output_lock(encoder, true);
 	radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
+	radeon_encoder_set_active_device(encoder);
 }
 
 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
@@ -566,6 +581,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs
 	.prepare = radeon_legacy_tmds_int_prepare,
 	.mode_set = radeon_legacy_tmds_int_mode_set,
 	.commit = radeon_legacy_tmds_int_commit,
+	.disable = radeon_legacy_encoder_disable,
 };
 
 
@@ -620,6 +636,7 @@ static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
 	else
 		radeon_combios_output_lock(encoder, true);
 	radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
+	radeon_encoder_set_active_device(encoder);
 }
 
 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
@@ -706,6 +723,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs
 	.prepare = radeon_legacy_tmds_ext_prepare,
 	.mode_set = radeon_legacy_tmds_ext_mode_set,
 	.commit = radeon_legacy_tmds_ext_commit,
+	.disable = radeon_legacy_encoder_disable,
 };
 
 
@@ -727,17 +745,21 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
 {
 	struct drm_device *dev = encoder->dev;
 	struct radeon_device *rdev = dev->dev_private;
+	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 	uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
-	/* uint32_t tv_master_cntl = 0; */
-
+	uint32_t tv_master_cntl = 0;
+	bool is_tv;
 	DRM_DEBUG("\n");
 
+	is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
+
 	if (rdev->family == CHIP_R200)
 		fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 	else {
-		crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
-		/*  FIXME TV */
-		/* tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); */
+		if (is_tv)
+			tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
+		else
+			crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 		tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
 	}
 
@@ -746,20 +768,23 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
 		if (rdev->family == CHIP_R200) {
 			fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 		} else {
-			crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
-			/* tv_master_cntl |= RADEON_TV_ON; */
+			if (is_tv)
+				tv_master_cntl |= RADEON_TV_ON;
+			else
+				crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
+
 			if (rdev->family == CHIP_R420 ||
-					rdev->family == CHIP_R423 ||
-					rdev->family == CHIP_RV410)
+			    rdev->family == CHIP_R423 ||
+			    rdev->family == CHIP_RV410)
 				tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
-						R420_TV_DAC_GDACPD |
-						R420_TV_DAC_BDACPD |
-						RADEON_TV_DAC_BGSLEEP);
+						 R420_TV_DAC_GDACPD |
+						 R420_TV_DAC_BDACPD |
+						 RADEON_TV_DAC_BGSLEEP);
 			else
 				tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
-						RADEON_TV_DAC_GDACPD |
-						RADEON_TV_DAC_BDACPD |
-						RADEON_TV_DAC_BGSLEEP);
+						 RADEON_TV_DAC_GDACPD |
+						 RADEON_TV_DAC_BDACPD |
+						 RADEON_TV_DAC_BGSLEEP);
 		}
 		break;
 	case DRM_MODE_DPMS_STANDBY:
@@ -768,8 +793,11 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
 		if (rdev->family == CHIP_R200)
 			fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 		else {
-			crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
-			/* tv_master_cntl &= ~RADEON_TV_ON; */
+			if (is_tv)
+				tv_master_cntl &= ~RADEON_TV_ON;
+			else
+				crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
+
 			if (rdev->family == CHIP_R420 ||
 					rdev->family == CHIP_R423 ||
 					rdev->family == CHIP_RV410)
@@ -789,8 +817,10 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
 	if (rdev->family == CHIP_R200) {
 		WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 	} else {
-		WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
-		/* WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); */
+		if (is_tv)
+			WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
+		else
+			WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 		WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 	}
 
@@ -809,6 +839,7 @@ static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
 	else
 		radeon_combios_output_lock(encoder, true);
 	radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
+	radeon_encoder_set_active_device(encoder);
 }
 
 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
@@ -831,11 +862,15 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
 	struct radeon_device *rdev = dev->dev_private;
 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
 	uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
-	uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0;
+	uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
+	bool is_tv = false;
 
 	DRM_DEBUG("\n");
 
+	is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
+
 	if (rdev->family != CHIP_R200) {
 		tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
 		if (rdev->family == CHIP_R420 ||
@@ -858,7 +893,7 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
 		}
 
 		/*  FIXME TV */
-		if (radeon_encoder->enc_priv) {
+		if (tv_dac) {
 			struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
 			tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
 					RADEON_TV_DAC_NHOLD |
@@ -875,44 +910,93 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
 	if (ASIC_IS_R300(rdev)) {
 		gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
 		disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
-	} else if (rdev->family == CHIP_R200)
-		fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
+	}
+
+	if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev))
+		disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
 	else
 		disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
 
-	dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
+	if (rdev->family == CHIP_R200)
+		fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 
-	if (radeon_crtc->crtc_id == 0) {
-		if (ASIC_IS_R300(rdev)) {
-			disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
-			disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
-		} else if (rdev->family == CHIP_R200) {
-			fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
-					  RADEON_FP2_DVO_RATE_SEL_SDR);
-		} else
-			disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
+	if (is_tv) {
+		uint32_t dac_cntl;
+
+		dac_cntl = RREG32(RADEON_DAC_CNTL);
+		dac_cntl &= ~RADEON_DAC_TVO_EN;
+		WREG32(RADEON_DAC_CNTL, dac_cntl);
+
+		if (ASIC_IS_R300(rdev))
+			gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
+
+		dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
+		if (radeon_crtc->crtc_id == 0) {
+			if (ASIC_IS_R300(rdev)) {
+				disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
+				disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
+						     RADEON_DISP_TV_SOURCE_CRTC);
+			}
+			if (rdev->family >= CHIP_R200) {
+				disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
+			} else {
+				disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
+			}
+		} else {
+			if (ASIC_IS_R300(rdev)) {
+				disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
+				disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
+			}
+			if (rdev->family >= CHIP_R200) {
+				disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
+			} else {
+				disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
+			}
+		}
+		WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 	} else {
-		if (ASIC_IS_R300(rdev)) {
-			disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
-			disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
-		} else if (rdev->family == CHIP_R200) {
-			fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
-					  RADEON_FP2_DVO_RATE_SEL_SDR);
-			fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
-		} else
-			disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
-	}
 
-	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
+		dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
+
+		if (radeon_crtc->crtc_id == 0) {
+			if (ASIC_IS_R300(rdev)) {
+				disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
+				disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
+			} else if (rdev->family == CHIP_R200) {
+				fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
+						  RADEON_FP2_DVO_RATE_SEL_SDR);
+			} else
+				disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
+		} else {
+			if (ASIC_IS_R300(rdev)) {
+				disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
+				disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
+			} else if (rdev->family == CHIP_R200) {
+				fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
+						  RADEON_FP2_DVO_RATE_SEL_SDR);
+				fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
+			} else
+				disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
+		}
+		WREG32(RADEON_DAC_CNTL2, dac2_cntl);
+	}
 
 	if (ASIC_IS_R300(rdev)) {
 		WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
-		WREG32(RADEON_DISP_TV_OUT_CNTL, disp_output_cntl);
-	} else if (rdev->family == CHIP_R200)
-		WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
+		WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
+	}
+
+	if (rdev->family >= CHIP_R200)
+		WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
 	else
 		WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
 
+	if (rdev->family == CHIP_R200)
+		WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
+
+	if (is_tv)
+		radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
+
 	if (rdev->is_atom_bios)
 		radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 	else
@@ -920,6 +1004,141 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
 
 }
 
+static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
+				  struct drm_connector *connector)
+{
+	struct drm_device *dev = encoder->dev;
+	struct radeon_device *rdev = dev->dev_private;
+	uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
+	uint32_t disp_output_cntl, gpiopad_a, tmp;
+	bool found = false;
+
+	/* save regs needed */
+	gpiopad_a = RREG32(RADEON_GPIOPAD_A);
+	dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
+	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
+	dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
+	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
+	disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
+
+	WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
+
+	WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
+
+	WREG32(RADEON_CRTC2_GEN_CNTL,
+	       RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
+
+	tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
+	tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
+	WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
+
+	WREG32(RADEON_DAC_EXT_CNTL,
+	       RADEON_DAC2_FORCE_BLANK_OFF_EN |
+	       RADEON_DAC2_FORCE_DATA_EN |
+	       RADEON_DAC_FORCE_DATA_SEL_RGB |
+	       (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
+
+	WREG32(RADEON_TV_DAC_CNTL,
+	       RADEON_TV_DAC_STD_NTSC |
+	       (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
+	       (6 << RADEON_TV_DAC_DACADJ_SHIFT));
+
+	RREG32(RADEON_TV_DAC_CNTL);
+	mdelay(4);
+
+	WREG32(RADEON_TV_DAC_CNTL,
+	       RADEON_TV_DAC_NBLANK |
+	       RADEON_TV_DAC_NHOLD |
+	       RADEON_TV_MONITOR_DETECT_EN |
+	       RADEON_TV_DAC_STD_NTSC |
+	       (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
+	       (6 << RADEON_TV_DAC_DACADJ_SHIFT));
+
+	RREG32(RADEON_TV_DAC_CNTL);
+	mdelay(6);
+
+	tmp = RREG32(RADEON_TV_DAC_CNTL);
+	if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
+		found = true;
+		DRM_DEBUG("S-video TV connection detected\n");
+	} else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
+		found = true;
+		DRM_DEBUG("Composite TV connection detected\n");
+	}
+
+	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
+	WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
+	WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
+	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
+	WREG32(RADEON_DAC_CNTL2, dac_cntl2);
+	WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
+	return found;
+}
+
+static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
+				    struct drm_connector *connector)
+{
+	struct drm_device *dev = encoder->dev;
+	struct radeon_device *rdev = dev->dev_private;
+	uint32_t tv_dac_cntl, dac_cntl2;
+	uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
+	bool found = false;
+
+	if (ASIC_IS_R300(rdev))
+		return r300_legacy_tv_detect(encoder, connector);
+
+	dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
+	tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
+	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
+	config_cntl = RREG32(RADEON_CONFIG_CNTL);
+	tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
+
+	tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
+	WREG32(RADEON_DAC_CNTL2, tmp);
+
+	tmp = tv_master_cntl | RADEON_TV_ON;
+	tmp &= ~(RADEON_TV_ASYNC_RST |
+		 RADEON_RESTART_PHASE_FIX |
+		 RADEON_CRT_FIFO_CE_EN |
+		 RADEON_TV_FIFO_CE_EN |
+		 RADEON_RE_SYNC_NOW_SEL_MASK);
+	tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
+	WREG32(RADEON_TV_MASTER_CNTL, tmp);
+
+	tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
+		RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
+		(8 << RADEON_TV_DAC_BGADJ_SHIFT);
+
+	if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
+		tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
+	else
+		tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
+	WREG32(RADEON_TV_DAC_CNTL, tmp);
+
+	tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
+		RADEON_RED_MX_FORCE_DAC_DATA |
+		RADEON_GRN_MX_FORCE_DAC_DATA |
+		RADEON_BLU_MX_FORCE_DAC_DATA |
+		(0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
+	WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
+
+	mdelay(3);
+	tmp = RREG32(RADEON_TV_DAC_CNTL);
+	if (tmp & RADEON_TV_DAC_GDACDET) {
+		found = true;
+		DRM_DEBUG("S-video TV connection detected\n");
+	} else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
+		found = true;
+		DRM_DEBUG("Composite TV connection detected\n");
+	}
+
+	WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
+	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
+	WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
+	WREG32(RADEON_DAC_CNTL2, dac_cntl2);
+	return found;
+}
+
 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
 							     struct drm_connector *connector)
 {
@@ -928,9 +1147,29 @@ static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder
 	uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
 	uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
 	enum drm_connector_status found = connector_status_disconnected;
+	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
 	bool color = true;
 
-	/*  FIXME tv */
+	if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
+	    connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
+	    connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
+		bool tv_detect;
+
+		if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
+			return connector_status_disconnected;
+
+		tv_detect = radeon_legacy_tv_detect(encoder, connector);
+		if (tv_detect && tv_dac)
+			found = connector_status_connected;
+		return found;
+	}
+
+	/* don't probe if the encoder is being used for something else not CRT related */
+	if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
+		DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
+		return connector_status_disconnected;
+	}
 
 	/* save the regs we need */
 	pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
@@ -1013,8 +1252,7 @@ static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder
 	}
 	WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
 
-	/* return found; */
-	return connector_status_disconnected;
+	return found;
 
 }
 
@@ -1025,6 +1263,7 @@ static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs =
 	.mode_set = radeon_legacy_tv_dac_mode_set,
 	.commit = radeon_legacy_tv_dac_commit,
 	.detect = radeon_legacy_tv_dac_detect,
+	.disable = radeon_legacy_encoder_disable,
 };
 
 
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_tv.c b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
new file mode 100644
index 00000000000..3a12bb0c056
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
@@ -0,0 +1,904 @@
+#include "drmP.h"
+#include "drm_crtc_helper.h"
+#include "radeon.h"
+
+/*
+ * Integrated TV out support based on the GATOS code by
+ * Federico Ulivi <fulivi@lycos.com>
+ */
+
+
+/*
+ * Limits of h/v positions (hPos & vPos)
+ */
+#define MAX_H_POSITION 5 /* Range: [-5..5], negative is on the left, 0 is default, positive is on the right */
+#define MAX_V_POSITION 5 /* Range: [-5..5], negative is up, 0 is default, positive is down */
+
+/*
+ * Unit for hPos (in TV clock periods)
+ */
+#define H_POS_UNIT 10
+
+/*
+ * Indexes in h. code timing table for horizontal line position adjustment
+ */
+#define H_TABLE_POS1 6
+#define H_TABLE_POS2 8
+
+/*
+ * Limits of hor. size (hSize)
+ */
+#define MAX_H_SIZE 5 /* Range: [-5..5], negative is smaller, positive is larger */
+
+/* tv standard constants */
+#define NTSC_TV_CLOCK_T 233
+#define NTSC_TV_VFTOTAL 1
+#define NTSC_TV_LINES_PER_FRAME 525
+#define NTSC_TV_ZERO_H_SIZE 479166
+#define NTSC_TV_H_SIZE_UNIT 9478
+
+#define PAL_TV_CLOCK_T 188
+#define PAL_TV_VFTOTAL 3
+#define PAL_TV_LINES_PER_FRAME 625
+#define PAL_TV_ZERO_H_SIZE 473200
+#define PAL_TV_H_SIZE_UNIT 9360
+
+/* tv pll setting for 27 mhz ref clk */
+#define NTSC_TV_PLL_M_27 22
+#define NTSC_TV_PLL_N_27 175
+#define NTSC_TV_PLL_P_27 5
+
+#define PAL_TV_PLL_M_27 113
+#define PAL_TV_PLL_N_27 668
+#define PAL_TV_PLL_P_27 3
+
+/* tv pll setting for 14 mhz ref clk */
+#define NTSC_TV_PLL_M_14 33
+#define NTSC_TV_PLL_N_14 693
+#define NTSC_TV_PLL_P_14 7
+
+#define VERT_LEAD_IN_LINES 2
+#define FRAC_BITS 0xe
+#define FRAC_MASK 0x3fff
+
+struct radeon_tv_mode_constants {
+	uint16_t hor_resolution;
+	uint16_t ver_resolution;
+	enum radeon_tv_std standard;
+	uint16_t hor_total;
+	uint16_t ver_total;
+	uint16_t hor_start;
+	uint16_t hor_syncstart;
+	uint16_t ver_syncstart;
+	unsigned def_restart;
+	uint16_t crtcPLL_N;
+	uint8_t  crtcPLL_M;
+	uint8_t  crtcPLL_post_div;
+	unsigned pix_to_tv;
+};
+
+static const uint16_t hor_timing_NTSC[] = {
+	0x0007,
+	0x003f,
+	0x0263,
+	0x0a24,
+	0x2a6b,
+	0x0a36,
+	0x126d, /* H_TABLE_POS1 */
+	0x1bfe,
+	0x1a8f, /* H_TABLE_POS2 */
+	0x1ec7,
+	0x3863,
+	0x1bfe,
+	0x1bfe,
+	0x1a2a,
+	0x1e95,
+	0x0e31,
+	0x201b,
+	0
+};
+
+static const uint16_t vert_timing_NTSC[] = {
+	0x2001,
+	0x200d,
+	0x1006,
+	0x0c06,
+	0x1006,
+	0x1818,
+	0x21e3,
+	0x1006,
+	0x0c06,
+	0x1006,
+	0x1817,
+	0x21d4,
+	0x0002,
+	0
+};
+
+static const uint16_t hor_timing_PAL[] = {
+	0x0007,
+	0x0058,
+	0x027c,
+	0x0a31,
+	0x2a77,
+	0x0a95,
+	0x124f, /* H_TABLE_POS1 */
+	0x1bfe,
+	0x1b22, /* H_TABLE_POS2 */
+	0x1ef9,
+	0x387c,
+	0x1bfe,
+	0x1bfe,
+	0x1b31,
+	0x1eb5,
+	0x0e43,
+	0x201b,
+	0
+};
+
+static const uint16_t vert_timing_PAL[] = 	{
+	0x2001,
+	0x200c,
+	0x1005,
+	0x0c05,
+	0x1005,
+	0x1401,
+	0x1821,
+	0x2240,
+	0x1005,
+	0x0c05,
+	0x1005,
+	0x1401,
+	0x1822,
+	0x2230,
+	0x0002,
+	0
+};
+
+/**********************************************************************
+ *
+ * availableModes
+ *
+ * Table of all allowed modes for tv output
+ *
+ **********************************************************************/
+static const struct radeon_tv_mode_constants available_tv_modes[] = {
+	{   /* NTSC timing for 27 Mhz ref clk */
+		800,                /* horResolution */
+		600,                /* verResolution */
+		TV_STD_NTSC,        /* standard */
+		990,                /* horTotal */
+		740,                /* verTotal */
+		813,                /* horStart */
+		824,                /* horSyncStart */
+		632,                /* verSyncStart */
+		625592,             /* defRestart */
+		592,                /* crtcPLL_N */
+		91,                 /* crtcPLL_M */
+		4,                  /* crtcPLL_postDiv */
+		1022,               /* pixToTV */
+	},
+	{   /* PAL timing for 27 Mhz ref clk */
+		800,               /* horResolution */
+		600,               /* verResolution */
+		TV_STD_PAL,        /* standard */
+		1144,              /* horTotal */
+		706,               /* verTotal */
+		812,               /* horStart */
+		824,               /* horSyncStart */
+		669,               /* verSyncStart */
+		696700,            /* defRestart */
+		1382,              /* crtcPLL_N */
+		231,               /* crtcPLL_M */
+		4,                 /* crtcPLL_postDiv */
+		759,               /* pixToTV */
+	},
+	{   /* NTSC timing for 14 Mhz ref clk */
+		800,                /* horResolution */
+		600,                /* verResolution */
+		TV_STD_NTSC,        /* standard */
+		1018,               /* horTotal */
+		727,                /* verTotal */
+		813,                /* horStart */
+		840,                /* horSyncStart */
+		633,                /* verSyncStart */
+		630627,             /* defRestart */
+		347,                /* crtcPLL_N */
+		14,                 /* crtcPLL_M */
+			8,                  /* crtcPLL_postDiv */
+		1022,               /* pixToTV */
+	},
+};
+
+#define N_AVAILABLE_MODES ARRAY_SIZE(available_tv_modes)
+
+static const struct radeon_tv_mode_constants *radeon_legacy_tv_get_std_mode(struct radeon_encoder *radeon_encoder,
+									    uint16_t *pll_ref_freq)
+{
+	struct drm_device *dev = radeon_encoder->base.dev;
+	struct radeon_device *rdev = dev->dev_private;
+	struct radeon_crtc *radeon_crtc;
+	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
+	const struct radeon_tv_mode_constants *const_ptr;
+	struct radeon_pll *pll;
+
+	radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc);
+	if (radeon_crtc->crtc_id == 1)
+		pll = &rdev->clock.p2pll;
+	else
+		pll = &rdev->clock.p1pll;
+
+	if (pll_ref_freq)
+		*pll_ref_freq = pll->reference_freq;
+
+	if (tv_dac->tv_std == TV_STD_NTSC ||
+	    tv_dac->tv_std == TV_STD_NTSC_J ||
+	    tv_dac->tv_std == TV_STD_PAL_M) {
+		if (pll->reference_freq == 2700)
+			const_ptr = &available_tv_modes[0];
+		else
+			const_ptr = &available_tv_modes[2];
+	} else {
+		if (pll->reference_freq == 2700)
+			const_ptr = &available_tv_modes[1];
+		else
+			const_ptr = &available_tv_modes[1]; /* FIX ME */
+	}
+	return const_ptr;
+}
+
+static long YCOEF_value[5] = { 2, 2, 0, 4, 0 };
+static long YCOEF_EN_value[5] = { 1, 1, 0, 1, 0 };
+static long SLOPE_value[5] = { 1, 2, 2, 4, 8 };
+static long SLOPE_limit[5] = { 6, 5, 4, 3, 2 };
+
+static void radeon_wait_pll_lock(struct drm_encoder *encoder, unsigned n_tests,
+				 unsigned n_wait_loops, unsigned cnt_threshold)
+{
+	struct drm_device *dev = encoder->dev;
+	struct radeon_device *rdev = dev->dev_private;
+	uint32_t save_pll_test;
+	unsigned int i, j;
+
+	WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100);
+	save_pll_test = RREG32_PLL(RADEON_PLL_TEST_CNTL);
+	WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test & ~RADEON_PLL_MASK_READ_B);
+
+	WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL);
+	for (i = 0; i < n_tests; i++) {
+		WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0);
+		for (j = 0; j < n_wait_loops; j++)
+			if (RREG8(RADEON_CLOCK_CNTL_DATA + 3) >= cnt_threshold)
+				break;
+	}
+	WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test);
+	WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff);
+}
+
+
+static void radeon_legacy_tv_write_fifo(struct radeon_encoder *radeon_encoder,
+					uint16_t addr, uint32_t value)
+{
+	struct drm_device *dev = radeon_encoder->base.dev;
+	struct radeon_device *rdev = dev->dev_private;
+	uint32_t tmp;
+	int i = 0;
+
+	WREG32(RADEON_TV_HOST_WRITE_DATA, value);
+
+	WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr);
+	WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_WT);
+
+	do {
+		tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL);
+		if ((tmp & RADEON_HOST_FIFO_WT_ACK) == 0)
+			break;
+		i++;
+	} while (i < 10000);
+	WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0);
+}
+
+#if 0 /* included for completeness */
+static uint32_t radeon_legacy_tv_read_fifo(struct radeon_encoder *radeon_encoder, uint16_t addr)
+{
+	struct drm_device *dev = radeon_encoder->base.dev;
+	struct radeon_device *rdev = dev->dev_private;
+	uint32_t tmp;
+	int i = 0;
+
+	WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr);
+	WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_RD);
+
+	do {
+		tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL);
+		if ((tmp & RADEON_HOST_FIFO_RD_ACK) == 0)
+			break;
+		i++;
+	} while (i < 10000);
+	WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0);
+	return RREG32(RADEON_TV_HOST_READ_DATA);
+}
+#endif
+
+static uint16_t radeon_get_htiming_tables_addr(uint32_t tv_uv_adr)
+{
+	uint16_t h_table;
+
+	switch ((tv_uv_adr & RADEON_HCODE_TABLE_SEL_MASK) >> RADEON_HCODE_TABLE_SEL_SHIFT) {
+	case 0:
+		h_table = RADEON_TV_MAX_FIFO_ADDR_INTERNAL;
+		break;
+	case 1:
+		h_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2;
+		break;
+	case 2:
+		h_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2;
+		break;
+	default:
+		h_table = 0;
+		break;
+	}
+	return h_table;
+}
+
+static uint16_t radeon_get_vtiming_tables_addr(uint32_t tv_uv_adr)
+{
+	uint16_t v_table;
+
+	switch ((tv_uv_adr & RADEON_VCODE_TABLE_SEL_MASK) >> RADEON_VCODE_TABLE_SEL_SHIFT) {
+	case 0:
+		v_table = ((tv_uv_adr & RADEON_MAX_UV_ADR_MASK) >> RADEON_MAX_UV_ADR_SHIFT) * 2 + 1;
+		break;
+	case 1:
+		v_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2 + 1;
+		break;
+	case 2:
+		v_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2 + 1;
+		break;
+	default:
+		v_table = 0;
+		break;
+	}
+	return v_table;
+}
+
+static void radeon_restore_tv_timing_tables(struct radeon_encoder *radeon_encoder)
+{
+	struct drm_device *dev = radeon_encoder->base.dev;
+	struct radeon_device *rdev = dev->dev_private;
+	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
+	uint16_t h_table, v_table;
+	uint32_t tmp;
+	int i;
+
+	WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr);
+	h_table = radeon_get_htiming_tables_addr(tv_dac->tv.tv_uv_adr);
+	v_table = radeon_get_vtiming_tables_addr(tv_dac->tv.tv_uv_adr);
+
+	for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2, h_table--) {
+		tmp = ((uint32_t)tv_dac->tv.h_code_timing[i] << 14) | ((uint32_t)tv_dac->tv.h_code_timing[i+1]);
+		radeon_legacy_tv_write_fifo(radeon_encoder, h_table, tmp);
+		if (tv_dac->tv.h_code_timing[i] == 0 || tv_dac->tv.h_code_timing[i + 1] == 0)
+			break;
+	}
+	for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2, v_table++) {
+		tmp = ((uint32_t)tv_dac->tv.v_code_timing[i+1] << 14) | ((uint32_t)tv_dac->tv.v_code_timing[i]);
+		radeon_legacy_tv_write_fifo(radeon_encoder, v_table, tmp);
+		if (tv_dac->tv.v_code_timing[i] == 0 || tv_dac->tv.v_code_timing[i + 1] == 0)
+			break;
+	}
+}
+
+static void radeon_legacy_write_tv_restarts(struct radeon_encoder *radeon_encoder)
+{
+	struct drm_device *dev = radeon_encoder->base.dev;
+	struct radeon_device *rdev = dev->dev_private;
+	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
+	WREG32(RADEON_TV_FRESTART, tv_dac->tv.frestart);
+	WREG32(RADEON_TV_HRESTART, tv_dac->tv.hrestart);
+	WREG32(RADEON_TV_VRESTART, tv_dac->tv.vrestart);
+}
+
+static bool radeon_legacy_tv_init_restarts(struct drm_encoder *encoder)
+{
+	struct drm_device *dev = encoder->dev;
+	struct radeon_device *rdev = dev->dev_private;
+	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
+	struct radeon_crtc *radeon_crtc;
+	int restart;
+	unsigned int h_total, v_total, f_total;
+	int v_offset, h_offset;
+	u16 p1, p2, h_inc;
+	bool h_changed;
+	const struct radeon_tv_mode_constants *const_ptr;
+	struct radeon_pll *pll;
+
+	radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc);
+	if (radeon_crtc->crtc_id == 1)
+		pll = &rdev->clock.p2pll;
+	else
+		pll = &rdev->clock.p1pll;
+
+	const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
+	if (!const_ptr)
+		return false;
+
+	h_total = const_ptr->hor_total;
+	v_total = const_ptr->ver_total;
+
+	if (tv_dac->tv_std == TV_STD_NTSC ||
+	    tv_dac->tv_std == TV_STD_NTSC_J ||
+	    tv_dac->tv_std == TV_STD_PAL_M ||
+	    tv_dac->tv_std == TV_STD_PAL_60)
+		f_total = NTSC_TV_VFTOTAL + 1;
+	else
+		f_total = PAL_TV_VFTOTAL + 1;
+
+	/* adjust positions 1&2 in hor. cod timing table */
+	h_offset = tv_dac->h_pos * H_POS_UNIT;
+
+	if (tv_dac->tv_std == TV_STD_NTSC ||
+	    tv_dac->tv_std == TV_STD_NTSC_J ||
+	    tv_dac->tv_std == TV_STD_PAL_M) {
+		h_offset -= 50;
+		p1 = hor_timing_NTSC[H_TABLE_POS1];
+		p2 = hor_timing_NTSC[H_TABLE_POS2];
+	} else {
+		p1 = hor_timing_PAL[H_TABLE_POS1];
+		p2 = hor_timing_PAL[H_TABLE_POS2];
+	}
+
+	p1 = (u16)((int)p1 + h_offset);
+	p2 = (u16)((int)p2 - h_offset);
+
+	h_changed = (p1 != tv_dac->tv.h_code_timing[H_TABLE_POS1] ||
+		     p2 != tv_dac->tv.h_code_timing[H_TABLE_POS2]);
+
+	tv_dac->tv.h_code_timing[H_TABLE_POS1] = p1;
+	tv_dac->tv.h_code_timing[H_TABLE_POS2] = p2;
+
+	/* Convert hOffset from n. of TV clock periods to n. of CRTC clock periods (CRTC pixels) */
+	h_offset = (h_offset * (int)(const_ptr->pix_to_tv)) / 1000;
+
+	/* adjust restart */
+	restart = const_ptr->def_restart;
+
+	/*
+	 * convert v_pos TV lines to n. of CRTC pixels
+	 */
+	if (tv_dac->tv_std == TV_STD_NTSC ||
+	    tv_dac->tv_std == TV_STD_NTSC_J ||
+	    tv_dac->tv_std == TV_STD_PAL_M ||
+	    tv_dac->tv_std == TV_STD_PAL_60)
+		v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(NTSC_TV_LINES_PER_FRAME);
+	else
+		v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(PAL_TV_LINES_PER_FRAME);
+
+	restart -= v_offset + h_offset;
+
+	DRM_DEBUG("compute_restarts: def = %u h = %d v = %d, p1 = %04x, p2 = %04x, restart = %d\n",
+		  const_ptr->def_restart, tv_dac->h_pos, tv_dac->v_pos, p1, p2, restart);
+
+	tv_dac->tv.hrestart = restart % h_total;
+	restart /= h_total;
+	tv_dac->tv.vrestart = restart % v_total;
+	restart /= v_total;
+	tv_dac->tv.frestart = restart % f_total;
+
+	DRM_DEBUG("compute_restart: F/H/V=%u,%u,%u\n",
+		  (unsigned)tv_dac->tv.frestart,
+		  (unsigned)tv_dac->tv.vrestart,
+		  (unsigned)tv_dac->tv.hrestart);
+
+	/* compute h_inc from hsize */
+	if (tv_dac->tv_std == TV_STD_NTSC ||
+	    tv_dac->tv_std == TV_STD_NTSC_J ||
+	    tv_dac->tv_std == TV_STD_PAL_M)
+		h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * NTSC_TV_CLOCK_T) /
+			      (tv_dac->h_size * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE)));
+	else
+		h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * PAL_TV_CLOCK_T) /
+			      (tv_dac->h_size * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE)));
+
+	tv_dac->tv.timing_cntl = (tv_dac->tv.timing_cntl & ~RADEON_H_INC_MASK) |
+		((u32)h_inc << RADEON_H_INC_SHIFT);
+
+	DRM_DEBUG("compute_restart: h_size = %d h_inc = %d\n", tv_dac->h_size, h_inc);
+
+	return h_changed;
+}
+
+void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
+			       struct drm_display_mode *mode,
+			       struct drm_display_mode *adjusted_mode)
+{
+	struct drm_device *dev = encoder->dev;
+	struct radeon_device *rdev = dev->dev_private;
+	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
+	const struct radeon_tv_mode_constants *const_ptr;
+	struct radeon_crtc *radeon_crtc;
+	int i;
+	uint16_t pll_ref_freq;
+	uint32_t vert_space, flicker_removal, tmp;
+	uint32_t tv_master_cntl, tv_rgb_cntl, tv_dac_cntl;
+	uint32_t tv_modulator_cntl1, tv_modulator_cntl2;
+	uint32_t tv_vscaler_cntl1, tv_vscaler_cntl2;
+	uint32_t tv_pll_cntl, tv_pll_cntl1, tv_ftotal;
+	uint32_t tv_y_fall_cntl, tv_y_rise_cntl, tv_y_saw_tooth_cntl;
+	uint32_t m, n, p;
+	const uint16_t *hor_timing;
+	const uint16_t *vert_timing;
+
+	const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, &pll_ref_freq);
+	if (!const_ptr)
+		return;
+
+	radeon_crtc = to_radeon_crtc(encoder->crtc);
+
+	tv_master_cntl = (RADEON_VIN_ASYNC_RST |
+			  RADEON_CRT_FIFO_CE_EN |
+			  RADEON_TV_FIFO_CE_EN |
+			  RADEON_TV_ON);
+
+	if (!ASIC_IS_R300(rdev))
+		tv_master_cntl |= RADEON_TVCLK_ALWAYS_ONb;
+
+	if (tv_dac->tv_std == TV_STD_NTSC ||
+	    tv_dac->tv_std == TV_STD_NTSC_J)
+		tv_master_cntl |= RADEON_RESTART_PHASE_FIX;
+
+	tv_modulator_cntl1 = (RADEON_SLEW_RATE_LIMIT |
+			      RADEON_SYNC_TIP_LEVEL |
+			      RADEON_YFLT_EN |
+			      RADEON_UVFLT_EN |
+			      (6 << RADEON_CY_FILT_BLEND_SHIFT));
+
+	if (tv_dac->tv_std == TV_STD_NTSC ||
+	    tv_dac->tv_std == TV_STD_NTSC_J) {
+		tv_modulator_cntl1 |= (0x46 << RADEON_SET_UP_LEVEL_SHIFT) |
+			(0x3b << RADEON_BLANK_LEVEL_SHIFT);
+		tv_modulator_cntl2 = (-111 & RADEON_TV_U_BURST_LEVEL_MASK) |
+			((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
+	} else if (tv_dac->tv_std == TV_STD_SCART_PAL) {
+		tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN;
+		tv_modulator_cntl2 = (0 & RADEON_TV_U_BURST_LEVEL_MASK) |
+			((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
+	} else {
+		tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN |
+			(0x3b << RADEON_SET_UP_LEVEL_SHIFT) |
+			(0x3b << RADEON_BLANK_LEVEL_SHIFT);
+		tv_modulator_cntl2 = (-78 & RADEON_TV_U_BURST_LEVEL_MASK) |
+			((62 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
+	}
+
+
+	tv_rgb_cntl = (RADEON_RGB_DITHER_EN
+		       | RADEON_TVOUT_SCALE_EN
+		       | (0x0b << RADEON_UVRAM_READ_MARGIN_SHIFT)
+		       | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT)
+		       | RADEON_RGB_ATTEN_SEL(0x3)
+		       | RADEON_RGB_ATTEN_VAL(0xc));
+
+	if (radeon_crtc->crtc_id == 1)
+		tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC2;
+	else {
+		if (radeon_crtc->rmx_type != RMX_OFF)
+			tv_rgb_cntl |= RADEON_RGB_SRC_SEL_RMX;
+		else
+			tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC1;
+	}
+
+	if (tv_dac->tv_std == TV_STD_NTSC ||
+	    tv_dac->tv_std == TV_STD_NTSC_J ||
+	    tv_dac->tv_std == TV_STD_PAL_M ||
+	    tv_dac->tv_std == TV_STD_PAL_60)
+		vert_space = const_ptr->ver_total * 2 * 10000 / NTSC_TV_LINES_PER_FRAME;
+	else
+		vert_space = const_ptr->ver_total * 2 * 10000 / PAL_TV_LINES_PER_FRAME;
+
+	tmp = RREG32(RADEON_TV_VSCALER_CNTL1);
+	tmp &= 0xe3ff0000;
+	tmp |= (vert_space * (1 << FRAC_BITS) / 10000);
+	tv_vscaler_cntl1 = tmp;
+
+	if (pll_ref_freq == 2700)
+		tv_vscaler_cntl1 |= RADEON_RESTART_FIELD;
+
+	if (const_ptr->hor_resolution == 1024)
+		tv_vscaler_cntl1 |= (4 << RADEON_Y_DEL_W_SIG_SHIFT);
+	else
+		tv_vscaler_cntl1 |= (2 << RADEON_Y_DEL_W_SIG_SHIFT);
+
+	/* scale up for int divide */
+	tmp = const_ptr->ver_total * 2 * 1000;
+	if (tv_dac->tv_std == TV_STD_NTSC ||
+	    tv_dac->tv_std == TV_STD_NTSC_J ||
+	    tv_dac->tv_std == TV_STD_PAL_M ||
+	    tv_dac->tv_std == TV_STD_PAL_60) {
+		tmp /= NTSC_TV_LINES_PER_FRAME;
+	} else {
+		tmp /= PAL_TV_LINES_PER_FRAME;
+	}
+	flicker_removal = (tmp + 500) / 1000;
+
+	if (flicker_removal < 3)
+		flicker_removal = 3;
+	for (i = 0; i < 6; ++i) {
+		if (flicker_removal == SLOPE_limit[i])
+			break;
+	}
+
+	tv_y_saw_tooth_cntl = (vert_space * SLOPE_value[i] * (1 << (FRAC_BITS - 1)) +
+				5001) / 10000 / 8 | ((SLOPE_value[i] *
+				(1 << (FRAC_BITS - 1)) / 8) << 16);
+	tv_y_fall_cntl =
+		(YCOEF_EN_value[i] << 17) | ((YCOEF_value[i] * (1 << 8) / 8) << 24) |
+		RADEON_Y_FALL_PING_PONG | (272 * SLOPE_value[i] / 8) * (1 << (FRAC_BITS - 1)) /
+		1024;
+	tv_y_rise_cntl = RADEON_Y_RISE_PING_PONG|
+		(flicker_removal * 1024 - 272) * SLOPE_value[i] / 8 * (1 << (FRAC_BITS - 1)) / 1024;
+
+	tv_vscaler_cntl2 = RREG32(RADEON_TV_VSCALER_CNTL2) & 0x00fffff0;
+	tv_vscaler_cntl2 |= (0x10 << 24) |
+		RADEON_DITHER_MODE |
+		RADEON_Y_OUTPUT_DITHER_EN |
+		RADEON_UV_OUTPUT_DITHER_EN |
+		RADEON_UV_TO_BUF_DITHER_EN;
+
+	tmp = (tv_vscaler_cntl1 >> RADEON_UV_INC_SHIFT) & RADEON_UV_INC_MASK;
+	tmp = ((16384 * 256 * 10) / tmp + 5) / 10;
+	tmp = (tmp << RADEON_UV_OUTPUT_POST_SCALE_SHIFT) | 0x000b0000;
+	tv_dac->tv.timing_cntl = tmp;
+
+	if (tv_dac->tv_std == TV_STD_NTSC ||
+	    tv_dac->tv_std == TV_STD_NTSC_J ||
+	    tv_dac->tv_std == TV_STD_PAL_M ||
+	    tv_dac->tv_std == TV_STD_PAL_60)
+		tv_dac_cntl = tv_dac->ntsc_tvdac_adj;
+	else
+		tv_dac_cntl = tv_dac->pal_tvdac_adj;
+
+	tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
+
+	if (tv_dac->tv_std == TV_STD_NTSC ||
+	    tv_dac->tv_std == TV_STD_NTSC_J)
+		tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
+	else
+		tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
+
+	if (tv_dac->tv_std == TV_STD_NTSC ||
+	    tv_dac->tv_std == TV_STD_NTSC_J) {
+		if (pll_ref_freq == 2700) {
+			m = NTSC_TV_PLL_M_27;
+			n = NTSC_TV_PLL_N_27;
+			p = NTSC_TV_PLL_P_27;
+		} else {
+			m = NTSC_TV_PLL_M_14;
+			n = NTSC_TV_PLL_N_14;
+			p = NTSC_TV_PLL_P_14;
+		}
+	} else {
+		if (pll_ref_freq == 2700) {
+			m = PAL_TV_PLL_M_27;
+			n = PAL_TV_PLL_N_27;
+			p = PAL_TV_PLL_P_27;
+		} else {
+			m = PAL_TV_PLL_M_27;
+			n = PAL_TV_PLL_N_27;
+			p = PAL_TV_PLL_P_27;
+		}
+	}
+
+	tv_pll_cntl = (m & RADEON_TV_M0LO_MASK) |
+		(((m >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) |
+		((n & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) |
+		(((n >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) |
+		((p & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT);
+
+	tv_pll_cntl1 = (((4 & RADEON_TVPCP_MASK) << RADEON_TVPCP_SHIFT) |
+			((4 & RADEON_TVPVG_MASK) << RADEON_TVPVG_SHIFT) |
+			((1 & RADEON_TVPDC_MASK) << RADEON_TVPDC_SHIFT) |
+			RADEON_TVCLK_SRC_SEL_TVPLL |
+			RADEON_TVPLL_TEST_DIS);
+
+	tv_dac->tv.tv_uv_adr = 0xc8;
+
+	if (tv_dac->tv_std == TV_STD_NTSC ||
+	    tv_dac->tv_std == TV_STD_NTSC_J ||
+	    tv_dac->tv_std == TV_STD_PAL_M ||
+	    tv_dac->tv_std == TV_STD_PAL_60) {
+		tv_ftotal = NTSC_TV_VFTOTAL;
+		hor_timing = hor_timing_NTSC;
+		vert_timing = vert_timing_NTSC;
+	} else {
+		hor_timing = hor_timing_PAL;
+		vert_timing = vert_timing_PAL;
+		tv_ftotal = PAL_TV_VFTOTAL;
+	}
+
+	for (i = 0; i < MAX_H_CODE_TIMING_LEN; i++) {
+		if ((tv_dac->tv.h_code_timing[i] = hor_timing[i]) == 0)
+			break;
+	}
+
+	for (i = 0; i < MAX_V_CODE_TIMING_LEN; i++) {
+		if ((tv_dac->tv.v_code_timing[i] = vert_timing[i]) == 0)
+			break;
+	}
+
+	radeon_legacy_tv_init_restarts(encoder);
+
+	/* play with DAC_CNTL */
+	/* play with GPIOPAD_A */
+	/* DISP_OUTPUT_CNTL */
+	/* use reference freq */
+
+	/* program the TV registers */
+	WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST |
+				       RADEON_CRT_ASYNC_RST | RADEON_TV_FIFO_ASYNC_RST));
+
+	tmp = RREG32(RADEON_TV_DAC_CNTL);
+	tmp &= ~RADEON_TV_DAC_NBLANK;
+	tmp |= RADEON_TV_DAC_BGSLEEP |
+		RADEON_TV_DAC_RDACPD |
+		RADEON_TV_DAC_GDACPD |
+		RADEON_TV_DAC_BDACPD;
+	WREG32(RADEON_TV_DAC_CNTL, tmp);
+
+	/* TV PLL */
+	WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL);
+	WREG32_PLL(RADEON_TV_PLL_CNTL, tv_pll_cntl);
+	WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVPLL_RESET, ~RADEON_TVPLL_RESET);
+
+	radeon_wait_pll_lock(encoder, 200, 800, 135);
+
+	WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET);
+
+	radeon_wait_pll_lock(encoder, 300, 160, 27);
+	radeon_wait_pll_lock(encoder, 200, 800, 135);
+
+	WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~0xf);
+	WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVCLK_SRC_SEL_TVPLL, ~RADEON_TVCLK_SRC_SEL_TVPLL);
+
+	WREG32_PLL_P(RADEON_TV_PLL_CNTL1, (1 << RADEON_TVPDC_SHIFT), ~RADEON_TVPDC_MASK);
+	WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP);
+
+	/* TV HV */
+	WREG32(RADEON_TV_RGB_CNTL, tv_rgb_cntl);
+	WREG32(RADEON_TV_HTOTAL, const_ptr->hor_total - 1);
+	WREG32(RADEON_TV_HDISP, const_ptr->hor_resolution - 1);
+	WREG32(RADEON_TV_HSTART, const_ptr->hor_start);
+
+	WREG32(RADEON_TV_VTOTAL, const_ptr->ver_total - 1);
+	WREG32(RADEON_TV_VDISP, const_ptr->ver_resolution - 1);
+	WREG32(RADEON_TV_FTOTAL, tv_ftotal);
+	WREG32(RADEON_TV_VSCALER_CNTL1, tv_vscaler_cntl1);
+	WREG32(RADEON_TV_VSCALER_CNTL2, tv_vscaler_cntl2);
+
+	WREG32(RADEON_TV_Y_FALL_CNTL, tv_y_fall_cntl);
+	WREG32(RADEON_TV_Y_RISE_CNTL, tv_y_rise_cntl);
+	WREG32(RADEON_TV_Y_SAW_TOOTH_CNTL, tv_y_saw_tooth_cntl);
+
+	WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST |
+				       RADEON_CRT_ASYNC_RST));
+
+	/* TV restarts */
+	radeon_legacy_write_tv_restarts(radeon_encoder);
+
+	/* tv timings */
+	radeon_restore_tv_timing_tables(radeon_encoder);
+
+	WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST));
+
+	/* tv std */
+	WREG32(RADEON_TV_SYNC_CNTL, (RADEON_SYNC_PUB | RADEON_TV_SYNC_IO_DRIVE));
+	WREG32(RADEON_TV_TIMING_CNTL, tv_dac->tv.timing_cntl);
+	WREG32(RADEON_TV_MODULATOR_CNTL1, tv_modulator_cntl1);
+	WREG32(RADEON_TV_MODULATOR_CNTL2, tv_modulator_cntl2);
+	WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, (RADEON_Y_RED_EN |
+					    RADEON_C_GRN_EN |
+					    RADEON_CMP_BLU_EN |
+					    RADEON_DAC_DITHER_EN));
+
+	WREG32(RADEON_TV_CRC_CNTL, 0);
+
+	WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
+
+	WREG32(RADEON_TV_GAIN_LIMIT_SETTINGS, ((0x17f << RADEON_UV_GAIN_LIMIT_SHIFT) |
+					       (0x5ff << RADEON_Y_GAIN_LIMIT_SHIFT)));
+	WREG32(RADEON_TV_LINEAR_GAIN_SETTINGS, ((0x100 << RADEON_UV_GAIN_SHIFT) |
+						(0x100 << RADEON_Y_GAIN_SHIFT)));
+
+	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
+
+}
+
+void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
+				      uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
+				      uint32_t *v_total_disp, uint32_t *v_sync_strt_wid)
+{
+	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+	const struct radeon_tv_mode_constants *const_ptr;
+	uint32_t tmp;
+
+	const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
+	if (!const_ptr)
+		return;
+
+	*h_total_disp = (((const_ptr->hor_resolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) |
+		(((const_ptr->hor_total / 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT);
+
+	tmp = *h_sync_strt_wid;
+	tmp &= ~(RADEON_CRTC_H_SYNC_STRT_PIX | RADEON_CRTC_H_SYNC_STRT_CHAR);
+	tmp |= (((const_ptr->hor_syncstart / 8) - 1) << RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT) |
+		(const_ptr->hor_syncstart & 7);
+	*h_sync_strt_wid = tmp;
+
+	*v_total_disp = ((const_ptr->ver_resolution - 1) << RADEON_CRTC_V_DISP_SHIFT) |
+		((const_ptr->ver_total - 1) << RADEON_CRTC_V_TOTAL_SHIFT);
+
+	tmp = *v_sync_strt_wid;
+	tmp &= ~RADEON_CRTC_V_SYNC_STRT;
+	tmp |= ((const_ptr->ver_syncstart - 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT);
+	*v_sync_strt_wid = tmp;
+}
+
+static inline int get_post_div(int value)
+{
+	int post_div;
+	switch (value) {
+	case 1: post_div = 0; break;
+	case 2: post_div = 1; break;
+	case 3: post_div = 4; break;
+	case 4: post_div = 2; break;
+	case 6: post_div = 6; break;
+	case 8: post_div = 3; break;
+	case 12: post_div = 7; break;
+	case 16:
+	default: post_div = 5; break;
+	}
+	return post_div;
+}
+
+void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
+				  uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
+				  uint32_t *ppll_div_3, uint32_t *pixclks_cntl)
+{
+	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+	const struct radeon_tv_mode_constants *const_ptr;
+
+	const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
+	if (!const_ptr)
+		return;
+
+	*htotal_cntl = (const_ptr->hor_total & 0x7) | RADEON_HTOT_CNTL_VGA_EN;
+
+	*ppll_ref_div = const_ptr->crtcPLL_M;
+
+	*ppll_div_3 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16);
+	*pixclks_cntl &= ~(RADEON_PIX2CLK_SRC_SEL_MASK | RADEON_PIXCLK_TV_SRC_SEL);
+	*pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK;
+}
+
+void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
+				  uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
+				  uint32_t *p2pll_div_0, uint32_t *pixclks_cntl)
+{
+	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+	const struct radeon_tv_mode_constants *const_ptr;
+
+	const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
+	if (!const_ptr)
+		return;
+
+	*htotal2_cntl = (const_ptr->hor_total & 0x7);
+
+	*p2pll_ref_div = const_ptr->crtcPLL_M;
+
+	*p2pll_div_0 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16);
+	*pixclks_cntl &= ~RADEON_PIX2CLK_SRC_SEL_MASK;
+	*pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK | RADEON_PIXCLK_TV_SRC_SEL;
+}
+
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 20e9509a713..523d6cbd4f0 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -188,6 +188,21 @@ struct radeon_native_mode {
 	uint32_t flags;
 };
 
+#define MAX_H_CODE_TIMING_LEN 32
+#define MAX_V_CODE_TIMING_LEN 32
+
+/* need to store these as reading
+   back code tables is excessive */
+struct radeon_tv_regs {
+	uint32_t tv_uv_adr;
+	uint32_t timing_cntl;
+	uint32_t hrestart;
+	uint32_t vrestart;
+	uint32_t frestart;
+	uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
+	uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
+};
+
 struct radeon_crtc {
 	struct drm_crtc base;
 	int crtc_id;
@@ -202,7 +217,6 @@ struct radeon_crtc {
 	uint32_t legacy_display_base_addr;
 	uint32_t legacy_cursor_offset;
 	enum radeon_rmx_type rmx_type;
-	uint32_t devices;
 	fixed20_12 vsc;
 	fixed20_12 hsc;
 	struct radeon_native_mode native_mode;
@@ -234,7 +248,13 @@ struct radeon_encoder_tv_dac {
 	uint32_t ntsc_tvdac_adj;
 	uint32_t pal_tvdac_adj;
 
+	int               h_pos;
+	int               v_pos;
+	int               h_size;
+	int               supported_tv_stds;
+	bool              tv_on;
 	enum radeon_tv_std tv_std;
+	struct radeon_tv_regs tv;
 };
 
 struct radeon_encoder_int_tmds {
@@ -253,10 +273,15 @@ struct radeon_encoder_atom_dig {
 	struct radeon_native_mode native_mode;
 };
 
+struct radeon_encoder_atom_dac {
+	enum radeon_tv_std tv_std;
+};
+
 struct radeon_encoder {
 	struct drm_encoder base;
 	uint32_t encoder_id;
 	uint32_t devices;
+	uint32_t active_device;
 	uint32_t flags;
 	uint32_t pixel_clock;
 	enum radeon_rmx_type rmx_type;
@@ -274,7 +299,10 @@ struct radeon_connector {
 	uint32_t connector_id;
 	uint32_t devices;
 	struct radeon_i2c_chan *ddc_bus;
-	int use_digital;
+	bool use_digital;
+	/* we need to mind the EDID between detect
+	   and get modes due to analog/digital/tvencoder */
+	struct edid *edid;
 	void *con_priv;
 };
 
@@ -308,6 +336,7 @@ struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, i
 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
 extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
 extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
+extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
 
 extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
@@ -394,6 +423,19 @@ extern int radeon_static_clocks_init(struct drm_device *dev);
 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
 					struct drm_display_mode *mode,
 					struct drm_display_mode *adjusted_mode);
-void atom_rv515_force_tv_scaler(struct radeon_device *rdev);
-
+void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
+
+/* legacy tv */
+void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
+				      uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
+				      uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
+void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
+				  uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
+				  uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
+void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
+				  uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
+				  uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
+void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
+			       struct drm_display_mode *mode,
+			       struct drm_display_mode *adjusted_mode);
 #endif
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
index 404b39bf343..28be2f1165c 100644
--- a/drivers/gpu/drm/radeon/radeon_reg.h
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -3462,7 +3462,9 @@
 #       define RADEON_RGB_CONVERT_BY_PASS	  (1 << 10)
 #       define RADEON_UVRAM_READ_MARGIN_SHIFT	  16
 #       define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT	  20
-#	define RADEON_TVOUT_SCALE_EN		  (1 << 26)
+#       define RADEON_RGB_ATTEN_SEL(x)            ((x) << 24)
+#       define RADEON_TVOUT_SCALE_EN              (1 << 26)
+#       define RADEON_RGB_ATTEN_VAL(x)            ((x) << 28)
 #define RADEON_TV_SYNC_CNTL                          0x0808
 #       define RADEON_SYNC_OE                     (1 <<  0)
 #       define RADEON_SYNC_OUT                    (1 <<  1)
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 60a194f1d9a..97965c430c1 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -475,232 +475,234 @@ int rv515_init(struct radeon_device *rdev)
 	return 0;
 }
 
-void atom_rv515_force_tv_scaler(struct radeon_device *rdev)
+void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
 {
-
-	WREG32(0x659C, 0x0);
-	WREG32(0x6594, 0x705);
-	WREG32(0x65A4, 0x10001);
-	WREG32(0x65D8, 0x0);
-	WREG32(0x65B0, 0x0);
-	WREG32(0x65C0, 0x0);
-	WREG32(0x65D4, 0x0);
-	WREG32(0x6578, 0x0);
-	WREG32(0x657C, 0x841880A8);
-	WREG32(0x6578, 0x1);
-	WREG32(0x657C, 0x84208680);
-	WREG32(0x6578, 0x2);
-	WREG32(0x657C, 0xBFF880B0);
-	WREG32(0x6578, 0x100);
-	WREG32(0x657C, 0x83D88088);
-	WREG32(0x6578, 0x101);
-	WREG32(0x657C, 0x84608680);
-	WREG32(0x6578, 0x102);
-	WREG32(0x657C, 0xBFF080D0);
-	WREG32(0x6578, 0x200);
-	WREG32(0x657C, 0x83988068);
-	WREG32(0x6578, 0x201);
-	WREG32(0x657C, 0x84A08680);
-	WREG32(0x6578, 0x202);
-	WREG32(0x657C, 0xBFF080F8);
-	WREG32(0x6578, 0x300);
-	WREG32(0x657C, 0x83588058);
-	WREG32(0x6578, 0x301);
-	WREG32(0x657C, 0x84E08660);
-	WREG32(0x6578, 0x302);
-	WREG32(0x657C, 0xBFF88120);
-	WREG32(0x6578, 0x400);
-	WREG32(0x657C, 0x83188040);
-	WREG32(0x6578, 0x401);
-	WREG32(0x657C, 0x85008660);
-	WREG32(0x6578, 0x402);
-	WREG32(0x657C, 0xBFF88150);
-	WREG32(0x6578, 0x500);
-	WREG32(0x657C, 0x82D88030);
-	WREG32(0x6578, 0x501);
-	WREG32(0x657C, 0x85408640);
-	WREG32(0x6578, 0x502);
-	WREG32(0x657C, 0xBFF88180);
-	WREG32(0x6578, 0x600);
-	WREG32(0x657C, 0x82A08018);
-	WREG32(0x6578, 0x601);
-	WREG32(0x657C, 0x85808620);
-	WREG32(0x6578, 0x602);
-	WREG32(0x657C, 0xBFF081B8);
-	WREG32(0x6578, 0x700);
-	WREG32(0x657C, 0x82608010);
-	WREG32(0x6578, 0x701);
-	WREG32(0x657C, 0x85A08600);
-	WREG32(0x6578, 0x702);
-	WREG32(0x657C, 0x800081F0);
-	WREG32(0x6578, 0x800);
-	WREG32(0x657C, 0x8228BFF8);
-	WREG32(0x6578, 0x801);
-	WREG32(0x657C, 0x85E085E0);
-	WREG32(0x6578, 0x802);
-	WREG32(0x657C, 0xBFF88228);
-	WREG32(0x6578, 0x10000);
-	WREG32(0x657C, 0x82A8BF00);
-	WREG32(0x6578, 0x10001);
-	WREG32(0x657C, 0x82A08CC0);
-	WREG32(0x6578, 0x10002);
-	WREG32(0x657C, 0x8008BEF8);
-	WREG32(0x6578, 0x10100);
-	WREG32(0x657C, 0x81F0BF28);
-	WREG32(0x6578, 0x10101);
-	WREG32(0x657C, 0x83608CA0);
-	WREG32(0x6578, 0x10102);
-	WREG32(0x657C, 0x8018BED0);
-	WREG32(0x6578, 0x10200);
-	WREG32(0x657C, 0x8148BF38);
-	WREG32(0x6578, 0x10201);
-	WREG32(0x657C, 0x84408C80);
-	WREG32(0x6578, 0x10202);
-	WREG32(0x657C, 0x8008BEB8);
-	WREG32(0x6578, 0x10300);
-	WREG32(0x657C, 0x80B0BF78);
-	WREG32(0x6578, 0x10301);
-	WREG32(0x657C, 0x85008C20);
-	WREG32(0x6578, 0x10302);
-	WREG32(0x657C, 0x8020BEA0);
-	WREG32(0x6578, 0x10400);
-	WREG32(0x657C, 0x8028BF90);
-	WREG32(0x6578, 0x10401);
-	WREG32(0x657C, 0x85E08BC0);
-	WREG32(0x6578, 0x10402);
-	WREG32(0x657C, 0x8018BE90);
-	WREG32(0x6578, 0x10500);
-	WREG32(0x657C, 0xBFB8BFB0);
-	WREG32(0x6578, 0x10501);
-	WREG32(0x657C, 0x86C08B40);
-	WREG32(0x6578, 0x10502);
-	WREG32(0x657C, 0x8010BE90);
-	WREG32(0x6578, 0x10600);
-	WREG32(0x657C, 0xBF58BFC8);
-	WREG32(0x6578, 0x10601);
-	WREG32(0x657C, 0x87A08AA0);
-	WREG32(0x6578, 0x10602);
-	WREG32(0x657C, 0x8010BE98);
-	WREG32(0x6578, 0x10700);
-	WREG32(0x657C, 0xBF10BFF0);
-	WREG32(0x6578, 0x10701);
-	WREG32(0x657C, 0x886089E0);
-	WREG32(0x6578, 0x10702);
-	WREG32(0x657C, 0x8018BEB0);
-	WREG32(0x6578, 0x10800);
-	WREG32(0x657C, 0xBED8BFE8);
-	WREG32(0x6578, 0x10801);
-	WREG32(0x657C, 0x89408940);
-	WREG32(0x6578, 0x10802);
-	WREG32(0x657C, 0xBFE8BED8);
-	WREG32(0x6578, 0x20000);
-	WREG32(0x657C, 0x80008000);
-	WREG32(0x6578, 0x20001);
-	WREG32(0x657C, 0x90008000);
-	WREG32(0x6578, 0x20002);
-	WREG32(0x657C, 0x80008000);
-	WREG32(0x6578, 0x20003);
-	WREG32(0x657C, 0x80008000);
-	WREG32(0x6578, 0x20100);
-	WREG32(0x657C, 0x80108000);
-	WREG32(0x6578, 0x20101);
-	WREG32(0x657C, 0x8FE0BF70);
-	WREG32(0x6578, 0x20102);
-	WREG32(0x657C, 0xBFE880C0);
-	WREG32(0x6578, 0x20103);
-	WREG32(0x657C, 0x80008000);
-	WREG32(0x6578, 0x20200);
-	WREG32(0x657C, 0x8018BFF8);
-	WREG32(0x6578, 0x20201);
-	WREG32(0x657C, 0x8F80BF08);
-	WREG32(0x6578, 0x20202);
-	WREG32(0x657C, 0xBFD081A0);
-	WREG32(0x6578, 0x20203);
-	WREG32(0x657C, 0xBFF88000);
-	WREG32(0x6578, 0x20300);
-	WREG32(0x657C, 0x80188000);
-	WREG32(0x6578, 0x20301);
-	WREG32(0x657C, 0x8EE0BEC0);
-	WREG32(0x6578, 0x20302);
-	WREG32(0x657C, 0xBFB082A0);
-	WREG32(0x6578, 0x20303);
-	WREG32(0x657C, 0x80008000);
-	WREG32(0x6578, 0x20400);
-	WREG32(0x657C, 0x80188000);
-	WREG32(0x6578, 0x20401);
-	WREG32(0x657C, 0x8E00BEA0);
-	WREG32(0x6578, 0x20402);
-	WREG32(0x657C, 0xBF8883C0);
-	WREG32(0x6578, 0x20403);
-	WREG32(0x657C, 0x80008000);
-	WREG32(0x6578, 0x20500);
-	WREG32(0x657C, 0x80188000);
-	WREG32(0x6578, 0x20501);
-	WREG32(0x657C, 0x8D00BE90);
-	WREG32(0x6578, 0x20502);
-	WREG32(0x657C, 0xBF588500);
-	WREG32(0x6578, 0x20503);
-	WREG32(0x657C, 0x80008008);
-	WREG32(0x6578, 0x20600);
-	WREG32(0x657C, 0x80188000);
-	WREG32(0x6578, 0x20601);
-	WREG32(0x657C, 0x8BC0BE98);
-	WREG32(0x6578, 0x20602);
-	WREG32(0x657C, 0xBF308660);
-	WREG32(0x6578, 0x20603);
-	WREG32(0x657C, 0x80008008);
-	WREG32(0x6578, 0x20700);
-	WREG32(0x657C, 0x80108000);
-	WREG32(0x6578, 0x20701);
-	WREG32(0x657C, 0x8A80BEB0);
-	WREG32(0x6578, 0x20702);
-	WREG32(0x657C, 0xBF0087C0);
-	WREG32(0x6578, 0x20703);
-	WREG32(0x657C, 0x80008008);
-	WREG32(0x6578, 0x20800);
-	WREG32(0x657C, 0x80108000);
-	WREG32(0x6578, 0x20801);
-	WREG32(0x657C, 0x8920BED0);
-	WREG32(0x6578, 0x20802);
-	WREG32(0x657C, 0xBED08920);
-	WREG32(0x6578, 0x20803);
-	WREG32(0x657C, 0x80008010);
-	WREG32(0x6578, 0x30000);
-	WREG32(0x657C, 0x90008000);
-	WREG32(0x6578, 0x30001);
-	WREG32(0x657C, 0x80008000);
-	WREG32(0x6578, 0x30100);
-	WREG32(0x657C, 0x8FE0BF90);
-	WREG32(0x6578, 0x30101);
-	WREG32(0x657C, 0xBFF880A0);
-	WREG32(0x6578, 0x30200);
-	WREG32(0x657C, 0x8F60BF40);
-	WREG32(0x6578, 0x30201);
-	WREG32(0x657C, 0xBFE88180);
-	WREG32(0x6578, 0x30300);
-	WREG32(0x657C, 0x8EC0BF00);
-	WREG32(0x6578, 0x30301);
-	WREG32(0x657C, 0xBFC88280);
-	WREG32(0x6578, 0x30400);
-	WREG32(0x657C, 0x8DE0BEE0);
-	WREG32(0x6578, 0x30401);
-	WREG32(0x657C, 0xBFA083A0);
-	WREG32(0x6578, 0x30500);
-	WREG32(0x657C, 0x8CE0BED0);
-	WREG32(0x6578, 0x30501);
-	WREG32(0x657C, 0xBF7884E0);
-	WREG32(0x6578, 0x30600);
-	WREG32(0x657C, 0x8BA0BED8);
-	WREG32(0x6578, 0x30601);
-	WREG32(0x657C, 0xBF508640);
-	WREG32(0x6578, 0x30700);
-	WREG32(0x657C, 0x8A60BEE8);
-	WREG32(0x6578, 0x30701);
-	WREG32(0x657C, 0xBF2087A0);
-	WREG32(0x6578, 0x30800);
-	WREG32(0x657C, 0x8900BF00);
-	WREG32(0x6578, 0x30801);
-	WREG32(0x657C, 0xBF008900);
+	int index_reg = 0x6578 + crtc->crtc_offset;
+	int data_reg = 0x657c + crtc->crtc_offset;
+
+	WREG32(0x659C + crtc->crtc_offset, 0x0);
+	WREG32(0x6594 + crtc->crtc_offset, 0x705);
+	WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
+	WREG32(0x65D8 + crtc->crtc_offset, 0x0);
+	WREG32(0x65B0 + crtc->crtc_offset, 0x0);
+	WREG32(0x65C0 + crtc->crtc_offset, 0x0);
+	WREG32(0x65D4 + crtc->crtc_offset, 0x0);
+	WREG32(index_reg, 0x0);
+	WREG32(data_reg, 0x841880A8);
+	WREG32(index_reg, 0x1);
+	WREG32(data_reg, 0x84208680);
+	WREG32(index_reg, 0x2);
+	WREG32(data_reg, 0xBFF880B0);
+	WREG32(index_reg, 0x100);
+	WREG32(data_reg, 0x83D88088);
+	WREG32(index_reg, 0x101);
+	WREG32(data_reg, 0x84608680);
+	WREG32(index_reg, 0x102);
+	WREG32(data_reg, 0xBFF080D0);
+	WREG32(index_reg, 0x200);
+	WREG32(data_reg, 0x83988068);
+	WREG32(index_reg, 0x201);
+	WREG32(data_reg, 0x84A08680);
+	WREG32(index_reg, 0x202);
+	WREG32(data_reg, 0xBFF080F8);
+	WREG32(index_reg, 0x300);
+	WREG32(data_reg, 0x83588058);
+	WREG32(index_reg, 0x301);
+	WREG32(data_reg, 0x84E08660);
+	WREG32(index_reg, 0x302);
+	WREG32(data_reg, 0xBFF88120);
+	WREG32(index_reg, 0x400);
+	WREG32(data_reg, 0x83188040);
+	WREG32(index_reg, 0x401);
+	WREG32(data_reg, 0x85008660);
+	WREG32(index_reg, 0x402);
+	WREG32(data_reg, 0xBFF88150);
+	WREG32(index_reg, 0x500);
+	WREG32(data_reg, 0x82D88030);
+	WREG32(index_reg, 0x501);
+	WREG32(data_reg, 0x85408640);
+	WREG32(index_reg, 0x502);
+	WREG32(data_reg, 0xBFF88180);
+	WREG32(index_reg, 0x600);
+	WREG32(data_reg, 0x82A08018);
+	WREG32(index_reg, 0x601);
+	WREG32(data_reg, 0x85808620);
+	WREG32(index_reg, 0x602);
+	WREG32(data_reg, 0xBFF081B8);
+	WREG32(index_reg, 0x700);
+	WREG32(data_reg, 0x82608010);
+	WREG32(index_reg, 0x701);
+	WREG32(data_reg, 0x85A08600);
+	WREG32(index_reg, 0x702);
+	WREG32(data_reg, 0x800081F0);
+	WREG32(index_reg, 0x800);
+	WREG32(data_reg, 0x8228BFF8);
+	WREG32(index_reg, 0x801);
+	WREG32(data_reg, 0x85E085E0);
+	WREG32(index_reg, 0x802);
+	WREG32(data_reg, 0xBFF88228);
+	WREG32(index_reg, 0x10000);
+	WREG32(data_reg, 0x82A8BF00);
+	WREG32(index_reg, 0x10001);
+	WREG32(data_reg, 0x82A08CC0);
+	WREG32(index_reg, 0x10002);
+	WREG32(data_reg, 0x8008BEF8);
+	WREG32(index_reg, 0x10100);
+	WREG32(data_reg, 0x81F0BF28);
+	WREG32(index_reg, 0x10101);
+	WREG32(data_reg, 0x83608CA0);
+	WREG32(index_reg, 0x10102);
+	WREG32(data_reg, 0x8018BED0);
+	WREG32(index_reg, 0x10200);
+	WREG32(data_reg, 0x8148BF38);
+	WREG32(index_reg, 0x10201);
+	WREG32(data_reg, 0x84408C80);
+	WREG32(index_reg, 0x10202);
+	WREG32(data_reg, 0x8008BEB8);
+	WREG32(index_reg, 0x10300);
+	WREG32(data_reg, 0x80B0BF78);
+	WREG32(index_reg, 0x10301);
+	WREG32(data_reg, 0x85008C20);
+	WREG32(index_reg, 0x10302);
+	WREG32(data_reg, 0x8020BEA0);
+	WREG32(index_reg, 0x10400);
+	WREG32(data_reg, 0x8028BF90);
+	WREG32(index_reg, 0x10401);
+	WREG32(data_reg, 0x85E08BC0);
+	WREG32(index_reg, 0x10402);
+	WREG32(data_reg, 0x8018BE90);
+	WREG32(index_reg, 0x10500);
+	WREG32(data_reg, 0xBFB8BFB0);
+	WREG32(index_reg, 0x10501);
+	WREG32(data_reg, 0x86C08B40);
+	WREG32(index_reg, 0x10502);
+	WREG32(data_reg, 0x8010BE90);
+	WREG32(index_reg, 0x10600);
+	WREG32(data_reg, 0xBF58BFC8);
+	WREG32(index_reg, 0x10601);
+	WREG32(data_reg, 0x87A08AA0);
+	WREG32(index_reg, 0x10602);
+	WREG32(data_reg, 0x8010BE98);
+	WREG32(index_reg, 0x10700);
+	WREG32(data_reg, 0xBF10BFF0);
+	WREG32(index_reg, 0x10701);
+	WREG32(data_reg, 0x886089E0);
+	WREG32(index_reg, 0x10702);
+	WREG32(data_reg, 0x8018BEB0);
+	WREG32(index_reg, 0x10800);
+	WREG32(data_reg, 0xBED8BFE8);
+	WREG32(index_reg, 0x10801);
+	WREG32(data_reg, 0x89408940);
+	WREG32(index_reg, 0x10802);
+	WREG32(data_reg, 0xBFE8BED8);
+	WREG32(index_reg, 0x20000);
+	WREG32(data_reg, 0x80008000);
+	WREG32(index_reg, 0x20001);
+	WREG32(data_reg, 0x90008000);
+	WREG32(index_reg, 0x20002);
+	WREG32(data_reg, 0x80008000);
+	WREG32(index_reg, 0x20003);
+	WREG32(data_reg, 0x80008000);
+	WREG32(index_reg, 0x20100);
+	WREG32(data_reg, 0x80108000);
+	WREG32(index_reg, 0x20101);
+	WREG32(data_reg, 0x8FE0BF70);
+	WREG32(index_reg, 0x20102);
+	WREG32(data_reg, 0xBFE880C0);
+	WREG32(index_reg, 0x20103);
+	WREG32(data_reg, 0x80008000);
+	WREG32(index_reg, 0x20200);
+	WREG32(data_reg, 0x8018BFF8);
+	WREG32(index_reg, 0x20201);
+	WREG32(data_reg, 0x8F80BF08);
+	WREG32(index_reg, 0x20202);
+	WREG32(data_reg, 0xBFD081A0);
+	WREG32(index_reg, 0x20203);
+	WREG32(data_reg, 0xBFF88000);
+	WREG32(index_reg, 0x20300);
+	WREG32(data_reg, 0x80188000);
+	WREG32(index_reg, 0x20301);
+	WREG32(data_reg, 0x8EE0BEC0);
+	WREG32(index_reg, 0x20302);
+	WREG32(data_reg, 0xBFB082A0);
+	WREG32(index_reg, 0x20303);
+	WREG32(data_reg, 0x80008000);
+	WREG32(index_reg, 0x20400);
+	WREG32(data_reg, 0x80188000);
+	WREG32(index_reg, 0x20401);
+	WREG32(data_reg, 0x8E00BEA0);
+	WREG32(index_reg, 0x20402);
+	WREG32(data_reg, 0xBF8883C0);
+	WREG32(index_reg, 0x20403);
+	WREG32(data_reg, 0x80008000);
+	WREG32(index_reg, 0x20500);
+	WREG32(data_reg, 0x80188000);
+	WREG32(index_reg, 0x20501);
+	WREG32(data_reg, 0x8D00BE90);
+	WREG32(index_reg, 0x20502);
+	WREG32(data_reg, 0xBF588500);
+	WREG32(index_reg, 0x20503);
+	WREG32(data_reg, 0x80008008);
+	WREG32(index_reg, 0x20600);
+	WREG32(data_reg, 0x80188000);
+	WREG32(index_reg, 0x20601);
+	WREG32(data_reg, 0x8BC0BE98);
+	WREG32(index_reg, 0x20602);
+	WREG32(data_reg, 0xBF308660);
+	WREG32(index_reg, 0x20603);
+	WREG32(data_reg, 0x80008008);
+	WREG32(index_reg, 0x20700);
+	WREG32(data_reg, 0x80108000);
+	WREG32(index_reg, 0x20701);
+	WREG32(data_reg, 0x8A80BEB0);
+	WREG32(index_reg, 0x20702);
+	WREG32(data_reg, 0xBF0087C0);
+	WREG32(index_reg, 0x20703);
+	WREG32(data_reg, 0x80008008);
+	WREG32(index_reg, 0x20800);
+	WREG32(data_reg, 0x80108000);
+	WREG32(index_reg, 0x20801);
+	WREG32(data_reg, 0x8920BED0);
+	WREG32(index_reg, 0x20802);
+	WREG32(data_reg, 0xBED08920);
+	WREG32(index_reg, 0x20803);
+	WREG32(data_reg, 0x80008010);
+	WREG32(index_reg, 0x30000);
+	WREG32(data_reg, 0x90008000);
+	WREG32(index_reg, 0x30001);
+	WREG32(data_reg, 0x80008000);
+	WREG32(index_reg, 0x30100);
+	WREG32(data_reg, 0x8FE0BF90);
+	WREG32(index_reg, 0x30101);
+	WREG32(data_reg, 0xBFF880A0);
+	WREG32(index_reg, 0x30200);
+	WREG32(data_reg, 0x8F60BF40);
+	WREG32(index_reg, 0x30201);
+	WREG32(data_reg, 0xBFE88180);
+	WREG32(index_reg, 0x30300);
+	WREG32(data_reg, 0x8EC0BF00);
+	WREG32(index_reg, 0x30301);
+	WREG32(data_reg, 0xBFC88280);
+	WREG32(index_reg, 0x30400);
+	WREG32(data_reg, 0x8DE0BEE0);
+	WREG32(index_reg, 0x30401);
+	WREG32(data_reg, 0xBFA083A0);
+	WREG32(index_reg, 0x30500);
+	WREG32(data_reg, 0x8CE0BED0);
+	WREG32(index_reg, 0x30501);
+	WREG32(data_reg, 0xBF7884E0);
+	WREG32(index_reg, 0x30600);
+	WREG32(data_reg, 0x8BA0BED8);
+	WREG32(index_reg, 0x30601);
+	WREG32(data_reg, 0xBF508640);
+	WREG32(index_reg, 0x30700);
+	WREG32(data_reg, 0x8A60BEE8);
+	WREG32(index_reg, 0x30701);
+	WREG32(data_reg, 0xBF2087A0);
+	WREG32(index_reg, 0x30800);
+	WREG32(data_reg, 0x8900BF00);
+	WREG32(index_reg, 0x30801);
+	WREG32(data_reg, 0xBF008900);
 }
 
 struct rv515_watermark {
-- 
cgit v1.2.3


From 3ce0a23d2d253185df24e22e3d5f89800bb3dd1c Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Tue, 8 Sep 2009 10:10:24 +1000
Subject: drm/radeon/kms: add r600 KMS support

This adds the r600 KMS + CS support to the Linux kernel.

The r600 TTM support is quite basic and still needs more
work esp around using interrupts, but the polled fencing
should work okay for now.

Also currently TTM is using memcpy to do VRAM moves,
the code is here to use a 3D blit to do this, but
isn't fully debugged yet.

Authors:
Alex Deucher <alexdeucher@gmail.com>
Dave Airlie <airlied@redhat.com>
Jerome Glisse <jglisse@redhat.com>

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/Makefile            |    5 +-
 drivers/gpu/drm/radeon/atombios_crtc.c     |    1 +
 drivers/gpu/drm/radeon/avivod.h            |   60 +
 drivers/gpu/drm/radeon/r100.c              |  135 ++-
 drivers/gpu/drm/radeon/r100d.h             |   76 ++
 drivers/gpu/drm/radeon/r300.c              |    3 +-
 drivers/gpu/drm/radeon/r300.h              |   36 -
 drivers/gpu/drm/radeon/r300d.h             |   76 ++
 drivers/gpu/drm/radeon/r600.c              | 1714 ++++++++++++++++++++++++++--
 drivers/gpu/drm/radeon/r600_blit.c         |  855 ++++++++++++++
 drivers/gpu/drm/radeon/r600_blit_kms.c     |  777 +++++++++++++
 drivers/gpu/drm/radeon/r600_blit_shaders.c | 1072 +++++++++++++++++
 drivers/gpu/drm/radeon/r600_blit_shaders.h |   14 +
 drivers/gpu/drm/radeon/r600_cp.c           |  252 +++-
 drivers/gpu/drm/radeon/r600_cs.c           |  658 +++++++++++
 drivers/gpu/drm/radeon/r600d.h             |  661 +++++++++++
 drivers/gpu/drm/radeon/radeon.h            |  120 +-
 drivers/gpu/drm/radeon/radeon_asic.h       |  156 ++-
 drivers/gpu/drm/radeon/radeon_atombios.c   |    4 -
 drivers/gpu/drm/radeon/radeon_clocks.c     |   10 +-
 drivers/gpu/drm/radeon/radeon_device.c     |  340 +++---
 drivers/gpu/drm/radeon/radeon_drv.h        |  141 ++-
 drivers/gpu/drm/radeon/radeon_fence.c      |   54 +-
 drivers/gpu/drm/radeon/radeon_reg.h        |   18 +
 drivers/gpu/drm/radeon/radeon_ring.c       |  119 +-
 drivers/gpu/drm/radeon/radeon_share.h      |   77 ++
 drivers/gpu/drm/radeon/radeon_state.c      |   18 +-
 drivers/gpu/drm/radeon/radeon_ttm.c        |    7 +-
 drivers/gpu/drm/radeon/rs400.c             |    2 +-
 drivers/gpu/drm/radeon/rs780.c             |  102 --
 drivers/gpu/drm/radeon/rv515.c             |    2 +-
 drivers/gpu/drm/radeon/rv515d.h            |  220 ++++
 drivers/gpu/drm/radeon/rv515r.h            |  170 ---
 drivers/gpu/drm/radeon/rv770.c             |  987 +++++++++++++++-
 drivers/gpu/drm/radeon/rv770d.h            |  341 ++++++
 35 files changed, 8483 insertions(+), 800 deletions(-)
 create mode 100644 drivers/gpu/drm/radeon/avivod.h
 create mode 100644 drivers/gpu/drm/radeon/r100d.h
 delete mode 100644 drivers/gpu/drm/radeon/r300.h
 create mode 100644 drivers/gpu/drm/radeon/r300d.h
 create mode 100644 drivers/gpu/drm/radeon/r600_blit.c
 create mode 100644 drivers/gpu/drm/radeon/r600_blit_kms.c
 create mode 100644 drivers/gpu/drm/radeon/r600_blit_shaders.c
 create mode 100644 drivers/gpu/drm/radeon/r600_blit_shaders.h
 create mode 100644 drivers/gpu/drm/radeon/r600_cs.c
 create mode 100644 drivers/gpu/drm/radeon/r600d.h
 delete mode 100644 drivers/gpu/drm/radeon/rs780.c
 create mode 100644 drivers/gpu/drm/radeon/rv515d.h
 delete mode 100644 drivers/gpu/drm/radeon/rv515r.h
 create mode 100644 drivers/gpu/drm/radeon/rv770d.h

diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index c5db0c4fe78..14c3fe69272 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -46,8 +46,9 @@ radeon-$(CONFIG_DRM_RADEON_KMS) += radeon_device.o radeon_kms.o \
 	radeon_encoders.o radeon_display.o radeon_cursor.o radeon_i2c.o \
 	radeon_clocks.o radeon_fb.o radeon_gem.o radeon_ring.o radeon_irq_kms.o \
 	radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \
-	rs400.o rs600.o rs690.o rv515.o r520.o r600.o rs780.o rv770.o \
-	radeon_test.o r200.o radeon_legacy_tv.o
+	rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \
+	r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \
+	r600_blit_kms.o
 
 radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
 
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 8e31e992ec5..a7edd0f2ac3 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -389,6 +389,7 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 					pll_flags |= RADEON_PLL_USE_REF_DIV;
 			}
 			radeon_encoder = to_radeon_encoder(encoder);
+			break;
 		}
 	}
 
diff --git a/drivers/gpu/drm/radeon/avivod.h b/drivers/gpu/drm/radeon/avivod.h
new file mode 100644
index 00000000000..d4e6e6e4a93
--- /dev/null
+++ b/drivers/gpu/drm/radeon/avivod.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2009 Advanced Micro Devices, Inc.
+ * Copyright 2009 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#ifndef AVIVOD_H
+#define AVIVOD_H
+
+
+#define	D1CRTC_CONTROL					0x6080
+#define		CRTC_EN						(1 << 0)
+#define	D1CRTC_UPDATE_LOCK				0x60E8
+#define	D1GRPH_PRIMARY_SURFACE_ADDRESS			0x6110
+#define	D1GRPH_SECONDARY_SURFACE_ADDRESS		0x6118
+
+#define	D2CRTC_CONTROL					0x6880
+#define	D2CRTC_UPDATE_LOCK				0x68E8
+#define	D2GRPH_PRIMARY_SURFACE_ADDRESS			0x6910
+#define	D2GRPH_SECONDARY_SURFACE_ADDRESS		0x6918
+
+#define	D1VGA_CONTROL					0x0330
+#define		DVGA_CONTROL_MODE_ENABLE			(1 << 0)
+#define		DVGA_CONTROL_TIMING_SELECT			(1 << 8)
+#define		DVGA_CONTROL_SYNC_POLARITY_SELECT		(1 << 9)
+#define		DVGA_CONTROL_OVERSCAN_TIMING_SELECT		(1 << 10)
+#define		DVGA_CONTROL_OVERSCAN_COLOR_EN			(1 << 16)
+#define		DVGA_CONTROL_ROTATE				(1 << 24)
+#define D2VGA_CONTROL					0x0338
+
+#define	VGA_HDP_CONTROL					0x328
+#define		VGA_MEM_PAGE_SELECT_EN				(1 << 0)
+#define		VGA_MEMORY_DISABLE				(1 << 4)
+#define		VGA_RBBM_LOCK_DISABLE				(1 << 8)
+#define		VGA_SOFT_RESET					(1 << 16)
+#define	VGA_MEMORY_BASE_ADDRESS				0x0310
+#define	VGA_RENDER_CONTROL				0x0300
+#define		VGA_VSTATUS_CNTL_MASK				0x00030000
+
+#endif
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index ee3ab62417e..5708c07ce73 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -31,6 +31,8 @@
 #include "radeon_drm.h"
 #include "radeon_reg.h"
 #include "radeon.h"
+#include "r100d.h"
+
 #include <linux/firmware.h>
 #include <linux/platform_device.h>
 
@@ -391,9 +393,9 @@ int r100_wb_init(struct radeon_device *rdev)
 			return r;
 		}
 	}
-	WREG32(0x774, rdev->wb.gpu_addr);
-	WREG32(0x70C, rdev->wb.gpu_addr + 1024);
-	WREG32(0x770, 0xff);
+	WREG32(RADEON_SCRATCH_ADDR, rdev->wb.gpu_addr);
+	WREG32(RADEON_CP_RB_RPTR_ADDR, rdev->wb.gpu_addr + 1024);
+	WREG32(RADEON_SCRATCH_UMSK, 0xff);
 	return 0;
 }
 
@@ -559,18 +561,18 @@ static int r100_cp_init_microcode(struct radeon_device *rdev)
 		fw_name = FIRMWARE_R520;
 	}
 
-	err = request_firmware(&rdev->fw, fw_name, &pdev->dev);
+	err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 	platform_device_unregister(pdev);
 	if (err) {
 		printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
 		       fw_name);
-	} else if (rdev->fw->size % 8) {
+	} else if (rdev->me_fw->size % 8) {
 		printk(KERN_ERR
 		       "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
-		       rdev->fw->size, fw_name);
+		       rdev->me_fw->size, fw_name);
 		err = -EINVAL;
-		release_firmware(rdev->fw);
-		rdev->fw = NULL;
+		release_firmware(rdev->me_fw);
+		rdev->me_fw = NULL;
 	}
 	return err;
 }
@@ -584,9 +586,9 @@ static void r100_cp_load_microcode(struct radeon_device *rdev)
 		       "programming pipes. Bad things might happen.\n");
 	}
 
-	if (rdev->fw) {
-		size = rdev->fw->size / 4;
-		fw_data = (const __be32 *)&rdev->fw->data[0];
+	if (rdev->me_fw) {
+		size = rdev->me_fw->size / 4;
+		fw_data = (const __be32 *)&rdev->me_fw->data[0];
 		WREG32(RADEON_CP_ME_RAM_ADDR, 0);
 		for (i = 0; i < size; i += 2) {
 			WREG32(RADEON_CP_ME_RAM_DATAH,
@@ -632,7 +634,7 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
 		DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
 	}
 
-	if (!rdev->fw) {
+	if (!rdev->me_fw) {
 		r = r100_cp_init_microcode(rdev);
 		if (r) {
 			DRM_ERROR("Failed to load firmware!\n");
@@ -765,6 +767,12 @@ int r100_cp_reset(struct radeon_device *rdev)
 	return -1;
 }
 
+void r100_cp_commit(struct radeon_device *rdev)
+{
+	WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
+	(void)RREG32(RADEON_CP_RB_WPTR);
+}
+
 
 /*
  * CS functions
@@ -2954,3 +2962,106 @@ void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track
 			}
 	}
 }
+
+int r100_ring_test(struct radeon_device *rdev)
+{
+	uint32_t scratch;
+	uint32_t tmp = 0;
+	unsigned i;
+	int r;
+
+	r = radeon_scratch_get(rdev, &scratch);
+	if (r) {
+		DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
+		return r;
+	}
+	WREG32(scratch, 0xCAFEDEAD);
+	r = radeon_ring_lock(rdev, 2);
+	if (r) {
+		DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
+		radeon_scratch_free(rdev, scratch);
+		return r;
+	}
+	radeon_ring_write(rdev, PACKET0(scratch, 0));
+	radeon_ring_write(rdev, 0xDEADBEEF);
+	radeon_ring_unlock_commit(rdev);
+	for (i = 0; i < rdev->usec_timeout; i++) {
+		tmp = RREG32(scratch);
+		if (tmp == 0xDEADBEEF) {
+			break;
+		}
+		DRM_UDELAY(1);
+	}
+	if (i < rdev->usec_timeout) {
+		DRM_INFO("ring test succeeded in %d usecs\n", i);
+	} else {
+		DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
+			  scratch, tmp);
+		r = -EINVAL;
+	}
+	radeon_scratch_free(rdev, scratch);
+	return r;
+}
+
+void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
+{
+	radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
+	radeon_ring_write(rdev, ib->gpu_addr);
+	radeon_ring_write(rdev, ib->length_dw);
+}
+
+int r100_ib_test(struct radeon_device *rdev)
+{
+	struct radeon_ib *ib;
+	uint32_t scratch;
+	uint32_t tmp = 0;
+	unsigned i;
+	int r;
+
+	r = radeon_scratch_get(rdev, &scratch);
+	if (r) {
+		DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
+		return r;
+	}
+	WREG32(scratch, 0xCAFEDEAD);
+	r = radeon_ib_get(rdev, &ib);
+	if (r) {
+		return r;
+	}
+	ib->ptr[0] = PACKET0(scratch, 0);
+	ib->ptr[1] = 0xDEADBEEF;
+	ib->ptr[2] = PACKET2(0);
+	ib->ptr[3] = PACKET2(0);
+	ib->ptr[4] = PACKET2(0);
+	ib->ptr[5] = PACKET2(0);
+	ib->ptr[6] = PACKET2(0);
+	ib->ptr[7] = PACKET2(0);
+	ib->length_dw = 8;
+	r = radeon_ib_schedule(rdev, ib);
+	if (r) {
+		radeon_scratch_free(rdev, scratch);
+		radeon_ib_free(rdev, &ib);
+		return r;
+	}
+	r = radeon_fence_wait(ib->fence, false);
+	if (r) {
+		return r;
+	}
+	for (i = 0; i < rdev->usec_timeout; i++) {
+		tmp = RREG32(scratch);
+		if (tmp == 0xDEADBEEF) {
+			break;
+		}
+		DRM_UDELAY(1);
+	}
+	if (i < rdev->usec_timeout) {
+		DRM_INFO("ib test succeeded in %u usecs\n", i);
+	} else {
+		DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
+			  scratch, tmp);
+		r = -EINVAL;
+	}
+	radeon_scratch_free(rdev, scratch);
+	radeon_ib_free(rdev, &ib);
+	return r;
+}
diff --git a/drivers/gpu/drm/radeon/r100d.h b/drivers/gpu/drm/radeon/r100d.h
new file mode 100644
index 00000000000..6da7d92c321
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r100d.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#ifndef __R100D_H__
+#define __R100D_H__
+
+#define CP_PACKET0			0x00000000
+#define		PACKET0_BASE_INDEX_SHIFT	0
+#define		PACKET0_BASE_INDEX_MASK		(0x1ffff << 0)
+#define		PACKET0_COUNT_SHIFT		16
+#define		PACKET0_COUNT_MASK		(0x3fff << 16)
+#define CP_PACKET1			0x40000000
+#define CP_PACKET2			0x80000000
+#define		PACKET2_PAD_SHIFT		0
+#define		PACKET2_PAD_MASK		(0x3fffffff << 0)
+#define CP_PACKET3			0xC0000000
+#define		PACKET3_IT_OPCODE_SHIFT		8
+#define		PACKET3_IT_OPCODE_MASK		(0xff << 8)
+#define		PACKET3_COUNT_SHIFT		16
+#define		PACKET3_COUNT_MASK		(0x3fff << 16)
+/* PACKET3 op code */
+#define		PACKET3_NOP			0x10
+#define		PACKET3_3D_DRAW_VBUF		0x28
+#define		PACKET3_3D_DRAW_IMMD		0x29
+#define		PACKET3_3D_DRAW_INDX		0x2A
+#define		PACKET3_3D_LOAD_VBPNTR		0x2F
+#define		PACKET3_INDX_BUFFER		0x33
+#define		PACKET3_3D_DRAW_VBUF_2		0x34
+#define		PACKET3_3D_DRAW_IMMD_2		0x35
+#define		PACKET3_3D_DRAW_INDX_2		0x36
+#define		PACKET3_BITBLT_MULTI		0x9B
+
+#define PACKET0(reg, n)	(CP_PACKET0 |					\
+			 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) |	\
+			 REG_SET(PACKET0_COUNT, (n)))
+#define PACKET2(v)	(CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
+#define PACKET3(op, n)	(CP_PACKET3 |					\
+			 REG_SET(PACKET3_IT_OPCODE, (op)) |		\
+			 REG_SET(PACKET3_COUNT, (n)))
+
+#define	PACKET_TYPE0	0
+#define	PACKET_TYPE1	1
+#define	PACKET_TYPE2	2
+#define	PACKET_TYPE3	3
+
+#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
+#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
+#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
+#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
+#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
+
+#endif
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 33a2c557eac..a5f82f7beed 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -33,6 +33,7 @@
 #include "radeon_drm.h"
 #include "radeon_share.h"
 #include "r100_track.h"
+#include "r300d.h"
 
 #include "r300_reg_safe.h"
 
@@ -127,7 +128,7 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev)
 	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
 	rv370_pcie_gart_tlb_flush(rdev);
 	DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
-		 rdev->mc.gtt_size >> 20, table_addr);
+		 (unsigned)(rdev->mc.gtt_size >> 20), table_addr);
 	rdev->gart.ready = true;
 	return 0;
 }
diff --git a/drivers/gpu/drm/radeon/r300.h b/drivers/gpu/drm/radeon/r300.h
deleted file mode 100644
index 8486b4da9d6..00000000000
--- a/drivers/gpu/drm/radeon/r300.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright 2008 Advanced Micro Devices, Inc.
- * Copyright 2008 Red Hat Inc.
- * Copyright 2009 Jerome Glisse.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- *          Alex Deucher
- *          Jerome Glisse
- */
-#ifndef R300_H
-#define R300_H
-
-struct r300_asic {
-	const unsigned	*reg_safe_bm;
-	unsigned	reg_safe_bm_size;
-};
-
-#endif
diff --git a/drivers/gpu/drm/radeon/r300d.h b/drivers/gpu/drm/radeon/r300d.h
new file mode 100644
index 00000000000..63ec076f2cd
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r300d.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#ifndef __R300D_H__
+#define __R300D_H__
+
+#define CP_PACKET0			0x00000000
+#define		PACKET0_BASE_INDEX_SHIFT	0
+#define		PACKET0_BASE_INDEX_MASK		(0x1ffff << 0)
+#define		PACKET0_COUNT_SHIFT		16
+#define		PACKET0_COUNT_MASK		(0x3fff << 16)
+#define CP_PACKET1			0x40000000
+#define CP_PACKET2			0x80000000
+#define		PACKET2_PAD_SHIFT		0
+#define		PACKET2_PAD_MASK		(0x3fffffff << 0)
+#define CP_PACKET3			0xC0000000
+#define		PACKET3_IT_OPCODE_SHIFT		8
+#define		PACKET3_IT_OPCODE_MASK		(0xff << 8)
+#define		PACKET3_COUNT_SHIFT		16
+#define		PACKET3_COUNT_MASK		(0x3fff << 16)
+/* PACKET3 op code */
+#define		PACKET3_NOP			0x10
+#define		PACKET3_3D_DRAW_VBUF		0x28
+#define		PACKET3_3D_DRAW_IMMD		0x29
+#define		PACKET3_3D_DRAW_INDX		0x2A
+#define		PACKET3_3D_LOAD_VBPNTR		0x2F
+#define		PACKET3_INDX_BUFFER		0x33
+#define		PACKET3_3D_DRAW_VBUF_2		0x34
+#define		PACKET3_3D_DRAW_IMMD_2		0x35
+#define		PACKET3_3D_DRAW_INDX_2		0x36
+#define		PACKET3_BITBLT_MULTI		0x9B
+
+#define PACKET0(reg, n)	(CP_PACKET0 |					\
+			 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) |	\
+			 REG_SET(PACKET0_COUNT, (n)))
+#define PACKET2(v)	(CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
+#define PACKET3(op, n)	(CP_PACKET3 |					\
+			 REG_SET(PACKET3_IT_OPCODE, (op)) |		\
+			 REG_SET(PACKET3_COUNT, (n)))
+
+#define	PACKET_TYPE0	0
+#define	PACKET_TYPE1	1
+#define	PACKET_TYPE2	2
+#define	PACKET_TYPE3	3
+
+#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
+#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
+#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
+#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
+#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
+
+#endif
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 538cd907df6..d8fcef44a69 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -25,12 +25,46 @@
  *          Alex Deucher
  *          Jerome Glisse
  */
+#include <linux/seq_file.h>
+#include <linux/firmware.h>
+#include <linux/platform_device.h>
 #include "drmP.h"
-#include "radeon_reg.h"
+#include "radeon_drm.h"
 #include "radeon.h"
+#include "radeon_mode.h"
+#include "radeon_share.h"
+#include "r600d.h"
+#include "avivod.h"
+#include "atom.h"
 
-/* r600,rv610,rv630,rv620,rv635,rv670 depends on : */
-void rs600_mc_disable_clients(struct radeon_device *rdev);
+#define PFP_UCODE_SIZE 576
+#define PM4_UCODE_SIZE 1792
+#define R700_PFP_UCODE_SIZE 848
+#define R700_PM4_UCODE_SIZE 1360
+
+/* Firmware Names */
+MODULE_FIRMWARE("radeon/R600_pfp.bin");
+MODULE_FIRMWARE("radeon/R600_me.bin");
+MODULE_FIRMWARE("radeon/RV610_pfp.bin");
+MODULE_FIRMWARE("radeon/RV610_me.bin");
+MODULE_FIRMWARE("radeon/RV630_pfp.bin");
+MODULE_FIRMWARE("radeon/RV630_me.bin");
+MODULE_FIRMWARE("radeon/RV620_pfp.bin");
+MODULE_FIRMWARE("radeon/RV620_me.bin");
+MODULE_FIRMWARE("radeon/RV635_pfp.bin");
+MODULE_FIRMWARE("radeon/RV635_me.bin");
+MODULE_FIRMWARE("radeon/RV670_pfp.bin");
+MODULE_FIRMWARE("radeon/RV670_me.bin");
+MODULE_FIRMWARE("radeon/RS780_pfp.bin");
+MODULE_FIRMWARE("radeon/RS780_me.bin");
+MODULE_FIRMWARE("radeon/RV770_pfp.bin");
+MODULE_FIRMWARE("radeon/RV770_me.bin");
+MODULE_FIRMWARE("radeon/RV730_pfp.bin");
+MODULE_FIRMWARE("radeon/RV730_me.bin");
+MODULE_FIRMWARE("radeon/RV710_pfp.bin");
+MODULE_FIRMWARE("radeon/RV710_me.bin");
+
+int r600_debugfs_mc_info_init(struct radeon_device *rdev);
 
 /* This files gather functions specifics to:
  * r600,rv610,rv630,rv620,rv635,rv670
@@ -39,87 +73,270 @@ void rs600_mc_disable_clients(struct radeon_device *rdev);
  */
 int r600_mc_wait_for_idle(struct radeon_device *rdev);
 void r600_gpu_init(struct radeon_device *rdev);
+void r600_fini(struct radeon_device *rdev);
 
 
 /*
- * MC
+ * R600 PCIE GART
  */
-int r600_mc_init(struct radeon_device *rdev)
+int r600_gart_clear_page(struct radeon_device *rdev, int i)
 {
-	uint32_t tmp;
+	void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
+	u64 pte;
 
-	r600_gpu_init(rdev);
+	if (i < 0 || i > rdev->gart.num_gpu_pages)
+		return -EINVAL;
+	pte = 0;
+	writeq(pte, ((void __iomem *)ptr) + (i * 8));
+	return 0;
+}
 
-	/* setup the gart before changing location so we can ask to
-	 * discard unmapped mc request
-	 */
-	/* FIXME: disable out of gart access */
-	tmp = rdev->mc.gtt_location / 4096;
-	tmp = REG_SET(R600_LOGICAL_PAGE_NUMBER, tmp);
-	WREG32(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, tmp);
-	tmp = (rdev->mc.gtt_location + rdev->mc.gtt_size) / 4096;
-	tmp = REG_SET(R600_LOGICAL_PAGE_NUMBER, tmp);
-	WREG32(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, tmp);
-
-	rs600_mc_disable_clients(rdev);
-	if (r600_mc_wait_for_idle(rdev)) {
-		printk(KERN_WARNING "Failed to wait MC idle while "
-		       "programming pipes. Bad things might happen.\n");
+void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
+{
+	unsigned i;
+	u32 tmp;
+
+	WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
+	WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
+	WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
+	for (i = 0; i < rdev->usec_timeout; i++) {
+		/* read MC_STATUS */
+		tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
+		tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
+		if (tmp == 2) {
+			printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
+			return;
+		}
+		if (tmp) {
+			return;
+		}
+		udelay(1);
+	}
+}
+
+int r600_pcie_gart_enable(struct radeon_device *rdev)
+{
+	u32 tmp;
+	int r, i;
+
+	/* Initialize common gart structure */
+	r = radeon_gart_init(rdev);
+	if (r) {
+		return r;
+	}
+	rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
+	r = radeon_gart_table_vram_alloc(rdev);
+	if (r) {
+		return r;
 	}
+	for (i = 0; i < rdev->gart.num_gpu_pages; i++)
+		r600_gart_clear_page(rdev, i);
+	/* Setup L2 cache */
+	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
+				ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
+				EFFECTIVE_L2_QUEUE_SIZE(7));
+	WREG32(VM_L2_CNTL2, 0);
+	WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
+	/* Setup TLB control */
+	tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
+		SYSTEM_ACCESS_MODE_NOT_IN_SYS |
+		EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
+		ENABLE_WAIT_L2_QUERY;
+	WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
+	WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
+	WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
+	WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
+	WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
+	WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
+	WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
+	WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
+	WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
+	WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
+	WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
+	WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
+	WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
+	WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
+	WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
+	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12);
+	WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
+	WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
+				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
+	WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
+			(u32)(rdev->dummy_page.addr >> 12));
+	for (i = 1; i < 7; i++)
+		WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 
-	tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
-	tmp = REG_SET(R600_MC_FB_TOP, tmp >> 24);
-	tmp |= REG_SET(R600_MC_FB_BASE, rdev->mc.vram_location >> 24);
-	WREG32(R600_MC_VM_FB_LOCATION, tmp);
-	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
-	tmp = REG_SET(R600_MC_AGP_TOP, tmp >> 22);
-	WREG32(R600_MC_VM_AGP_TOP, tmp);
-	tmp = REG_SET(R600_MC_AGP_BOT, rdev->mc.gtt_location >> 22);
-	WREG32(R600_MC_VM_AGP_BOT, tmp);
+	r600_pcie_gart_tlb_flush(rdev);
+	rdev->gart.ready = true;
 	return 0;
 }
 
-void r600_mc_fini(struct radeon_device *rdev)
+void r600_pcie_gart_disable(struct radeon_device *rdev)
 {
-	/* FIXME: implement */
-}
+	u32 tmp;
+	int i;
 
+	/* Clear ptes*/
+	for (i = 0; i < rdev->gart.num_gpu_pages; i++)
+		r600_gart_clear_page(rdev, i);
+	r600_pcie_gart_tlb_flush(rdev);
+	/* Disable all tables */
+	for (i = 0; i < 7; i++)
+		WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 
-/*
- * Global GPU functions
- */
-void r600_errata(struct radeon_device *rdev)
-{
-	rdev->pll_errata = 0;
+	/* Disable L2 cache */
+	WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
+				EFFECTIVE_L2_QUEUE_SIZE(7));
+	WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
+	/* Setup L1 TLB control */
+	tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
+		ENABLE_WAIT_L2_QUERY;
+	WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
+	WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
+	WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
+	WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
+	WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
+	WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
+	WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
+	WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
+	WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
+	WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
+	WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
+	WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
+	WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
+	WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 }
 
 int r600_mc_wait_for_idle(struct radeon_device *rdev)
 {
-	/* FIXME: implement */
-	return 0;
+	unsigned i;
+	u32 tmp;
+
+	for (i = 0; i < rdev->usec_timeout; i++) {
+		/* read MC_STATUS */
+		tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
+		if (!tmp)
+			return 0;
+		udelay(1);
+	}
+	return -1;
 }
 
-void r600_gpu_init(struct radeon_device *rdev)
+static void r600_mc_resume(struct radeon_device *rdev)
 {
-	/* FIXME: implement */
-}
+	u32 d1vga_control, d2vga_control;
+	u32 vga_render_control, vga_hdp_control;
+	u32 d1crtc_control, d2crtc_control;
+	u32 new_d1grph_primary, new_d1grph_secondary;
+	u32 new_d2grph_primary, new_d2grph_secondary;
+	u64 old_vram_start;
+	u32 tmp;
+	int i, j;
 
+	/* Initialize HDP */
+	for (i = 0, j = 0; i < 32; i++, j += 0x18) {
+		WREG32((0x2c14 + j), 0x00000000);
+		WREG32((0x2c18 + j), 0x00000000);
+		WREG32((0x2c1c + j), 0x00000000);
+		WREG32((0x2c20 + j), 0x00000000);
+		WREG32((0x2c24 + j), 0x00000000);
+	}
+	WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
 
-/*
- * VRAM info
- */
-void r600_vram_get_type(struct radeon_device *rdev)
+	d1vga_control = RREG32(D1VGA_CONTROL);
+	d2vga_control = RREG32(D2VGA_CONTROL);
+	vga_render_control = RREG32(VGA_RENDER_CONTROL);
+	vga_hdp_control = RREG32(VGA_HDP_CONTROL);
+	d1crtc_control = RREG32(D1CRTC_CONTROL);
+	d2crtc_control = RREG32(D2CRTC_CONTROL);
+	old_vram_start = (u64)(RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
+	new_d1grph_primary = RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS);
+	new_d1grph_secondary = RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS);
+	new_d1grph_primary += rdev->mc.vram_start - old_vram_start;
+	new_d1grph_secondary += rdev->mc.vram_start - old_vram_start;
+	new_d2grph_primary = RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS);
+	new_d2grph_secondary = RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS);
+	new_d2grph_primary += rdev->mc.vram_start - old_vram_start;
+	new_d2grph_secondary += rdev->mc.vram_start - old_vram_start;
+
+	/* Stop all video */
+	WREG32(D1VGA_CONTROL, 0);
+	WREG32(D2VGA_CONTROL, 0);
+	WREG32(VGA_RENDER_CONTROL, 0);
+	WREG32(D1CRTC_UPDATE_LOCK, 1);
+	WREG32(D2CRTC_UPDATE_LOCK, 1);
+	WREG32(D1CRTC_CONTROL, 0);
+	WREG32(D2CRTC_CONTROL, 0);
+	WREG32(D1CRTC_UPDATE_LOCK, 0);
+	WREG32(D2CRTC_UPDATE_LOCK, 0);
+
+	mdelay(1);
+	if (r600_mc_wait_for_idle(rdev)) {
+		printk(KERN_WARNING "[drm] MC not idle !\n");
+	}
+
+	/* Lockout access through VGA aperture*/
+	WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
+
+	/* Update configuration */
+	WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
+	WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12);
+	WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
+	tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16;
+	tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
+	WREG32(MC_VM_FB_LOCATION, tmp);
+	WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
+	WREG32(HDP_NONSURFACE_INFO, (2 << 7));
+	WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
+	if (rdev->flags & RADEON_IS_AGP) {
+		WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16);
+		WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
+		WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
+	} else {
+		WREG32(MC_VM_AGP_BASE, 0);
+		WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
+		WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
+	}
+	WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS, new_d1grph_primary);
+	WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS, new_d1grph_secondary);
+	WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS, new_d2grph_primary);
+	WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS, new_d2grph_secondary);
+	WREG32(VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
+
+	/* Unlock host access */
+	WREG32(VGA_HDP_CONTROL, vga_hdp_control);
+
+	mdelay(1);
+	if (r600_mc_wait_for_idle(rdev)) {
+		printk(KERN_WARNING "[drm] MC not idle !\n");
+	}
+
+	/* Restore video state */
+	WREG32(D1CRTC_UPDATE_LOCK, 1);
+	WREG32(D2CRTC_UPDATE_LOCK, 1);
+	WREG32(D1CRTC_CONTROL, d1crtc_control);
+	WREG32(D2CRTC_CONTROL, d2crtc_control);
+	WREG32(D1CRTC_UPDATE_LOCK, 0);
+	WREG32(D2CRTC_UPDATE_LOCK, 0);
+	WREG32(D1VGA_CONTROL, d1vga_control);
+	WREG32(D2VGA_CONTROL, d2vga_control);
+	WREG32(VGA_RENDER_CONTROL, vga_render_control);
+}
+
+int r600_mc_init(struct radeon_device *rdev)
 {
-	uint32_t tmp;
+	fixed20_12 a;
+	u32 tmp;
 	int chansize;
+	int r;
 
+	/* Get VRAM informations */
 	rdev->mc.vram_width = 128;
 	rdev->mc.vram_is_ddr = true;
-
-	tmp = RREG32(R600_RAMCFG);
-	if (tmp & R600_CHANSIZE_OVERRIDE) {
+	tmp = RREG32(RAMCFG);
+	if (tmp & CHANSIZE_OVERRIDE) {
 		chansize = 16;
-	} else if (tmp & R600_CHANSIZE) {
+	} else if (tmp & CHANSIZE_MASK) {
 		chansize = 64;
 	} else {
 		chansize = 32;
@@ -135,36 +352,1391 @@ void r600_vram_get_type(struct radeon_device *rdev)
 			(rdev->family == CHIP_RV635)) {
 		rdev->mc.vram_width = 2 * chansize;
 	}
+	/* Could aper size report 0 ? */
+	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
+	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
+	/* Setup GPU memory space */
+	rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
+	rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
+	if (rdev->flags & RADEON_IS_AGP) {
+		r = radeon_agp_init(rdev);
+		if (r)
+			return r;
+		/* gtt_size is setup by radeon_agp_init */
+		rdev->mc.gtt_location = rdev->mc.agp_base;
+		tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
+		/* Try to put vram before or after AGP because we
+		 * we want SYSTEM_APERTURE to cover both VRAM and
+		 * AGP so that GPU can catch out of VRAM/AGP access
+		 */
+		if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
+			/* Enought place before */
+			rdev->mc.vram_location = rdev->mc.gtt_location -
+							rdev->mc.mc_vram_size;
+		} else if (tmp > rdev->mc.mc_vram_size) {
+			/* Enought place after */
+			rdev->mc.vram_location = rdev->mc.gtt_location +
+							rdev->mc.gtt_size;
+		} else {
+			/* Try to setup VRAM then AGP might not
+			 * not work on some card
+			 */
+			rdev->mc.vram_location = 0x00000000UL;
+			rdev->mc.gtt_location = rdev->mc.mc_vram_size;
+		}
+	} else {
+		if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
+			rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
+								0xFFFF) << 24;
+			rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
+			tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
+			if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
+				/* Enough place after vram */
+				rdev->mc.gtt_location = tmp;
+			} else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
+				/* Enough place before vram */
+				rdev->mc.gtt_location = 0;
+			} else {
+				/* Not enough place after or before shrink
+				 * gart size
+				 */
+				if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
+					rdev->mc.gtt_location = 0;
+					rdev->mc.gtt_size = rdev->mc.vram_location;
+				} else {
+					rdev->mc.gtt_location = tmp;
+					rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
+				}
+			}
+			rdev->mc.gtt_location = rdev->mc.mc_vram_size;
+		} else {
+			rdev->mc.vram_location = 0x00000000UL;
+			rdev->mc.gtt_location = rdev->mc.mc_vram_size;
+			rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
+		}
+	}
+	rdev->mc.vram_start = rdev->mc.vram_location;
+	rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size;
+	rdev->mc.gtt_start = rdev->mc.gtt_location;
+	rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size;
+	/* FIXME: we should enforce default clock in case GPU is not in
+	 * default setup
+	 */
+	a.full = rfixed_const(100);
+	rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
+	rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
+	return 0;
 }
 
-void r600_vram_info(struct radeon_device *rdev)
+/* We doesn't check that the GPU really needs a reset we simply do the
+ * reset, it's up to the caller to determine if the GPU needs one. We
+ * might add an helper function to check that.
+ */
+int r600_gpu_soft_reset(struct radeon_device *rdev)
 {
-	r600_vram_get_type(rdev);
-	rdev->mc.real_vram_size = RREG32(R600_CONFIG_MEMSIZE);
-	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
+	u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
+				S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
+				S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
+				S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
+				S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
+				S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
+				S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
+				S_008010_GUI_ACTIVE(1);
+	u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
+			S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
+			S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
+			S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
+			S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
+			S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
+			S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
+			S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
+	u32 srbm_reset = 0;
 
-	/* Could aper size report 0 ? */
-	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
-	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
+	/* Disable CP parsing/prefetching */
+	WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
+	/* Check if any of the rendering block is busy and reset it */
+	if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
+	    (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
+		WREG32(R_008020_GRBM_SOFT_RESET, S_008020_SOFT_RESET_CR(1) |
+			S_008020_SOFT_RESET_DB(1) |
+			S_008020_SOFT_RESET_CB(1) |
+			S_008020_SOFT_RESET_PA(1) |
+			S_008020_SOFT_RESET_SC(1) |
+			S_008020_SOFT_RESET_SMX(1) |
+			S_008020_SOFT_RESET_SPI(1) |
+			S_008020_SOFT_RESET_SX(1) |
+			S_008020_SOFT_RESET_SH(1) |
+			S_008020_SOFT_RESET_TC(1) |
+			S_008020_SOFT_RESET_TA(1) |
+			S_008020_SOFT_RESET_VC(1) |
+			S_008020_SOFT_RESET_VGT(1));
+		(void)RREG32(R_008020_GRBM_SOFT_RESET);
+		udelay(50);
+		WREG32(R_008020_GRBM_SOFT_RESET, 0);
+		(void)RREG32(R_008020_GRBM_SOFT_RESET);
+	}
+	/* Reset CP (we always reset CP) */
+	WREG32(R_008020_GRBM_SOFT_RESET, S_008020_SOFT_RESET_CP(1));
+	(void)RREG32(R_008020_GRBM_SOFT_RESET);
+	udelay(50);
+	WREG32(R_008020_GRBM_SOFT_RESET, 0);
+	(void)RREG32(R_008020_GRBM_SOFT_RESET);
+	/* Reset others GPU block if necessary */
+	if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
+		srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
+	if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
+		srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
+	if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
+		srbm_reset |= S_000E60_SOFT_RESET_IH(1);
+	if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
+		srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
+	if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
+		srbm_reset |= S_000E60_SOFT_RESET_MC(1);
+	if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
+		srbm_reset |= S_000E60_SOFT_RESET_MC(1);
+	if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
+		srbm_reset |= S_000E60_SOFT_RESET_MC(1);
+	if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
+		srbm_reset |= S_000E60_SOFT_RESET_MC(1);
+	if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
+		srbm_reset |= S_000E60_SOFT_RESET_MC(1);
+	if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
+		srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
+	if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
+		srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
+	WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
+	(void)RREG32(R_000E60_SRBM_SOFT_RESET);
+	udelay(50);
+	WREG32(R_000E60_SRBM_SOFT_RESET, 0);
+	(void)RREG32(R_000E60_SRBM_SOFT_RESET);
+	/* Wait a little for things to settle down */
+	udelay(50);
+	return 0;
+}
+
+int r600_gpu_reset(struct radeon_device *rdev)
+{
+	return r600_gpu_soft_reset(rdev);
+}
+
+static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
+					     u32 num_backends,
+					     u32 backend_disable_mask)
+{
+	u32 backend_map = 0;
+	u32 enabled_backends_mask;
+	u32 enabled_backends_count;
+	u32 cur_pipe;
+	u32 swizzle_pipe[R6XX_MAX_PIPES];
+	u32 cur_backend;
+	u32 i;
+
+	if (num_tile_pipes > R6XX_MAX_PIPES)
+		num_tile_pipes = R6XX_MAX_PIPES;
+	if (num_tile_pipes < 1)
+		num_tile_pipes = 1;
+	if (num_backends > R6XX_MAX_BACKENDS)
+		num_backends = R6XX_MAX_BACKENDS;
+	if (num_backends < 1)
+		num_backends = 1;
+
+	enabled_backends_mask = 0;
+	enabled_backends_count = 0;
+	for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
+		if (((backend_disable_mask >> i) & 1) == 0) {
+			enabled_backends_mask |= (1 << i);
+			++enabled_backends_count;
+		}
+		if (enabled_backends_count == num_backends)
+			break;
+	}
+
+	if (enabled_backends_count == 0) {
+		enabled_backends_mask = 1;
+		enabled_backends_count = 1;
+	}
+
+	if (enabled_backends_count != num_backends)
+		num_backends = enabled_backends_count;
+
+	memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
+	switch (num_tile_pipes) {
+	case 1:
+		swizzle_pipe[0] = 0;
+		break;
+	case 2:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 1;
+		break;
+	case 3:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 1;
+		swizzle_pipe[2] = 2;
+		break;
+	case 4:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 1;
+		swizzle_pipe[2] = 2;
+		swizzle_pipe[3] = 3;
+		break;
+	case 5:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 1;
+		swizzle_pipe[2] = 2;
+		swizzle_pipe[3] = 3;
+		swizzle_pipe[4] = 4;
+		break;
+	case 6:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 2;
+		swizzle_pipe[2] = 4;
+		swizzle_pipe[3] = 5;
+		swizzle_pipe[4] = 1;
+		swizzle_pipe[5] = 3;
+		break;
+	case 7:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 2;
+		swizzle_pipe[2] = 4;
+		swizzle_pipe[3] = 6;
+		swizzle_pipe[4] = 1;
+		swizzle_pipe[5] = 3;
+		swizzle_pipe[6] = 5;
+		break;
+	case 8:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 2;
+		swizzle_pipe[2] = 4;
+		swizzle_pipe[3] = 6;
+		swizzle_pipe[4] = 1;
+		swizzle_pipe[5] = 3;
+		swizzle_pipe[6] = 5;
+		swizzle_pipe[7] = 7;
+		break;
+	}
+
+	cur_backend = 0;
+	for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
+		while (((1 << cur_backend) & enabled_backends_mask) == 0)
+			cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
+
+		backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
+
+		cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
+	}
+
+	return backend_map;
+}
+
+int r600_count_pipe_bits(uint32_t val)
+{
+	int i, ret = 0;
+
+	for (i = 0; i < 32; i++) {
+		ret += val & 1;
+		val >>= 1;
+	}
+	return ret;
 }
 
+void r600_gpu_init(struct radeon_device *rdev)
+{
+	u32 tiling_config;
+	u32 ramcfg;
+	u32 tmp;
+	int i, j;
+	u32 sq_config;
+	u32 sq_gpr_resource_mgmt_1 = 0;
+	u32 sq_gpr_resource_mgmt_2 = 0;
+	u32 sq_thread_resource_mgmt = 0;
+	u32 sq_stack_resource_mgmt_1 = 0;
+	u32 sq_stack_resource_mgmt_2 = 0;
+
+	/* FIXME: implement */
+	switch (rdev->family) {
+	case CHIP_R600:
+		rdev->config.r600.max_pipes = 4;
+		rdev->config.r600.max_tile_pipes = 8;
+		rdev->config.r600.max_simds = 4;
+		rdev->config.r600.max_backends = 4;
+		rdev->config.r600.max_gprs = 256;
+		rdev->config.r600.max_threads = 192;
+		rdev->config.r600.max_stack_entries = 256;
+		rdev->config.r600.max_hw_contexts = 8;
+		rdev->config.r600.max_gs_threads = 16;
+		rdev->config.r600.sx_max_export_size = 128;
+		rdev->config.r600.sx_max_export_pos_size = 16;
+		rdev->config.r600.sx_max_export_smx_size = 128;
+		rdev->config.r600.sq_num_cf_insts = 2;
+		break;
+	case CHIP_RV630:
+	case CHIP_RV635:
+		rdev->config.r600.max_pipes = 2;
+		rdev->config.r600.max_tile_pipes = 2;
+		rdev->config.r600.max_simds = 3;
+		rdev->config.r600.max_backends = 1;
+		rdev->config.r600.max_gprs = 128;
+		rdev->config.r600.max_threads = 192;
+		rdev->config.r600.max_stack_entries = 128;
+		rdev->config.r600.max_hw_contexts = 8;
+		rdev->config.r600.max_gs_threads = 4;
+		rdev->config.r600.sx_max_export_size = 128;
+		rdev->config.r600.sx_max_export_pos_size = 16;
+		rdev->config.r600.sx_max_export_smx_size = 128;
+		rdev->config.r600.sq_num_cf_insts = 2;
+		break;
+	case CHIP_RV610:
+	case CHIP_RV620:
+	case CHIP_RS780:
+	case CHIP_RS880:
+		rdev->config.r600.max_pipes = 1;
+		rdev->config.r600.max_tile_pipes = 1;
+		rdev->config.r600.max_simds = 2;
+		rdev->config.r600.max_backends = 1;
+		rdev->config.r600.max_gprs = 128;
+		rdev->config.r600.max_threads = 192;
+		rdev->config.r600.max_stack_entries = 128;
+		rdev->config.r600.max_hw_contexts = 4;
+		rdev->config.r600.max_gs_threads = 4;
+		rdev->config.r600.sx_max_export_size = 128;
+		rdev->config.r600.sx_max_export_pos_size = 16;
+		rdev->config.r600.sx_max_export_smx_size = 128;
+		rdev->config.r600.sq_num_cf_insts = 1;
+		break;
+	case CHIP_RV670:
+		rdev->config.r600.max_pipes = 4;
+		rdev->config.r600.max_tile_pipes = 4;
+		rdev->config.r600.max_simds = 4;
+		rdev->config.r600.max_backends = 4;
+		rdev->config.r600.max_gprs = 192;
+		rdev->config.r600.max_threads = 192;
+		rdev->config.r600.max_stack_entries = 256;
+		rdev->config.r600.max_hw_contexts = 8;
+		rdev->config.r600.max_gs_threads = 16;
+		rdev->config.r600.sx_max_export_size = 128;
+		rdev->config.r600.sx_max_export_pos_size = 16;
+		rdev->config.r600.sx_max_export_smx_size = 128;
+		rdev->config.r600.sq_num_cf_insts = 2;
+		break;
+	default:
+		break;
+	}
+
+	/* Initialize HDP */
+	for (i = 0, j = 0; i < 32; i++, j += 0x18) {
+		WREG32((0x2c14 + j), 0x00000000);
+		WREG32((0x2c18 + j), 0x00000000);
+		WREG32((0x2c1c + j), 0x00000000);
+		WREG32((0x2c20 + j), 0x00000000);
+		WREG32((0x2c24 + j), 0x00000000);
+	}
+
+	WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
+
+	/* Setup tiling */
+	tiling_config = 0;
+	ramcfg = RREG32(RAMCFG);
+	switch (rdev->config.r600.max_tile_pipes) {
+	case 1:
+		tiling_config |= PIPE_TILING(0);
+		break;
+	case 2:
+		tiling_config |= PIPE_TILING(1);
+		break;
+	case 4:
+		tiling_config |= PIPE_TILING(2);
+		break;
+	case 8:
+		tiling_config |= PIPE_TILING(3);
+		break;
+	default:
+		break;
+	}
+	tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
+	tiling_config |= GROUP_SIZE(0);
+	tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
+	if (tmp > 3) {
+		tiling_config |= ROW_TILING(3);
+		tiling_config |= SAMPLE_SPLIT(3);
+	} else {
+		tiling_config |= ROW_TILING(tmp);
+		tiling_config |= SAMPLE_SPLIT(tmp);
+	}
+	tiling_config |= BANK_SWAPS(1);
+	tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
+						rdev->config.r600.max_backends,
+						(0xff << rdev->config.r600.max_backends) & 0xff);
+	tiling_config |= BACKEND_MAP(tmp);
+	WREG32(GB_TILING_CONFIG, tiling_config);
+	WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
+	WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
+
+	tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
+	WREG32(CC_RB_BACKEND_DISABLE, tmp);
+
+	/* Setup pipes */
+	tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
+	tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
+	WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp);
+	WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
+
+	tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK);
+	WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
+	WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
+
+	/* Setup some CP states */
+	WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
+	WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
+
+	WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
+			     SYNC_WALKER | SYNC_ALIGNER));
+	/* Setup various GPU states */
+	if (rdev->family == CHIP_RV670)
+		WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
+
+	tmp = RREG32(SX_DEBUG_1);
+	tmp |= SMX_EVENT_RELEASE;
+	if ((rdev->family > CHIP_R600))
+		tmp |= ENABLE_NEW_SMX_ADDRESS;
+	WREG32(SX_DEBUG_1, tmp);
+
+	if (((rdev->family) == CHIP_R600) ||
+	    ((rdev->family) == CHIP_RV630) ||
+	    ((rdev->family) == CHIP_RV610) ||
+	    ((rdev->family) == CHIP_RV620) ||
+	    ((rdev->family) == CHIP_RS780)) {
+		WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
+	} else {
+		WREG32(DB_DEBUG, 0);
+	}
+	WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
+			       DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
+
+	WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
+	WREG32(VGT_NUM_INSTANCES, 0);
+
+	WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
+	WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
+
+	tmp = RREG32(SQ_MS_FIFO_SIZES);
+	if (((rdev->family) == CHIP_RV610) ||
+	    ((rdev->family) == CHIP_RV620) ||
+	    ((rdev->family) == CHIP_RS780)) {
+		tmp = (CACHE_FIFO_SIZE(0xa) |
+		       FETCH_FIFO_HIWATER(0xa) |
+		       DONE_FIFO_HIWATER(0xe0) |
+		       ALU_UPDATE_FIFO_HIWATER(0x8));
+	} else if (((rdev->family) == CHIP_R600) ||
+		   ((rdev->family) == CHIP_RV630)) {
+		tmp &= ~DONE_FIFO_HIWATER(0xff);
+		tmp |= DONE_FIFO_HIWATER(0x4);
+	}
+	WREG32(SQ_MS_FIFO_SIZES, tmp);
+
+	/* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
+	 * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
+	 */
+	sq_config = RREG32(SQ_CONFIG);
+	sq_config &= ~(PS_PRIO(3) |
+		       VS_PRIO(3) |
+		       GS_PRIO(3) |
+		       ES_PRIO(3));
+	sq_config |= (DX9_CONSTS |
+		      VC_ENABLE |
+		      PS_PRIO(0) |
+		      VS_PRIO(1) |
+		      GS_PRIO(2) |
+		      ES_PRIO(3));
+
+	if ((rdev->family) == CHIP_R600) {
+		sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
+					  NUM_VS_GPRS(124) |
+					  NUM_CLAUSE_TEMP_GPRS(4));
+		sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
+					  NUM_ES_GPRS(0));
+		sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
+					   NUM_VS_THREADS(48) |
+					   NUM_GS_THREADS(4) |
+					   NUM_ES_THREADS(4));
+		sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
+					    NUM_VS_STACK_ENTRIES(128));
+		sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
+					    NUM_ES_STACK_ENTRIES(0));
+	} else if (((rdev->family) == CHIP_RV610) ||
+		   ((rdev->family) == CHIP_RV620) ||
+		   ((rdev->family) == CHIP_RS780)) {
+		/* no vertex cache */
+		sq_config &= ~VC_ENABLE;
+
+		sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
+					  NUM_VS_GPRS(44) |
+					  NUM_CLAUSE_TEMP_GPRS(2));
+		sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
+					  NUM_ES_GPRS(17));
+		sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
+					   NUM_VS_THREADS(78) |
+					   NUM_GS_THREADS(4) |
+					   NUM_ES_THREADS(31));
+		sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
+					    NUM_VS_STACK_ENTRIES(40));
+		sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
+					    NUM_ES_STACK_ENTRIES(16));
+	} else if (((rdev->family) == CHIP_RV630) ||
+		   ((rdev->family) == CHIP_RV635)) {
+		sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
+					  NUM_VS_GPRS(44) |
+					  NUM_CLAUSE_TEMP_GPRS(2));
+		sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
+					  NUM_ES_GPRS(18));
+		sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
+					   NUM_VS_THREADS(78) |
+					   NUM_GS_THREADS(4) |
+					   NUM_ES_THREADS(31));
+		sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
+					    NUM_VS_STACK_ENTRIES(40));
+		sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
+					    NUM_ES_STACK_ENTRIES(16));
+	} else if ((rdev->family) == CHIP_RV670) {
+		sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
+					  NUM_VS_GPRS(44) |
+					  NUM_CLAUSE_TEMP_GPRS(2));
+		sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
+					  NUM_ES_GPRS(17));
+		sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
+					   NUM_VS_THREADS(78) |
+					   NUM_GS_THREADS(4) |
+					   NUM_ES_THREADS(31));
+		sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
+					    NUM_VS_STACK_ENTRIES(64));
+		sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
+					    NUM_ES_STACK_ENTRIES(64));
+	}
+
+	WREG32(SQ_CONFIG, sq_config);
+	WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
+	WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
+	WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
+	WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
+	WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
+
+	if (((rdev->family) == CHIP_RV610) ||
+	    ((rdev->family) == CHIP_RV620) ||
+	    ((rdev->family) == CHIP_RS780)) {
+		WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
+	} else {
+		WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
+	}
+
+	/* More default values. 2D/3D driver should adjust as needed */
+	WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
+					 S1_X(0x4) | S1_Y(0xc)));
+	WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
+					 S1_X(0x2) | S1_Y(0x2) |
+					 S2_X(0xa) | S2_Y(0x6) |
+					 S3_X(0x6) | S3_Y(0xa)));
+	WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
+					     S1_X(0x4) | S1_Y(0xc) |
+					     S2_X(0x1) | S2_Y(0x6) |
+					     S3_X(0xa) | S3_Y(0xe)));
+	WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
+					     S5_X(0x0) | S5_Y(0x0) |
+					     S6_X(0xb) | S6_Y(0x4) |
+					     S7_X(0x7) | S7_Y(0x8)));
+
+	WREG32(VGT_STRMOUT_EN, 0);
+	tmp = rdev->config.r600.max_pipes * 16;
+	switch (rdev->family) {
+	case CHIP_RV610:
+	case CHIP_RS780:
+	case CHIP_RV620:
+		tmp += 32;
+		break;
+	case CHIP_RV670:
+		tmp += 128;
+		break;
+	default:
+		break;
+	}
+	if (tmp > 256) {
+		tmp = 256;
+	}
+	WREG32(VGT_ES_PER_GS, 128);
+	WREG32(VGT_GS_PER_ES, tmp);
+	WREG32(VGT_GS_PER_VS, 2);
+	WREG32(VGT_GS_VERTEX_REUSE, 16);
+
+	/* more default values. 2D/3D driver should adjust as needed */
+	WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
+	WREG32(VGT_STRMOUT_EN, 0);
+	WREG32(SX_MISC, 0);
+	WREG32(PA_SC_MODE_CNTL, 0);
+	WREG32(PA_SC_AA_CONFIG, 0);
+	WREG32(PA_SC_LINE_STIPPLE, 0);
+	WREG32(SPI_INPUT_Z, 0);
+	WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
+	WREG32(CB_COLOR7_FRAG, 0);
+
+	/* Clear render buffer base addresses */
+	WREG32(CB_COLOR0_BASE, 0);
+	WREG32(CB_COLOR1_BASE, 0);
+	WREG32(CB_COLOR2_BASE, 0);
+	WREG32(CB_COLOR3_BASE, 0);
+	WREG32(CB_COLOR4_BASE, 0);
+	WREG32(CB_COLOR5_BASE, 0);
+	WREG32(CB_COLOR6_BASE, 0);
+	WREG32(CB_COLOR7_BASE, 0);
+	WREG32(CB_COLOR7_FRAG, 0);
+
+	switch (rdev->family) {
+	case CHIP_RV610:
+	case CHIP_RS780:
+	case CHIP_RV620:
+		tmp = TC_L2_SIZE(8);
+		break;
+	case CHIP_RV630:
+	case CHIP_RV635:
+		tmp = TC_L2_SIZE(4);
+		break;
+	case CHIP_R600:
+		tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
+		break;
+	default:
+		tmp = TC_L2_SIZE(0);
+		break;
+	}
+	WREG32(TC_CNTL, tmp);
+
+	tmp = RREG32(HDP_HOST_PATH_CNTL);
+	WREG32(HDP_HOST_PATH_CNTL, tmp);
+
+	tmp = RREG32(ARB_POP);
+	tmp |= ENABLE_TC128;
+	WREG32(ARB_POP, tmp);
+
+	WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
+	WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
+			       NUM_CLIP_SEQ(3)));
+	WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
+}
+
+
 /*
  * Indirect registers accessor
  */
-uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg)
+u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
+{
+	u32 r;
+
+	WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
+	(void)RREG32(PCIE_PORT_INDEX);
+	r = RREG32(PCIE_PORT_DATA);
+	return r;
+}
+
+void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
+{
+	WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
+	(void)RREG32(PCIE_PORT_INDEX);
+	WREG32(PCIE_PORT_DATA, (v));
+	(void)RREG32(PCIE_PORT_DATA);
+}
+
+
+/*
+ * CP & Ring
+ */
+void r600_cp_stop(struct radeon_device *rdev)
+{
+	WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
+}
+
+int r600_cp_init_microcode(struct radeon_device *rdev)
+{
+	struct platform_device *pdev;
+	const char *chip_name;
+	size_t pfp_req_size, me_req_size;
+	char fw_name[30];
+	int err;
+
+	DRM_DEBUG("\n");
+
+	pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
+	err = IS_ERR(pdev);
+	if (err) {
+		printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
+		return -EINVAL;
+	}
+
+	switch (rdev->family) {
+	case CHIP_R600: chip_name = "R600"; break;
+	case CHIP_RV610: chip_name = "RV610"; break;
+	case CHIP_RV630: chip_name = "RV630"; break;
+	case CHIP_RV620: chip_name = "RV620"; break;
+	case CHIP_RV635: chip_name = "RV635"; break;
+	case CHIP_RV670: chip_name = "RV670"; break;
+	case CHIP_RS780:
+	case CHIP_RS880: chip_name = "RS780"; break;
+	case CHIP_RV770: chip_name = "RV770"; break;
+	case CHIP_RV730:
+	case CHIP_RV740: chip_name = "RV730"; break;
+	case CHIP_RV710: chip_name = "RV710"; break;
+	default: BUG();
+	}
+
+	if (rdev->family >= CHIP_RV770) {
+		pfp_req_size = R700_PFP_UCODE_SIZE * 4;
+		me_req_size = R700_PM4_UCODE_SIZE * 4;
+	} else {
+		pfp_req_size = PFP_UCODE_SIZE * 4;
+		me_req_size = PM4_UCODE_SIZE * 12;
+	}
+
+	DRM_INFO("Loading %s CP Microcode\n", chip_name);
+
+	snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
+	err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
+	if (err)
+		goto out;
+	if (rdev->pfp_fw->size != pfp_req_size) {
+		printk(KERN_ERR
+		       "r600_cp: Bogus length %zu in firmware \"%s\"\n",
+		       rdev->pfp_fw->size, fw_name);
+		err = -EINVAL;
+		goto out;
+	}
+
+	snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
+	err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
+	if (err)
+		goto out;
+	if (rdev->me_fw->size != me_req_size) {
+		printk(KERN_ERR
+		       "r600_cp: Bogus length %zu in firmware \"%s\"\n",
+		       rdev->me_fw->size, fw_name);
+		err = -EINVAL;
+	}
+out:
+	platform_device_unregister(pdev);
+
+	if (err) {
+		if (err != -EINVAL)
+			printk(KERN_ERR
+			       "r600_cp: Failed to load firmware \"%s\"\n",
+			       fw_name);
+		release_firmware(rdev->pfp_fw);
+		rdev->pfp_fw = NULL;
+		release_firmware(rdev->me_fw);
+		rdev->me_fw = NULL;
+	}
+	return err;
+}
+
+static int r600_cp_load_microcode(struct radeon_device *rdev)
+{
+	const __be32 *fw_data;
+	int i;
+
+	if (!rdev->me_fw || !rdev->pfp_fw)
+		return -EINVAL;
+
+	r600_cp_stop(rdev);
+
+	WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
+
+	/* Reset cp */
+	WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
+	RREG32(GRBM_SOFT_RESET);
+	mdelay(15);
+	WREG32(GRBM_SOFT_RESET, 0);
+
+	WREG32(CP_ME_RAM_WADDR, 0);
+
+	fw_data = (const __be32 *)rdev->me_fw->data;
+	WREG32(CP_ME_RAM_WADDR, 0);
+	for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
+		WREG32(CP_ME_RAM_DATA,
+		       be32_to_cpup(fw_data++));
+
+	fw_data = (const __be32 *)rdev->pfp_fw->data;
+	WREG32(CP_PFP_UCODE_ADDR, 0);
+	for (i = 0; i < PFP_UCODE_SIZE; i++)
+		WREG32(CP_PFP_UCODE_DATA,
+		       be32_to_cpup(fw_data++));
+
+	WREG32(CP_PFP_UCODE_ADDR, 0);
+	WREG32(CP_ME_RAM_WADDR, 0);
+	WREG32(CP_ME_RAM_RADDR, 0);
+	return 0;
+}
+
+int r600_cp_start(struct radeon_device *rdev)
+{
+	int r;
+	uint32_t cp_me;
+
+	r = radeon_ring_lock(rdev, 7);
+	if (r) {
+		DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
+		return r;
+	}
+	radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
+	radeon_ring_write(rdev, 0x1);
+	if (rdev->family < CHIP_RV770) {
+		radeon_ring_write(rdev, 0x3);
+		radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
+	} else {
+		radeon_ring_write(rdev, 0x0);
+		radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
+	}
+	radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
+	radeon_ring_write(rdev, 0);
+	radeon_ring_write(rdev, 0);
+	radeon_ring_unlock_commit(rdev);
+
+	cp_me = 0xff;
+	WREG32(R_0086D8_CP_ME_CNTL, cp_me);
+	return 0;
+}
+
+int r600_cp_resume(struct radeon_device *rdev)
+{
+	u32 tmp;
+	u32 rb_bufsz;
+	int r;
+
+	/* Reset cp */
+	WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
+	RREG32(GRBM_SOFT_RESET);
+	mdelay(15);
+	WREG32(GRBM_SOFT_RESET, 0);
+
+	/* Set ring buffer size */
+	rb_bufsz = drm_order(rdev->cp.ring_size / 8);
+#ifdef __BIG_ENDIAN
+	WREG32(CP_RB_CNTL, BUF_SWAP_32BIT | RB_NO_UPDATE |
+		(drm_order(4096/8) << 8) | rb_bufsz);
+#else
+	WREG32(CP_RB_CNTL, RB_NO_UPDATE | (drm_order(4096/8) << 8) | rb_bufsz);
+#endif
+	WREG32(CP_SEM_WAIT_TIMER, 0x4);
+
+	/* Set the write pointer delay */
+	WREG32(CP_RB_WPTR_DELAY, 0);
+
+	/* Initialize the ring buffer's read and write pointers */
+	tmp = RREG32(CP_RB_CNTL);
+	WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
+	WREG32(CP_RB_RPTR_WR, 0);
+	WREG32(CP_RB_WPTR, 0);
+	WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
+	WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
+	mdelay(1);
+	WREG32(CP_RB_CNTL, tmp);
+
+	WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
+	WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
+
+	rdev->cp.rptr = RREG32(CP_RB_RPTR);
+	rdev->cp.wptr = RREG32(CP_RB_WPTR);
+
+	r600_cp_start(rdev);
+	rdev->cp.ready = true;
+	r = radeon_ring_test(rdev);
+	if (r) {
+		rdev->cp.ready = false;
+		return r;
+	}
+	return 0;
+}
+
+void r600_cp_commit(struct radeon_device *rdev)
+{
+	WREG32(CP_RB_WPTR, rdev->cp.wptr);
+	(void)RREG32(CP_RB_WPTR);
+}
+
+void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
+{
+	u32 rb_bufsz;
+
+	/* Align ring size */
+	rb_bufsz = drm_order(ring_size / 8);
+	ring_size = (1 << (rb_bufsz + 1)) * 4;
+	rdev->cp.ring_size = ring_size;
+	rdev->cp.align_mask = 16 - 1;
+}
+
+
+/*
+ * GPU scratch registers helpers function.
+ */
+void r600_scratch_init(struct radeon_device *rdev)
+{
+	int i;
+
+	rdev->scratch.num_reg = 7;
+	for (i = 0; i < rdev->scratch.num_reg; i++) {
+		rdev->scratch.free[i] = true;
+		rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
+	}
+}
+
+int r600_ring_test(struct radeon_device *rdev)
+{
+	uint32_t scratch;
+	uint32_t tmp = 0;
+	unsigned i;
+	int r;
+
+	r = radeon_scratch_get(rdev, &scratch);
+	if (r) {
+		DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
+		return r;
+	}
+	WREG32(scratch, 0xCAFEDEAD);
+	r = radeon_ring_lock(rdev, 3);
+	if (r) {
+		DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
+		radeon_scratch_free(rdev, scratch);
+		return r;
+	}
+	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+	radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
+	radeon_ring_write(rdev, 0xDEADBEEF);
+	radeon_ring_unlock_commit(rdev);
+	for (i = 0; i < rdev->usec_timeout; i++) {
+		tmp = RREG32(scratch);
+		if (tmp == 0xDEADBEEF)
+			break;
+		DRM_UDELAY(1);
+	}
+	if (i < rdev->usec_timeout) {
+		DRM_INFO("ring test succeeded in %d usecs\n", i);
+	} else {
+		DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
+			  scratch, tmp);
+		r = -EINVAL;
+	}
+	radeon_scratch_free(rdev, scratch);
+	return r;
+}
+
+/*
+ * Writeback
+ */
+int r600_wb_init(struct radeon_device *rdev)
+{
+	int r;
+
+	if (rdev->wb.wb_obj == NULL) {
+		r = radeon_object_create(rdev, NULL, 4096,
+					 true,
+					 RADEON_GEM_DOMAIN_GTT,
+					 false, &rdev->wb.wb_obj);
+		if (r) {
+			DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
+			return r;
+		}
+		r = radeon_object_pin(rdev->wb.wb_obj,
+				      RADEON_GEM_DOMAIN_GTT,
+				      &rdev->wb.gpu_addr);
+		if (r) {
+			DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
+			return r;
+		}
+		r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
+		if (r) {
+			DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
+			return r;
+		}
+	}
+	WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
+	WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
+	WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
+	WREG32(SCRATCH_UMSK, 0xff);
+	return 0;
+}
+
+void r600_wb_fini(struct radeon_device *rdev)
+{
+	if (rdev->wb.wb_obj) {
+		radeon_object_kunmap(rdev->wb.wb_obj);
+		radeon_object_unpin(rdev->wb.wb_obj);
+		radeon_object_unref(&rdev->wb.wb_obj);
+		rdev->wb.wb = NULL;
+		rdev->wb.wb_obj = NULL;
+	}
+}
+
+
+/*
+ * CS
+ */
+void r600_fence_ring_emit(struct radeon_device *rdev,
+			  struct radeon_fence *fence)
+{
+	/* Emit fence sequence & fire IRQ */
+	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+	radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
+	radeon_ring_write(rdev, fence->seq);
+}
+
+int r600_copy_dma(struct radeon_device *rdev,
+		  uint64_t src_offset,
+		  uint64_t dst_offset,
+		  unsigned num_pages,
+		  struct radeon_fence *fence)
+{
+	/* FIXME: implement */
+	return 0;
+}
+
+int r600_copy_blit(struct radeon_device *rdev,
+		   uint64_t src_offset, uint64_t dst_offset,
+		   unsigned num_pages, struct radeon_fence *fence)
+{
+	r600_blit_prepare_copy(rdev, num_pages * 4096);
+	r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * 4096);
+	r600_blit_done_copy(rdev, fence);
+	return 0;
+}
+
+int r600_irq_process(struct radeon_device *rdev)
+{
+	/* FIXME: implement */
+	return 0;
+}
+
+int r600_irq_set(struct radeon_device *rdev)
+{
+	/* FIXME: implement */
+	return 0;
+}
+
+int r600_set_surface_reg(struct radeon_device *rdev, int reg,
+			 uint32_t tiling_flags, uint32_t pitch,
+			 uint32_t offset, uint32_t obj_size)
+{
+	/* FIXME: implement */
+	return 0;
+}
+
+void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
+{
+	/* FIXME: implement */
+}
+
+
+bool r600_card_posted(struct radeon_device *rdev)
+{
+	uint32_t reg;
+
+	/* first check CRTCs */
+	reg = RREG32(D1CRTC_CONTROL) |
+		RREG32(D2CRTC_CONTROL);
+	if (reg & CRTC_EN)
+		return true;
+
+	/* then check MEM_SIZE, in case the crtcs are off */
+	if (RREG32(CONFIG_MEMSIZE))
+		return true;
+
+	return false;
+}
+
+int r600_resume(struct radeon_device *rdev)
+{
+	int r;
+
+	r600_gpu_reset(rdev);
+	r600_mc_resume(rdev);
+	r = r600_pcie_gart_enable(rdev);
+	if (r)
+		return r;
+	r600_gpu_init(rdev);
+	r = radeon_ring_init(rdev, rdev->cp.ring_size);
+	if (r)
+		return r;
+	r = r600_cp_load_microcode(rdev);
+	if (r)
+		return r;
+	r = r600_cp_resume(rdev);
+	if (r)
+		return r;
+	r = r600_wb_init(rdev);
+	if (r)
+		return r;
+	return 0;
+}
+
+int r600_suspend(struct radeon_device *rdev)
+{
+	/* FIXME: we should wait for ring to be empty */
+	r600_cp_stop(rdev);
+	return 0;
+}
+
+/* Plan is to move initialization in that function and use
+ * helper function so that radeon_device_init pretty much
+ * do nothing more than calling asic specific function. This
+ * should also allow to remove a bunch of callback function
+ * like vram_info.
+ */
+int r600_init(struct radeon_device *rdev)
 {
-	uint32_t r;
+	int r;
 
-	WREG32(R600_PCIE_PORT_INDEX, ((reg) & 0xff));
-	(void)RREG32(R600_PCIE_PORT_INDEX);
-	r = RREG32(R600_PCIE_PORT_DATA);
+	rdev->new_init_path = true;
+	r = radeon_dummy_page_init(rdev);
+	if (r)
+		return r;
+	if (r600_debugfs_mc_info_init(rdev)) {
+		DRM_ERROR("Failed to register debugfs file for mc !\n");
+	}
+	/* This don't do much */
+	r = radeon_gem_init(rdev);
+	if (r)
+		return r;
+	/* Read BIOS */
+	if (!radeon_get_bios(rdev)) {
+		if (ASIC_IS_AVIVO(rdev))
+			return -EINVAL;
+	}
+	/* Must be an ATOMBIOS */
+	if (!rdev->is_atom_bios)
+		return -EINVAL;
+	r = radeon_atombios_init(rdev);
+	if (r)
+		return r;
+	/* Post card if necessary */
+	if (!r600_card_posted(rdev) && rdev->bios) {
+		DRM_INFO("GPU not posted. posting now...\n");
+		atom_asic_init(rdev->mode_info.atom_context);
+	}
+	/* Initialize scratch registers */
+	r600_scratch_init(rdev);
+	/* Initialize surface registers */
+	radeon_surface_init(rdev);
+	r = radeon_clocks_init(rdev);
+	if (r)
+		return r;
+	/* Fence driver */
+	r = radeon_fence_driver_init(rdev);
+	if (r)
+		return r;
+	r = r600_mc_init(rdev);
+	if (r) {
+		if (rdev->flags & RADEON_IS_AGP) {
+			/* Retry with disabling AGP */
+			r600_fini(rdev);
+			rdev->flags &= ~RADEON_IS_AGP;
+			return r600_init(rdev);
+		}
+		return r;
+	}
+	/* Memory manager */
+	r = radeon_object_init(rdev);
+	if (r)
+		return r;
+	rdev->cp.ring_obj = NULL;
+	r600_ring_init(rdev, 1024 * 1024);
+
+	if (!rdev->me_fw || !rdev->pfp_fw) {
+		r = r600_cp_init_microcode(rdev);
+		if (r) {
+			DRM_ERROR("Failed to load firmware!\n");
+			return r;
+		}
+	}
+
+	r = r600_resume(rdev);
+	if (r) {
+		if (rdev->flags & RADEON_IS_AGP) {
+			/* Retry with disabling AGP */
+			r600_fini(rdev);
+			rdev->flags &= ~RADEON_IS_AGP;
+			return r600_init(rdev);
+		}
+		return r;
+	}
+	r = radeon_ib_pool_init(rdev);
+	if (r) {
+		DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
+		return r;
+	}
+	r = r600_blit_init(rdev);
+	if (r) {
+		DRM_ERROR("radeon: failled blitter (%d).\n", r);
+		return r;
+	}
+	r = radeon_ib_test(rdev);
+	if (r) {
+		DRM_ERROR("radeon: failled testing IB (%d).\n", r);
+			return r;
+	}
+	return 0;
+}
+
+void r600_fini(struct radeon_device *rdev)
+{
+	/* Suspend operations */
+	r600_suspend(rdev);
+
+	r600_blit_fini(rdev);
+	radeon_ring_fini(rdev);
+	r600_pcie_gart_disable(rdev);
+	radeon_gart_table_vram_free(rdev);
+	radeon_gart_fini(rdev);
+	radeon_gem_fini(rdev);
+	radeon_fence_driver_fini(rdev);
+	radeon_clocks_fini(rdev);
+#if __OS_HAS_AGP
+	if (rdev->flags & RADEON_IS_AGP)
+		radeon_agp_fini(rdev);
+#endif
+	radeon_object_fini(rdev);
+	if (rdev->is_atom_bios)
+		radeon_atombios_fini(rdev);
+	else
+		radeon_combios_fini(rdev);
+	kfree(rdev->bios);
+	rdev->bios = NULL;
+	radeon_dummy_page_fini(rdev);
+}
+
+
+/*
+ * CS stuff
+ */
+void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
+{
+	/* FIXME: implement */
+	radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
+	radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
+	radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
+	radeon_ring_write(rdev, ib->length_dw);
+}
+
+int r600_ib_test(struct radeon_device *rdev)
+{
+	struct radeon_ib *ib;
+	uint32_t scratch;
+	uint32_t tmp = 0;
+	unsigned i;
+	int r;
+
+	r = radeon_scratch_get(rdev, &scratch);
+	if (r) {
+		DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
+		return r;
+	}
+	WREG32(scratch, 0xCAFEDEAD);
+	r = radeon_ib_get(rdev, &ib);
+	if (r) {
+		DRM_ERROR("radeon: failed to get ib (%d).\n", r);
+		return r;
+	}
+	ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
+	ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
+	ib->ptr[2] = 0xDEADBEEF;
+	ib->ptr[3] = PACKET2(0);
+	ib->ptr[4] = PACKET2(0);
+	ib->ptr[5] = PACKET2(0);
+	ib->ptr[6] = PACKET2(0);
+	ib->ptr[7] = PACKET2(0);
+	ib->ptr[8] = PACKET2(0);
+	ib->ptr[9] = PACKET2(0);
+	ib->ptr[10] = PACKET2(0);
+	ib->ptr[11] = PACKET2(0);
+	ib->ptr[12] = PACKET2(0);
+	ib->ptr[13] = PACKET2(0);
+	ib->ptr[14] = PACKET2(0);
+	ib->ptr[15] = PACKET2(0);
+	ib->length_dw = 16;
+	r = radeon_ib_schedule(rdev, ib);
+	if (r) {
+		radeon_scratch_free(rdev, scratch);
+		radeon_ib_free(rdev, &ib);
+		DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
+		return r;
+	}
+	r = radeon_fence_wait(ib->fence, false);
+	if (r) {
+		DRM_ERROR("radeon: fence wait failed (%d).\n", r);
+		return r;
+	}
+	for (i = 0; i < rdev->usec_timeout; i++) {
+		tmp = RREG32(scratch);
+		if (tmp == 0xDEADBEEF)
+			break;
+		DRM_UDELAY(1);
+	}
+	if (i < rdev->usec_timeout) {
+		DRM_INFO("ib test succeeded in %u usecs\n", i);
+	} else {
+		DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
+			  scratch, tmp);
+		r = -EINVAL;
+	}
+	radeon_scratch_free(rdev, scratch);
+	radeon_ib_free(rdev, &ib);
 	return r;
 }
 
-void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
+
+
+
+/*
+ * Debugfs info
+ */
+#if defined(CONFIG_DEBUG_FS)
+
+static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
 {
-	WREG32(R600_PCIE_PORT_INDEX, ((reg) & 0xff));
-	(void)RREG32(R600_PCIE_PORT_INDEX);
-	WREG32(R600_PCIE_PORT_DATA, (v));
-	(void)RREG32(R600_PCIE_PORT_DATA);
+	struct drm_info_node *node = (struct drm_info_node *) m->private;
+	struct drm_device *dev = node->minor->dev;
+	struct radeon_device *rdev = dev->dev_private;
+	uint32_t rdp, wdp;
+	unsigned count, i, j;
+
+	radeon_ring_free_size(rdev);
+	rdp = RREG32(CP_RB_RPTR);
+	wdp = RREG32(CP_RB_WPTR);
+	count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
+	seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
+	seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
+	seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
+	seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
+	seq_printf(m, "%u dwords in ring\n", count);
+	for (j = 0; j <= count; j++) {
+		i = (rdp + j) & rdev->cp.ptr_mask;
+		seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
+	}
+	return 0;
+}
+
+static int r600_debugfs_mc_info(struct seq_file *m, void *data)
+{
+	struct drm_info_node *node = (struct drm_info_node *) m->private;
+	struct drm_device *dev = node->minor->dev;
+	struct radeon_device *rdev = dev->dev_private;
+
+	DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
+	DREG32_SYS(m, rdev, VM_L2_STATUS);
+	return 0;
+}
+
+static struct drm_info_list r600_mc_info_list[] = {
+	{"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
+	{"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
+};
+#endif
+
+int r600_debugfs_mc_info_init(struct radeon_device *rdev)
+{
+#if defined(CONFIG_DEBUG_FS)
+	return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
+#else
+	return 0;
+#endif
 }
diff --git a/drivers/gpu/drm/radeon/r600_blit.c b/drivers/gpu/drm/radeon/r600_blit.c
new file mode 100644
index 00000000000..c51402e9249
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r600_blit.c
@@ -0,0 +1,855 @@
+/*
+ * Copyright 2009 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *     Alex Deucher <alexander.deucher@amd.com>
+ */
+#include "drmP.h"
+#include "drm.h"
+#include "radeon_drm.h"
+#include "radeon_drv.h"
+
+#include "r600_blit_shaders.h"
+
+#define DI_PT_RECTLIST        0x11
+#define DI_INDEX_SIZE_16_BIT  0x0
+#define DI_SRC_SEL_AUTO_INDEX 0x2
+
+#define FMT_8                 0x1
+#define FMT_5_6_5             0x8
+#define FMT_8_8_8_8           0x1a
+#define COLOR_8               0x1
+#define COLOR_5_6_5           0x8
+#define COLOR_8_8_8_8         0x1a
+
+static inline void
+set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64 gpu_addr)
+{
+	u32 cb_color_info;
+	int pitch, slice;
+	RING_LOCALS;
+	DRM_DEBUG("\n");
+
+	h = (h + 7) & ~7;
+	if (h < 8)
+		h = 8;
+
+	cb_color_info = ((format << 2) | (1 << 27));
+	pitch = (w / 8) - 1;
+	slice = ((w * h) / 64) - 1;
+
+	if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600) &&
+	    ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) {
+		BEGIN_RING(21 + 2);
+		OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+		OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+		OUT_RING(gpu_addr >> 8);
+		OUT_RING(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
+		OUT_RING(2 << 0);
+	} else {
+		BEGIN_RING(21);
+		OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+		OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+		OUT_RING(gpu_addr >> 8);
+	}
+
+	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+	OUT_RING((R600_CB_COLOR0_SIZE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+	OUT_RING((pitch << 0) | (slice << 10));
+
+	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+	OUT_RING((R600_CB_COLOR0_VIEW - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+	OUT_RING(0);
+
+	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+	OUT_RING((R600_CB_COLOR0_INFO - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+	OUT_RING(cb_color_info);
+
+	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+	OUT_RING((R600_CB_COLOR0_TILE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+	OUT_RING(0);
+
+	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+	OUT_RING((R600_CB_COLOR0_FRAG - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+	OUT_RING(0);
+
+	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+	OUT_RING((R600_CB_COLOR0_MASK - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+	OUT_RING(0);
+
+	ADVANCE_RING();
+}
+
+static inline void
+cp_set_surface_sync(drm_radeon_private_t *dev_priv,
+		    u32 sync_type, u32 size, u64 mc_addr)
+{
+	u32 cp_coher_size;
+	RING_LOCALS;
+	DRM_DEBUG("\n");
+
+	if (size == 0xffffffff)
+		cp_coher_size = 0xffffffff;
+	else
+		cp_coher_size = ((size + 255) >> 8);
+
+	BEGIN_RING(5);
+	OUT_RING(CP_PACKET3(R600_IT_SURFACE_SYNC, 3));
+	OUT_RING(sync_type);
+	OUT_RING(cp_coher_size);
+	OUT_RING((mc_addr >> 8));
+	OUT_RING(10); /* poll interval */
+	ADVANCE_RING();
+}
+
+static inline void
+set_shaders(struct drm_device *dev)
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	u64 gpu_addr;
+	int shader_size, i;
+	u32 *vs, *ps;
+	uint32_t sq_pgm_resources;
+	RING_LOCALS;
+	DRM_DEBUG("\n");
+
+	/* load shaders */
+	vs = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset);
+	ps = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset + 256);
+
+	shader_size = r6xx_vs_size;
+	for (i = 0; i < shader_size; i++)
+		vs[i] = r6xx_vs[i];
+	shader_size = r6xx_ps_size;
+	for (i = 0; i < shader_size; i++)
+		ps[i] = r6xx_ps[i];
+
+	dev_priv->blit_vb->used = 512;
+
+	gpu_addr = dev_priv->gart_buffers_offset + dev_priv->blit_vb->offset;
+
+	/* setup shader regs */
+	sq_pgm_resources = (1 << 0);
+
+	BEGIN_RING(9 + 12);
+	/* VS */
+	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+	OUT_RING((R600_SQ_PGM_START_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+	OUT_RING(gpu_addr >> 8);
+
+	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+	OUT_RING((R600_SQ_PGM_RESOURCES_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+	OUT_RING(sq_pgm_resources);
+
+	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+	OUT_RING((R600_SQ_PGM_CF_OFFSET_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+	OUT_RING(0);
+
+	/* PS */
+	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+	OUT_RING((R600_SQ_PGM_START_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+	OUT_RING((gpu_addr + 256) >> 8);
+
+	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+	OUT_RING((R600_SQ_PGM_RESOURCES_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+	OUT_RING(sq_pgm_resources | (1 << 28));
+
+	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+	OUT_RING((R600_SQ_PGM_EXPORTS_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+	OUT_RING(2);
+
+	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
+	OUT_RING((R600_SQ_PGM_CF_OFFSET_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+	OUT_RING(0);
+	ADVANCE_RING();
+
+	cp_set_surface_sync(dev_priv,
+			    R600_SH_ACTION_ENA, 512, gpu_addr);
+}
+
+static inline void
+set_vtx_resource(drm_radeon_private_t *dev_priv, u64 gpu_addr)
+{
+	uint32_t sq_vtx_constant_word2;
+	RING_LOCALS;
+	DRM_DEBUG("\n");
+
+	sq_vtx_constant_word2 = (((gpu_addr >> 32) & 0xff) | (16 << 8));
+
+	BEGIN_RING(9);
+	OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
+	OUT_RING(0x460);
+	OUT_RING(gpu_addr & 0xffffffff);
+	OUT_RING(48 - 1);
+	OUT_RING(sq_vtx_constant_word2);
+	OUT_RING(1 << 0);
+	OUT_RING(0);
+	OUT_RING(0);
+	OUT_RING(R600_SQ_TEX_VTX_VALID_BUFFER << 30);
+	ADVANCE_RING();
+
+	if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
+	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
+	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
+	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) ||
+	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710))
+		cp_set_surface_sync(dev_priv,
+				    R600_TC_ACTION_ENA, 48, gpu_addr);
+	else
+		cp_set_surface_sync(dev_priv,
+				    R600_VC_ACTION_ENA, 48, gpu_addr);
+}
+
+static inline void
+set_tex_resource(drm_radeon_private_t *dev_priv,
+		 int format, int w, int h, int pitch, u64 gpu_addr)
+{
+	uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
+	RING_LOCALS;
+	DRM_DEBUG("\n");
+
+	if (h < 1)
+		h = 1;
+
+	sq_tex_resource_word0 = (1 << 0);
+	sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) |
+				  ((w - 1) << 19));
+
+	sq_tex_resource_word1 = (format << 26);
+	sq_tex_resource_word1 |= ((h - 1) << 0);
+
+	sq_tex_resource_word4 = ((1 << 14) |
+				 (0 << 16) |
+				 (1 << 19) |
+				 (2 << 22) |
+				 (3 << 25));
+
+	BEGIN_RING(9);
+	OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
+	OUT_RING(0);
+	OUT_RING(sq_tex_resource_word0);
+	OUT_RING(sq_tex_resource_word1);
+	OUT_RING(gpu_addr >> 8);
+	OUT_RING(gpu_addr >> 8);
+	OUT_RING(sq_tex_resource_word4);
+	OUT_RING(0);
+	OUT_RING(R600_SQ_TEX_VTX_VALID_TEXTURE << 30);
+	ADVANCE_RING();
+
+}
+
+static inline void
+set_scissors(drm_radeon_private_t *dev_priv, int x1, int y1, int x2, int y2)
+{
+	RING_LOCALS;
+	DRM_DEBUG("\n");
+
+	BEGIN_RING(12);
+	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
+	OUT_RING((R600_PA_SC_SCREEN_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+	OUT_RING((x1 << 0) | (y1 << 16));
+	OUT_RING((x2 << 0) | (y2 << 16));
+
+	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
+	OUT_RING((R600_PA_SC_GENERIC_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+	OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));
+	OUT_RING((x2 << 0) | (y2 << 16));
+
+	OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
+	OUT_RING((R600_PA_SC_WINDOW_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
+	OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));
+	OUT_RING((x2 << 0) | (y2 << 16));
+	ADVANCE_RING();
+}
+
+static inline void
+draw_auto(drm_radeon_private_t *dev_priv)
+{
+	RING_LOCALS;
+	DRM_DEBUG("\n");
+
+	BEGIN_RING(10);
+	OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
+	OUT_RING((R600_VGT_PRIMITIVE_TYPE - R600_SET_CONFIG_REG_OFFSET) >> 2);
+	OUT_RING(DI_PT_RECTLIST);
+
+	OUT_RING(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
+	OUT_RING(DI_INDEX_SIZE_16_BIT);
+
+	OUT_RING(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
+	OUT_RING(1);
+
+	OUT_RING(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
+	OUT_RING(3);
+	OUT_RING(DI_SRC_SEL_AUTO_INDEX);
+
+	ADVANCE_RING();
+	COMMIT_RING();
+}
+
+static inline void
+set_default_state(drm_radeon_private_t *dev_priv)
+{
+	int default_state_dw, i;
+	u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
+	u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
+	int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
+	int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
+	int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
+	RING_LOCALS;
+
+	switch ((dev_priv->flags & RADEON_FAMILY_MASK)) {
+	case CHIP_R600:
+		num_ps_gprs = 192;
+		num_vs_gprs = 56;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 136;
+		num_vs_threads = 48;
+		num_gs_threads = 4;
+		num_es_threads = 4;
+		num_ps_stack_entries = 128;
+		num_vs_stack_entries = 128;
+		num_gs_stack_entries = 0;
+		num_es_stack_entries = 0;
+		break;
+	case CHIP_RV630:
+	case CHIP_RV635:
+		num_ps_gprs = 84;
+		num_vs_gprs = 36;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 144;
+		num_vs_threads = 40;
+		num_gs_threads = 4;
+		num_es_threads = 4;
+		num_ps_stack_entries = 40;
+		num_vs_stack_entries = 40;
+		num_gs_stack_entries = 32;
+		num_es_stack_entries = 16;
+		break;
+	case CHIP_RV610:
+	case CHIP_RV620:
+	case CHIP_RS780:
+	case CHIP_RS880:
+	default:
+		num_ps_gprs = 84;
+		num_vs_gprs = 36;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 136;
+		num_vs_threads = 48;
+		num_gs_threads = 4;
+		num_es_threads = 4;
+		num_ps_stack_entries = 40;
+		num_vs_stack_entries = 40;
+		num_gs_stack_entries = 32;
+		num_es_stack_entries = 16;
+		break;
+	case CHIP_RV670:
+		num_ps_gprs = 144;
+		num_vs_gprs = 40;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 136;
+		num_vs_threads = 48;
+		num_gs_threads = 4;
+		num_es_threads = 4;
+		num_ps_stack_entries = 40;
+		num_vs_stack_entries = 40;
+		num_gs_stack_entries = 32;
+		num_es_stack_entries = 16;
+		break;
+	case CHIP_RV770:
+		num_ps_gprs = 192;
+		num_vs_gprs = 56;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 188;
+		num_vs_threads = 60;
+		num_gs_threads = 0;
+		num_es_threads = 0;
+		num_ps_stack_entries = 256;
+		num_vs_stack_entries = 256;
+		num_gs_stack_entries = 0;
+		num_es_stack_entries = 0;
+		break;
+	case CHIP_RV730:
+	case CHIP_RV740:
+		num_ps_gprs = 84;
+		num_vs_gprs = 36;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 188;
+		num_vs_threads = 60;
+		num_gs_threads = 0;
+		num_es_threads = 0;
+		num_ps_stack_entries = 128;
+		num_vs_stack_entries = 128;
+		num_gs_stack_entries = 0;
+		num_es_stack_entries = 0;
+		break;
+	case CHIP_RV710:
+		num_ps_gprs = 192;
+		num_vs_gprs = 56;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 144;
+		num_vs_threads = 48;
+		num_gs_threads = 0;
+		num_es_threads = 0;
+		num_ps_stack_entries = 128;
+		num_vs_stack_entries = 128;
+		num_gs_stack_entries = 0;
+		num_es_stack_entries = 0;
+		break;
+	}
+
+	if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
+	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
+	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
+	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) ||
+	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710))
+		sq_config = 0;
+	else
+		sq_config = R600_VC_ENABLE;
+
+	sq_config |= (R600_DX9_CONSTS |
+		      R600_ALU_INST_PREFER_VECTOR |
+		      R600_PS_PRIO(0) |
+		      R600_VS_PRIO(1) |
+		      R600_GS_PRIO(2) |
+		      R600_ES_PRIO(3));
+
+	sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(num_ps_gprs) |
+				  R600_NUM_VS_GPRS(num_vs_gprs) |
+				  R600_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
+	sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(num_gs_gprs) |
+				  R600_NUM_ES_GPRS(num_es_gprs));
+	sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(num_ps_threads) |
+				   R600_NUM_VS_THREADS(num_vs_threads) |
+				   R600_NUM_GS_THREADS(num_gs_threads) |
+				   R600_NUM_ES_THREADS(num_es_threads));
+	sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
+				    R600_NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
+	sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
+				    R600_NUM_ES_STACK_ENTRIES(num_es_stack_entries));
+
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
+		default_state_dw = r7xx_default_size * 4;
+		BEGIN_RING(default_state_dw + 10);
+		for (i = 0; i < default_state_dw; i++)
+			OUT_RING(r7xx_default_state[i]);
+	} else {
+		default_state_dw = r6xx_default_size * 4;
+		BEGIN_RING(default_state_dw + 10);
+		for (i = 0; i < default_state_dw; i++)
+			OUT_RING(r6xx_default_state[i]);
+	}
+	OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
+	OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
+	/* SQ config */
+	OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 6));
+	OUT_RING((R600_SQ_CONFIG - R600_SET_CONFIG_REG_OFFSET) >> 2);
+	OUT_RING(sq_config);
+	OUT_RING(sq_gpr_resource_mgmt_1);
+	OUT_RING(sq_gpr_resource_mgmt_2);
+	OUT_RING(sq_thread_resource_mgmt);
+	OUT_RING(sq_stack_resource_mgmt_1);
+	OUT_RING(sq_stack_resource_mgmt_2);
+	ADVANCE_RING();
+}
+
+static inline uint32_t i2f(uint32_t input)
+{
+	u32 result, i, exponent, fraction;
+
+	if ((input & 0x3fff) == 0)
+		result = 0; /* 0 is a special case */
+	else {
+		exponent = 140; /* exponent biased by 127; */
+		fraction = (input & 0x3fff) << 10; /* cheat and only
+						      handle numbers below 2^^15 */
+		for (i = 0; i < 14; i++) {
+			if (fraction & 0x800000)
+				break;
+			else {
+				fraction = fraction << 1; /* keep
+							     shifting left until top bit = 1 */
+				exponent = exponent - 1;
+			}
+		}
+		result = exponent << 23 | (fraction & 0x7fffff); /* mask
+								    off top bit; assumed 1 */
+	}
+	return result;
+}
+
+
+int r600_nomm_get_vb(struct drm_device *dev)
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	dev_priv->blit_vb = radeon_freelist_get(dev);
+	if (!dev_priv->blit_vb) {
+		DRM_ERROR("Unable to allocate vertex buffer for blit\n");
+		return -EAGAIN;
+	}
+	return 0;
+}
+
+void r600_nomm_put_vb(struct drm_device *dev)
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+
+	dev_priv->blit_vb->used = 0;
+	radeon_cp_discard_buffer(dev, dev_priv->blit_vb->file_priv->master, dev_priv->blit_vb);
+}
+
+void *r600_nomm_get_vb_ptr(struct drm_device *dev)
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	return (((char *)dev->agp_buffer_map->handle +
+		 dev_priv->blit_vb->offset + dev_priv->blit_vb->used));
+}
+
+int
+r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv)
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	DRM_DEBUG("\n");
+
+	r600_nomm_get_vb(dev);
+
+	dev_priv->blit_vb->file_priv = file_priv;
+
+	set_default_state(dev_priv);
+	set_shaders(dev);
+
+	return 0;
+}
+
+
+void
+r600_done_blit_copy(struct drm_device *dev)
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	RING_LOCALS;
+	DRM_DEBUG("\n");
+
+	BEGIN_RING(5);
+	OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
+	OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
+	/* wait for 3D idle clean */
+	OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
+	OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
+	OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
+
+	ADVANCE_RING();
+	COMMIT_RING();
+
+	r600_nomm_put_vb(dev);
+}
+
+void
+r600_blit_copy(struct drm_device *dev,
+	       uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
+	       int size_bytes)
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	int max_bytes;
+	u64 vb_addr;
+	u32 *vb;
+
+	vb = r600_nomm_get_vb_ptr(dev);
+
+	if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
+		max_bytes = 8192;
+
+		while (size_bytes) {
+			int cur_size = size_bytes;
+			int src_x = src_gpu_addr & 255;
+			int dst_x = dst_gpu_addr & 255;
+			int h = 1;
+			src_gpu_addr = src_gpu_addr & ~255;
+			dst_gpu_addr = dst_gpu_addr & ~255;
+
+			if (!src_x && !dst_x) {
+				h = (cur_size / max_bytes);
+				if (h > 8192)
+					h = 8192;
+				if (h == 0)
+					h = 1;
+				else
+					cur_size = max_bytes;
+			} else {
+				if (cur_size > max_bytes)
+					cur_size = max_bytes;
+				if (cur_size > (max_bytes - dst_x))
+					cur_size = (max_bytes - dst_x);
+				if (cur_size > (max_bytes - src_x))
+					cur_size = (max_bytes - src_x);
+			}
+
+			if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
+
+				r600_nomm_put_vb(dev);
+				r600_nomm_get_vb(dev);
+				if (!dev_priv->blit_vb)
+					return;
+				set_shaders(dev);
+				vb = r600_nomm_get_vb_ptr(dev);
+			}
+
+			vb[0] = i2f(dst_x);
+			vb[1] = 0;
+			vb[2] = i2f(src_x);
+			vb[3] = 0;
+
+			vb[4] = i2f(dst_x);
+			vb[5] = i2f(h);
+			vb[6] = i2f(src_x);
+			vb[7] = i2f(h);
+
+			vb[8] = i2f(dst_x + cur_size);
+			vb[9] = i2f(h);
+			vb[10] = i2f(src_x + cur_size);
+			vb[11] = i2f(h);
+
+			/* src */
+			set_tex_resource(dev_priv, FMT_8,
+					 src_x + cur_size, h, src_x + cur_size,
+					 src_gpu_addr);
+
+			cp_set_surface_sync(dev_priv,
+					    R600_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
+
+			/* dst */
+			set_render_target(dev_priv, COLOR_8,
+					  dst_x + cur_size, h,
+					  dst_gpu_addr);
+
+			/* scissors */
+			set_scissors(dev_priv, dst_x, 0, dst_x + cur_size, h);
+
+			/* Vertex buffer setup */
+			vb_addr = dev_priv->gart_buffers_offset +
+				dev_priv->blit_vb->offset +
+				dev_priv->blit_vb->used;
+			set_vtx_resource(dev_priv, vb_addr);
+
+			/* draw */
+			draw_auto(dev_priv);
+
+			cp_set_surface_sync(dev_priv,
+					    R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
+					    cur_size * h, dst_gpu_addr);
+
+			vb += 12;
+			dev_priv->blit_vb->used += 12 * 4;
+
+			src_gpu_addr += cur_size * h;
+			dst_gpu_addr += cur_size * h;
+			size_bytes -= cur_size * h;
+		}
+	} else {
+		max_bytes = 8192 * 4;
+
+		while (size_bytes) {
+			int cur_size = size_bytes;
+			int src_x = (src_gpu_addr & 255);
+			int dst_x = (dst_gpu_addr & 255);
+			int h = 1;
+			src_gpu_addr = src_gpu_addr & ~255;
+			dst_gpu_addr = dst_gpu_addr & ~255;
+
+			if (!src_x && !dst_x) {
+				h = (cur_size / max_bytes);
+				if (h > 8192)
+					h = 8192;
+				if (h == 0)
+					h = 1;
+				else
+					cur_size = max_bytes;
+			} else {
+				if (cur_size > max_bytes)
+					cur_size = max_bytes;
+				if (cur_size > (max_bytes - dst_x))
+					cur_size = (max_bytes - dst_x);
+				if (cur_size > (max_bytes - src_x))
+					cur_size = (max_bytes - src_x);
+			}
+
+			if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
+				r600_nomm_put_vb(dev);
+				r600_nomm_get_vb(dev);
+				if (!dev_priv->blit_vb)
+					return;
+
+				set_shaders(dev);
+				vb = r600_nomm_get_vb_ptr(dev);
+			}
+
+			vb[0] = i2f(dst_x / 4);
+			vb[1] = 0;
+			vb[2] = i2f(src_x / 4);
+			vb[3] = 0;
+
+			vb[4] = i2f(dst_x / 4);
+			vb[5] = i2f(h);
+			vb[6] = i2f(src_x / 4);
+			vb[7] = i2f(h);
+
+			vb[8] = i2f((dst_x + cur_size) / 4);
+			vb[9] = i2f(h);
+			vb[10] = i2f((src_x + cur_size) / 4);
+			vb[11] = i2f(h);
+
+			/* src */
+			set_tex_resource(dev_priv, FMT_8_8_8_8,
+					 (src_x + cur_size) / 4,
+					 h, (src_x + cur_size) / 4,
+					 src_gpu_addr);
+
+			cp_set_surface_sync(dev_priv,
+					    R600_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
+
+			/* dst */
+			set_render_target(dev_priv, COLOR_8_8_8_8,
+					  dst_x + cur_size, h,
+					  dst_gpu_addr);
+
+			/* scissors */
+			set_scissors(dev_priv, (dst_x / 4), 0, (dst_x + cur_size / 4), h);
+
+			/* Vertex buffer setup */
+			vb_addr = dev_priv->gart_buffers_offset +
+				dev_priv->blit_vb->offset +
+				dev_priv->blit_vb->used;
+			set_vtx_resource(dev_priv, vb_addr);
+
+			/* draw */
+			draw_auto(dev_priv);
+
+			cp_set_surface_sync(dev_priv,
+					    R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
+					    cur_size * h, dst_gpu_addr);
+
+			vb += 12;
+			dev_priv->blit_vb->used += 12 * 4;
+
+			src_gpu_addr += cur_size * h;
+			dst_gpu_addr += cur_size * h;
+			size_bytes -= cur_size * h;
+		}
+	}
+}
+
+void
+r600_blit_swap(struct drm_device *dev,
+	       uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
+	       int sx, int sy, int dx, int dy,
+	       int w, int h, int src_pitch, int dst_pitch, int cpp)
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	int cb_format, tex_format;
+	u64 vb_addr;
+	u32 *vb;
+
+	vb = (u32 *) ((char *)dev->agp_buffer_map->handle +
+		      dev_priv->blit_vb->offset + dev_priv->blit_vb->used);
+
+	if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
+
+		r600_nomm_put_vb(dev);
+		r600_nomm_get_vb(dev);
+		if (!dev_priv->blit_vb)
+			return;
+
+		set_shaders(dev);
+		vb = r600_nomm_get_vb_ptr(dev);
+	}
+
+	if (cpp == 4) {
+		cb_format = COLOR_8_8_8_8;
+		tex_format = FMT_8_8_8_8;
+	} else if (cpp == 2) {
+		cb_format = COLOR_5_6_5;
+		tex_format = FMT_5_6_5;
+	} else {
+		cb_format = COLOR_8;
+		tex_format = FMT_8;
+	}
+
+	vb[0] = i2f(dx);
+	vb[1] = i2f(dy);
+	vb[2] = i2f(sx);
+	vb[3] = i2f(sy);
+
+	vb[4] = i2f(dx);
+	vb[5] = i2f(dy + h);
+	vb[6] = i2f(sx);
+	vb[7] = i2f(sy + h);
+
+	vb[8] = i2f(dx + w);
+	vb[9] = i2f(dy + h);
+	vb[10] = i2f(sx + w);
+	vb[11] = i2f(sy + h);
+
+	/* src */
+	set_tex_resource(dev_priv, tex_format,
+			 src_pitch / cpp,
+			 sy + h, src_pitch / cpp,
+			 src_gpu_addr);
+
+	cp_set_surface_sync(dev_priv,
+			    R600_TC_ACTION_ENA, (src_pitch * (sy + h)), src_gpu_addr);
+
+	/* dst */
+	set_render_target(dev_priv, cb_format,
+			  dst_pitch / cpp, dy + h,
+			  dst_gpu_addr);
+
+	/* scissors */
+	set_scissors(dev_priv, dx, dy, dx + w, dy + h);
+
+	/* Vertex buffer setup */
+	vb_addr = dev_priv->gart_buffers_offset +
+		dev_priv->blit_vb->offset +
+		dev_priv->blit_vb->used;
+	set_vtx_resource(dev_priv, vb_addr);
+
+	/* draw */
+	draw_auto(dev_priv);
+
+	cp_set_surface_sync(dev_priv,
+			    R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
+			    dst_pitch * (dy + h), dst_gpu_addr);
+
+	dev_priv->blit_vb->used += 12 * 4;
+}
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
new file mode 100644
index 00000000000..5755647e688
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -0,0 +1,777 @@
+#include "drmP.h"
+#include "drm.h"
+#include "radeon_drm.h"
+#include "radeon.h"
+
+#include "r600d.h"
+#include "r600_blit_shaders.h"
+
+#define DI_PT_RECTLIST        0x11
+#define DI_INDEX_SIZE_16_BIT  0x0
+#define DI_SRC_SEL_AUTO_INDEX 0x2
+
+#define FMT_8                 0x1
+#define FMT_5_6_5             0x8
+#define FMT_8_8_8_8           0x1a
+#define COLOR_8               0x1
+#define COLOR_5_6_5           0x8
+#define COLOR_8_8_8_8         0x1a
+
+/* emits 21 on rv770+, 23 on r600 */
+static void
+set_render_target(struct radeon_device *rdev, int format,
+		  int w, int h, u64 gpu_addr)
+{
+	u32 cb_color_info;
+	int pitch, slice;
+
+	h = (h + 7) & ~7;
+	if (h < 8)
+		h = 8;
+
+	cb_color_info = ((format << 2) | (1 << 27));
+	pitch = (w / 8) - 1;
+	slice = ((w * h) / 64) - 1;
+
+	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+	radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+	radeon_ring_write(rdev, gpu_addr >> 8);
+
+	if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
+		radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
+		radeon_ring_write(rdev, 2 << 0);
+	}
+
+	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+	radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+	radeon_ring_write(rdev, (pitch << 0) | (slice << 10));
+
+	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+	radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+	radeon_ring_write(rdev, 0);
+
+	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+	radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+	radeon_ring_write(rdev, cb_color_info);
+
+	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+	radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+	radeon_ring_write(rdev, 0);
+
+	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+	radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+	radeon_ring_write(rdev, 0);
+
+	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+	radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+	radeon_ring_write(rdev, 0);
+}
+
+/* emits 5dw */
+static void
+cp_set_surface_sync(struct radeon_device *rdev,
+		    u32 sync_type, u32 size,
+		    u64 mc_addr)
+{
+	u32 cp_coher_size;
+
+	if (size == 0xffffffff)
+		cp_coher_size = 0xffffffff;
+	else
+		cp_coher_size = ((size + 255) >> 8);
+
+	radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
+	radeon_ring_write(rdev, sync_type);
+	radeon_ring_write(rdev, cp_coher_size);
+	radeon_ring_write(rdev, mc_addr >> 8);
+	radeon_ring_write(rdev, 10); /* poll interval */
+}
+
+/* emits 21dw + 1 surface sync = 26dw */
+static void
+set_shaders(struct radeon_device *rdev)
+{
+	u64 gpu_addr;
+	u32 sq_pgm_resources;
+
+	/* setup shader regs */
+	sq_pgm_resources = (1 << 0);
+
+	/* VS */
+	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
+	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+	radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+	radeon_ring_write(rdev, gpu_addr >> 8);
+
+	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+	radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+	radeon_ring_write(rdev, sq_pgm_resources);
+
+	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+	radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+	radeon_ring_write(rdev, 0);
+
+	/* PS */
+	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
+	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+	radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+	radeon_ring_write(rdev, gpu_addr >> 8);
+
+	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+	radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+	radeon_ring_write(rdev, sq_pgm_resources | (1 << 28));
+
+	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+	radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+	radeon_ring_write(rdev, 2);
+
+	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+	radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+	radeon_ring_write(rdev, 0);
+
+	cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
+}
+
+/* emits 9 + 1 sync (5) = 14*/
+static void
+set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
+{
+	u32 sq_vtx_constant_word2;
+
+	sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8));
+
+	radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
+	radeon_ring_write(rdev, 0x460);
+	radeon_ring_write(rdev, gpu_addr & 0xffffffff);
+	radeon_ring_write(rdev, 48 - 1);
+	radeon_ring_write(rdev, sq_vtx_constant_word2);
+	radeon_ring_write(rdev, 1 << 0);
+	radeon_ring_write(rdev, 0);
+	radeon_ring_write(rdev, 0);
+	radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
+
+	if ((rdev->family == CHIP_RV610) ||
+	    (rdev->family == CHIP_RV620) ||
+	    (rdev->family == CHIP_RS780) ||
+	    (rdev->family == CHIP_RS880) ||
+	    (rdev->family == CHIP_RV710))
+		cp_set_surface_sync(rdev,
+				    PACKET3_TC_ACTION_ENA, 48, gpu_addr);
+	else
+		cp_set_surface_sync(rdev,
+				    PACKET3_VC_ACTION_ENA, 48, gpu_addr);
+}
+
+/* emits 9 */
+static void
+set_tex_resource(struct radeon_device *rdev,
+		 int format, int w, int h, int pitch,
+		 u64 gpu_addr)
+{
+	uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
+
+	if (h < 1)
+		h = 1;
+
+	sq_tex_resource_word0 = (1 << 0);
+	sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) |
+				  ((w - 1) << 19));
+
+	sq_tex_resource_word1 = (format << 26);
+	sq_tex_resource_word1 |= ((h - 1) << 0);
+
+	sq_tex_resource_word4 = ((1 << 14) |
+				 (0 << 16) |
+				 (1 << 19) |
+				 (2 << 22) |
+				 (3 << 25));
+
+	radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
+	radeon_ring_write(rdev, 0);
+	radeon_ring_write(rdev, sq_tex_resource_word0);
+	radeon_ring_write(rdev, sq_tex_resource_word1);
+	radeon_ring_write(rdev, gpu_addr >> 8);
+	radeon_ring_write(rdev, gpu_addr >> 8);
+	radeon_ring_write(rdev, sq_tex_resource_word4);
+	radeon_ring_write(rdev, 0);
+	radeon_ring_write(rdev, SQ_TEX_VTX_VALID_TEXTURE << 30);
+}
+
+/* emits 12 */
+static void
+set_scissors(struct radeon_device *rdev, int x1, int y1,
+	     int x2, int y2)
+{
+	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
+	radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+	radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
+	radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
+
+	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
+	radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+	radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
+	radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
+
+	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
+	radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+	radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
+	radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
+}
+
+/* emits 10 */
+static void
+draw_auto(struct radeon_device *rdev)
+{
+	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+	radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
+	radeon_ring_write(rdev, DI_PT_RECTLIST);
+
+	radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0));
+	radeon_ring_write(rdev, DI_INDEX_SIZE_16_BIT);
+
+	radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0));
+	radeon_ring_write(rdev, 1);
+
+	radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
+	radeon_ring_write(rdev, 3);
+	radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);
+
+}
+
+/* emits 14 */
+static void
+set_default_state(struct radeon_device *rdev)
+{
+	u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
+	u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
+	int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
+	int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
+	int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
+	u64 gpu_addr;
+
+	switch (rdev->family) {
+	case CHIP_R600:
+		num_ps_gprs = 192;
+		num_vs_gprs = 56;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 136;
+		num_vs_threads = 48;
+		num_gs_threads = 4;
+		num_es_threads = 4;
+		num_ps_stack_entries = 128;
+		num_vs_stack_entries = 128;
+		num_gs_stack_entries = 0;
+		num_es_stack_entries = 0;
+		break;
+	case CHIP_RV630:
+	case CHIP_RV635:
+		num_ps_gprs = 84;
+		num_vs_gprs = 36;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 144;
+		num_vs_threads = 40;
+		num_gs_threads = 4;
+		num_es_threads = 4;
+		num_ps_stack_entries = 40;
+		num_vs_stack_entries = 40;
+		num_gs_stack_entries = 32;
+		num_es_stack_entries = 16;
+		break;
+	case CHIP_RV610:
+	case CHIP_RV620:
+	case CHIP_RS780:
+	case CHIP_RS880:
+	default:
+		num_ps_gprs = 84;
+		num_vs_gprs = 36;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 136;
+		num_vs_threads = 48;
+		num_gs_threads = 4;
+		num_es_threads = 4;
+		num_ps_stack_entries = 40;
+		num_vs_stack_entries = 40;
+		num_gs_stack_entries = 32;
+		num_es_stack_entries = 16;
+		break;
+	case CHIP_RV670:
+		num_ps_gprs = 144;
+		num_vs_gprs = 40;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 136;
+		num_vs_threads = 48;
+		num_gs_threads = 4;
+		num_es_threads = 4;
+		num_ps_stack_entries = 40;
+		num_vs_stack_entries = 40;
+		num_gs_stack_entries = 32;
+		num_es_stack_entries = 16;
+		break;
+	case CHIP_RV770:
+		num_ps_gprs = 192;
+		num_vs_gprs = 56;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 188;
+		num_vs_threads = 60;
+		num_gs_threads = 0;
+		num_es_threads = 0;
+		num_ps_stack_entries = 256;
+		num_vs_stack_entries = 256;
+		num_gs_stack_entries = 0;
+		num_es_stack_entries = 0;
+		break;
+	case CHIP_RV730:
+	case CHIP_RV740:
+		num_ps_gprs = 84;
+		num_vs_gprs = 36;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 188;
+		num_vs_threads = 60;
+		num_gs_threads = 0;
+		num_es_threads = 0;
+		num_ps_stack_entries = 128;
+		num_vs_stack_entries = 128;
+		num_gs_stack_entries = 0;
+		num_es_stack_entries = 0;
+		break;
+	case CHIP_RV710:
+		num_ps_gprs = 192;
+		num_vs_gprs = 56;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 144;
+		num_vs_threads = 48;
+		num_gs_threads = 0;
+		num_es_threads = 0;
+		num_ps_stack_entries = 128;
+		num_vs_stack_entries = 128;
+		num_gs_stack_entries = 0;
+		num_es_stack_entries = 0;
+		break;
+	}
+
+	if ((rdev->family == CHIP_RV610) ||
+	    (rdev->family == CHIP_RV620) ||
+	    (rdev->family == CHIP_RS780) ||
+	    (rdev->family == CHIP_RS780) ||
+	    (rdev->family == CHIP_RV710))
+		sq_config = 0;
+	else
+		sq_config = VC_ENABLE;
+
+	sq_config |= (DX9_CONSTS |
+		      ALU_INST_PREFER_VECTOR |
+		      PS_PRIO(0) |
+		      VS_PRIO(1) |
+		      GS_PRIO(2) |
+		      ES_PRIO(3));
+
+	sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
+				  NUM_VS_GPRS(num_vs_gprs) |
+				  NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
+	sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
+				  NUM_ES_GPRS(num_es_gprs));
+	sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
+				   NUM_VS_THREADS(num_vs_threads) |
+				   NUM_GS_THREADS(num_gs_threads) |
+				   NUM_ES_THREADS(num_es_threads));
+	sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
+				    NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
+	sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
+				    NUM_ES_STACK_ENTRIES(num_es_stack_entries));
+
+	/* emit an IB pointing at default state */
+	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
+	radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
+	radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC);
+	radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
+	radeon_ring_write(rdev, (rdev->r600_blit.state_len / 4));
+
+	radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
+	radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
+	/* SQ config */
+	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6));
+	radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
+	radeon_ring_write(rdev, sq_config);
+	radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
+	radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
+	radeon_ring_write(rdev, sq_thread_resource_mgmt);
+	radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
+	radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
+}
+
+static inline uint32_t i2f(uint32_t input)
+{
+	u32 result, i, exponent, fraction;
+
+	if ((input & 0x3fff) == 0)
+		result = 0; /* 0 is a special case */
+	else {
+		exponent = 140; /* exponent biased by 127; */
+		fraction = (input & 0x3fff) << 10; /* cheat and only
+						      handle numbers below 2^^15 */
+		for (i = 0; i < 14; i++) {
+			if (fraction & 0x800000)
+				break;
+			else {
+				fraction = fraction << 1; /* keep
+							     shifting left until top bit = 1 */
+				exponent = exponent - 1;
+			}
+		}
+		result = exponent << 23 | (fraction & 0x7fffff); /* mask
+								    off top bit; assumed 1 */
+	}
+	return result;
+}
+
+int r600_blit_init(struct radeon_device *rdev)
+{
+	u32 obj_size;
+	int r;
+	void *ptr;
+
+	rdev->r600_blit.state_offset = 0;
+
+	if (rdev->family >= CHIP_RV770)
+		rdev->r600_blit.state_len = r7xx_default_size * 4;
+	else
+		rdev->r600_blit.state_len = r6xx_default_size * 4;
+
+	obj_size = rdev->r600_blit.state_len;
+	obj_size = ALIGN(obj_size, 256);
+
+	rdev->r600_blit.vs_offset = obj_size;
+	obj_size += r6xx_vs_size * 4;
+	obj_size = ALIGN(obj_size, 256);
+
+	rdev->r600_blit.ps_offset = obj_size;
+	obj_size += r6xx_ps_size * 4;
+	obj_size = ALIGN(obj_size, 256);
+
+	r = radeon_object_create(rdev, NULL, obj_size,
+				 true, RADEON_GEM_DOMAIN_VRAM,
+				 false, &rdev->r600_blit.shader_obj);
+	if (r) {
+		DRM_ERROR("r600 failed to allocate shader\n");
+		return r;
+	}
+
+	r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
+			     &rdev->r600_blit.shader_gpu_addr);
+	if (r) {
+		DRM_ERROR("failed to pin blit object %d\n", r);
+		return r;
+	}
+
+	DRM_DEBUG("r6xx blit allocated bo @ 0x%16llx %08x vs %08x ps %08x\n",
+		  rdev->r600_blit.shader_gpu_addr, obj_size,
+		  rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
+
+	r = radeon_object_kmap(rdev->r600_blit.shader_obj, &ptr);
+	if (r) {
+		DRM_ERROR("failed to map blit object %d\n", r);
+		return r;
+	}
+
+	if (rdev->family >= CHIP_RV770)
+		memcpy_toio(ptr + rdev->r600_blit.state_offset, r7xx_default_state, rdev->r600_blit.state_len);
+	else
+		memcpy_toio(ptr + rdev->r600_blit.state_offset, r6xx_default_state, rdev->r600_blit.state_len);
+
+	memcpy(ptr + rdev->r600_blit.vs_offset, r6xx_vs, r6xx_vs_size * 4);
+	memcpy(ptr + rdev->r600_blit.ps_offset, r6xx_ps, r6xx_ps_size * 4);
+
+	radeon_object_kunmap(rdev->r600_blit.shader_obj);
+	return 0;
+}
+
+void r600_blit_fini(struct radeon_device *rdev)
+{
+	radeon_object_unpin(rdev->r600_blit.shader_obj);
+	radeon_object_unref(&rdev->r600_blit.shader_obj);
+}
+
+int r600_vb_ib_get(struct radeon_device *rdev)
+{
+	int r;
+	r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib);
+	if (r) {
+		DRM_ERROR("failed to get IB for vertex buffer\n");
+		return r;
+	}
+
+	rdev->r600_blit.vb_total = 64*1024;
+	rdev->r600_blit.vb_used = 0;
+	return 0;
+}
+
+void r600_vb_ib_put(struct radeon_device *rdev)
+{
+	mutex_lock(&rdev->ib_pool.mutex);
+	radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence);
+	list_add_tail(&rdev->r600_blit.vb_ib->list, &rdev->ib_pool.scheduled_ibs);
+	mutex_unlock(&rdev->ib_pool.mutex);
+	radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
+}
+
+int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
+{
+	int r;
+	int ring_size;
+	const int max_size = 8192*8192;
+
+	r = r600_vb_ib_get(rdev);
+	WARN_ON(r);
+
+	/* loops of emits 64 + fence emit possible */
+	ring_size = ((size_bytes + max_size) / max_size) * 78;
+	/* set default  + shaders */
+	ring_size += 40; /* shaders + def state */
+	ring_size += 3; /* fence emit for VB IB */
+	ring_size += 5; /* done copy */
+	ring_size += 3; /* fence emit for done copy */
+	r = radeon_ring_lock(rdev, ring_size);
+	WARN_ON(r);
+
+	set_default_state(rdev); /* 14 */
+	set_shaders(rdev); /* 26 */
+	return 0;
+}
+
+void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
+{
+	int r;
+
+	radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
+	radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
+	/* wait for 3D idle clean */
+	radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+	radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
+	radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
+
+	if (rdev->r600_blit.vb_ib)
+		r600_vb_ib_put(rdev);
+
+	if (fence)
+		r = radeon_fence_emit(rdev, fence);
+
+	radeon_ring_unlock_commit(rdev);
+}
+
+void r600_kms_blit_copy(struct radeon_device *rdev,
+			u64 src_gpu_addr, u64 dst_gpu_addr,
+			int size_bytes)
+{
+	int max_bytes;
+	u64 vb_gpu_addr;
+	u32 *vb;
+
+	DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr,
+		  size_bytes, rdev->r600_blit.vb_used);
+	vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
+	if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
+		max_bytes = 8192;
+
+		while (size_bytes) {
+			int cur_size = size_bytes;
+			int src_x = src_gpu_addr & 255;
+			int dst_x = dst_gpu_addr & 255;
+			int h = 1;
+			src_gpu_addr = src_gpu_addr & ~255;
+			dst_gpu_addr = dst_gpu_addr & ~255;
+
+			if (!src_x && !dst_x) {
+				h = (cur_size / max_bytes);
+				if (h > 8192)
+					h = 8192;
+				if (h == 0)
+					h = 1;
+				else
+					cur_size = max_bytes;
+			} else {
+				if (cur_size > max_bytes)
+					cur_size = max_bytes;
+				if (cur_size > (max_bytes - dst_x))
+					cur_size = (max_bytes - dst_x);
+				if (cur_size > (max_bytes - src_x))
+					cur_size = (max_bytes - src_x);
+			}
+
+			if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
+				WARN_ON(1);
+
+#if 0
+				r600_vb_ib_put(rdev);
+
+				r600_nomm_put_vb(dev);
+				r600_nomm_get_vb(dev);
+				if (!dev_priv->blit_vb)
+					return;
+				set_shaders(dev);
+				vb = r600_nomm_get_vb_ptr(dev);
+#endif
+			}
+
+			vb[0] = i2f(dst_x);
+			vb[1] = 0;
+			vb[2] = i2f(src_x);
+			vb[3] = 0;
+
+			vb[4] = i2f(dst_x);
+			vb[5] = i2f(h);
+			vb[6] = i2f(src_x);
+			vb[7] = i2f(h);
+
+			vb[8] = i2f(dst_x + cur_size);
+			vb[9] = i2f(h);
+			vb[10] = i2f(src_x + cur_size);
+			vb[11] = i2f(h);
+
+			/* src 9 */
+			set_tex_resource(rdev, FMT_8,
+					 src_x + cur_size, h, src_x + cur_size,
+					 src_gpu_addr);
+
+			/* 5 */
+			cp_set_surface_sync(rdev,
+					    PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
+
+			/* dst 23 */
+			set_render_target(rdev, COLOR_8,
+					  dst_x + cur_size, h,
+					  dst_gpu_addr);
+
+			/* scissors 12 */
+			set_scissors(rdev, dst_x, 0, dst_x + cur_size, h);
+
+			/* 14 */
+			vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
+			set_vtx_resource(rdev, vb_gpu_addr);
+
+			/* draw 10 */
+			draw_auto(rdev);
+
+			/* 5 */
+			cp_set_surface_sync(rdev,
+					    PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
+					    cur_size * h, dst_gpu_addr);
+
+			vb += 12;
+			rdev->r600_blit.vb_used += 12 * 4;
+
+			src_gpu_addr += cur_size * h;
+			dst_gpu_addr += cur_size * h;
+			size_bytes -= cur_size * h;
+		}
+	} else {
+		max_bytes = 8192 * 4;
+
+		while (size_bytes) {
+			int cur_size = size_bytes;
+			int src_x = (src_gpu_addr & 255);
+			int dst_x = (dst_gpu_addr & 255);
+			int h = 1;
+			src_gpu_addr = src_gpu_addr & ~255;
+			dst_gpu_addr = dst_gpu_addr & ~255;
+
+			if (!src_x && !dst_x) {
+				h = (cur_size / max_bytes);
+				if (h > 8192)
+					h = 8192;
+				if (h == 0)
+					h = 1;
+				else
+					cur_size = max_bytes;
+			} else {
+				if (cur_size > max_bytes)
+					cur_size = max_bytes;
+				if (cur_size > (max_bytes - dst_x))
+					cur_size = (max_bytes - dst_x);
+				if (cur_size > (max_bytes - src_x))
+					cur_size = (max_bytes - src_x);
+			}
+
+			if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
+				WARN_ON(1);
+			}
+#if 0
+			if ((rdev->blit_vb->used + 48) > rdev->blit_vb->total) {
+				r600_nomm_put_vb(dev);
+				r600_nomm_get_vb(dev);
+				if (!rdev->blit_vb)
+					return;
+
+				set_shaders(dev);
+				vb = r600_nomm_get_vb_ptr(dev);
+			}
+#endif
+
+			vb[0] = i2f(dst_x / 4);
+			vb[1] = 0;
+			vb[2] = i2f(src_x / 4);
+			vb[3] = 0;
+
+			vb[4] = i2f(dst_x / 4);
+			vb[5] = i2f(h);
+			vb[6] = i2f(src_x / 4);
+			vb[7] = i2f(h);
+
+			vb[8] = i2f((dst_x + cur_size) / 4);
+			vb[9] = i2f(h);
+			vb[10] = i2f((src_x + cur_size) / 4);
+			vb[11] = i2f(h);
+
+			/* src 9 */
+			set_tex_resource(rdev, FMT_8_8_8_8,
+					 (src_x + cur_size) / 4,
+					 h, (src_x + cur_size) / 4,
+					 src_gpu_addr);
+			/* 5 */
+			cp_set_surface_sync(rdev,
+					    PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
+
+			/* dst 23 */
+			set_render_target(rdev, COLOR_8_8_8_8,
+					  dst_x + cur_size, h,
+					  dst_gpu_addr);
+
+			/* scissors 12  */
+			set_scissors(rdev, (dst_x / 4), 0, (dst_x + cur_size / 4), h);
+
+			/* Vertex buffer setup 14 */
+			vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
+			set_vtx_resource(rdev, vb_gpu_addr);
+
+			/* draw 10 */
+			draw_auto(rdev);
+
+			/* 5 */
+			cp_set_surface_sync(rdev,
+					    PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
+					    cur_size * h, dst_gpu_addr);
+
+			/* 78 ring dwords per loop */
+			vb += 12;
+			rdev->r600_blit.vb_used += 12 * 4;
+
+			src_gpu_addr += cur_size * h;
+			dst_gpu_addr += cur_size * h;
+			size_bytes -= cur_size * h;
+		}
+	}
+}
+
diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.c b/drivers/gpu/drm/radeon/r600_blit_shaders.c
new file mode 100644
index 00000000000..d745e815c2e
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r600_blit_shaders.c
@@ -0,0 +1,1072 @@
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+const u32 r6xx_default_state[] =
+{
+	0xc0002400,
+	0x00000000,
+	0xc0012800,
+	0x80000000,
+	0x80000000,
+	0xc0004600,
+	0x00000016,
+	0xc0016800,
+	0x00000010,
+	0x00028000,
+	0xc0016800,
+	0x00000010,
+	0x00008000,
+	0xc0016800,
+	0x00000542,
+	0x07000003,
+	0xc0016800,
+	0x000005c5,
+	0x00000000,
+	0xc0016800,
+	0x00000363,
+	0x00000000,
+	0xc0016800,
+	0x0000060c,
+	0x82000000,
+	0xc0016800,
+	0x0000060e,
+	0x01020204,
+	0xc0016f00,
+	0x00000000,
+	0x00000000,
+	0xc0016f00,
+	0x00000001,
+	0x00000000,
+	0xc0096900,
+	0x0000022a,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xc0016900,
+	0x00000004,
+	0x00000000,
+	0xc0016900,
+	0x0000000a,
+	0x00000000,
+	0xc0016900,
+	0x0000000b,
+	0x00000000,
+	0xc0016900,
+	0x0000010c,
+	0x00000000,
+	0xc0016900,
+	0x0000010d,
+	0x00000000,
+	0xc0016900,
+	0x00000200,
+	0x00000000,
+	0xc0016900,
+	0x00000343,
+	0x00000060,
+	0xc0016900,
+	0x00000344,
+	0x00000040,
+	0xc0016900,
+	0x00000351,
+	0x0000aa00,
+	0xc0016900,
+	0x00000104,
+	0x00000000,
+	0xc0016900,
+	0x0000010e,
+	0x00000000,
+	0xc0046900,
+	0x00000105,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xc0036900,
+	0x00000109,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xc0046900,
+	0x0000030c,
+	0x01000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xc0046900,
+	0x00000048,
+	0x3f800000,
+	0x00000000,
+	0x3f800000,
+	0x3f800000,
+	0xc0016900,
+	0x0000008e,
+	0x0000000f,
+	0xc0016900,
+	0x00000080,
+	0x00000000,
+	0xc0016900,
+	0x00000083,
+	0x0000ffff,
+	0xc0016900,
+	0x00000084,
+	0x00000000,
+	0xc0016900,
+	0x00000085,
+	0x20002000,
+	0xc0016900,
+	0x00000086,
+	0x00000000,
+	0xc0016900,
+	0x00000087,
+	0x20002000,
+	0xc0016900,
+	0x00000088,
+	0x00000000,
+	0xc0016900,
+	0x00000089,
+	0x20002000,
+	0xc0016900,
+	0x0000008a,
+	0x00000000,
+	0xc0016900,
+	0x0000008b,
+	0x20002000,
+	0xc0016900,
+	0x0000008c,
+	0x00000000,
+	0xc0016900,
+	0x00000094,
+	0x80000000,
+	0xc0016900,
+	0x00000095,
+	0x20002000,
+	0xc0026900,
+	0x000000b4,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x00000096,
+	0x80000000,
+	0xc0016900,
+	0x00000097,
+	0x20002000,
+	0xc0026900,
+	0x000000b6,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x00000098,
+	0x80000000,
+	0xc0016900,
+	0x00000099,
+	0x20002000,
+	0xc0026900,
+	0x000000b8,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x0000009a,
+	0x80000000,
+	0xc0016900,
+	0x0000009b,
+	0x20002000,
+	0xc0026900,
+	0x000000ba,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x0000009c,
+	0x80000000,
+	0xc0016900,
+	0x0000009d,
+	0x20002000,
+	0xc0026900,
+	0x000000bc,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x0000009e,
+	0x80000000,
+	0xc0016900,
+	0x0000009f,
+	0x20002000,
+	0xc0026900,
+	0x000000be,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x000000a0,
+	0x80000000,
+	0xc0016900,
+	0x000000a1,
+	0x20002000,
+	0xc0026900,
+	0x000000c0,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x000000a2,
+	0x80000000,
+	0xc0016900,
+	0x000000a3,
+	0x20002000,
+	0xc0026900,
+	0x000000c2,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x000000a4,
+	0x80000000,
+	0xc0016900,
+	0x000000a5,
+	0x20002000,
+	0xc0026900,
+	0x000000c4,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x000000a6,
+	0x80000000,
+	0xc0016900,
+	0x000000a7,
+	0x20002000,
+	0xc0026900,
+	0x000000c6,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x000000a8,
+	0x80000000,
+	0xc0016900,
+	0x000000a9,
+	0x20002000,
+	0xc0026900,
+	0x000000c8,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x000000aa,
+	0x80000000,
+	0xc0016900,
+	0x000000ab,
+	0x20002000,
+	0xc0026900,
+	0x000000ca,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x000000ac,
+	0x80000000,
+	0xc0016900,
+	0x000000ad,
+	0x20002000,
+	0xc0026900,
+	0x000000cc,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x000000ae,
+	0x80000000,
+	0xc0016900,
+	0x000000af,
+	0x20002000,
+	0xc0026900,
+	0x000000ce,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x000000b0,
+	0x80000000,
+	0xc0016900,
+	0x000000b1,
+	0x20002000,
+	0xc0026900,
+	0x000000d0,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x000000b2,
+	0x80000000,
+	0xc0016900,
+	0x000000b3,
+	0x20002000,
+	0xc0026900,
+	0x000000d2,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x00000293,
+	0x00004010,
+	0xc0016900,
+	0x00000300,
+	0x00000000,
+	0xc0016900,
+	0x00000301,
+	0x00000000,
+	0xc0016900,
+	0x00000312,
+	0xffffffff,
+	0xc0016900,
+	0x00000307,
+	0x00000000,
+	0xc0016900,
+	0x00000308,
+	0x00000000,
+	0xc0016900,
+	0x00000283,
+	0x00000000,
+	0xc0016900,
+	0x00000292,
+	0x00000000,
+	0xc0066900,
+	0x0000010f,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xc0016900,
+	0x00000206,
+	0x00000000,
+	0xc0016900,
+	0x00000207,
+	0x00000000,
+	0xc0016900,
+	0x00000208,
+	0x00000000,
+	0xc0046900,
+	0x00000303,
+	0x3f800000,
+	0x3f800000,
+	0x3f800000,
+	0x3f800000,
+	0xc0016900,
+	0x00000205,
+	0x00000004,
+	0xc0016900,
+	0x00000280,
+	0x00000000,
+	0xc0016900,
+	0x00000281,
+	0x00000000,
+	0xc0016900,
+	0x0000037e,
+	0x00000000,
+	0xc0016900,
+	0x00000382,
+	0x00000000,
+	0xc0016900,
+	0x00000380,
+	0x00000000,
+	0xc0016900,
+	0x00000383,
+	0x00000000,
+	0xc0016900,
+	0x00000381,
+	0x00000000,
+	0xc0016900,
+	0x00000282,
+	0x00000008,
+	0xc0016900,
+	0x00000302,
+	0x0000002d,
+	0xc0016900,
+	0x0000037f,
+	0x00000000,
+	0xc0016900,
+	0x000001b2,
+	0x00000000,
+	0xc0016900,
+	0x000001b6,
+	0x00000000,
+	0xc0016900,
+	0x000001b7,
+	0x00000000,
+	0xc0016900,
+	0x000001b8,
+	0x00000000,
+	0xc0016900,
+	0x000001b9,
+	0x00000000,
+	0xc0016900,
+	0x00000225,
+	0x00000000,
+	0xc0016900,
+	0x00000229,
+	0x00000000,
+	0xc0016900,
+	0x00000237,
+	0x00000000,
+	0xc0016900,
+	0x00000100,
+	0x00000800,
+	0xc0016900,
+	0x00000101,
+	0x00000000,
+	0xc0016900,
+	0x00000102,
+	0x00000000,
+	0xc0016900,
+	0x000002a8,
+	0x00000000,
+	0xc0016900,
+	0x000002a9,
+	0x00000000,
+	0xc0016900,
+	0x00000103,
+	0x00000000,
+	0xc0016900,
+	0x00000284,
+	0x00000000,
+	0xc0016900,
+	0x00000290,
+	0x00000000,
+	0xc0016900,
+	0x00000285,
+	0x00000000,
+	0xc0016900,
+	0x00000286,
+	0x00000000,
+	0xc0016900,
+	0x00000287,
+	0x00000000,
+	0xc0016900,
+	0x00000288,
+	0x00000000,
+	0xc0016900,
+	0x00000289,
+	0x00000000,
+	0xc0016900,
+	0x0000028a,
+	0x00000000,
+	0xc0016900,
+	0x0000028b,
+	0x00000000,
+	0xc0016900,
+	0x0000028c,
+	0x00000000,
+	0xc0016900,
+	0x0000028d,
+	0x00000000,
+	0xc0016900,
+	0x0000028e,
+	0x00000000,
+	0xc0016900,
+	0x0000028f,
+	0x00000000,
+	0xc0016900,
+	0x000002a1,
+	0x00000000,
+	0xc0016900,
+	0x000002a5,
+	0x00000000,
+	0xc0016900,
+	0x000002ac,
+	0x00000000,
+	0xc0016900,
+	0x000002ad,
+	0x00000000,
+	0xc0016900,
+	0x000002ae,
+	0x00000000,
+	0xc0016900,
+	0x000002c8,
+	0x00000000,
+	0xc0016900,
+	0x00000206,
+	0x00000100,
+	0xc0016900,
+	0x00000204,
+	0x00010000,
+	0xc0036e00,
+	0x00000000,
+	0x00000012,
+	0x00000000,
+	0x00000000,
+	0xc0016900,
+	0x0000008f,
+	0x0000000f,
+	0xc0016900,
+	0x000001e8,
+	0x00000001,
+	0xc0016900,
+	0x00000202,
+	0x00cc0000,
+	0xc0016900,
+	0x00000205,
+	0x00000244,
+	0xc0016900,
+	0x00000203,
+	0x00000210,
+	0xc0016900,
+	0x000001b1,
+	0x00000000,
+	0xc0016900,
+	0x00000185,
+	0x00000000,
+	0xc0016900,
+	0x000001b3,
+	0x00000001,
+	0xc0016900,
+	0x000001b4,
+	0x00000000,
+	0xc0016900,
+	0x00000191,
+	0x00000b00,
+	0xc0016900,
+	0x000001b5,
+	0x00000000,
+};
+
+const u32 r7xx_default_state[] =
+{
+	0xc0012800,
+	0x80000000,
+	0x80000000,
+	0xc0004600,
+	0x00000016,
+	0xc0016800,
+	0x00000010,
+	0x00028000,
+	0xc0016800,
+	0x00000010,
+	0x00008000,
+	0xc0016800,
+	0x00000542,
+	0x07000002,
+	0xc0016800,
+	0x000005c5,
+	0x00000000,
+	0xc0016800,
+	0x00000363,
+	0x00004000,
+	0xc0016800,
+	0x0000060c,
+	0x00000000,
+	0xc0016800,
+	0x0000060e,
+	0x00420204,
+	0xc0016f00,
+	0x00000000,
+	0x00000000,
+	0xc0016f00,
+	0x00000001,
+	0x00000000,
+	0xc0096900,
+	0x0000022a,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xc0016900,
+	0x00000004,
+	0x00000000,
+	0xc0016900,
+	0x0000000a,
+	0x00000000,
+	0xc0016900,
+	0x0000000b,
+	0x00000000,
+	0xc0016900,
+	0x0000010c,
+	0x00000000,
+	0xc0016900,
+	0x0000010d,
+	0x00000000,
+	0xc0016900,
+	0x00000200,
+	0x00000000,
+	0xc0016900,
+	0x00000343,
+	0x00000060,
+	0xc0016900,
+	0x00000344,
+	0x00000000,
+	0xc0016900,
+	0x00000351,
+	0x0000aa00,
+	0xc0016900,
+	0x00000104,
+	0x00000000,
+	0xc0016900,
+	0x0000010e,
+	0x00000000,
+	0xc0046900,
+	0x00000105,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xc0046900,
+	0x0000030c,
+	0x01000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xc0016900,
+	0x0000008e,
+	0x0000000f,
+	0xc0016900,
+	0x00000080,
+	0x00000000,
+	0xc0016900,
+	0x00000083,
+	0x0000ffff,
+	0xc0016900,
+	0x00000084,
+	0x00000000,
+	0xc0016900,
+	0x00000085,
+	0x20002000,
+	0xc0016900,
+	0x00000086,
+	0x00000000,
+	0xc0016900,
+	0x00000087,
+	0x20002000,
+	0xc0016900,
+	0x00000088,
+	0x00000000,
+	0xc0016900,
+	0x00000089,
+	0x20002000,
+	0xc0016900,
+	0x0000008a,
+	0x00000000,
+	0xc0016900,
+	0x0000008b,
+	0x20002000,
+	0xc0016900,
+	0x0000008c,
+	0xaaaaaaaa,
+	0xc0016900,
+	0x00000094,
+	0x80000000,
+	0xc0016900,
+	0x00000095,
+	0x20002000,
+	0xc0026900,
+	0x000000b4,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x00000096,
+	0x80000000,
+	0xc0016900,
+	0x00000097,
+	0x20002000,
+	0xc0026900,
+	0x000000b6,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x00000098,
+	0x80000000,
+	0xc0016900,
+	0x00000099,
+	0x20002000,
+	0xc0026900,
+	0x000000b8,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x0000009a,
+	0x80000000,
+	0xc0016900,
+	0x0000009b,
+	0x20002000,
+	0xc0026900,
+	0x000000ba,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x0000009c,
+	0x80000000,
+	0xc0016900,
+	0x0000009d,
+	0x20002000,
+	0xc0026900,
+	0x000000bc,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x0000009e,
+	0x80000000,
+	0xc0016900,
+	0x0000009f,
+	0x20002000,
+	0xc0026900,
+	0x000000be,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x000000a0,
+	0x80000000,
+	0xc0016900,
+	0x000000a1,
+	0x20002000,
+	0xc0026900,
+	0x000000c0,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x000000a2,
+	0x80000000,
+	0xc0016900,
+	0x000000a3,
+	0x20002000,
+	0xc0026900,
+	0x000000c2,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x000000a4,
+	0x80000000,
+	0xc0016900,
+	0x000000a5,
+	0x20002000,
+	0xc0026900,
+	0x000000c4,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x000000a6,
+	0x80000000,
+	0xc0016900,
+	0x000000a7,
+	0x20002000,
+	0xc0026900,
+	0x000000c6,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x000000a8,
+	0x80000000,
+	0xc0016900,
+	0x000000a9,
+	0x20002000,
+	0xc0026900,
+	0x000000c8,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x000000aa,
+	0x80000000,
+	0xc0016900,
+	0x000000ab,
+	0x20002000,
+	0xc0026900,
+	0x000000ca,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x000000ac,
+	0x80000000,
+	0xc0016900,
+	0x000000ad,
+	0x20002000,
+	0xc0026900,
+	0x000000cc,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x000000ae,
+	0x80000000,
+	0xc0016900,
+	0x000000af,
+	0x20002000,
+	0xc0026900,
+	0x000000ce,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x000000b0,
+	0x80000000,
+	0xc0016900,
+	0x000000b1,
+	0x20002000,
+	0xc0026900,
+	0x000000d0,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x000000b2,
+	0x80000000,
+	0xc0016900,
+	0x000000b3,
+	0x20002000,
+	0xc0026900,
+	0x000000d2,
+	0x00000000,
+	0x3f800000,
+	0xc0016900,
+	0x00000293,
+	0x00514000,
+	0xc0016900,
+	0x00000300,
+	0x00000000,
+	0xc0016900,
+	0x00000301,
+	0x00000000,
+	0xc0016900,
+	0x00000312,
+	0xffffffff,
+	0xc0016900,
+	0x00000307,
+	0x00000000,
+	0xc0016900,
+	0x00000308,
+	0x00000000,
+	0xc0016900,
+	0x00000283,
+	0x00000000,
+	0xc0016900,
+	0x00000292,
+	0x00000000,
+	0xc0066900,
+	0x0000010f,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xc0016900,
+	0x00000206,
+	0x00000000,
+	0xc0016900,
+	0x00000207,
+	0x00000000,
+	0xc0016900,
+	0x00000208,
+	0x00000000,
+	0xc0046900,
+	0x00000303,
+	0x3f800000,
+	0x3f800000,
+	0x3f800000,
+	0x3f800000,
+	0xc0016900,
+	0x00000205,
+	0x00000004,
+	0xc0016900,
+	0x00000280,
+	0x00000000,
+	0xc0016900,
+	0x00000281,
+	0x00000000,
+	0xc0016900,
+	0x0000037e,
+	0x00000000,
+	0xc0016900,
+	0x00000382,
+	0x00000000,
+	0xc0016900,
+	0x00000380,
+	0x00000000,
+	0xc0016900,
+	0x00000383,
+	0x00000000,
+	0xc0016900,
+	0x00000381,
+	0x00000000,
+	0xc0016900,
+	0x00000282,
+	0x00000008,
+	0xc0016900,
+	0x00000302,
+	0x0000002d,
+	0xc0016900,
+	0x0000037f,
+	0x00000000,
+	0xc0016900,
+	0x000001b2,
+	0x00000001,
+	0xc0016900,
+	0x000001b6,
+	0x00000000,
+	0xc0016900,
+	0x000001b7,
+	0x00000000,
+	0xc0016900,
+	0x000001b8,
+	0x00000000,
+	0xc0016900,
+	0x000001b9,
+	0x00000000,
+	0xc0016900,
+	0x00000225,
+	0x00000000,
+	0xc0016900,
+	0x00000229,
+	0x00000000,
+	0xc0016900,
+	0x00000237,
+	0x00000000,
+	0xc0016900,
+	0x00000100,
+	0x00000800,
+	0xc0016900,
+	0x00000101,
+	0x00000000,
+	0xc0016900,
+	0x00000102,
+	0x00000000,
+	0xc0016900,
+	0x000002a8,
+	0x00000000,
+	0xc0016900,
+	0x000002a9,
+	0x00000000,
+	0xc0016900,
+	0x00000103,
+	0x00000000,
+	0xc0016900,
+	0x00000284,
+	0x00000000,
+	0xc0016900,
+	0x00000290,
+	0x00000000,
+	0xc0016900,
+	0x00000285,
+	0x00000000,
+	0xc0016900,
+	0x00000286,
+	0x00000000,
+	0xc0016900,
+	0x00000287,
+	0x00000000,
+	0xc0016900,
+	0x00000288,
+	0x00000000,
+	0xc0016900,
+	0x00000289,
+	0x00000000,
+	0xc0016900,
+	0x0000028a,
+	0x00000000,
+	0xc0016900,
+	0x0000028b,
+	0x00000000,
+	0xc0016900,
+	0x0000028c,
+	0x00000000,
+	0xc0016900,
+	0x0000028d,
+	0x00000000,
+	0xc0016900,
+	0x0000028e,
+	0x00000000,
+	0xc0016900,
+	0x0000028f,
+	0x00000000,
+	0xc0016900,
+	0x000002a1,
+	0x00000000,
+	0xc0016900,
+	0x000002a5,
+	0x00000000,
+	0xc0016900,
+	0x000002ac,
+	0x00000000,
+	0xc0016900,
+	0x000002ad,
+	0x00000000,
+	0xc0016900,
+	0x000002ae,
+	0x00000000,
+	0xc0016900,
+	0x000002c8,
+	0x00000000,
+	0xc0016900,
+	0x00000206,
+	0x00000100,
+	0xc0016900,
+	0x00000204,
+	0x00010000,
+	0xc0036e00,
+	0x00000000,
+	0x00000012,
+	0x00000000,
+	0x00000000,
+	0xc0016900,
+	0x0000008f,
+	0x0000000f,
+	0xc0016900,
+	0x000001e8,
+	0x00000001,
+	0xc0016900,
+	0x00000202,
+	0x00cc0000,
+	0xc0016900,
+	0x00000205,
+	0x00000244,
+	0xc0016900,
+	0x00000203,
+	0x00000210,
+	0xc0016900,
+	0x000001b1,
+	0x00000000,
+	0xc0016900,
+	0x00000185,
+	0x00000000,
+	0xc0016900,
+	0x000001b3,
+	0x00000001,
+	0xc0016900,
+	0x000001b4,
+	0x00000000,
+	0xc0016900,
+	0x00000191,
+	0x00000b00,
+	0xc0016900,
+	0x000001b5,
+	0x00000000,
+};
+
+/* same for r6xx/r7xx */
+const u32 r6xx_vs[] =
+{
+	0x00000004,
+	0x81000000,
+	0x0000203c,
+	0x94000b08,
+	0x00004000,
+	0x14200b1a,
+	0x00000000,
+	0x00000000,
+	0x3c000000,
+	0x68cd1000,
+	0x00080000,
+	0x00000000,
+};
+
+const u32 r6xx_ps[] =
+{
+	0x00000002,
+	0x80800000,
+	0x00000000,
+	0x94200688,
+	0x00000010,
+	0x000d1000,
+	0xb0800000,
+	0x00000000,
+};
+
+const u32 r6xx_ps_size = ARRAY_SIZE(r6xx_ps);
+const u32 r6xx_vs_size = ARRAY_SIZE(r6xx_vs);
+const u32 r6xx_default_size = ARRAY_SIZE(r6xx_default_state);
+const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state);
diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.h b/drivers/gpu/drm/radeon/r600_blit_shaders.h
new file mode 100644
index 00000000000..fdc3b378cbb
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r600_blit_shaders.h
@@ -0,0 +1,14 @@
+
+#ifndef R600_BLIT_SHADERS_H
+#define R600_BLIT_SHADERS_H
+
+extern const u32 r6xx_ps[];
+extern const u32 r6xx_vs[];
+extern const u32 r7xx_default_state[];
+extern const u32 r6xx_default_state[];
+
+
+extern const u32 r6xx_ps_size, r6xx_vs_size;
+extern const u32 r6xx_default_size, r7xx_default_size;
+
+#endif
diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c
index 8327912de96..6d5a711c2e9 100644
--- a/drivers/gpu/drm/radeon/r600_cp.c
+++ b/drivers/gpu/drm/radeon/r600_cp.c
@@ -58,6 +58,12 @@ MODULE_FIRMWARE("radeon/RV730_me.bin");
 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
 MODULE_FIRMWARE("radeon/RV710_me.bin");
 
+
+int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
+			unsigned family, u32 *ib, int *l);
+void r600_cs_legacy_init(void);
+
+
 # define ATI_PCIGART_PAGE_SIZE		4096	/**< PCI GART page size */
 # define ATI_PCIGART_PAGE_MASK		(~(ATI_PCIGART_PAGE_SIZE-1))
 
@@ -1857,6 +1863,8 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
 
 	DRM_DEBUG("\n");
 
+	mutex_init(&dev_priv->cs_mutex);
+	r600_cs_legacy_init();
 	/* if we require new memory map but we don't have it fail */
 	if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
 		DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
@@ -1888,7 +1896,7 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
 	/* Enable vblank on CRTC1 for older X servers
 	 */
 	dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
-
+	dev_priv->do_boxes = 0;
 	dev_priv->cp_mode = init->cp_mode;
 
 	/* We don't support anything other than bus-mastering ring mode,
@@ -1974,11 +1982,11 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
 	} else
 #endif
 	{
-		dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
+		dev_priv->cp_ring->handle = (void *)(unsigned long)dev_priv->cp_ring->offset;
 		dev_priv->ring_rptr->handle =
-		    (void *)dev_priv->ring_rptr->offset;
+			(void *)(unsigned long)dev_priv->ring_rptr->offset;
 		dev->agp_buffer_map->handle =
-		    (void *)dev->agp_buffer_map->offset;
+			(void *)(unsigned long)dev->agp_buffer_map->offset;
 
 		DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
 			  dev_priv->cp_ring->handle);
@@ -2282,3 +2290,239 @@ int r600_cp_dispatch_indirect(struct drm_device *dev,
 
 	return 0;
 }
+
+void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv)
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	struct drm_master *master = file_priv->master;
+	struct drm_radeon_master_private *master_priv = master->driver_priv;
+	drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
+	int nbox = sarea_priv->nbox;
+	struct drm_clip_rect *pbox = sarea_priv->boxes;
+	int i, cpp, src_pitch, dst_pitch;
+	uint64_t src, dst;
+	RING_LOCALS;
+	DRM_DEBUG("\n");
+
+	if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888)
+		cpp = 4;
+	else
+		cpp = 2;
+
+	if (sarea_priv->pfCurrentPage == 0) {
+		src_pitch = dev_priv->back_pitch;
+		dst_pitch = dev_priv->front_pitch;
+		src = dev_priv->back_offset + dev_priv->fb_location;
+		dst = dev_priv->front_offset + dev_priv->fb_location;
+	} else {
+		src_pitch = dev_priv->front_pitch;
+		dst_pitch = dev_priv->back_pitch;
+		src = dev_priv->front_offset + dev_priv->fb_location;
+		dst = dev_priv->back_offset + dev_priv->fb_location;
+	}
+
+	if (r600_prepare_blit_copy(dev, file_priv)) {
+		DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
+		return;
+	}
+	for (i = 0; i < nbox; i++) {
+		int x = pbox[i].x1;
+		int y = pbox[i].y1;
+		int w = pbox[i].x2 - x;
+		int h = pbox[i].y2 - y;
+
+		DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h);
+
+		r600_blit_swap(dev,
+			       src, dst,
+			       x, y, x, y, w, h,
+			       src_pitch, dst_pitch, cpp);
+	}
+	r600_done_blit_copy(dev);
+
+	/* Increment the frame counter.  The client-side 3D driver must
+	 * throttle the framerate by waiting for this value before
+	 * performing the swapbuffer ioctl.
+	 */
+	sarea_priv->last_frame++;
+
+	BEGIN_RING(3);
+	R600_FRAME_AGE(sarea_priv->last_frame);
+	ADVANCE_RING();
+}
+
+int r600_cp_dispatch_texture(struct drm_device *dev,
+			     struct drm_file *file_priv,
+			     drm_radeon_texture_t *tex,
+			     drm_radeon_tex_image_t *image)
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	struct drm_buf *buf;
+	u32 *buffer;
+	const u8 __user *data;
+	int size, pass_size;
+	u64 src_offset, dst_offset;
+
+	if (!radeon_check_offset(dev_priv, tex->offset)) {
+		DRM_ERROR("Invalid destination offset\n");
+		return -EINVAL;
+	}
+
+	/* this might fail for zero-sized uploads - are those illegal? */
+	if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) {
+		DRM_ERROR("Invalid final destination offset\n");
+		return -EINVAL;
+	}
+
+	size = tex->height * tex->pitch;
+
+	if (size == 0)
+		return 0;
+
+	dst_offset = tex->offset;
+
+	if (r600_prepare_blit_copy(dev, file_priv)) {
+		DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
+		return -EAGAIN;
+	}
+	do {
+		data = (const u8 __user *)image->data;
+		pass_size = size;
+
+		buf = radeon_freelist_get(dev);
+		if (!buf) {
+			DRM_DEBUG("EAGAIN\n");
+			if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image)))
+				return -EFAULT;
+			return -EAGAIN;
+		}
+
+		if (pass_size > buf->total)
+			pass_size = buf->total;
+
+		/* Dispatch the indirect buffer.
+		 */
+		buffer =
+		    (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
+
+		if (DRM_COPY_FROM_USER(buffer, data, pass_size)) {
+			DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size);
+			return -EFAULT;
+		}
+
+		buf->file_priv = file_priv;
+		buf->used = pass_size;
+		src_offset = dev_priv->gart_buffers_offset + buf->offset;
+
+		r600_blit_copy(dev, src_offset, dst_offset, pass_size);
+
+		radeon_cp_discard_buffer(dev, file_priv->master, buf);
+
+		/* Update the input parameters for next time */
+		image->data = (const u8 __user *)image->data + pass_size;
+		dst_offset += pass_size;
+		size -= pass_size;
+	} while (size > 0);
+	r600_done_blit_copy(dev);
+
+	return 0;
+}
+
+/*
+ * Legacy cs ioctl
+ */
+static u32 radeon_cs_id_get(struct drm_radeon_private *radeon)
+{
+	/* FIXME: check if wrap affect last reported wrap & sequence */
+	radeon->cs_id_scnt = (radeon->cs_id_scnt + 1) & 0x00FFFFFF;
+	if (!radeon->cs_id_scnt) {
+		/* increment wrap counter */
+		radeon->cs_id_wcnt += 0x01000000;
+		/* valid sequence counter start at 1 */
+		radeon->cs_id_scnt = 1;
+	}
+	return (radeon->cs_id_scnt | radeon->cs_id_wcnt);
+}
+
+static void r600_cs_id_emit(drm_radeon_private_t *dev_priv, u32 *id)
+{
+	RING_LOCALS;
+
+	*id = radeon_cs_id_get(dev_priv);
+
+	/* SCRATCH 2 */
+	BEGIN_RING(3);
+	R600_CLEAR_AGE(*id);
+	ADVANCE_RING();
+	COMMIT_RING();
+}
+
+static int r600_ib_get(struct drm_device *dev,
+			struct drm_file *fpriv,
+			struct drm_buf **buffer)
+{
+	struct drm_buf *buf;
+
+	*buffer = NULL;
+	buf = radeon_freelist_get(dev);
+	if (!buf) {
+		return -EBUSY;
+	}
+	buf->file_priv = fpriv;
+	*buffer = buf;
+	return 0;
+}
+
+static void r600_ib_free(struct drm_device *dev, struct drm_buf *buf,
+			struct drm_file *fpriv, int l, int r)
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+
+	if (buf) {
+		if (!r)
+			r600_cp_dispatch_indirect(dev, buf, 0, l * 4);
+		radeon_cp_discard_buffer(dev, fpriv->master, buf);
+		COMMIT_RING();
+	}
+}
+
+int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
+{
+	struct drm_radeon_private *dev_priv = dev->dev_private;
+	struct drm_radeon_cs *cs = data;
+	struct drm_buf *buf;
+	unsigned family;
+	int l, r = 0;
+	u32 *ib, cs_id = 0;
+
+	if (dev_priv == NULL) {
+		DRM_ERROR("called with no initialization\n");
+		return -EINVAL;
+	}
+	family = dev_priv->flags & RADEON_FAMILY_MASK;
+	if (family < CHIP_R600) {
+		DRM_ERROR("cs ioctl valid only for R6XX & R7XX in legacy mode\n");
+		return -EINVAL;
+	}
+	mutex_lock(&dev_priv->cs_mutex);
+	/* get ib */
+	r = r600_ib_get(dev, fpriv, &buf);
+	if (r) {
+		DRM_ERROR("ib_get failed\n");
+		goto out;
+	}
+	ib = dev->agp_buffer_map->handle + buf->offset;
+	/* now parse command stream */
+	r = r600_cs_legacy(dev, data,  fpriv, family, ib, &l);
+	if (r) {
+		goto out;
+	}
+
+out:
+	r600_ib_free(dev, buf, fpriv, l, r);
+	/* emit cs id sequence */
+	r600_cs_id_emit(dev_priv, &cs_id);
+	cs->cs_id = cs_id;
+	mutex_unlock(&dev_priv->cs_mutex);
+	return r;
+}
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
new file mode 100644
index 00000000000..39bf6349351
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -0,0 +1,658 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#include "drmP.h"
+#include "radeon.h"
+#include "radeon_share.h"
+#include "r600d.h"
+#include "avivod.h"
+
+static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
+					struct radeon_cs_reloc **cs_reloc);
+static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
+					struct radeon_cs_reloc **cs_reloc);
+typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
+static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
+
+/**
+ * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
+ * @parser:	parser structure holding parsing context.
+ * @pkt:	where to store packet informations
+ *
+ * Assume that chunk_ib_index is properly set. Will return -EINVAL
+ * if packet is bigger than remaining ib size. or if packets is unknown.
+ **/
+int r600_cs_packet_parse(struct radeon_cs_parser *p,
+			struct radeon_cs_packet *pkt,
+			unsigned idx)
+{
+	struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
+	uint32_t header;
+
+	if (idx >= ib_chunk->length_dw) {
+		DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
+			  idx, ib_chunk->length_dw);
+		return -EINVAL;
+	}
+	header = ib_chunk->kdata[idx];
+	pkt->idx = idx;
+	pkt->type = CP_PACKET_GET_TYPE(header);
+	pkt->count = CP_PACKET_GET_COUNT(header);
+	pkt->one_reg_wr = 0;
+	switch (pkt->type) {
+	case PACKET_TYPE0:
+		pkt->reg = CP_PACKET0_GET_REG(header);
+		break;
+	case PACKET_TYPE3:
+		pkt->opcode = CP_PACKET3_GET_OPCODE(header);
+		break;
+	case PACKET_TYPE2:
+		pkt->count = -1;
+		break;
+	default:
+		DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
+		return -EINVAL;
+	}
+	if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
+		DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
+			  pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
+		return -EINVAL;
+	}
+	return 0;
+}
+
+/**
+ * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
+ * @parser:		parser structure holding parsing context.
+ * @data:		pointer to relocation data
+ * @offset_start:	starting offset
+ * @offset_mask:	offset mask (to align start offset on)
+ * @reloc:		reloc informations
+ *
+ * Check next packet is relocation packet3, do bo validation and compute
+ * GPU offset using the provided start.
+ **/
+static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
+					struct radeon_cs_reloc **cs_reloc)
+{
+	struct radeon_cs_chunk *ib_chunk;
+	struct radeon_cs_chunk *relocs_chunk;
+	struct radeon_cs_packet p3reloc;
+	unsigned idx;
+	int r;
+
+	if (p->chunk_relocs_idx == -1) {
+		DRM_ERROR("No relocation chunk !\n");
+		return -EINVAL;
+	}
+	*cs_reloc = NULL;
+	ib_chunk = &p->chunks[p->chunk_ib_idx];
+	relocs_chunk = &p->chunks[p->chunk_relocs_idx];
+	r = r600_cs_packet_parse(p, &p3reloc, p->idx);
+	if (r) {
+		return r;
+	}
+	p->idx += p3reloc.count + 2;
+	if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
+		DRM_ERROR("No packet3 for relocation for packet at %d.\n",
+			  p3reloc.idx);
+		return -EINVAL;
+	}
+	idx = ib_chunk->kdata[p3reloc.idx + 1];
+	if (idx >= relocs_chunk->length_dw) {
+		DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
+			  idx, relocs_chunk->length_dw);
+		return -EINVAL;
+	}
+	/* FIXME: we assume reloc size is 4 dwords */
+	*cs_reloc = p->relocs_ptr[(idx / 4)];
+	return 0;
+}
+
+/**
+ * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
+ * @parser:		parser structure holding parsing context.
+ * @data:		pointer to relocation data
+ * @offset_start:	starting offset
+ * @offset_mask:	offset mask (to align start offset on)
+ * @reloc:		reloc informations
+ *
+ * Check next packet is relocation packet3, do bo validation and compute
+ * GPU offset using the provided start.
+ **/
+static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
+					struct radeon_cs_reloc **cs_reloc)
+{
+	struct radeon_cs_chunk *ib_chunk;
+	struct radeon_cs_chunk *relocs_chunk;
+	struct radeon_cs_packet p3reloc;
+	unsigned idx;
+	int r;
+
+	if (p->chunk_relocs_idx == -1) {
+		DRM_ERROR("No relocation chunk !\n");
+		return -EINVAL;
+	}
+	*cs_reloc = NULL;
+	ib_chunk = &p->chunks[p->chunk_ib_idx];
+	relocs_chunk = &p->chunks[p->chunk_relocs_idx];
+	r = r600_cs_packet_parse(p, &p3reloc, p->idx);
+	if (r) {
+		return r;
+	}
+	p->idx += p3reloc.count + 2;
+	if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
+		DRM_ERROR("No packet3 for relocation for packet at %d.\n",
+			  p3reloc.idx);
+		return -EINVAL;
+	}
+	idx = ib_chunk->kdata[p3reloc.idx + 1];
+	if (idx >= relocs_chunk->length_dw) {
+		DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
+			  idx, relocs_chunk->length_dw);
+		return -EINVAL;
+	}
+	*cs_reloc = &p->relocs[0];
+	(*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
+	(*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
+	return 0;
+}
+
+static int r600_packet0_check(struct radeon_cs_parser *p,
+				struct radeon_cs_packet *pkt,
+				unsigned idx, unsigned reg)
+{
+	switch (reg) {
+	case AVIVO_D1MODE_VLINE_START_END:
+	case AVIVO_D2MODE_VLINE_START_END:
+		break;
+	default:
+		printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
+		       reg, idx);
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
+				struct radeon_cs_packet *pkt)
+{
+	unsigned reg, i;
+	unsigned idx;
+	int r;
+
+	idx = pkt->idx + 1;
+	reg = pkt->reg;
+	for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
+		r = r600_packet0_check(p, pkt, idx, reg);
+		if (r) {
+			return r;
+		}
+	}
+	return 0;
+}
+
+static int r600_packet3_check(struct radeon_cs_parser *p,
+				struct radeon_cs_packet *pkt)
+{
+	struct radeon_cs_chunk *ib_chunk;
+	struct radeon_cs_reloc *reloc;
+	volatile u32 *ib;
+	unsigned idx;
+	unsigned i;
+	unsigned start_reg, end_reg, reg;
+	int r;
+
+	ib = p->ib->ptr;
+	ib_chunk = &p->chunks[p->chunk_ib_idx];
+	idx = pkt->idx + 1;
+	switch (pkt->opcode) {
+	case PACKET3_START_3D_CMDBUF:
+		if (p->family >= CHIP_RV770 || pkt->count) {
+			DRM_ERROR("bad START_3D\n");
+			return -EINVAL;
+		}
+		break;
+	case PACKET3_CONTEXT_CONTROL:
+		if (pkt->count != 1) {
+			DRM_ERROR("bad CONTEXT_CONTROL\n");
+			return -EINVAL;
+		}
+		break;
+	case PACKET3_INDEX_TYPE:
+	case PACKET3_NUM_INSTANCES:
+		if (pkt->count) {
+			DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
+			return -EINVAL;
+		}
+		break;
+	case PACKET3_DRAW_INDEX:
+		if (pkt->count != 3) {
+			DRM_ERROR("bad DRAW_INDEX\n");
+			return -EINVAL;
+		}
+		r = r600_cs_packet_next_reloc(p, &reloc);
+		if (r) {
+			DRM_ERROR("bad DRAW_INDEX\n");
+			return -EINVAL;
+		}
+		ib[idx+0] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
+		ib[idx+1] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
+		break;
+	case PACKET3_DRAW_INDEX_AUTO:
+		if (pkt->count != 1) {
+			DRM_ERROR("bad DRAW_INDEX_AUTO\n");
+			return -EINVAL;
+		}
+		break;
+	case PACKET3_DRAW_INDEX_IMMD_BE:
+	case PACKET3_DRAW_INDEX_IMMD:
+		if (pkt->count < 2) {
+			DRM_ERROR("bad DRAW_INDEX_IMMD\n");
+			return -EINVAL;
+		}
+		break;
+	case PACKET3_WAIT_REG_MEM:
+		if (pkt->count != 5) {
+			DRM_ERROR("bad WAIT_REG_MEM\n");
+			return -EINVAL;
+		}
+		/* bit 4 is reg (0) or mem (1) */
+		if (ib_chunk->kdata[idx+0] & 0x10) {
+			r = r600_cs_packet_next_reloc(p, &reloc);
+			if (r) {
+				DRM_ERROR("bad WAIT_REG_MEM\n");
+				return -EINVAL;
+			}
+			ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
+			ib[idx+2] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
+		}
+		break;
+	case PACKET3_SURFACE_SYNC:
+		if (pkt->count != 3) {
+			DRM_ERROR("bad SURFACE_SYNC\n");
+			return -EINVAL;
+		}
+		/* 0xffffffff/0x0 is flush all cache flag */
+		if (ib_chunk->kdata[idx+1] != 0xffffffff ||
+		    ib_chunk->kdata[idx+2] != 0) {
+			r = r600_cs_packet_next_reloc(p, &reloc);
+			if (r) {
+				DRM_ERROR("bad SURFACE_SYNC\n");
+				return -EINVAL;
+			}
+			ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+		}
+		break;
+	case PACKET3_EVENT_WRITE:
+		if (pkt->count != 2 && pkt->count != 0) {
+			DRM_ERROR("bad EVENT_WRITE\n");
+			return -EINVAL;
+		}
+		if (pkt->count) {
+			r = r600_cs_packet_next_reloc(p, &reloc);
+			if (r) {
+				DRM_ERROR("bad EVENT_WRITE\n");
+				return -EINVAL;
+			}
+			ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
+			ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
+		}
+		break;
+	case PACKET3_EVENT_WRITE_EOP:
+		if (pkt->count != 4) {
+			DRM_ERROR("bad EVENT_WRITE_EOP\n");
+			return -EINVAL;
+		}
+		r = r600_cs_packet_next_reloc(p, &reloc);
+		if (r) {
+			DRM_ERROR("bad EVENT_WRITE\n");
+			return -EINVAL;
+		}
+		ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
+		ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
+		break;
+	case PACKET3_SET_CONFIG_REG:
+		start_reg = (ib[idx+0] << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
+		end_reg = 4 * pkt->count + start_reg - 4;
+		if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
+		    (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
+		    (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
+			DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
+			return -EINVAL;
+		}
+		for (i = 0; i < pkt->count; i++) {
+			reg = start_reg + (4 * i);
+			switch (reg) {
+			case CP_COHER_BASE:
+				/* use PACKET3_SURFACE_SYNC */
+				return -EINVAL;
+			default:
+				break;
+			}
+		}
+		break;
+	case PACKET3_SET_CONTEXT_REG:
+		start_reg = (ib[idx+0] << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
+		end_reg = 4 * pkt->count + start_reg - 4;
+		if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
+		    (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
+		    (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
+			DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
+			return -EINVAL;
+		}
+		for (i = 0; i < pkt->count; i++) {
+			reg = start_reg + (4 * i);
+			switch (reg) {
+			case DB_DEPTH_BASE:
+			case CB_COLOR0_BASE:
+			case CB_COLOR1_BASE:
+			case CB_COLOR2_BASE:
+			case CB_COLOR3_BASE:
+			case CB_COLOR4_BASE:
+			case CB_COLOR5_BASE:
+			case CB_COLOR6_BASE:
+			case CB_COLOR7_BASE:
+			case SQ_PGM_START_FS:
+			case SQ_PGM_START_ES:
+			case SQ_PGM_START_VS:
+			case SQ_PGM_START_GS:
+			case SQ_PGM_START_PS:
+				r = r600_cs_packet_next_reloc(p, &reloc);
+				if (r) {
+					DRM_ERROR("bad SET_CONTEXT_REG "
+							"0x%04X\n", reg);
+					return -EINVAL;
+				}
+				ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+				break;
+			case VGT_DMA_BASE:
+			case VGT_DMA_BASE_HI:
+				/* These should be handled by DRAW_INDEX packet 3 */
+			case VGT_STRMOUT_BASE_OFFSET_0:
+			case VGT_STRMOUT_BASE_OFFSET_1:
+			case VGT_STRMOUT_BASE_OFFSET_2:
+			case VGT_STRMOUT_BASE_OFFSET_3:
+			case VGT_STRMOUT_BASE_OFFSET_HI_0:
+			case VGT_STRMOUT_BASE_OFFSET_HI_1:
+			case VGT_STRMOUT_BASE_OFFSET_HI_2:
+			case VGT_STRMOUT_BASE_OFFSET_HI_3:
+			case VGT_STRMOUT_BUFFER_BASE_0:
+			case VGT_STRMOUT_BUFFER_BASE_1:
+			case VGT_STRMOUT_BUFFER_BASE_2:
+			case VGT_STRMOUT_BUFFER_BASE_3:
+			case VGT_STRMOUT_BUFFER_OFFSET_0:
+			case VGT_STRMOUT_BUFFER_OFFSET_1:
+			case VGT_STRMOUT_BUFFER_OFFSET_2:
+			case VGT_STRMOUT_BUFFER_OFFSET_3:
+				/* These should be handled by STRMOUT_BUFFER packet 3 */
+				DRM_ERROR("bad context reg: 0x%08x\n", reg);
+				return -EINVAL;
+			default:
+				break;
+			}
+		}
+		break;
+	case PACKET3_SET_RESOURCE:
+		if (pkt->count % 7) {
+			DRM_ERROR("bad SET_RESOURCE\n");
+			return -EINVAL;
+		}
+		start_reg = (ib[idx+0] << 2) + PACKET3_SET_RESOURCE_OFFSET;
+		end_reg = 4 * pkt->count + start_reg - 4;
+		if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
+		    (start_reg >= PACKET3_SET_RESOURCE_END) ||
+		    (end_reg >= PACKET3_SET_RESOURCE_END)) {
+			DRM_ERROR("bad SET_RESOURCE\n");
+			return -EINVAL;
+		}
+		for (i = 0; i < (pkt->count / 7); i++) {
+			switch (G__SQ_VTX_CONSTANT_TYPE(ib[idx+(i*7)+6+1])) {
+			case SQ_TEX_VTX_VALID_TEXTURE:
+				/* tex base */
+				r = r600_cs_packet_next_reloc(p, &reloc);
+				if (r) {
+					DRM_ERROR("bad SET_RESOURCE\n");
+					return -EINVAL;
+				}
+				ib[idx+1+(i*7)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+				/* tex mip base */
+				r = r600_cs_packet_next_reloc(p, &reloc);
+				if (r) {
+					DRM_ERROR("bad SET_RESOURCE\n");
+					return -EINVAL;
+				}
+				ib[idx+1+(i*7)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+				break;
+			case SQ_TEX_VTX_VALID_BUFFER:
+				/* vtx base */
+				r = r600_cs_packet_next_reloc(p, &reloc);
+				if (r) {
+					DRM_ERROR("bad SET_RESOURCE\n");
+					return -EINVAL;
+				}
+				ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
+				ib[idx+1+(i*7)+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
+				break;
+			case SQ_TEX_VTX_INVALID_TEXTURE:
+			case SQ_TEX_VTX_INVALID_BUFFER:
+			default:
+				DRM_ERROR("bad SET_RESOURCE\n");
+				return -EINVAL;
+			}
+		}
+		break;
+	case PACKET3_SET_ALU_CONST:
+		start_reg = (ib[idx+0] << 2) + PACKET3_SET_ALU_CONST_OFFSET;
+		end_reg = 4 * pkt->count + start_reg - 4;
+		if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
+		    (start_reg >= PACKET3_SET_ALU_CONST_END) ||
+		    (end_reg >= PACKET3_SET_ALU_CONST_END)) {
+			DRM_ERROR("bad SET_ALU_CONST\n");
+			return -EINVAL;
+		}
+		break;
+	case PACKET3_SET_BOOL_CONST:
+		start_reg = (ib[idx+0] << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
+		end_reg = 4 * pkt->count + start_reg - 4;
+		if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
+		    (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
+		    (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
+			DRM_ERROR("bad SET_BOOL_CONST\n");
+			return -EINVAL;
+		}
+		break;
+	case PACKET3_SET_LOOP_CONST:
+		start_reg = (ib[idx+0] << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
+		end_reg = 4 * pkt->count + start_reg - 4;
+		if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
+		    (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
+		    (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
+			DRM_ERROR("bad SET_LOOP_CONST\n");
+			return -EINVAL;
+		}
+		break;
+	case PACKET3_SET_CTL_CONST:
+		start_reg = (ib[idx+0] << 2) + PACKET3_SET_CTL_CONST_OFFSET;
+		end_reg = 4 * pkt->count + start_reg - 4;
+		if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
+		    (start_reg >= PACKET3_SET_CTL_CONST_END) ||
+		    (end_reg >= PACKET3_SET_CTL_CONST_END)) {
+			DRM_ERROR("bad SET_CTL_CONST\n");
+			return -EINVAL;
+		}
+		break;
+	case PACKET3_SET_SAMPLER:
+		if (pkt->count % 3) {
+			DRM_ERROR("bad SET_SAMPLER\n");
+			return -EINVAL;
+		}
+		start_reg = (ib[idx+0] << 2) + PACKET3_SET_SAMPLER_OFFSET;
+		end_reg = 4 * pkt->count + start_reg - 4;
+		if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
+		    (start_reg >= PACKET3_SET_SAMPLER_END) ||
+		    (end_reg >= PACKET3_SET_SAMPLER_END)) {
+			DRM_ERROR("bad SET_SAMPLER\n");
+			return -EINVAL;
+		}
+		break;
+	case PACKET3_SURFACE_BASE_UPDATE:
+		if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
+			DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
+			return -EINVAL;
+		}
+		if (pkt->count) {
+			DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
+			return -EINVAL;
+		}
+		break;
+	case PACKET3_NOP:
+		break;
+	default:
+		DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
+		return -EINVAL;
+	}
+	return 0;
+}
+
+int r600_cs_parse(struct radeon_cs_parser *p)
+{
+	struct radeon_cs_packet pkt;
+	int r;
+
+	do {
+		r = r600_cs_packet_parse(p, &pkt, p->idx);
+		if (r) {
+			return r;
+		}
+		p->idx += pkt.count + 2;
+		switch (pkt.type) {
+		case PACKET_TYPE0:
+			r = r600_cs_parse_packet0(p, &pkt);
+			break;
+		case PACKET_TYPE2:
+			break;
+		case PACKET_TYPE3:
+			r = r600_packet3_check(p, &pkt);
+			break;
+		default:
+			DRM_ERROR("Unknown packet type %d !\n", pkt.type);
+			return -EINVAL;
+		}
+		if (r) {
+			return r;
+		}
+	} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
+#if 0
+	for (r = 0; r < p->ib->length_dw; r++) {
+		printk(KERN_INFO "%05d  0x%08X\n", r, p->ib->ptr[r]);
+		mdelay(1);
+	}
+#endif
+	return 0;
+}
+
+static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
+{
+	if (p->chunk_relocs_idx == -1) {
+		return 0;
+	}
+	p->relocs = kcalloc(1, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
+	if (p->relocs == NULL) {
+		return -ENOMEM;
+	}
+	return 0;
+}
+
+/**
+ * cs_parser_fini() - clean parser states
+ * @parser:	parser structure holding parsing context.
+ * @error:	error number
+ *
+ * If error is set than unvalidate buffer, otherwise just free memory
+ * used by parsing context.
+ **/
+static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
+{
+	unsigned i;
+
+	kfree(parser->relocs);
+	for (i = 0; i < parser->nchunks; i++) {
+		kfree(parser->chunks[i].kdata);
+	}
+	kfree(parser->chunks);
+	kfree(parser->chunks_array);
+}
+
+int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
+			unsigned family, u32 *ib, int *l)
+{
+	struct radeon_cs_parser parser;
+	struct radeon_cs_chunk *ib_chunk;
+	struct radeon_ib	fake_ib;
+	int r;
+
+	/* initialize parser */
+	memset(&parser, 0, sizeof(struct radeon_cs_parser));
+	parser.filp = filp;
+	parser.rdev = NULL;
+	parser.family = family;
+	parser.ib = &fake_ib;
+	fake_ib.ptr = ib;
+	r = radeon_cs_parser_init(&parser, data);
+	if (r) {
+		DRM_ERROR("Failed to initialize parser !\n");
+		r600_cs_parser_fini(&parser, r);
+		return r;
+	}
+	r = r600_cs_parser_relocs_legacy(&parser);
+	if (r) {
+		DRM_ERROR("Failed to parse relocation !\n");
+		r600_cs_parser_fini(&parser, r);
+		return r;
+	}
+	/* Copy the packet into the IB, the parser will read from the
+	 * input memory (cached) and write to the IB (which can be
+	 * uncached). */
+	ib_chunk = &parser.chunks[parser.chunk_ib_idx];
+	parser.ib->length_dw = ib_chunk->length_dw;
+	memcpy((void *)parser.ib->ptr, ib_chunk->kdata, ib_chunk->length_dw*4);
+	*l = parser.ib->length_dw;
+	r = r600_cs_parse(&parser);
+	if (r) {
+		DRM_ERROR("Invalid command stream !\n");
+		r600_cs_parser_fini(&parser, r);
+		return r;
+	}
+	r600_cs_parser_fini(&parser, r);
+	return r;
+}
+
+void r600_cs_legacy_init(void)
+{
+	r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
+}
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
new file mode 100644
index 00000000000..723295f5928
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -0,0 +1,661 @@
+/*
+ * Copyright 2009 Advanced Micro Devices, Inc.
+ * Copyright 2009 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#ifndef R600D_H
+#define R600D_H
+
+#define CP_PACKET2			0x80000000
+#define		PACKET2_PAD_SHIFT		0
+#define		PACKET2_PAD_MASK		(0x3fffffff << 0)
+
+#define PACKET2(v)	(CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
+
+#define R6XX_MAX_SH_GPRS			256
+#define R6XX_MAX_TEMP_GPRS			16
+#define R6XX_MAX_SH_THREADS			256
+#define R6XX_MAX_SH_STACK_ENTRIES		4096
+#define R6XX_MAX_BACKENDS			8
+#define R6XX_MAX_BACKENDS_MASK			0xff
+#define R6XX_MAX_SIMDS				8
+#define R6XX_MAX_SIMDS_MASK			0xff
+#define R6XX_MAX_PIPES				8
+#define R6XX_MAX_PIPES_MASK			0xff
+
+/* PTE flags */
+#define PTE_VALID				(1 << 0)
+#define PTE_SYSTEM				(1 << 1)
+#define PTE_SNOOPED				(1 << 2)
+#define PTE_READABLE				(1 << 5)
+#define PTE_WRITEABLE				(1 << 6)
+
+/* Registers */
+#define	ARB_POP						0x2418
+#define 	ENABLE_TC128					(1 << 30)
+#define	ARB_GDEC_RD_CNTL				0x246C
+
+#define	CC_GC_SHADER_PIPE_CONFIG			0x8950
+#define	CC_RB_BACKEND_DISABLE				0x98F4
+#define		BACKEND_DISABLE(x)				((x) << 16)
+
+#define	CB_COLOR0_BASE					0x28040
+#define	CB_COLOR1_BASE					0x28044
+#define	CB_COLOR2_BASE					0x28048
+#define	CB_COLOR3_BASE					0x2804C
+#define	CB_COLOR4_BASE					0x28050
+#define	CB_COLOR5_BASE					0x28054
+#define	CB_COLOR6_BASE					0x28058
+#define	CB_COLOR7_BASE					0x2805C
+#define	CB_COLOR7_FRAG					0x280FC
+
+#define CB_COLOR0_SIZE                                  0x28060
+#define CB_COLOR0_VIEW                                  0x28080
+#define CB_COLOR0_INFO                                  0x280a0
+#define CB_COLOR0_TILE                                  0x280c0
+#define CB_COLOR0_FRAG                                  0x280e0
+#define CB_COLOR0_MASK                                  0x28100
+
+#define	CONFIG_MEMSIZE					0x5428
+#define	CP_STAT						0x8680
+#define	CP_COHER_BASE					0x85F8
+#define	CP_DEBUG					0xC1FC
+#define	R_0086D8_CP_ME_CNTL			0x86D8
+#define		S_0086D8_CP_ME_HALT(x)			(((x) & 1)<<28)
+#define		C_0086D8_CP_ME_HALT(x)			((x) & 0xEFFFFFFF)
+#define	CP_ME_RAM_DATA					0xC160
+#define	CP_ME_RAM_RADDR					0xC158
+#define	CP_ME_RAM_WADDR					0xC15C
+#define CP_MEQ_THRESHOLDS				0x8764
+#define		MEQ_END(x)					((x) << 16)
+#define		ROQ_END(x)					((x) << 24)
+#define	CP_PERFMON_CNTL					0x87FC
+#define	CP_PFP_UCODE_ADDR				0xC150
+#define	CP_PFP_UCODE_DATA				0xC154
+#define	CP_QUEUE_THRESHOLDS				0x8760
+#define		ROQ_IB1_START(x)				((x) << 0)
+#define		ROQ_IB2_START(x)				((x) << 8)
+#define	CP_RB_BASE					0xC100
+#define	CP_RB_CNTL					0xC104
+#define		RB_BUFSZ(x)					((x)<<0)
+#define		RB_BLKSZ(x)					((x)<<8)
+#define		RB_NO_UPDATE					(1<<27)
+#define		RB_RPTR_WR_ENA					(1<<31)
+#define		BUF_SWAP_32BIT					(2 << 16)
+#define	CP_RB_RPTR					0x8700
+#define	CP_RB_RPTR_ADDR					0xC10C
+#define	CP_RB_RPTR_ADDR_HI				0xC110
+#define	CP_RB_RPTR_WR					0xC108
+#define	CP_RB_WPTR					0xC114
+#define	CP_RB_WPTR_ADDR					0xC118
+#define	CP_RB_WPTR_ADDR_HI				0xC11C
+#define	CP_RB_WPTR_DELAY				0x8704
+#define	CP_ROQ_IB1_STAT					0x8784
+#define	CP_ROQ_IB2_STAT					0x8788
+#define	CP_SEM_WAIT_TIMER				0x85BC
+
+#define	DB_DEBUG					0x9830
+#define		PREZ_MUST_WAIT_FOR_POSTZ_DONE			(1 << 31)
+#define	DB_DEPTH_BASE					0x2800C
+#define	DB_WATERMARKS					0x9838
+#define		DEPTH_FREE(x)					((x) << 0)
+#define		DEPTH_FLUSH(x)					((x) << 5)
+#define		DEPTH_PENDING_FREE(x)				((x) << 15)
+#define		DEPTH_CACHELINE_FREE(x)				((x) << 20)
+
+#define	DCP_TILING_CONFIG				0x6CA0
+#define		PIPE_TILING(x)					((x) << 1)
+#define 	BANK_TILING(x)					((x) << 4)
+#define		GROUP_SIZE(x)					((x) << 6)
+#define		ROW_TILING(x)					((x) << 8)
+#define		BANK_SWAPS(x)					((x) << 11)
+#define		SAMPLE_SPLIT(x)					((x) << 14)
+#define		BACKEND_MAP(x)					((x) << 16)
+
+#define GB_TILING_CONFIG				0x98F0
+
+#define	GC_USER_SHADER_PIPE_CONFIG			0x8954
+#define		INACTIVE_QD_PIPES(x)				((x) << 8)
+#define		INACTIVE_QD_PIPES_MASK				0x0000FF00
+#define		INACTIVE_SIMDS(x)				((x) << 16)
+#define		INACTIVE_SIMDS_MASK				0x00FF0000
+
+#define SQ_CONFIG                                         0x8c00
+#       define VC_ENABLE                                  (1 << 0)
+#       define EXPORT_SRC_C                               (1 << 1)
+#       define DX9_CONSTS                                 (1 << 2)
+#       define ALU_INST_PREFER_VECTOR                     (1 << 3)
+#       define DX10_CLAMP                                 (1 << 4)
+#       define CLAUSE_SEQ_PRIO(x)                         ((x) << 8)
+#       define PS_PRIO(x)                                 ((x) << 24)
+#       define VS_PRIO(x)                                 ((x) << 26)
+#       define GS_PRIO(x)                                 ((x) << 28)
+#       define ES_PRIO(x)                                 ((x) << 30)
+#define SQ_GPR_RESOURCE_MGMT_1                            0x8c04
+#       define NUM_PS_GPRS(x)                             ((x) << 0)
+#       define NUM_VS_GPRS(x)                             ((x) << 16)
+#       define NUM_CLAUSE_TEMP_GPRS(x)                    ((x) << 28)
+#define SQ_GPR_RESOURCE_MGMT_2                            0x8c08
+#       define NUM_GS_GPRS(x)                             ((x) << 0)
+#       define NUM_ES_GPRS(x)                             ((x) << 16)
+#define SQ_THREAD_RESOURCE_MGMT                           0x8c0c
+#       define NUM_PS_THREADS(x)                          ((x) << 0)
+#       define NUM_VS_THREADS(x)                          ((x) << 8)
+#       define NUM_GS_THREADS(x)                          ((x) << 16)
+#       define NUM_ES_THREADS(x)                          ((x) << 24)
+#define SQ_STACK_RESOURCE_MGMT_1                          0x8c10
+#       define NUM_PS_STACK_ENTRIES(x)                    ((x) << 0)
+#       define NUM_VS_STACK_ENTRIES(x)                    ((x) << 16)
+#define SQ_STACK_RESOURCE_MGMT_2                          0x8c14
+#       define NUM_GS_STACK_ENTRIES(x)                    ((x) << 0)
+#       define NUM_ES_STACK_ENTRIES(x)                    ((x) << 16)
+
+#define GRBM_CNTL                                       0x8000
+#       define GRBM_READ_TIMEOUT(x)                     ((x) << 0)
+#define	GRBM_STATUS					0x8010
+#define		CMDFIFO_AVAIL_MASK				0x0000001F
+#define		GUI_ACTIVE					(1<<31)
+#define	GRBM_STATUS2					0x8014
+#define	GRBM_SOFT_RESET					0x8020
+#define		SOFT_RESET_CP					(1<<0)
+
+#define	HDP_HOST_PATH_CNTL				0x2C00
+#define	HDP_NONSURFACE_BASE				0x2C04
+#define	HDP_NONSURFACE_INFO				0x2C08
+#define	HDP_NONSURFACE_SIZE				0x2C0C
+#define HDP_REG_COHERENCY_FLUSH_CNTL			0x54A0
+#define	HDP_TILING_CONFIG				0x2F3C
+
+#define MC_VM_AGP_TOP					0x2184
+#define MC_VM_AGP_BOT					0x2188
+#define	MC_VM_AGP_BASE					0x218C
+#define MC_VM_FB_LOCATION				0x2180
+#define MC_VM_L1_TLB_MCD_RD_A_CNTL			0x219C
+#define 	ENABLE_L1_TLB					(1 << 0)
+#define		ENABLE_L1_FRAGMENT_PROCESSING			(1 << 1)
+#define		ENABLE_L1_STRICT_ORDERING			(1 << 2)
+#define		SYSTEM_ACCESS_MODE_MASK				0x000000C0
+#define		SYSTEM_ACCESS_MODE_SHIFT			6
+#define		SYSTEM_ACCESS_MODE_PA_ONLY			(0 << 6)
+#define		SYSTEM_ACCESS_MODE_USE_SYS_MAP			(1 << 6)
+#define		SYSTEM_ACCESS_MODE_IN_SYS			(2 << 6)
+#define		SYSTEM_ACCESS_MODE_NOT_IN_SYS			(3 << 6)
+#define		SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU	(0 << 8)
+#define		SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE	(1 << 8)
+#define		ENABLE_SEMAPHORE_MODE				(1 << 10)
+#define		ENABLE_WAIT_L2_QUERY				(1 << 11)
+#define		EFFECTIVE_L1_TLB_SIZE(x)			(((x) & 7) << 12)
+#define		EFFECTIVE_L1_TLB_SIZE_MASK			0x00007000
+#define		EFFECTIVE_L1_TLB_SIZE_SHIFT			12
+#define		EFFECTIVE_L1_QUEUE_SIZE(x)			(((x) & 7) << 15)
+#define		EFFECTIVE_L1_QUEUE_SIZE_MASK			0x00038000
+#define		EFFECTIVE_L1_QUEUE_SIZE_SHIFT			15
+#define MC_VM_L1_TLB_MCD_RD_B_CNTL			0x21A0
+#define MC_VM_L1_TLB_MCB_RD_GFX_CNTL			0x21FC
+#define MC_VM_L1_TLB_MCB_RD_HDP_CNTL			0x2204
+#define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL			0x2208
+#define MC_VM_L1_TLB_MCB_RD_SEM_CNTL			0x220C
+#define	MC_VM_L1_TLB_MCB_RD_SYS_CNTL			0x2200
+#define MC_VM_L1_TLB_MCD_WR_A_CNTL			0x21A4
+#define MC_VM_L1_TLB_MCD_WR_B_CNTL			0x21A8
+#define MC_VM_L1_TLB_MCB_WR_GFX_CNTL			0x2210
+#define MC_VM_L1_TLB_MCB_WR_HDP_CNTL			0x2218
+#define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL			0x221C
+#define MC_VM_L1_TLB_MCB_WR_SEM_CNTL			0x2220
+#define MC_VM_L1_TLB_MCB_WR_SYS_CNTL			0x2214
+#define MC_VM_SYSTEM_APERTURE_LOW_ADDR			0x2190
+#define		LOGICAL_PAGE_NUMBER_MASK			0x000FFFFF
+#define		LOGICAL_PAGE_NUMBER_SHIFT			0
+#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR			0x2194
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR		0x2198
+
+#define	PA_CL_ENHANCE					0x8A14
+#define		CLIP_VTX_REORDER_ENA				(1 << 0)
+#define		NUM_CLIP_SEQ(x)					((x) << 1)
+#define PA_SC_AA_CONFIG					0x28C04
+#define	PA_SC_AA_SAMPLE_LOCS_2S				0x8B40
+#define	PA_SC_AA_SAMPLE_LOCS_4S				0x8B44
+#define	PA_SC_AA_SAMPLE_LOCS_8S_WD0			0x8B48
+#define	PA_SC_AA_SAMPLE_LOCS_8S_WD1			0x8B4C
+#define		S0_X(x)						((x) << 0)
+#define		S0_Y(x)						((x) << 4)
+#define		S1_X(x)						((x) << 8)
+#define		S1_Y(x)						((x) << 12)
+#define		S2_X(x)						((x) << 16)
+#define		S2_Y(x)						((x) << 20)
+#define		S3_X(x)						((x) << 24)
+#define		S3_Y(x)						((x) << 28)
+#define		S4_X(x)						((x) << 0)
+#define		S4_Y(x)						((x) << 4)
+#define		S5_X(x)						((x) << 8)
+#define		S5_Y(x)						((x) << 12)
+#define		S6_X(x)						((x) << 16)
+#define		S6_Y(x)						((x) << 20)
+#define		S7_X(x)						((x) << 24)
+#define		S7_Y(x)						((x) << 28)
+#define PA_SC_CLIPRECT_RULE				0x2820c
+#define	PA_SC_ENHANCE					0x8BF0
+#define		FORCE_EOV_MAX_CLK_CNT(x)			((x) << 0)
+#define		FORCE_EOV_MAX_TILE_CNT(x)			((x) << 12)
+#define PA_SC_LINE_STIPPLE				0x28A0C
+#define	PA_SC_LINE_STIPPLE_STATE			0x8B10
+#define PA_SC_MODE_CNTL					0x28A4C
+#define	PA_SC_MULTI_CHIP_CNTL				0x8B20
+
+#define PA_SC_SCREEN_SCISSOR_TL                         0x28030
+#define PA_SC_GENERIC_SCISSOR_TL                        0x28240
+#define PA_SC_WINDOW_SCISSOR_TL                         0x28204
+
+#define	PCIE_PORT_INDEX					0x0038
+#define	PCIE_PORT_DATA					0x003C
+
+#define RAMCFG						0x2408
+#define		NOOFBANK_SHIFT					0
+#define		NOOFBANK_MASK					0x00000001
+#define		NOOFRANK_SHIFT					1
+#define		NOOFRANK_MASK					0x00000002
+#define		NOOFROWS_SHIFT					2
+#define		NOOFROWS_MASK					0x0000001C
+#define		NOOFCOLS_SHIFT					5
+#define		NOOFCOLS_MASK					0x00000060
+#define		CHANSIZE_SHIFT					7
+#define		CHANSIZE_MASK					0x00000080
+#define		BURSTLENGTH_SHIFT				8
+#define		BURSTLENGTH_MASK				0x00000100
+#define		CHANSIZE_OVERRIDE				(1 << 10)
+
+#define	SCRATCH_REG0					0x8500
+#define	SCRATCH_REG1					0x8504
+#define	SCRATCH_REG2					0x8508
+#define	SCRATCH_REG3					0x850C
+#define	SCRATCH_REG4					0x8510
+#define	SCRATCH_REG5					0x8514
+#define	SCRATCH_REG6					0x8518
+#define	SCRATCH_REG7					0x851C
+#define	SCRATCH_UMSK					0x8540
+#define	SCRATCH_ADDR					0x8544
+
+#define	SPI_CONFIG_CNTL					0x9100
+#define		GPR_WRITE_PRIORITY(x)				((x) << 0)
+#define		DISABLE_INTERP_1				(1 << 5)
+#define	SPI_CONFIG_CNTL_1				0x913C
+#define		VTX_DONE_DELAY(x)				((x) << 0)
+#define		INTERP_ONE_PRIM_PER_ROW				(1 << 4)
+#define	SPI_INPUT_Z					0x286D8
+#define	SPI_PS_IN_CONTROL_0				0x286CC
+#define		NUM_INTERP(x)					((x)<<0)
+#define		POSITION_ENA					(1<<8)
+#define		POSITION_CENTROID				(1<<9)
+#define		POSITION_ADDR(x)				((x)<<10)
+#define		PARAM_GEN(x)					((x)<<15)
+#define		PARAM_GEN_ADDR(x)				((x)<<19)
+#define		BARYC_SAMPLE_CNTL(x)				((x)<<26)
+#define		PERSP_GRADIENT_ENA				(1<<28)
+#define		LINEAR_GRADIENT_ENA				(1<<29)
+#define		POSITION_SAMPLE					(1<<30)
+#define		BARYC_AT_SAMPLE_ENA				(1<<31)
+#define	SPI_PS_IN_CONTROL_1				0x286D0
+#define		GEN_INDEX_PIX					(1<<0)
+#define		GEN_INDEX_PIX_ADDR(x)				((x)<<1)
+#define		FRONT_FACE_ENA					(1<<8)
+#define		FRONT_FACE_CHAN(x)				((x)<<9)
+#define		FRONT_FACE_ALL_BITS				(1<<11)
+#define		FRONT_FACE_ADDR(x)				((x)<<12)
+#define		FOG_ADDR(x)					((x)<<17)
+#define		FIXED_PT_POSITION_ENA				(1<<24)
+#define		FIXED_PT_POSITION_ADDR(x)			((x)<<25)
+
+#define	SQ_MS_FIFO_SIZES				0x8CF0
+#define		CACHE_FIFO_SIZE(x)				((x) << 0)
+#define		FETCH_FIFO_HIWATER(x)				((x) << 8)
+#define		DONE_FIFO_HIWATER(x)				((x) << 16)
+#define		ALU_UPDATE_FIFO_HIWATER(x)			((x) << 24)
+#define	SQ_PGM_START_ES					0x28880
+#define	SQ_PGM_START_FS					0x28894
+#define	SQ_PGM_START_GS					0x2886C
+#define	SQ_PGM_START_PS					0x28840
+#define SQ_PGM_RESOURCES_PS                             0x28850
+#define SQ_PGM_EXPORTS_PS                               0x28854
+#define SQ_PGM_CF_OFFSET_PS                             0x288cc
+#define	SQ_PGM_START_VS					0x28858
+#define SQ_PGM_RESOURCES_VS                             0x28868
+#define SQ_PGM_CF_OFFSET_VS                             0x288d0
+#define	SQ_VTX_CONSTANT_WORD6_0				0x38018
+#define		S__SQ_VTX_CONSTANT_TYPE(x)			(((x) & 3) << 30)
+#define		G__SQ_VTX_CONSTANT_TYPE(x)			(((x) >> 30) & 3)
+#define			SQ_TEX_VTX_INVALID_TEXTURE			0x0
+#define			SQ_TEX_VTX_INVALID_BUFFER			0x1
+#define			SQ_TEX_VTX_VALID_TEXTURE			0x2
+#define			SQ_TEX_VTX_VALID_BUFFER				0x3
+
+
+#define	SX_MISC						0x28350
+#define	SX_DEBUG_1					0x9054
+#define		SMX_EVENT_RELEASE				(1 << 0)
+#define		ENABLE_NEW_SMX_ADDRESS				(1 << 16)
+
+#define	TA_CNTL_AUX					0x9508
+#define		DISABLE_CUBE_WRAP				(1 << 0)
+#define		DISABLE_CUBE_ANISO				(1 << 1)
+#define		SYNC_GRADIENT					(1 << 24)
+#define		SYNC_WALKER					(1 << 25)
+#define		SYNC_ALIGNER					(1 << 26)
+#define		BILINEAR_PRECISION_6_BIT			(0 << 31)
+#define		BILINEAR_PRECISION_8_BIT			(1 << 31)
+
+#define	TC_CNTL						0x9608
+#define		TC_L2_SIZE(x)					((x)<<5)
+#define		L2_DISABLE_LATE_HIT				(1<<9)
+
+
+#define	VGT_CACHE_INVALIDATION				0x88C4
+#define		CACHE_INVALIDATION(x)				((x)<<0)
+#define			VC_ONLY						0
+#define			TC_ONLY						1
+#define			VC_AND_TC					2
+#define	VGT_DMA_BASE					0x287E8
+#define	VGT_DMA_BASE_HI					0x287E4
+#define	VGT_ES_PER_GS					0x88CC
+#define	VGT_GS_PER_ES					0x88C8
+#define	VGT_GS_PER_VS					0x88E8
+#define	VGT_GS_VERTEX_REUSE				0x88D4
+#define VGT_PRIMITIVE_TYPE                              0x8958
+#define	VGT_NUM_INSTANCES				0x8974
+#define	VGT_OUT_DEALLOC_CNTL				0x28C5C
+#define		DEALLOC_DIST_MASK				0x0000007F
+#define	VGT_STRMOUT_BASE_OFFSET_0			0x28B10
+#define	VGT_STRMOUT_BASE_OFFSET_1			0x28B14
+#define	VGT_STRMOUT_BASE_OFFSET_2			0x28B18
+#define	VGT_STRMOUT_BASE_OFFSET_3			0x28B1c
+#define	VGT_STRMOUT_BASE_OFFSET_HI_0			0x28B44
+#define	VGT_STRMOUT_BASE_OFFSET_HI_1			0x28B48
+#define	VGT_STRMOUT_BASE_OFFSET_HI_2			0x28B4c
+#define	VGT_STRMOUT_BASE_OFFSET_HI_3			0x28B50
+#define	VGT_STRMOUT_BUFFER_BASE_0			0x28AD8
+#define	VGT_STRMOUT_BUFFER_BASE_1			0x28AE8
+#define	VGT_STRMOUT_BUFFER_BASE_2			0x28AF8
+#define	VGT_STRMOUT_BUFFER_BASE_3			0x28B08
+#define	VGT_STRMOUT_BUFFER_OFFSET_0			0x28ADC
+#define	VGT_STRMOUT_BUFFER_OFFSET_1			0x28AEC
+#define	VGT_STRMOUT_BUFFER_OFFSET_2			0x28AFC
+#define	VGT_STRMOUT_BUFFER_OFFSET_3			0x28B0C
+#define	VGT_STRMOUT_EN					0x28AB0
+#define	VGT_VERTEX_REUSE_BLOCK_CNTL			0x28C58
+#define		VTX_REUSE_DEPTH_MASK				0x000000FF
+#define VGT_EVENT_INITIATOR                             0x28a90
+#       define CACHE_FLUSH_AND_INV_EVENT                        (0x16 << 0)
+
+#define VM_CONTEXT0_CNTL				0x1410
+#define		ENABLE_CONTEXT					(1 << 0)
+#define		PAGE_TABLE_DEPTH(x)				(((x) & 3) << 1)
+#define		RANGE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 4)
+#define VM_CONTEXT0_INVALIDATION_LOW_ADDR		0x1490
+#define VM_CONTEXT0_INVALIDATION_HIGH_ADDR		0x14B0
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR		0x1574
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR		0x1594
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR			0x15B4
+#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR	0x1554
+#define VM_CONTEXT0_REQUEST_RESPONSE			0x1470
+#define		REQUEST_TYPE(x)					(((x) & 0xf) << 0)
+#define		RESPONSE_TYPE_MASK				0x000000F0
+#define		RESPONSE_TYPE_SHIFT				4
+#define VM_L2_CNTL					0x1400
+#define		ENABLE_L2_CACHE					(1 << 0)
+#define		ENABLE_L2_FRAGMENT_PROCESSING			(1 << 1)
+#define		ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE		(1 << 9)
+#define		EFFECTIVE_L2_QUEUE_SIZE(x)			(((x) & 7) << 13)
+#define VM_L2_CNTL2					0x1404
+#define		INVALIDATE_ALL_L1_TLBS				(1 << 0)
+#define		INVALIDATE_L2_CACHE				(1 << 1)
+#define VM_L2_CNTL3					0x1408
+#define		BANK_SELECT_0(x)				(((x) & 0x1f) << 0)
+#define		BANK_SELECT_1(x)				(((x) & 0x1f) << 5)
+#define		L2_CACHE_UPDATE_MODE(x)				(((x) & 3) << 10)
+#define	VM_L2_STATUS					0x140C
+#define		L2_BUSY						(1 << 0)
+
+#define	WAIT_UNTIL					0x8040
+#define         WAIT_2D_IDLE_bit                                (1 << 14)
+#define         WAIT_3D_IDLE_bit                                (1 << 15)
+#define         WAIT_2D_IDLECLEAN_bit                           (1 << 16)
+#define         WAIT_3D_IDLECLEAN_bit                           (1 << 17)
+
+
+
+/*
+ * PM4
+ */
+#define	PACKET_TYPE0	0
+#define	PACKET_TYPE1	1
+#define	PACKET_TYPE2	2
+#define	PACKET_TYPE3	3
+
+#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
+#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
+#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
+#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
+#define PACKET0(reg, n)	((PACKET_TYPE0 << 30) |				\
+			 (((reg) >> 2) & 0xFFFF) |			\
+			 ((n) & 0x3FFF) << 16)
+#define PACKET3(op, n)	((PACKET_TYPE3 << 30) |				\
+			 (((op) & 0xFF) << 8) |				\
+			 ((n) & 0x3FFF) << 16)
+
+/* Packet 3 types */
+#define	PACKET3_NOP					0x10
+#define	PACKET3_INDIRECT_BUFFER_END			0x17
+#define	PACKET3_SET_PREDICATION				0x20
+#define	PACKET3_REG_RMW					0x21
+#define	PACKET3_COND_EXEC				0x22
+#define	PACKET3_PRED_EXEC				0x23
+#define	PACKET3_START_3D_CMDBUF				0x24
+#define	PACKET3_DRAW_INDEX_2				0x27
+#define	PACKET3_CONTEXT_CONTROL				0x28
+#define	PACKET3_DRAW_INDEX_IMMD_BE			0x29
+#define	PACKET3_INDEX_TYPE				0x2A
+#define	PACKET3_DRAW_INDEX				0x2B
+#define	PACKET3_DRAW_INDEX_AUTO				0x2D
+#define	PACKET3_DRAW_INDEX_IMMD				0x2E
+#define	PACKET3_NUM_INSTANCES				0x2F
+#define	PACKET3_STRMOUT_BUFFER_UPDATE			0x34
+#define	PACKET3_INDIRECT_BUFFER_MP			0x38
+#define	PACKET3_MEM_SEMAPHORE				0x39
+#define	PACKET3_MPEG_INDEX				0x3A
+#define	PACKET3_WAIT_REG_MEM				0x3C
+#define	PACKET3_MEM_WRITE				0x3D
+#define	PACKET3_INDIRECT_BUFFER				0x32
+#define	PACKET3_CP_INTERRUPT				0x40
+#define	PACKET3_SURFACE_SYNC				0x43
+#              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)
+#              define PACKET3_TC_ACTION_ENA        (1 << 23)
+#              define PACKET3_VC_ACTION_ENA        (1 << 24)
+#              define PACKET3_CB_ACTION_ENA        (1 << 25)
+#              define PACKET3_DB_ACTION_ENA        (1 << 26)
+#              define PACKET3_SH_ACTION_ENA        (1 << 27)
+#              define PACKET3_SMX_ACTION_ENA       (1 << 28)
+#define	PACKET3_ME_INITIALIZE				0x44
+#define		PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
+#define	PACKET3_COND_WRITE				0x45
+#define	PACKET3_EVENT_WRITE				0x46
+#define	PACKET3_EVENT_WRITE_EOP				0x47
+#define	PACKET3_ONE_REG_WRITE				0x57
+#define	PACKET3_SET_CONFIG_REG				0x68
+#define		PACKET3_SET_CONFIG_REG_OFFSET			0x00008000
+#define		PACKET3_SET_CONFIG_REG_END			0x0000ac00
+#define	PACKET3_SET_CONTEXT_REG				0x69
+#define		PACKET3_SET_CONTEXT_REG_OFFSET			0x00028000
+#define		PACKET3_SET_CONTEXT_REG_END			0x00029000
+#define	PACKET3_SET_ALU_CONST				0x6A
+#define		PACKET3_SET_ALU_CONST_OFFSET			0x00030000
+#define		PACKET3_SET_ALU_CONST_END			0x00032000
+#define	PACKET3_SET_BOOL_CONST				0x6B
+#define		PACKET3_SET_BOOL_CONST_OFFSET			0x0003e380
+#define		PACKET3_SET_BOOL_CONST_END			0x00040000
+#define	PACKET3_SET_LOOP_CONST				0x6C
+#define		PACKET3_SET_LOOP_CONST_OFFSET			0x0003e200
+#define		PACKET3_SET_LOOP_CONST_END			0x0003e380
+#define	PACKET3_SET_RESOURCE				0x6D
+#define		PACKET3_SET_RESOURCE_OFFSET			0x00038000
+#define		PACKET3_SET_RESOURCE_END			0x0003c000
+#define	PACKET3_SET_SAMPLER				0x6E
+#define		PACKET3_SET_SAMPLER_OFFSET			0x0003c000
+#define		PACKET3_SET_SAMPLER_END				0x0003cff0
+#define	PACKET3_SET_CTL_CONST				0x6F
+#define		PACKET3_SET_CTL_CONST_OFFSET			0x0003cff0
+#define		PACKET3_SET_CTL_CONST_END			0x0003e200
+#define	PACKET3_SURFACE_BASE_UPDATE			0x73
+
+
+#define	R_008020_GRBM_SOFT_RESET		0x8020
+#define		S_008020_SOFT_RESET_CP(x)		(((x) & 1) << 0)
+#define		S_008020_SOFT_RESET_CB(x)		(((x) & 1) << 1)
+#define		S_008020_SOFT_RESET_CR(x)		(((x) & 1) << 2)
+#define		S_008020_SOFT_RESET_DB(x)		(((x) & 1) << 3)
+#define		S_008020_SOFT_RESET_PA(x)		(((x) & 1) << 5)
+#define		S_008020_SOFT_RESET_SC(x)		(((x) & 1) << 6)
+#define		S_008020_SOFT_RESET_SMX(x)		(((x) & 1) << 7)
+#define		S_008020_SOFT_RESET_SPI(x)		(((x) & 1) << 8)
+#define		S_008020_SOFT_RESET_SH(x)		(((x) & 1) << 9)
+#define		S_008020_SOFT_RESET_SX(x)		(((x) & 1) << 10)
+#define		S_008020_SOFT_RESET_TC(x)		(((x) & 1) << 11)
+#define		S_008020_SOFT_RESET_TA(x)		(((x) & 1) << 12)
+#define		S_008020_SOFT_RESET_VC(x)		(((x) & 1) << 13)
+#define		S_008020_SOFT_RESET_VGT(x)		(((x) & 1) << 14)
+#define	R_008010_GRBM_STATUS			0x8010
+#define		S_008010_CMDFIFO_AVAIL(x)		(((x) & 0x1F) << 0)
+#define		S_008010_CP_RQ_PENDING(x)		(((x) & 1) << 6)
+#define		S_008010_CF_RQ_PENDING(x)		(((x) & 1) << 7)
+#define		S_008010_PF_RQ_PENDING(x)		(((x) & 1) << 8)
+#define		S_008010_GRBM_EE_BUSY(x)		(((x) & 1) << 10)
+#define		S_008010_VC_BUSY(x)			(((x) & 1) << 11)
+#define		S_008010_DB03_CLEAN(x)			(((x) & 1) << 12)
+#define		S_008010_CB03_CLEAN(x)			(((x) & 1) << 13)
+#define		S_008010_VGT_BUSY_NO_DMA(x)		(((x) & 1) << 16)
+#define		S_008010_VGT_BUSY(x)			(((x) & 1) << 17)
+#define		S_008010_TA03_BUSY(x)			(((x) & 1) << 18)
+#define		S_008010_TC_BUSY(x)			(((x) & 1) << 19)
+#define		S_008010_SX_BUSY(x)			(((x) & 1) << 20)
+#define		S_008010_SH_BUSY(x)			(((x) & 1) << 21)
+#define		S_008010_SPI03_BUSY(x)			(((x) & 1) << 22)
+#define		S_008010_SMX_BUSY(x)			(((x) & 1) << 23)
+#define		S_008010_SC_BUSY(x)			(((x) & 1) << 24)
+#define		S_008010_PA_BUSY(x)			(((x) & 1) << 25)
+#define		S_008010_DB03_BUSY(x)			(((x) & 1) << 26)
+#define		S_008010_CR_BUSY(x)			(((x) & 1) << 27)
+#define		S_008010_CP_COHERENCY_BUSY(x)		(((x) & 1) << 28)
+#define		S_008010_CP_BUSY(x)			(((x) & 1) << 29)
+#define		S_008010_CB03_BUSY(x)			(((x) & 1) << 30)
+#define		S_008010_GUI_ACTIVE(x)			(((x) & 1) << 31)
+#define		G_008010_CMDFIFO_AVAIL(x)		(((x) >> 0) & 0x1F)
+#define		G_008010_CP_RQ_PENDING(x)		(((x) >> 6) & 1)
+#define		G_008010_CF_RQ_PENDING(x)		(((x) >> 7) & 1)
+#define		G_008010_PF_RQ_PENDING(x)		(((x) >> 8) & 1)
+#define		G_008010_GRBM_EE_BUSY(x)		(((x) >> 10) & 1)
+#define		G_008010_VC_BUSY(x)			(((x) >> 11) & 1)
+#define		G_008010_DB03_CLEAN(x)			(((x) >> 12) & 1)
+#define		G_008010_CB03_CLEAN(x)			(((x) >> 13) & 1)
+#define		G_008010_VGT_BUSY_NO_DMA(x)		(((x) >> 16) & 1)
+#define		G_008010_VGT_BUSY(x)			(((x) >> 17) & 1)
+#define		G_008010_TA03_BUSY(x)			(((x) >> 18) & 1)
+#define		G_008010_TC_BUSY(x)			(((x) >> 19) & 1)
+#define		G_008010_SX_BUSY(x)			(((x) >> 20) & 1)
+#define		G_008010_SH_BUSY(x)			(((x) >> 21) & 1)
+#define		G_008010_SPI03_BUSY(x)			(((x) >> 22) & 1)
+#define		G_008010_SMX_BUSY(x)			(((x) >> 23) & 1)
+#define		G_008010_SC_BUSY(x)			(((x) >> 24) & 1)
+#define		G_008010_PA_BUSY(x)			(((x) >> 25) & 1)
+#define		G_008010_DB03_BUSY(x)			(((x) >> 26) & 1)
+#define		G_008010_CR_BUSY(x)			(((x) >> 27) & 1)
+#define		G_008010_CP_COHERENCY_BUSY(x)		(((x) >> 28) & 1)
+#define		G_008010_CP_BUSY(x)			(((x) >> 29) & 1)
+#define		G_008010_CB03_BUSY(x)			(((x) >> 30) & 1)
+#define		G_008010_GUI_ACTIVE(x)			(((x) >> 31) & 1)
+#define	R_008014_GRBM_STATUS2			0x8014
+#define		S_008014_CR_CLEAN(x)			(((x) & 1) << 0)
+#define		S_008014_SMX_CLEAN(x)			(((x) & 1) << 1)
+#define		S_008014_SPI0_BUSY(x)			(((x) & 1) << 8)
+#define		S_008014_SPI1_BUSY(x)			(((x) & 1) << 9)
+#define		S_008014_SPI2_BUSY(x)			(((x) & 1) << 10)
+#define		S_008014_SPI3_BUSY(x)			(((x) & 1) << 11)
+#define		S_008014_TA0_BUSY(x)			(((x) & 1) << 12)
+#define		S_008014_TA1_BUSY(x)			(((x) & 1) << 13)
+#define		S_008014_TA2_BUSY(x)			(((x) & 1) << 14)
+#define		S_008014_TA3_BUSY(x)			(((x) & 1) << 15)
+#define		S_008014_DB0_BUSY(x)			(((x) & 1) << 16)
+#define		S_008014_DB1_BUSY(x)			(((x) & 1) << 17)
+#define		S_008014_DB2_BUSY(x)			(((x) & 1) << 18)
+#define		S_008014_DB3_BUSY(x)			(((x) & 1) << 19)
+#define		S_008014_CB0_BUSY(x)			(((x) & 1) << 20)
+#define		S_008014_CB1_BUSY(x)			(((x) & 1) << 21)
+#define		S_008014_CB2_BUSY(x)			(((x) & 1) << 22)
+#define		S_008014_CB3_BUSY(x)			(((x) & 1) << 23)
+#define		G_008014_CR_CLEAN(x)			(((x) >> 0) & 1)
+#define		G_008014_SMX_CLEAN(x)			(((x) >> 1) & 1)
+#define		G_008014_SPI0_BUSY(x)			(((x) >> 8) & 1)
+#define		G_008014_SPI1_BUSY(x)			(((x) >> 9) & 1)
+#define		G_008014_SPI2_BUSY(x)			(((x) >> 10) & 1)
+#define		G_008014_SPI3_BUSY(x)			(((x) >> 11) & 1)
+#define		G_008014_TA0_BUSY(x)			(((x) >> 12) & 1)
+#define		G_008014_TA1_BUSY(x)			(((x) >> 13) & 1)
+#define		G_008014_TA2_BUSY(x)			(((x) >> 14) & 1)
+#define		G_008014_TA3_BUSY(x)			(((x) >> 15) & 1)
+#define		G_008014_DB0_BUSY(x)			(((x) >> 16) & 1)
+#define		G_008014_DB1_BUSY(x)			(((x) >> 17) & 1)
+#define		G_008014_DB2_BUSY(x)			(((x) >> 18) & 1)
+#define		G_008014_DB3_BUSY(x)			(((x) >> 19) & 1)
+#define		G_008014_CB0_BUSY(x)			(((x) >> 20) & 1)
+#define		G_008014_CB1_BUSY(x)			(((x) >> 21) & 1)
+#define		G_008014_CB2_BUSY(x)			(((x) >> 22) & 1)
+#define		G_008014_CB3_BUSY(x)			(((x) >> 23) & 1)
+#define	R_000E50_SRBM_STATUS				0x0E50
+#define		G_000E50_RLC_RQ_PENDING(x)		(((x) >> 3) & 1)
+#define		G_000E50_RCU_RQ_PENDING(x)		(((x) >> 4) & 1)
+#define		G_000E50_GRBM_RQ_PENDING(x)		(((x) >> 5) & 1)
+#define		G_000E50_HI_RQ_PENDING(x)		(((x) >> 6) & 1)
+#define		G_000E50_IO_EXTERN_SIGNAL(x)		(((x) >> 7) & 1)
+#define		G_000E50_VMC_BUSY(x)			(((x) >> 8) & 1)
+#define		G_000E50_MCB_BUSY(x)			(((x) >> 9) & 1)
+#define		G_000E50_MCDZ_BUSY(x)			(((x) >> 10) & 1)
+#define		G_000E50_MCDY_BUSY(x)			(((x) >> 11) & 1)
+#define		G_000E50_MCDX_BUSY(x)			(((x) >> 12) & 1)
+#define		G_000E50_MCDW_BUSY(x)			(((x) >> 13) & 1)
+#define		G_000E50_SEM_BUSY(x)			(((x) >> 14) & 1)
+#define		G_000E50_RLC_BUSY(x)			(((x) >> 15) & 1)
+#define	R_000E60_SRBM_SOFT_RESET			0x0E60
+#define		S_000E60_SOFT_RESET_BIF(x)		(((x) & 1) << 1)
+#define		S_000E60_SOFT_RESET_CG(x)		(((x) & 1) << 2)
+#define		S_000E60_SOFT_RESET_CMC(x)		(((x) & 1) << 3)
+#define		S_000E60_SOFT_RESET_CSC(x)		(((x) & 1) << 4)
+#define		S_000E60_SOFT_RESET_DC(x)		(((x) & 1) << 5)
+#define		S_000E60_SOFT_RESET_GRBM(x)		(((x) & 1) << 8)
+#define		S_000E60_SOFT_RESET_HDP(x)		(((x) & 1) << 9)
+#define		S_000E60_SOFT_RESET_IH(x)		(((x) & 1) << 10)
+#define		S_000E60_SOFT_RESET_MC(x)		(((x) & 1) << 11)
+#define		S_000E60_SOFT_RESET_RLC(x)		(((x) & 1) << 13)
+#define		S_000E60_SOFT_RESET_ROM(x)		(((x) & 1) << 14)
+#define		S_000E60_SOFT_RESET_SEM(x)		(((x) & 1) << 15)
+#define		S_000E60_SOFT_RESET_TSC(x)		(((x) & 1) << 16)
+#define		S_000E60_SOFT_RESET_VMC(x)		(((x) & 1) << 17)
+
+#endif
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index e47f2fc294c..3299733ac30 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -50,8 +50,8 @@
 #include <linux/kref.h>
 
 #include "radeon_mode.h"
+#include "radeon_share.h"
 #include "radeon_reg.h"
-#include "r300.h"
 
 /*
  * Modules parameters.
@@ -112,10 +112,11 @@ enum radeon_family {
 	CHIP_RV635,
 	CHIP_RV670,
 	CHIP_RS780,
+	CHIP_RS880,
 	CHIP_RV770,
 	CHIP_RV730,
 	CHIP_RV710,
-	CHIP_RS880,
+	CHIP_RV740,
 	CHIP_LAST,
 };
 
@@ -152,10 +153,21 @@ struct radeon_device;
  */
 bool radeon_get_bios(struct radeon_device *rdev);
 
+
 /*
- * Clocks
+ * Dummy page
  */
+struct radeon_dummy_page {
+	struct page	*page;
+	dma_addr_t	addr;
+};
+int radeon_dummy_page_init(struct radeon_device *rdev);
+void radeon_dummy_page_fini(struct radeon_device *rdev);
+
 
+/*
+ * Clocks
+ */
 struct radeon_clock {
 	struct radeon_pll p1pll;
 	struct radeon_pll p2pll;
@@ -166,6 +178,7 @@ struct radeon_clock {
 	uint32_t default_sclk;
 };
 
+
 /*
  * Fences.
  */
@@ -332,14 +345,18 @@ struct radeon_mc {
 	resource_size_t		aper_size;
 	resource_size_t		aper_base;
 	resource_size_t		agp_base;
-	unsigned		gtt_location;
-	unsigned		gtt_size;
-	unsigned		vram_location;
 	/* for some chips with <= 32MB we need to lie
 	 * about vram size near mc fb location */
-	unsigned		mc_vram_size;
+	u64			mc_vram_size;
+	u64			gtt_location;
+	u64			gtt_size;
+	u64			gtt_start;
+	u64			gtt_end;
+	u64			vram_location;
+	u64			vram_start;
+	u64			vram_end;
 	unsigned		vram_width;
-	unsigned		real_vram_size;
+	u64			real_vram_size;
 	int			vram_mtrr;
 	bool			vram_is_ddr;
 };
@@ -411,6 +428,16 @@ struct radeon_cp {
 	bool			ready;
 };
 
+struct r600_blit {
+	struct radeon_object	*shader_obj;
+	u64 shader_gpu_addr;
+	u32 vs_offset, ps_offset;
+	u32 state_offset;
+	u32 state_len;
+	u32 vb_used, vb_total;
+	struct radeon_ib *vb_ib;
+};
+
 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
@@ -463,6 +490,7 @@ struct radeon_cs_parser {
 	int			chunk_relocs_idx;
 	struct radeon_ib	*ib;
 	void			*track;
+	unsigned		family;
 };
 
 struct radeon_cs_packet {
@@ -559,6 +587,9 @@ int r100_debugfs_cp_init(struct radeon_device *rdev);
  */
 struct radeon_asic {
 	int (*init)(struct radeon_device *rdev);
+	void (*fini)(struct radeon_device *rdev);
+	int (*resume)(struct radeon_device *rdev);
+	int (*suspend)(struct radeon_device *rdev);
 	void (*errata)(struct radeon_device *rdev);
 	void (*vram_info)(struct radeon_device *rdev);
 	int (*gpu_reset)(struct radeon_device *rdev);
@@ -573,7 +604,11 @@ struct radeon_asic {
 	int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
 	void (*cp_fini)(struct radeon_device *rdev);
 	void (*cp_disable)(struct radeon_device *rdev);
+	void (*cp_commit)(struct radeon_device *rdev);
 	void (*ring_start)(struct radeon_device *rdev);
+	int (*ring_test)(struct radeon_device *rdev);
+	void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
+	int (*ib_test)(struct radeon_device *rdev);
 	int (*irq_set)(struct radeon_device *rdev);
 	int (*irq_process)(struct radeon_device *rdev);
 	u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
@@ -613,6 +648,8 @@ struct r100_asic {
 union radeon_asic_config {
 	struct r300_asic	r300;
 	struct r100_asic	r100;
+	struct r600_asic	r600;
+	struct rv770_asic	rv770;
 };
 
 
@@ -698,12 +735,16 @@ struct radeon_device {
 	struct radeon_pm		pm;
 	struct mutex			cs_mutex;
 	struct radeon_wb		wb;
+	struct radeon_dummy_page	dummy_page;
 	bool				gpu_lockup;
 	bool				shutdown;
 	bool				suspend;
 	bool				need_dma32;
+	bool				new_init_path;
 	struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
-	const struct firmware *fw;	/* firmware */
+	const struct firmware *me_fw;	/* all family ME firmware */
+	const struct firmware *pfp_fw;	/* r6/700 PFP firmware */
+	struct r600_blit r600_blit;
 };
 
 int radeon_device_init(struct radeon_device *rdev,
@@ -713,6 +754,13 @@ int radeon_device_init(struct radeon_device *rdev,
 void radeon_device_fini(struct radeon_device *rdev);
 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
 
+/* r600 blit */
+int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
+void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
+void r600_kms_blit_copy(struct radeon_device *rdev,
+			u64 src_gpu_addr, u64 dst_gpu_addr,
+			int size_bytes);
+
 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
 {
 	if (reg < 0x10000)
@@ -740,6 +788,7 @@ static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32
 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
+#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
@@ -763,6 +812,7 @@ static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32
 		tmp_ |= ((val) & ~(mask));			\
 		WREG32_PLL(reg, tmp_);				\
 	} while (0)
+#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
 
 /*
  * Indirect registers accessor
@@ -827,51 +877,6 @@ void radeon_atombios_fini(struct radeon_device *rdev);
 /*
  * RING helpers.
  */
-#define CP_PACKET0			0x00000000
-#define		PACKET0_BASE_INDEX_SHIFT	0
-#define		PACKET0_BASE_INDEX_MASK		(0x1ffff << 0)
-#define		PACKET0_COUNT_SHIFT		16
-#define		PACKET0_COUNT_MASK		(0x3fff << 16)
-#define CP_PACKET1			0x40000000
-#define CP_PACKET2			0x80000000
-#define		PACKET2_PAD_SHIFT		0
-#define		PACKET2_PAD_MASK		(0x3fffffff << 0)
-#define CP_PACKET3			0xC0000000
-#define		PACKET3_IT_OPCODE_SHIFT		8
-#define		PACKET3_IT_OPCODE_MASK		(0xff << 8)
-#define		PACKET3_COUNT_SHIFT		16
-#define		PACKET3_COUNT_MASK		(0x3fff << 16)
-/* PACKET3 op code */
-#define		PACKET3_NOP			0x10
-#define		PACKET3_3D_DRAW_VBUF		0x28
-#define		PACKET3_3D_DRAW_IMMD		0x29
-#define		PACKET3_3D_DRAW_INDX		0x2A
-#define		PACKET3_3D_LOAD_VBPNTR		0x2F
-#define		PACKET3_INDX_BUFFER		0x33
-#define		PACKET3_3D_DRAW_VBUF_2		0x34
-#define		PACKET3_3D_DRAW_IMMD_2		0x35
-#define		PACKET3_3D_DRAW_INDX_2		0x36
-#define		PACKET3_BITBLT_MULTI		0x9B
-
-#define PACKET0(reg, n)	(CP_PACKET0 |					\
-			 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) |	\
-			 REG_SET(PACKET0_COUNT, (n)))
-#define PACKET2(v)	(CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
-#define PACKET3(op, n)	(CP_PACKET3 |					\
-			 REG_SET(PACKET3_IT_OPCODE, (op)) |		\
-			 REG_SET(PACKET3_COUNT, (n)))
-
-#define	PACKET_TYPE0	0
-#define	PACKET_TYPE1	1
-#define	PACKET_TYPE2	2
-#define	PACKET_TYPE3	3
-
-#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
-#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
-#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
-#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
-#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
-
 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
 {
 #if DRM_DEBUG_CODE
@@ -890,6 +895,9 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
  * ASICs macro.
  */
 #define radeon_init(rdev) (rdev)->asic->init((rdev))
+#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
+#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
+#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
 #define radeon_errata(rdev) (rdev)->asic->errata((rdev))
 #define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
@@ -905,7 +913,11 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
 #define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
 #define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
 #define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
+#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
+#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
+#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
+#define radeon_ib_test(rdev) (rdev)->asic->ib_test((rdev))
 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index c9cbd8ae1f9..e87bb915a6d 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -60,6 +60,7 @@ int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
 void r100_cp_fini(struct radeon_device *rdev);
 void r100_cp_disable(struct radeon_device *rdev);
+void r100_cp_commit(struct radeon_device *rdev);
 void r100_ring_start(struct radeon_device *rdev);
 int r100_irq_set(struct radeon_device *rdev);
 int r100_irq_process(struct radeon_device *rdev);
@@ -78,6 +79,9 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg,
 			 uint32_t offset, uint32_t obj_size);
 int r100_clear_surface_reg(struct radeon_device *rdev, int reg);
 void r100_bandwidth_update(struct radeon_device *rdev);
+void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
+int r100_ib_test(struct radeon_device *rdev);
+int r100_ring_test(struct radeon_device *rdev);
 
 static struct radeon_asic r100_asic = {
 	.init = &r100_init,
@@ -95,7 +99,11 @@ static struct radeon_asic r100_asic = {
 	.cp_init = &r100_cp_init,
 	.cp_fini = &r100_cp_fini,
 	.cp_disable = &r100_cp_disable,
+	.cp_commit = &r100_cp_commit,
 	.ring_start = &r100_ring_start,
+	.ring_test = &r100_ring_test,
+	.ring_ib_execute = &r100_ring_ib_execute,
+	.ib_test = &r100_ib_test,
 	.irq_set = &r100_irq_set,
 	.irq_process = &r100_irq_process,
 	.get_vblank_counter = &r100_get_vblank_counter,
@@ -156,7 +164,11 @@ static struct radeon_asic r300_asic = {
 	.cp_init = &r100_cp_init,
 	.cp_fini = &r100_cp_fini,
 	.cp_disable = &r100_cp_disable,
+	.cp_commit = &r100_cp_commit,
 	.ring_start = &r300_ring_start,
+	.ring_test = &r100_ring_test,
+	.ring_ib_execute = &r100_ring_ib_execute,
+	.ib_test = &r100_ib_test,
 	.irq_set = &r100_irq_set,
 	.irq_process = &r100_irq_process,
 	.get_vblank_counter = &r100_get_vblank_counter,
@@ -197,7 +209,11 @@ static struct radeon_asic r420_asic = {
 	.cp_init = &r100_cp_init,
 	.cp_fini = &r100_cp_fini,
 	.cp_disable = &r100_cp_disable,
+	.cp_commit = &r100_cp_commit,
 	.ring_start = &r300_ring_start,
+	.ring_test = &r100_ring_test,
+	.ring_ib_execute = &r100_ring_ib_execute,
+	.ib_test = &r100_ib_test,
 	.irq_set = &r100_irq_set,
 	.irq_process = &r100_irq_process,
 	.get_vblank_counter = &r100_get_vblank_counter,
@@ -245,7 +261,11 @@ static struct radeon_asic rs400_asic = {
 	.cp_init = &r100_cp_init,
 	.cp_fini = &r100_cp_fini,
 	.cp_disable = &r100_cp_disable,
+	.cp_commit = &r100_cp_commit,
 	.ring_start = &r300_ring_start,
+	.ring_test = &r100_ring_test,
+	.ring_ib_execute = &r100_ring_ib_execute,
+	.ib_test = &r100_ib_test,
 	.irq_set = &r100_irq_set,
 	.irq_process = &r100_irq_process,
 	.get_vblank_counter = &r100_get_vblank_counter,
@@ -298,7 +318,11 @@ static struct radeon_asic rs600_asic = {
 	.cp_init = &r100_cp_init,
 	.cp_fini = &r100_cp_fini,
 	.cp_disable = &r100_cp_disable,
+	.cp_commit = &r100_cp_commit,
 	.ring_start = &r300_ring_start,
+	.ring_test = &r100_ring_test,
+	.ring_ib_execute = &r100_ring_ib_execute,
+	.ib_test = &r100_ib_test,
 	.irq_set = &rs600_irq_set,
 	.irq_process = &rs600_irq_process,
 	.get_vblank_counter = &rs600_get_vblank_counter,
@@ -341,7 +365,11 @@ static struct radeon_asic rs690_asic = {
 	.cp_init = &r100_cp_init,
 	.cp_fini = &r100_cp_fini,
 	.cp_disable = &r100_cp_disable,
+	.cp_commit = &r100_cp_commit,
 	.ring_start = &r300_ring_start,
+	.ring_test = &r100_ring_test,
+	.ring_ib_execute = &r100_ring_ib_execute,
+	.ib_test = &r100_ib_test,
 	.irq_set = &rs600_irq_set,
 	.irq_process = &rs600_irq_process,
 	.get_vblank_counter = &rs600_get_vblank_counter,
@@ -391,7 +419,11 @@ static struct radeon_asic rv515_asic = {
 	.cp_init = &r100_cp_init,
 	.cp_fini = &r100_cp_fini,
 	.cp_disable = &r100_cp_disable,
+	.cp_commit = &r100_cp_commit,
 	.ring_start = &rv515_ring_start,
+	.ring_test = &r100_ring_test,
+	.ring_ib_execute = &r100_ring_ib_execute,
+	.ib_test = &r100_ib_test,
 	.irq_set = &rs600_irq_set,
 	.irq_process = &rs600_irq_process,
 	.get_vblank_counter = &rs600_get_vblank_counter,
@@ -434,7 +466,11 @@ static struct radeon_asic r520_asic = {
 	.cp_init = &r100_cp_init,
 	.cp_fini = &r100_cp_fini,
 	.cp_disable = &r100_cp_disable,
+	.cp_commit = &r100_cp_commit,
 	.ring_start = &rv515_ring_start,
+	.ring_test = &r100_ring_test,
+	.ring_ib_execute = &r100_ring_ib_execute,
+	.ib_test = &r100_ib_test,
 	.irq_set = &rs600_irq_set,
 	.irq_process = &rs600_irq_process,
 	.get_vblank_counter = &rs600_get_vblank_counter,
@@ -453,9 +489,127 @@ static struct radeon_asic r520_asic = {
 };
 
 /*
- * r600,rv610,rv630,rv620,rv635,rv670,rs780,rv770,rv730,rv710
+ * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
  */
+int r600_init(struct radeon_device *rdev);
+void r600_fini(struct radeon_device *rdev);
+int r600_suspend(struct radeon_device *rdev);
+int r600_resume(struct radeon_device *rdev);
+int r600_wb_init(struct radeon_device *rdev);
+void r600_wb_fini(struct radeon_device *rdev);
+void r600_cp_commit(struct radeon_device *rdev);
+void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
+int r600_cs_parse(struct radeon_cs_parser *p);
+void r600_fence_ring_emit(struct radeon_device *rdev,
+			  struct radeon_fence *fence);
+int r600_copy_dma(struct radeon_device *rdev,
+		  uint64_t src_offset,
+		  uint64_t dst_offset,
+		  unsigned num_pages,
+		  struct radeon_fence *fence);
+int r600_irq_process(struct radeon_device *rdev);
+int r600_irq_set(struct radeon_device *rdev);
+int r600_gpu_reset(struct radeon_device *rdev);
+int r600_set_surface_reg(struct radeon_device *rdev, int reg,
+			 uint32_t tiling_flags, uint32_t pitch,
+			 uint32_t offset, uint32_t obj_size);
+int r600_clear_surface_reg(struct radeon_device *rdev, int reg);
+void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
+int r600_ib_test(struct radeon_device *rdev);
+int r600_ring_test(struct radeon_device *rdev);
+int r600_copy_blit(struct radeon_device *rdev,
+		   uint64_t src_offset, uint64_t dst_offset,
+		   unsigned num_pages, struct radeon_fence *fence);
+
+static struct radeon_asic r600_asic = {
+	.errata = NULL,
+	.init = &r600_init,
+	.fini = &r600_fini,
+	.suspend = &r600_suspend,
+	.resume = &r600_resume,
+	.cp_commit = &r600_cp_commit,
+	.vram_info = NULL,
+	.gpu_reset = &r600_gpu_reset,
+	.mc_init = NULL,
+	.mc_fini = NULL,
+	.wb_init = &r600_wb_init,
+	.wb_fini = &r600_wb_fini,
+	.gart_enable = NULL,
+	.gart_disable = NULL,
+	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
+	.gart_set_page = &rs600_gart_set_page,
+	.cp_init = NULL,
+	.cp_fini = NULL,
+	.cp_disable = NULL,
+	.ring_start = NULL,
+	.ring_test = &r600_ring_test,
+	.ring_ib_execute = &r600_ring_ib_execute,
+	.ib_test = &r600_ib_test,
+	.irq_set = &r600_irq_set,
+	.irq_process = &r600_irq_process,
+	.fence_ring_emit = &r600_fence_ring_emit,
+	.cs_parse = &r600_cs_parse,
+	.copy_blit = &r600_copy_blit,
+	.copy_dma = &r600_copy_blit,
+	.copy = NULL,
+	.set_engine_clock = &radeon_atom_set_engine_clock,
+	.set_memory_clock = &radeon_atom_set_memory_clock,
+	.set_pcie_lanes = NULL,
+	.set_clock_gating = &radeon_atom_set_clock_gating,
+	.set_surface_reg = r600_set_surface_reg,
+	.clear_surface_reg = r600_clear_surface_reg,
+	.bandwidth_update = &r520_bandwidth_update,
+};
+
+/*
+ * rv770,rv730,rv710,rv740
+ */
+int rv770_init(struct radeon_device *rdev);
+void rv770_fini(struct radeon_device *rdev);
+int rv770_suspend(struct radeon_device *rdev);
+int rv770_resume(struct radeon_device *rdev);
+int rv770_gpu_reset(struct radeon_device *rdev);
+
+static struct radeon_asic rv770_asic = {
+	.errata = NULL,
+	.init = &rv770_init,
+	.fini = &rv770_fini,
+	.suspend = &rv770_suspend,
+	.resume = &rv770_resume,
+	.cp_commit = &r600_cp_commit,
+	.vram_info = NULL,
+	.gpu_reset = &rv770_gpu_reset,
+	.mc_init = NULL,
+	.mc_fini = NULL,
+	.wb_init = &r600_wb_init,
+	.wb_fini = &r600_wb_fini,
+	.gart_enable = NULL,
+	.gart_disable = NULL,
+	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
+	.gart_set_page = &rs600_gart_set_page,
+	.cp_init = NULL,
+	.cp_fini = NULL,
+	.cp_disable = NULL,
+	.ring_start = NULL,
+	.ring_test = &r600_ring_test,
+	.ring_ib_execute = &r600_ring_ib_execute,
+	.ib_test = &r600_ib_test,
+	.irq_set = &r600_irq_set,
+	.irq_process = &r600_irq_process,
+	.fence_ring_emit = &r600_fence_ring_emit,
+	.cs_parse = &r600_cs_parse,
+	.copy_blit = &r600_copy_blit,
+	.copy_dma = &r600_copy_blit,
+	.copy = NULL,
+	.set_engine_clock = &radeon_atom_set_engine_clock,
+	.set_memory_clock = &radeon_atom_set_memory_clock,
+	.set_pcie_lanes = NULL,
+	.set_clock_gating = &radeon_atom_set_clock_gating,
+	.set_surface_reg = r600_set_surface_reg,
+	.clear_surface_reg = r600_clear_surface_reg,
+	.bandwidth_update = &r520_bandwidth_update,
+};
 
 #endif
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index bba9b4bd8f5..a8fb392c9cd 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -370,10 +370,6 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 						       && record->
 						       ucRecordType <=
 						       ATOM_MAX_OBJECT_RECORD_NUMBER) {
-							DRM_ERROR
-							    ("record type %d\n",
-							     record->
-							     ucRecordType);
 							switch (record->
 								ucRecordType) {
 							case ATOM_I2C_RECORD_TYPE:
diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c
index a37cbce5318..152eef13197 100644
--- a/drivers/gpu/drm/radeon/radeon_clocks.c
+++ b/drivers/gpu/drm/radeon/radeon_clocks.c
@@ -102,10 +102,12 @@ void radeon_get_clock_info(struct drm_device *dev)
 			p1pll->reference_div = 12;
 		if (p2pll->reference_div < 2)
 			p2pll->reference_div = 12;
-		if (spll->reference_div < 2)
-			spll->reference_div =
-			    RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
-			    RADEON_M_SPLL_REF_DIV_MASK;
+		if (rdev->family < CHIP_RS600) {
+			if (spll->reference_div < 2)
+				spll->reference_div =
+					RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
+					RADEON_M_SPLL_REF_DIV_MASK;
+		}
 		if (mpll->reference_div < 2)
 			mpll->reference_div = spll->reference_div;
 	} else {
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 7693f7c67bd..f2469c51178 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -37,7 +37,7 @@
 /*
  * Clear GPU surface registers.
  */
-static void radeon_surface_init(struct radeon_device *rdev)
+void radeon_surface_init(struct radeon_device *rdev)
 {
 	/* FIXME: check this out */
 	if (rdev->family < CHIP_R600) {
@@ -56,7 +56,7 @@ static void radeon_surface_init(struct radeon_device *rdev)
 /*
  * GPU scratch registers helpers function.
  */
-static void radeon_scratch_init(struct radeon_device *rdev)
+void radeon_scratch_init(struct radeon_device *rdev)
 {
 	int i;
 
@@ -156,16 +156,14 @@ int radeon_mc_setup(struct radeon_device *rdev)
 		tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
 		rdev->mc.gtt_location = tmp;
 	}
-	DRM_INFO("radeon: VRAM %uM\n", rdev->mc.real_vram_size >> 20);
+	DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
 	DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
-		 rdev->mc.vram_location,
-		 rdev->mc.vram_location + rdev->mc.mc_vram_size - 1);
-	if (rdev->mc.real_vram_size != rdev->mc.mc_vram_size)
-		DRM_INFO("radeon: VRAM less than aperture workaround enabled\n");
-	DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20);
+		 (unsigned)rdev->mc.vram_location,
+		 (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
+	DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
 	DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
-		 rdev->mc.gtt_location,
-		 rdev->mc.gtt_location + rdev->mc.gtt_size - 1);
+		 (unsigned)rdev->mc.gtt_location,
+		 (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
 	return 0;
 }
 
@@ -205,6 +203,31 @@ static bool radeon_card_posted(struct radeon_device *rdev)
 
 }
 
+int radeon_dummy_page_init(struct radeon_device *rdev)
+{
+	rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
+	if (rdev->dummy_page.page == NULL)
+		return -ENOMEM;
+	rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
+					0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+	if (!rdev->dummy_page.addr) {
+		__free_page(rdev->dummy_page.page);
+		rdev->dummy_page.page = NULL;
+		return -ENOMEM;
+	}
+	return 0;
+}
+
+void radeon_dummy_page_fini(struct radeon_device *rdev)
+{
+	if (rdev->dummy_page.page == NULL)
+		return;
+	pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
+			PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+	__free_page(rdev->dummy_page.page);
+	rdev->dummy_page.page = NULL;
+}
+
 
 /*
  * Registers accessors functions.
@@ -323,9 +346,15 @@ int radeon_asic_init(struct radeon_device *rdev)
 	case CHIP_RV635:
 	case CHIP_RV670:
 	case CHIP_RS780:
+	case CHIP_RS880:
+		rdev->asic = &r600_asic;
+		break;
 	case CHIP_RV770:
 	case CHIP_RV730:
 	case CHIP_RV710:
+	case CHIP_RV740:
+		rdev->asic = &rv770_asic;
+		break;
 	default:
 		/* FIXME: not supported yet */
 		return -EINVAL;
@@ -448,7 +477,7 @@ int radeon_device_init(struct radeon_device *rdev,
 		       struct pci_dev *pdev,
 		       uint32_t flags)
 {
-	int r, ret;
+	int r, ret = 0;
 	int dma_bits;
 
 	DRM_INFO("radeon: Initializing kernel modesetting.\n");
@@ -487,10 +516,6 @@ int radeon_device_init(struct radeon_device *rdev,
 	if (r) {
 		return r;
 	}
-	r = radeon_init(rdev);
-	if (r) {
-		return r;
-	}
 
 	/* set DMA mask + need_dma32 flags.
 	 * PCIE - can handle 40-bits.
@@ -521,111 +546,118 @@ int radeon_device_init(struct radeon_device *rdev,
 	DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
 	DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
 
-	/* Setup errata flags */
-	radeon_errata(rdev);
-	/* Initialize scratch registers */
-	radeon_scratch_init(rdev);
-	/* Initialize surface registers */
-	radeon_surface_init(rdev);
-
-	/* TODO: disable VGA need to use VGA request */
-	/* BIOS*/
-	if (!radeon_get_bios(rdev)) {
-		if (ASIC_IS_AVIVO(rdev))
-			return -EINVAL;
-	}
-	if (rdev->is_atom_bios) {
-		r = radeon_atombios_init(rdev);
+	rdev->new_init_path = false;
+	r = radeon_init(rdev);
+	if (r) {
+		return r;
+	}
+	if (!rdev->new_init_path) {
+		/* Setup errata flags */
+		radeon_errata(rdev);
+		/* Initialize scratch registers */
+		radeon_scratch_init(rdev);
+		/* Initialize surface registers */
+		radeon_surface_init(rdev);
+
+		/* TODO: disable VGA need to use VGA request */
+		/* BIOS*/
+		if (!radeon_get_bios(rdev)) {
+			if (ASIC_IS_AVIVO(rdev))
+				return -EINVAL;
+		}
+		if (rdev->is_atom_bios) {
+			r = radeon_atombios_init(rdev);
+			if (r) {
+				return r;
+			}
+		} else {
+			r = radeon_combios_init(rdev);
+			if (r) {
+				return r;
+			}
+		}
+		/* Reset gpu before posting otherwise ATOM will enter infinite loop */
+		if (radeon_gpu_reset(rdev)) {
+			/* FIXME: what do we want to do here ? */
+		}
+		/* check if cards are posted or not */
+		if (!radeon_card_posted(rdev) && rdev->bios) {
+			DRM_INFO("GPU not posted. posting now...\n");
+			if (rdev->is_atom_bios) {
+				atom_asic_init(rdev->mode_info.atom_context);
+			} else {
+				radeon_combios_asic_init(rdev->ddev);
+			}
+		}
+		/* Initialize clocks */
+		r = radeon_clocks_init(rdev);
 		if (r) {
 			return r;
 		}
-	} else {
-		r = radeon_combios_init(rdev);
+		/* Get vram informations */
+		radeon_vram_info(rdev);
+
+		/* Add an MTRR for the VRAM */
+		rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
+				MTRR_TYPE_WRCOMB, 1);
+		DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n",
+				(unsigned)(rdev->mc.mc_vram_size >> 20),
+				(unsigned)(rdev->mc.aper_size >> 20));
+		DRM_INFO("RAM width %dbits %cDR\n",
+				rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
+		/* Initialize memory controller (also test AGP) */
+		r = radeon_mc_init(rdev);
 		if (r) {
 			return r;
 		}
-	}
-	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
-	if (radeon_gpu_reset(rdev)) {
-		/* FIXME: what do we want to do here ? */
-	}
-	/* check if cards are posted or not */
-	if (!radeon_card_posted(rdev) && rdev->bios) {
-		DRM_INFO("GPU not posted. posting now...\n");
-		if (rdev->is_atom_bios) {
-			atom_asic_init(rdev->mode_info.atom_context);
-		} else {
-			radeon_combios_asic_init(rdev->ddev);
-		}
-	}
-	/* Initialize clocks */
-	r = radeon_clocks_init(rdev);
-	if (r) {
-		return r;
-	}
-	/* Get vram informations */
-	radeon_vram_info(rdev);
-
-	/* Add an MTRR for the VRAM */
-	rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
-				      MTRR_TYPE_WRCOMB, 1);
-	DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n",
-		 rdev->mc.real_vram_size >> 20,
-		 (unsigned)rdev->mc.aper_size >> 20);
-	DRM_INFO("RAM width %dbits %cDR\n",
-		 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
-	/* Initialize memory controller (also test AGP) */
-	r = radeon_mc_init(rdev);
-	if (r) {
-		return r;
-	}
-	/* Fence driver */
-	r = radeon_fence_driver_init(rdev);
-	if (r) {
-		return r;
-	}
-	r = radeon_irq_kms_init(rdev);
-	if (r) {
-		return r;
-	}
-	/* Memory manager */
-	r = radeon_object_init(rdev);
-	if (r) {
-		return r;
-	}
-	/* Initialize GART (initialize after TTM so we can allocate
-	 * memory through TTM but finalize after TTM) */
-	r = radeon_gart_enable(rdev);
-	if (!r) {
-		r = radeon_gem_init(rdev);
-	}
-
-	/* 1M ring buffer */
-	if (!r) {
-		r = radeon_cp_init(rdev, 1024 * 1024);
-	}
-	if (!r) {
-		r = radeon_wb_init(rdev);
+		/* Fence driver */
+		r = radeon_fence_driver_init(rdev);
 		if (r) {
-			DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
 			return r;
 		}
-	}
-	if (!r) {
-		r = radeon_ib_pool_init(rdev);
+		r = radeon_irq_kms_init(rdev);
 		if (r) {
-			DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
 			return r;
 		}
-	}
-	if (!r) {
-		r = radeon_ib_test(rdev);
+		/* Memory manager */
+		r = radeon_object_init(rdev);
 		if (r) {
-			DRM_ERROR("radeon: failled testing IB (%d).\n", r);
 			return r;
 		}
+		/* Initialize GART (initialize after TTM so we can allocate
+		 * memory through TTM but finalize after TTM) */
+		r = radeon_gart_enable(rdev);
+		if (!r) {
+			r = radeon_gem_init(rdev);
+		}
+
+		/* 1M ring buffer */
+		if (!r) {
+			r = radeon_cp_init(rdev, 1024 * 1024);
+		}
+		if (!r) {
+			r = radeon_wb_init(rdev);
+			if (r) {
+				DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
+				return r;
+			}
+		}
+		if (!r) {
+			r = radeon_ib_pool_init(rdev);
+			if (r) {
+				DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
+				return r;
+			}
+		}
+		if (!r) {
+			r = radeon_ib_test(rdev);
+			if (r) {
+				DRM_ERROR("radeon: failled testing IB (%d).\n", r);
+				return r;
+			}
+		}
+		ret = r;
 	}
-	ret = r;
 	r = radeon_modeset_init(rdev);
 	if (r) {
 		return r;
@@ -651,26 +683,29 @@ void radeon_device_fini(struct radeon_device *rdev)
 	rdev->shutdown = true;
 	/* Order matter so becarefull if you rearrange anythings */
 	radeon_modeset_fini(rdev);
-	radeon_ib_pool_fini(rdev);
-	radeon_cp_fini(rdev);
-	radeon_wb_fini(rdev);
-	radeon_gem_fini(rdev);
-	radeon_object_fini(rdev);
-	/* mc_fini must be after object_fini */
-	radeon_mc_fini(rdev);
+	if (!rdev->new_init_path) {
+		radeon_ib_pool_fini(rdev);
+		radeon_cp_fini(rdev);
+		radeon_wb_fini(rdev);
+		radeon_gem_fini(rdev);
+		radeon_mc_fini(rdev);
 #if __OS_HAS_AGP
-	radeon_agp_fini(rdev);
+		radeon_agp_fini(rdev);
 #endif
-	radeon_irq_kms_fini(rdev);
-	radeon_fence_driver_fini(rdev);
-	radeon_clocks_fini(rdev);
-	if (rdev->is_atom_bios) {
-		radeon_atombios_fini(rdev);
+		radeon_irq_kms_fini(rdev);
+		radeon_fence_driver_fini(rdev);
+		radeon_clocks_fini(rdev);
+		radeon_object_fini(rdev);
+		if (rdev->is_atom_bios) {
+			radeon_atombios_fini(rdev);
+		} else {
+			radeon_combios_fini(rdev);
+		}
+		kfree(rdev->bios);
+		rdev->bios = NULL;
 	} else {
-		radeon_combios_fini(rdev);
+		radeon_fini(rdev);
 	}
-	kfree(rdev->bios);
-	rdev->bios = NULL;
 	iounmap(rdev->rmmio);
 	rdev->rmmio = NULL;
 }
@@ -708,9 +743,12 @@ int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
 	/* wait for gpu to finish processing current batch */
 	radeon_fence_wait_last(rdev);
 
-	radeon_cp_disable(rdev);
-	radeon_gart_disable(rdev);
-
+	if (!rdev->new_init_path) {
+		radeon_cp_disable(rdev);
+		radeon_gart_disable(rdev);
+	} else {
+		radeon_suspend(rdev);
+	}
 	/* evict remaining vram memory */
 	radeon_object_evict_vram(rdev);
 
@@ -746,33 +784,37 @@ int radeon_resume_kms(struct drm_device *dev)
 	if (radeon_gpu_reset(rdev)) {
 		/* FIXME: what do we want to do here ? */
 	}
-	/* post card */
-	if (rdev->is_atom_bios) {
-		atom_asic_init(rdev->mode_info.atom_context);
+	if (!rdev->new_init_path) {
+		/* post card */
+		if (rdev->is_atom_bios) {
+			atom_asic_init(rdev->mode_info.atom_context);
+		} else {
+			radeon_combios_asic_init(rdev->ddev);
+		}
+		/* Initialize clocks */
+		r = radeon_clocks_init(rdev);
+		if (r) {
+			release_console_sem();
+			return r;
+		}
+		/* Enable IRQ */
+		rdev->irq.sw_int = true;
+		radeon_irq_set(rdev);
+		/* Initialize GPU Memory Controller */
+		r = radeon_mc_init(rdev);
+		if (r) {
+			goto out;
+		}
+		r = radeon_gart_enable(rdev);
+		if (r) {
+			goto out;
+		}
+		r = radeon_cp_init(rdev, rdev->cp.ring_size);
+		if (r) {
+			goto out;
+		}
 	} else {
-		radeon_combios_asic_init(rdev->ddev);
-	}
-	/* Initialize clocks */
-	r = radeon_clocks_init(rdev);
-	if (r) {
-		release_console_sem();
-		return r;
-	}
-	/* Enable IRQ */
-	rdev->irq.sw_int = true;
-	radeon_irq_set(rdev);
-	/* Initialize GPU Memory Controller */
-	r = radeon_mc_init(rdev);
-	if (r) {
-		goto out;
-	}
-	r = radeon_gart_enable(rdev);
-	if (r) {
-		goto out;
-	}
-	r = radeon_cp_init(rdev, rdev->cp.ring_size);
-	if (r) {
-		goto out;
+		radeon_resume(rdev);
 	}
 out:
 	fb_set_suspend(rdev->fbdev_info, 0);
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index 40294a07976..c7b185924f6 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -356,6 +356,12 @@ typedef struct drm_radeon_private {
 	int r700_sc_hiz_tile_fifo_size;
 	int r700_sc_earlyz_tile_fifo_fize;
 
+	struct mutex cs_mutex;
+	u32 cs_id_scnt;
+	u32 cs_id_wcnt;
+	/* r6xx/r7xx drm blit vertex buffer */
+	struct drm_buf *blit_vb;
+
 	/* firmware */
 	const struct firmware *me_fw, *pfp_fw;
 } drm_radeon_private_t;
@@ -396,6 +402,9 @@ static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
 		(off >= gart_start && off <= gart_end));
 }
 
+/* radeon_state.c */
+extern void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf);
+
 				/* radeon_cp.c */
 extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
 extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
@@ -487,6 +496,22 @@ extern int r600_cp_dispatch_indirect(struct drm_device *dev,
 				     struct drm_buf *buf, int start, int end);
 extern int r600_page_table_init(struct drm_device *dev);
 extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info);
+extern int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv);
+extern void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv);
+extern int r600_cp_dispatch_texture(struct drm_device *dev,
+				    struct drm_file *file_priv,
+				    drm_radeon_texture_t *tex,
+				    drm_radeon_tex_image_t *image);
+/* r600_blit.c */
+extern int r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv);
+extern void r600_done_blit_copy(struct drm_device *dev);
+extern void r600_blit_copy(struct drm_device *dev,
+			   uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
+			   int size_bytes);
+extern void r600_blit_swap(struct drm_device *dev,
+			   uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
+			   int sx, int sy, int dx, int dy,
+			   int w, int h, int src_pitch, int dst_pitch, int cpp);
 
 /* Flags for stats.boxes
  */
@@ -1114,13 +1139,71 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
 #	define RADEON_CNTL_BITBLT_MULTI		0x00009B00
 #	define RADEON_CNTL_SET_SCISSORS		0xC0001E00
 
-#	define R600_IT_INDIRECT_BUFFER		0x00003200
-#	define R600_IT_ME_INITIALIZE		0x00004400
+#       define R600_IT_INDIRECT_BUFFER_END      0x00001700
+#       define R600_IT_SET_PREDICATION          0x00002000
+#       define R600_IT_REG_RMW                  0x00002100
+#       define R600_IT_COND_EXEC                0x00002200
+#       define R600_IT_PRED_EXEC                0x00002300
+#       define R600_IT_START_3D_CMDBUF          0x00002400
+#       define R600_IT_DRAW_INDEX_2             0x00002700
+#       define R600_IT_CONTEXT_CONTROL          0x00002800
+#       define R600_IT_DRAW_INDEX_IMMD_BE       0x00002900
+#       define R600_IT_INDEX_TYPE               0x00002A00
+#       define R600_IT_DRAW_INDEX               0x00002B00
+#       define R600_IT_DRAW_INDEX_AUTO          0x00002D00
+#       define R600_IT_DRAW_INDEX_IMMD          0x00002E00
+#       define R600_IT_NUM_INSTANCES            0x00002F00
+#       define R600_IT_STRMOUT_BUFFER_UPDATE    0x00003400
+#       define R600_IT_INDIRECT_BUFFER_MP       0x00003800
+#       define R600_IT_MEM_SEMAPHORE            0x00003900
+#       define R600_IT_MPEG_INDEX               0x00003A00
+#       define R600_IT_WAIT_REG_MEM             0x00003C00
+#       define R600_IT_MEM_WRITE                0x00003D00
+#       define R600_IT_INDIRECT_BUFFER          0x00003200
+#       define R600_IT_CP_INTERRUPT             0x00004000
+#       define R600_IT_SURFACE_SYNC             0x00004300
+#              define R600_CB0_DEST_BASE_ENA    (1 << 6)
+#              define R600_TC_ACTION_ENA        (1 << 23)
+#              define R600_VC_ACTION_ENA        (1 << 24)
+#              define R600_CB_ACTION_ENA        (1 << 25)
+#              define R600_DB_ACTION_ENA        (1 << 26)
+#              define R600_SH_ACTION_ENA        (1 << 27)
+#              define R600_SMX_ACTION_ENA       (1 << 28)
+#       define R600_IT_ME_INITIALIZE            0x00004400
 #	       define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
-#	define R600_IT_EVENT_WRITE		0x00004600
-#	define R600_IT_SET_CONFIG_REG		0x00006800
-#	define R600_SET_CONFIG_REG_OFFSET       0x00008000
-#	define R600_SET_CONFIG_REG_END          0x0000ac00
+#       define R600_IT_COND_WRITE               0x00004500
+#       define R600_IT_EVENT_WRITE              0x00004600
+#       define R600_IT_EVENT_WRITE_EOP          0x00004700
+#       define R600_IT_ONE_REG_WRITE            0x00005700
+#       define R600_IT_SET_CONFIG_REG           0x00006800
+#              define R600_SET_CONFIG_REG_OFFSET 0x00008000
+#              define R600_SET_CONFIG_REG_END   0x0000ac00
+#       define R600_IT_SET_CONTEXT_REG          0x00006900
+#              define R600_SET_CONTEXT_REG_OFFSET 0x00028000
+#              define R600_SET_CONTEXT_REG_END  0x00029000
+#       define R600_IT_SET_ALU_CONST            0x00006A00
+#              define R600_SET_ALU_CONST_OFFSET 0x00030000
+#              define R600_SET_ALU_CONST_END    0x00032000
+#       define R600_IT_SET_BOOL_CONST           0x00006B00
+#              define R600_SET_BOOL_CONST_OFFSET 0x0003e380
+#              define R600_SET_BOOL_CONST_END   0x00040000
+#       define R600_IT_SET_LOOP_CONST           0x00006C00
+#              define R600_SET_LOOP_CONST_OFFSET 0x0003e200
+#              define R600_SET_LOOP_CONST_END   0x0003e380
+#       define R600_IT_SET_RESOURCE             0x00006D00
+#              define R600_SET_RESOURCE_OFFSET  0x00038000
+#              define R600_SET_RESOURCE_END     0x0003c000
+#              define R600_SQ_TEX_VTX_INVALID_TEXTURE  0x0
+#              define R600_SQ_TEX_VTX_INVALID_BUFFER   0x1
+#              define R600_SQ_TEX_VTX_VALID_TEXTURE    0x2
+#              define R600_SQ_TEX_VTX_VALID_BUFFER     0x3
+#       define R600_IT_SET_SAMPLER              0x00006E00
+#              define R600_SET_SAMPLER_OFFSET   0x0003c000
+#              define R600_SET_SAMPLER_END      0x0003cff0
+#       define R600_IT_SET_CTL_CONST            0x00006F00
+#              define R600_SET_CTL_CONST_OFFSET 0x0003cff0
+#              define R600_SET_CTL_CONST_END    0x0003e200
+#       define R600_IT_SURFACE_BASE_UPDATE      0x00007300
 
 #define RADEON_CP_PACKET_MASK		0xC0000000
 #define RADEON_CP_PACKET_COUNT_MASK	0x3fff0000
@@ -1598,6 +1681,52 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
 #define R600_CB_COLOR7_BASE                                    0x2805c
 #define R600_CB_COLOR7_FRAG                                    0x280fc
 
+#define R600_CB_COLOR0_SIZE                                    0x28060
+#define R600_CB_COLOR0_VIEW                                    0x28080
+#define R600_CB_COLOR0_INFO                                    0x280a0
+#define R600_CB_COLOR0_TILE                                    0x280c0
+#define R600_CB_COLOR0_FRAG                                    0x280e0
+#define R600_CB_COLOR0_MASK                                    0x28100
+
+#define AVIVO_D1MODE_VLINE_START_END                           0x6538
+#define AVIVO_D2MODE_VLINE_START_END                           0x6d38
+#define R600_CP_COHER_BASE                                     0x85f8
+#define R600_DB_DEPTH_BASE                                     0x2800c
+#define R600_SQ_PGM_START_FS                                   0x28894
+#define R600_SQ_PGM_START_ES                                   0x28880
+#define R600_SQ_PGM_START_VS                                   0x28858
+#define R600_SQ_PGM_RESOURCES_VS                               0x28868
+#define R600_SQ_PGM_CF_OFFSET_VS                               0x288d0
+#define R600_SQ_PGM_START_GS                                   0x2886c
+#define R600_SQ_PGM_START_PS                                   0x28840
+#define R600_SQ_PGM_RESOURCES_PS                               0x28850
+#define R600_SQ_PGM_EXPORTS_PS                                 0x28854
+#define R600_SQ_PGM_CF_OFFSET_PS                               0x288cc
+#define R600_VGT_DMA_BASE                                      0x287e8
+#define R600_VGT_DMA_BASE_HI                                   0x287e4
+#define R600_VGT_STRMOUT_BASE_OFFSET_0                         0x28b10
+#define R600_VGT_STRMOUT_BASE_OFFSET_1                         0x28b14
+#define R600_VGT_STRMOUT_BASE_OFFSET_2                         0x28b18
+#define R600_VGT_STRMOUT_BASE_OFFSET_3                         0x28b1c
+#define R600_VGT_STRMOUT_BASE_OFFSET_HI_0                      0x28b44
+#define R600_VGT_STRMOUT_BASE_OFFSET_HI_1                      0x28b48
+#define R600_VGT_STRMOUT_BASE_OFFSET_HI_2                      0x28b4c
+#define R600_VGT_STRMOUT_BASE_OFFSET_HI_3                      0x28b50
+#define R600_VGT_STRMOUT_BUFFER_BASE_0                         0x28ad8
+#define R600_VGT_STRMOUT_BUFFER_BASE_1                         0x28ae8
+#define R600_VGT_STRMOUT_BUFFER_BASE_2                         0x28af8
+#define R600_VGT_STRMOUT_BUFFER_BASE_3                         0x28b08
+#define R600_VGT_STRMOUT_BUFFER_OFFSET_0                       0x28adc
+#define R600_VGT_STRMOUT_BUFFER_OFFSET_1                       0x28aec
+#define R600_VGT_STRMOUT_BUFFER_OFFSET_2                       0x28afc
+#define R600_VGT_STRMOUT_BUFFER_OFFSET_3                       0x28b0c
+
+#define R600_VGT_PRIMITIVE_TYPE                                0x8958
+
+#define R600_PA_SC_SCREEN_SCISSOR_TL                           0x28030
+#define R600_PA_SC_GENERIC_SCISSOR_TL                          0x28240
+#define R600_PA_SC_WINDOW_SCISSOR_TL                           0x28204
+
 #define R600_TC_CNTL                                           0x9608
 #       define R600_TC_L2_SIZE(x)                              ((x) << 5)
 #       define R600_L2_DISABLE_LATE_HIT                        (1 << 9)
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index b4e48dd2e85..506dd4dd3a2 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -53,9 +53,9 @@ int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
 		 * away
 		 */
 		WREG32(rdev->fence_drv.scratch_reg, fence->seq);
-	} else {
+	} else
 		radeon_fence_ring_emit(rdev, fence);
-	}
+
 	fence->emited = true;
 	fence->timeout = jiffies + ((2000 * HZ) / 1000);
 	list_del(&fence->list);
@@ -168,7 +168,47 @@ bool radeon_fence_signaled(struct radeon_fence *fence)
 	return signaled;
 }
 
-int radeon_fence_wait(struct radeon_fence *fence, bool interruptible)
+int r600_fence_wait(struct radeon_fence *fence,  bool intr, bool lazy)
+{
+	struct radeon_device *rdev;
+	unsigned long cur_jiffies;
+	unsigned long timeout;
+	int ret = 0;
+
+	cur_jiffies = jiffies;
+	timeout = HZ / 100;
+
+	if (time_after(fence->timeout, cur_jiffies)) {
+		timeout = fence->timeout - cur_jiffies;
+	}
+
+	rdev = fence->rdev;
+
+	__set_current_state(intr ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
+
+	while (1) {
+		if (radeon_fence_signaled(fence))
+			break;
+
+		if (time_after_eq(jiffies, timeout)) {
+			ret = -EBUSY;
+			break;
+		}
+
+		if (lazy)
+			schedule_timeout(1);
+
+		if (intr && signal_pending(current)) {
+			ret = -ERESTART;
+			break;
+		}
+	}
+	__set_current_state(TASK_RUNNING);
+	return ret;
+}
+
+
+int radeon_fence_wait(struct radeon_fence *fence, bool intr)
 {
 	struct radeon_device *rdev;
 	unsigned long cur_jiffies;
@@ -176,7 +216,6 @@ int radeon_fence_wait(struct radeon_fence *fence, bool interruptible)
 	bool expired = false;
 	int r;
 
-
 	if (fence == NULL) {
 		WARN(1, "Querying an invalid fence : %p !\n", fence);
 		return 0;
@@ -185,13 +224,18 @@ int radeon_fence_wait(struct radeon_fence *fence, bool interruptible)
 	if (radeon_fence_signaled(fence)) {
 		return 0;
 	}
+
+	if (rdev->family >= CHIP_R600)
+		return r600_fence_wait(fence, intr, 0);
+
 retry:
 	cur_jiffies = jiffies;
 	timeout = HZ / 100;
 	if (time_after(fence->timeout, cur_jiffies)) {
 		timeout = fence->timeout - cur_jiffies;
 	}
-	if (interruptible) {
+
+	if (intr) {
 		r = wait_event_interruptible_timeout(rdev->fence_drv.queue,
 				radeon_fence_signaled(fence), timeout);
 		if (unlikely(r == -ERESTARTSYS)) {
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
index 28be2f1165c..21da871a793 100644
--- a/drivers/gpu/drm/radeon/radeon_reg.h
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -3255,6 +3255,24 @@
 #define RADEON_CP_RB_WPTR                   0x0714
 #define RADEON_CP_RB_RPTR_WR                0x071c
 
+#define RADEON_SCRATCH_UMSK		    0x0770
+#define RADEON_SCRATCH_ADDR		    0x0774
+
+#define R600_CP_RB_BASE                     0xc100
+#define R600_CP_RB_CNTL                     0xc104
+#       define R600_RB_BUFSZ(x)             ((x) << 0)
+#       define R600_RB_BLKSZ(x)             ((x) << 8)
+#       define R600_RB_NO_UPDATE            (1 << 27)
+#       define R600_RB_RPTR_WR_ENA          (1 << 31)
+#define R600_CP_RB_RPTR_WR                  0xc108
+#define R600_CP_RB_RPTR_ADDR                0xc10c
+#define R600_CP_RB_RPTR_ADDR_HI             0xc110
+#define R600_CP_RB_WPTR                     0xc114
+#define R600_CP_RB_WPTR_ADDR                0xc118
+#define R600_CP_RB_WPTR_ADDR_HI             0xc11c
+#define R600_CP_RB_RPTR                     0x8700
+#define R600_CP_RB_WPTR_DELAY               0x8704
+
 #define RADEON_CP_IB_BASE                   0x0738
 #define RADEON_CP_IB_BUFSZ                  0x073c
 
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index 60d159308b8..aa9837a6aa7 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -110,7 +110,6 @@ void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
 		return;
 	}
 	list_del(&tmp->list);
-	INIT_LIST_HEAD(&tmp->list);
 	if (tmp->fence) {
 		radeon_fence_unref(&tmp->fence);
 	}
@@ -119,19 +118,11 @@ void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
 	mutex_unlock(&rdev->ib_pool.mutex);
 }
 
-static void radeon_ib_align(struct radeon_device *rdev, struct radeon_ib *ib)
-{
-	while ((ib->length_dw & rdev->cp.align_mask)) {
-		ib->ptr[ib->length_dw++] = PACKET2(0);
-	}
-}
-
 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
 {
 	int r = 0;
 
 	mutex_lock(&rdev->ib_pool.mutex);
-	radeon_ib_align(rdev, ib);
 	if (!ib->length_dw || !rdev->cp.ready) {
 		/* TODO: Nothings in the ib we should report. */
 		mutex_unlock(&rdev->ib_pool.mutex);
@@ -145,9 +136,7 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
 		mutex_unlock(&rdev->ib_pool.mutex);
 		return r;
 	}
-	radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
-	radeon_ring_write(rdev, ib->gpu_addr);
-	radeon_ring_write(rdev, ib->length_dw);
+	radeon_ring_ib_execute(rdev, ib);
 	radeon_fence_emit(rdev, ib->fence);
 	radeon_ring_unlock_commit(rdev);
 	list_add_tail(&ib->list, &rdev->ib_pool.scheduled_ibs);
@@ -215,69 +204,16 @@ void radeon_ib_pool_fini(struct radeon_device *rdev)
 	mutex_unlock(&rdev->ib_pool.mutex);
 }
 
-int radeon_ib_test(struct radeon_device *rdev)
-{
-	struct radeon_ib *ib;
-	uint32_t scratch;
-	uint32_t tmp = 0;
-	unsigned i;
-	int r;
-
-	r = radeon_scratch_get(rdev, &scratch);
-	if (r) {
-		DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
-		return r;
-	}
-	WREG32(scratch, 0xCAFEDEAD);
-	r = radeon_ib_get(rdev, &ib);
-	if (r) {
-		return r;
-	}
-	ib->ptr[0] = PACKET0(scratch, 0);
-	ib->ptr[1] = 0xDEADBEEF;
-	ib->ptr[2] = PACKET2(0);
-	ib->ptr[3] = PACKET2(0);
-	ib->ptr[4] = PACKET2(0);
-	ib->ptr[5] = PACKET2(0);
-	ib->ptr[6] = PACKET2(0);
-	ib->ptr[7] = PACKET2(0);
-	ib->length_dw = 8;
-	r = radeon_ib_schedule(rdev, ib);
-	if (r) {
-		radeon_scratch_free(rdev, scratch);
-		radeon_ib_free(rdev, &ib);
-		return r;
-	}
-	r = radeon_fence_wait(ib->fence, false);
-	if (r) {
-		return r;
-	}
-	for (i = 0; i < rdev->usec_timeout; i++) {
-		tmp = RREG32(scratch);
-		if (tmp == 0xDEADBEEF) {
-			break;
-		}
-		DRM_UDELAY(1);
-	}
-	if (i < rdev->usec_timeout) {
-		DRM_INFO("ib test succeeded in %u usecs\n", i);
-	} else {
-		DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
-			  scratch, tmp);
-		r = -EINVAL;
-	}
-	radeon_scratch_free(rdev, scratch);
-	radeon_ib_free(rdev, &ib);
-	return r;
-}
-
 
 /*
  * Ring.
  */
 void radeon_ring_free_size(struct radeon_device *rdev)
 {
-	rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
+	if (rdev->family >= CHIP_R600)
+		rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
+	else
+		rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
 	/* This works because ring_size is a power of 2 */
 	rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4));
 	rdev->cp.ring_free_dw -= rdev->cp.wptr;
@@ -320,11 +256,10 @@ void radeon_ring_unlock_commit(struct radeon_device *rdev)
 	count_dw_pad = (rdev->cp.align_mask + 1) -
 		       (rdev->cp.wptr & rdev->cp.align_mask);
 	for (i = 0; i < count_dw_pad; i++) {
-		radeon_ring_write(rdev, PACKET2(0));
+		radeon_ring_write(rdev, 2 << 30);
 	}
 	DRM_MEMORYBARRIER();
-	WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
-	(void)RREG32(RADEON_CP_RB_WPTR);
+	radeon_cp_commit(rdev);
 	mutex_unlock(&rdev->cp.mutex);
 }
 
@@ -334,46 +269,6 @@ void radeon_ring_unlock_undo(struct radeon_device *rdev)
 	mutex_unlock(&rdev->cp.mutex);
 }
 
-int radeon_ring_test(struct radeon_device *rdev)
-{
-	uint32_t scratch;
-	uint32_t tmp = 0;
-	unsigned i;
-	int r;
-
-	r = radeon_scratch_get(rdev, &scratch);
-	if (r) {
-		DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
-		return r;
-	}
-	WREG32(scratch, 0xCAFEDEAD);
-	r = radeon_ring_lock(rdev, 2);
-	if (r) {
-		DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
-		radeon_scratch_free(rdev, scratch);
-		return r;
-	}
-	radeon_ring_write(rdev, PACKET0(scratch, 0));
-	radeon_ring_write(rdev, 0xDEADBEEF);
-	radeon_ring_unlock_commit(rdev);
-	for (i = 0; i < rdev->usec_timeout; i++) {
-		tmp = RREG32(scratch);
-		if (tmp == 0xDEADBEEF) {
-			break;
-		}
-		DRM_UDELAY(1);
-	}
-	if (i < rdev->usec_timeout) {
-		DRM_INFO("ring test succeeded in %d usecs\n", i);
-	} else {
-		DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
-			  scratch, tmp);
-		r = -EINVAL;
-	}
-	radeon_scratch_free(rdev, scratch);
-	return r;
-}
-
 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size)
 {
 	int r;
diff --git a/drivers/gpu/drm/radeon/radeon_share.h b/drivers/gpu/drm/radeon/radeon_share.h
index 63a773578f1..5f9e358ab50 100644
--- a/drivers/gpu/drm/radeon/radeon_share.h
+++ b/drivers/gpu/drm/radeon/radeon_share.h
@@ -28,12 +28,89 @@
 #ifndef __RADEON_SHARE_H__
 #define __RADEON_SHARE_H__
 
+/* Common */
+struct radeon_device;
+struct radeon_cs_parser;
+int radeon_clocks_init(struct radeon_device *rdev);
+void radeon_clocks_fini(struct radeon_device *rdev);
+void radeon_scratch_init(struct radeon_device *rdev);
+void radeon_surface_init(struct radeon_device *rdev);
+int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
+
+
+/* R100, RV100, RS100, RV200, RS200, R200, RV250, RS300, RV280 */
 void r100_vram_init_sizes(struct radeon_device *rdev);
 
+
+/* R300, R350, RV350, RV380 */
+struct r300_asic {
+	const unsigned	*reg_safe_bm;
+	unsigned	reg_safe_bm_size;
+};
+
+
+/* RS690, RS740 */
 void rs690_line_buffer_adjust(struct radeon_device *rdev,
 			      struct drm_display_mode *mode1,
 			      struct drm_display_mode *mode2);
 
+
+/* RV515 */
 void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
 
+
+/* R600, RV610, RV630, RV620, RV635, RV670, RS780, RS880 */
+bool r600_card_posted(struct radeon_device *rdev);
+void r600_cp_stop(struct radeon_device *rdev);
+void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
+int r600_cp_resume(struct radeon_device *rdev);
+int r600_count_pipe_bits(uint32_t val);
+int r600_gart_clear_page(struct radeon_device *rdev, int i);
+int r600_mc_wait_for_idle(struct radeon_device *rdev);
+void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
+int r600_ib_test(struct radeon_device *rdev);
+int r600_ring_test(struct radeon_device *rdev);
+int r600_wb_init(struct radeon_device *rdev);
+void r600_wb_fini(struct radeon_device *rdev);
+void r600_scratch_init(struct radeon_device *rdev);
+int r600_blit_init(struct radeon_device *rdev);
+void r600_blit_fini(struct radeon_device *rdev);
+int r600_cp_init_microcode(struct radeon_device *rdev);
+struct r600_asic {
+	unsigned max_pipes;
+	unsigned max_tile_pipes;
+	unsigned max_simds;
+	unsigned max_backends;
+	unsigned max_gprs;
+	unsigned max_threads;
+	unsigned max_stack_entries;
+	unsigned max_hw_contexts;
+	unsigned max_gs_threads;
+	unsigned sx_max_export_size;
+	unsigned sx_max_export_pos_size;
+	unsigned sx_max_export_smx_size;
+	unsigned sq_num_cf_insts;
+};
+
+/* RV770, RV7300, RV710 */
+struct rv770_asic {
+	unsigned max_pipes;
+	unsigned max_tile_pipes;
+	unsigned max_simds;
+	unsigned max_backends;
+	unsigned max_gprs;
+	unsigned max_threads;
+	unsigned max_stack_entries;
+	unsigned max_hw_contexts;
+	unsigned max_gs_threads;
+	unsigned sx_max_export_size;
+	unsigned sx_max_export_pos_size;
+	unsigned sx_max_export_smx_size;
+	unsigned sq_num_cf_insts;
+	unsigned sx_num_of_sets;
+	unsigned sc_prim_fifo_size;
+	unsigned sc_hiz_tile_fifo_size;
+	unsigned sc_earlyz_tile_fifo_fize;
+};
+
 #endif
diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c
index 2882f40d5ec..aad0c6fafcf 100644
--- a/drivers/gpu/drm/radeon/radeon_state.c
+++ b/drivers/gpu/drm/radeon/radeon_state.c
@@ -1546,7 +1546,7 @@ static void radeon_cp_dispatch_vertex(struct drm_device * dev,
 	} while (i < nbox);
 }
 
-static void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf)
+void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	struct drm_radeon_master_private *master_priv = master->driver_priv;
@@ -2213,7 +2213,10 @@ static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *f
 	if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
 		sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
 
-	radeon_cp_dispatch_swap(dev, file_priv->master);
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+		r600_cp_dispatch_swap(dev, file_priv);
+	else
+		radeon_cp_dispatch_swap(dev, file_priv->master);
 	sarea_priv->ctx_owner = 0;
 
 	COMMIT_RING();
@@ -2412,7 +2415,10 @@ static int radeon_cp_texture(struct drm_device *dev, void *data, struct drm_file
 	RING_SPACE_TEST_WITH_RETURN(dev_priv);
 	VB_AGE_TEST_WITH_RETURN(dev_priv);
 
-	ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image);
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+		ret = r600_cp_dispatch_texture(dev, file_priv, tex, &image);
+	else
+		ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image);
 
 	return ret;
 }
@@ -2495,8 +2501,9 @@ static int radeon_cp_indirect(struct drm_device *dev, void *data, struct drm_fil
 		radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
 	}
 
-	if (indirect->discard)
+	if (indirect->discard) {
 		radeon_cp_discard_buffer(dev, file_priv->master, buf);
+	}
 
 	COMMIT_RING();
 	return 0;
@@ -3227,7 +3234,8 @@ struct drm_ioctl_desc radeon_ioctls[] = {
 	DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait, DRM_AUTH),
 	DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam, DRM_AUTH),
 	DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc, DRM_AUTH),
-	DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH)
+	DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH),
+	DRM_IOCTL_DEF(DRM_RADEON_CS, r600_cs_legacy_ioctl, DRM_AUTH)
 };
 
 int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls);
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index dc7a44274ea..acd889c9454 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -376,9 +376,8 @@ static int radeon_bo_move(struct ttm_buffer_object *bo,
 		radeon_move_null(bo, new_mem);
 		return 0;
 	}
-	if (!rdev->cp.ready) {
+	if (!rdev->cp.ready || rdev->asic->copy == NULL) {
 		/* use memcpy */
-		DRM_ERROR("CP is not ready use memcpy.\n");
 		goto memcpy;
 	}
 
@@ -495,7 +494,7 @@ int radeon_ttm_init(struct radeon_device *rdev)
 		return r;
 	}
 	DRM_INFO("radeon: %uM of VRAM memory ready\n",
-		 rdev->mc.real_vram_size / (1024 * 1024));
+		 (unsigned)rdev->mc.real_vram_size / (1024 * 1024));
 	r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, 0,
 			   ((rdev->mc.gtt_size) >> PAGE_SHIFT));
 	if (r) {
@@ -503,7 +502,7 @@ int radeon_ttm_init(struct radeon_device *rdev)
 		return r;
 	}
 	DRM_INFO("radeon: %uM of GTT memory ready.\n",
-		 rdev->mc.gtt_size / (1024 * 1024));
+		 (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
 	if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
 		rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
 	}
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index b29affd9c5d..8c3ea7e3606 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -63,7 +63,7 @@ void rs400_gart_adjust_size(struct radeon_device *rdev)
 		break;
 	default:
 		DRM_ERROR("Unable to use IGP GART size %uM\n",
-			  rdev->mc.gtt_size >> 20);
+			  (unsigned)(rdev->mc.gtt_size >> 20));
 		DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
 		DRM_ERROR("Forcing to 32M GART size\n");
 		rdev->mc.gtt_size = 32 * 1024 * 1024;
diff --git a/drivers/gpu/drm/radeon/rs780.c b/drivers/gpu/drm/radeon/rs780.c
deleted file mode 100644
index 0affcff8182..00000000000
--- a/drivers/gpu/drm/radeon/rs780.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Copyright 2008 Advanced Micro Devices, Inc.
- * Copyright 2008 Red Hat Inc.
- * Copyright 2009 Jerome Glisse.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- *          Alex Deucher
- *          Jerome Glisse
- */
-#include "drmP.h"
-#include "radeon_reg.h"
-#include "radeon.h"
-
-/* rs780  depends on : */
-void rs600_mc_disable_clients(struct radeon_device *rdev);
-
-/* This files gather functions specifics to:
- * rs780
- *
- * Some of these functions might be used by newer ASICs.
- */
-int rs780_mc_wait_for_idle(struct radeon_device *rdev);
-void rs780_gpu_init(struct radeon_device *rdev);
-
-
-/*
- * MC
- */
-int rs780_mc_init(struct radeon_device *rdev)
-{
-	rs780_gpu_init(rdev);
-	/* FIXME: implement */
-
-	rs600_mc_disable_clients(rdev);
-	if (rs780_mc_wait_for_idle(rdev)) {
-		printk(KERN_WARNING "Failed to wait MC idle while "
-		       "programming pipes. Bad things might happen.\n");
-	}
-	return 0;
-}
-
-void rs780_mc_fini(struct radeon_device *rdev)
-{
-	/* FIXME: implement */
-}
-
-
-/*
- * Global GPU functions
- */
-void rs780_errata(struct radeon_device *rdev)
-{
-	rdev->pll_errata = 0;
-}
-
-int rs780_mc_wait_for_idle(struct radeon_device *rdev)
-{
-	/* FIXME: implement */
-	return 0;
-}
-
-void rs780_gpu_init(struct radeon_device *rdev)
-{
-	/* FIXME: implement */
-}
-
-
-/*
- * VRAM info
- */
-void rs780_vram_get_type(struct radeon_device *rdev)
-{
-	/* FIXME: implement */
-}
-
-void rs780_vram_info(struct radeon_device *rdev)
-{
-	rs780_vram_get_type(rdev);
-
-	/* FIXME: implement */
-	/* Could aper size report 0 ? */
-	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
-	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
-}
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 97965c430c1..99e397f1638 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -27,7 +27,7 @@
  */
 #include <linux/seq_file.h>
 #include "drmP.h"
-#include "rv515r.h"
+#include "rv515d.h"
 #include "radeon.h"
 #include "radeon_share.h"
 
diff --git a/drivers/gpu/drm/radeon/rv515d.h b/drivers/gpu/drm/radeon/rv515d.h
new file mode 100644
index 00000000000..a65e17ec1c0
--- /dev/null
+++ b/drivers/gpu/drm/radeon/rv515d.h
@@ -0,0 +1,220 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#ifndef __RV515D_H__
+#define __RV515D_H__
+
+/*
+ * RV515 registers
+ */
+#define PCIE_INDEX			0x0030
+#define PCIE_DATA			0x0034
+#define	MC_IND_INDEX			0x0070
+#define		MC_IND_WR_EN				(1 << 24)
+#define	MC_IND_DATA			0x0074
+#define	RBBM_SOFT_RESET			0x00F0
+#define	CONFIG_MEMSIZE			0x00F8
+#define HDP_FB_LOCATION			0x0134
+#define	CP_CSQ_CNTL			0x0740
+#define	CP_CSQ_MODE			0x0744
+#define	CP_CSQ_ADDR			0x07F0
+#define	CP_CSQ_DATA			0x07F4
+#define	CP_CSQ_STAT			0x07F8
+#define	CP_CSQ2_STAT			0x07FC
+#define	RBBM_STATUS			0x0E40
+#define	DST_PIPE_CONFIG			0x170C
+#define	WAIT_UNTIL			0x1720
+#define		WAIT_2D_IDLE				(1 << 14)
+#define		WAIT_3D_IDLE				(1 << 15)
+#define		WAIT_2D_IDLECLEAN			(1 << 16)
+#define		WAIT_3D_IDLECLEAN			(1 << 17)
+#define	ISYNC_CNTL			0x1724
+#define		ISYNC_ANY2D_IDLE3D			(1 << 0)
+#define		ISYNC_ANY3D_IDLE2D			(1 << 1)
+#define		ISYNC_TRIG2D_IDLE3D			(1 << 2)
+#define		ISYNC_TRIG3D_IDLE2D			(1 << 3)
+#define		ISYNC_WAIT_IDLEGUI			(1 << 4)
+#define		ISYNC_CPSCRATCH_IDLEGUI			(1 << 5)
+#define	VAP_INDEX_OFFSET		0x208C
+#define	VAP_PVS_STATE_FLUSH_REG		0x2284
+#define	GB_ENABLE			0x4008
+#define	GB_MSPOS0			0x4010
+#define		MS_X0_SHIFT				0
+#define		MS_Y0_SHIFT				4
+#define		MS_X1_SHIFT				8
+#define		MS_Y1_SHIFT				12
+#define		MS_X2_SHIFT				16
+#define		MS_Y2_SHIFT				20
+#define		MSBD0_Y_SHIFT				24
+#define		MSBD0_X_SHIFT				28
+#define	GB_MSPOS1			0x4014
+#define		MS_X3_SHIFT				0
+#define		MS_Y3_SHIFT				4
+#define		MS_X4_SHIFT				8
+#define		MS_Y4_SHIFT				12
+#define		MS_X5_SHIFT				16
+#define		MS_Y5_SHIFT				20
+#define		MSBD1_SHIFT				24
+#define GB_TILE_CONFIG			0x4018
+#define		ENABLE_TILING				(1 << 0)
+#define		PIPE_COUNT_MASK				0x0000000E
+#define		PIPE_COUNT_SHIFT			1
+#define		TILE_SIZE_8				(0 << 4)
+#define		TILE_SIZE_16				(1 << 4)
+#define		TILE_SIZE_32				(2 << 4)
+#define		SUBPIXEL_1_12				(0 << 16)
+#define		SUBPIXEL_1_16				(1 << 16)
+#define	GB_SELECT			0x401C
+#define	GB_AA_CONFIG			0x4020
+#define	GB_PIPE_SELECT			0x402C
+#define	GA_ENHANCE			0x4274
+#define		GA_DEADLOCK_CNTL			(1 << 0)
+#define		GA_FASTSYNC_CNTL			(1 << 1)
+#define	GA_POLY_MODE			0x4288
+#define		FRONT_PTYPE_POINT			(0 << 4)
+#define		FRONT_PTYPE_LINE			(1 << 4)
+#define		FRONT_PTYPE_TRIANGE			(2 << 4)
+#define		BACK_PTYPE_POINT			(0 << 7)
+#define		BACK_PTYPE_LINE				(1 << 7)
+#define		BACK_PTYPE_TRIANGE			(2 << 7)
+#define	GA_ROUND_MODE			0x428C
+#define		GEOMETRY_ROUND_TRUNC			(0 << 0)
+#define		GEOMETRY_ROUND_NEAREST			(1 << 0)
+#define		COLOR_ROUND_TRUNC			(0 << 2)
+#define		COLOR_ROUND_NEAREST			(1 << 2)
+#define	SU_REG_DEST			0x42C8
+#define	RB3D_DSTCACHE_CTLSTAT		0x4E4C
+#define		RB3D_DC_FLUSH				(2 << 0)
+#define		RB3D_DC_FREE				(2 << 2)
+#define		RB3D_DC_FINISH				(1 << 4)
+#define ZB_ZCACHE_CTLSTAT		0x4F18
+#define		ZC_FLUSH				(1 << 0)
+#define		ZC_FREE					(1 << 1)
+#define DC_LB_MEMORY_SPLIT		0x6520
+#define		DC_LB_MEMORY_SPLIT_MASK			0x00000003
+#define		DC_LB_MEMORY_SPLIT_SHIFT		0
+#define		DC_LB_MEMORY_SPLIT_D1HALF_D2HALF	0
+#define		DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q		1
+#define		DC_LB_MEMORY_SPLIT_D1_ONLY		2
+#define		DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q		3
+#define		DC_LB_MEMORY_SPLIT_SHIFT_MODE		(1 << 2)
+#define		DC_LB_DISP1_END_ADR_SHIFT		4
+#define		DC_LB_DISP1_END_ADR_MASK		0x00007FF0
+#define D1MODE_PRIORITY_A_CNT		0x6548
+#define		MODE_PRIORITY_MARK_MASK			0x00007FFF
+#define		MODE_PRIORITY_OFF			(1 << 16)
+#define		MODE_PRIORITY_ALWAYS_ON			(1 << 20)
+#define		MODE_PRIORITY_FORCE_MASK		(1 << 24)
+#define D1MODE_PRIORITY_B_CNT		0x654C
+#define LB_MAX_REQ_OUTSTANDING		0x6D58
+#define		LB_D1_MAX_REQ_OUTSTANDING_MASK		0x0000000F
+#define		LB_D1_MAX_REQ_OUTSTANDING_SHIFT		0
+#define		LB_D2_MAX_REQ_OUTSTANDING_MASK		0x000F0000
+#define		LB_D2_MAX_REQ_OUTSTANDING_SHIFT		16
+#define D2MODE_PRIORITY_A_CNT		0x6D48
+#define D2MODE_PRIORITY_B_CNT		0x6D4C
+
+/* ix[MC] registers */
+#define MC_FB_LOCATION			0x01
+#define		MC_FB_START_MASK			0x0000FFFF
+#define		MC_FB_START_SHIFT			0
+#define		MC_FB_TOP_MASK				0xFFFF0000
+#define		MC_FB_TOP_SHIFT				16
+#define MC_AGP_LOCATION			0x02
+#define		MC_AGP_START_MASK			0x0000FFFF
+#define		MC_AGP_START_SHIFT			0
+#define		MC_AGP_TOP_MASK				0xFFFF0000
+#define		MC_AGP_TOP_SHIFT			16
+#define MC_AGP_BASE			0x03
+#define MC_AGP_BASE_2			0x04
+#define	MC_CNTL				0x5
+#define		MEM_NUM_CHANNELS_MASK			0x00000003
+#define	MC_STATUS			0x08
+#define		MC_STATUS_IDLE				(1 << 4)
+#define	MC_MISC_LAT_TIMER		0x09
+#define		MC_CPR_INIT_LAT_MASK			0x0000000F
+#define		MC_VF_INIT_LAT_MASK			0x000000F0
+#define		MC_DISP0R_INIT_LAT_MASK			0x00000F00
+#define		MC_DISP0R_INIT_LAT_SHIFT		8
+#define		MC_DISP1R_INIT_LAT_MASK			0x0000F000
+#define		MC_DISP1R_INIT_LAT_SHIFT		12
+#define		MC_FIXED_INIT_LAT_MASK			0x000F0000
+#define		MC_E2R_INIT_LAT_MASK			0x00F00000
+#define		SAME_PAGE_PRIO_MASK			0x0F000000
+#define		MC_GLOBW_INIT_LAT_MASK			0xF0000000
+
+
+/*
+ * PM4 packet
+ */
+#define CP_PACKET0			0x00000000
+#define		PACKET0_BASE_INDEX_SHIFT	0
+#define		PACKET0_BASE_INDEX_MASK		(0x1ffff << 0)
+#define		PACKET0_COUNT_SHIFT		16
+#define		PACKET0_COUNT_MASK		(0x3fff << 16)
+#define CP_PACKET1			0x40000000
+#define CP_PACKET2			0x80000000
+#define		PACKET2_PAD_SHIFT		0
+#define		PACKET2_PAD_MASK		(0x3fffffff << 0)
+#define CP_PACKET3			0xC0000000
+#define		PACKET3_IT_OPCODE_SHIFT		8
+#define		PACKET3_IT_OPCODE_MASK		(0xff << 8)
+#define		PACKET3_COUNT_SHIFT		16
+#define		PACKET3_COUNT_MASK		(0x3fff << 16)
+/* PACKET3 op code */
+#define		PACKET3_NOP			0x10
+#define		PACKET3_3D_DRAW_VBUF		0x28
+#define		PACKET3_3D_DRAW_IMMD		0x29
+#define		PACKET3_3D_DRAW_INDX		0x2A
+#define		PACKET3_3D_LOAD_VBPNTR		0x2F
+#define		PACKET3_INDX_BUFFER		0x33
+#define		PACKET3_3D_DRAW_VBUF_2		0x34
+#define		PACKET3_3D_DRAW_IMMD_2		0x35
+#define		PACKET3_3D_DRAW_INDX_2		0x36
+#define		PACKET3_BITBLT_MULTI		0x9B
+
+#define PACKET0(reg, n)	(CP_PACKET0 |					\
+			 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) |	\
+			 REG_SET(PACKET0_COUNT, (n)))
+#define PACKET2(v)	(CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
+#define PACKET3(op, n)	(CP_PACKET3 |					\
+			 REG_SET(PACKET3_IT_OPCODE, (op)) |		\
+			 REG_SET(PACKET3_COUNT, (n)))
+
+#define	PACKET_TYPE0	0
+#define	PACKET_TYPE1	1
+#define	PACKET_TYPE2	2
+#define	PACKET_TYPE3	3
+
+#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
+#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
+#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
+#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
+#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
+
+#endif
+
diff --git a/drivers/gpu/drm/radeon/rv515r.h b/drivers/gpu/drm/radeon/rv515r.h
deleted file mode 100644
index f3cf8403990..00000000000
--- a/drivers/gpu/drm/radeon/rv515r.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * Copyright 2008 Advanced Micro Devices, Inc.
- * Copyright 2008 Red Hat Inc.
- * Copyright 2009 Jerome Glisse.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- *          Alex Deucher
- *          Jerome Glisse
- */
-#ifndef RV515R_H
-#define RV515R_H
-
-/* RV515 registers */
-#define PCIE_INDEX			0x0030
-#define PCIE_DATA			0x0034
-#define	MC_IND_INDEX			0x0070
-#define		MC_IND_WR_EN				(1 << 24)
-#define	MC_IND_DATA			0x0074
-#define	RBBM_SOFT_RESET			0x00F0
-#define	CONFIG_MEMSIZE			0x00F8
-#define HDP_FB_LOCATION			0x0134
-#define	CP_CSQ_CNTL			0x0740
-#define	CP_CSQ_MODE			0x0744
-#define	CP_CSQ_ADDR			0x07F0
-#define	CP_CSQ_DATA			0x07F4
-#define	CP_CSQ_STAT			0x07F8
-#define	CP_CSQ2_STAT			0x07FC
-#define	RBBM_STATUS			0x0E40
-#define	DST_PIPE_CONFIG			0x170C
-#define	WAIT_UNTIL			0x1720
-#define		WAIT_2D_IDLE				(1 << 14)
-#define		WAIT_3D_IDLE				(1 << 15)
-#define		WAIT_2D_IDLECLEAN			(1 << 16)
-#define		WAIT_3D_IDLECLEAN			(1 << 17)
-#define	ISYNC_CNTL			0x1724
-#define		ISYNC_ANY2D_IDLE3D			(1 << 0)
-#define		ISYNC_ANY3D_IDLE2D			(1 << 1)
-#define		ISYNC_TRIG2D_IDLE3D			(1 << 2)
-#define		ISYNC_TRIG3D_IDLE2D			(1 << 3)
-#define		ISYNC_WAIT_IDLEGUI			(1 << 4)
-#define		ISYNC_CPSCRATCH_IDLEGUI			(1 << 5)
-#define	VAP_INDEX_OFFSET		0x208C
-#define	VAP_PVS_STATE_FLUSH_REG		0x2284
-#define	GB_ENABLE			0x4008
-#define	GB_MSPOS0			0x4010
-#define		MS_X0_SHIFT				0
-#define		MS_Y0_SHIFT				4
-#define		MS_X1_SHIFT				8
-#define		MS_Y1_SHIFT				12
-#define		MS_X2_SHIFT				16
-#define		MS_Y2_SHIFT				20
-#define		MSBD0_Y_SHIFT				24
-#define		MSBD0_X_SHIFT				28
-#define	GB_MSPOS1			0x4014
-#define		MS_X3_SHIFT				0
-#define		MS_Y3_SHIFT				4
-#define		MS_X4_SHIFT				8
-#define		MS_Y4_SHIFT				12
-#define		MS_X5_SHIFT				16
-#define		MS_Y5_SHIFT				20
-#define		MSBD1_SHIFT				24
-#define GB_TILE_CONFIG			0x4018
-#define		ENABLE_TILING				(1 << 0)
-#define		PIPE_COUNT_MASK				0x0000000E
-#define		PIPE_COUNT_SHIFT			1
-#define		TILE_SIZE_8				(0 << 4)
-#define		TILE_SIZE_16				(1 << 4)
-#define		TILE_SIZE_32				(2 << 4)
-#define		SUBPIXEL_1_12				(0 << 16)
-#define		SUBPIXEL_1_16				(1 << 16)
-#define	GB_SELECT			0x401C
-#define	GB_AA_CONFIG			0x4020
-#define	GB_PIPE_SELECT			0x402C
-#define	GA_ENHANCE			0x4274
-#define		GA_DEADLOCK_CNTL			(1 << 0)
-#define		GA_FASTSYNC_CNTL			(1 << 1)
-#define	GA_POLY_MODE			0x4288
-#define		FRONT_PTYPE_POINT			(0 << 4)
-#define		FRONT_PTYPE_LINE			(1 << 4)
-#define		FRONT_PTYPE_TRIANGE			(2 << 4)
-#define		BACK_PTYPE_POINT			(0 << 7)
-#define		BACK_PTYPE_LINE				(1 << 7)
-#define		BACK_PTYPE_TRIANGE			(2 << 7)
-#define	GA_ROUND_MODE			0x428C
-#define		GEOMETRY_ROUND_TRUNC			(0 << 0)
-#define		GEOMETRY_ROUND_NEAREST			(1 << 0)
-#define		COLOR_ROUND_TRUNC			(0 << 2)
-#define		COLOR_ROUND_NEAREST			(1 << 2)
-#define	SU_REG_DEST			0x42C8
-#define	RB3D_DSTCACHE_CTLSTAT		0x4E4C
-#define		RB3D_DC_FLUSH				(2 << 0)
-#define		RB3D_DC_FREE				(2 << 2)
-#define		RB3D_DC_FINISH				(1 << 4)
-#define ZB_ZCACHE_CTLSTAT		0x4F18
-#define		ZC_FLUSH				(1 << 0)
-#define		ZC_FREE					(1 << 1)
-#define DC_LB_MEMORY_SPLIT		0x6520
-#define		DC_LB_MEMORY_SPLIT_MASK			0x00000003
-#define		DC_LB_MEMORY_SPLIT_SHIFT		0
-#define		DC_LB_MEMORY_SPLIT_D1HALF_D2HALF	0
-#define		DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q		1
-#define		DC_LB_MEMORY_SPLIT_D1_ONLY		2
-#define		DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q		3
-#define		DC_LB_MEMORY_SPLIT_SHIFT_MODE		(1 << 2)
-#define		DC_LB_DISP1_END_ADR_SHIFT		4
-#define		DC_LB_DISP1_END_ADR_MASK		0x00007FF0
-#define D1MODE_PRIORITY_A_CNT		0x6548
-#define		MODE_PRIORITY_MARK_MASK			0x00007FFF
-#define		MODE_PRIORITY_OFF			(1 << 16)
-#define		MODE_PRIORITY_ALWAYS_ON			(1 << 20)
-#define		MODE_PRIORITY_FORCE_MASK		(1 << 24)
-#define D1MODE_PRIORITY_B_CNT		0x654C
-#define LB_MAX_REQ_OUTSTANDING		0x6D58
-#define		LB_D1_MAX_REQ_OUTSTANDING_MASK		0x0000000F
-#define		LB_D1_MAX_REQ_OUTSTANDING_SHIFT		0
-#define		LB_D2_MAX_REQ_OUTSTANDING_MASK		0x000F0000
-#define		LB_D2_MAX_REQ_OUTSTANDING_SHIFT		16
-#define D2MODE_PRIORITY_A_CNT		0x6D48
-#define D2MODE_PRIORITY_B_CNT		0x6D4C
-
-/* ix[MC] registers */
-#define MC_FB_LOCATION			0x01
-#define		MC_FB_START_MASK			0x0000FFFF
-#define		MC_FB_START_SHIFT			0
-#define		MC_FB_TOP_MASK				0xFFFF0000
-#define		MC_FB_TOP_SHIFT				16
-#define MC_AGP_LOCATION			0x02
-#define		MC_AGP_START_MASK			0x0000FFFF
-#define		MC_AGP_START_SHIFT			0
-#define		MC_AGP_TOP_MASK				0xFFFF0000
-#define		MC_AGP_TOP_SHIFT			16
-#define MC_AGP_BASE			0x03
-#define MC_AGP_BASE_2			0x04
-#define	MC_CNTL				0x5
-#define		MEM_NUM_CHANNELS_MASK			0x00000003
-#define	MC_STATUS			0x08
-#define		MC_STATUS_IDLE				(1 << 4)
-#define	MC_MISC_LAT_TIMER		0x09
-#define		MC_CPR_INIT_LAT_MASK			0x0000000F
-#define		MC_VF_INIT_LAT_MASK			0x000000F0
-#define		MC_DISP0R_INIT_LAT_MASK			0x00000F00
-#define		MC_DISP0R_INIT_LAT_SHIFT		8
-#define		MC_DISP1R_INIT_LAT_MASK			0x0000F000
-#define		MC_DISP1R_INIT_LAT_SHIFT		12
-#define		MC_FIXED_INIT_LAT_MASK			0x000F0000
-#define		MC_E2R_INIT_LAT_MASK			0x00F00000
-#define		SAME_PAGE_PRIO_MASK			0x0F000000
-#define		MC_GLOBW_INIT_LAT_MASK			0xF0000000
-
-
-#endif
-
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 21d8ffd5730..57765f6d5b2 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -25,100 +25,975 @@
  *          Alex Deucher
  *          Jerome Glisse
  */
+#include <linux/firmware.h>
+#include <linux/platform_device.h>
 #include "drmP.h"
-#include "radeon_reg.h"
 #include "radeon.h"
+#include "radeon_share.h"
+#include "rv770d.h"
+#include "avivod.h"
+#include "atom.h"
 
-/* rv770,rv730,rv710  depends on : */
-void rs600_mc_disable_clients(struct radeon_device *rdev);
+#define R700_PFP_UCODE_SIZE 848
+#define R700_PM4_UCODE_SIZE 1360
 
-/* This files gather functions specifics to:
- * rv770,rv730,rv710
- *
- * Some of these functions might be used by newer ASICs.
- */
-int rv770_mc_wait_for_idle(struct radeon_device *rdev);
-void rv770_gpu_init(struct radeon_device *rdev);
+static void rv770_gpu_init(struct radeon_device *rdev);
+void rv770_fini(struct radeon_device *rdev);
 
 
 /*
- * MC
+ * GART
  */
-int rv770_mc_init(struct radeon_device *rdev)
+int rv770_pcie_gart_enable(struct radeon_device *rdev)
 {
-	uint32_t tmp;
+	u32 tmp;
+	int r, i;
 
-	rv770_gpu_init(rdev);
+	/* Initialize common gart structure */
+	r = radeon_gart_init(rdev);
+	if (r) {
+		return r;
+	}
+	rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
+	r = radeon_gart_table_vram_alloc(rdev);
+	if (r) {
+		return r;
+	}
+	for (i = 0; i < rdev->gart.num_gpu_pages; i++)
+		r600_gart_clear_page(rdev, i);
+	/* Setup L2 cache */
+	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
+				ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
+				EFFECTIVE_L2_QUEUE_SIZE(7));
+	WREG32(VM_L2_CNTL2, 0);
+	WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
+	/* Setup TLB control */
+	tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
+		SYSTEM_ACCESS_MODE_NOT_IN_SYS |
+		SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
+		EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
+	WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
+	WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
+	WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
+	WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
+	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
+	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
+	WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
+	WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
+	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12);
+	WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
+	WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
+				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
+	WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
+			(u32)(rdev->dummy_page.addr >> 12));
+	for (i = 1; i < 7; i++)
+		WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 
-	/* setup the gart before changing location so we can ask to
-	 * discard unmapped mc request
-	 */
-	/* FIXME: disable out of gart access */
-	tmp = rdev->mc.gtt_location / 4096;
-	tmp = REG_SET(R700_LOGICAL_PAGE_NUMBER, tmp);
-	WREG32(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, tmp);
-	tmp = (rdev->mc.gtt_location + rdev->mc.gtt_size) / 4096;
-	tmp = REG_SET(R700_LOGICAL_PAGE_NUMBER, tmp);
-	WREG32(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, tmp);
-
-	rs600_mc_disable_clients(rdev);
-	if (rv770_mc_wait_for_idle(rdev)) {
-		printk(KERN_WARNING "Failed to wait MC idle while "
-		       "programming pipes. Bad things might happen.\n");
-	}
-
-	tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
-	tmp = REG_SET(R700_MC_FB_TOP, tmp >> 24);
-	tmp |= REG_SET(R700_MC_FB_BASE, rdev->mc.vram_location >> 24);
-	WREG32(R700_MC_VM_FB_LOCATION, tmp);
-	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
-	tmp = REG_SET(R700_MC_AGP_TOP, tmp >> 22);
-	WREG32(R700_MC_VM_AGP_TOP, tmp);
-	tmp = REG_SET(R700_MC_AGP_BOT, rdev->mc.gtt_location >> 22);
-	WREG32(R700_MC_VM_AGP_BOT, tmp);
+	r600_pcie_gart_tlb_flush(rdev);
+	rdev->gart.ready = true;
 	return 0;
 }
 
-void rv770_mc_fini(struct radeon_device *rdev)
+void rv770_pcie_gart_disable(struct radeon_device *rdev)
 {
-	/* FIXME: implement */
+	u32 tmp;
+	int i;
+
+	/* Clear ptes*/
+	for (i = 0; i < rdev->gart.num_gpu_pages; i++)
+		r600_gart_clear_page(rdev, i);
+	r600_pcie_gart_tlb_flush(rdev);
+	/* Disable all tables */
+	for (i = 0; i < 7; i++)
+		WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
+
+	/* Setup L2 cache */
+	WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
+				EFFECTIVE_L2_QUEUE_SIZE(7));
+	WREG32(VM_L2_CNTL2, 0);
+	WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
+	/* Setup TLB control */
+	tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
+	WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
+	WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
+	WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
+	WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
+	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
+	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
+	WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 }
 
 
 /*
- * Global GPU functions
+ * MC
  */
-void rv770_errata(struct radeon_device *rdev)
+static void rv770_mc_resume(struct radeon_device *rdev)
 {
-	rdev->pll_errata = 0;
+	u32 d1vga_control, d2vga_control;
+	u32 vga_render_control, vga_hdp_control;
+	u32 d1crtc_control, d2crtc_control;
+	u32 new_d1grph_primary, new_d1grph_secondary;
+	u32 new_d2grph_primary, new_d2grph_secondary;
+	u64 old_vram_start;
+	u32 tmp;
+	int i, j;
+
+	/* Initialize HDP */
+	for (i = 0, j = 0; i < 32; i++, j += 0x18) {
+		WREG32((0x2c14 + j), 0x00000000);
+		WREG32((0x2c18 + j), 0x00000000);
+		WREG32((0x2c1c + j), 0x00000000);
+		WREG32((0x2c20 + j), 0x00000000);
+		WREG32((0x2c24 + j), 0x00000000);
+	}
+	WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
+
+	d1vga_control = RREG32(D1VGA_CONTROL);
+	d2vga_control = RREG32(D2VGA_CONTROL);
+	vga_render_control = RREG32(VGA_RENDER_CONTROL);
+	vga_hdp_control = RREG32(VGA_HDP_CONTROL);
+	d1crtc_control = RREG32(D1CRTC_CONTROL);
+	d2crtc_control = RREG32(D2CRTC_CONTROL);
+	old_vram_start = (u64)(RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
+	new_d1grph_primary = RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS);
+	new_d1grph_secondary = RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS);
+	new_d1grph_primary += rdev->mc.vram_start - old_vram_start;
+	new_d1grph_secondary += rdev->mc.vram_start - old_vram_start;
+	new_d2grph_primary = RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS);
+	new_d2grph_secondary = RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS);
+	new_d2grph_primary += rdev->mc.vram_start - old_vram_start;
+	new_d2grph_secondary += rdev->mc.vram_start - old_vram_start;
+
+	/* Stop all video */
+	WREG32(D1VGA_CONTROL, 0);
+	WREG32(D2VGA_CONTROL, 0);
+	WREG32(VGA_RENDER_CONTROL, 0);
+	WREG32(D1CRTC_UPDATE_LOCK, 1);
+	WREG32(D2CRTC_UPDATE_LOCK, 1);
+	WREG32(D1CRTC_CONTROL, 0);
+	WREG32(D2CRTC_CONTROL, 0);
+	WREG32(D1CRTC_UPDATE_LOCK, 0);
+	WREG32(D2CRTC_UPDATE_LOCK, 0);
+
+	mdelay(1);
+	if (r600_mc_wait_for_idle(rdev)) {
+		printk(KERN_WARNING "[drm] MC not idle !\n");
+	}
+
+	/* Lockout access through VGA aperture*/
+	WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
+
+	/* Update configuration */
+	WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
+	WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12);
+	WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
+	tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16;
+	tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
+	WREG32(MC_VM_FB_LOCATION, tmp);
+	WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
+	WREG32(HDP_NONSURFACE_INFO, (2 << 7));
+	WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
+	if (rdev->flags & RADEON_IS_AGP) {
+		WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16);
+		WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
+		WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
+	} else {
+		WREG32(MC_VM_AGP_BASE, 0);
+		WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
+		WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
+	}
+	WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS, new_d1grph_primary);
+	WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS, new_d1grph_secondary);
+	WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS, new_d2grph_primary);
+	WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS, new_d2grph_secondary);
+	WREG32(VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
+
+	/* Unlock host access */
+	WREG32(VGA_HDP_CONTROL, vga_hdp_control);
+
+	mdelay(1);
+	if (r600_mc_wait_for_idle(rdev)) {
+		printk(KERN_WARNING "[drm] MC not idle !\n");
+	}
+
+	/* Restore video state */
+	WREG32(D1CRTC_UPDATE_LOCK, 1);
+	WREG32(D2CRTC_UPDATE_LOCK, 1);
+	WREG32(D1CRTC_CONTROL, d1crtc_control);
+	WREG32(D2CRTC_CONTROL, d2crtc_control);
+	WREG32(D1CRTC_UPDATE_LOCK, 0);
+	WREG32(D2CRTC_UPDATE_LOCK, 0);
+	WREG32(D1VGA_CONTROL, d1vga_control);
+	WREG32(D2VGA_CONTROL, d2vga_control);
+	WREG32(VGA_RENDER_CONTROL, vga_render_control);
 }
 
-int rv770_mc_wait_for_idle(struct radeon_device *rdev)
+
+/*
+ * CP.
+ */
+void r700_cp_stop(struct radeon_device *rdev)
 {
-	/* FIXME: implement */
-	return 0;
+	WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
 }
 
-void rv770_gpu_init(struct radeon_device *rdev)
+
+static int rv770_cp_load_microcode(struct radeon_device *rdev)
 {
-	/* FIXME: implement */
+	const __be32 *fw_data;
+	int i;
+
+	if (!rdev->me_fw || !rdev->pfp_fw)
+		return -EINVAL;
+
+	r700_cp_stop(rdev);
+	WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
+
+	/* Reset cp */
+	WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
+	RREG32(GRBM_SOFT_RESET);
+	mdelay(15);
+	WREG32(GRBM_SOFT_RESET, 0);
+
+	fw_data = (const __be32 *)rdev->pfp_fw->data;
+	WREG32(CP_PFP_UCODE_ADDR, 0);
+	for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
+		WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
+	WREG32(CP_PFP_UCODE_ADDR, 0);
+
+	fw_data = (const __be32 *)rdev->me_fw->data;
+	WREG32(CP_ME_RAM_WADDR, 0);
+	for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
+		WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
+
+	WREG32(CP_PFP_UCODE_ADDR, 0);
+	WREG32(CP_ME_RAM_WADDR, 0);
+	WREG32(CP_ME_RAM_RADDR, 0);
+	return 0;
 }
 
 
 /*
- * VRAM info
+ * Core functions
  */
-void rv770_vram_get_type(struct radeon_device *rdev)
+static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
+						u32 num_backends,
+						u32 backend_disable_mask)
 {
-	/* FIXME: implement */
+	u32 backend_map = 0;
+	u32 enabled_backends_mask;
+	u32 enabled_backends_count;
+	u32 cur_pipe;
+	u32 swizzle_pipe[R7XX_MAX_PIPES];
+	u32 cur_backend;
+	u32 i;
+
+	if (num_tile_pipes > R7XX_MAX_PIPES)
+		num_tile_pipes = R7XX_MAX_PIPES;
+	if (num_tile_pipes < 1)
+		num_tile_pipes = 1;
+	if (num_backends > R7XX_MAX_BACKENDS)
+		num_backends = R7XX_MAX_BACKENDS;
+	if (num_backends < 1)
+		num_backends = 1;
+
+	enabled_backends_mask = 0;
+	enabled_backends_count = 0;
+	for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
+		if (((backend_disable_mask >> i) & 1) == 0) {
+			enabled_backends_mask |= (1 << i);
+			++enabled_backends_count;
+		}
+		if (enabled_backends_count == num_backends)
+			break;
+	}
+
+	if (enabled_backends_count == 0) {
+		enabled_backends_mask = 1;
+		enabled_backends_count = 1;
+	}
+
+	if (enabled_backends_count != num_backends)
+		num_backends = enabled_backends_count;
+
+	memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
+	switch (num_tile_pipes) {
+	case 1:
+		swizzle_pipe[0] = 0;
+		break;
+	case 2:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 1;
+		break;
+	case 3:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 2;
+		swizzle_pipe[2] = 1;
+		break;
+	case 4:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 2;
+		swizzle_pipe[2] = 3;
+		swizzle_pipe[3] = 1;
+		break;
+	case 5:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 2;
+		swizzle_pipe[2] = 4;
+		swizzle_pipe[3] = 1;
+		swizzle_pipe[4] = 3;
+		break;
+	case 6:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 2;
+		swizzle_pipe[2] = 4;
+		swizzle_pipe[3] = 5;
+		swizzle_pipe[4] = 3;
+		swizzle_pipe[5] = 1;
+		break;
+	case 7:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 2;
+		swizzle_pipe[2] = 4;
+		swizzle_pipe[3] = 6;
+		swizzle_pipe[4] = 3;
+		swizzle_pipe[5] = 1;
+		swizzle_pipe[6] = 5;
+		break;
+	case 8:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 2;
+		swizzle_pipe[2] = 4;
+		swizzle_pipe[3] = 6;
+		swizzle_pipe[4] = 3;
+		swizzle_pipe[5] = 1;
+		swizzle_pipe[6] = 7;
+		swizzle_pipe[7] = 5;
+		break;
+	}
+
+	cur_backend = 0;
+	for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
+		while (((1 << cur_backend) & enabled_backends_mask) == 0)
+			cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
+
+		backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
+
+		cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
+	}
+
+	return backend_map;
 }
 
-void rv770_vram_info(struct radeon_device *rdev)
+static void rv770_gpu_init(struct radeon_device *rdev)
 {
-	rv770_vram_get_type(rdev);
+	int i, j, num_qd_pipes;
+	u32 sx_debug_1;
+	u32 smx_dc_ctl0;
+	u32 num_gs_verts_per_thread;
+	u32 vgt_gs_per_es;
+	u32 gs_prim_buffer_depth = 0;
+	u32 sq_ms_fifo_sizes;
+	u32 sq_config;
+	u32 sq_thread_resource_mgmt;
+	u32 hdp_host_path_cntl;
+	u32 sq_dyn_gpr_size_simd_ab_0;
+	u32 backend_map;
+	u32 gb_tiling_config = 0;
+	u32 cc_rb_backend_disable = 0;
+	u32 cc_gc_shader_pipe_config = 0;
+	u32 mc_arb_ramcfg;
+	u32 db_debug4;
 
-	/* FIXME: implement */
+	/* setup chip specs */
+	switch (rdev->family) {
+	case CHIP_RV770:
+		rdev->config.rv770.max_pipes = 4;
+		rdev->config.rv770.max_tile_pipes = 8;
+		rdev->config.rv770.max_simds = 10;
+		rdev->config.rv770.max_backends = 4;
+		rdev->config.rv770.max_gprs = 256;
+		rdev->config.rv770.max_threads = 248;
+		rdev->config.rv770.max_stack_entries = 512;
+		rdev->config.rv770.max_hw_contexts = 8;
+		rdev->config.rv770.max_gs_threads = 16 * 2;
+		rdev->config.rv770.sx_max_export_size = 128;
+		rdev->config.rv770.sx_max_export_pos_size = 16;
+		rdev->config.rv770.sx_max_export_smx_size = 112;
+		rdev->config.rv770.sq_num_cf_insts = 2;
+
+		rdev->config.rv770.sx_num_of_sets = 7;
+		rdev->config.rv770.sc_prim_fifo_size = 0xF9;
+		rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
+		rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
+		break;
+	case CHIP_RV730:
+		rdev->config.rv770.max_pipes = 2;
+		rdev->config.rv770.max_tile_pipes = 4;
+		rdev->config.rv770.max_simds = 8;
+		rdev->config.rv770.max_backends = 2;
+		rdev->config.rv770.max_gprs = 128;
+		rdev->config.rv770.max_threads = 248;
+		rdev->config.rv770.max_stack_entries = 256;
+		rdev->config.rv770.max_hw_contexts = 8;
+		rdev->config.rv770.max_gs_threads = 16 * 2;
+		rdev->config.rv770.sx_max_export_size = 256;
+		rdev->config.rv770.sx_max_export_pos_size = 32;
+		rdev->config.rv770.sx_max_export_smx_size = 224;
+		rdev->config.rv770.sq_num_cf_insts = 2;
+
+		rdev->config.rv770.sx_num_of_sets = 7;
+		rdev->config.rv770.sc_prim_fifo_size = 0xf9;
+		rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
+		rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
+		if (rdev->config.rv770.sx_max_export_pos_size > 16) {
+			rdev->config.rv770.sx_max_export_pos_size -= 16;
+			rdev->config.rv770.sx_max_export_smx_size += 16;
+		}
+		break;
+	case CHIP_RV710:
+		rdev->config.rv770.max_pipes = 2;
+		rdev->config.rv770.max_tile_pipes = 2;
+		rdev->config.rv770.max_simds = 2;
+		rdev->config.rv770.max_backends = 1;
+		rdev->config.rv770.max_gprs = 256;
+		rdev->config.rv770.max_threads = 192;
+		rdev->config.rv770.max_stack_entries = 256;
+		rdev->config.rv770.max_hw_contexts = 4;
+		rdev->config.rv770.max_gs_threads = 8 * 2;
+		rdev->config.rv770.sx_max_export_size = 128;
+		rdev->config.rv770.sx_max_export_pos_size = 16;
+		rdev->config.rv770.sx_max_export_smx_size = 112;
+		rdev->config.rv770.sq_num_cf_insts = 1;
+
+		rdev->config.rv770.sx_num_of_sets = 7;
+		rdev->config.rv770.sc_prim_fifo_size = 0x40;
+		rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
+		rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
+		break;
+	case CHIP_RV740:
+		rdev->config.rv770.max_pipes = 4;
+		rdev->config.rv770.max_tile_pipes = 4;
+		rdev->config.rv770.max_simds = 8;
+		rdev->config.rv770.max_backends = 4;
+		rdev->config.rv770.max_gprs = 256;
+		rdev->config.rv770.max_threads = 248;
+		rdev->config.rv770.max_stack_entries = 512;
+		rdev->config.rv770.max_hw_contexts = 8;
+		rdev->config.rv770.max_gs_threads = 16 * 2;
+		rdev->config.rv770.sx_max_export_size = 256;
+		rdev->config.rv770.sx_max_export_pos_size = 32;
+		rdev->config.rv770.sx_max_export_smx_size = 224;
+		rdev->config.rv770.sq_num_cf_insts = 2;
+
+		rdev->config.rv770.sx_num_of_sets = 7;
+		rdev->config.rv770.sc_prim_fifo_size = 0x100;
+		rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
+		rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
+
+		if (rdev->config.rv770.sx_max_export_pos_size > 16) {
+			rdev->config.rv770.sx_max_export_pos_size -= 16;
+			rdev->config.rv770.sx_max_export_smx_size += 16;
+		}
+		break;
+	default:
+		break;
+	}
+
+	/* Initialize HDP */
+	j = 0;
+	for (i = 0; i < 32; i++) {
+		WREG32((0x2c14 + j), 0x00000000);
+		WREG32((0x2c18 + j), 0x00000000);
+		WREG32((0x2c1c + j), 0x00000000);
+		WREG32((0x2c20 + j), 0x00000000);
+		WREG32((0x2c24 + j), 0x00000000);
+		j += 0x18;
+	}
+
+	WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
+
+	/* setup tiling, simd, pipe config */
+	mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
+
+	switch (rdev->config.rv770.max_tile_pipes) {
+	case 1:
+		gb_tiling_config |= PIPE_TILING(0);
+		break;
+	case 2:
+		gb_tiling_config |= PIPE_TILING(1);
+		break;
+	case 4:
+		gb_tiling_config |= PIPE_TILING(2);
+		break;
+	case 8:
+		gb_tiling_config |= PIPE_TILING(3);
+		break;
+	default:
+		break;
+	}
+
+	if (rdev->family == CHIP_RV770)
+		gb_tiling_config |= BANK_TILING(1);
+	else
+		gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_SHIFT) >> NOOFBANK_MASK);
+
+	gb_tiling_config |= GROUP_SIZE(0);
+
+	if (((mc_arb_ramcfg & NOOFROWS_MASK) & NOOFROWS_SHIFT) > 3) {
+		gb_tiling_config |= ROW_TILING(3);
+		gb_tiling_config |= SAMPLE_SPLIT(3);
+	} else {
+		gb_tiling_config |=
+			ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
+		gb_tiling_config |=
+			SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
+	}
+
+	gb_tiling_config |= BANK_SWAPS(1);
+
+	backend_map = r700_get_tile_pipe_to_backend_map(rdev->config.rv770.max_tile_pipes,
+							rdev->config.rv770.max_backends,
+							(0xff << rdev->config.rv770.max_backends) & 0xff);
+	gb_tiling_config |= BACKEND_MAP(backend_map);
+
+	cc_gc_shader_pipe_config =
+		INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
+	cc_gc_shader_pipe_config |=
+		INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
+
+	cc_rb_backend_disable =
+		BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
+
+	WREG32(GB_TILING_CONFIG, gb_tiling_config);
+	WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
+	WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
+
+	WREG32(CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
+	WREG32(CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
+	WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
+
+	WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
+	WREG32(CGTS_SYS_TCC_DISABLE, 0);
+	WREG32(CGTS_TCC_DISABLE, 0);
+	WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
+	WREG32(CGTS_USER_TCC_DISABLE, 0);
+
+	num_qd_pipes =
+		R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK);
+	WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
+	WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
+
+	/* set HW defaults for 3D engine */
+	WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
+						ROQ_IB2_START(0x2b)));
+
+	WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
+
+	WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
+					SYNC_GRADIENT |
+					SYNC_WALKER |
+					SYNC_ALIGNER));
+
+	sx_debug_1 = RREG32(SX_DEBUG_1);
+	sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
+	WREG32(SX_DEBUG_1, sx_debug_1);
+
+	smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
+	smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
+	smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
+	WREG32(SMX_DC_CTL0, smx_dc_ctl0);
+
+	WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
+					  GS_FLUSH_CTL(4) |
+					  ACK_FLUSH_CTL(3) |
+					  SYNC_FLUSH_CTL));
+
+	if (rdev->family == CHIP_RV770)
+		WREG32(DB_DEBUG3, DB_CLK_OFF_DELAY(0x1f));
+	else {
+		db_debug4 = RREG32(DB_DEBUG4);
+		db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
+		WREG32(DB_DEBUG4, db_debug4);
+	}
+
+	WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
+						   POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
+						   SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
+
+	WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
+						 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
+						 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
+
+	WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
+
+	WREG32(VGT_NUM_INSTANCES, 1);
+
+	WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
+
+	WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
+
+	WREG32(CP_PERFMON_CNTL, 0);
+
+	sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
+			    DONE_FIFO_HIWATER(0xe0) |
+			    ALU_UPDATE_FIFO_HIWATER(0x8));
+	switch (rdev->family) {
+	case CHIP_RV770:
+		sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
+		break;
+	case CHIP_RV730:
+	case CHIP_RV710:
+	case CHIP_RV740:
+	default:
+		sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
+		break;
+	}
+	WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
+
+	/* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
+	 * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
+	 */
+	sq_config = RREG32(SQ_CONFIG);
+	sq_config &= ~(PS_PRIO(3) |
+		       VS_PRIO(3) |
+		       GS_PRIO(3) |
+		       ES_PRIO(3));
+	sq_config |= (DX9_CONSTS |
+		      VC_ENABLE |
+		      EXPORT_SRC_C |
+		      PS_PRIO(0) |
+		      VS_PRIO(1) |
+		      GS_PRIO(2) |
+		      ES_PRIO(3));
+	if (rdev->family == CHIP_RV710)
+		/* no vertex cache */
+		sq_config &= ~VC_ENABLE;
+
+	WREG32(SQ_CONFIG, sq_config);
+
+	WREG32(SQ_GPR_RESOURCE_MGMT_1,  (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
+						    NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
+						    NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
+
+	WREG32(SQ_GPR_RESOURCE_MGMT_2,  (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
+						    NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
+
+	sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
+				   NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
+				   NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
+	if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
+		sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
+	else
+		sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
+	WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
+
+	WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
+						     NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
+
+	WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
+						     NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
+
+	sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
+				     SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
+				     SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
+				     SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
+
+	WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
+	WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
+	WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
+	WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
+	WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
+	WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
+	WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
+	WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
+
+	WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
+						     FORCE_EOV_MAX_REZ_CNT(255)));
+
+	if (rdev->family == CHIP_RV710)
+		WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
+							   AUTO_INVLD_EN(ES_AND_GS_AUTO)));
+	else
+		WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
+							   AUTO_INVLD_EN(ES_AND_GS_AUTO)));
+
+	switch (rdev->family) {
+	case CHIP_RV770:
+	case CHIP_RV730:
+	case CHIP_RV740:
+		gs_prim_buffer_depth = 384;
+		break;
+	case CHIP_RV710:
+		gs_prim_buffer_depth = 128;
+		break;
+	default:
+		break;
+	}
+
+	num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
+	vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
+	/* Max value for this is 256 */
+	if (vgt_gs_per_es > 256)
+		vgt_gs_per_es = 256;
+
+	WREG32(VGT_ES_PER_GS, 128);
+	WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
+	WREG32(VGT_GS_PER_VS, 2);
+
+	/* more default values. 2D/3D driver should adjust as needed */
+	WREG32(VGT_GS_VERTEX_REUSE, 16);
+	WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
+	WREG32(VGT_STRMOUT_EN, 0);
+	WREG32(SX_MISC, 0);
+	WREG32(PA_SC_MODE_CNTL, 0);
+	WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
+	WREG32(PA_SC_AA_CONFIG, 0);
+	WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
+	WREG32(PA_SC_LINE_STIPPLE, 0);
+	WREG32(SPI_INPUT_Z, 0);
+	WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
+	WREG32(CB_COLOR7_FRAG, 0);
+
+	/* clear render buffer base addresses */
+	WREG32(CB_COLOR0_BASE, 0);
+	WREG32(CB_COLOR1_BASE, 0);
+	WREG32(CB_COLOR2_BASE, 0);
+	WREG32(CB_COLOR3_BASE, 0);
+	WREG32(CB_COLOR4_BASE, 0);
+	WREG32(CB_COLOR5_BASE, 0);
+	WREG32(CB_COLOR6_BASE, 0);
+	WREG32(CB_COLOR7_BASE, 0);
+
+	WREG32(TCP_CNTL, 0);
+
+	hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
+	WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
+
+	WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
+
+	WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
+					  NUM_CLIP_SEQ(3)));
+
+}
+
+int rv770_mc_init(struct radeon_device *rdev)
+{
+	fixed20_12 a;
+	u32 tmp;
+	int r;
+
+	/* Get VRAM informations */
+	/* FIXME: Don't know how to determine vram width, need to check
+	 * vram_width usage
+	 */
+	rdev->mc.vram_width = 128;
+	rdev->mc.vram_is_ddr = true;
 	/* Could aper size report 0 ? */
 	rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 	rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
+	/* Setup GPU memory space */
+	rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
+	rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
+	if (rdev->flags & RADEON_IS_AGP) {
+		r = radeon_agp_init(rdev);
+		if (r)
+			return r;
+		/* gtt_size is setup by radeon_agp_init */
+		rdev->mc.gtt_location = rdev->mc.agp_base;
+		tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
+		/* Try to put vram before or after AGP because we
+		 * we want SYSTEM_APERTURE to cover both VRAM and
+		 * AGP so that GPU can catch out of VRAM/AGP access
+		 */
+		if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
+			/* Enought place before */
+			rdev->mc.vram_location = rdev->mc.gtt_location -
+							rdev->mc.mc_vram_size;
+		} else if (tmp > rdev->mc.mc_vram_size) {
+			/* Enought place after */
+			rdev->mc.vram_location = rdev->mc.gtt_location +
+							rdev->mc.gtt_size;
+		} else {
+			/* Try to setup VRAM then AGP might not
+			 * not work on some card
+			 */
+			rdev->mc.vram_location = 0x00000000UL;
+			rdev->mc.gtt_location = rdev->mc.mc_vram_size;
+		}
+	} else {
+		rdev->mc.vram_location = 0x00000000UL;
+		rdev->mc.gtt_location = rdev->mc.mc_vram_size;
+		rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
+	}
+	rdev->mc.vram_start = rdev->mc.vram_location;
+	rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size;
+	rdev->mc.gtt_start = rdev->mc.gtt_location;
+	rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size;
+	/* FIXME: we should enforce default clock in case GPU is not in
+	 * default setup
+	 */
+	a.full = rfixed_const(100);
+	rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
+	rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
+	return 0;
+}
+int rv770_gpu_reset(struct radeon_device *rdev)
+{
+	/* FIXME: implement */
+	return 0;
+}
+
+int rv770_resume(struct radeon_device *rdev)
+{
+	int r;
+
+	rv770_mc_resume(rdev);
+	r = rv770_pcie_gart_enable(rdev);
+	if (r)
+		return r;
+	rv770_gpu_init(rdev);
+	r = radeon_ring_init(rdev, rdev->cp.ring_size);
+	if (r)
+		return r;
+	r = rv770_cp_load_microcode(rdev);
+	if (r)
+		return r;
+	r = r600_cp_resume(rdev);
+	if (r)
+		return r;
+	r = r600_wb_init(rdev);
+	if (r)
+		return r;
+	return 0;
+}
+
+int rv770_suspend(struct radeon_device *rdev)
+{
+	/* FIXME: we should wait for ring to be empty */
+	r700_cp_stop(rdev);
+	return 0;
+}
+
+/* Plan is to move initialization in that function and use
+ * helper function so that radeon_device_init pretty much
+ * do nothing more than calling asic specific function. This
+ * should also allow to remove a bunch of callback function
+ * like vram_info.
+ */
+int rv770_init(struct radeon_device *rdev)
+{
+	int r;
+
+	rdev->new_init_path = true;
+	r = radeon_dummy_page_init(rdev);
+	if (r)
+		return r;
+	/* This don't do much */
+	r = radeon_gem_init(rdev);
+	if (r)
+		return r;
+	/* Read BIOS */
+	if (!radeon_get_bios(rdev)) {
+		if (ASIC_IS_AVIVO(rdev))
+			return -EINVAL;
+	}
+	/* Must be an ATOMBIOS */
+	if (!rdev->is_atom_bios)
+		return -EINVAL;
+	r = radeon_atombios_init(rdev);
+	if (r)
+		return r;
+	/* Post card if necessary */
+	if (!r600_card_posted(rdev) && rdev->bios) {
+		DRM_INFO("GPU not posted. posting now...\n");
+		atom_asic_init(rdev->mode_info.atom_context);
+	}
+	/* Initialize scratch registers */
+	r600_scratch_init(rdev);
+	/* Initialize surface registers */
+	radeon_surface_init(rdev);
+	r = radeon_clocks_init(rdev);
+	if (r)
+		return r;
+	/* Fence driver */
+	r = radeon_fence_driver_init(rdev);
+	if (r)
+		return r;
+	r = rv770_mc_init(rdev);
+	if (r) {
+		if (rdev->flags & RADEON_IS_AGP) {
+			/* Retry with disabling AGP */
+			rv770_fini(rdev);
+			rdev->flags &= ~RADEON_IS_AGP;
+			return rv770_init(rdev);
+		}
+		return r;
+	}
+	/* Memory manager */
+	r = radeon_object_init(rdev);
+	if (r)
+		return r;
+	rdev->cp.ring_obj = NULL;
+	r600_ring_init(rdev, 1024 * 1024);
+
+	if (!rdev->me_fw || !rdev->pfp_fw) {
+		r = r600_cp_init_microcode(rdev);
+		if (r) {
+			DRM_ERROR("Failed to load firmware!\n");
+			return r;
+		}
+	}
+
+	r = rv770_resume(rdev);
+	if (r) {
+		if (rdev->flags & RADEON_IS_AGP) {
+			/* Retry with disabling AGP */
+			rv770_fini(rdev);
+			rdev->flags &= ~RADEON_IS_AGP;
+			return rv770_init(rdev);
+		}
+		return r;
+	}
+	r = r600_blit_init(rdev);
+	if (r) {
+		DRM_ERROR("radeon: failled blitter (%d).\n", r);
+		return r;
+	}
+	r = radeon_ib_pool_init(rdev);
+	if (r) {
+		DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
+		return r;
+	}
+	r = radeon_ib_test(rdev);
+	if (r) {
+		DRM_ERROR("radeon: failled testing IB (%d).\n", r);
+			return r;
+	}
+	return 0;
+}
+
+void rv770_fini(struct radeon_device *rdev)
+{
+	r600_blit_fini(rdev);
+	radeon_ring_fini(rdev);
+	rv770_pcie_gart_disable(rdev);
+	radeon_gart_table_vram_free(rdev);
+	radeon_gart_fini(rdev);
+	radeon_gem_fini(rdev);
+	radeon_fence_driver_fini(rdev);
+	radeon_clocks_fini(rdev);
+#if __OS_HAS_AGP
+	if (rdev->flags & RADEON_IS_AGP)
+		radeon_agp_fini(rdev);
+#endif
+	radeon_object_fini(rdev);
+	if (rdev->is_atom_bios) {
+		radeon_atombios_fini(rdev);
+	} else {
+		radeon_combios_fini(rdev);
+	}
+	kfree(rdev->bios);
+	rdev->bios = NULL;
+	radeon_dummy_page_fini(rdev);
 }
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
new file mode 100644
index 00000000000..4b9c3d6396f
--- /dev/null
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -0,0 +1,341 @@
+/*
+ * Copyright 2009 Advanced Micro Devices, Inc.
+ * Copyright 2009 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#ifndef RV770_H
+#define RV770_H
+
+#define R7XX_MAX_SH_GPRS           256
+#define R7XX_MAX_TEMP_GPRS         16
+#define R7XX_MAX_SH_THREADS        256
+#define R7XX_MAX_SH_STACK_ENTRIES  4096
+#define R7XX_MAX_BACKENDS          8
+#define R7XX_MAX_BACKENDS_MASK     0xff
+#define R7XX_MAX_SIMDS             16
+#define R7XX_MAX_SIMDS_MASK        0xffff
+#define R7XX_MAX_PIPES             8
+#define R7XX_MAX_PIPES_MASK        0xff
+
+/* Registers */
+#define	CB_COLOR0_BASE					0x28040
+#define	CB_COLOR1_BASE					0x28044
+#define	CB_COLOR2_BASE					0x28048
+#define	CB_COLOR3_BASE					0x2804C
+#define	CB_COLOR4_BASE					0x28050
+#define	CB_COLOR5_BASE					0x28054
+#define	CB_COLOR6_BASE					0x28058
+#define	CB_COLOR7_BASE					0x2805C
+#define	CB_COLOR7_FRAG					0x280FC
+
+#define	CC_GC_SHADER_PIPE_CONFIG			0x8950
+#define	CC_RB_BACKEND_DISABLE				0x98F4
+#define		BACKEND_DISABLE(x)				((x) << 16)
+#define	CC_SYS_RB_BACKEND_DISABLE			0x3F88
+
+#define	CGTS_SYS_TCC_DISABLE				0x3F90
+#define	CGTS_TCC_DISABLE				0x9148
+#define	CGTS_USER_SYS_TCC_DISABLE			0x3F94
+#define	CGTS_USER_TCC_DISABLE				0x914C
+
+#define	CONFIG_MEMSIZE					0x5428
+
+#define	CP_ME_CNTL					0x86D8
+#define		CP_ME_HALT					(1<<28)
+#define		CP_PFP_HALT					(1<<26)
+#define	CP_ME_RAM_DATA					0xC160
+#define	CP_ME_RAM_RADDR					0xC158
+#define	CP_ME_RAM_WADDR					0xC15C
+#define CP_MEQ_THRESHOLDS				0x8764
+#define		STQ_SPLIT(x)					((x) << 0)
+#define	CP_PERFMON_CNTL					0x87FC
+#define	CP_PFP_UCODE_ADDR				0xC150
+#define	CP_PFP_UCODE_DATA				0xC154
+#define	CP_QUEUE_THRESHOLDS				0x8760
+#define		ROQ_IB1_START(x)				((x) << 0)
+#define		ROQ_IB2_START(x)				((x) << 8)
+#define	CP_RB_CNTL					0xC104
+#define		RB_BUFSZ(x)					((x)<<0)
+#define		RB_BLKSZ(x)					((x)<<8)
+#define		RB_NO_UPDATE					(1<<27)
+#define		RB_RPTR_WR_ENA					(1<<31)
+#define		BUF_SWAP_32BIT					(2 << 16)
+#define	CP_RB_RPTR					0x8700
+#define	CP_RB_RPTR_ADDR					0xC10C
+#define	CP_RB_RPTR_ADDR_HI				0xC110
+#define	CP_RB_RPTR_WR					0xC108
+#define	CP_RB_WPTR					0xC114
+#define	CP_RB_WPTR_ADDR					0xC118
+#define	CP_RB_WPTR_ADDR_HI				0xC11C
+#define	CP_RB_WPTR_DELAY				0x8704
+#define	CP_SEM_WAIT_TIMER				0x85BC
+
+#define	DB_DEBUG3					0x98B0
+#define		DB_CLK_OFF_DELAY(x)				((x) << 11)
+#define DB_DEBUG4					0x9B8C
+#define		DISABLE_TILE_COVERED_FOR_PS_ITER		(1 << 6)
+
+#define	DCP_TILING_CONFIG				0x6CA0
+#define		PIPE_TILING(x)					((x) << 1)
+#define 	BANK_TILING(x)					((x) << 4)
+#define		GROUP_SIZE(x)					((x) << 6)
+#define		ROW_TILING(x)					((x) << 8)
+#define		BANK_SWAPS(x)					((x) << 11)
+#define		SAMPLE_SPLIT(x)					((x) << 14)
+#define		BACKEND_MAP(x)					((x) << 16)
+
+#define GB_TILING_CONFIG				0x98F0
+
+#define	GC_USER_SHADER_PIPE_CONFIG			0x8954
+#define		INACTIVE_QD_PIPES(x)				((x) << 8)
+#define		INACTIVE_QD_PIPES_MASK				0x0000FF00
+#define		INACTIVE_SIMDS(x)				((x) << 16)
+#define		INACTIVE_SIMDS_MASK				0x00FF0000
+
+#define	GRBM_CNTL					0x8000
+#define		GRBM_READ_TIMEOUT(x)				((x) << 0)
+#define	GRBM_SOFT_RESET					0x8020
+#define		SOFT_RESET_CP					(1<<0)
+#define	GRBM_STATUS					0x8010
+#define		CMDFIFO_AVAIL_MASK				0x0000000F
+#define		GUI_ACTIVE					(1<<31)
+#define	GRBM_STATUS2					0x8014
+
+#define	HDP_HOST_PATH_CNTL				0x2C00
+#define	HDP_NONSURFACE_BASE				0x2C04
+#define	HDP_NONSURFACE_INFO				0x2C08
+#define	HDP_NONSURFACE_SIZE				0x2C0C
+#define HDP_REG_COHERENCY_FLUSH_CNTL			0x54A0
+#define	HDP_TILING_CONFIG				0x2F3C
+
+#define	MC_ARB_RAMCFG					0x2760
+#define		NOOFBANK_SHIFT					0
+#define		NOOFBANK_MASK					0x00000003
+#define		NOOFRANK_SHIFT					2
+#define		NOOFRANK_MASK					0x00000004
+#define		NOOFROWS_SHIFT					3
+#define		NOOFROWS_MASK					0x00000038
+#define		NOOFCOLS_SHIFT					6
+#define		NOOFCOLS_MASK					0x000000C0
+#define		CHANSIZE_SHIFT					8
+#define		CHANSIZE_MASK					0x00000100
+#define		BURSTLENGTH_SHIFT				9
+#define		BURSTLENGTH_MASK				0x00000200
+#define	MC_VM_AGP_TOP					0x2028
+#define	MC_VM_AGP_BOT					0x202C
+#define	MC_VM_AGP_BASE					0x2030
+#define	MC_VM_FB_LOCATION				0x2024
+#define	MC_VM_MB_L1_TLB0_CNTL				0x2234
+#define	MC_VM_MB_L1_TLB1_CNTL				0x2238
+#define	MC_VM_MB_L1_TLB2_CNTL				0x223C
+#define	MC_VM_MB_L1_TLB3_CNTL				0x2240
+#define		ENABLE_L1_TLB					(1 << 0)
+#define		ENABLE_L1_FRAGMENT_PROCESSING			(1 << 1)
+#define		SYSTEM_ACCESS_MODE_PA_ONLY			(0 << 3)
+#define		SYSTEM_ACCESS_MODE_USE_SYS_MAP			(1 << 3)
+#define		SYSTEM_ACCESS_MODE_IN_SYS			(2 << 3)
+#define		SYSTEM_ACCESS_MODE_NOT_IN_SYS			(3 << 3)
+#define		SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU	(0 << 5)
+#define		EFFECTIVE_L1_TLB_SIZE(x)			((x)<<15)
+#define		EFFECTIVE_L1_QUEUE_SIZE(x)			((x)<<18)
+#define	MC_VM_MD_L1_TLB0_CNTL				0x2654
+#define	MC_VM_MD_L1_TLB1_CNTL				0x2658
+#define	MC_VM_MD_L1_TLB2_CNTL				0x265C
+#define	MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR		0x203C
+#define	MC_VM_SYSTEM_APERTURE_HIGH_ADDR			0x2038
+#define	MC_VM_SYSTEM_APERTURE_LOW_ADDR			0x2034
+
+#define	PA_CL_ENHANCE					0x8A14
+#define		CLIP_VTX_REORDER_ENA				(1 << 0)
+#define		NUM_CLIP_SEQ(x)					((x) << 1)
+#define PA_SC_AA_CONFIG					0x28C04
+#define PA_SC_CLIPRECT_RULE				0x2820C
+#define	PA_SC_EDGERULE					0x28230
+#define	PA_SC_FIFO_SIZE					0x8BCC
+#define		SC_PRIM_FIFO_SIZE(x)				((x) << 0)
+#define		SC_HIZ_TILE_FIFO_SIZE(x)			((x) << 12)
+#define	PA_SC_FORCE_EOV_MAX_CNTS			0x8B24
+#define		FORCE_EOV_MAX_CLK_CNT(x)			((x)<<0)
+#define		FORCE_EOV_MAX_REZ_CNT(x)			((x)<<16)
+#define PA_SC_LINE_STIPPLE				0x28A0C
+#define	PA_SC_LINE_STIPPLE_STATE			0x8B10
+#define PA_SC_MODE_CNTL					0x28A4C
+#define	PA_SC_MULTI_CHIP_CNTL				0x8B20
+#define		SC_EARLYZ_TILE_FIFO_SIZE(x)			((x) << 20)
+
+#define	SCRATCH_REG0					0x8500
+#define	SCRATCH_REG1					0x8504
+#define	SCRATCH_REG2					0x8508
+#define	SCRATCH_REG3					0x850C
+#define	SCRATCH_REG4					0x8510
+#define	SCRATCH_REG5					0x8514
+#define	SCRATCH_REG6					0x8518
+#define	SCRATCH_REG7					0x851C
+#define	SCRATCH_UMSK					0x8540
+#define	SCRATCH_ADDR					0x8544
+
+#define	SMX_DC_CTL0					0xA020
+#define		USE_HASH_FUNCTION				(1 << 0)
+#define		CACHE_DEPTH(x)					((x) << 1)
+#define		FLUSH_ALL_ON_EVENT				(1 << 10)
+#define		STALL_ON_EVENT					(1 << 11)
+#define	SMX_EVENT_CTL					0xA02C
+#define		ES_FLUSH_CTL(x)					((x) << 0)
+#define		GS_FLUSH_CTL(x)					((x) << 3)
+#define		ACK_FLUSH_CTL(x)				((x) << 6)
+#define		SYNC_FLUSH_CTL					(1 << 8)
+
+#define	SPI_CONFIG_CNTL					0x9100
+#define		GPR_WRITE_PRIORITY(x)				((x) << 0)
+#define		DISABLE_INTERP_1				(1 << 5)
+#define	SPI_CONFIG_CNTL_1				0x913C
+#define		VTX_DONE_DELAY(x)				((x) << 0)
+#define		INTERP_ONE_PRIM_PER_ROW				(1 << 4)
+#define	SPI_INPUT_Z					0x286D8
+#define	SPI_PS_IN_CONTROL_0				0x286CC
+#define		NUM_INTERP(x)					((x)<<0)
+#define		POSITION_ENA					(1<<8)
+#define		POSITION_CENTROID				(1<<9)
+#define		POSITION_ADDR(x)				((x)<<10)
+#define		PARAM_GEN(x)					((x)<<15)
+#define		PARAM_GEN_ADDR(x)				((x)<<19)
+#define		BARYC_SAMPLE_CNTL(x)				((x)<<26)
+#define		PERSP_GRADIENT_ENA				(1<<28)
+#define		LINEAR_GRADIENT_ENA				(1<<29)
+#define		POSITION_SAMPLE					(1<<30)
+#define		BARYC_AT_SAMPLE_ENA				(1<<31)
+
+#define	SQ_CONFIG					0x8C00
+#define		VC_ENABLE					(1 << 0)
+#define		EXPORT_SRC_C					(1 << 1)
+#define		DX9_CONSTS					(1 << 2)
+#define		ALU_INST_PREFER_VECTOR				(1 << 3)
+#define		DX10_CLAMP					(1 << 4)
+#define		CLAUSE_SEQ_PRIO(x)				((x) << 8)
+#define		PS_PRIO(x)					((x) << 24)
+#define		VS_PRIO(x)					((x) << 26)
+#define		GS_PRIO(x)					((x) << 28)
+#define	SQ_DYN_GPR_SIZE_SIMD_AB_0			0x8DB0
+#define		SIMDA_RING0(x)					((x)<<0)
+#define		SIMDA_RING1(x)					((x)<<8)
+#define		SIMDB_RING0(x)					((x)<<16)
+#define		SIMDB_RING1(x)					((x)<<24)
+#define	SQ_DYN_GPR_SIZE_SIMD_AB_1			0x8DB4
+#define	SQ_DYN_GPR_SIZE_SIMD_AB_2			0x8DB8
+#define	SQ_DYN_GPR_SIZE_SIMD_AB_3			0x8DBC
+#define	SQ_DYN_GPR_SIZE_SIMD_AB_4			0x8DC0
+#define	SQ_DYN_GPR_SIZE_SIMD_AB_5			0x8DC4
+#define	SQ_DYN_GPR_SIZE_SIMD_AB_6			0x8DC8
+#define	SQ_DYN_GPR_SIZE_SIMD_AB_7			0x8DCC
+#define		ES_PRIO(x)					((x) << 30)
+#define	SQ_GPR_RESOURCE_MGMT_1				0x8C04
+#define		NUM_PS_GPRS(x)					((x) << 0)
+#define		NUM_VS_GPRS(x)					((x) << 16)
+#define		DYN_GPR_ENABLE					(1 << 27)
+#define		NUM_CLAUSE_TEMP_GPRS(x)				((x) << 28)
+#define	SQ_GPR_RESOURCE_MGMT_2				0x8C08
+#define		NUM_GS_GPRS(x)					((x) << 0)
+#define		NUM_ES_GPRS(x)					((x) << 16)
+#define	SQ_MS_FIFO_SIZES				0x8CF0
+#define		CACHE_FIFO_SIZE(x)				((x) << 0)
+#define		FETCH_FIFO_HIWATER(x)				((x) << 8)
+#define		DONE_FIFO_HIWATER(x)				((x) << 16)
+#define		ALU_UPDATE_FIFO_HIWATER(x)			((x) << 24)
+#define	SQ_STACK_RESOURCE_MGMT_1			0x8C10
+#define		NUM_PS_STACK_ENTRIES(x)				((x) << 0)
+#define		NUM_VS_STACK_ENTRIES(x)				((x) << 16)
+#define	SQ_STACK_RESOURCE_MGMT_2			0x8C14
+#define		NUM_GS_STACK_ENTRIES(x)				((x) << 0)
+#define		NUM_ES_STACK_ENTRIES(x)				((x) << 16)
+#define	SQ_THREAD_RESOURCE_MGMT				0x8C0C
+#define		NUM_PS_THREADS(x)				((x) << 0)
+#define		NUM_VS_THREADS(x)				((x) << 8)
+#define		NUM_GS_THREADS(x)				((x) << 16)
+#define		NUM_ES_THREADS(x)				((x) << 24)
+
+#define	SX_DEBUG_1					0x9058
+#define		ENABLE_NEW_SMX_ADDRESS				(1 << 16)
+#define	SX_EXPORT_BUFFER_SIZES				0x900C
+#define		COLOR_BUFFER_SIZE(x)				((x) << 0)
+#define		POSITION_BUFFER_SIZE(x)				((x) << 8)
+#define		SMX_BUFFER_SIZE(x)				((x) << 16)
+#define	SX_MISC						0x28350
+
+#define	TA_CNTL_AUX					0x9508
+#define		DISABLE_CUBE_WRAP				(1 << 0)
+#define		DISABLE_CUBE_ANISO				(1 << 1)
+#define		SYNC_GRADIENT					(1 << 24)
+#define		SYNC_WALKER					(1 << 25)
+#define		SYNC_ALIGNER					(1 << 26)
+#define		BILINEAR_PRECISION_6_BIT			(0 << 31)
+#define		BILINEAR_PRECISION_8_BIT			(1 << 31)
+
+#define	TCP_CNTL					0x9610
+
+#define	VGT_CACHE_INVALIDATION				0x88C4
+#define		CACHE_INVALIDATION(x)				((x)<<0)
+#define			VC_ONLY						0
+#define			TC_ONLY						1
+#define			VC_AND_TC					2
+#define		AUTO_INVLD_EN(x)				((x) << 6)
+#define			NO_AUTO						0
+#define			ES_AUTO						1
+#define			GS_AUTO						2
+#define			ES_AND_GS_AUTO					3
+#define	VGT_ES_PER_GS					0x88CC
+#define	VGT_GS_PER_ES					0x88C8
+#define	VGT_GS_PER_VS					0x88E8
+#define	VGT_GS_VERTEX_REUSE				0x88D4
+#define	VGT_NUM_INSTANCES				0x8974
+#define	VGT_OUT_DEALLOC_CNTL				0x28C5C
+#define		DEALLOC_DIST_MASK				0x0000007F
+#define	VGT_STRMOUT_EN					0x28AB0
+#define	VGT_VERTEX_REUSE_BLOCK_CNTL			0x28C58
+#define		VTX_REUSE_DEPTH_MASK				0x000000FF
+
+#define VM_CONTEXT0_CNTL				0x1410
+#define		ENABLE_CONTEXT					(1 << 0)
+#define		PAGE_TABLE_DEPTH(x)				(((x) & 3) << 1)
+#define		RANGE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 4)
+#define	VM_CONTEXT0_PAGE_TABLE_BASE_ADDR		0x153C
+#define	VM_CONTEXT0_PAGE_TABLE_END_ADDR			0x157C
+#define	VM_CONTEXT0_PAGE_TABLE_START_ADDR		0x155C
+#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR	0x1518
+#define VM_L2_CNTL					0x1400
+#define		ENABLE_L2_CACHE					(1 << 0)
+#define		ENABLE_L2_FRAGMENT_PROCESSING			(1 << 1)
+#define		ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE		(1 << 9)
+#define		EFFECTIVE_L2_QUEUE_SIZE(x)			(((x) & 7) << 14)
+#define VM_L2_CNTL2					0x1404
+#define		INVALIDATE_ALL_L1_TLBS				(1 << 0)
+#define		INVALIDATE_L2_CACHE				(1 << 1)
+#define VM_L2_CNTL3					0x1408
+#define		BANK_SELECT(x)					((x) << 0)
+#define		CACHE_UPDATE_MODE(x)				((x) << 6)
+#define	VM_L2_STATUS					0x140C
+#define		L2_BUSY						(1 << 0)
+
+#define	WAIT_UNTIL					0x8040
+
+#endif
-- 
cgit v1.2.3


From 6fcefd56f5060ca99ab03c9f2ad1f17c3a543ca1 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 8 Sep 2009 11:08:32 +1000
Subject: drm/kms: fix kms helper license + Kconfig

Allow the KMS module to work properly, and also rename
it to KMS_HELPER so its clearer what its for.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/Kconfig         | 8 ++++----
 drivers/gpu/drm/Makefile        | 4 ++--
 drivers/gpu/drm/drm_fb_helper.c | 4 ++++
 drivers/gpu/drm/radeon/Kconfig  | 2 +-
 4 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 8c7309177c0..d42cf54f780 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -18,12 +18,13 @@ menuconfig DRM
 	  details.  You should also select and configure AGP
 	  (/dev/agpgart) support.
 
-config DRM_MODE_HELPER
+config DRM_KMS_HELPER
 	tristate
 	depends on DRM
 	select FB
+	select FRAMEBUFFER_CONSOLE if !EMBEDDED
 	help
-	  FB and CRTC helpers for kms drivers.
+	  FB and CRTC helpers for KMS drivers.
 
 config DRM_TTM
 	tristate
@@ -90,11 +91,10 @@ config DRM_I830
 config DRM_I915
 	tristate "i915 driver"
 	depends on AGP_INTEL
-	select DRM_MODE_HELPER
+	select DRM_KMS_HELPER
 	select FB_CFB_FILLRECT
 	select FB_CFB_COPYAREA
 	select FB_CFB_IMAGEBLIT
-	select FRAMEBUFFER_CONSOLE if !EMBEDDED
 	# i915 depends on ACPI_VIDEO when ACPI is enabled
 	# but for select to work, need to select ACPI_VIDEO's dependencies, ick
 	select VIDEO_OUTPUT_CONTROL if ACPI
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 7e96d74242f..3c8827a7aab 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -15,9 +15,9 @@ drm-y       :=	drm_auth.o drm_bufs.o drm_cache.o \
 
 drm-$(CONFIG_COMPAT) += drm_ioc32.o
 
-drm_helper-y := drm_fb_helper.o drm_crtc_helper.o
+drm_kms_helper-y := drm_fb_helper.o drm_crtc_helper.o
 
-obj-$(CONFIG_DRM_MODE_HELPER) += drm_helper.o
+obj-$(CONFIG_DRM_KMS_HELPER) += drm_kms_helper.o
 
 obj-$(CONFIG_DRM)	+= drm.o
 obj-$(CONFIG_DRM_TTM)	+= ttm/
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 41086e98059..8eee4a62037 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -34,6 +34,10 @@
 #include "drm_fb_helper.h"
 #include "drm_crtc_helper.h"
 
+MODULE_AUTHOR("David Airlie, Jesse Barnes");
+MODULE_DESCRIPTION("DRM KMS helper");
+MODULE_LICENSE("GPL and additional rights");
+
 static LIST_HEAD(kernel_fb_helper_list);
 
 bool drm_fb_helper_force_kernel_mode(void)
diff --git a/drivers/gpu/drm/radeon/Kconfig b/drivers/gpu/drm/radeon/Kconfig
index fdd9c894992..3cc89b27112 100644
--- a/drivers/gpu/drm/radeon/Kconfig
+++ b/drivers/gpu/drm/radeon/Kconfig
@@ -1,7 +1,7 @@
 config DRM_RADEON_KMS
 	bool "Enable modesetting on radeon by default"
 	depends on DRM_RADEON
-	select DRM_MODE_HELPER
+	select DRM_KMS_HELPER
 	select DRM_TTM
 	help
 	  Choose this option if you want kernel modesetting enabled by default,
-- 
cgit v1.2.3


From a0cdc6495bdd0ea12390b9edaf13c8cb653df109 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 8 Sep 2009 11:09:50 +1000
Subject: drm/kms/radeon: make kms default a runtime option

This makes the kms/enable disable a runtime not a build time
option.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/Kconfig             |  3 ++-
 drivers/gpu/drm/radeon/Kconfig      |  2 --
 drivers/gpu/drm/radeon/Makefile     |  7 ++++---
 drivers/gpu/drm/radeon/radeon_drv.c | 17 ++++++-----------
 4 files changed, 12 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index d42cf54f780..e4d971c8b9d 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -56,8 +56,9 @@ config DRM_RADEON
 	select FB_CFB_FILLRECT
 	select FB_CFB_COPYAREA
 	select FB_CFB_IMAGEBLIT
-	select FRAMEBUFFER_CONSOLE if !EMBEDDED
 	select FW_LOADER
+        select DRM_KMS_HELPER
+        select DRM_TTM
 	help
 	  Choose this option if you have an ATI Radeon graphics card.  There
 	  are both PCI and AGP versions.  You don't need to choose this to
diff --git a/drivers/gpu/drm/radeon/Kconfig b/drivers/gpu/drm/radeon/Kconfig
index 3cc89b27112..5982321be4d 100644
--- a/drivers/gpu/drm/radeon/Kconfig
+++ b/drivers/gpu/drm/radeon/Kconfig
@@ -1,8 +1,6 @@
 config DRM_RADEON_KMS
 	bool "Enable modesetting on radeon by default"
 	depends on DRM_RADEON
-	select DRM_KMS_HELPER
-	select DRM_TTM
 	help
 	  Choose this option if you want kernel modesetting enabled by default,
 	  and you have a new enough userspace to support this. Running old
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index 14c3fe69272..09a28923f46 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -3,8 +3,6 @@
 # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
 
 ccflags-y := -Iinclude/drm
-radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \
-	radeon_irq.o r300_cmdbuf.o r600_cp.o
 
 hostprogs-y := mkregtable
 
@@ -39,7 +37,10 @@ $(obj)/r300.o: $(obj)/r300_reg_safe.h
 
 $(obj)/rs600.o: $(obj)/rs600_reg_safe.h
 
-radeon-$(CONFIG_DRM_RADEON_KMS) += radeon_device.o radeon_kms.o \
+radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \
+	radeon_irq.o r300_cmdbuf.o r600_cp.o
+# add KMS driver
+radeon-y += radeon_device.o radeon_kms.o \
 	radeon_atombios.o radeon_agp.o atombios_crtc.o radeon_combios.o \
 	atom.o radeon_fence.o radeon_ttm.o radeon_object.o radeon_gart.o \
 	radeon_legacy_crtc.o radeon_legacy_encoders.o radeon_connectors.o \
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 133e975dbf0..29f040a7861 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -38,7 +38,6 @@
 #include <linux/console.h>
 
 
-#if defined(CONFIG_DRM_RADEON_KMS)
 /*
  * KMS wrapper.
  */
@@ -77,11 +76,9 @@ int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
 int radeon_debugfs_init(struct drm_minor *minor);
 void radeon_debugfs_cleanup(struct drm_minor *minor);
 #endif
-#endif
 
 
 int radeon_no_wb;
-#if defined(CONFIG_DRM_RADEON_KMS)
 int radeon_modeset = -1;
 int radeon_dynclks = -1;
 int radeon_r4xx_atom = 0;
@@ -92,12 +89,10 @@ int radeon_benchmarking = 0;
 int radeon_testing = 0;
 int radeon_connector_table = 0;
 int radeon_tv = 1;
-#endif
 
 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
 module_param_named(no_wb, radeon_no_wb, int, 0444);
 
-#if defined(CONFIG_DRM_RADEON_KMS)
 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
 module_param_named(modeset, radeon_modeset, int, 0400);
 
@@ -127,7 +122,6 @@ module_param_named(connector_table, radeon_connector_table, int, 0444);
 
 MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
 module_param_named(tv, radeon_tv, int, 0444);
-#endif
 
 static int radeon_suspend(struct drm_device *dev, pm_message_t state)
 {
@@ -219,7 +213,6 @@ static struct drm_driver driver_old = {
 	.patchlevel = DRIVER_PATCHLEVEL,
 };
 
-#if defined(CONFIG_DRM_RADEON_KMS)
 static struct drm_driver kms_driver;
 
 static int __devinit
@@ -313,7 +306,6 @@ static struct drm_driver kms_driver = {
 	.minor = KMS_DRIVER_MINOR,
 	.patchlevel = KMS_DRIVER_PATCHLEVEL,
 };
-#endif
 
 static struct drm_driver *driver;
 
@@ -321,7 +313,6 @@ static int __init radeon_init(void)
 {
 	driver = &driver_old;
 	driver->num_ioctls = radeon_max_ioctl;
-#if defined(CONFIG_DRM_RADEON_KMS)
 #ifdef CONFIG_VGA_CONSOLE
 	if (vgacon_text_force() && radeon_modeset == -1) {
 		DRM_INFO("VGACON disable radeon kernel modesetting.\n");
@@ -332,8 +323,13 @@ static int __init radeon_init(void)
 #endif
 	/* if enabled by default */
 	if (radeon_modeset == -1) {
-		DRM_INFO("radeon default to kernel modesetting.\n");
+#ifdef CONFIG_DRM_RADEON_KMS
+		DRM_INFO("radeon defaulting to kernel modesetting.\n");
 		radeon_modeset = 1;
+#else
+		DRM_INFO("radeon defaulting to userspace modesetting.\n");
+		radeon_modeset = 0;
+#endif
 	}
 	if (radeon_modeset == 1) {
 		DRM_INFO("radeon kernel modesetting enabled.\n");
@@ -343,7 +339,6 @@ static int __init radeon_init(void)
 	}
 	/* if the vga console setting is enabled still
 	 * let modprobe override it */
-#endif
 	return drm_init(driver);
 }
 
-- 
cgit v1.2.3


From f641e51e7469cc3a8115a3bd70b4526d566b1c60 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 8 Sep 2009 11:17:38 +1000
Subject: drm/radeon/kms: lower debugging on dpms events.

Lower the debugging on encoders when getting DPMS events.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/radeon_encoders.c | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 5c4ede7c990..8a353eab4f3 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -136,9 +136,9 @@ void radeon_encoder_set_active_device(struct drm_encoder *encoder)
 		if (connector->encoder == encoder) {
 			struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 			radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
-			DRM_INFO("setting active device to %08x from %08x %08x for encoder %d\n",
-				 radeon_encoder->active_device, radeon_encoder->devices,
-				 radeon_connector->devices, encoder->encoder_type);
+			DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
+				  radeon_encoder->active_device, radeon_encoder->devices,
+				  radeon_connector->devices, encoder->encoder_type);
 		}
 	}
 }
@@ -878,9 +878,9 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
 	else
 		devices = radeon_encoder->active_device;
 
-	DRM_INFO("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
-		 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
-		radeon_encoder->active_device);
+	DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
+		  radeon_encoder->encoder_id, mode, radeon_encoder->devices,
+		  radeon_encoder->active_device);
 	switch (radeon_encoder->encoder_id) {
 	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
@@ -1276,7 +1276,6 @@ static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
 {
 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
-	DRM_INFO("setting active device to 0 for encoder %d\n", encoder->encoder_type);
 	radeon_encoder->active_device = 0;
 }
 
-- 
cgit v1.2.3


From f1938cd6e900a85de64184e46d841efc9efd3484 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 8 Sep 2009 11:32:08 +1000
Subject: drm: include seq_file.h for debugfs builds.

Fixes a warning seen on powerpc.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 include/drm/drm_mm.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/drm/drm_mm.h b/include/drm/drm_mm.h
index bc5a87e8aee..62329f9a42c 100644
--- a/include/drm/drm_mm.h
+++ b/include/drm/drm_mm.h
@@ -37,6 +37,9 @@
  * Generic range manager structs
  */
 #include <linux/list.h>
+#ifdef CONFIG_DEBUG_FS
+#include <linux/seq_file.h>
+#endif
 
 struct drm_mm_node {
 	struct list_head fl_entry;
-- 
cgit v1.2.3


From ec2a4c3fdc8e82fe82a25d800e85c1ea06b74372 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 4 Aug 2009 11:43:41 +1000
Subject: drm/i915: get the bridge device once.

The driver gets the bridge device in a number of places, upcoming
vga arb code paths need the bridge device, however they need it in
under a lock, and the pci lookup can allocate memory. So clean
this code up before then and get the bridge once for the driver lifetime.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/i915/i915_dma.c        | 33 +++++++++++------
 drivers/gpu/drm/i915/i915_drv.h        |  1 +
 drivers/gpu/drm/i915/i915_gem_tiling.c | 65 +++++++++++-----------------------
 3 files changed, 44 insertions(+), 55 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 91ef4c15019..9909505d070 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -898,6 +898,18 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
 	return 0;
 }
 
+static int i915_get_bridge_dev(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
+	if (!dev_priv->bridge_dev) {
+		DRM_ERROR("bridge device not found\n");
+		return -1;
+	}
+	return 0;
+}
+
 /**
  * i915_probe_agp - get AGP bootup configuration
  * @pdev: PCI device
@@ -911,20 +923,13 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
 static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
 			  uint32_t *preallocated_size)
 {
-	struct pci_dev *bridge_dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	u16 tmp = 0;
 	unsigned long overhead;
 	unsigned long stolen;
 
-	bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
-	if (!bridge_dev) {
-		DRM_ERROR("bridge device not found\n");
-		return -1;
-	}
-
 	/* Get the fb aperture size and "stolen" memory amount. */
-	pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
-	pci_dev_put(bridge_dev);
+	pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
 
 	*aperture_size = 1024 * 1024;
 	*preallocated_size = 1024 * 1024;
@@ -1176,11 +1181,16 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	base = drm_get_resource_start(dev, mmio_bar);
 	size = drm_get_resource_len(dev, mmio_bar);
 
+	if (i915_get_bridge_dev(dev)) {
+		ret = -EIO;
+		goto free_priv;
+	}
+
 	dev_priv->regs = ioremap(base, size);
 	if (!dev_priv->regs) {
 		DRM_ERROR("failed to map registers\n");
 		ret = -EIO;
-		goto free_priv;
+		goto put_bridge;
 	}
 
         dev_priv->mm.gtt_mapping =
@@ -1292,6 +1302,8 @@ out_iomapfree:
 	io_mapping_free(dev_priv->mm.gtt_mapping);
 out_rmmap:
 	iounmap(dev_priv->regs);
+put_bridge:
+	pci_dev_put(dev_priv->bridge_dev);
 free_priv:
 	kfree(dev_priv);
 	return ret;
@@ -1335,6 +1347,7 @@ int i915_driver_unload(struct drm_device *dev)
 		i915_gem_lastclose(dev);
 	}
 
+	pci_dev_put(dev_priv->bridge_dev);
 	kfree(dev->dev_private);
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2d5bce643e6..77ed060b429 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -155,6 +155,7 @@ typedef struct drm_i915_private {
 
 	void __iomem *regs;
 
+	struct pci_dev *bridge_dev;
 	drm_i915_ring_buffer_t ring;
 
 	drm_dma_handle_t *status_page_dmah;
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index e774a4a1a50..200e398453c 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -94,23 +94,15 @@
 static int
 intel_alloc_mchbar_resource(struct drm_device *dev)
 {
-	struct pci_dev *bridge_dev;
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
 	u32 temp_lo, temp_hi = 0;
 	u64 mchbar_addr;
 	int ret = 0;
 
-	bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
-	if (!bridge_dev) {
-		DRM_DEBUG("no bridge dev?!\n");
-		ret = -ENODEV;
-		goto out;
-	}
-
 	if (IS_I965G(dev))
-		pci_read_config_dword(bridge_dev, reg + 4, &temp_hi);
-	pci_read_config_dword(bridge_dev, reg, &temp_lo);
+		pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
+	pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 	mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 
 	/* If ACPI doesn't have it, assume we need to allocate it ourselves */
@@ -118,30 +110,28 @@ intel_alloc_mchbar_resource(struct drm_device *dev)
 	if (mchbar_addr &&
 	    pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {
 		ret = 0;
-		goto out_put;
+		goto out;
 	}
 #endif
 
 	/* Get some space for it */
-	ret = pci_bus_alloc_resource(bridge_dev->bus, &dev_priv->mch_res,
+	ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res,
 				     MCHBAR_SIZE, MCHBAR_SIZE,
 				     PCIBIOS_MIN_MEM,
 				     0,   pcibios_align_resource,
-				     bridge_dev);
+				     dev_priv->bridge_dev);
 	if (ret) {
 		DRM_DEBUG("failed bus alloc: %d\n", ret);
 		dev_priv->mch_res.start = 0;
-		goto out_put;
+		goto out;
 	}
 
 	if (IS_I965G(dev))
-		pci_write_config_dword(bridge_dev, reg + 4,
+		pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 				       upper_32_bits(dev_priv->mch_res.start));
 
-	pci_write_config_dword(bridge_dev, reg,
+	pci_write_config_dword(dev_priv->bridge_dev, reg,
 			       lower_32_bits(dev_priv->mch_res.start));
-out_put:
-	pci_dev_put(bridge_dev);
 out:
 	return ret;
 }
@@ -150,44 +140,36 @@ out:
 static bool
 intel_setup_mchbar(struct drm_device *dev)
 {
-	struct pci_dev *bridge_dev;
+	drm_i915_private_t *dev_priv = dev->dev_private;
 	int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
 	u32 temp;
 	bool need_disable = false, enabled;
 
-	bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
-	if (!bridge_dev) {
-		DRM_DEBUG("no bridge dev?!\n");
-		goto out;
-	}
-
 	if (IS_I915G(dev) || IS_I915GM(dev)) {
-		pci_read_config_dword(bridge_dev, DEVEN_REG, &temp);
+		pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 		enabled = !!(temp & DEVEN_MCHBAR_EN);
 	} else {
-		pci_read_config_dword(bridge_dev, mchbar_reg, &temp);
+		pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 		enabled = temp & 1;
 	}
 
 	/* If it's already enabled, don't have to do anything */
 	if (enabled)
-		goto out_put;
+		goto out;
 
 	if (intel_alloc_mchbar_resource(dev))
-		goto out_put;
+		goto out;
 
 	need_disable = true;
 
 	/* Space is allocated or reserved, so enable it. */
 	if (IS_I915G(dev) || IS_I915GM(dev)) {
-		pci_write_config_dword(bridge_dev, DEVEN_REG,
+		pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 				       temp | DEVEN_MCHBAR_EN);
 	} else {
-		pci_read_config_dword(bridge_dev, mchbar_reg, &temp);
-		pci_write_config_dword(bridge_dev, mchbar_reg, temp | 1);
+		pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
+		pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 	}
-out_put:
-	pci_dev_put(bridge_dev);
 out:
 	return need_disable;
 }
@@ -196,25 +178,18 @@ static void
 intel_teardown_mchbar(struct drm_device *dev, bool disable)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
-	struct pci_dev *bridge_dev;
 	int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
 	u32 temp;
 
-	bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
-	if (!bridge_dev) {
-		DRM_DEBUG("no bridge dev?!\n");
-		return;
-	}
-
 	if (disable) {
 		if (IS_I915G(dev) || IS_I915GM(dev)) {
-			pci_read_config_dword(bridge_dev, DEVEN_REG, &temp);
+			pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 			temp &= ~DEVEN_MCHBAR_EN;
-			pci_write_config_dword(bridge_dev, DEVEN_REG, temp);
+			pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
 		} else {
-			pci_read_config_dword(bridge_dev, mchbar_reg, &temp);
+			pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 			temp &= ~1;
-			pci_write_config_dword(bridge_dev, mchbar_reg, temp);
+			pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
 		}
 	}
 
-- 
cgit v1.2.3


From 1ecff1eb0b83efa85be5b54c958e831e37f993f3 Mon Sep 17 00:00:00 2001
From: Adam Jackson <ajax@redhat.com>
Date: Tue, 8 Sep 2009 11:48:40 +1000
Subject: drm: shut the EDID warnings up.

These really aren't all that useful.

taken from Fedora kernel.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_edid.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index e2d5f515f7b..90d76bacff1 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1011,7 +1011,6 @@ int drm_do_probe_ddc_edid(struct i2c_adapter *adapter,
 	if (i2c_transfer(adapter, msgs, 2) == 2)
 		return 0;
 
-	dev_info(&adapter->dev, "unable to read EDID block.\n");
 	return -1;
 }
 EXPORT_SYMBOL(drm_do_probe_ddc_edid);
@@ -1024,8 +1023,6 @@ static int drm_ddc_read_edid(struct drm_connector *connector,
 
 	ret = drm_do_probe_ddc_edid(adapter, buf, len);
 	if (ret != 0) {
-		dev_info(&connector->dev->pdev->dev, "%s: no EDID data\n",
-			 drm_get_connector_name(connector));
 		goto end;
 	}
 	if (!edid_is_valid((struct edid *)buf)) {
-- 
cgit v1.2.3


From 620f37811dcc9e0f97ee79fbf8908fcc097deaee Mon Sep 17 00:00:00 2001
From: Adam Jackson <ajax@redhat.com>
Date: Tue, 8 Sep 2009 11:51:46 +1000
Subject: drm: prune modes when output is disconnected.

When an output was disconnected, its mode list would remain.  If you later
plugged into a sink with no EDID (projector, etc), you'd inherit the mode
list from the old sink, which is not what you want.

taken from Fedora kernel

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_crtc_helper.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index c9a50c72933..ff447f175a5 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -95,8 +95,7 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector,
 	if (connector->status == connector_status_disconnected) {
 		DRM_DEBUG_KMS("%s is disconnected\n",
 			  drm_get_connector_name(connector));
-		/* TODO set EDID to NULL */
-		return 0;
+		goto prune;
 	}
 
 	count = (*connector_funcs->get_modes)(connector);
@@ -124,6 +123,7 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector,
 								   mode);
 	}
 
+prune:
 	drm_mode_prune_invalid(dev, &connector->modes, true);
 
 	if (list_empty(&connector->modes))
-- 
cgit v1.2.3


From c746e205f2fb6f74b4a622382607f065eca5eb49 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Tue, 8 Sep 2009 14:38:45 +1000
Subject: drm/radeon/kms: don't allow ERESTART to hit userspace.

the pre-r600 fence code returns ebusy if we get hit by a signal
so we should continue to do that.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/radeon_fence.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index 506dd4dd3a2..01a89633e26 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -199,7 +199,7 @@ int r600_fence_wait(struct radeon_fence *fence,  bool intr, bool lazy)
 			schedule_timeout(1);
 
 		if (intr && signal_pending(current)) {
-			ret = -ERESTART;
+			ret = -ERESTARTSYS;
 			break;
 		}
 	}
@@ -225,8 +225,12 @@ int radeon_fence_wait(struct radeon_fence *fence, bool intr)
 		return 0;
 	}
 
-	if (rdev->family >= CHIP_R600)
-		return r600_fence_wait(fence, intr, 0);
+	if (rdev->family >= CHIP_R600) {
+		r = r600_fence_wait(fence, intr, 0);
+		if (r == -ERESTARTSYS)
+			return -EBUSY;
+		return r;
+	}
 
 retry:
 	cur_jiffies = jiffies;
-- 
cgit v1.2.3


From 60d15f551abdbc5fef70d85f55aac1e85950bf59 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Tue, 8 Sep 2009 14:22:45 -0400
Subject: drm/radeon/kms: re-apply 2007d633d639c896396e4c4b53b38068f3831307

Got accidently reverted by c93bb85b5cba3e3a06f2cad8e9bc5c23d3d10aac

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@linux.ie>
---
 drivers/gpu/drm/radeon/radeon_encoders.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 8a353eab4f3..9ad20350118 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -1400,8 +1400,14 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su
 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
-		drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
-		radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
+		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
+			radeon_encoder->rmx_type = RMX_FULL;
+			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
+			radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
+		} else {
+			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
+			radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
+		}
 		drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
 		break;
 	}
-- 
cgit v1.2.3


From cecc6b63a5de547a345c491bb4c18c01a15984a4 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Tue, 8 Sep 2009 14:45:05 -0400
Subject: drm/radeon/r600: use fence->timeout directly

Fixes fence timeouts on r6xx/r7xx.  Noticed by
taiu on IRC.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
---
 drivers/gpu/drm/radeon/radeon_fence.c | 11 +----------
 1 file changed, 1 insertion(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index 01a89633e26..3beb26d7471 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -171,17 +171,8 @@ bool radeon_fence_signaled(struct radeon_fence *fence)
 int r600_fence_wait(struct radeon_fence *fence,  bool intr, bool lazy)
 {
 	struct radeon_device *rdev;
-	unsigned long cur_jiffies;
-	unsigned long timeout;
 	int ret = 0;
 
-	cur_jiffies = jiffies;
-	timeout = HZ / 100;
-
-	if (time_after(fence->timeout, cur_jiffies)) {
-		timeout = fence->timeout - cur_jiffies;
-	}
-
 	rdev = fence->rdev;
 
 	__set_current_state(intr ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
@@ -190,7 +181,7 @@ int r600_fence_wait(struct radeon_fence *fence,  bool intr, bool lazy)
 		if (radeon_fence_signaled(fence))
 			break;
 
-		if (time_after_eq(jiffies, timeout)) {
+		if (time_after_eq(jiffies, fence->timeout)) {
 			ret = -EBUSY;
 			break;
 		}
-- 
cgit v1.2.3


From 5d93b135fc051be3740cbe55729fc7b86a7069d7 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Wed, 9 Sep 2009 16:09:36 -0400
Subject: drm/radeon/r600: fix legacy blit code

ARRAY_SIZE is number of elements not bytes.  Fix
ring counts accordingly, also make a few functions
static.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/r600_blit.c | 29 ++++++++++++-----------------
 1 file changed, 12 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r600_blit.c b/drivers/gpu/drm/radeon/r600_blit.c
index c51402e9249..dde2ccbf1d1 100644
--- a/drivers/gpu/drm/radeon/r600_blit.c
+++ b/drivers/gpu/drm/radeon/r600_blit.c
@@ -126,7 +126,7 @@ set_shaders(struct drm_device *dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	u64 gpu_addr;
-	int shader_size, i;
+	int i;
 	u32 *vs, *ps;
 	uint32_t sq_pgm_resources;
 	RING_LOCALS;
@@ -136,11 +136,9 @@ set_shaders(struct drm_device *dev)
 	vs = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset);
 	ps = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset + 256);
 
-	shader_size = r6xx_vs_size;
-	for (i = 0; i < shader_size; i++)
+	for (i = 0; i < r6xx_vs_size; i++)
 		vs[i] = r6xx_vs[i];
-	shader_size = r6xx_ps_size;
-	for (i = 0; i < shader_size; i++)
+	for (i = 0; i < r6xx_ps_size; i++)
 		ps[i] = r6xx_ps[i];
 
 	dev_priv->blit_vb->used = 512;
@@ -309,7 +307,7 @@ draw_auto(drm_radeon_private_t *dev_priv)
 static inline void
 set_default_state(drm_radeon_private_t *dev_priv)
 {
-	int default_state_dw, i;
+	int i;
 	u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
 	u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
 	int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
@@ -462,14 +460,12 @@ set_default_state(drm_radeon_private_t *dev_priv)
 				    R600_NUM_ES_STACK_ENTRIES(num_es_stack_entries));
 
 	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
-		default_state_dw = r7xx_default_size * 4;
-		BEGIN_RING(default_state_dw + 10);
-		for (i = 0; i < default_state_dw; i++)
+		BEGIN_RING(r7xx_default_size + 10);
+		for (i = 0; i < r7xx_default_size; i++)
 			OUT_RING(r7xx_default_state[i]);
 	} else {
-		default_state_dw = r6xx_default_size * 4;
-		BEGIN_RING(default_state_dw + 10);
-		for (i = 0; i < default_state_dw; i++)
+		BEGIN_RING(r6xx_default_size + 10);
+		for (i = 0; i < r6xx_default_size; i++)
 			OUT_RING(r6xx_default_state[i]);
 	}
 	OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
@@ -512,7 +508,7 @@ static inline uint32_t i2f(uint32_t input)
 }
 
 
-int r600_nomm_get_vb(struct drm_device *dev)
+static inline int r600_nomm_get_vb(struct drm_device *dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	dev_priv->blit_vb = radeon_freelist_get(dev);
@@ -523,7 +519,7 @@ int r600_nomm_get_vb(struct drm_device *dev)
 	return 0;
 }
 
-void r600_nomm_put_vb(struct drm_device *dev)
+static inline void r600_nomm_put_vb(struct drm_device *dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 
@@ -531,7 +527,7 @@ void r600_nomm_put_vb(struct drm_device *dev)
 	radeon_cp_discard_buffer(dev, dev_priv->blit_vb->file_priv->master, dev_priv->blit_vb);
 }
 
-void *r600_nomm_get_vb_ptr(struct drm_device *dev)
+static inline void *r600_nomm_get_vb_ptr(struct drm_device *dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	return (((char *)dev->agp_buffer_map->handle +
@@ -781,8 +777,7 @@ r600_blit_swap(struct drm_device *dev,
 	u64 vb_addr;
 	u32 *vb;
 
-	vb = (u32 *) ((char *)dev->agp_buffer_map->handle +
-		      dev_priv->blit_vb->offset + dev_priv->blit_vb->used);
+	vb = r600_nomm_get_vb_ptr(dev);
 
 	if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
 
-- 
cgit v1.2.3


From 45600232b3dbb97817c9e15de848c742901893e1 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Wed, 9 Sep 2009 22:23:45 +0200
Subject: drm/radeon/kms: wait for cp idle before stopping it.

If we stop CP and that it's still processing thing GPU hang might
happen, this patch wait for CP idle (the wait can timeout) so we
can avoid shutting down CP at bad time. This is especialy usefull
when reseting the GPU as it seems GPU reset fails to properly reset
CP when the CP wasn't stop after being idle.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/r100.c  | 18 +++++++++++++
 drivers/gpu/drm/radeon/r100d.h | 60 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 78 insertions(+)

diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 5708c07ce73..938a6936d92 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -487,6 +487,21 @@ int r100_copy_blit(struct radeon_device *rdev,
 /*
  * CP
  */
+static int r100_cp_wait_for_idle(struct radeon_device *rdev)
+{
+	unsigned i;
+	u32 tmp;
+
+	for (i = 0; i < rdev->usec_timeout; i++) {
+		tmp = RREG32(R_000E40_RBBM_STATUS);
+		if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
+			return 0;
+		}
+		udelay(1);
+	}
+	return -1;
+}
+
 void r100_ring_start(struct radeon_device *rdev)
 {
 	int r;
@@ -715,6 +730,9 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
 
 void r100_cp_fini(struct radeon_device *rdev)
 {
+	if (r100_cp_wait_for_idle(rdev)) {
+		DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
+	}
 	/* Disable ring */
 	rdev->cp.ready = false;
 	WREG32(RADEON_CP_CSQ_CNTL, 0);
diff --git a/drivers/gpu/drm/radeon/r100d.h b/drivers/gpu/drm/radeon/r100d.h
index 6da7d92c321..1d951ab77dc 100644
--- a/drivers/gpu/drm/radeon/r100d.h
+++ b/drivers/gpu/drm/radeon/r100d.h
@@ -73,4 +73,64 @@
 #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
 
+/* Registers */
+#define R_000E40_RBBM_STATUS                         0x000E40
+#define   S_000E40_CMDFIFO_AVAIL(x)                    (((x) & 0x7F) << 0)
+#define   G_000E40_CMDFIFO_AVAIL(x)                    (((x) >> 0) & 0x7F)
+#define   C_000E40_CMDFIFO_AVAIL                       0xFFFFFF80
+#define   S_000E40_HIRQ_ON_RBB(x)                      (((x) & 0x1) << 8)
+#define   G_000E40_HIRQ_ON_RBB(x)                      (((x) >> 8) & 0x1)
+#define   C_000E40_HIRQ_ON_RBB                         0xFFFFFEFF
+#define   S_000E40_CPRQ_ON_RBB(x)                      (((x) & 0x1) << 9)
+#define   G_000E40_CPRQ_ON_RBB(x)                      (((x) >> 9) & 0x1)
+#define   C_000E40_CPRQ_ON_RBB                         0xFFFFFDFF
+#define   S_000E40_CFRQ_ON_RBB(x)                      (((x) & 0x1) << 10)
+#define   G_000E40_CFRQ_ON_RBB(x)                      (((x) >> 10) & 0x1)
+#define   C_000E40_CFRQ_ON_RBB                         0xFFFFFBFF
+#define   S_000E40_HIRQ_IN_RTBUF(x)                    (((x) & 0x1) << 11)
+#define   G_000E40_HIRQ_IN_RTBUF(x)                    (((x) >> 11) & 0x1)
+#define   C_000E40_HIRQ_IN_RTBUF                       0xFFFFF7FF
+#define   S_000E40_CPRQ_IN_RTBUF(x)                    (((x) & 0x1) << 12)
+#define   G_000E40_CPRQ_IN_RTBUF(x)                    (((x) >> 12) & 0x1)
+#define   C_000E40_CPRQ_IN_RTBUF                       0xFFFFEFFF
+#define   S_000E40_CFRQ_IN_RTBUF(x)                    (((x) & 0x1) << 13)
+#define   G_000E40_CFRQ_IN_RTBUF(x)                    (((x) >> 13) & 0x1)
+#define   C_000E40_CFRQ_IN_RTBUF                       0xFFFFDFFF
+#define   S_000E40_CF_PIPE_BUSY(x)                     (((x) & 0x1) << 14)
+#define   G_000E40_CF_PIPE_BUSY(x)                     (((x) >> 14) & 0x1)
+#define   C_000E40_CF_PIPE_BUSY                        0xFFFFBFFF
+#define   S_000E40_ENG_EV_BUSY(x)                      (((x) & 0x1) << 15)
+#define   G_000E40_ENG_EV_BUSY(x)                      (((x) >> 15) & 0x1)
+#define   C_000E40_ENG_EV_BUSY                         0xFFFF7FFF
+#define   S_000E40_CP_CMDSTRM_BUSY(x)                  (((x) & 0x1) << 16)
+#define   G_000E40_CP_CMDSTRM_BUSY(x)                  (((x) >> 16) & 0x1)
+#define   C_000E40_CP_CMDSTRM_BUSY                     0xFFFEFFFF
+#define   S_000E40_E2_BUSY(x)                          (((x) & 0x1) << 17)
+#define   G_000E40_E2_BUSY(x)                          (((x) >> 17) & 0x1)
+#define   C_000E40_E2_BUSY                             0xFFFDFFFF
+#define   S_000E40_RB2D_BUSY(x)                        (((x) & 0x1) << 18)
+#define   G_000E40_RB2D_BUSY(x)                        (((x) >> 18) & 0x1)
+#define   C_000E40_RB2D_BUSY                           0xFFFBFFFF
+#define   S_000E40_RB3D_BUSY(x)                        (((x) & 0x1) << 19)
+#define   G_000E40_RB3D_BUSY(x)                        (((x) >> 19) & 0x1)
+#define   C_000E40_RB3D_BUSY                           0xFFF7FFFF
+#define   S_000E40_SE_BUSY(x)                          (((x) & 0x1) << 20)
+#define   G_000E40_SE_BUSY(x)                          (((x) >> 20) & 0x1)
+#define   C_000E40_SE_BUSY                             0xFFEFFFFF
+#define   S_000E40_RE_BUSY(x)                          (((x) & 0x1) << 21)
+#define   G_000E40_RE_BUSY(x)                          (((x) >> 21) & 0x1)
+#define   C_000E40_RE_BUSY                             0xFFDFFFFF
+#define   S_000E40_TAM_BUSY(x)                         (((x) & 0x1) << 22)
+#define   G_000E40_TAM_BUSY(x)                         (((x) >> 22) & 0x1)
+#define   C_000E40_TAM_BUSY                            0xFFBFFFFF
+#define   S_000E40_TDM_BUSY(x)                         (((x) & 0x1) << 23)
+#define   G_000E40_TDM_BUSY(x)                         (((x) >> 23) & 0x1)
+#define   C_000E40_TDM_BUSY                            0xFF7FFFFF
+#define   S_000E40_PB_BUSY(x)                          (((x) & 0x1) << 24)
+#define   G_000E40_PB_BUSY(x)                          (((x) >> 24) & 0x1)
+#define   C_000E40_PB_BUSY                             0xFEFFFFFF
+#define   S_000E40_GUI_ACTIVE(x)                       (((x) & 0x1) << 31)
+#define   G_000E40_GUI_ACTIVE(x)                       (((x) >> 31) & 0x1)
+#define   C_000E40_GUI_ACTIVE                          0x7FFFFFFF
+
 #endif
-- 
cgit v1.2.3


From a18d7ea15356679f58c2fafe2957786c5f7f9201 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Wed, 9 Sep 2009 22:23:27 +0200
Subject: drm/radeon/kms: call r100_cp_disable rather than duplicating code.

r100_cp_fini was duplicating code of r100_cp_disable, call r100_cp_disable
instead.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/r100.c   | 3 +--
 drivers/gpu/drm/radeon/radeon.h | 3 +++
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 938a6936d92..4e1c55162cc 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -734,8 +734,7 @@ void r100_cp_fini(struct radeon_device *rdev)
 		DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
 	}
 	/* Disable ring */
-	rdev->cp.ready = false;
-	WREG32(RADEON_CP_CSQ_CNTL, 0);
+	r100_cp_disable(rdev);
 	radeon_ring_fini(rdev);
 	DRM_INFO("radeon: cp finalized\n");
 }
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 3299733ac30..24574bc0f2a 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -933,4 +933,7 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
 
+/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
+void r100_cp_disable(struct radeon_device *rdev);
+
 #endif
-- 
cgit v1.2.3


From 905b68223be18937159a29b354e6a332952ff952 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Wed, 9 Sep 2009 22:24:20 +0200
Subject: drm/radeon/kms: add R4XX mc register access helper.

Atombios will use the mc register access helper and R4XX hw have a
bigger mc range than R3XX so add R4XX specific mc register access
helper.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/r420.c          | 17 ++++++++++++++
 drivers/gpu/drm/radeon/r420d.h         | 43 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/radeon/radeon.h        |  4 ++++
 drivers/gpu/drm/radeon/radeon_device.c |  4 ++++
 4 files changed, 68 insertions(+)
 create mode 100644 drivers/gpu/drm/radeon/r420d.h

diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 97426a6f370..96303f064db 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -29,6 +29,7 @@
 #include "drmP.h"
 #include "radeon_reg.h"
 #include "radeon.h"
+#include "r420d.h"
 
 /* r420,r423,rv410 depends on : */
 void r100_pci_gart_disable(struct radeon_device *rdev);
@@ -232,3 +233,19 @@ int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
 	return 0;
 #endif
 }
+
+u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
+{
+	u32 r;
+
+	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
+	r = RREG32(R_0001FC_MC_IND_DATA);
+	return r;
+}
+
+void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
+{
+	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
+		S_0001F8_MC_IND_WR_EN(1));
+	WREG32(R_0001FC_MC_IND_DATA, v);
+}
diff --git a/drivers/gpu/drm/radeon/r420d.h b/drivers/gpu/drm/radeon/r420d.h
new file mode 100644
index 00000000000..8b946c1883b
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r420d.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#ifndef R420D_H
+#define R420D_H
+
+#define R_0001F8_MC_IND_INDEX                        0x0001F8
+#define   S_0001F8_MC_IND_ADDR(x)                      (((x) & 0x7F) << 0)
+#define   G_0001F8_MC_IND_ADDR(x)                      (((x) >> 0) & 0x7F)
+#define   C_0001F8_MC_IND_ADDR                         0xFFFFFF80
+#define   S_0001F8_MC_IND_WR_EN(x)                     (((x) & 0x1) << 8)
+#define   G_0001F8_MC_IND_WR_EN(x)                     (((x) >> 8) & 0x1)
+#define   C_0001F8_MC_IND_WR_EN                        0xFFFFFEFF
+#define R_0001FC_MC_IND_DATA                         0x0001FC
+#define   S_0001FC_MC_IND_DATA(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_0001FC_MC_IND_DATA(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0001FC_MC_IND_DATA                         0x00000000
+
+#endif
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 24574bc0f2a..fa84c77577a 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -936,4 +936,8 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
 void r100_cp_disable(struct radeon_device *rdev);
 
+/* r420,r423,rv410 */
+u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
+void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
+
 #endif
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index f2469c51178..05e1af0156c 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -266,6 +266,10 @@ void radeon_register_accessor_init(struct radeon_device *rdev)
 		rdev->pll_rreg = &r100_pll_rreg;
 		rdev->pll_wreg = &r100_pll_wreg;
 	}
+	if (rdev->family >= CHIP_R420) {
+		rdev->mc_rreg = &r420_mc_rreg;
+		rdev->mc_wreg = &r420_mc_wreg;
+	}
 	if (rdev->family >= CHIP_RV515) {
 		rdev->mc_rreg = &rv515_mc_rreg;
 		rdev->mc_wreg = &rv515_mc_wreg;
-- 
cgit v1.2.3


From a513c184d99fe10e7b20771ef86f5f807769318f Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Wed, 9 Sep 2009 22:23:07 +0200
Subject: drm/radeon/kms: Don't try to process irq when we are unloading

If module is being unloaded we should not try to handle irq especialy
we should not call into drm helper or we could hard hang the computer
free_irq will call the irq handler to make sure we behave properly.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/r100.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 4e1c55162cc..4dd5ca50c0c 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -319,6 +319,9 @@ int r100_irq_process(struct radeon_device *rdev)
 	if (!status) {
 		return IRQ_NONE;
 	}
+	if (rdev->shutdown) {
+		return IRQ_NONE;
+	}
 	while (status) {
 		/* SW interrupt */
 		if (status & RADEON_SW_INT_TEST) {
-- 
cgit v1.2.3


From 119e20dc149581db3064661b2e659f308f97b663 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Thu, 10 Sep 2009 02:53:50 -0400
Subject: drm/radeon/kms/r600: fix blit support

select the correct max number of bytes per blit based
on whether the size is multiple of 4 bytes.  This
determines whether we can use 8 or 32 bit pixels for
the blit.

airlied: also merged the IB padding patch +
correcting the VS offset for context

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/r600_blit_kms.c | 39 +++++++++++++++++++++++++++-------
 1 file changed, 31 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index 5755647e688..bbb0d615ac1 100644
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -129,6 +129,7 @@ set_shaders(struct radeon_device *rdev)
 	radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
 	radeon_ring_write(rdev, 0);
 
+	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
 	cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
 }
 
@@ -248,6 +249,7 @@ set_default_state(struct radeon_device *rdev)
 	int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
 	int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
 	u64 gpu_addr;
+	int dwords;
 
 	switch (rdev->family) {
 	case CHIP_R600:
@@ -394,11 +396,12 @@ set_default_state(struct radeon_device *rdev)
 				    NUM_ES_STACK_ENTRIES(num_es_stack_entries));
 
 	/* emit an IB pointing at default state */
+	dwords = (rdev->r600_blit.state_len + 0xf) & ~0xf;
 	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
 	radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
 	radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC);
 	radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
-	radeon_ring_write(rdev, (rdev->r600_blit.state_len / 4));
+	radeon_ring_write(rdev, dwords);
 
 	radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
 	radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
@@ -441,17 +444,25 @@ static inline uint32_t i2f(uint32_t input)
 int r600_blit_init(struct radeon_device *rdev)
 {
 	u32 obj_size;
-	int r;
+	int r, dwords;
 	void *ptr;
+	u32 packet2s[16];
+	int num_packet2s = 0;
 
 	rdev->r600_blit.state_offset = 0;
 
 	if (rdev->family >= CHIP_RV770)
-		rdev->r600_blit.state_len = r7xx_default_size * 4;
+		rdev->r600_blit.state_len = r7xx_default_size;
 	else
-		rdev->r600_blit.state_len = r6xx_default_size * 4;
+		rdev->r600_blit.state_len = r6xx_default_size;
+
+	dwords = rdev->r600_blit.state_len;
+	while (dwords & 0xf) {
+		packet2s[num_packet2s++] = PACKET2(0);
+		dwords++;
+	}
 
-	obj_size = rdev->r600_blit.state_len;
+	obj_size = dwords * 4;
 	obj_size = ALIGN(obj_size, 256);
 
 	rdev->r600_blit.vs_offset = obj_size;
@@ -488,9 +499,15 @@ int r600_blit_init(struct radeon_device *rdev)
 	}
 
 	if (rdev->family >= CHIP_RV770)
-		memcpy_toio(ptr + rdev->r600_blit.state_offset, r7xx_default_state, rdev->r600_blit.state_len);
+		memcpy_toio(ptr + rdev->r600_blit.state_offset,
+			    r7xx_default_state, rdev->r600_blit.state_len * 4);
 	else
-		memcpy_toio(ptr + rdev->r600_blit.state_offset, r6xx_default_state, rdev->r600_blit.state_len);
+		memcpy_toio(ptr + rdev->r600_blit.state_offset,
+			    r6xx_default_state, rdev->r600_blit.state_len * 4);
+	if (num_packet2s)
+		memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
+			    packet2s, num_packet2s * 4);
+
 
 	memcpy(ptr + rdev->r600_blit.vs_offset, r6xx_vs, r6xx_vs_size * 4);
 	memcpy(ptr + rdev->r600_blit.ps_offset, r6xx_ps, r6xx_ps_size * 4);
@@ -532,7 +549,13 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
 {
 	int r;
 	int ring_size;
-	const int max_size = 8192*8192;
+	int max_size;
+
+	/* 8 bpp vs 32 bpp for xfer unit */
+	if (size_bytes & 3)
+		max_size = 8192*8192;
+	else
+		max_size = 8192*8192*4;
 
 	r = r600_vb_ib_get(rdev);
 	WARN_ON(r);
-- 
cgit v1.2.3


From c000273ebc830c27b8c9e03d5f4c147d3e310f48 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Thu, 10 Sep 2009 13:47:09 +0200
Subject: drm/radeon/kms: R3XX/R4XX AGP asic use PCI GART not PCIE GART

R3XX/R4XX AGP asic use the old PCI GART block, not the new PCIE GART.
Make sure we pick the right GART when disabling AGP.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Acked-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/r300.c          | 6 ++++++
 drivers/gpu/drm/radeon/r420.c          | 9 +++++++--
 drivers/gpu/drm/radeon/radeon.h        | 4 ++++
 drivers/gpu/drm/radeon/radeon_device.c | 2 +-
 4 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index a5f82f7beed..9c17b786982 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -181,6 +181,12 @@ int r300_gart_enable(struct radeon_device *rdev)
 		rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
 		return rv370_pcie_gart_enable(rdev);
 	}
+	if (rdev->flags & RADEON_IS_PCI) {
+		rdev->asic->gart_disable = &r100_pci_gart_disable;
+		rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
+		rdev->asic->gart_set_page = &r100_pci_gart_set_page;
+		return r100_pci_gart_enable(rdev);
+	}
 	return r100_pci_gart_enable(rdev);
 }
 
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 96303f064db..551d6996d3f 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -101,8 +101,13 @@ int r420_mc_init(struct radeon_device *rdev)
 
 void r420_mc_fini(struct radeon_device *rdev)
 {
-	rv370_pcie_gart_disable(rdev);
-	radeon_gart_table_vram_free(rdev);
+	if (rdev->flags & RADEON_IS_PCIE) {
+		rv370_pcie_gart_disable(rdev);
+		radeon_gart_table_vram_free(rdev);
+	} else {
+		r100_pci_gart_disable(rdev);
+		radeon_gart_table_ram_free(rdev);
+	}
 	radeon_gart_fini(rdev);
 }
 
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index fa84c77577a..d6ff4e01206 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -935,6 +935,10 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
 
 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
 void r100_cp_disable(struct radeon_device *rdev);
+void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
+int r100_pci_gart_enable(struct radeon_device *rdev);
+void r100_pci_gart_disable(struct radeon_device *rdev);
+int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 
 /* r420,r423,rv410 */
 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 05e1af0156c..bf6939497e1 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -503,7 +503,7 @@ int radeon_device_init(struct radeon_device *rdev,
 
 	if (radeon_agpmode == -1) {
 		rdev->flags &= ~RADEON_IS_AGP;
-		if (rdev->family > CHIP_RV515 ||
+		if (rdev->family >= CHIP_RV515 ||
 		    rdev->family == CHIP_RV380 ||
 		    rdev->family == CHIP_RV410 ||
 		    rdev->family == CHIP_R423) {
-- 
cgit v1.2.3


From a381287759b2b65e7de9fb35801c781cab016f10 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Thu, 10 Sep 2009 15:54:35 -0400
Subject: drm/radeon/kms/r600: use blit for BO moves

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/radeon_asic.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index e87bb915a6d..f9c8f9a041d 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -553,7 +553,7 @@ static struct radeon_asic r600_asic = {
 	.cs_parse = &r600_cs_parse,
 	.copy_blit = &r600_copy_blit,
 	.copy_dma = &r600_copy_blit,
-	.copy = NULL,
+	.copy = &r600_copy_blit,
 	.set_engine_clock = &radeon_atom_set_engine_clock,
 	.set_memory_clock = &radeon_atom_set_memory_clock,
 	.set_pcie_lanes = NULL,
@@ -602,7 +602,7 @@ static struct radeon_asic rv770_asic = {
 	.cs_parse = &r600_cs_parse,
 	.copy_blit = &r600_copy_blit,
 	.copy_dma = &r600_copy_blit,
-	.copy = NULL,
+	.copy = &r600_copy_blit,
 	.set_engine_clock = &radeon_atom_set_engine_clock,
 	.set_memory_clock = &radeon_atom_set_memory_clock,
 	.set_pcie_lanes = NULL,
-- 
cgit v1.2.3


From 705af9c7a8bcb9c8752a73be9ca356acb5c7688c Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Thu, 10 Sep 2009 16:31:13 -0400
Subject: drm/radeon/kms: pull in latest quirks and fixes from ddx

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/radeon_atombios.c | 47 ++++++++++++++++++++++----------
 drivers/gpu/drm/radeon/radeon_encoders.c |  2 +-
 2 files changed, 33 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index a8fb392c9cd..4dff85b450e 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -104,7 +104,7 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
 				     uint32_t supported_device,
 				     int *connector_type,
 				     struct radeon_i2c_bus_rec *i2c_bus,
-				     uint8_t *line_mux)
+				     uint16_t *line_mux)
 {
 
 	/* Asus M2A-VM HDMI board lists the DVI port as HDMI */
@@ -143,23 +143,34 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
 			return false;
 	}
 
-	/* some BIOSes seem to report DAC on HDMI - they hurt me with their lies */
-	if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) ||
-	    (*connector_type == DRM_MODE_CONNECTOR_HDMIB)) {
-		if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
-			return false;
-		}
-	}
-
 	/* ASUS HD 3600 XT board lists the DVI port as HDMI */
 	if ((dev->pdev->device == 0x9598) &&
 	    (dev->pdev->subsystem_vendor == 0x1043) &&
 	    (dev->pdev->subsystem_device == 0x01da)) {
-		if (*connector_type == DRM_MODE_CONNECTOR_HDMIB) {
+		if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
+			*connector_type = DRM_MODE_CONNECTOR_DVID;
+		}
+	}
+
+	/* ASUS HD 3450 board lists the DVI port as HDMI */
+	if ((dev->pdev->device == 0x95C5) &&
+	    (dev->pdev->subsystem_vendor == 0x1043) &&
+	    (dev->pdev->subsystem_device == 0x01e2)) {
+		if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 			*connector_type = DRM_MODE_CONNECTOR_DVID;
 		}
 	}
 
+	/* some BIOSes seem to report DAC on HDMI - usually this is a board with
+	 * HDMI + VGA reporting as HDMI
+	 */
+	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
+		if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
+			*connector_type = DRM_MODE_CONNECTOR_VGA;
+			*line_mux = 0;
+		}
+	}
+
 	return true;
 }
 
@@ -192,11 +203,11 @@ const int object_connector_convert[] = {
 	DRM_MODE_CONNECTOR_Composite,
 	DRM_MODE_CONNECTOR_SVIDEO,
 	DRM_MODE_CONNECTOR_Unknown,
+	DRM_MODE_CONNECTOR_Unknown,
 	DRM_MODE_CONNECTOR_9PinDIN,
 	DRM_MODE_CONNECTOR_Unknown,
 	DRM_MODE_CONNECTOR_HDMIA,
 	DRM_MODE_CONNECTOR_HDMIB,
-	DRM_MODE_CONNECTOR_HDMIB,
 	DRM_MODE_CONNECTOR_LVDS,
 	DRM_MODE_CONNECTOR_9PinDIN,
 	DRM_MODE_CONNECTOR_Unknown,
@@ -218,7 +229,7 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 	ATOM_OBJECT_HEADER *obj_header;
 	int i, j, path_size, device_support;
 	int connector_type;
-	uint16_t igp_lane_info;
+	uint16_t igp_lane_info, conn_id;
 	bool linkb;
 	struct radeon_i2c_bus_rec ddc_bus;
 
@@ -405,9 +416,15 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 			else
 				ddc_bus = radeon_lookup_gpio(dev, line_mux);
 
+			conn_id = le16_to_cpu(path->usConnObjectId);
+
+			if (!radeon_atom_apply_quirks
+			    (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
+			     &ddc_bus, &conn_id))
+				continue;
+
 			radeon_add_atom_connector(dev,
-						  le16_to_cpu(path->
-							      usConnObjectId),
+						  conn_id,
 						  le16_to_cpu(path->
 							      usDeviceTag),
 						  connector_type, &ddc_bus,
@@ -423,7 +440,7 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 
 struct bios_connector {
 	bool valid;
-	uint8_t line_mux;
+	uint16_t line_mux;
 	uint16_t devices;
 	int connector_type;
 	struct radeon_i2c_bus_rec ddc_bus;
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 9ad20350118..e274bb13866 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -537,6 +537,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
 
 	switch (connector->connector_type) {
 	case DRM_MODE_CONNECTOR_DVII:
+	case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 		if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
 			return ATOM_ENCODER_MODE_HDMI;
 		else if (radeon_connector->use_digital)
@@ -546,7 +547,6 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
 		break;
 	case DRM_MODE_CONNECTOR_DVID:
 	case DRM_MODE_CONNECTOR_HDMIA:
-	case DRM_MODE_CONNECTOR_HDMIB:
 	default:
 		if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
 			return ATOM_ENCODER_MODE_HDMI;
-- 
cgit v1.2.3


From 923f6848e1686059ef8d272d1fca4d3577911a41 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Thu, 10 Sep 2009 17:53:39 -0400
Subject: drm/radeon/kms: add common scaled modes for TV and LVDS

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/radeon_connectors.c | 73 ++++++++++++++++++++++++++----
 1 file changed, 64 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 6a2b0296adf..c44871c80ab 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -28,6 +28,7 @@
 #include "drm_crtc_helper.h"
 #include "radeon_drm.h"
 #include "radeon.h"
+#include "atom.h"
 
 extern void
 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
@@ -174,6 +175,50 @@ static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encode
 	return mode;
 }
 
+static void radeon_add_common_modes(struct drm_encoder *encoder, struct drm_connector *connector)
+{
+	struct drm_device *dev = encoder->dev;
+	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+	struct drm_display_mode *mode = NULL;
+	struct radeon_native_mode *native_mode = &radeon_encoder->native_mode;
+	int i;
+	struct mode_size {
+		int w;
+		int h;
+	} common_modes[17] = {
+		{ 640,  480},
+		{ 720,  480},
+		{ 800,  600},
+		{ 848,  480},
+		{1024,  768},
+		{1152,  768},
+		{1280,  720},
+		{1280,  800},
+		{1280,  854},
+		{1280,  960},
+		{1280, 1024},
+		{1440,  900},
+		{1400, 1050},
+		{1680, 1050},
+		{1600, 1200},
+		{1920, 1080},
+		{1920, 1200}
+	};
+
+	for (i = 0; i < 17; i++) {
+		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
+			if (common_modes[i].w >= native_mode->panel_xres &&
+			    common_modes[i].h >= native_mode->panel_yres)
+				continue;
+		}
+		if (common_modes[i].w < 320 || common_modes[i].h < 200)
+			continue;
+
+		mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false);
+		drm_mode_probed_add(connector, mode);
+	}
+}
+
 int radeon_connector_set_property(struct drm_connector *connector, struct drm_property *property,
 				  uint64_t val)
 {
@@ -205,6 +250,10 @@ static int radeon_lvds_get_modes(struct drm_connector *connector)
 		ret = 1;
 		drm_mode_probed_add(connector, mode);
 	}
+
+	/* add scaled modes */
+	radeon_add_common_modes(encoder, connector);
+
 	return ret;
 }
 
@@ -306,21 +355,27 @@ struct drm_connector_funcs radeon_vga_connector_funcs = {
 	.set_property = radeon_connector_set_property,
 };
 
-static struct drm_display_mode tv_fixed_mode = {
-	DRM_MODE("800x600", DRM_MODE_TYPE_DEFAULT, 38250, 800, 832,
-		 912, 1024, 0, 600, 603, 607, 624, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC),
-};
-
 static int radeon_tv_get_modes(struct drm_connector *connector)
 {
 	struct drm_device *dev = connector->dev;
+	struct radeon_device *rdev = dev->dev_private;
 	struct drm_display_mode *tv_mode;
+	struct drm_encoder *encoder;
 
-	tv_mode = drm_mode_duplicate(dev, &tv_fixed_mode);
-	tv_mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
-
-	drm_mode_probed_add(connector, tv_mode);
+	encoder = radeon_best_single_encoder(connector);
+	if (!encoder)
+		return 0;
 
+	/* avivo chips can scale any mode */
+	if (rdev->family >= CHIP_RS600)
+		/* add scaled modes */
+		radeon_add_common_modes(encoder, connector);
+	else {
+		/* only 800x600 is supported right now on pre-avivo chips */
+		tv_mode = drm_cvt_mode(dev, 800, 600, 60, false, false);
+		tv_mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+		drm_mode_probed_add(connector, tv_mode);
+	}
 	return 1;
 }
 
-- 
cgit v1.2.3


From 6cf8a3f58806f12b975a89cfd7edf01566ff80a0 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Thu, 10 Sep 2009 21:46:48 +0200
Subject: drm/radeon/kms: move modeset init outside of GPU init

We are splitting GPU & modeset init so that it's easier
to abord only remaining GPU init when somethings fails.
We want to always provide enough funcionalities to get
fbcon and a shadowfb X working. Only acceptable error
during initialization are memory allocation failure or
io mapping failure.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/radeon.h        |  4 ++++
 drivers/gpu/drm/radeon/radeon_device.c | 20 +++-----------------
 drivers/gpu/drm/radeon/radeon_kms.c    | 22 ++++++++++++++++++----
 3 files changed, 25 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index d6ff4e01206..23ede0e4783 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -933,6 +933,10 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
 
+/* Common functions */
+int radeon_modeset_init(struct radeon_device *rdev);
+void radeon_modeset_fini(struct radeon_device *rdev);
+
 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
 void r100_cp_disable(struct radeon_device *rdev);
 void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index bf6939497e1..72f6262ea73 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -469,9 +469,6 @@ void radeon_combios_fini(struct radeon_device *rdev)
 {
 }
 
-int radeon_modeset_init(struct radeon_device *rdev);
-void radeon_modeset_fini(struct radeon_device *rdev);
-
 
 /*
  * Radeon device.
@@ -481,7 +478,7 @@ int radeon_device_init(struct radeon_device *rdev,
 		       struct pci_dev *pdev,
 		       uint32_t flags)
 {
-	int r, ret = 0;
+	int r;
 	int dma_bits;
 
 	DRM_INFO("radeon: Initializing kernel modesetting.\n");
@@ -660,33 +657,22 @@ int radeon_device_init(struct radeon_device *rdev,
 				return r;
 			}
 		}
-		ret = r;
-	}
-	r = radeon_modeset_init(rdev);
-	if (r) {
-		return r;
-	}
-	if (!ret) {
-		DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
 	}
+	DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
 	if (radeon_testing) {
 		radeon_test_moves(rdev);
 	}
 	if (radeon_benchmarking) {
 		radeon_benchmark(rdev);
 	}
-	return ret;
+	return 0;
 }
 
 void radeon_device_fini(struct radeon_device *rdev)
 {
-	if (rdev == NULL || rdev->rmmio == NULL) {
-		return;
-	}
 	DRM_INFO("radeon: finishing device.\n");
 	rdev->shutdown = true;
 	/* Order matter so becarefull if you rearrange anythings */
-	radeon_modeset_fini(rdev);
 	if (!rdev->new_init_path) {
 		radeon_ib_pool_fini(rdev);
 		radeon_cp_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index dce09ada32b..ac8505fe2ca 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -54,12 +54,23 @@ int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
 		flags |= RADEON_IS_PCI;
 	}
 
+	/* radeon_device_init should report only fatal error
+	 * like memory allocation failure or iomapping failure,
+	 * or memory manager initialization failure, it must
+	 * properly initialize the GPU MC controller and permit
+	 * VRAM allocation
+	 */
 	r = radeon_device_init(rdev, dev, dev->pdev, flags);
 	if (r) {
-		DRM_ERROR("Failed to initialize radeon, disabling IOCTL\n");
-		radeon_device_fini(rdev);
-		kfree(rdev);
-		dev->dev_private = NULL;
+		DRM_ERROR("Fatal error while trying to initialize radeon.\n");
+		return r;
+	}
+	/* Again modeset_init should fail only on fatal error
+	 * otherwise it should provide enough functionalities
+	 * for shadowfb to run
+	 */
+	r = radeon_modeset_init(rdev);
+	if (r) {
 		return r;
 	}
 	return 0;
@@ -69,6 +80,9 @@ int radeon_driver_unload_kms(struct drm_device *dev)
 {
 	struct radeon_device *rdev = dev->dev_private;
 
+	if (rdev == NULL)
+		return 0;
+	radeon_modeset_fini(rdev);
 	radeon_device_fini(rdev);
 	kfree(rdev);
 	dev->dev_private = NULL;
-- 
cgit v1.2.3


From 2f9a60d76692ffbc749d97ac55717f70eb1f9432 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Fri, 11 Sep 2009 18:35:38 +1000
Subject: drm/radeon/kms: set fbdev_info for suspend/resume

this hopefully will bring back suspend/resume under kms.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/radeon_fb.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index ebb58959f41..19e244a512b 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -258,6 +258,7 @@ int radeonfb_create(struct drm_device *dev,
 		goto out_unref;
 	}
 
+	rdev->fbdev_info = info;
 	rfbdev = info->par;
 	rfbdev->helper.funcs = &radeon_fb_helper_funcs;
 	rfbdev->helper.dev = dev;
-- 
cgit v1.2.3


From 7747b713049e63aa64bcac679535ddfff92b312d Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Fri, 11 Sep 2009 11:15:43 -0400
Subject: drm/radeon/kms: add common lvds modes in the ddc case

previous patch only handled the non-ddc case.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@linux.ie>
---
 drivers/gpu/drm/radeon/radeon_connectors.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index c44871c80ab..04ecb11ebb8 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -236,6 +236,10 @@ static int radeon_lvds_get_modes(struct drm_connector *connector)
 	if (radeon_connector->ddc_bus) {
 		ret = radeon_ddc_get_modes(radeon_connector);
 		if (ret > 0) {
+			encoder = radeon_best_single_encoder(connector);
+			if (encoder)
+				/* add scaled modes */
+				radeon_add_common_modes(encoder, connector);
 			return ret;
 		}
 	}
@@ -249,11 +253,10 @@ static int radeon_lvds_get_modes(struct drm_connector *connector)
 	if (mode) {
 		ret = 1;
 		drm_mode_probed_add(connector, mode);
+		/* add scaled modes */
+		radeon_add_common_modes(encoder, connector);
 	}
 
-	/* add scaled modes */
-	radeon_add_common_modes(encoder, connector);
-
 	return ret;
 }
 
-- 
cgit v1.2.3


From 1be340563cf40210487afe332c0d7c9a523dba5f Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Fri, 11 Sep 2009 12:02:03 -0400
Subject: drm/radeon/kms/r600: fix blit dword count for non r6xx

rv6xx emits two extra dwords in the render target setup.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@linux.ie>
---
 drivers/gpu/drm/radeon/r600_blit_kms.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index bbb0d615ac1..1ebfd5a6dfe 100644
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -550,6 +550,12 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
 	int r;
 	int ring_size;
 	int max_size;
+	/* loops of emits 64 + fence emit possible */
+	int dwords_per_loop = 76;
+
+	/* set_render_target emits 2 extra dwords on rv6xx */
+	if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
+		dwords_per_loop += 2;
 
 	/* 8 bpp vs 32 bpp for xfer unit */
 	if (size_bytes & 3)
@@ -560,8 +566,7 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
 	r = r600_vb_ib_get(rdev);
 	WARN_ON(r);
 
-	/* loops of emits 64 + fence emit possible */
-	ring_size = ((size_bytes + max_size) / max_size) * 78;
+	ring_size = ((size_bytes + max_size) / max_size) * dwords_per_loop;
 	/* set default  + shaders */
 	ring_size += 40; /* shaders + def state */
 	ring_size += 3; /* fence emit for VB IB */
-- 
cgit v1.2.3


From d42571efe33552cd519b7f3800a788b5f2d51798 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Fri, 11 Sep 2009 15:27:14 -0400
Subject: drm/radeon/kms: fix typo in quirks

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@linux.ie>
---
 drivers/gpu/drm/radeon/radeon_atombios.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 4dff85b450e..aa756dec895 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -148,7 +148,7 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
 	    (dev->pdev->subsystem_vendor == 0x1043) &&
 	    (dev->pdev->subsystem_device == 0x01da)) {
 		if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
-			*connector_type = DRM_MODE_CONNECTOR_DVID;
+			*connector_type = DRM_MODE_CONNECTOR_DVII;
 		}
 	}
 
@@ -157,7 +157,7 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
 	    (dev->pdev->subsystem_vendor == 0x1043) &&
 	    (dev->pdev->subsystem_device == 0x01e2)) {
 		if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
-			*connector_type = DRM_MODE_CONNECTOR_DVID;
+			*connector_type = DRM_MODE_CONNECTOR_DVII;
 		}
 	}
 
-- 
cgit v1.2.3


From 9f022ddfb23793b475ff7e57ac08a766dd5d31bd Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Fri, 11 Sep 2009 15:35:22 +0200
Subject: drm/radeon/kms: convert r4xx to new init path

This convert r4xx to new init path it also fix few bugs.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/r100.c          | 114 +++++++-
 drivers/gpu/drm/radeon/r100d.h         | 471 +++++++++++++++++++++++++++++++++
 drivers/gpu/drm/radeon/r300.c          |  50 +++-
 drivers/gpu/drm/radeon/r300d.h         |  25 ++
 drivers/gpu/drm/radeon/r420.c          | 293 +++++++++++++-------
 drivers/gpu/drm/radeon/r420d.h         | 206 ++++++++++++++
 drivers/gpu/drm/radeon/radeon.h        |  32 ++-
 drivers/gpu/drm/radeon/radeon_asic.h   |  33 +--
 drivers/gpu/drm/radeon/radeon_device.c |  19 +-
 drivers/gpu/drm/radeon/radeon_ring.c   |   2 +
 10 files changed, 1121 insertions(+), 124 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 4dd5ca50c0c..47263d3ede9 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -299,6 +299,17 @@ int r100_irq_set(struct radeon_device *rdev)
 	return 0;
 }
 
+void r100_irq_disable(struct radeon_device *rdev)
+{
+	u32 tmp;
+
+	WREG32(R_000040_GEN_INT_CNTL, 0);
+	/* Wait and acknowledge irq */
+	mdelay(1);
+	tmp = RREG32(R_000044_GEN_INT_STATUS);
+	WREG32(R_000044_GEN_INT_STATUS, tmp);
+}
+
 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
 {
 	uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
@@ -396,14 +407,21 @@ int r100_wb_init(struct radeon_device *rdev)
 			return r;
 		}
 	}
-	WREG32(RADEON_SCRATCH_ADDR, rdev->wb.gpu_addr);
-	WREG32(RADEON_CP_RB_RPTR_ADDR, rdev->wb.gpu_addr + 1024);
-	WREG32(RADEON_SCRATCH_UMSK, 0xff);
+	WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
+	WREG32(R_00070C_CP_RB_RPTR_ADDR,
+		S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
+	WREG32(R_000770_SCRATCH_UMSK, 0xff);
 	return 0;
 }
 
+void r100_wb_disable(struct radeon_device *rdev)
+{
+	WREG32(R_000770_SCRATCH_UMSK, 0);
+}
+
 void r100_wb_fini(struct radeon_device *rdev)
 {
+	r100_wb_disable(rdev);
 	if (rdev->wb.wb_obj) {
 		radeon_object_kunmap(rdev->wb.wb_obj);
 		radeon_object_unpin(rdev->wb.wb_obj);
@@ -1581,11 +1599,12 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
 int r100_cs_parse(struct radeon_cs_parser *p)
 {
 	struct radeon_cs_packet pkt;
-	struct r100_cs_track track;
+	struct r100_cs_track *track;
 	int r;
 
-	r100_cs_track_clear(p->rdev, &track);
-	p->track = &track;
+	track = kzalloc(sizeof(*track), GFP_KERNEL);
+	r100_cs_track_clear(p->rdev, track);
+	p->track = track;
 	do {
 		r = r100_cs_packet_parse(p, &pkt, p->idx);
 		if (r) {
@@ -3085,3 +3104,86 @@ int r100_ib_test(struct radeon_device *rdev)
 	radeon_ib_free(rdev, &ib);
 	return r;
 }
+
+void r100_ib_fini(struct radeon_device *rdev)
+{
+	radeon_ib_pool_fini(rdev);
+}
+
+int r100_ib_init(struct radeon_device *rdev)
+{
+	int r;
+
+	r = radeon_ib_pool_init(rdev);
+	if (r) {
+		dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
+		r100_ib_fini(rdev);
+		return r;
+	}
+	r = r100_ib_test(rdev);
+	if (r) {
+		dev_err(rdev->dev, "failled testing IB (%d).\n", r);
+		r100_ib_fini(rdev);
+		return r;
+	}
+	return 0;
+}
+
+void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
+{
+	/* Shutdown CP we shouldn't need to do that but better be safe than
+	 * sorry
+	 */
+	rdev->cp.ready = false;
+	WREG32(R_000740_CP_CSQ_CNTL, 0);
+
+	/* Save few CRTC registers */
+	save->GENMO_WT = RREG32(R_0003C0_GENMO_WT);
+	save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
+	save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
+	save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
+	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
+		save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
+		save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
+	}
+
+	/* Disable VGA aperture access */
+	WREG32(R_0003C0_GENMO_WT, C_0003C0_VGA_RAM_EN & save->GENMO_WT);
+	/* Disable cursor, overlay, crtc */
+	WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
+	WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
+					S_000054_CRTC_DISPLAY_DIS(1));
+	WREG32(R_000050_CRTC_GEN_CNTL,
+			(C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
+			S_000050_CRTC_DISP_REQ_EN_B(1));
+	WREG32(R_000420_OV0_SCALE_CNTL,
+		C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
+	WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
+	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
+		WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
+						S_000360_CUR2_LOCK(1));
+		WREG32(R_0003F8_CRTC2_GEN_CNTL,
+			(C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
+			S_0003F8_CRTC2_DISPLAY_DIS(1) |
+			S_0003F8_CRTC2_DISP_REQ_EN_B(1));
+		WREG32(R_000360_CUR2_OFFSET,
+			C_000360_CUR2_LOCK & save->CUR2_OFFSET);
+	}
+}
+
+void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
+{
+	/* Update base address for crtc */
+	WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location);
+	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
+		WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR,
+				rdev->mc.vram_location);
+	}
+	/* Restore CRTC registers */
+	WREG32(R_0003C0_GENMO_WT, save->GENMO_WT);
+	WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
+	WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
+	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
+		WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
+	}
+}
diff --git a/drivers/gpu/drm/radeon/r100d.h b/drivers/gpu/drm/radeon/r100d.h
index 1d951ab77dc..c4b257ec920 100644
--- a/drivers/gpu/drm/radeon/r100d.h
+++ b/drivers/gpu/drm/radeon/r100d.h
@@ -74,6 +74,477 @@
 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
 
 /* Registers */
+#define R_000040_GEN_INT_CNTL                        0x000040
+#define   S_000040_CRTC_VBLANK(x)                      (((x) & 0x1) << 0)
+#define   G_000040_CRTC_VBLANK(x)                      (((x) >> 0) & 0x1)
+#define   C_000040_CRTC_VBLANK                         0xFFFFFFFE
+#define   S_000040_CRTC_VLINE(x)                       (((x) & 0x1) << 1)
+#define   G_000040_CRTC_VLINE(x)                       (((x) >> 1) & 0x1)
+#define   C_000040_CRTC_VLINE                          0xFFFFFFFD
+#define   S_000040_CRTC_VSYNC(x)                       (((x) & 0x1) << 2)
+#define   G_000040_CRTC_VSYNC(x)                       (((x) >> 2) & 0x1)
+#define   C_000040_CRTC_VSYNC                          0xFFFFFFFB
+#define   S_000040_SNAPSHOT(x)                         (((x) & 0x1) << 3)
+#define   G_000040_SNAPSHOT(x)                         (((x) >> 3) & 0x1)
+#define   C_000040_SNAPSHOT                            0xFFFFFFF7
+#define   S_000040_FP_DETECT(x)                        (((x) & 0x1) << 4)
+#define   G_000040_FP_DETECT(x)                        (((x) >> 4) & 0x1)
+#define   C_000040_FP_DETECT                           0xFFFFFFEF
+#define   S_000040_CRTC2_VLINE(x)                      (((x) & 0x1) << 5)
+#define   G_000040_CRTC2_VLINE(x)                      (((x) >> 5) & 0x1)
+#define   C_000040_CRTC2_VLINE                         0xFFFFFFDF
+#define   S_000040_DMA_VIPH0_INT_EN(x)                 (((x) & 0x1) << 12)
+#define   G_000040_DMA_VIPH0_INT_EN(x)                 (((x) >> 12) & 0x1)
+#define   C_000040_DMA_VIPH0_INT_EN                    0xFFFFEFFF
+#define   S_000040_CRTC2_VSYNC(x)                      (((x) & 0x1) << 6)
+#define   G_000040_CRTC2_VSYNC(x)                      (((x) >> 6) & 0x1)
+#define   C_000040_CRTC2_VSYNC                         0xFFFFFFBF
+#define   S_000040_SNAPSHOT2(x)                        (((x) & 0x1) << 7)
+#define   G_000040_SNAPSHOT2(x)                        (((x) >> 7) & 0x1)
+#define   C_000040_SNAPSHOT2                           0xFFFFFF7F
+#define   S_000040_CRTC2_VBLANK(x)                     (((x) & 0x1) << 9)
+#define   G_000040_CRTC2_VBLANK(x)                     (((x) >> 9) & 0x1)
+#define   C_000040_CRTC2_VBLANK                        0xFFFFFDFF
+#define   S_000040_FP2_DETECT(x)                       (((x) & 0x1) << 10)
+#define   G_000040_FP2_DETECT(x)                       (((x) >> 10) & 0x1)
+#define   C_000040_FP2_DETECT                          0xFFFFFBFF
+#define   S_000040_VSYNC_DIFF_OVER_LIMIT(x)            (((x) & 0x1) << 11)
+#define   G_000040_VSYNC_DIFF_OVER_LIMIT(x)            (((x) >> 11) & 0x1)
+#define   C_000040_VSYNC_DIFF_OVER_LIMIT               0xFFFFF7FF
+#define   S_000040_DMA_VIPH1_INT_EN(x)                 (((x) & 0x1) << 13)
+#define   G_000040_DMA_VIPH1_INT_EN(x)                 (((x) >> 13) & 0x1)
+#define   C_000040_DMA_VIPH1_INT_EN                    0xFFFFDFFF
+#define   S_000040_DMA_VIPH2_INT_EN(x)                 (((x) & 0x1) << 14)
+#define   G_000040_DMA_VIPH2_INT_EN(x)                 (((x) >> 14) & 0x1)
+#define   C_000040_DMA_VIPH2_INT_EN                    0xFFFFBFFF
+#define   S_000040_DMA_VIPH3_INT_EN(x)                 (((x) & 0x1) << 15)
+#define   G_000040_DMA_VIPH3_INT_EN(x)                 (((x) >> 15) & 0x1)
+#define   C_000040_DMA_VIPH3_INT_EN                    0xFFFF7FFF
+#define   S_000040_I2C_INT_EN(x)                       (((x) & 0x1) << 17)
+#define   G_000040_I2C_INT_EN(x)                       (((x) >> 17) & 0x1)
+#define   C_000040_I2C_INT_EN                          0xFFFDFFFF
+#define   S_000040_GUI_IDLE(x)                         (((x) & 0x1) << 19)
+#define   G_000040_GUI_IDLE(x)                         (((x) >> 19) & 0x1)
+#define   C_000040_GUI_IDLE                            0xFFF7FFFF
+#define   S_000040_VIPH_INT_EN(x)                      (((x) & 0x1) << 24)
+#define   G_000040_VIPH_INT_EN(x)                      (((x) >> 24) & 0x1)
+#define   C_000040_VIPH_INT_EN                         0xFEFFFFFF
+#define   S_000040_SW_INT_EN(x)                        (((x) & 0x1) << 25)
+#define   G_000040_SW_INT_EN(x)                        (((x) >> 25) & 0x1)
+#define   C_000040_SW_INT_EN                           0xFDFFFFFF
+#define   S_000040_GEYSERVILLE(x)                      (((x) & 0x1) << 27)
+#define   G_000040_GEYSERVILLE(x)                      (((x) >> 27) & 0x1)
+#define   C_000040_GEYSERVILLE                         0xF7FFFFFF
+#define   S_000040_HDCP_AUTHORIZED_INT(x)              (((x) & 0x1) << 28)
+#define   G_000040_HDCP_AUTHORIZED_INT(x)              (((x) >> 28) & 0x1)
+#define   C_000040_HDCP_AUTHORIZED_INT                 0xEFFFFFFF
+#define   S_000040_DVI_I2C_INT(x)                      (((x) & 0x1) << 29)
+#define   G_000040_DVI_I2C_INT(x)                      (((x) >> 29) & 0x1)
+#define   C_000040_DVI_I2C_INT                         0xDFFFFFFF
+#define   S_000040_GUIDMA(x)                           (((x) & 0x1) << 30)
+#define   G_000040_GUIDMA(x)                           (((x) >> 30) & 0x1)
+#define   C_000040_GUIDMA                              0xBFFFFFFF
+#define   S_000040_VIDDMA(x)                           (((x) & 0x1) << 31)
+#define   G_000040_VIDDMA(x)                           (((x) >> 31) & 0x1)
+#define   C_000040_VIDDMA                              0x7FFFFFFF
+#define R_000044_GEN_INT_STATUS                      0x000044
+#define   S_000044_CRTC_VBLANK_STAT(x)                 (((x) & 0x1) << 0)
+#define   G_000044_CRTC_VBLANK_STAT(x)                 (((x) >> 0) & 0x1)
+#define   C_000044_CRTC_VBLANK_STAT                    0xFFFFFFFE
+#define   S_000044_CRTC_VBLANK_STAT_AK(x)              (((x) & 0x1) << 0)
+#define   G_000044_CRTC_VBLANK_STAT_AK(x)              (((x) >> 0) & 0x1)
+#define   C_000044_CRTC_VBLANK_STAT_AK                 0xFFFFFFFE
+#define   S_000044_CRTC_VLINE_STAT(x)                  (((x) & 0x1) << 1)
+#define   G_000044_CRTC_VLINE_STAT(x)                  (((x) >> 1) & 0x1)
+#define   C_000044_CRTC_VLINE_STAT                     0xFFFFFFFD
+#define   S_000044_CRTC_VLINE_STAT_AK(x)               (((x) & 0x1) << 1)
+#define   G_000044_CRTC_VLINE_STAT_AK(x)               (((x) >> 1) & 0x1)
+#define   C_000044_CRTC_VLINE_STAT_AK                  0xFFFFFFFD
+#define   S_000044_CRTC_VSYNC_STAT(x)                  (((x) & 0x1) << 2)
+#define   G_000044_CRTC_VSYNC_STAT(x)                  (((x) >> 2) & 0x1)
+#define   C_000044_CRTC_VSYNC_STAT                     0xFFFFFFFB
+#define   S_000044_CRTC_VSYNC_STAT_AK(x)               (((x) & 0x1) << 2)
+#define   G_000044_CRTC_VSYNC_STAT_AK(x)               (((x) >> 2) & 0x1)
+#define   C_000044_CRTC_VSYNC_STAT_AK                  0xFFFFFFFB
+#define   S_000044_SNAPSHOT_STAT(x)                    (((x) & 0x1) << 3)
+#define   G_000044_SNAPSHOT_STAT(x)                    (((x) >> 3) & 0x1)
+#define   C_000044_SNAPSHOT_STAT                       0xFFFFFFF7
+#define   S_000044_SNAPSHOT_STAT_AK(x)                 (((x) & 0x1) << 3)
+#define   G_000044_SNAPSHOT_STAT_AK(x)                 (((x) >> 3) & 0x1)
+#define   C_000044_SNAPSHOT_STAT_AK                    0xFFFFFFF7
+#define   S_000044_FP_DETECT_STAT(x)                   (((x) & 0x1) << 4)
+#define   G_000044_FP_DETECT_STAT(x)                   (((x) >> 4) & 0x1)
+#define   C_000044_FP_DETECT_STAT                      0xFFFFFFEF
+#define   S_000044_FP_DETECT_STAT_AK(x)                (((x) & 0x1) << 4)
+#define   G_000044_FP_DETECT_STAT_AK(x)                (((x) >> 4) & 0x1)
+#define   C_000044_FP_DETECT_STAT_AK                   0xFFFFFFEF
+#define   S_000044_CRTC2_VLINE_STAT(x)                 (((x) & 0x1) << 5)
+#define   G_000044_CRTC2_VLINE_STAT(x)                 (((x) >> 5) & 0x1)
+#define   C_000044_CRTC2_VLINE_STAT                    0xFFFFFFDF
+#define   S_000044_CRTC2_VLINE_STAT_AK(x)              (((x) & 0x1) << 5)
+#define   G_000044_CRTC2_VLINE_STAT_AK(x)              (((x) >> 5) & 0x1)
+#define   C_000044_CRTC2_VLINE_STAT_AK                 0xFFFFFFDF
+#define   S_000044_CRTC2_VSYNC_STAT(x)                 (((x) & 0x1) << 6)
+#define   G_000044_CRTC2_VSYNC_STAT(x)                 (((x) >> 6) & 0x1)
+#define   C_000044_CRTC2_VSYNC_STAT                    0xFFFFFFBF
+#define   S_000044_CRTC2_VSYNC_STAT_AK(x)              (((x) & 0x1) << 6)
+#define   G_000044_CRTC2_VSYNC_STAT_AK(x)              (((x) >> 6) & 0x1)
+#define   C_000044_CRTC2_VSYNC_STAT_AK                 0xFFFFFFBF
+#define   S_000044_SNAPSHOT2_STAT(x)                   (((x) & 0x1) << 7)
+#define   G_000044_SNAPSHOT2_STAT(x)                   (((x) >> 7) & 0x1)
+#define   C_000044_SNAPSHOT2_STAT                      0xFFFFFF7F
+#define   S_000044_SNAPSHOT2_STAT_AK(x)                (((x) & 0x1) << 7)
+#define   G_000044_SNAPSHOT2_STAT_AK(x)                (((x) >> 7) & 0x1)
+#define   C_000044_SNAPSHOT2_STAT_AK                   0xFFFFFF7F
+#define   S_000044_CAP0_INT_ACTIVE(x)                  (((x) & 0x1) << 8)
+#define   G_000044_CAP0_INT_ACTIVE(x)                  (((x) >> 8) & 0x1)
+#define   C_000044_CAP0_INT_ACTIVE                     0xFFFFFEFF
+#define   S_000044_CRTC2_VBLANK_STAT(x)                (((x) & 0x1) << 9)
+#define   G_000044_CRTC2_VBLANK_STAT(x)                (((x) >> 9) & 0x1)
+#define   C_000044_CRTC2_VBLANK_STAT                   0xFFFFFDFF
+#define   S_000044_CRTC2_VBLANK_STAT_AK(x)             (((x) & 0x1) << 9)
+#define   G_000044_CRTC2_VBLANK_STAT_AK(x)             (((x) >> 9) & 0x1)
+#define   C_000044_CRTC2_VBLANK_STAT_AK                0xFFFFFDFF
+#define   S_000044_FP2_DETECT_STAT(x)                  (((x) & 0x1) << 10)
+#define   G_000044_FP2_DETECT_STAT(x)                  (((x) >> 10) & 0x1)
+#define   C_000044_FP2_DETECT_STAT                     0xFFFFFBFF
+#define   S_000044_FP2_DETECT_STAT_AK(x)               (((x) & 0x1) << 10)
+#define   G_000044_FP2_DETECT_STAT_AK(x)               (((x) >> 10) & 0x1)
+#define   C_000044_FP2_DETECT_STAT_AK                  0xFFFFFBFF
+#define   S_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x)       (((x) & 0x1) << 11)
+#define   G_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x)       (((x) >> 11) & 0x1)
+#define   C_000044_VSYNC_DIFF_OVER_LIMIT_STAT          0xFFFFF7FF
+#define   S_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x)    (((x) & 0x1) << 11)
+#define   G_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x)    (((x) >> 11) & 0x1)
+#define   C_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK       0xFFFFF7FF
+#define   S_000044_DMA_VIPH0_INT(x)                    (((x) & 0x1) << 12)
+#define   G_000044_DMA_VIPH0_INT(x)                    (((x) >> 12) & 0x1)
+#define   C_000044_DMA_VIPH0_INT                       0xFFFFEFFF
+#define   S_000044_DMA_VIPH0_INT_AK(x)                 (((x) & 0x1) << 12)
+#define   G_000044_DMA_VIPH0_INT_AK(x)                 (((x) >> 12) & 0x1)
+#define   C_000044_DMA_VIPH0_INT_AK                    0xFFFFEFFF
+#define   S_000044_DMA_VIPH1_INT(x)                    (((x) & 0x1) << 13)
+#define   G_000044_DMA_VIPH1_INT(x)                    (((x) >> 13) & 0x1)
+#define   C_000044_DMA_VIPH1_INT                       0xFFFFDFFF
+#define   S_000044_DMA_VIPH1_INT_AK(x)                 (((x) & 0x1) << 13)
+#define   G_000044_DMA_VIPH1_INT_AK(x)                 (((x) >> 13) & 0x1)
+#define   C_000044_DMA_VIPH1_INT_AK                    0xFFFFDFFF
+#define   S_000044_DMA_VIPH2_INT(x)                    (((x) & 0x1) << 14)
+#define   G_000044_DMA_VIPH2_INT(x)                    (((x) >> 14) & 0x1)
+#define   C_000044_DMA_VIPH2_INT                       0xFFFFBFFF
+#define   S_000044_DMA_VIPH2_INT_AK(x)                 (((x) & 0x1) << 14)
+#define   G_000044_DMA_VIPH2_INT_AK(x)                 (((x) >> 14) & 0x1)
+#define   C_000044_DMA_VIPH2_INT_AK                    0xFFFFBFFF
+#define   S_000044_DMA_VIPH3_INT(x)                    (((x) & 0x1) << 15)
+#define   G_000044_DMA_VIPH3_INT(x)                    (((x) >> 15) & 0x1)
+#define   C_000044_DMA_VIPH3_INT                       0xFFFF7FFF
+#define   S_000044_DMA_VIPH3_INT_AK(x)                 (((x) & 0x1) << 15)
+#define   G_000044_DMA_VIPH3_INT_AK(x)                 (((x) >> 15) & 0x1)
+#define   C_000044_DMA_VIPH3_INT_AK                    0xFFFF7FFF
+#define   S_000044_I2C_INT(x)                          (((x) & 0x1) << 17)
+#define   G_000044_I2C_INT(x)                          (((x) >> 17) & 0x1)
+#define   C_000044_I2C_INT                             0xFFFDFFFF
+#define   S_000044_I2C_INT_AK(x)                       (((x) & 0x1) << 17)
+#define   G_000044_I2C_INT_AK(x)                       (((x) >> 17) & 0x1)
+#define   C_000044_I2C_INT_AK                          0xFFFDFFFF
+#define   S_000044_GUI_IDLE_STAT(x)                    (((x) & 0x1) << 19)
+#define   G_000044_GUI_IDLE_STAT(x)                    (((x) >> 19) & 0x1)
+#define   C_000044_GUI_IDLE_STAT                       0xFFF7FFFF
+#define   S_000044_GUI_IDLE_STAT_AK(x)                 (((x) & 0x1) << 19)
+#define   G_000044_GUI_IDLE_STAT_AK(x)                 (((x) >> 19) & 0x1)
+#define   C_000044_GUI_IDLE_STAT_AK                    0xFFF7FFFF
+#define   S_000044_VIPH_INT(x)                         (((x) & 0x1) << 24)
+#define   G_000044_VIPH_INT(x)                         (((x) >> 24) & 0x1)
+#define   C_000044_VIPH_INT                            0xFEFFFFFF
+#define   S_000044_SW_INT(x)                           (((x) & 0x1) << 25)
+#define   G_000044_SW_INT(x)                           (((x) >> 25) & 0x1)
+#define   C_000044_SW_INT                              0xFDFFFFFF
+#define   S_000044_SW_INT_AK(x)                        (((x) & 0x1) << 25)
+#define   G_000044_SW_INT_AK(x)                        (((x) >> 25) & 0x1)
+#define   C_000044_SW_INT_AK                           0xFDFFFFFF
+#define   S_000044_SW_INT_SET(x)                       (((x) & 0x1) << 26)
+#define   G_000044_SW_INT_SET(x)                       (((x) >> 26) & 0x1)
+#define   C_000044_SW_INT_SET                          0xFBFFFFFF
+#define   S_000044_GEYSERVILLE_STAT(x)                 (((x) & 0x1) << 27)
+#define   G_000044_GEYSERVILLE_STAT(x)                 (((x) >> 27) & 0x1)
+#define   C_000044_GEYSERVILLE_STAT                    0xF7FFFFFF
+#define   S_000044_GEYSERVILLE_STAT_AK(x)              (((x) & 0x1) << 27)
+#define   G_000044_GEYSERVILLE_STAT_AK(x)              (((x) >> 27) & 0x1)
+#define   C_000044_GEYSERVILLE_STAT_AK                 0xF7FFFFFF
+#define   S_000044_HDCP_AUTHORIZED_INT_STAT(x)         (((x) & 0x1) << 28)
+#define   G_000044_HDCP_AUTHORIZED_INT_STAT(x)         (((x) >> 28) & 0x1)
+#define   C_000044_HDCP_AUTHORIZED_INT_STAT            0xEFFFFFFF
+#define   S_000044_HDCP_AUTHORIZED_INT_AK(x)           (((x) & 0x1) << 28)
+#define   G_000044_HDCP_AUTHORIZED_INT_AK(x)           (((x) >> 28) & 0x1)
+#define   C_000044_HDCP_AUTHORIZED_INT_AK              0xEFFFFFFF
+#define   S_000044_DVI_I2C_INT_STAT(x)                 (((x) & 0x1) << 29)
+#define   G_000044_DVI_I2C_INT_STAT(x)                 (((x) >> 29) & 0x1)
+#define   C_000044_DVI_I2C_INT_STAT                    0xDFFFFFFF
+#define   S_000044_DVI_I2C_INT_AK(x)                   (((x) & 0x1) << 29)
+#define   G_000044_DVI_I2C_INT_AK(x)                   (((x) >> 29) & 0x1)
+#define   C_000044_DVI_I2C_INT_AK                      0xDFFFFFFF
+#define   S_000044_GUIDMA_STAT(x)                      (((x) & 0x1) << 30)
+#define   G_000044_GUIDMA_STAT(x)                      (((x) >> 30) & 0x1)
+#define   C_000044_GUIDMA_STAT                         0xBFFFFFFF
+#define   S_000044_GUIDMA_AK(x)                        (((x) & 0x1) << 30)
+#define   G_000044_GUIDMA_AK(x)                        (((x) >> 30) & 0x1)
+#define   C_000044_GUIDMA_AK                           0xBFFFFFFF
+#define   S_000044_VIDDMA_STAT(x)                      (((x) & 0x1) << 31)
+#define   G_000044_VIDDMA_STAT(x)                      (((x) >> 31) & 0x1)
+#define   C_000044_VIDDMA_STAT                         0x7FFFFFFF
+#define   S_000044_VIDDMA_AK(x)                        (((x) & 0x1) << 31)
+#define   G_000044_VIDDMA_AK(x)                        (((x) >> 31) & 0x1)
+#define   C_000044_VIDDMA_AK                           0x7FFFFFFF
+#define R_000050_CRTC_GEN_CNTL                       0x000050
+#define   S_000050_CRTC_DBL_SCAN_EN(x)                 (((x) & 0x1) << 0)
+#define   G_000050_CRTC_DBL_SCAN_EN(x)                 (((x) >> 0) & 0x1)
+#define   C_000050_CRTC_DBL_SCAN_EN                    0xFFFFFFFE
+#define   S_000050_CRTC_INTERLACE_EN(x)                (((x) & 0x1) << 1)
+#define   G_000050_CRTC_INTERLACE_EN(x)                (((x) >> 1) & 0x1)
+#define   C_000050_CRTC_INTERLACE_EN                   0xFFFFFFFD
+#define   S_000050_CRTC_C_SYNC_EN(x)                   (((x) & 0x1) << 4)
+#define   G_000050_CRTC_C_SYNC_EN(x)                   (((x) >> 4) & 0x1)
+#define   C_000050_CRTC_C_SYNC_EN                      0xFFFFFFEF
+#define   S_000050_CRTC_PIX_WIDTH(x)                   (((x) & 0xF) << 8)
+#define   G_000050_CRTC_PIX_WIDTH(x)                   (((x) >> 8) & 0xF)
+#define   C_000050_CRTC_PIX_WIDTH                      0xFFFFF0FF
+#define   S_000050_CRTC_ICON_EN(x)                     (((x) & 0x1) << 15)
+#define   G_000050_CRTC_ICON_EN(x)                     (((x) >> 15) & 0x1)
+#define   C_000050_CRTC_ICON_EN                        0xFFFF7FFF
+#define   S_000050_CRTC_CUR_EN(x)                      (((x) & 0x1) << 16)
+#define   G_000050_CRTC_CUR_EN(x)                      (((x) >> 16) & 0x1)
+#define   C_000050_CRTC_CUR_EN                         0xFFFEFFFF
+#define   S_000050_CRTC_VSTAT_MODE(x)                  (((x) & 0x3) << 17)
+#define   G_000050_CRTC_VSTAT_MODE(x)                  (((x) >> 17) & 0x3)
+#define   C_000050_CRTC_VSTAT_MODE                     0xFFF9FFFF
+#define   S_000050_CRTC_CUR_MODE(x)                    (((x) & 0x7) << 20)
+#define   G_000050_CRTC_CUR_MODE(x)                    (((x) >> 20) & 0x7)
+#define   C_000050_CRTC_CUR_MODE                       0xFF8FFFFF
+#define   S_000050_CRTC_EXT_DISP_EN(x)                 (((x) & 0x1) << 24)
+#define   G_000050_CRTC_EXT_DISP_EN(x)                 (((x) >> 24) & 0x1)
+#define   C_000050_CRTC_EXT_DISP_EN                    0xFEFFFFFF
+#define   S_000050_CRTC_EN(x)                          (((x) & 0x1) << 25)
+#define   G_000050_CRTC_EN(x)                          (((x) >> 25) & 0x1)
+#define   C_000050_CRTC_EN                             0xFDFFFFFF
+#define   S_000050_CRTC_DISP_REQ_EN_B(x)               (((x) & 0x1) << 26)
+#define   G_000050_CRTC_DISP_REQ_EN_B(x)               (((x) >> 26) & 0x1)
+#define   C_000050_CRTC_DISP_REQ_EN_B                  0xFBFFFFFF
+#define R_000054_CRTC_EXT_CNTL                       0x000054
+#define   S_000054_CRTC_VGA_XOVERSCAN(x)               (((x) & 0x1) << 0)
+#define   G_000054_CRTC_VGA_XOVERSCAN(x)               (((x) >> 0) & 0x1)
+#define   C_000054_CRTC_VGA_XOVERSCAN                  0xFFFFFFFE
+#define   S_000054_VGA_BLINK_RATE(x)                   (((x) & 0x3) << 1)
+#define   G_000054_VGA_BLINK_RATE(x)                   (((x) >> 1) & 0x3)
+#define   C_000054_VGA_BLINK_RATE                      0xFFFFFFF9
+#define   S_000054_VGA_ATI_LINEAR(x)                   (((x) & 0x1) << 3)
+#define   G_000054_VGA_ATI_LINEAR(x)                   (((x) >> 3) & 0x1)
+#define   C_000054_VGA_ATI_LINEAR                      0xFFFFFFF7
+#define   S_000054_VGA_128KAP_PAGING(x)                (((x) & 0x1) << 4)
+#define   G_000054_VGA_128KAP_PAGING(x)                (((x) >> 4) & 0x1)
+#define   C_000054_VGA_128KAP_PAGING                   0xFFFFFFEF
+#define   S_000054_VGA_TEXT_132(x)                     (((x) & 0x1) << 5)
+#define   G_000054_VGA_TEXT_132(x)                     (((x) >> 5) & 0x1)
+#define   C_000054_VGA_TEXT_132                        0xFFFFFFDF
+#define   S_000054_VGA_XCRT_CNT_EN(x)                  (((x) & 0x1) << 6)
+#define   G_000054_VGA_XCRT_CNT_EN(x)                  (((x) >> 6) & 0x1)
+#define   C_000054_VGA_XCRT_CNT_EN                     0xFFFFFFBF
+#define   S_000054_CRTC_HSYNC_DIS(x)                   (((x) & 0x1) << 8)
+#define   G_000054_CRTC_HSYNC_DIS(x)                   (((x) >> 8) & 0x1)
+#define   C_000054_CRTC_HSYNC_DIS                      0xFFFFFEFF
+#define   S_000054_CRTC_VSYNC_DIS(x)                   (((x) & 0x1) << 9)
+#define   G_000054_CRTC_VSYNC_DIS(x)                   (((x) >> 9) & 0x1)
+#define   C_000054_CRTC_VSYNC_DIS                      0xFFFFFDFF
+#define   S_000054_CRTC_DISPLAY_DIS(x)                 (((x) & 0x1) << 10)
+#define   G_000054_CRTC_DISPLAY_DIS(x)                 (((x) >> 10) & 0x1)
+#define   C_000054_CRTC_DISPLAY_DIS                    0xFFFFFBFF
+#define   S_000054_CRTC_SYNC_TRISTATE(x)               (((x) & 0x1) << 11)
+#define   G_000054_CRTC_SYNC_TRISTATE(x)               (((x) >> 11) & 0x1)
+#define   C_000054_CRTC_SYNC_TRISTATE                  0xFFFFF7FF
+#define   S_000054_CRTC_HSYNC_TRISTATE(x)              (((x) & 0x1) << 12)
+#define   G_000054_CRTC_HSYNC_TRISTATE(x)              (((x) >> 12) & 0x1)
+#define   C_000054_CRTC_HSYNC_TRISTATE                 0xFFFFEFFF
+#define   S_000054_CRTC_VSYNC_TRISTATE(x)              (((x) & 0x1) << 13)
+#define   G_000054_CRTC_VSYNC_TRISTATE(x)              (((x) >> 13) & 0x1)
+#define   C_000054_CRTC_VSYNC_TRISTATE                 0xFFFFDFFF
+#define   S_000054_CRT_ON(x)                           (((x) & 0x1) << 15)
+#define   G_000054_CRT_ON(x)                           (((x) >> 15) & 0x1)
+#define   C_000054_CRT_ON                              0xFFFF7FFF
+#define   S_000054_VGA_CUR_B_TEST(x)                   (((x) & 0x1) << 17)
+#define   G_000054_VGA_CUR_B_TEST(x)                   (((x) >> 17) & 0x1)
+#define   C_000054_VGA_CUR_B_TEST                      0xFFFDFFFF
+#define   S_000054_VGA_PACK_DIS(x)                     (((x) & 0x1) << 18)
+#define   G_000054_VGA_PACK_DIS(x)                     (((x) >> 18) & 0x1)
+#define   C_000054_VGA_PACK_DIS                        0xFFFBFFFF
+#define   S_000054_VGA_MEM_PS_EN(x)                    (((x) & 0x1) << 19)
+#define   G_000054_VGA_MEM_PS_EN(x)                    (((x) >> 19) & 0x1)
+#define   C_000054_VGA_MEM_PS_EN                       0xFFF7FFFF
+#define   S_000054_VCRTC_IDX_MASTER(x)                 (((x) & 0x7F) << 24)
+#define   G_000054_VCRTC_IDX_MASTER(x)                 (((x) >> 24) & 0x7F)
+#define   C_000054_VCRTC_IDX_MASTER                    0x80FFFFFF
+#define R_00023C_DISPLAY_BASE_ADDR                   0x00023C
+#define   S_00023C_DISPLAY_BASE_ADDR(x)                (((x) & 0xFFFFFFFF) << 0)
+#define   G_00023C_DISPLAY_BASE_ADDR(x)                (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00023C_DISPLAY_BASE_ADDR                   0x00000000
+#define R_000260_CUR_OFFSET                          0x000260
+#define   S_000260_CUR_OFFSET(x)                       (((x) & 0x7FFFFFF) << 0)
+#define   G_000260_CUR_OFFSET(x)                       (((x) >> 0) & 0x7FFFFFF)
+#define   C_000260_CUR_OFFSET                          0xF8000000
+#define   S_000260_CUR_LOCK(x)                         (((x) & 0x1) << 31)
+#define   G_000260_CUR_LOCK(x)                         (((x) >> 31) & 0x1)
+#define   C_000260_CUR_LOCK                            0x7FFFFFFF
+#define R_00033C_CRTC2_DISPLAY_BASE_ADDR             0x00033C
+#define   S_00033C_CRTC2_DISPLAY_BASE_ADDR(x)          (((x) & 0xFFFFFFFF) << 0)
+#define   G_00033C_CRTC2_DISPLAY_BASE_ADDR(x)          (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00033C_CRTC2_DISPLAY_BASE_ADDR             0x00000000
+#define R_000360_CUR2_OFFSET                         0x000360
+#define   S_000360_CUR2_OFFSET(x)                      (((x) & 0x7FFFFFF) << 0)
+#define   G_000360_CUR2_OFFSET(x)                      (((x) >> 0) & 0x7FFFFFF)
+#define   C_000360_CUR2_OFFSET                         0xF8000000
+#define   S_000360_CUR2_LOCK(x)                        (((x) & 0x1) << 31)
+#define   G_000360_CUR2_LOCK(x)                        (((x) >> 31) & 0x1)
+#define   C_000360_CUR2_LOCK                           0x7FFFFFFF
+#define R_0003C0_GENMO_WT                            0x0003C0
+#define   S_0003C0_GENMO_MONO_ADDRESS_B(x)             (((x) & 0x1) << 0)
+#define   G_0003C0_GENMO_MONO_ADDRESS_B(x)             (((x) >> 0) & 0x1)
+#define   C_0003C0_GENMO_MONO_ADDRESS_B                0xFFFFFFFE
+#define   S_0003C0_VGA_RAM_EN(x)                       (((x) & 0x1) << 1)
+#define   G_0003C0_VGA_RAM_EN(x)                       (((x) >> 1) & 0x1)
+#define   C_0003C0_VGA_RAM_EN                          0xFFFFFFFD
+#define   S_0003C0_VGA_CKSEL(x)                        (((x) & 0x3) << 2)
+#define   G_0003C0_VGA_CKSEL(x)                        (((x) >> 2) & 0x3)
+#define   C_0003C0_VGA_CKSEL                           0xFFFFFFF3
+#define   S_0003C0_ODD_EVEN_MD_PGSEL(x)                (((x) & 0x1) << 5)
+#define   G_0003C0_ODD_EVEN_MD_PGSEL(x)                (((x) >> 5) & 0x1)
+#define   C_0003C0_ODD_EVEN_MD_PGSEL                   0xFFFFFFDF
+#define   S_0003C0_VGA_HSYNC_POL(x)                    (((x) & 0x1) << 6)
+#define   G_0003C0_VGA_HSYNC_POL(x)                    (((x) >> 6) & 0x1)
+#define   C_0003C0_VGA_HSYNC_POL                       0xFFFFFFBF
+#define   S_0003C0_VGA_VSYNC_POL(x)                    (((x) & 0x1) << 7)
+#define   G_0003C0_VGA_VSYNC_POL(x)                    (((x) >> 7) & 0x1)
+#define   C_0003C0_VGA_VSYNC_POL                       0xFFFFFF7F
+#define R_0003F8_CRTC2_GEN_CNTL                      0x0003F8
+#define   S_0003F8_CRTC2_DBL_SCAN_EN(x)                (((x) & 0x1) << 0)
+#define   G_0003F8_CRTC2_DBL_SCAN_EN(x)                (((x) >> 0) & 0x1)
+#define   C_0003F8_CRTC2_DBL_SCAN_EN                   0xFFFFFFFE
+#define   S_0003F8_CRTC2_INTERLACE_EN(x)               (((x) & 0x1) << 1)
+#define   G_0003F8_CRTC2_INTERLACE_EN(x)               (((x) >> 1) & 0x1)
+#define   C_0003F8_CRTC2_INTERLACE_EN                  0xFFFFFFFD
+#define   S_0003F8_CRTC2_SYNC_TRISTATE(x)              (((x) & 0x1) << 4)
+#define   G_0003F8_CRTC2_SYNC_TRISTATE(x)              (((x) >> 4) & 0x1)
+#define   C_0003F8_CRTC2_SYNC_TRISTATE                 0xFFFFFFEF
+#define   S_0003F8_CRTC2_HSYNC_TRISTATE(x)             (((x) & 0x1) << 5)
+#define   G_0003F8_CRTC2_HSYNC_TRISTATE(x)             (((x) >> 5) & 0x1)
+#define   C_0003F8_CRTC2_HSYNC_TRISTATE                0xFFFFFFDF
+#define   S_0003F8_CRTC2_VSYNC_TRISTATE(x)             (((x) & 0x1) << 6)
+#define   G_0003F8_CRTC2_VSYNC_TRISTATE(x)             (((x) >> 6) & 0x1)
+#define   C_0003F8_CRTC2_VSYNC_TRISTATE                0xFFFFFFBF
+#define   S_0003F8_CRT2_ON(x)                          (((x) & 0x1) << 7)
+#define   G_0003F8_CRT2_ON(x)                          (((x) >> 7) & 0x1)
+#define   C_0003F8_CRT2_ON                             0xFFFFFF7F
+#define   S_0003F8_CRTC2_PIX_WIDTH(x)                  (((x) & 0xF) << 8)
+#define   G_0003F8_CRTC2_PIX_WIDTH(x)                  (((x) >> 8) & 0xF)
+#define   C_0003F8_CRTC2_PIX_WIDTH                     0xFFFFF0FF
+#define   S_0003F8_CRTC2_ICON_EN(x)                    (((x) & 0x1) << 15)
+#define   G_0003F8_CRTC2_ICON_EN(x)                    (((x) >> 15) & 0x1)
+#define   C_0003F8_CRTC2_ICON_EN                       0xFFFF7FFF
+#define   S_0003F8_CRTC2_CUR_EN(x)                     (((x) & 0x1) << 16)
+#define   G_0003F8_CRTC2_CUR_EN(x)                     (((x) >> 16) & 0x1)
+#define   C_0003F8_CRTC2_CUR_EN                        0xFFFEFFFF
+#define   S_0003F8_CRTC2_CUR_MODE(x)                   (((x) & 0x7) << 20)
+#define   G_0003F8_CRTC2_CUR_MODE(x)                   (((x) >> 20) & 0x7)
+#define   C_0003F8_CRTC2_CUR_MODE                      0xFF8FFFFF
+#define   S_0003F8_CRTC2_DISPLAY_DIS(x)                (((x) & 0x1) << 23)
+#define   G_0003F8_CRTC2_DISPLAY_DIS(x)                (((x) >> 23) & 0x1)
+#define   C_0003F8_CRTC2_DISPLAY_DIS                   0xFF7FFFFF
+#define   S_0003F8_CRTC2_EN(x)                         (((x) & 0x1) << 25)
+#define   G_0003F8_CRTC2_EN(x)                         (((x) >> 25) & 0x1)
+#define   C_0003F8_CRTC2_EN                            0xFDFFFFFF
+#define   S_0003F8_CRTC2_DISP_REQ_EN_B(x)              (((x) & 0x1) << 26)
+#define   G_0003F8_CRTC2_DISP_REQ_EN_B(x)              (((x) >> 26) & 0x1)
+#define   C_0003F8_CRTC2_DISP_REQ_EN_B                 0xFBFFFFFF
+#define   S_0003F8_CRTC2_C_SYNC_EN(x)                  (((x) & 0x1) << 27)
+#define   G_0003F8_CRTC2_C_SYNC_EN(x)                  (((x) >> 27) & 0x1)
+#define   C_0003F8_CRTC2_C_SYNC_EN                     0xF7FFFFFF
+#define   S_0003F8_CRTC2_HSYNC_DIS(x)                  (((x) & 0x1) << 28)
+#define   G_0003F8_CRTC2_HSYNC_DIS(x)                  (((x) >> 28) & 0x1)
+#define   C_0003F8_CRTC2_HSYNC_DIS                     0xEFFFFFFF
+#define   S_0003F8_CRTC2_VSYNC_DIS(x)                  (((x) & 0x1) << 29)
+#define   G_0003F8_CRTC2_VSYNC_DIS(x)                  (((x) >> 29) & 0x1)
+#define   C_0003F8_CRTC2_VSYNC_DIS                     0xDFFFFFFF
+#define R_000420_OV0_SCALE_CNTL                      0x000420
+#define   S_000420_OV0_NO_READ_BEHIND_SCAN(x)          (((x) & 0x1) << 1)
+#define   G_000420_OV0_NO_READ_BEHIND_SCAN(x)          (((x) >> 1) & 0x1)
+#define   C_000420_OV0_NO_READ_BEHIND_SCAN             0xFFFFFFFD
+#define   S_000420_OV0_HORZ_PICK_NEAREST(x)            (((x) & 0x1) << 2)
+#define   G_000420_OV0_HORZ_PICK_NEAREST(x)            (((x) >> 2) & 0x1)
+#define   C_000420_OV0_HORZ_PICK_NEAREST               0xFFFFFFFB
+#define   S_000420_OV0_VERT_PICK_NEAREST(x)            (((x) & 0x1) << 3)
+#define   G_000420_OV0_VERT_PICK_NEAREST(x)            (((x) >> 3) & 0x1)
+#define   C_000420_OV0_VERT_PICK_NEAREST               0xFFFFFFF7
+#define   S_000420_OV0_SIGNED_UV(x)                    (((x) & 0x1) << 4)
+#define   G_000420_OV0_SIGNED_UV(x)                    (((x) >> 4) & 0x1)
+#define   C_000420_OV0_SIGNED_UV                       0xFFFFFFEF
+#define   S_000420_OV0_GAMMA_SEL(x)                    (((x) & 0x7) << 5)
+#define   G_000420_OV0_GAMMA_SEL(x)                    (((x) >> 5) & 0x7)
+#define   C_000420_OV0_GAMMA_SEL                       0xFFFFFF1F
+#define   S_000420_OV0_SURFACE_FORMAT(x)               (((x) & 0xF) << 8)
+#define   G_000420_OV0_SURFACE_FORMAT(x)               (((x) >> 8) & 0xF)
+#define   C_000420_OV0_SURFACE_FORMAT                  0xFFFFF0FF
+#define   S_000420_OV0_ADAPTIVE_DEINT(x)               (((x) & 0x1) << 12)
+#define   G_000420_OV0_ADAPTIVE_DEINT(x)               (((x) >> 12) & 0x1)
+#define   C_000420_OV0_ADAPTIVE_DEINT                  0xFFFFEFFF
+#define   S_000420_OV0_CRTC_SEL(x)                     (((x) & 0x1) << 14)
+#define   G_000420_OV0_CRTC_SEL(x)                     (((x) >> 14) & 0x1)
+#define   C_000420_OV0_CRTC_SEL                        0xFFFFBFFF
+#define   S_000420_OV0_BURST_PER_PLANE(x)              (((x) & 0x7F) << 16)
+#define   G_000420_OV0_BURST_PER_PLANE(x)              (((x) >> 16) & 0x7F)
+#define   C_000420_OV0_BURST_PER_PLANE                 0xFF80FFFF
+#define   S_000420_OV0_DOUBLE_BUFFER_REGS(x)           (((x) & 0x1) << 24)
+#define   G_000420_OV0_DOUBLE_BUFFER_REGS(x)           (((x) >> 24) & 0x1)
+#define   C_000420_OV0_DOUBLE_BUFFER_REGS              0xFEFFFFFF
+#define   S_000420_OV0_BANDWIDTH(x)                    (((x) & 0x1) << 26)
+#define   G_000420_OV0_BANDWIDTH(x)                    (((x) >> 26) & 0x1)
+#define   C_000420_OV0_BANDWIDTH                       0xFBFFFFFF
+#define   S_000420_OV0_LIN_TRANS_BYPASS(x)             (((x) & 0x1) << 28)
+#define   G_000420_OV0_LIN_TRANS_BYPASS(x)             (((x) >> 28) & 0x1)
+#define   C_000420_OV0_LIN_TRANS_BYPASS                0xEFFFFFFF
+#define   S_000420_OV0_INT_EMU(x)                      (((x) & 0x1) << 29)
+#define   G_000420_OV0_INT_EMU(x)                      (((x) >> 29) & 0x1)
+#define   C_000420_OV0_INT_EMU                         0xDFFFFFFF
+#define   S_000420_OV0_OVERLAY_EN(x)                   (((x) & 0x1) << 30)
+#define   G_000420_OV0_OVERLAY_EN(x)                   (((x) >> 30) & 0x1)
+#define   C_000420_OV0_OVERLAY_EN                      0xBFFFFFFF
+#define   S_000420_OV0_SOFT_RESET(x)                   (((x) & 0x1) << 31)
+#define   G_000420_OV0_SOFT_RESET(x)                   (((x) >> 31) & 0x1)
+#define   C_000420_OV0_SOFT_RESET                      0x7FFFFFFF
+#define R_00070C_CP_RB_RPTR_ADDR                     0x00070C
+#define   S_00070C_RB_RPTR_SWAP(x)                     (((x) & 0x3) << 0)
+#define   G_00070C_RB_RPTR_SWAP(x)                     (((x) >> 0) & 0x3)
+#define   C_00070C_RB_RPTR_SWAP                        0xFFFFFFFC
+#define   S_00070C_RB_RPTR_ADDR(x)                     (((x) & 0x3FFFFFFF) << 2)
+#define   G_00070C_RB_RPTR_ADDR(x)                     (((x) >> 2) & 0x3FFFFFFF)
+#define   C_00070C_RB_RPTR_ADDR                        0x00000003
+#define R_000740_CP_CSQ_CNTL                         0x000740
+#define   S_000740_CSQ_CNT_PRIMARY(x)                  (((x) & 0xFF) << 0)
+#define   G_000740_CSQ_CNT_PRIMARY(x)                  (((x) >> 0) & 0xFF)
+#define   C_000740_CSQ_CNT_PRIMARY                     0xFFFFFF00
+#define   S_000740_CSQ_CNT_INDIRECT(x)                 (((x) & 0xFF) << 8)
+#define   G_000740_CSQ_CNT_INDIRECT(x)                 (((x) >> 8) & 0xFF)
+#define   C_000740_CSQ_CNT_INDIRECT                    0xFFFF00FF
+#define   S_000740_CSQ_MODE(x)                         (((x) & 0xF) << 28)
+#define   G_000740_CSQ_MODE(x)                         (((x) >> 28) & 0xF)
+#define   C_000740_CSQ_MODE                            0x0FFFFFFF
+#define R_000770_SCRATCH_UMSK                        0x000770
+#define   S_000770_SCRATCH_UMSK(x)                     (((x) & 0x3F) << 0)
+#define   G_000770_SCRATCH_UMSK(x)                     (((x) >> 0) & 0x3F)
+#define   C_000770_SCRATCH_UMSK                        0xFFFFFFC0
+#define   S_000770_SCRATCH_SWAP(x)                     (((x) & 0x3) << 16)
+#define   G_000770_SCRATCH_SWAP(x)                     (((x) >> 16) & 0x3)
+#define   C_000770_SCRATCH_SWAP                        0xFFFCFFFF
+#define R_000774_SCRATCH_ADDR                        0x000774
+#define   S_000774_SCRATCH_ADDR(x)                     (((x) & 0x7FFFFFF) << 5)
+#define   G_000774_SCRATCH_ADDR(x)                     (((x) >> 5) & 0x7FFFFFF)
+#define   C_000774_SCRATCH_ADDR                        0x0000001F
 #define R_000E40_RBBM_STATUS                         0x000E40
 #define   S_000E40_CMDFIFO_AVAIL(x)                    (((x) & 0x7F) << 0)
 #define   G_000E40_CMDFIFO_AVAIL(x)                    (((x) >> 0) & 0x7F)
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 9c17b786982..92f9cb74a7d 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -1241,11 +1241,12 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
 int r300_cs_parse(struct radeon_cs_parser *p)
 {
 	struct radeon_cs_packet pkt;
-	struct r100_cs_track track;
+	struct r100_cs_track *track;
 	int r;
 
-	r100_cs_track_clear(p->rdev, &track);
-	p->track = &track;
+	track = kzalloc(sizeof(*track), GFP_KERNEL);
+	r100_cs_track_clear(p->rdev, track);
+	p->track = track;
 	do {
 		r = r100_cs_packet_parse(p, &pkt, p->idx);
 		if (r) {
@@ -1275,9 +1276,50 @@ int r300_cs_parse(struct radeon_cs_parser *p)
 	return 0;
 }
 
-int r300_init(struct radeon_device *rdev)
+void r300_set_reg_safe(struct radeon_device *rdev)
 {
 	rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
 	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
+}
+
+int r300_init(struct radeon_device *rdev)
+{
+	r300_set_reg_safe(rdev);
 	return 0;
 }
+
+void r300_mc_program(struct radeon_device *rdev)
+{
+	struct r100_mc_save save;
+	int r;
+
+	r = r100_debugfs_mc_info_init(rdev);
+	if (r) {
+		dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
+	}
+
+	/* Stops all mc clients */
+	r100_mc_stop(rdev, &save);
+	/* Shutdown PCI/PCIE GART */
+	radeon_gart_disable(rdev);
+	if (rdev->flags & RADEON_IS_AGP) {
+		WREG32(R_00014C_MC_AGP_LOCATION,
+			S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
+			S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
+		WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
+		WREG32(R_00015C_AGP_BASE_2,
+			upper_32_bits(rdev->mc.agp_base) & 0xff);
+	} else {
+		WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
+		WREG32(R_000170_AGP_BASE, 0);
+		WREG32(R_00015C_AGP_BASE_2, 0);
+	}
+	/* Wait for mc idle */
+	if (r300_mc_wait_for_idle(rdev))
+		DRM_INFO("Failed to wait MC idle before programming MC.\n");
+	/* Program MC, should be a 32bits limited address space */
+	WREG32(R_000148_MC_FB_LOCATION,
+		S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
+		S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
+	r100_mc_resume(rdev, &save);
+}
diff --git a/drivers/gpu/drm/radeon/r300d.h b/drivers/gpu/drm/radeon/r300d.h
index 63ec076f2cd..d4fa3eb1074 100644
--- a/drivers/gpu/drm/radeon/r300d.h
+++ b/drivers/gpu/drm/radeon/r300d.h
@@ -73,4 +73,29 @@
 #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
 
+/* Registers */
+#define R_000148_MC_FB_LOCATION                      0x000148
+#define   S_000148_MC_FB_START(x)                      (((x) & 0xFFFF) << 0)
+#define   G_000148_MC_FB_START(x)                      (((x) >> 0) & 0xFFFF)
+#define   C_000148_MC_FB_START                         0xFFFF0000
+#define   S_000148_MC_FB_TOP(x)                        (((x) & 0xFFFF) << 16)
+#define   G_000148_MC_FB_TOP(x)                        (((x) >> 16) & 0xFFFF)
+#define   C_000148_MC_FB_TOP                           0x0000FFFF
+#define R_00014C_MC_AGP_LOCATION                     0x00014C
+#define   S_00014C_MC_AGP_START(x)                     (((x) & 0xFFFF) << 0)
+#define   G_00014C_MC_AGP_START(x)                     (((x) >> 0) & 0xFFFF)
+#define   C_00014C_MC_AGP_START                        0xFFFF0000
+#define   S_00014C_MC_AGP_TOP(x)                       (((x) & 0xFFFF) << 16)
+#define   G_00014C_MC_AGP_TOP(x)                       (((x) >> 16) & 0xFFFF)
+#define   C_00014C_MC_AGP_TOP                          0x0000FFFF
+#define R_00015C_AGP_BASE_2                          0x00015C
+#define   S_00015C_AGP_BASE_ADDR_2(x)                  (((x) & 0xF) << 0)
+#define   G_00015C_AGP_BASE_ADDR_2(x)                  (((x) >> 0) & 0xF)
+#define   C_00015C_AGP_BASE_ADDR_2                     0xFFFFFFF0
+#define R_000170_AGP_BASE                            0x000170
+#define   S_000170_AGP_BASE_ADDR(x)                    (((x) & 0xFFFFFFFF) << 0)
+#define   G_000170_AGP_BASE_ADDR(x)                    (((x) >> 0) & 0xFFFFFFFF)
+#define   C_000170_AGP_BASE_ADDR                       0x00000000
+
+
 #endif
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 551d6996d3f..e57b9ba4aaf 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -29,48 +29,13 @@
 #include "drmP.h"
 #include "radeon_reg.h"
 #include "radeon.h"
+#include "atom.h"
 #include "r420d.h"
 
-/* r420,r423,rv410 depends on : */
-void r100_pci_gart_disable(struct radeon_device *rdev);
-void r100_hdp_reset(struct radeon_device *rdev);
-void r100_mc_setup(struct radeon_device *rdev);
-int r100_gui_wait_for_idle(struct radeon_device *rdev);
-void r100_mc_disable_clients(struct radeon_device *rdev);
-void r300_vram_info(struct radeon_device *rdev);
-int r300_mc_wait_for_idle(struct radeon_device *rdev);
-int rv370_pcie_gart_enable(struct radeon_device *rdev);
-void rv370_pcie_gart_disable(struct radeon_device *rdev);
-
-/* This files gather functions specifics to :
- * r420,r423,rv410
- *
- * Some of these functions might be used by newer ASICs.
- */
-void r420_gpu_init(struct radeon_device *rdev);
-int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
-
-
-/*
- * MC
- */
 int r420_mc_init(struct radeon_device *rdev)
 {
 	int r;
 
-	if (r100_debugfs_rbbm_init(rdev)) {
-		DRM_ERROR("Failed to register debugfs file for RBBM !\n");
-	}
-	if (r420_debugfs_pipes_info_init(rdev)) {
-		DRM_ERROR("Failed to register debugfs file for pipes !\n");
-	}
-
-	r420_gpu_init(rdev);
-	r100_pci_gart_disable(rdev);
-	if (rdev->flags & RADEON_IS_PCIE) {
-		rv370_pcie_gart_disable(rdev);
-	}
-
 	/* Setup GPU memory space */
 	rdev->mc.vram_location = 0xFFFFFFFFUL;
 	rdev->mc.gtt_location = 0xFFFFFFFFUL;
@@ -88,38 +53,9 @@ int r420_mc_init(struct radeon_device *rdev)
 	if (r) {
 		return r;
 	}
-
-	/* Program GPU memory space */
-	r100_mc_disable_clients(rdev);
-	if (r300_mc_wait_for_idle(rdev)) {
-		printk(KERN_WARNING "Failed to wait MC idle while "
-		       "programming pipes. Bad things might happen.\n");
-	}
-	r100_mc_setup(rdev);
 	return 0;
 }
 
-void r420_mc_fini(struct radeon_device *rdev)
-{
-	if (rdev->flags & RADEON_IS_PCIE) {
-		rv370_pcie_gart_disable(rdev);
-		radeon_gart_table_vram_free(rdev);
-	} else {
-		r100_pci_gart_disable(rdev);
-		radeon_gart_table_ram_free(rdev);
-	}
-	radeon_gart_fini(rdev);
-}
-
-
-/*
- * Global GPU functions
- */
-void r420_errata(struct radeon_device *rdev)
-{
-	rdev->pll_errata = 0;
-}
-
 void r420_pipes_init(struct radeon_device *rdev)
 {
 	unsigned tmp;
@@ -185,25 +121,216 @@ void r420_pipes_init(struct radeon_device *rdev)
 		 rdev->num_gb_pipes, rdev->num_z_pipes);
 }
 
-void r420_gpu_init(struct radeon_device *rdev)
+u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
 {
-	r100_hdp_reset(rdev);
+	u32 r;
+
+	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
+	r = RREG32(R_0001FC_MC_IND_DATA);
+	return r;
+}
+
+void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
+{
+	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
+		S_0001F8_MC_IND_WR_EN(1));
+	WREG32(R_0001FC_MC_IND_DATA, v);
+}
+
+static void r420_debugfs(struct radeon_device *rdev)
+{
+	if (r100_debugfs_rbbm_init(rdev)) {
+		DRM_ERROR("Failed to register debugfs file for RBBM !\n");
+	}
+	if (r420_debugfs_pipes_info_init(rdev)) {
+		DRM_ERROR("Failed to register debugfs file for pipes !\n");
+	}
+}
+
+static void r420_clock_resume(struct radeon_device *rdev)
+{
+	u32 sclk_cntl;
+	sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
+	sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
+	if (rdev->family == CHIP_R420)
+		sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
+	WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
+}
+
+int r420_resume(struct radeon_device *rdev)
+{
+	int r;
+
+	/* Resume clock before doing reset */
+	r420_clock_resume(rdev);
+	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
+	if (radeon_gpu_reset(rdev)) {
+		dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
+			RREG32(R_000E40_RBBM_STATUS),
+			RREG32(R_0007C0_CP_STAT));
+	}
+	/* check if cards are posted or not */
+	if (rdev->is_atom_bios) {
+		atom_asic_init(rdev->mode_info.atom_context);
+	} else {
+		radeon_combios_asic_init(rdev->ddev);
+	}
+	/* Resume clock after posting */
+	r420_clock_resume(rdev);
+	r300_mc_program(rdev);
+	/* Initialize GART (initialize after TTM so we can allocate
+	 * memory through TTM but finalize after TTM) */
+	r = radeon_gart_enable(rdev);
+	if (r) {
+		dev_err(rdev->dev, "failled initializing GART (%d).\n", r);
+		return r;
+	}
 	r420_pipes_init(rdev);
-	if (r300_mc_wait_for_idle(rdev)) {
-		printk(KERN_WARNING "Failed to wait MC idle while "
-		       "programming pipes. Bad things might happen.\n");
+	/* Enable IRQ */
+	rdev->irq.sw_int = true;
+	r100_irq_set(rdev);
+	/* 1M ring buffer */
+	r = r100_cp_init(rdev, 1024 * 1024);
+	if (r) {
+		dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
+		return r;
+	}
+	r = r100_wb_init(rdev);
+	if (r) {
+		dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
 	}
+	r = r100_ib_init(rdev);
+	if (r) {
+		dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
+		return r;
+	}
+	return 0;
 }
 
+int r420_suspend(struct radeon_device *rdev)
+{
+	r100_cp_disable(rdev);
+	r100_wb_disable(rdev);
+	r100_irq_disable(rdev);
+	radeon_gart_disable(rdev);
+	return 0;
+}
 
-/*
- * r420,r423,rv410 VRAM info
- */
-void r420_vram_info(struct radeon_device *rdev)
+void r420_fini(struct radeon_device *rdev)
 {
-	r300_vram_info(rdev);
+	r100_cp_fini(rdev);
+	r100_wb_fini(rdev);
+	r100_ib_fini(rdev);
+	radeon_gem_fini(rdev);
+	if (rdev->flags & RADEON_IS_PCIE) {
+		rv370_pcie_gart_disable(rdev);
+		radeon_gart_table_vram_free(rdev);
+	} else {
+		r100_pci_gart_disable(rdev);
+		radeon_gart_table_ram_free(rdev);
+	}
+	radeon_gart_fini(rdev);
+	radeon_agp_fini(rdev);
+	radeon_irq_kms_fini(rdev);
+	radeon_fence_driver_fini(rdev);
+	radeon_object_fini(rdev);
+	if (rdev->is_atom_bios) {
+		radeon_atombios_fini(rdev);
+	} else {
+		radeon_combios_fini(rdev);
+	}
+	kfree(rdev->bios);
+	rdev->bios = NULL;
 }
 
+int r420_init(struct radeon_device *rdev)
+{
+	int r;
+
+	rdev->new_init_path = true;
+	/* Initialize scratch registers */
+	radeon_scratch_init(rdev);
+	/* Initialize surface registers */
+	radeon_surface_init(rdev);
+	/* TODO: disable VGA need to use VGA request */
+	/* BIOS*/
+	if (!radeon_get_bios(rdev)) {
+		if (ASIC_IS_AVIVO(rdev))
+			return -EINVAL;
+	}
+	if (rdev->is_atom_bios) {
+		r = radeon_atombios_init(rdev);
+		if (r) {
+			return r;
+		}
+	} else {
+		r = radeon_combios_init(rdev);
+		if (r) {
+			return r;
+		}
+	}
+	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
+	if (radeon_gpu_reset(rdev)) {
+		dev_warn(rdev->dev,
+			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
+			RREG32(R_000E40_RBBM_STATUS),
+			RREG32(R_0007C0_CP_STAT));
+	}
+	/* check if cards are posted or not */
+	if (!radeon_card_posted(rdev) && rdev->bios) {
+		DRM_INFO("GPU not posted. posting now...\n");
+		if (rdev->is_atom_bios) {
+			atom_asic_init(rdev->mode_info.atom_context);
+		} else {
+			radeon_combios_asic_init(rdev->ddev);
+		}
+	}
+	/* Initialize clocks */
+	radeon_get_clock_info(rdev->ddev);
+	/* Get vram informations */
+	r300_vram_info(rdev);
+	/* Initialize memory controller (also test AGP) */
+	r = r420_mc_init(rdev);
+	if (r) {
+		return r;
+	}
+	r420_debugfs(rdev);
+	/* Fence driver */
+	r = radeon_fence_driver_init(rdev);
+	if (r) {
+		return r;
+	}
+	r = radeon_irq_kms_init(rdev);
+	if (r) {
+		return r;
+	}
+	/* Memory manager */
+	r = radeon_object_init(rdev);
+	if (r) {
+		return r;
+	}
+	r300_set_reg_safe(rdev);
+	r = r420_resume(rdev);
+	if (r) {
+		/* Somethings want wront with the accel init stop accel */
+		dev_err(rdev->dev, "Disabling GPU acceleration\n");
+		r420_suspend(rdev);
+		r100_cp_fini(rdev);
+		r100_wb_fini(rdev);
+		r100_ib_fini(rdev);
+		if (rdev->flags & RADEON_IS_PCIE) {
+			rv370_pcie_gart_disable(rdev);
+			radeon_gart_table_vram_free(rdev);
+		} else {
+			r100_pci_gart_disable(rdev);
+			radeon_gart_table_ram_free(rdev);
+		}
+		radeon_gart_fini(rdev);
+		radeon_agp_fini(rdev);
+		radeon_irq_kms_fini(rdev);
+	}
+	return 0;
+}
 
 /*
  * Debugfs info
@@ -238,19 +365,3 @@ int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
 	return 0;
 #endif
 }
-
-u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
-{
-	u32 r;
-
-	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
-	r = RREG32(R_0001FC_MC_IND_DATA);
-	return r;
-}
-
-void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
-{
-	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
-		S_0001F8_MC_IND_WR_EN(1));
-	WREG32(R_0001FC_MC_IND_DATA, v);
-}
diff --git a/drivers/gpu/drm/radeon/r420d.h b/drivers/gpu/drm/radeon/r420d.h
index 8b946c1883b..a48a7db1e2a 100644
--- a/drivers/gpu/drm/radeon/r420d.h
+++ b/drivers/gpu/drm/radeon/r420d.h
@@ -39,5 +39,211 @@
 #define   S_0001FC_MC_IND_DATA(x)                      (((x) & 0xFFFFFFFF) << 0)
 #define   G_0001FC_MC_IND_DATA(x)                      (((x) >> 0) & 0xFFFFFFFF)
 #define   C_0001FC_MC_IND_DATA                         0x00000000
+#define R_0007C0_CP_STAT                             0x0007C0
+#define   S_0007C0_MRU_BUSY(x)                         (((x) & 0x1) << 0)
+#define   G_0007C0_MRU_BUSY(x)                         (((x) >> 0) & 0x1)
+#define   C_0007C0_MRU_BUSY                            0xFFFFFFFE
+#define   S_0007C0_MWU_BUSY(x)                         (((x) & 0x1) << 1)
+#define   G_0007C0_MWU_BUSY(x)                         (((x) >> 1) & 0x1)
+#define   C_0007C0_MWU_BUSY                            0xFFFFFFFD
+#define   S_0007C0_RSIU_BUSY(x)                        (((x) & 0x1) << 2)
+#define   G_0007C0_RSIU_BUSY(x)                        (((x) >> 2) & 0x1)
+#define   C_0007C0_RSIU_BUSY                           0xFFFFFFFB
+#define   S_0007C0_RCIU_BUSY(x)                        (((x) & 0x1) << 3)
+#define   G_0007C0_RCIU_BUSY(x)                        (((x) >> 3) & 0x1)
+#define   C_0007C0_RCIU_BUSY                           0xFFFFFFF7
+#define   S_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) & 0x1) << 9)
+#define   G_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) >> 9) & 0x1)
+#define   C_0007C0_CSF_PRIMARY_BUSY                    0xFFFFFDFF
+#define   S_0007C0_CSF_INDIRECT_BUSY(x)                (((x) & 0x1) << 10)
+#define   G_0007C0_CSF_INDIRECT_BUSY(x)                (((x) >> 10) & 0x1)
+#define   C_0007C0_CSF_INDIRECT_BUSY                   0xFFFFFBFF
+#define   S_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) & 0x1) << 11)
+#define   G_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) >> 11) & 0x1)
+#define   C_0007C0_CSQ_PRIMARY_BUSY                    0xFFFFF7FF
+#define   S_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) & 0x1) << 12)
+#define   G_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) >> 12) & 0x1)
+#define   C_0007C0_CSQ_INDIRECT_BUSY                   0xFFFFEFFF
+#define   S_0007C0_CSI_BUSY(x)                         (((x) & 0x1) << 13)
+#define   G_0007C0_CSI_BUSY(x)                         (((x) >> 13) & 0x1)
+#define   C_0007C0_CSI_BUSY                            0xFFFFDFFF
+#define   S_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) & 0x1) << 14)
+#define   G_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) >> 14) & 0x1)
+#define   C_0007C0_CSF_INDIRECT2_BUSY                  0xFFFFBFFF
+#define   S_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) & 0x1) << 15)
+#define   G_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) >> 15) & 0x1)
+#define   C_0007C0_CSQ_INDIRECT2_BUSY                  0xFFFF7FFF
+#define   S_0007C0_GUIDMA_BUSY(x)                      (((x) & 0x1) << 28)
+#define   G_0007C0_GUIDMA_BUSY(x)                      (((x) >> 28) & 0x1)
+#define   C_0007C0_GUIDMA_BUSY                         0xEFFFFFFF
+#define   S_0007C0_VIDDMA_BUSY(x)                      (((x) & 0x1) << 29)
+#define   G_0007C0_VIDDMA_BUSY(x)                      (((x) >> 29) & 0x1)
+#define   C_0007C0_VIDDMA_BUSY                         0xDFFFFFFF
+#define   S_0007C0_CMDSTRM_BUSY(x)                     (((x) & 0x1) << 30)
+#define   G_0007C0_CMDSTRM_BUSY(x)                     (((x) >> 30) & 0x1)
+#define   C_0007C0_CMDSTRM_BUSY                        0xBFFFFFFF
+#define   S_0007C0_CP_BUSY(x)                          (((x) & 0x1) << 31)
+#define   G_0007C0_CP_BUSY(x)                          (((x) >> 31) & 0x1)
+#define   C_0007C0_CP_BUSY                             0x7FFFFFFF
+#define R_000E40_RBBM_STATUS                         0x000E40
+#define   S_000E40_CMDFIFO_AVAIL(x)                    (((x) & 0x7F) << 0)
+#define   G_000E40_CMDFIFO_AVAIL(x)                    (((x) >> 0) & 0x7F)
+#define   C_000E40_CMDFIFO_AVAIL                       0xFFFFFF80
+#define   S_000E40_HIRQ_ON_RBB(x)                      (((x) & 0x1) << 8)
+#define   G_000E40_HIRQ_ON_RBB(x)                      (((x) >> 8) & 0x1)
+#define   C_000E40_HIRQ_ON_RBB                         0xFFFFFEFF
+#define   S_000E40_CPRQ_ON_RBB(x)                      (((x) & 0x1) << 9)
+#define   G_000E40_CPRQ_ON_RBB(x)                      (((x) >> 9) & 0x1)
+#define   C_000E40_CPRQ_ON_RBB                         0xFFFFFDFF
+#define   S_000E40_CFRQ_ON_RBB(x)                      (((x) & 0x1) << 10)
+#define   G_000E40_CFRQ_ON_RBB(x)                      (((x) >> 10) & 0x1)
+#define   C_000E40_CFRQ_ON_RBB                         0xFFFFFBFF
+#define   S_000E40_HIRQ_IN_RTBUF(x)                    (((x) & 0x1) << 11)
+#define   G_000E40_HIRQ_IN_RTBUF(x)                    (((x) >> 11) & 0x1)
+#define   C_000E40_HIRQ_IN_RTBUF                       0xFFFFF7FF
+#define   S_000E40_CPRQ_IN_RTBUF(x)                    (((x) & 0x1) << 12)
+#define   G_000E40_CPRQ_IN_RTBUF(x)                    (((x) >> 12) & 0x1)
+#define   C_000E40_CPRQ_IN_RTBUF                       0xFFFFEFFF
+#define   S_000E40_CFRQ_IN_RTBUF(x)                    (((x) & 0x1) << 13)
+#define   G_000E40_CFRQ_IN_RTBUF(x)                    (((x) >> 13) & 0x1)
+#define   C_000E40_CFRQ_IN_RTBUF                       0xFFFFDFFF
+#define   S_000E40_CF_PIPE_BUSY(x)                     (((x) & 0x1) << 14)
+#define   G_000E40_CF_PIPE_BUSY(x)                     (((x) >> 14) & 0x1)
+#define   C_000E40_CF_PIPE_BUSY                        0xFFFFBFFF
+#define   S_000E40_ENG_EV_BUSY(x)                      (((x) & 0x1) << 15)
+#define   G_000E40_ENG_EV_BUSY(x)                      (((x) >> 15) & 0x1)
+#define   C_000E40_ENG_EV_BUSY                         0xFFFF7FFF
+#define   S_000E40_CP_CMDSTRM_BUSY(x)                  (((x) & 0x1) << 16)
+#define   G_000E40_CP_CMDSTRM_BUSY(x)                  (((x) >> 16) & 0x1)
+#define   C_000E40_CP_CMDSTRM_BUSY                     0xFFFEFFFF
+#define   S_000E40_E2_BUSY(x)                          (((x) & 0x1) << 17)
+#define   G_000E40_E2_BUSY(x)                          (((x) >> 17) & 0x1)
+#define   C_000E40_E2_BUSY                             0xFFFDFFFF
+#define   S_000E40_RB2D_BUSY(x)                        (((x) & 0x1) << 18)
+#define   G_000E40_RB2D_BUSY(x)                        (((x) >> 18) & 0x1)
+#define   C_000E40_RB2D_BUSY                           0xFFFBFFFF
+#define   S_000E40_RB3D_BUSY(x)                        (((x) & 0x1) << 19)
+#define   G_000E40_RB3D_BUSY(x)                        (((x) >> 19) & 0x1)
+#define   C_000E40_RB3D_BUSY                           0xFFF7FFFF
+#define   S_000E40_VAP_BUSY(x)                         (((x) & 0x1) << 20)
+#define   G_000E40_VAP_BUSY(x)                         (((x) >> 20) & 0x1)
+#define   C_000E40_VAP_BUSY                            0xFFEFFFFF
+#define   S_000E40_RE_BUSY(x)                          (((x) & 0x1) << 21)
+#define   G_000E40_RE_BUSY(x)                          (((x) >> 21) & 0x1)
+#define   C_000E40_RE_BUSY                             0xFFDFFFFF
+#define   S_000E40_TAM_BUSY(x)                         (((x) & 0x1) << 22)
+#define   G_000E40_TAM_BUSY(x)                         (((x) >> 22) & 0x1)
+#define   C_000E40_TAM_BUSY                            0xFFBFFFFF
+#define   S_000E40_TDM_BUSY(x)                         (((x) & 0x1) << 23)
+#define   G_000E40_TDM_BUSY(x)                         (((x) >> 23) & 0x1)
+#define   C_000E40_TDM_BUSY                            0xFF7FFFFF
+#define   S_000E40_PB_BUSY(x)                          (((x) & 0x1) << 24)
+#define   G_000E40_PB_BUSY(x)                          (((x) >> 24) & 0x1)
+#define   C_000E40_PB_BUSY                             0xFEFFFFFF
+#define   S_000E40_TIM_BUSY(x)                         (((x) & 0x1) << 25)
+#define   G_000E40_TIM_BUSY(x)                         (((x) >> 25) & 0x1)
+#define   C_000E40_TIM_BUSY                            0xFDFFFFFF
+#define   S_000E40_GA_BUSY(x)                          (((x) & 0x1) << 26)
+#define   G_000E40_GA_BUSY(x)                          (((x) >> 26) & 0x1)
+#define   C_000E40_GA_BUSY                             0xFBFFFFFF
+#define   S_000E40_CBA2D_BUSY(x)                       (((x) & 0x1) << 27)
+#define   G_000E40_CBA2D_BUSY(x)                       (((x) >> 27) & 0x1)
+#define   C_000E40_CBA2D_BUSY                          0xF7FFFFFF
+#define   S_000E40_GUI_ACTIVE(x)                       (((x) & 0x1) << 31)
+#define   G_000E40_GUI_ACTIVE(x)                       (((x) >> 31) & 0x1)
+#define   C_000E40_GUI_ACTIVE                          0x7FFFFFFF
+
+/* CLK registers */
+#define R_00000D_SCLK_CNTL                           0x00000D
+#define   S_00000D_SCLK_SRC_SEL(x)                     (((x) & 0x7) << 0)
+#define   G_00000D_SCLK_SRC_SEL(x)                     (((x) >> 0) & 0x7)
+#define   C_00000D_SCLK_SRC_SEL                        0xFFFFFFF8
+#define   S_00000D_CP_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 3)
+#define   G_00000D_CP_MAX_DYN_STOP_LAT(x)              (((x) >> 3) & 0x1)
+#define   C_00000D_CP_MAX_DYN_STOP_LAT                 0xFFFFFFF7
+#define   S_00000D_HDP_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 4)
+#define   G_00000D_HDP_MAX_DYN_STOP_LAT(x)             (((x) >> 4) & 0x1)
+#define   C_00000D_HDP_MAX_DYN_STOP_LAT                0xFFFFFFEF
+#define   S_00000D_TV_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 5)
+#define   G_00000D_TV_MAX_DYN_STOP_LAT(x)              (((x) >> 5) & 0x1)
+#define   C_00000D_TV_MAX_DYN_STOP_LAT                 0xFFFFFFDF
+#define   S_00000D_E2_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 6)
+#define   G_00000D_E2_MAX_DYN_STOP_LAT(x)              (((x) >> 6) & 0x1)
+#define   C_00000D_E2_MAX_DYN_STOP_LAT                 0xFFFFFFBF
+#define   S_00000D_SE_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 7)
+#define   G_00000D_SE_MAX_DYN_STOP_LAT(x)              (((x) >> 7) & 0x1)
+#define   C_00000D_SE_MAX_DYN_STOP_LAT                 0xFFFFFF7F
+#define   S_00000D_IDCT_MAX_DYN_STOP_LAT(x)            (((x) & 0x1) << 8)
+#define   G_00000D_IDCT_MAX_DYN_STOP_LAT(x)            (((x) >> 8) & 0x1)
+#define   C_00000D_IDCT_MAX_DYN_STOP_LAT               0xFFFFFEFF
+#define   S_00000D_VIP_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 9)
+#define   G_00000D_VIP_MAX_DYN_STOP_LAT(x)             (((x) >> 9) & 0x1)
+#define   C_00000D_VIP_MAX_DYN_STOP_LAT                0xFFFFFDFF
+#define   S_00000D_RE_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 10)
+#define   G_00000D_RE_MAX_DYN_STOP_LAT(x)              (((x) >> 10) & 0x1)
+#define   C_00000D_RE_MAX_DYN_STOP_LAT                 0xFFFFFBFF
+#define   S_00000D_PB_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 11)
+#define   G_00000D_PB_MAX_DYN_STOP_LAT(x)              (((x) >> 11) & 0x1)
+#define   C_00000D_PB_MAX_DYN_STOP_LAT                 0xFFFFF7FF
+#define   S_00000D_TAM_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 12)
+#define   G_00000D_TAM_MAX_DYN_STOP_LAT(x)             (((x) >> 12) & 0x1)
+#define   C_00000D_TAM_MAX_DYN_STOP_LAT                0xFFFFEFFF
+#define   S_00000D_TDM_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 13)
+#define   G_00000D_TDM_MAX_DYN_STOP_LAT(x)             (((x) >> 13) & 0x1)
+#define   C_00000D_TDM_MAX_DYN_STOP_LAT                0xFFFFDFFF
+#define   S_00000D_RB_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 14)
+#define   G_00000D_RB_MAX_DYN_STOP_LAT(x)              (((x) >> 14) & 0x1)
+#define   C_00000D_RB_MAX_DYN_STOP_LAT                 0xFFFFBFFF
+#define   S_00000D_FORCE_DISP2(x)                      (((x) & 0x1) << 15)
+#define   G_00000D_FORCE_DISP2(x)                      (((x) >> 15) & 0x1)
+#define   C_00000D_FORCE_DISP2                         0xFFFF7FFF
+#define   S_00000D_FORCE_CP(x)                         (((x) & 0x1) << 16)
+#define   G_00000D_FORCE_CP(x)                         (((x) >> 16) & 0x1)
+#define   C_00000D_FORCE_CP                            0xFFFEFFFF
+#define   S_00000D_FORCE_HDP(x)                        (((x) & 0x1) << 17)
+#define   G_00000D_FORCE_HDP(x)                        (((x) >> 17) & 0x1)
+#define   C_00000D_FORCE_HDP                           0xFFFDFFFF
+#define   S_00000D_FORCE_DISP1(x)                      (((x) & 0x1) << 18)
+#define   G_00000D_FORCE_DISP1(x)                      (((x) >> 18) & 0x1)
+#define   C_00000D_FORCE_DISP1                         0xFFFBFFFF
+#define   S_00000D_FORCE_TOP(x)                        (((x) & 0x1) << 19)
+#define   G_00000D_FORCE_TOP(x)                        (((x) >> 19) & 0x1)
+#define   C_00000D_FORCE_TOP                           0xFFF7FFFF
+#define   S_00000D_FORCE_E2(x)                         (((x) & 0x1) << 20)
+#define   G_00000D_FORCE_E2(x)                         (((x) >> 20) & 0x1)
+#define   C_00000D_FORCE_E2                            0xFFEFFFFF
+#define   S_00000D_FORCE_SE(x)                         (((x) & 0x1) << 21)
+#define   G_00000D_FORCE_SE(x)                         (((x) >> 21) & 0x1)
+#define   C_00000D_FORCE_SE                            0xFFDFFFFF
+#define   S_00000D_FORCE_IDCT(x)                       (((x) & 0x1) << 22)
+#define   G_00000D_FORCE_IDCT(x)                       (((x) >> 22) & 0x1)
+#define   C_00000D_FORCE_IDCT                          0xFFBFFFFF
+#define   S_00000D_FORCE_VIP(x)                        (((x) & 0x1) << 23)
+#define   G_00000D_FORCE_VIP(x)                        (((x) >> 23) & 0x1)
+#define   C_00000D_FORCE_VIP                           0xFF7FFFFF
+#define   S_00000D_FORCE_RE(x)                         (((x) & 0x1) << 24)
+#define   G_00000D_FORCE_RE(x)                         (((x) >> 24) & 0x1)
+#define   C_00000D_FORCE_RE                            0xFEFFFFFF
+#define   S_00000D_FORCE_PB(x)                         (((x) & 0x1) << 25)
+#define   G_00000D_FORCE_PB(x)                         (((x) >> 25) & 0x1)
+#define   C_00000D_FORCE_PB                            0xFDFFFFFF
+#define   S_00000D_FORCE_PX(x)                         (((x) & 0x1) << 26)
+#define   G_00000D_FORCE_PX(x)                         (((x) >> 26) & 0x1)
+#define   C_00000D_FORCE_PX                            0xFBFFFFFF
+#define   S_00000D_FORCE_TX(x)                         (((x) & 0x1) << 27)
+#define   G_00000D_FORCE_TX(x)                         (((x) >> 27) & 0x1)
+#define   C_00000D_FORCE_TX                            0xF7FFFFFF
+#define   S_00000D_FORCE_RB(x)                         (((x) & 0x1) << 28)
+#define   G_00000D_FORCE_RB(x)                         (((x) >> 28) & 0x1)
+#define   C_00000D_FORCE_RB                            0xEFFFFFFF
+#define   S_00000D_FORCE_TV_SCLK(x)                    (((x) & 0x1) << 29)
+#define   G_00000D_FORCE_TV_SCLK(x)                    (((x) >> 29) & 0x1)
+#define   C_00000D_FORCE_TV_SCLK                       0xDFFFFFFF
+#define   S_00000D_FORCE_SUBPIC(x)                     (((x) & 0x1) << 30)
+#define   G_00000D_FORCE_SUBPIC(x)                     (((x) >> 30) & 0x1)
+#define   C_00000D_FORCE_SUBPIC                        0xBFFFFFFF
+#define   S_00000D_FORCE_OV0(x)                        (((x) & 0x1) << 31)
+#define   G_00000D_FORCE_OV0(x)                        (((x) >> 31) & 0x1)
+#define   C_00000D_FORCE_OV0                           0x7FFFFFFF
 
 #endif
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 23ede0e4783..e314756dacc 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -690,6 +690,7 @@ typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
 
 struct radeon_device {
+	struct device			*dev;
 	struct drm_device		*ddev;
 	struct pci_dev			*pdev;
 	/* ASIC */
@@ -936,16 +937,45 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
 /* Common functions */
 int radeon_modeset_init(struct radeon_device *rdev);
 void radeon_modeset_fini(struct radeon_device *rdev);
+extern bool radeon_card_posted(struct radeon_device *rdev);
 
 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
-void r100_cp_disable(struct radeon_device *rdev);
+struct r100_mc_save {
+	u32	GENMO_WT;
+	u32	CRTC_EXT_CNTL;
+	u32	CRTC_GEN_CNTL;
+	u32	CRTC2_GEN_CNTL;
+	u32	CUR_OFFSET;
+	u32	CUR2_OFFSET;
+};
+extern void r100_cp_disable(struct radeon_device *rdev);
+extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
+extern void r100_cp_fini(struct radeon_device *rdev);
 void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
 int r100_pci_gart_enable(struct radeon_device *rdev);
 void r100_pci_gart_disable(struct radeon_device *rdev);
 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
+extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
+extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
+extern void r100_ib_fini(struct radeon_device *rdev);
+extern int r100_ib_init(struct radeon_device *rdev);
+extern void r100_irq_disable(struct radeon_device *rdev);
+extern int r100_irq_set(struct radeon_device *rdev);
+extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
+extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
+extern void r100_wb_disable(struct radeon_device *rdev);
+extern void r100_wb_fini(struct radeon_device *rdev);
+extern int r100_wb_init(struct radeon_device *rdev);
+
+/* r300,r350,rv350,rv370,rv380 */
+extern void r300_set_reg_safe(struct radeon_device *rdev);
+extern void r300_mc_program(struct radeon_device *rdev);
+extern void r300_vram_info(struct radeon_device *rdev);
+extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
 
 /* r420,r423,rv410 */
 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
+extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
 
 #endif
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index f9c8f9a041d..8f27be31e09 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -189,31 +189,34 @@ static struct radeon_asic r300_asic = {
 /*
  * r420,r423,rv410
  */
-void r420_errata(struct radeon_device *rdev);
-void r420_vram_info(struct radeon_device *rdev);
-int r420_mc_init(struct radeon_device *rdev);
-void r420_mc_fini(struct radeon_device *rdev);
+extern int r420_init(struct radeon_device *rdev);
+extern void r420_fini(struct radeon_device *rdev);
+extern int r420_suspend(struct radeon_device *rdev);
+extern int r420_resume(struct radeon_device *rdev);
 static struct radeon_asic r420_asic = {
-	.init = &r300_init,
-	.errata = &r420_errata,
-	.vram_info = &r420_vram_info,
+	.init = &r420_init,
+	.fini = &r420_fini,
+	.suspend = &r420_suspend,
+	.resume = &r420_resume,
+	.errata = NULL,
+	.vram_info = NULL,
 	.gpu_reset = &r300_gpu_reset,
-	.mc_init = &r420_mc_init,
-	.mc_fini = &r420_mc_fini,
-	.wb_init = &r100_wb_init,
-	.wb_fini = &r100_wb_fini,
+	.mc_init = NULL,
+	.mc_fini = NULL,
+	.wb_init = NULL,
+	.wb_fini = NULL,
 	.gart_enable = &r300_gart_enable,
 	.gart_disable = &rv370_pcie_gart_disable,
 	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 	.gart_set_page = &rv370_pcie_gart_set_page,
-	.cp_init = &r100_cp_init,
-	.cp_fini = &r100_cp_fini,
-	.cp_disable = &r100_cp_disable,
+	.cp_init = NULL,
+	.cp_fini = NULL,
+	.cp_disable = NULL,
 	.cp_commit = &r100_cp_commit,
 	.ring_start = &r300_ring_start,
 	.ring_test = &r100_ring_test,
 	.ring_ib_execute = &r100_ring_ib_execute,
-	.ib_test = &r100_ib_test,
+	.ib_test = NULL,
 	.irq_set = &r100_irq_set,
 	.irq_process = &r100_irq_process,
 	.get_vblank_counter = &r100_get_vblank_counter,
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 72f6262ea73..633acf71400 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -156,6 +156,10 @@ int radeon_mc_setup(struct radeon_device *rdev)
 		tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
 		rdev->mc.gtt_location = tmp;
 	}
+	rdev->mc.vram_start = rdev->mc.vram_location;
+	rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
+	rdev->mc.gtt_start = rdev->mc.gtt_location;
+	rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
 	DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
 	DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
 		 (unsigned)rdev->mc.vram_location,
@@ -171,7 +175,7 @@ int radeon_mc_setup(struct radeon_device *rdev)
 /*
  * GPU helpers function.
  */
-static bool radeon_card_posted(struct radeon_device *rdev)
+bool radeon_card_posted(struct radeon_device *rdev)
 {
 	uint32_t reg;
 
@@ -483,6 +487,7 @@ int radeon_device_init(struct radeon_device *rdev,
 
 	DRM_INFO("radeon: Initializing kernel modesetting.\n");
 	rdev->shutdown = false;
+	rdev->dev = &pdev->dev;
 	rdev->ddev = ddev;
 	rdev->pdev = pdev;
 	rdev->flags = flags;
@@ -497,6 +502,7 @@ int radeon_device_init(struct radeon_device *rdev,
 	mutex_init(&rdev->ib_pool.mutex);
 	mutex_init(&rdev->cp.mutex);
 	rwlock_init(&rdev->fence_drv.lock);
+	INIT_LIST_HEAD(&rdev->gem.objects);
 
 	if (radeon_agpmode == -1) {
 		rdev->flags &= ~RADEON_IS_AGP;
@@ -736,15 +742,14 @@ int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
 	if (!rdev->new_init_path) {
 		radeon_cp_disable(rdev);
 		radeon_gart_disable(rdev);
+		rdev->irq.sw_int = false;
+		radeon_irq_set(rdev);
 	} else {
 		radeon_suspend(rdev);
 	}
 	/* evict remaining vram memory */
 	radeon_object_evict_vram(rdev);
 
-	rdev->irq.sw_int = false;
-	radeon_irq_set(rdev);
-
 	pci_save_state(dev->pdev);
 	if (state.event == PM_EVENT_SUSPEND) {
 		/* Shut down the device */
@@ -771,10 +776,10 @@ int radeon_resume_kms(struct drm_device *dev)
 	}
 	pci_set_master(dev->pdev);
 	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
-	if (radeon_gpu_reset(rdev)) {
-		/* FIXME: what do we want to do here ? */
-	}
 	if (!rdev->new_init_path) {
+		if (radeon_gpu_reset(rdev)) {
+			/* FIXME: what do we want to do here ? */
+		}
 		/* post card */
 		if (rdev->is_atom_bios) {
 			atom_asic_init(rdev->mode_info.atom_context);
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index aa9837a6aa7..168a555d6fb 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -151,6 +151,8 @@ int radeon_ib_pool_init(struct radeon_device *rdev)
 	int i;
 	int r = 0;
 
+	if (rdev->ib_pool.robj)
+		return 0;
 	/* Allocate 1M object buffer */
 	INIT_LIST_HEAD(&rdev->ib_pool.scheduled_ibs);
 	r = radeon_object_create(rdev, NULL,  RADEON_IB_POOL_SIZE*64*1024,
-- 
cgit v1.2.3


From a4d68279b44522a2b2374a6bd4861756bfad40fe Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Fri, 11 Sep 2009 13:00:43 +0200
Subject: drm/radeon/kms: move mtrr range add and memory information

Move mtrr range and memory information printing to radeon_object_init,
this are memory information and initialization common to all GPU and
they better fit in this function. Will also prevent code duplication
with upcoming init path changes.

airlied: fixed warning introduced

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/radeon_device.c | 8 --------
 drivers/gpu/drm/radeon/radeon_object.c | 8 ++++++++
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 633acf71400..ece097c3e07 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -604,14 +604,6 @@ int radeon_device_init(struct radeon_device *rdev,
 		/* Get vram informations */
 		radeon_vram_info(rdev);
 
-		/* Add an MTRR for the VRAM */
-		rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
-				MTRR_TYPE_WRCOMB, 1);
-		DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n",
-				(unsigned)(rdev->mc.mc_vram_size >> 20),
-				(unsigned)(rdev->mc.aper_size >> 20));
-		DRM_INFO("RAM width %dbits %cDR\n",
-				rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
 		/* Initialize memory controller (also test AGP) */
 		r = radeon_mc_init(rdev);
 		if (r) {
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index b85fb83d7ae..1500d5bc7af 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -369,6 +369,14 @@ void radeon_object_force_delete(struct radeon_device *rdev)
 
 int radeon_object_init(struct radeon_device *rdev)
 {
+	/* Add an MTRR for the VRAM */
+	rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
+			MTRR_TYPE_WRCOMB, 1);
+	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
+		rdev->mc.mc_vram_size >> 20,
+		(unsigned long long)rdev->mc.aper_size >> 20);
+	DRM_INFO("RAM width %dbits %cDR\n",
+			rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
 	return radeon_ttm_init(rdev);
 }
 
-- 
cgit v1.2.3


From 21f9a437222e92adb3abc68584a5f04801b92739 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Fri, 11 Sep 2009 15:55:33 +0200
Subject: drm/radeon/kms: cleanup - remove radeon_share.h

radeon_share.h was begining to give problem with include order in
respect of radeon.h. It's easier and also i think cleaner to move
what was in radeon_share.h into radeon.h. At the same time use the
extern keyword for function shared accross the module.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/r300.c         |   1 -
 drivers/gpu/drm/radeon/r520.c         |   1 -
 drivers/gpu/drm/radeon/r600.c         |   1 -
 drivers/gpu/drm/radeon/r600_cs.c      |   1 -
 drivers/gpu/drm/radeon/radeon.h       |  93 ++++++++++++++++++++++++---
 drivers/gpu/drm/radeon/radeon_share.h | 116 ----------------------------------
 drivers/gpu/drm/radeon/rs400.c        |   1 -
 drivers/gpu/drm/radeon/rv515.c        |   1 -
 drivers/gpu/drm/radeon/rv770.c        |   1 -
 9 files changed, 84 insertions(+), 132 deletions(-)
 delete mode 100644 drivers/gpu/drm/radeon/radeon_share.h

diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 92f9cb74a7d..ced3322bd5f 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -31,7 +31,6 @@
 #include "radeon_reg.h"
 #include "radeon.h"
 #include "radeon_drm.h"
-#include "radeon_share.h"
 #include "r100_track.h"
 #include "r300d.h"
 
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index ebd6b0f7bdf..0e1686d1c87 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -28,7 +28,6 @@
 #include "drmP.h"
 #include "radeon_reg.h"
 #include "radeon.h"
-#include "radeon_share.h"
 
 /* r520,rv530,rv560,rv570,r580 depends on : */
 void r100_hdp_reset(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index d8fcef44a69..1bc25678986 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -32,7 +32,6 @@
 #include "radeon_drm.h"
 #include "radeon.h"
 #include "radeon_mode.h"
-#include "radeon_share.h"
 #include "r600d.h"
 #include "avivod.h"
 #include "atom.h"
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 39bf6349351..33b89cd8743 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -27,7 +27,6 @@
  */
 #include "drmP.h"
 #include "radeon.h"
-#include "radeon_share.h"
 #include "r600d.h"
 #include "avivod.h"
 
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index e314756dacc..8cec5bf2922 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -50,7 +50,6 @@
 #include <linux/kref.h>
 
 #include "radeon_mode.h"
-#include "radeon_share.h"
 #include "radeon_reg.h"
 
 /*
@@ -640,11 +639,55 @@ struct radeon_asic {
 	void (*bandwidth_update)(struct radeon_device *rdev);
 };
 
+/*
+ * Asic structures
+ */
 struct r100_asic {
 	const unsigned	*reg_safe_bm;
 	unsigned	reg_safe_bm_size;
 };
 
+struct r300_asic {
+	const unsigned	*reg_safe_bm;
+	unsigned	reg_safe_bm_size;
+};
+
+struct r600_asic {
+	unsigned max_pipes;
+	unsigned max_tile_pipes;
+	unsigned max_simds;
+	unsigned max_backends;
+	unsigned max_gprs;
+	unsigned max_threads;
+	unsigned max_stack_entries;
+	unsigned max_hw_contexts;
+	unsigned max_gs_threads;
+	unsigned sx_max_export_size;
+	unsigned sx_max_export_pos_size;
+	unsigned sx_max_export_smx_size;
+	unsigned sq_num_cf_insts;
+};
+
+struct rv770_asic {
+	unsigned max_pipes;
+	unsigned max_tile_pipes;
+	unsigned max_simds;
+	unsigned max_backends;
+	unsigned max_gprs;
+	unsigned max_threads;
+	unsigned max_stack_entries;
+	unsigned max_hw_contexts;
+	unsigned max_gs_threads;
+	unsigned sx_max_export_size;
+	unsigned sx_max_export_pos_size;
+	unsigned sx_max_export_smx_size;
+	unsigned sq_num_cf_insts;
+	unsigned sx_num_of_sets;
+	unsigned sc_prim_fifo_size;
+	unsigned sc_hiz_tile_fifo_size;
+	unsigned sc_earlyz_tile_fifo_fize;
+};
+
 union radeon_asic_config {
 	struct r300_asic	r300;
 	struct r100_asic	r100;
@@ -935,9 +978,14 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
 
 /* Common functions */
-int radeon_modeset_init(struct radeon_device *rdev);
-void radeon_modeset_fini(struct radeon_device *rdev);
+extern int radeon_modeset_init(struct radeon_device *rdev);
+extern void radeon_modeset_fini(struct radeon_device *rdev);
 extern bool radeon_card_posted(struct radeon_device *rdev);
+extern int radeon_clocks_init(struct radeon_device *rdev);
+extern void radeon_clocks_fini(struct radeon_device *rdev);
+extern void radeon_scratch_init(struct radeon_device *rdev);
+extern void radeon_surface_init(struct radeon_device *rdev);
+extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
 
 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
 struct r100_mc_save {
@@ -951,10 +999,10 @@ struct r100_mc_save {
 extern void r100_cp_disable(struct radeon_device *rdev);
 extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
 extern void r100_cp_fini(struct radeon_device *rdev);
-void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
-int r100_pci_gart_enable(struct radeon_device *rdev);
-void r100_pci_gart_disable(struct radeon_device *rdev);
-int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
+extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
+extern int r100_pci_gart_enable(struct radeon_device *rdev);
+extern void r100_pci_gart_disable(struct radeon_device *rdev);
+extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
 extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
 extern void r100_ib_fini(struct radeon_device *rdev);
@@ -963,6 +1011,7 @@ extern void r100_irq_disable(struct radeon_device *rdev);
 extern int r100_irq_set(struct radeon_device *rdev);
 extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
 extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
+extern void r100_vram_init_sizes(struct radeon_device *rdev);
 extern void r100_wb_disable(struct radeon_device *rdev);
 extern void r100_wb_fini(struct radeon_device *rdev);
 extern int r100_wb_init(struct radeon_device *rdev);
@@ -974,8 +1023,34 @@ extern void r300_vram_info(struct radeon_device *rdev);
 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
 
 /* r420,r423,rv410 */
-u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
-void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
+extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
+extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
 
+/* rv515 */
+extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
+
+/* rs690, rs740 */
+extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
+					struct drm_display_mode *mode1,
+					struct drm_display_mode *mode2);
+
+/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
+extern bool r600_card_posted(struct radeon_device *rdev);
+extern void r600_cp_stop(struct radeon_device *rdev);
+extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
+extern int r600_cp_resume(struct radeon_device *rdev);
+extern int r600_count_pipe_bits(uint32_t val);
+extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
+extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
+extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
+extern int r600_ib_test(struct radeon_device *rdev);
+extern int r600_ring_test(struct radeon_device *rdev);
+extern int r600_wb_init(struct radeon_device *rdev);
+extern void r600_wb_fini(struct radeon_device *rdev);
+extern void r600_scratch_init(struct radeon_device *rdev);
+extern int r600_blit_init(struct radeon_device *rdev);
+extern void r600_blit_fini(struct radeon_device *rdev);
+extern int r600_cp_init_microcode(struct radeon_device *rdev);
+
 #endif
diff --git a/drivers/gpu/drm/radeon/radeon_share.h b/drivers/gpu/drm/radeon/radeon_share.h
deleted file mode 100644
index 5f9e358ab50..00000000000
--- a/drivers/gpu/drm/radeon/radeon_share.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * Copyright 2008 Advanced Micro Devices, Inc.
- * Copyright 2008 Red Hat Inc.
- * Copyright 2009 Jerome Glisse.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- *          Alex Deucher
- *          Jerome Glisse
- */
-#ifndef __RADEON_SHARE_H__
-#define __RADEON_SHARE_H__
-
-/* Common */
-struct radeon_device;
-struct radeon_cs_parser;
-int radeon_clocks_init(struct radeon_device *rdev);
-void radeon_clocks_fini(struct radeon_device *rdev);
-void radeon_scratch_init(struct radeon_device *rdev);
-void radeon_surface_init(struct radeon_device *rdev);
-int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
-
-
-/* R100, RV100, RS100, RV200, RS200, R200, RV250, RS300, RV280 */
-void r100_vram_init_sizes(struct radeon_device *rdev);
-
-
-/* R300, R350, RV350, RV380 */
-struct r300_asic {
-	const unsigned	*reg_safe_bm;
-	unsigned	reg_safe_bm_size;
-};
-
-
-/* RS690, RS740 */
-void rs690_line_buffer_adjust(struct radeon_device *rdev,
-			      struct drm_display_mode *mode1,
-			      struct drm_display_mode *mode2);
-
-
-/* RV515 */
-void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
-
-
-/* R600, RV610, RV630, RV620, RV635, RV670, RS780, RS880 */
-bool r600_card_posted(struct radeon_device *rdev);
-void r600_cp_stop(struct radeon_device *rdev);
-void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
-int r600_cp_resume(struct radeon_device *rdev);
-int r600_count_pipe_bits(uint32_t val);
-int r600_gart_clear_page(struct radeon_device *rdev, int i);
-int r600_mc_wait_for_idle(struct radeon_device *rdev);
-void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
-int r600_ib_test(struct radeon_device *rdev);
-int r600_ring_test(struct radeon_device *rdev);
-int r600_wb_init(struct radeon_device *rdev);
-void r600_wb_fini(struct radeon_device *rdev);
-void r600_scratch_init(struct radeon_device *rdev);
-int r600_blit_init(struct radeon_device *rdev);
-void r600_blit_fini(struct radeon_device *rdev);
-int r600_cp_init_microcode(struct radeon_device *rdev);
-struct r600_asic {
-	unsigned max_pipes;
-	unsigned max_tile_pipes;
-	unsigned max_simds;
-	unsigned max_backends;
-	unsigned max_gprs;
-	unsigned max_threads;
-	unsigned max_stack_entries;
-	unsigned max_hw_contexts;
-	unsigned max_gs_threads;
-	unsigned sx_max_export_size;
-	unsigned sx_max_export_pos_size;
-	unsigned sx_max_export_smx_size;
-	unsigned sq_num_cf_insts;
-};
-
-/* RV770, RV7300, RV710 */
-struct rv770_asic {
-	unsigned max_pipes;
-	unsigned max_tile_pipes;
-	unsigned max_simds;
-	unsigned max_backends;
-	unsigned max_gprs;
-	unsigned max_threads;
-	unsigned max_stack_entries;
-	unsigned max_hw_contexts;
-	unsigned max_gs_threads;
-	unsigned sx_max_export_size;
-	unsigned sx_max_export_pos_size;
-	unsigned sx_max_export_smx_size;
-	unsigned sq_num_cf_insts;
-	unsigned sx_num_of_sets;
-	unsigned sc_prim_fifo_size;
-	unsigned sc_hiz_tile_fifo_size;
-	unsigned sc_earlyz_tile_fifo_fize;
-};
-
-#endif
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index 8c3ea7e3606..e1e4ce42782 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -29,7 +29,6 @@
 #include <drm/drmP.h>
 #include "radeon_reg.h"
 #include "radeon.h"
-#include "radeon_share.h"
 
 /* rs400,rs480 depends on : */
 void r100_hdp_reset(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 99e397f1638..03d490269ed 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -29,7 +29,6 @@
 #include "drmP.h"
 #include "rv515d.h"
 #include "radeon.h"
-#include "radeon_share.h"
 
 #include "rv515_reg_safe.h"
 /* rv515 depends on : */
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 57765f6d5b2..5ba5204091e 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -29,7 +29,6 @@
 #include <linux/platform_device.h>
 #include "drmP.h"
 #include "radeon.h"
-#include "radeon_share.h"
 #include "rv770d.h"
 #include "avivod.h"
 #include "atom.h"
-- 
cgit v1.2.3


From 4aac047323e3082d0866b8ad3784236632105af4 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Mon, 14 Sep 2009 18:29:49 +0200
Subject: drm/radeon/kms: clear confusion in GART init/deinit path

GART static one time initialization was mixed up with GART
enabling/disabling which could happen several time for instance
during suspend/resume cycles. This patch splits all GART
handling into 4 differents function. gart_init is for one
time initialization, gart_deinit is called upon module unload
to free resources allocated by gart_init, gart_enable enable
the GART and is intented to be call after first initialization
and at each resume cycle or reset cycle. Finaly gart_disable
stop the GART and is intended to be call at suspend time or
when unloading the module.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/r100.c          |  40 ++++++------
 drivers/gpu/drm/radeon/r300.c          | 108 ++++++++++++++-------------------
 drivers/gpu/drm/radeon/r420.c          |  57 ++++++++++-------
 drivers/gpu/drm/radeon/r520.c          |   5 --
 drivers/gpu/drm/radeon/r600.c          |  53 +++++++++++-----
 drivers/gpu/drm/radeon/radeon.h        |  11 ++++
 drivers/gpu/drm/radeon/radeon_asic.h   |  38 +++++++++---
 drivers/gpu/drm/radeon/radeon_device.c |  36 +++++++++--
 drivers/gpu/drm/radeon/radeon_gart.c   |   9 ++-
 drivers/gpu/drm/radeon/rs400.c         |  53 ++++++++++------
 drivers/gpu/drm/radeon/rs600.c         |  41 +++++++++----
 drivers/gpu/drm/radeon/rs690.c         |   3 -
 drivers/gpu/drm/radeon/rv515.c         |   5 --
 drivers/gpu/drm/radeon/rv770.c         |  37 ++++++-----
 14 files changed, 306 insertions(+), 190 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 47263d3ede9..fa0fdc1e345 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -84,23 +84,28 @@ void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 	 * could end up in wrong address. */
 }
 
-int r100_pci_gart_enable(struct radeon_device *rdev)
+int r100_pci_gart_init(struct radeon_device *rdev)
 {
-	uint32_t tmp;
 	int r;
 
+	if (rdev->gart.table.ram.ptr) {
+		WARN(1, "R100 PCI GART already initialized.\n");
+		return 0;
+	}
 	/* Initialize common gart structure */
 	r = radeon_gart_init(rdev);
-	if (r) {
+	if (r)
 		return r;
-	}
-	if (rdev->gart.table.ram.ptr == NULL) {
-		rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
-		r = radeon_gart_table_ram_alloc(rdev);
-		if (r) {
-			return r;
-		}
-	}
+	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
+	rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
+	rdev->asic->gart_set_page = &r100_pci_gart_set_page;
+	return radeon_gart_table_ram_alloc(rdev);
+}
+
+int r100_pci_gart_enable(struct radeon_device *rdev)
+{
+	uint32_t tmp;
+
 	/* discard memory request outside of configured range */
 	tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 	WREG32(RADEON_AIC_CNTL, tmp);
@@ -140,13 +145,11 @@ int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 	return 0;
 }
 
-int r100_gart_enable(struct radeon_device *rdev)
+void r100_pci_gart_fini(struct radeon_device *rdev)
 {
-	if (rdev->flags & RADEON_IS_AGP) {
-		r100_pci_gart_disable(rdev);
-		return 0;
-	}
-	return r100_pci_gart_enable(rdev);
+	r100_pci_gart_disable(rdev);
+	radeon_gart_table_ram_free(rdev);
+	radeon_gart_fini(rdev);
 }
 
 
@@ -273,9 +276,6 @@ int r100_mc_init(struct radeon_device *rdev)
 
 void r100_mc_fini(struct radeon_device *rdev)
 {
-	r100_pci_gart_disable(rdev);
-	radeon_gart_table_ram_free(rdev);
-	radeon_gart_fini(rdev);
 }
 
 
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index ced3322bd5f..bb151ecdf8f 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -42,7 +42,6 @@ int r100_cp_reset(struct radeon_device *rdev);
 int r100_rb2d_reset(struct radeon_device *rdev);
 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
 int r100_pci_gart_enable(struct radeon_device *rdev);
-void r100_pci_gart_disable(struct radeon_device *rdev);
 void r100_mc_setup(struct radeon_device *rdev);
 void r100_mc_disable_clients(struct radeon_device *rdev);
 int r100_gui_wait_for_idle(struct radeon_device *rdev);
@@ -86,26 +85,57 @@ void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
 	mb();
 }
 
-int rv370_pcie_gart_enable(struct radeon_device *rdev)
+int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
+{
+	void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
+
+	if (i < 0 || i > rdev->gart.num_gpu_pages) {
+		return -EINVAL;
+	}
+	addr = (lower_32_bits(addr) >> 8) |
+	       ((upper_32_bits(addr) & 0xff) << 24) |
+	       0xc;
+	/* on x86 we want this to be CPU endian, on powerpc
+	 * on powerpc without HW swappers, it'll get swapped on way
+	 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
+	writel(addr, ((void __iomem *)ptr) + (i * 4));
+	return 0;
+}
+
+int rv370_pcie_gart_init(struct radeon_device *rdev)
 {
-	uint32_t table_addr;
-	uint32_t tmp;
 	int r;
 
+	if (rdev->gart.table.vram.robj) {
+		WARN(1, "RV370 PCIE GART already initialized.\n");
+		return 0;
+	}
 	/* Initialize common gart structure */
 	r = radeon_gart_init(rdev);
-	if (r) {
+	if (r)
 		return r;
-	}
 	r = rv370_debugfs_pcie_gart_info_init(rdev);
-	if (r) {
+	if (r)
 		DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
-	}
 	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
-	r = radeon_gart_table_vram_alloc(rdev);
-	if (r) {
-		return r;
+	rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
+	rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
+	return radeon_gart_table_vram_alloc(rdev);
+}
+
+int rv370_pcie_gart_enable(struct radeon_device *rdev)
+{
+	uint32_t table_addr;
+	uint32_t tmp;
+	int r;
+
+	if (rdev->gart.table.vram.robj == NULL) {
+		dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
+		return -EINVAL;
 	}
+	r = radeon_gart_table_vram_pin(rdev);
+	if (r)
+		return r;
 	/* discard memory request outside of configured range */
 	tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
@@ -145,51 +175,13 @@ void rv370_pcie_gart_disable(struct radeon_device *rdev)
 	}
 }
 
-int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
-{
-	void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
-
-	if (i < 0 || i > rdev->gart.num_gpu_pages) {
-		return -EINVAL;
-	}
-	addr = (lower_32_bits(addr) >> 8) |
-	       ((upper_32_bits(addr) & 0xff) << 24) |
-	       0xc;
-	/* on x86 we want this to be CPU endian, on powerpc
-	 * on powerpc without HW swappers, it'll get swapped on way
-	 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
-	writel(addr, ((void __iomem *)ptr) + (i * 4));
-	return 0;
-}
-
-int r300_gart_enable(struct radeon_device *rdev)
+void rv370_pcie_gart_fini(struct radeon_device *rdev)
 {
-#if __OS_HAS_AGP
-	if (rdev->flags & RADEON_IS_AGP) {
-		if (rdev->family > CHIP_RV350) {
-			rv370_pcie_gart_disable(rdev);
-		} else {
-			r100_pci_gart_disable(rdev);
-		}
-		return 0;
-	}
-#endif
-	if (rdev->flags & RADEON_IS_PCIE) {
-		rdev->asic->gart_disable = &rv370_pcie_gart_disable;
-		rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
-		rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
-		return rv370_pcie_gart_enable(rdev);
-	}
-	if (rdev->flags & RADEON_IS_PCI) {
-		rdev->asic->gart_disable = &r100_pci_gart_disable;
-		rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
-		rdev->asic->gart_set_page = &r100_pci_gart_set_page;
-		return r100_pci_gart_enable(rdev);
-	}
-	return r100_pci_gart_enable(rdev);
+	rv370_pcie_gart_disable(rdev);
+	radeon_gart_table_vram_free(rdev);
+	radeon_gart_fini(rdev);
 }
 
-
 /*
  * MC
  */
@@ -237,14 +229,6 @@ int r300_mc_init(struct radeon_device *rdev)
 
 void r300_mc_fini(struct radeon_device *rdev)
 {
-	if (rdev->flags & RADEON_IS_PCIE) {
-		rv370_pcie_gart_disable(rdev);
-		radeon_gart_table_vram_free(rdev);
-	} else {
-		r100_pci_gart_disable(rdev);
-		radeon_gart_table_ram_free(rdev);
-	}
-	radeon_gart_fini(rdev);
 }
 
 
@@ -1299,8 +1283,6 @@ void r300_mc_program(struct radeon_device *rdev)
 
 	/* Stops all mc clients */
 	r100_mc_stop(rdev, &save);
-	/* Shutdown PCI/PCIE GART */
-	radeon_gart_disable(rdev);
 	if (rdev->flags & RADEON_IS_AGP) {
 		WREG32(R_00014C_MC_AGP_LOCATION,
 			S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index e57b9ba4aaf..33a25a4377b 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -161,6 +161,11 @@ int r420_resume(struct radeon_device *rdev)
 {
 	int r;
 
+	/* Make sur GART are not working */
+	if (rdev->flags & RADEON_IS_PCIE)
+		rv370_pcie_gart_disable(rdev);
+	if (rdev->flags & RADEON_IS_PCI)
+		r100_pci_gart_disable(rdev);
 	/* Resume clock before doing reset */
 	r420_clock_resume(rdev);
 	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
@@ -180,10 +185,15 @@ int r420_resume(struct radeon_device *rdev)
 	r300_mc_program(rdev);
 	/* Initialize GART (initialize after TTM so we can allocate
 	 * memory through TTM but finalize after TTM) */
-	r = radeon_gart_enable(rdev);
-	if (r) {
-		dev_err(rdev->dev, "failled initializing GART (%d).\n", r);
-		return r;
+	if (rdev->flags & RADEON_IS_PCIE) {
+		r = rv370_pcie_gart_enable(rdev);
+		if (r)
+			return r;
+	}
+	if (rdev->flags & RADEON_IS_PCI) {
+		r = r100_pci_gart_enable(rdev);
+		if (r)
+			return r;
 	}
 	r420_pipes_init(rdev);
 	/* Enable IRQ */
@@ -212,7 +222,10 @@ int r420_suspend(struct radeon_device *rdev)
 	r100_cp_disable(rdev);
 	r100_wb_disable(rdev);
 	r100_irq_disable(rdev);
-	radeon_gart_disable(rdev);
+	if (rdev->flags & RADEON_IS_PCIE)
+		rv370_pcie_gart_disable(rdev);
+	if (rdev->flags & RADEON_IS_PCI)
+		r100_pci_gart_disable(rdev);
 	return 0;
 }
 
@@ -222,14 +235,10 @@ void r420_fini(struct radeon_device *rdev)
 	r100_wb_fini(rdev);
 	r100_ib_fini(rdev);
 	radeon_gem_fini(rdev);
-	if (rdev->flags & RADEON_IS_PCIE) {
-		rv370_pcie_gart_disable(rdev);
-		radeon_gart_table_vram_free(rdev);
-	} else {
-		r100_pci_gart_disable(rdev);
-		radeon_gart_table_ram_free(rdev);
-	}
-	radeon_gart_fini(rdev);
+	if (rdev->flags & RADEON_IS_PCIE)
+		rv370_pcie_gart_fini(rdev);
+	if (rdev->flags & RADEON_IS_PCI)
+		r100_pci_gart_fini(rdev);
 	radeon_agp_fini(rdev);
 	radeon_irq_kms_fini(rdev);
 	radeon_fence_driver_fini(rdev);
@@ -309,6 +318,16 @@ int r420_init(struct radeon_device *rdev)
 	if (r) {
 		return r;
 	}
+	if (rdev->flags & RADEON_IS_PCIE) {
+		r = rv370_pcie_gart_init(rdev);
+		if (r)
+			return r;
+	}
+	if (rdev->flags & RADEON_IS_PCI) {
+		r = r100_pci_gart_init(rdev);
+		if (r)
+			return r;
+	}
 	r300_set_reg_safe(rdev);
 	r = r420_resume(rdev);
 	if (r) {
@@ -318,14 +337,10 @@ int r420_init(struct radeon_device *rdev)
 		r100_cp_fini(rdev);
 		r100_wb_fini(rdev);
 		r100_ib_fini(rdev);
-		if (rdev->flags & RADEON_IS_PCIE) {
-			rv370_pcie_gart_disable(rdev);
-			radeon_gart_table_vram_free(rdev);
-		} else {
-			r100_pci_gart_disable(rdev);
-			radeon_gart_table_ram_free(rdev);
-		}
-		radeon_gart_fini(rdev);
+		if (rdev->flags & RADEON_IS_PCIE)
+			rv370_pcie_gart_fini(rdev);
+		if (rdev->flags & RADEON_IS_PCI)
+			r100_pci_gart_fini(rdev);
 		radeon_agp_fini(rdev);
 		radeon_irq_kms_fini(rdev);
 	}
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index 0e1686d1c87..d4b0b9d2e39 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -31,8 +31,6 @@
 
 /* r520,rv530,rv560,rv570,r580 depends on : */
 void r100_hdp_reset(struct radeon_device *rdev);
-int rv370_pcie_gart_enable(struct radeon_device *rdev);
-void rv370_pcie_gart_disable(struct radeon_device *rdev);
 void r420_pipes_init(struct radeon_device *rdev);
 void rs600_mc_disable_clients(struct radeon_device *rdev);
 void rs600_disable_vga(struct radeon_device *rdev);
@@ -118,9 +116,6 @@ int r520_mc_init(struct radeon_device *rdev)
 
 void r520_mc_fini(struct radeon_device *rdev)
 {
-	rv370_pcie_gart_disable(rdev);
-	radeon_gart_table_vram_free(rdev);
-	radeon_gart_fini(rdev);
 }
 
 
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 1bc25678986..65699e9f202 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -113,21 +113,34 @@ void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 	}
 }
 
-int r600_pcie_gart_enable(struct radeon_device *rdev)
+int r600_pcie_gart_init(struct radeon_device *rdev)
 {
-	u32 tmp;
-	int r, i;
+	int r;
 
+	if (rdev->gart.table.vram.robj) {
+		WARN(1, "R600 PCIE GART already initialized.\n");
+		return 0;
+	}
 	/* Initialize common gart structure */
 	r = radeon_gart_init(rdev);
-	if (r) {
+	if (r)
 		return r;
-	}
 	rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
-	r = radeon_gart_table_vram_alloc(rdev);
-	if (r) {
-		return r;
+	return radeon_gart_table_vram_alloc(rdev);
+}
+
+int r600_pcie_gart_enable(struct radeon_device *rdev)
+{
+	u32 tmp;
+	int r, i;
+
+	if (rdev->gart.table.vram.robj == NULL) {
+		dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
+		return -EINVAL;
 	}
+	r = radeon_gart_table_vram_pin(rdev);
+	if (r)
+		return r;
 	for (i = 0; i < rdev->gart.num_gpu_pages; i++)
 		r600_gart_clear_page(rdev, i);
 	/* Setup L2 cache */
@@ -175,10 +188,6 @@ void r600_pcie_gart_disable(struct radeon_device *rdev)
 	u32 tmp;
 	int i;
 
-	/* Clear ptes*/
-	for (i = 0; i < rdev->gart.num_gpu_pages; i++)
-		r600_gart_clear_page(rdev, i);
-	r600_pcie_gart_tlb_flush(rdev);
 	/* Disable all tables */
 	for (i = 0; i < 7; i++)
 		WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
@@ -204,6 +213,17 @@ void r600_pcie_gart_disable(struct radeon_device *rdev)
 	WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 	WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
 	WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
+	if (rdev->gart.table.vram.robj) {
+		radeon_object_kunmap(rdev->gart.table.vram.robj);
+		radeon_object_unpin(rdev->gart.table.vram.robj);
+	}
+}
+
+void r600_pcie_gart_fini(struct radeon_device *rdev)
+{
+	r600_pcie_gart_disable(rdev);
+	radeon_gart_table_vram_free(rdev);
+	radeon_gart_fini(rdev);
 }
 
 int r600_mc_wait_for_idle(struct radeon_device *rdev)
@@ -1472,6 +1492,7 @@ int r600_suspend(struct radeon_device *rdev)
 {
 	/* FIXME: we should wait for ring to be empty */
 	r600_cp_stop(rdev);
+	r600_pcie_gart_disable(rdev);
 	return 0;
 }
 
@@ -1548,6 +1569,10 @@ int r600_init(struct radeon_device *rdev)
 		}
 	}
 
+	r = r600_pcie_gart_init(rdev);
+	if (r)
+		return r;
+
 	r = r600_resume(rdev);
 	if (r) {
 		if (rdev->flags & RADEON_IS_AGP) {
@@ -1583,9 +1608,7 @@ void r600_fini(struct radeon_device *rdev)
 
 	r600_blit_fini(rdev);
 	radeon_ring_fini(rdev);
-	r600_pcie_gart_disable(rdev);
-	radeon_gart_table_vram_free(rdev);
-	radeon_gart_fini(rdev);
+	r600_pcie_gart_fini(rdev);
 	radeon_gem_fini(rdev);
 	radeon_fence_driver_fini(rdev);
 	radeon_clocks_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 8cec5bf2922..99292be8bc9 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -596,6 +596,8 @@ struct radeon_asic {
 	void (*mc_fini)(struct radeon_device *rdev);
 	int (*wb_init)(struct radeon_device *rdev);
 	void (*wb_fini)(struct radeon_device *rdev);
+	int (*gart_init)(struct radeon_device *rdev);
+	void (*gart_fini)(struct radeon_device *rdev);
 	int (*gart_enable)(struct radeon_device *rdev);
 	void (*gart_disable)(struct radeon_device *rdev);
 	void (*gart_tlb_flush)(struct radeon_device *rdev);
@@ -950,6 +952,8 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
 #define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
 #define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
 #define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
+#define radeon_gpu_gart_init(rdev) (rdev)->asic->gart_init((rdev))
+#define radeon_gpu_gart_fini(rdev) (rdev)->asic->gart_fini((rdev))
 #define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
 #define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
@@ -978,6 +982,7 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
 
 /* Common functions */
+extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
 extern int radeon_modeset_init(struct radeon_device *rdev);
 extern void radeon_modeset_fini(struct radeon_device *rdev);
 extern bool radeon_card_posted(struct radeon_device *rdev);
@@ -1000,6 +1005,8 @@ extern void r100_cp_disable(struct radeon_device *rdev);
 extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
 extern void r100_cp_fini(struct radeon_device *rdev);
 extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
+extern int r100_pci_gart_init(struct radeon_device *rdev);
+extern void r100_pci_gart_fini(struct radeon_device *rdev);
 extern int r100_pci_gart_enable(struct radeon_device *rdev);
 extern void r100_pci_gart_disable(struct radeon_device *rdev);
 extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
@@ -1020,6 +1027,9 @@ extern int r100_wb_init(struct radeon_device *rdev);
 extern void r300_set_reg_safe(struct radeon_device *rdev);
 extern void r300_mc_program(struct radeon_device *rdev);
 extern void r300_vram_info(struct radeon_device *rdev);
+extern int rv370_pcie_gart_init(struct radeon_device *rdev);
+extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
+extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
 
 /* r420,r423,rv410 */
@@ -1043,6 +1053,7 @@ extern int r600_cp_resume(struct radeon_device *rdev);
 extern int r600_count_pipe_bits(uint32_t val);
 extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
+extern int r600_pcie_gart_init(struct radeon_device *rdev);
 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
 extern int r600_ib_test(struct radeon_device *rdev);
 extern int r600_ring_test(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 8f27be31e09..5f2a9e6f12c 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -53,7 +53,9 @@ void r100_mc_fini(struct radeon_device *rdev);
 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
 int r100_wb_init(struct radeon_device *rdev);
 void r100_wb_fini(struct radeon_device *rdev);
-int r100_gart_enable(struct radeon_device *rdev);
+int r100_pci_gart_init(struct radeon_device *rdev);
+void r100_pci_gart_fini(struct radeon_device *rdev);
+int r100_pci_gart_enable(struct radeon_device *rdev);
 void r100_pci_gart_disable(struct radeon_device *rdev);
 void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
@@ -92,7 +94,9 @@ static struct radeon_asic r100_asic = {
 	.mc_fini = &r100_mc_fini,
 	.wb_init = &r100_wb_init,
 	.wb_fini = &r100_wb_fini,
-	.gart_enable = &r100_gart_enable,
+	.gart_init = &r100_pci_gart_init,
+	.gart_fini = &r100_pci_gart_fini,
+	.gart_enable = &r100_pci_gart_enable,
 	.gart_disable = &r100_pci_gart_disable,
 	.gart_tlb_flush = &r100_pci_gart_tlb_flush,
 	.gart_set_page = &r100_pci_gart_set_page,
@@ -135,7 +139,9 @@ void r300_ring_start(struct radeon_device *rdev);
 void r300_fence_ring_emit(struct radeon_device *rdev,
 			  struct radeon_fence *fence);
 int r300_cs_parse(struct radeon_cs_parser *p);
-int r300_gart_enable(struct radeon_device *rdev);
+int rv370_pcie_gart_init(struct radeon_device *rdev);
+void rv370_pcie_gart_fini(struct radeon_device *rdev);
+int rv370_pcie_gart_enable(struct radeon_device *rdev);
 void rv370_pcie_gart_disable(struct radeon_device *rdev);
 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
@@ -157,7 +163,9 @@ static struct radeon_asic r300_asic = {
 	.mc_fini = &r300_mc_fini,
 	.wb_init = &r100_wb_init,
 	.wb_fini = &r100_wb_fini,
-	.gart_enable = &r300_gart_enable,
+	.gart_init = &r100_pci_gart_init,
+	.gart_fini = &r100_pci_gart_fini,
+	.gart_enable = &r100_pci_gart_enable,
 	.gart_disable = &r100_pci_gart_disable,
 	.gart_tlb_flush = &r100_pci_gart_tlb_flush,
 	.gart_set_page = &r100_pci_gart_set_page,
@@ -205,8 +213,8 @@ static struct radeon_asic r420_asic = {
 	.mc_fini = NULL,
 	.wb_init = NULL,
 	.wb_fini = NULL,
-	.gart_enable = &r300_gart_enable,
-	.gart_disable = &rv370_pcie_gart_disable,
+	.gart_enable = NULL,
+	.gart_disable = NULL,
 	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 	.gart_set_page = &rv370_pcie_gart_set_page,
 	.cp_init = NULL,
@@ -242,6 +250,8 @@ void rs400_errata(struct radeon_device *rdev);
 void rs400_vram_info(struct radeon_device *rdev);
 int rs400_mc_init(struct radeon_device *rdev);
 void rs400_mc_fini(struct radeon_device *rdev);
+int rs400_gart_init(struct radeon_device *rdev);
+void rs400_gart_fini(struct radeon_device *rdev);
 int rs400_gart_enable(struct radeon_device *rdev);
 void rs400_gart_disable(struct radeon_device *rdev);
 void rs400_gart_tlb_flush(struct radeon_device *rdev);
@@ -257,6 +267,8 @@ static struct radeon_asic rs400_asic = {
 	.mc_fini = &rs400_mc_fini,
 	.wb_init = &r100_wb_init,
 	.wb_fini = &r100_wb_fini,
+	.gart_init = &rs400_gart_init,
+	.gart_fini = &rs400_gart_fini,
 	.gart_enable = &rs400_gart_enable,
 	.gart_disable = &rs400_gart_disable,
 	.gart_tlb_flush = &rs400_gart_tlb_flush,
@@ -298,6 +310,8 @@ void rs600_mc_fini(struct radeon_device *rdev);
 int rs600_irq_set(struct radeon_device *rdev);
 int rs600_irq_process(struct radeon_device *rdev);
 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
+int rs600_gart_init(struct radeon_device *rdev);
+void rs600_gart_fini(struct radeon_device *rdev);
 int rs600_gart_enable(struct radeon_device *rdev);
 void rs600_gart_disable(struct radeon_device *rdev);
 void rs600_gart_tlb_flush(struct radeon_device *rdev);
@@ -314,6 +328,8 @@ static struct radeon_asic rs600_asic = {
 	.mc_fini = &rs600_mc_fini,
 	.wb_init = &r100_wb_init,
 	.wb_fini = &r100_wb_fini,
+	.gart_init = &rs600_gart_init,
+	.gart_fini = &rs600_gart_fini,
 	.gart_enable = &rs600_gart_enable,
 	.gart_disable = &rs600_gart_disable,
 	.gart_tlb_flush = &rs600_gart_tlb_flush,
@@ -361,6 +377,8 @@ static struct radeon_asic rs690_asic = {
 	.mc_fini = &rs690_mc_fini,
 	.wb_init = &r100_wb_init,
 	.wb_fini = &r100_wb_fini,
+	.gart_init = &rs400_gart_init,
+	.gart_fini = &rs400_gart_fini,
 	.gart_enable = &rs400_gart_enable,
 	.gart_disable = &rs400_gart_disable,
 	.gart_tlb_flush = &rs400_gart_tlb_flush,
@@ -415,7 +433,9 @@ static struct radeon_asic rv515_asic = {
 	.mc_fini = &rv515_mc_fini,
 	.wb_init = &r100_wb_init,
 	.wb_fini = &r100_wb_fini,
-	.gart_enable = &r300_gart_enable,
+	.gart_init = &rv370_pcie_gart_init,
+	.gart_fini = &rv370_pcie_gart_fini,
+	.gart_enable = &rv370_pcie_gart_enable,
 	.gart_disable = &rv370_pcie_gart_disable,
 	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 	.gart_set_page = &rv370_pcie_gart_set_page,
@@ -462,7 +482,9 @@ static struct radeon_asic r520_asic = {
 	.mc_fini = &r520_mc_fini,
 	.wb_init = &r100_wb_init,
 	.wb_fini = &r100_wb_fini,
-	.gart_enable = &r300_gart_enable,
+	.gart_init = &rv370_pcie_gart_init,
+	.gart_fini = &rv370_pcie_gart_fini,
+	.gart_enable = &rv370_pcie_gart_enable,
 	.gart_disable = &rv370_pcie_gart_disable,
 	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 	.gart_set_page = &rv370_pcie_gart_set_page,
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index ece097c3e07..7b6d0b1a596 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -320,6 +320,14 @@ int radeon_asic_init(struct radeon_device *rdev)
 	case CHIP_RV350:
 	case CHIP_RV380:
 		rdev->asic = &r300_asic;
+		if (rdev->flags & RADEON_IS_PCIE) {
+			rdev->asic->gart_init = &rv370_pcie_gart_init;
+			rdev->asic->gart_fini = &rv370_pcie_gart_fini;
+			rdev->asic->gart_enable = &rv370_pcie_gart_enable;
+			rdev->asic->gart_disable = &rv370_pcie_gart_disable;
+			rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
+			rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
+		}
 		break;
 	case CHIP_R420:
 	case CHIP_R423:
@@ -504,6 +512,12 @@ int radeon_device_init(struct radeon_device *rdev,
 	rwlock_init(&rdev->fence_drv.lock);
 	INIT_LIST_HEAD(&rdev->gem.objects);
 
+	/* Set asic functions */
+	r = radeon_asic_init(rdev);
+	if (r) {
+		return r;
+	}
+
 	if (radeon_agpmode == -1) {
 		rdev->flags &= ~RADEON_IS_AGP;
 		if (rdev->family >= CHIP_RV515 ||
@@ -512,18 +526,24 @@ int radeon_device_init(struct radeon_device *rdev,
 		    rdev->family == CHIP_R423) {
 			DRM_INFO("Forcing AGP to PCIE mode\n");
 			rdev->flags |= RADEON_IS_PCIE;
+			rdev->asic->gart_init = &rv370_pcie_gart_init;
+			rdev->asic->gart_fini = &rv370_pcie_gart_fini;
+			rdev->asic->gart_enable = &rv370_pcie_gart_enable;
+			rdev->asic->gart_disable = &rv370_pcie_gart_disable;
+			rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
+			rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
 		} else {
 			DRM_INFO("Forcing AGP to PCI mode\n");
 			rdev->flags |= RADEON_IS_PCI;
+			rdev->asic->gart_init = &r100_pci_gart_init;
+			rdev->asic->gart_fini = &r100_pci_gart_fini;
+			rdev->asic->gart_enable = &r100_pci_gart_enable;
+			rdev->asic->gart_disable = &r100_pci_gart_disable;
+			rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
+			rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 		}
 	}
 
-	/* Set asic functions */
-	r = radeon_asic_init(rdev);
-	if (r) {
-		return r;
-	}
-
 	/* set DMA mask + need_dma32 flags.
 	 * PCIE - can handle 40-bits.
 	 * IGP - can handle 40-bits (in theory)
@@ -623,6 +643,9 @@ int radeon_device_init(struct radeon_device *rdev,
 		if (r) {
 			return r;
 		}
+		r = radeon_gpu_gart_init(rdev);
+		if (r)
+			return r;
 		/* Initialize GART (initialize after TTM so we can allocate
 		 * memory through TTM but finalize after TTM) */
 		r = radeon_gart_enable(rdev);
@@ -675,6 +698,7 @@ void radeon_device_fini(struct radeon_device *rdev)
 		radeon_ib_pool_fini(rdev);
 		radeon_cp_fini(rdev);
 		radeon_wb_fini(rdev);
+		radeon_gpu_gart_fini(rdev);
 		radeon_gem_fini(rdev);
 		radeon_mc_fini(rdev);
 #if __OS_HAS_AGP
diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c
index 2977539880f..a931af065dd 100644
--- a/drivers/gpu/drm/radeon/radeon_gart.c
+++ b/drivers/gpu/drm/radeon/radeon_gart.c
@@ -75,7 +75,6 @@ void radeon_gart_table_ram_free(struct radeon_device *rdev)
 
 int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
 {
-	uint64_t gpu_addr;
 	int r;
 
 	if (rdev->gart.table.vram.robj == NULL) {
@@ -88,6 +87,14 @@ int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
 			return r;
 		}
 	}
+	return 0;
+}
+
+int radeon_gart_table_vram_pin(struct radeon_device *rdev)
+{
+	uint64_t gpu_addr;
+	int r;
+
 	r = radeon_object_pin(rdev->gart.table.vram.robj,
 			      RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
 	if (r) {
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index e1e4ce42782..a3fbdad938c 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -92,20 +92,41 @@ void rs400_gart_tlb_flush(struct radeon_device *rdev)
 	WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
 }
 
-int rs400_gart_enable(struct radeon_device *rdev)
+int rs400_gart_init(struct radeon_device *rdev)
 {
-	uint32_t size_reg;
-	uint32_t tmp;
 	int r;
 
+	if (rdev->gart.table.ram.ptr) {
+		WARN(1, "RS400 GART already initialized.\n");
+		return 0;
+	}
+	/* Check gart size */
+	switch(rdev->mc.gtt_size / (1024 * 1024)) {
+	case 32:
+	case 64:
+	case 128:
+	case 256:
+	case 512:
+	case 1024:
+	case 2048:
+		break;
+	default:
+		return -EINVAL;
+	}
 	/* Initialize common gart structure */
 	r = radeon_gart_init(rdev);
-	if (r) {
+	if (r)
 		return r;
-	}
-	if (rs400_debugfs_pcie_gart_info_init(rdev)) {
+	if (rs400_debugfs_pcie_gart_info_init(rdev))
 		DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
-	}
+	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
+	return radeon_gart_table_ram_alloc(rdev);
+}
+
+int rs400_gart_enable(struct radeon_device *rdev)
+{
+	uint32_t size_reg;
+	uint32_t tmp;
 
 	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
 	tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
@@ -136,13 +157,6 @@ int rs400_gart_enable(struct radeon_device *rdev)
 	default:
 		return -EINVAL;
 	}
-	if (rdev->gart.table.ram.ptr == NULL) {
-		rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
-		r = radeon_gart_table_ram_alloc(rdev);
-		if (r) {
-			return r;
-		}
-	}
 	/* It should be fine to program it to max value */
 	if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
 		WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
@@ -201,6 +215,13 @@ void rs400_gart_disable(struct radeon_device *rdev)
 	WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 }
 
+void rs400_gart_fini(struct radeon_device *rdev)
+{
+	rs400_gart_disable(rdev);
+	radeon_gart_table_ram_free(rdev);
+	radeon_gart_fini(rdev);
+}
+
 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 {
 	uint32_t entry;
@@ -255,14 +276,12 @@ int rs400_mc_init(struct radeon_device *rdev)
 	(void)RREG32(RADEON_HOST_PATH_CNTL);
 	WREG32(RADEON_HOST_PATH_CNTL, tmp);
 	(void)RREG32(RADEON_HOST_PATH_CNTL);
+
 	return 0;
 }
 
 void rs400_mc_fini(struct radeon_device *rdev)
 {
-	rs400_gart_disable(rdev);
-	radeon_gart_table_ram_free(rdev);
-	radeon_gart_fini(rdev);
 }
 
 
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 1b8d62f5e73..c31bd843925 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -68,22 +68,35 @@ void rs600_gart_tlb_flush(struct radeon_device *rdev)
 	tmp = RREG32_MC(RS600_MC_PT0_CNTL);
 }
 
-int rs600_gart_enable(struct radeon_device *rdev)
+int rs600_gart_init(struct radeon_device *rdev)
 {
-	uint32_t tmp;
-	int i;
 	int r;
 
+	if (rdev->gart.table.vram.robj) {
+		WARN(1, "RS600 GART already initialized.\n");
+		return 0;
+	}
 	/* Initialize common gart structure */
 	r = radeon_gart_init(rdev);
 	if (r) {
 		return r;
 	}
 	rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
-	r = radeon_gart_table_vram_alloc(rdev);
-	if (r) {
-		return r;
+	return radeon_gart_table_vram_alloc(rdev);
+}
+
+int rs600_gart_enable(struct radeon_device *rdev)
+{
+	uint32_t tmp;
+	int r, i;
+
+	if (rdev->gart.table.vram.robj == NULL) {
+		dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
+		return -EINVAL;
 	}
+	r = radeon_gart_table_vram_pin(rdev);
+	if (r)
+		return r;
 	/* FIXME: setup default page */
 	WREG32_MC(RS600_MC_PT0_CNTL,
 		 (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
@@ -138,8 +151,17 @@ void rs600_gart_disable(struct radeon_device *rdev)
 	tmp = RREG32_MC(RS600_MC_CNTL1);
 	tmp &= ~RS600_ENABLE_PAGE_TABLES;
 	WREG32_MC(RS600_MC_CNTL1, tmp);
-	radeon_object_kunmap(rdev->gart.table.vram.robj);
-	radeon_object_unpin(rdev->gart.table.vram.robj);
+	if (rdev->gart.table.vram.robj) {
+		radeon_object_kunmap(rdev->gart.table.vram.robj);
+		radeon_object_unpin(rdev->gart.table.vram.robj);
+	}
+}
+
+void rs600_gart_fini(struct radeon_device *rdev)
+{
+	rs600_gart_disable(rdev);
+	radeon_gart_table_vram_free(rdev);
+	radeon_gart_fini(rdev);
 }
 
 #define R600_PTE_VALID     (1 << 0)
@@ -235,9 +257,6 @@ int rs600_mc_init(struct radeon_device *rdev)
 
 void rs600_mc_fini(struct radeon_device *rdev)
 {
-	rs600_gart_disable(rdev);
-	radeon_gart_table_vram_free(rdev);
-	radeon_gart_fini(rdev);
 }
 
 
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 839595b0072..0f585ca8276 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -94,9 +94,6 @@ int rs690_mc_init(struct radeon_device *rdev)
 
 void rs690_mc_fini(struct radeon_device *rdev)
 {
-	rs400_gart_disable(rdev);
-	radeon_gart_table_ram_free(rdev);
-	radeon_gart_fini(rdev);
 }
 
 
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 03d490269ed..fd799748e7d 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -37,8 +37,6 @@ int r100_cp_reset(struct radeon_device *rdev);
 int r100_rb2d_reset(struct radeon_device *rdev);
 int r100_gui_wait_for_idle(struct radeon_device *rdev);
 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
-int rv370_pcie_gart_enable(struct radeon_device *rdev);
-void rv370_pcie_gart_disable(struct radeon_device *rdev);
 void r420_pipes_init(struct radeon_device *rdev);
 void rs600_mc_disable_clients(struct radeon_device *rdev);
 void rs600_disable_vga(struct radeon_device *rdev);
@@ -126,9 +124,6 @@ int rv515_mc_init(struct radeon_device *rdev)
 
 void rv515_mc_fini(struct radeon_device *rdev)
 {
-	rv370_pcie_gart_disable(rdev);
-	radeon_gart_table_vram_free(rdev);
-	radeon_gart_fini(rdev);
 }
 
 
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 5ba5204091e..4f2098bc797 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -48,16 +48,13 @@ int rv770_pcie_gart_enable(struct radeon_device *rdev)
 	u32 tmp;
 	int r, i;
 
-	/* Initialize common gart structure */
-	r = radeon_gart_init(rdev);
-	if (r) {
-		return r;
+	if (rdev->gart.table.vram.robj == NULL) {
+		dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
+		return -EINVAL;
 	}
-	rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
-	r = radeon_gart_table_vram_alloc(rdev);
-	if (r) {
+	r = radeon_gart_table_vram_pin(rdev);
+	if (r)
 		return r;
-	}
 	for (i = 0; i < rdev->gart.num_gpu_pages; i++)
 		r600_gart_clear_page(rdev, i);
 	/* Setup L2 cache */
@@ -98,10 +95,6 @@ void rv770_pcie_gart_disable(struct radeon_device *rdev)
 	u32 tmp;
 	int i;
 
-	/* Clear ptes*/
-	for (i = 0; i < rdev->gart.num_gpu_pages; i++)
-		r600_gart_clear_page(rdev, i);
-	r600_pcie_gart_tlb_flush(rdev);
 	/* Disable all tables */
 	for (i = 0; i < 7; i++)
 		WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
@@ -120,6 +113,17 @@ void rv770_pcie_gart_disable(struct radeon_device *rdev)
 	WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 	WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 	WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
+	if (rdev->gart.table.vram.robj) {
+		radeon_object_kunmap(rdev->gart.table.vram.robj);
+		radeon_object_unpin(rdev->gart.table.vram.robj);
+	}
+}
+
+void rv770_pcie_gart_fini(struct radeon_device *rdev)
+{
+	rv770_pcie_gart_disable(rdev);
+	radeon_gart_table_vram_free(rdev);
+	radeon_gart_fini(rdev);
 }
 
 
@@ -871,6 +875,7 @@ int rv770_suspend(struct radeon_device *rdev)
 {
 	/* FIXME: we should wait for ring to be empty */
 	r700_cp_stop(rdev);
+	rv770_pcie_gart_disable(rdev);
 	return 0;
 }
 
@@ -944,6 +949,10 @@ int rv770_init(struct radeon_device *rdev)
 		}
 	}
 
+	r = r600_pcie_gart_init(rdev);
+	if (r)
+		return r;
+
 	r = rv770_resume(rdev);
 	if (r) {
 		if (rdev->flags & RADEON_IS_AGP) {
@@ -976,9 +985,7 @@ void rv770_fini(struct radeon_device *rdev)
 {
 	r600_blit_fini(rdev);
 	radeon_ring_fini(rdev);
-	rv770_pcie_gart_disable(rdev);
-	radeon_gart_table_vram_free(rdev);
-	radeon_gart_fini(rdev);
+	rv770_pcie_gart_fini(rdev);
 	radeon_gem_fini(rdev);
 	radeon_fence_driver_fini(rdev);
 	radeon_clocks_fini(rdev);
-- 
cgit v1.2.3


From 70ba2a374704e00df8868a7ac3d7350329d28924 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 15 Sep 2009 09:03:43 +1000
Subject: drm/radeon/kms: add 32/64 ioctl support.

Although the new radeon driver ioctls don't need this, some of
the drm initialisation ioctls require it, so add this to make them
work.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/radeon_drv.c   |  2 +-
 drivers/gpu/drm/radeon/radeon_drv.h   |  2 ++
 drivers/gpu/drm/radeon/radeon_ioc32.c | 15 +++++++++++++++
 3 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 29f040a7861..50fce498910 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -286,7 +286,7 @@ static struct drm_driver kms_driver = {
 		 .poll = drm_poll,
 		 .fasync = drm_fasync,
 #ifdef CONFIG_COMPAT
-		 .compat_ioctl = NULL,
+		 .compat_ioctl = radeon_kms_compat_ioctl,
 #endif
 	},
 
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index c7b185924f6..bc79ad6199b 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -471,6 +471,8 @@ extern int radeon_driver_open(struct drm_device *dev,
 			      struct drm_file *file_priv);
 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
 				unsigned long arg);
+extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
+				    unsigned long arg);
 
 extern int radeon_master_create(struct drm_device *dev, struct drm_master *master);
 extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master);
diff --git a/drivers/gpu/drm/radeon/radeon_ioc32.c b/drivers/gpu/drm/radeon/radeon_ioc32.c
index 56decda2a71..a1bf11de308 100644
--- a/drivers/gpu/drm/radeon/radeon_ioc32.c
+++ b/drivers/gpu/drm/radeon/radeon_ioc32.c
@@ -422,3 +422,18 @@ long radeon_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
 
 	return ret;
 }
+
+long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+{
+	unsigned int nr = DRM_IOCTL_NR(cmd);
+	int ret;
+
+	if (nr < DRM_COMMAND_BASE)
+		return drm_compat_ioctl(filp, cmd, arg);
+
+	lock_kernel();		/* XXX for now */
+	ret = drm_ioctl(filp->f_path.dentry->d_inode, filp, cmd, arg);
+	unlock_kernel();
+
+	return ret;
+}
-- 
cgit v1.2.3


From fb1fbf8e098cd4cd2c1dece3dc8f15e7de82170a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <daenzer@vmware.com>
Date: Tue, 15 Sep 2009 17:09:28 +0200
Subject: drm/radeon/kms: Only add common modes which fit in both panel
 dimensions.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Signed-off-by: Michel Dänzer <daenzer@vmware.com>
Signed-off-by: Dave Airlie <airlied@linux.ie>
---
 drivers/gpu/drm/radeon/radeon_connectors.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 04ecb11ebb8..d2842da8c8b 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -207,8 +207,10 @@ static void radeon_add_common_modes(struct drm_encoder *encoder, struct drm_conn
 
 	for (i = 0; i < 17; i++) {
 		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
-			if (common_modes[i].w >= native_mode->panel_xres &&
-			    common_modes[i].h >= native_mode->panel_yres)
+			if (common_modes[i].w > native_mode->panel_xres ||
+			    common_modes[i].h > native_mode->panel_yres ||
+			    (common_modes[i].w == native_mode->panel_xres &&
+			     common_modes[i].h == native_mode->panel_yres))
 				continue;
 		}
 		if (common_modes[i].w < 320 || common_modes[i].h < 200)
-- 
cgit v1.2.3


From 95a8f1bf4f48b434c9f839ab5a0773f66b39d7c6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <daenzer@vmware.com>
Date: Tue, 15 Sep 2009 17:09:26 +0200
Subject: drm/radeon/kms: Move radeon_clocks_init() call back after getting
 VRAM info.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

It may indirectly call radeon_set_clock_gating() which relies on the VRAM info.

Signed-off-by: Michel Dänzer <daenzer@vmware.com>
Signed-off-by: Dave Airlie <airlied@linux.ie>
---
 drivers/gpu/drm/radeon/radeon_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 7b6d0b1a596..cc8e005c1b3 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -616,13 +616,13 @@ int radeon_device_init(struct radeon_device *rdev,
 				radeon_combios_asic_init(rdev->ddev);
 			}
 		}
+		/* Get vram informations */
+		radeon_vram_info(rdev);
 		/* Initialize clocks */
 		r = radeon_clocks_init(rdev);
 		if (r) {
 			return r;
 		}
-		/* Get vram informations */
-		radeon_vram_info(rdev);
 
 		/* Initialize memory controller (also test AGP) */
 		r = radeon_mc_init(rdev);
-- 
cgit v1.2.3


From fdd5cace733370ab7a518a98ef084e02aa76fdea Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <daenzer@vmware.com>
Date: Tue, 15 Sep 2009 17:09:33 +0200
Subject: drm/radeon/kms: Don't kzalloc memory which is immediately
 overwritten.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Signed-off-by: Michel Dänzer <daenzer@vmware.com>
Signed-off-by: Dave Airlie <airlied@linux.ie>
---
 drivers/gpu/drm/radeon/radeon_cs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index a169067efc4..b530926a217 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -145,7 +145,7 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
 		cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
 
 		size = p->chunks[i].length_dw * sizeof(uint32_t);
-		p->chunks[i].kdata = kzalloc(size, GFP_KERNEL);
+		p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
 		if (p->chunks[i].kdata == NULL) {
 			return -ENOMEM;
 		}
-- 
cgit v1.2.3


From 48e113e516a94ac9622a8326c4de670beb3366e6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <daenzer@vmware.com>
Date: Tue, 15 Sep 2009 17:09:32 +0200
Subject: drm/radeon/kms: Free CS parser state tracking memory.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Fixes leak hidden in commit 9f022ddfb23793b475ff7e57ac08a766dd5d31bd
('drm/radeon/kms: convert r4xx to new init path').

Signed-off-by: Michel Dänzer <daenzer@vmware.com>
Signed-off-by: Dave Airlie <airlied@linux.ie>
---
 drivers/gpu/drm/radeon/radeon_cs.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index b530926a217..12f5990c2d2 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -185,6 +185,7 @@ static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
 			mutex_unlock(&parser->rdev->ddev->struct_mutex);
 		}
 	}
+	kfree(parser->track);
 	kfree(parser->relocs);
 	kfree(parser->relocs_ptr);
 	for (i = 0; i < parser->nchunks; i++) {
-- 
cgit v1.2.3


From 42dea5ddb56fe10e1d9a7840ddcb1df97a208a99 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Tue, 15 Sep 2009 20:21:11 +1000
Subject: drm/radeon/kms: we should return 0 when we have no modes not -1.

This fixes my monitor with broken EDID so it at least get 800x600.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/radeon_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 9d817a62e7f..22da85fe5ae 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -365,7 +365,7 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 		return ret;
 	}
 	drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
-	return -1;
+	return 0;
 }
 
 static int radeon_ddc_dump(struct drm_connector *connector)
-- 
cgit v1.2.3


From ecb114a128d150422d22eda238cb812f6b20bf39 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Tue, 15 Sep 2009 11:12:56 +1000
Subject: drm/radeon/kms: IB locking dumps out a lockdep ordering issue

We sometimes lock IB then the ring and sometimes the ring then
the IB. This is mostly due to the IB locking not being well defined
about what data in the structs it actually locks. Define what I
believe is the correct behaviour and gets rid of the lock dep ordering
warning.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/r600_blit_kms.c |  2 +-
 drivers/gpu/drm/radeon/radeon.h        |  4 ++++
 drivers/gpu/drm/radeon/radeon_ring.c   | 24 +++++++++++++++++-------
 3 files changed, 22 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index 1ebfd5a6dfe..4f0d181a690 100644
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -538,8 +538,8 @@ int r600_vb_ib_get(struct radeon_device *rdev)
 
 void r600_vb_ib_put(struct radeon_device *rdev)
 {
-	mutex_lock(&rdev->ib_pool.mutex);
 	radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence);
+	mutex_lock(&rdev->ib_pool.mutex);
 	list_add_tail(&rdev->r600_blit.vb_ib->list, &rdev->ib_pool.scheduled_ibs);
 	mutex_unlock(&rdev->ib_pool.mutex);
 	radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 99292be8bc9..ff9e4171559 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -402,6 +402,10 @@ struct radeon_ib {
 	uint32_t		length_dw;
 };
 
+/*
+ * locking -
+ * mutex protects scheduled_ibs, ready, alloc_bm
+ */
 struct radeon_ib_pool {
 	struct mutex		mutex;
 	struct radeon_object	*robj;
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index 168a555d6fb..747b4bffb84 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -56,10 +56,12 @@ int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib)
 		set_bit(i, rdev->ib_pool.alloc_bm);
 		rdev->ib_pool.ibs[i].length_dw = 0;
 		*ib = &rdev->ib_pool.ibs[i];
+		mutex_unlock(&rdev->ib_pool.mutex);
 		goto out;
 	}
 	if (list_empty(&rdev->ib_pool.scheduled_ibs)) {
 		/* we go do nothings here */
+		mutex_unlock(&rdev->ib_pool.mutex);
 		DRM_ERROR("all IB allocated none scheduled.\n");
 		r = -EINVAL;
 		goto out;
@@ -69,10 +71,13 @@ int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib)
 			 struct radeon_ib, list);
 	if (nib->fence == NULL) {
 		/* we go do nothings here */
+		mutex_unlock(&rdev->ib_pool.mutex);
 		DRM_ERROR("IB %lu scheduled without a fence.\n", nib->idx);
 		r = -EINVAL;
 		goto out;
 	}
+	mutex_unlock(&rdev->ib_pool.mutex);
+
 	r = radeon_fence_wait(nib->fence, false);
 	if (r) {
 		DRM_ERROR("radeon: IB(%lu:0x%016lX:%u)\n", nib->idx,
@@ -81,12 +86,17 @@ int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib)
 		goto out;
 	}
 	radeon_fence_unref(&nib->fence);
+
 	nib->length_dw = 0;
+
+	/* scheduled list is accessed here */
+	mutex_lock(&rdev->ib_pool.mutex);
 	list_del(&nib->list);
 	INIT_LIST_HEAD(&nib->list);
+	mutex_unlock(&rdev->ib_pool.mutex);
+
 	*ib = nib;
 out:
-	mutex_unlock(&rdev->ib_pool.mutex);
 	if (r) {
 		radeon_fence_unref(&fence);
 	} else {
@@ -110,9 +120,10 @@ void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
 		return;
 	}
 	list_del(&tmp->list);
-	if (tmp->fence) {
+	INIT_LIST_HEAD(&tmp->list);
+	if (tmp->fence)
 		radeon_fence_unref(&tmp->fence);
-	}
+
 	tmp->length_dw = 0;
 	clear_bit(tmp->idx, rdev->ib_pool.alloc_bm);
 	mutex_unlock(&rdev->ib_pool.mutex);
@@ -122,25 +133,24 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
 {
 	int r = 0;
 
-	mutex_lock(&rdev->ib_pool.mutex);
 	if (!ib->length_dw || !rdev->cp.ready) {
 		/* TODO: Nothings in the ib we should report. */
-		mutex_unlock(&rdev->ib_pool.mutex);
 		DRM_ERROR("radeon: couldn't schedule IB(%lu).\n", ib->idx);
 		return -EINVAL;
 	}
+
 	/* 64 dwords should be enough for fence too */
 	r = radeon_ring_lock(rdev, 64);
 	if (r) {
 		DRM_ERROR("radeon: scheduling IB failled (%d).\n", r);
-		mutex_unlock(&rdev->ib_pool.mutex);
 		return r;
 	}
 	radeon_ring_ib_execute(rdev, ib);
 	radeon_fence_emit(rdev, ib->fence);
-	radeon_ring_unlock_commit(rdev);
+	mutex_lock(&rdev->ib_pool.mutex);
 	list_add_tail(&ib->list, &rdev->ib_pool.scheduled_ibs);
 	mutex_unlock(&rdev->ib_pool.mutex);
+	radeon_ring_unlock_commit(rdev);
 	return 0;
 }
 
-- 
cgit v1.2.3


From f657c2a7310ad56e2b67f35f4c5c6106a7146b9c Mon Sep 17 00:00:00 2001
From: Yang Zhao <yang@yangman.ca>
Date: Tue, 15 Sep 2009 12:21:01 +1000
Subject: drm/radeon: Save and restore bios scratch regs during S/R

[airlied:- adapted slightly in naming]

Signed-off-by: Yang Zhao <yang@yangman.ca>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/radeon.h          |  2 ++
 drivers/gpu/drm/radeon/radeon_atombios.c | 28 ++++++++++++++++++++++++++++
 drivers/gpu/drm/radeon/radeon_device.c   |  3 +++
 drivers/gpu/drm/radeon/radeon_mode.h     |  2 ++
 4 files changed, 35 insertions(+)

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index ff9e4171559..5bfc05612ac 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -75,6 +75,7 @@ extern int radeon_tv;
 #define RADEON_IB_POOL_SIZE		16
 #define RADEON_DEBUGFS_MAX_NUM_FILES	32
 #define RADEONFB_CONN_LIMIT		4
+#define RADEON_BIOS_NUM_SCRATCH		8
 
 enum radeon_family {
 	CHIP_R100,
@@ -783,6 +784,7 @@ struct radeon_device {
 	struct radeon_asic		*asic;
 	struct radeon_gem		gem;
 	struct radeon_pm		pm;
+	uint32_t			bios_scratch[RADEON_BIOS_NUM_SCRATCH];
 	struct mutex			cs_mutex;
 	struct radeon_wb		wb;
 	struct radeon_dummy_page	dummy_page;
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index aa756dec895..cb5efcaf2ba 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1045,6 +1045,34 @@ void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
 
 }
 
+void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
+{
+	uint32_t scratch_reg;
+	int i;
+
+	if (rdev->family >= CHIP_R600)
+		scratch_reg = R600_BIOS_0_SCRATCH;
+	else
+		scratch_reg = RADEON_BIOS_0_SCRATCH;
+
+	for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
+		rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
+}
+
+void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
+{
+	uint32_t scratch_reg;
+	int i;
+
+	if (rdev->family >= CHIP_R600)
+		scratch_reg = R600_BIOS_0_SCRATCH;
+	else
+		scratch_reg = RADEON_BIOS_0_SCRATCH;
+
+	for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
+		WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
+}
+
 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
 {
 	struct drm_device *dev = encoder->dev;
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index cc8e005c1b3..db5ae73d628 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -755,6 +755,8 @@ int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
 	/* wait for gpu to finish processing current batch */
 	radeon_fence_wait_last(rdev);
 
+	radeon_save_bios_scratch_regs(rdev);
+
 	if (!rdev->new_init_path) {
 		radeon_cp_disable(rdev);
 		radeon_gart_disable(rdev);
@@ -828,6 +830,7 @@ int radeon_resume_kms(struct drm_device *dev)
 		radeon_resume(rdev);
 	}
 out:
+	radeon_restore_bios_scratch_regs(rdev);
 	fb_set_suspend(rdev->fbdev_info, 0);
 	release_console_sem();
 
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 523d6cbd4f0..dde13817dee 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -383,6 +383,8 @@ extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
+extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
+extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
 extern void
 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
 extern void
-- 
cgit v1.2.3


From 8dfaa8a7779ad2667d539aca6ae11cd87f562db6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <daenzer@vmware.com>
Date: Tue, 15 Sep 2009 17:09:27 +0200
Subject: drm/radeon/kms: Get LVDS native mode details from EDID if necessary.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Fixes RMX problems on older Apple laptops which don't have an x86 BIOS ROM.

Signed-off-by: Michel Dänzer <daenzer@vmware.com>
Signed-off-by: Dave Airlie <airlied@linux.ie>
---
 drivers/gpu/drm/radeon/radeon_combios.c    | 12 +++++++----
 drivers/gpu/drm/radeon/radeon_connectors.c | 34 +++++++++++++++++++++++++++++-
 2 files changed, 41 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 2a027e00762..cb60f553233 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -863,8 +863,10 @@ struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
 	int tmp, i;
 	struct radeon_encoder_lvds *lvds = NULL;
 
-	if (rdev->bios == NULL)
-		return radeon_legacy_get_lvds_info_from_regs(rdev);
+	if (rdev->bios == NULL) {
+		lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
+		goto out;
+	}
 
 	lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
 
@@ -965,11 +967,13 @@ struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
 				lvds->native_mode.flags = 0;
 			}
 		}
-		encoder->native_mode = lvds->native_mode;
 	} else {
 		DRM_INFO("No panel info found in BIOS\n");
-		return radeon_legacy_get_lvds_info_from_regs(rdev);
+		lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
 	}
+out:
+	if (lvds)
+		encoder->native_mode = lvds->native_mode;
 	return lvds;
 }
 
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index d2842da8c8b..5ee81b6a879 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -227,6 +227,36 @@ int radeon_connector_set_property(struct drm_connector *connector, struct drm_pr
 	return 0;
 }
 
+static void radeon_fixup_lvds_native_mode(struct drm_encoder *encoder,
+					  struct drm_connector *connector)
+{
+	struct radeon_encoder *radeon_encoder =	to_radeon_encoder(encoder);
+	struct radeon_native_mode *native_mode = &radeon_encoder->native_mode;
+
+	/* Try to get native mode details from EDID if necessary */
+	if (!native_mode->dotclock) {
+		struct drm_display_mode *t, *mode;
+
+		list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
+			if (mode->hdisplay == native_mode->panel_xres &&
+			    mode->vdisplay == native_mode->panel_yres) {
+				native_mode->hblank = mode->htotal - mode->hdisplay;
+				native_mode->hoverplus = mode->hsync_start - mode->hdisplay;
+				native_mode->hsync_width = mode->hsync_end - mode->hsync_start;
+				native_mode->vblank = mode->vtotal - mode->vdisplay;
+				native_mode->voverplus = mode->vsync_start - mode->vdisplay;
+				native_mode->vsync_width = mode->vsync_end - mode->vsync_start;
+				native_mode->dotclock = mode->clock;
+				DRM_INFO("Determined LVDS native mode details from EDID\n");
+				break;
+			}
+		}
+	}
+	if (!native_mode->dotclock) {
+		DRM_INFO("No LVDS native mode details, disabling RMX\n");
+		radeon_encoder->rmx_type = RMX_OFF;
+	}
+}
 
 static int radeon_lvds_get_modes(struct drm_connector *connector)
 {
@@ -239,9 +269,11 @@ static int radeon_lvds_get_modes(struct drm_connector *connector)
 		ret = radeon_ddc_get_modes(radeon_connector);
 		if (ret > 0) {
 			encoder = radeon_best_single_encoder(connector);
-			if (encoder)
+			if (encoder) {
+				radeon_fixup_lvds_native_mode(encoder, connector);
 				/* add scaled modes */
 				radeon_add_common_modes(encoder, connector);
+			}
 			return ret;
 		}
 	}
-- 
cgit v1.2.3


From e87b2c42b397ae64ac13a390011931f7ef222321 Mon Sep 17 00:00:00 2001
From: Jesse Barnes <jbarnes@virtuousgeek.org>
Date: Thu, 17 Sep 2009 18:14:41 -0700
Subject: drm: fix drm_fb_helper handling of kernel crtcs

The drm_fb_helper shouldn't mess with CRTCs that aren't enabled or in
its initial config. Ideally it shouldn't even include CRTCs in its
initial config if they're not in use, but my old fix for that no longer
works.  At any rate, this fixes a real bug I was seeing where after a
console blank, both pipes would come back on, even though only one had
been enabled before that.  Since the other pipe had a bogus config,
this led to some screen corruption.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_fb_helper.c | 80 ++++++++++++++++++++++-------------------
 1 file changed, 43 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 8eee4a62037..2c467131488 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -116,27 +116,30 @@ static void drm_fb_helper_on(struct fb_info *info)
 	 * For each CRTC in this fb, turn the crtc on then,
 	 * find all associated encoders and turn them on.
 	 */
-	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-		struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+	for (i = 0; i < fb_helper->crtc_count; i++) {
+		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+			struct drm_crtc_helper_funcs *crtc_funcs =
+				crtc->helper_private;
 
-		for (i = 0; i < fb_helper->crtc_count; i++) {
-			if (crtc->base.id == fb_helper->crtc_info[i].crtc_id)
-				break;
-		}
+			/* Only mess with CRTCs in this fb */
+			if (crtc->base.id != fb_helper->crtc_info[i].crtc_id ||
+			    !crtc->enabled)
+				continue;
 
-		mutex_lock(&dev->mode_config.mutex);
-		crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
-		mutex_unlock(&dev->mode_config.mutex);
+			mutex_lock(&dev->mode_config.mutex);
+			crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
+			mutex_unlock(&dev->mode_config.mutex);
 
-		/* Found a CRTC on this fb, now find encoders */
-		list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
-			if (encoder->crtc == crtc) {
-				struct drm_encoder_helper_funcs *encoder_funcs;
+			/* Found a CRTC on this fb, now find encoders */
+			list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+				if (encoder->crtc == crtc) {
+					struct drm_encoder_helper_funcs *encoder_funcs;
 
-				encoder_funcs = encoder->helper_private;
-				mutex_lock(&dev->mode_config.mutex);
-				encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
-				mutex_unlock(&dev->mode_config.mutex);
+					encoder_funcs = encoder->helper_private;
+					mutex_lock(&dev->mode_config.mutex);
+					encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
+					mutex_unlock(&dev->mode_config.mutex);
+				}
 			}
 		}
 	}
@@ -154,30 +157,33 @@ static void drm_fb_helper_off(struct fb_info *info, int dpms_mode)
 	 * For each CRTC in this fb, find all associated encoders
 	 * and turn them off, then turn off the CRTC.
 	 */
-	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-		struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
-
-		for (i = 0; i < fb_helper->crtc_count; i++) {
-			if (crtc->base.id == fb_helper->crtc_info[i].crtc_id)
-				break;
-		}
-
-		/* Found a CRTC on this fb, now find encoders */
-		list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
-			if (encoder->crtc == crtc) {
-				struct drm_encoder_helper_funcs *encoder_funcs;
-
-				encoder_funcs = encoder->helper_private;
+	for (i = 0; i < fb_helper->crtc_count; i++) {
+		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+			struct drm_crtc_helper_funcs *crtc_funcs =
+				crtc->helper_private;
+
+			/* Only mess with CRTCs in this fb */
+			if (crtc->base.id != fb_helper->crtc_info[i].crtc_id ||
+			    !crtc->enabled)
+				continue;
+
+			/* Found a CRTC on this fb, now find encoders */
+			list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+				if (encoder->crtc == crtc) {
+					struct drm_encoder_helper_funcs *encoder_funcs;
+
+					encoder_funcs = encoder->helper_private;
+					mutex_lock(&dev->mode_config.mutex);
+					encoder_funcs->dpms(encoder, dpms_mode);
+					mutex_unlock(&dev->mode_config.mutex);
+				}
+			}
+			if (dpms_mode == DRM_MODE_DPMS_OFF) {
 				mutex_lock(&dev->mode_config.mutex);
-				encoder_funcs->dpms(encoder, dpms_mode);
+				crtc_funcs->dpms(crtc, dpms_mode);
 				mutex_unlock(&dev->mode_config.mutex);
 			}
 		}
-		if (dpms_mode == DRM_MODE_DPMS_OFF) {
-			mutex_lock(&dev->mode_config.mutex);
-			crtc_funcs->dpms(crtc, dpms_mode);
-			mutex_unlock(&dev->mode_config.mutex);
-		}
 	}
 }
 
-- 
cgit v1.2.3


From 9b1596af17dc9bf38c304f69fb253d6cfa73d136 Mon Sep 17 00:00:00 2001
From: Ben Skeggs <bskeggs@redhat.com>
Date: Fri, 18 Sep 2009 10:43:52 +1000
Subject: drm: update crtc x/y when only fb changes

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_crtc_helper.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index ff447f175a5..fe8697447f3 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -869,6 +869,9 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
 		}
 		drm_helper_disable_unused_functions(dev);
 	} else if (fb_changed) {
+		set->crtc->x = set->x;
+		set->crtc->y = set->y;
+
 		old_fb = set->crtc->fb;
 		if (set->crtc->fb != set->fb)
 			set->crtc->fb = set->fb;
-- 
cgit v1.2.3


From 812c369dbf3b5a726b52bbfb8adbc230f3f81bcf Mon Sep 17 00:00:00 2001
From: Pekka Paalanen <pq@iki.fi>
Date: Thu, 17 Sep 2009 22:59:54 +0300
Subject: drm: fix _DRM_GEM addmap error message

Fix the error message: this is add, not rm.
Move the closing brace to proper spot: _DRM_GEM branch should not be
included in the block.

Signed-off-by: Pekka Paalanen <pq@iki.fi>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_bufs.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c
index 6246e3f3dad..3d09e304f6f 100644
--- a/drivers/gpu/drm/drm_bufs.c
+++ b/drivers/gpu/drm/drm_bufs.c
@@ -310,10 +310,10 @@ static int drm_addmap_core(struct drm_device * dev, resource_size_t offset,
 			  (unsigned long long)map->offset, map->size);
 
 		break;
+	}
 	case _DRM_GEM:
-		DRM_ERROR("tried to rmmap GEM object\n");
+		DRM_ERROR("tried to addmap GEM object\n");
 		break;
-	}
 	case _DRM_SCATTER_GATHER:
 		if (!dev->sg) {
 			kfree(map);
-- 
cgit v1.2.3


From b15591f3120309093fc6d3df26b4242187d7b384 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Thu, 17 Sep 2009 14:25:12 -0400
Subject: drm/radeon/r600: don't do interrupts

Interrupts are not supported yet.  This prevents
things like mesa from trying to use them.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/radeon_irq.c   | 18 ++++++++++++++++++
 drivers/gpu/drm/radeon/radeon_state.c |  5 ++++-
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/radeon/radeon_irq.c b/drivers/gpu/drm/radeon/radeon_irq.c
index 9836c705a95..b79ecc4a7cc 100644
--- a/drivers/gpu/drm/radeon/radeon_irq.c
+++ b/drivers/gpu/drm/radeon/radeon_irq.c
@@ -188,6 +188,9 @@ irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
 	u32 stat;
 	u32 r500_disp_int;
 
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+		return IRQ_NONE;
+
 	/* Only consider the bits we're interested in - others could be used
 	 * outside the DRM
 	 */
@@ -286,6 +289,9 @@ int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_pr
 	drm_radeon_irq_emit_t *emit = data;
 	int result;
 
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+		return -EINVAL;
+
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
 	if (!dev_priv) {
@@ -315,6 +321,9 @@ int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_pr
 		return -EINVAL;
 	}
 
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+		return -EINVAL;
+
 	return radeon_wait_irq(dev, irqwait->irq_seq);
 }
 
@@ -326,6 +335,9 @@ void radeon_driver_irq_preinstall(struct drm_device * dev)
 	    (drm_radeon_private_t *) dev->dev_private;
 	u32 dummy;
 
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+		return;
+
 	/* Disable *all* interrupts */
 	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
 		RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
@@ -345,6 +357,9 @@ int radeon_driver_irq_postinstall(struct drm_device *dev)
 
 	dev->max_vblank_count = 0x001fffff;
 
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+		return 0;
+
 	radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
 
 	return 0;
@@ -357,6 +372,9 @@ void radeon_driver_irq_uninstall(struct drm_device * dev)
 	if (!dev_priv)
 		return;
 
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+		return;
+
 	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
 		RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
 	/* Disable *all* interrupts */
diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c
index aad0c6fafcf..38537d971a3 100644
--- a/drivers/gpu/drm/radeon/radeon_state.c
+++ b/drivers/gpu/drm/radeon/radeon_state.c
@@ -3034,7 +3034,10 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
 		value = GET_SCRATCH(dev_priv, 2);
 		break;
 	case RADEON_PARAM_IRQ_NR:
-		value = drm_dev_to_irq(dev);
+		if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+			value = 0;
+		else
+			value = drm_dev_to_irq(dev);
 		break;
 	case RADEON_PARAM_GART_BASE:
 		value = dev_priv->gart_vm_start;
-- 
cgit v1.2.3


From 65cb15a686cedab52abc336d7a400fe3a110ac4c Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Fri, 18 Sep 2009 14:31:48 +1000
Subject: drm/radeon: avivo chips have no separate int bit for display

display interrupts are not enabled via this register, the
DISPLAY_INT bit is a status only to show that other regs
need to be read.

Noticed by Alex Deucher

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/rs600.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index c31bd843925..6af0331cae0 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -272,11 +272,9 @@ int rs600_irq_set(struct radeon_device *rdev)
 		tmp |= RADEON_SW_INT_ENABLE;
 	}
 	if (rdev->irq.crtc_vblank_int[0]) {
-		tmp |= AVIVO_DISPLAY_INT_STATUS;
 		mode_int |= AVIVO_D1MODE_INT_MASK;
 	}
 	if (rdev->irq.crtc_vblank_int[1]) {
-		tmp |= AVIVO_DISPLAY_INT_STATUS;
 		mode_int |= AVIVO_D2MODE_INT_MASK;
 	}
 	WREG32(RADEON_GEN_INT_CNTL, tmp);
-- 
cgit v1.2.3


From 41456df2d45299c2eea5aaabafbaa2430ab9a124 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Wed, 16 Sep 2009 10:15:21 +1000
Subject: drm/radeon/kms: reprogram format in set base.

This should in theory fix the problem with a mode set being required
for adjusting the color depth.

This also adds in the necessary bits to the format tables for
8-bit, though it doesn't work yet.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/atombios_crtc.c      |  5 ++++
 drivers/gpu/drm/radeon/radeon_legacy_crtc.c | 41 +++++++++++++++++++++++++++++
 2 files changed, 46 insertions(+)

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index a7edd0f2ac3..6a015929dee 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -488,6 +488,11 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 	}
 
 	switch (crtc->fb->bits_per_pixel) {
+	case 8:
+		fb_format =
+		    AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
+		    AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
+		break;
 	case 15:
 		fb_format =
 		    AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index 0d29d15aa62..2b997a15fb1 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -341,6 +341,9 @@ void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
 	uint32_t crtc_pitch;
 
 	switch (crtc->fb->bits_per_pixel) {
+	case 8:
+		format = 2;
+		break;
 	case 15:      /*  555 */
 		format = 3;
 		break;
@@ -401,11 +404,33 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 	uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
 	uint32_t crtc_pitch, pitch_pixels;
 	uint32_t tiling_flags;
+	int format;
+	uint32_t gen_cntl_reg, gen_cntl_val;
 
 	DRM_DEBUG("\n");
 
 	radeon_fb = to_radeon_framebuffer(crtc->fb);
 
+	switch (crtc->fb->bits_per_pixel) {
+	case 8:
+		format = 2;
+		break;
+	case 15:      /*  555 */
+		format = 3;
+		break;
+	case 16:      /*  565 */
+		format = 4;
+		break;
+	case 24:      /*  RGB */
+		format = 5;
+		break;
+	case 32:      /* xRGB */
+		format = 6;
+		break;
+	default:
+		return false;
+	}
+
 	obj = radeon_fb->obj;
 	if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) {
 		return -EINVAL;
@@ -458,6 +483,9 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 	} else {
 		int offset = y * pitch_pixels + x;
 		switch (crtc->fb->bits_per_pixel) {
+		case 8:
+			offset *= 1;
+			break;
 		case 15:
 		case 16:
 			offset *= 2;
@@ -476,6 +504,16 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 
 	base &= ~7;
 
+	if (radeon_crtc->crtc_id == 1)
+		gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
+	else
+		gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
+
+	gen_cntl_val = RREG32(gen_cntl_reg);
+	gen_cntl_val &= ~(0xf << 8);
+	gen_cntl_val |= (format << 8);
+	WREG32(gen_cntl_reg, gen_cntl_val);
+
 	crtc_offset = (u32)base;
 
 	WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
@@ -526,6 +564,9 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
 	}
 
 	switch (crtc->fb->bits_per_pixel) {
+	case 8:
+		format = 2;
+		break;
 	case 15:      /*  555 */
 		format = 3;
 		break;
-- 
cgit v1.2.3


From 7cbb355e947b3b426cefd9a3dc0dda3af9f9345a Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Thu, 17 Sep 2009 16:11:31 +1000
Subject: drm/r600/kms: fixup number of loops per blit calculation.

Some people were seeing
*ERROR* radeon: writting more dword to ring than expected
after certain blits, the loops calculation didn't take
into account that we do a separate blit for the remainder
after doing the aligned blits.

Acked-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/r600_blit_kms.c | 21 ++++++++++++++-------
 1 file changed, 14 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index 4f0d181a690..1287f4d3fb2 100644
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -548,10 +548,13 @@ void r600_vb_ib_put(struct radeon_device *rdev)
 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
 {
 	int r;
-	int ring_size;
+	int ring_size, line_size;
 	int max_size;
 	/* loops of emits 64 + fence emit possible */
-	int dwords_per_loop = 76;
+	int dwords_per_loop = 76, num_loops;
+
+	r = r600_vb_ib_get(rdev);
+	WARN_ON(r);
 
 	/* set_render_target emits 2 extra dwords on rv6xx */
 	if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
@@ -559,14 +562,18 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
 
 	/* 8 bpp vs 32 bpp for xfer unit */
 	if (size_bytes & 3)
-		max_size = 8192*8192;
+		line_size = 8192;
 	else
-		max_size = 8192*8192*4;
+		line_size = 8192*4;
 
-	r = r600_vb_ib_get(rdev);
-	WARN_ON(r);
+	max_size = 8192 * line_size;
 
-	ring_size = ((size_bytes + max_size) / max_size) * dwords_per_loop;
+	/* major loops cover the max size transfer */
+	num_loops = ((size_bytes + max_size) / max_size);
+	/* minor loops cover the extra non aligned bits */
+	num_loops += ((size_bytes % line_size) ? 1 : 0);
+	/* calculate number of loops correctly */
+	ring_size = num_loops * dwords_per_loop;
 	/* set default  + shaders */
 	ring_size += 40; /* shaders + def state */
 	ring_size += 3; /* fence emit for VB IB */
-- 
cgit v1.2.3


From 733289c2656c556d5cf36eafa1c8ec77222c359f Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Wed, 16 Sep 2009 15:24:21 +0200
Subject: drm/radeon/kms: don't fail if we fail to init GPU acceleration

Userspace can query if acceleration is working or not true get
info ioctl and could fallback to software if for some reason
kernel failed to initialize KMS. This should allow to give a
working KMS setup in all case (even with non functionning accel).

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/r420.c          |  2 ++
 drivers/gpu/drm/radeon/r600.c          | 33 +++++++++++++------------
 drivers/gpu/drm/radeon/radeon.h        |  1 +
 drivers/gpu/drm/radeon/radeon_device.c | 44 ++++++++++++++--------------------
 drivers/gpu/drm/radeon/radeon_kms.c    |  3 +++
 drivers/gpu/drm/radeon/rv770.c         | 33 +++++++++++++------------
 include/drm/radeon_drm.h               |  1 +
 7 files changed, 61 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 33a25a4377b..2142a478197 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -329,6 +329,7 @@ int r420_init(struct radeon_device *rdev)
 			return r;
 	}
 	r300_set_reg_safe(rdev);
+	rdev->accel_working = true;
 	r = r420_resume(rdev);
 	if (r) {
 		/* Somethings want wront with the accel init stop accel */
@@ -343,6 +344,7 @@ int r420_init(struct radeon_device *rdev)
 			r100_pci_gart_fini(rdev);
 		radeon_agp_fini(rdev);
 		radeon_irq_kms_fini(rdev);
+		rdev->accel_working = false;
 	}
 	return 0;
 }
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 65699e9f202..af430d719e7 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1573,6 +1573,7 @@ int r600_init(struct radeon_device *rdev)
 	if (r)
 		return r;
 
+	rdev->accel_working = true;
 	r = r600_resume(rdev);
 	if (r) {
 		if (rdev->flags & RADEON_IS_AGP) {
@@ -1581,22 +1582,24 @@ int r600_init(struct radeon_device *rdev)
 			rdev->flags &= ~RADEON_IS_AGP;
 			return r600_init(rdev);
 		}
-		return r;
-	}
-	r = radeon_ib_pool_init(rdev);
-	if (r) {
-		DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
-		return r;
+		rdev->accel_working = false;
 	}
-	r = r600_blit_init(rdev);
-	if (r) {
-		DRM_ERROR("radeon: failled blitter (%d).\n", r);
-		return r;
-	}
-	r = radeon_ib_test(rdev);
-	if (r) {
-		DRM_ERROR("radeon: failled testing IB (%d).\n", r);
-			return r;
+	if (rdev->accel_working) {
+		r = radeon_ib_pool_init(rdev);
+		if (r) {
+			DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
+			rdev->accel_working = false;
+		}
+		r = r600_blit_init(rdev);
+		if (r) {
+			DRM_ERROR("radeon: failled blitter (%d).\n", r);
+			rdev->accel_working = false;
+		}
+		r = radeon_ib_test(rdev);
+		if (r) {
+			DRM_ERROR("radeon: failled testing IB (%d).\n", r);
+			rdev->accel_working = false;
+		}
 	}
 	return 0;
 }
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 5bfc05612ac..d7c4efd0892 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -793,6 +793,7 @@ struct radeon_device {
 	bool				suspend;
 	bool				need_dma32;
 	bool				new_init_path;
+	bool				accel_working;
 	struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
 	const struct firmware *me_fw;	/* all family ME firmware */
 	const struct firmware *pfp_fw;	/* r6/700 PFP firmware */
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index db5ae73d628..0b5014c2ae7 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -504,6 +504,7 @@ int radeon_device_init(struct radeon_device *rdev,
 	rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
 	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 	rdev->gpu_lockup = false;
+	rdev->accel_working = false;
 	/* mutex initialization are all done here so we
 	 * can recall function without having locking issues */
 	mutex_init(&rdev->cs_mutex);
@@ -649,35 +650,26 @@ int radeon_device_init(struct radeon_device *rdev,
 		/* Initialize GART (initialize after TTM so we can allocate
 		 * memory through TTM but finalize after TTM) */
 		r = radeon_gart_enable(rdev);
-		if (!r) {
+		if (r)
+			return 0;
 			r = radeon_gem_init(rdev);
-		}
+		if (r)
+			return 0;
 
 		/* 1M ring buffer */
-		if (!r) {
-			r = radeon_cp_init(rdev, 1024 * 1024);
-		}
-		if (!r) {
-			r = radeon_wb_init(rdev);
-			if (r) {
-				DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
-				return r;
-			}
-		}
-		if (!r) {
-			r = radeon_ib_pool_init(rdev);
-			if (r) {
-				DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
-				return r;
-			}
-		}
-		if (!r) {
-			r = radeon_ib_test(rdev);
-			if (r) {
-				DRM_ERROR("radeon: failled testing IB (%d).\n", r);
-				return r;
-			}
-		}
+		r = radeon_cp_init(rdev, 1024 * 1024);
+		if (r)
+			return 0;
+		r = radeon_wb_init(rdev);
+		if (r)
+			DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
+		r = radeon_ib_pool_init(rdev);
+		if (r)
+			return 0;
+		r = radeon_ib_test(rdev);
+		if (r)
+			return 0;
+		rdev->accel_working = true;
 	}
 	DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
 	if (radeon_testing) {
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index ac8505fe2ca..709bd892b3a 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -112,6 +112,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 	case RADEON_INFO_NUM_Z_PIPES:
 		value = rdev->num_z_pipes;
 		break;
+	case RADEON_INFO_ACCEL_WORKING:
+		value = rdev->accel_working;
+		break;
 	default:
 		DRM_DEBUG("Invalid request %d\n", info->request);
 		return -EINVAL;
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 4f2098bc797..be2f86539eb 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -953,6 +953,7 @@ int rv770_init(struct radeon_device *rdev)
 	if (r)
 		return r;
 
+	rdev->accel_working = true;
 	r = rv770_resume(rdev);
 	if (r) {
 		if (rdev->flags & RADEON_IS_AGP) {
@@ -961,22 +962,24 @@ int rv770_init(struct radeon_device *rdev)
 			rdev->flags &= ~RADEON_IS_AGP;
 			return rv770_init(rdev);
 		}
-		return r;
-	}
-	r = r600_blit_init(rdev);
-	if (r) {
-		DRM_ERROR("radeon: failled blitter (%d).\n", r);
-		return r;
+		rdev->accel_working = false;
 	}
-	r = radeon_ib_pool_init(rdev);
-	if (r) {
-		DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
-		return r;
-	}
-	r = radeon_ib_test(rdev);
-	if (r) {
-		DRM_ERROR("radeon: failled testing IB (%d).\n", r);
-			return r;
+	if (rdev->accel_working) {
+		r = r600_blit_init(rdev);
+		if (r) {
+			DRM_ERROR("radeon: failled blitter (%d).\n", r);
+			rdev->accel_working = false;
+		}
+		r = radeon_ib_pool_init(rdev);
+		if (r) {
+			DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
+			rdev->accel_working = false;
+		}
+		r = radeon_ib_test(rdev);
+		if (r) {
+			DRM_ERROR("radeon: failled testing IB (%d).\n", r);
+			rdev->accel_working = false;
+		}
 	}
 	return 0;
 }
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
index 2ba61e18fc8..b67bbd75bd2 100644
--- a/include/drm/radeon_drm.h
+++ b/include/drm/radeon_drm.h
@@ -899,6 +899,7 @@ struct drm_radeon_cs {
 #define RADEON_INFO_DEVICE_ID		0x00
 #define RADEON_INFO_NUM_GB_PIPES	0x01
 #define RADEON_INFO_NUM_Z_PIPES 	0x02
+#define RADEON_INFO_ACCEL_WORKING	0x03
 
 struct drm_radeon_info {
 	uint32_t		request;
-- 
cgit v1.2.3


From c88f9f0c91de55efaece6d9bd9ec920b90244776 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <daenzer@vmware.com>
Date: Tue, 15 Sep 2009 17:09:30 +0200
Subject: drm/radeon/kms: Use surfaces for scanout / cursor byte swapping on
 big endian.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Signed-off-by: Michel Dänzer <daenzer@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/r100.c          |   5 ++
 drivers/gpu/drm/radeon/radeon_fb.c     | 121 +++++----------------------------
 drivers/gpu/drm/radeon/radeon_object.c |   2 +
 include/drm/radeon_drm.h               |  11 +--
 4 files changed, 31 insertions(+), 108 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index fa0fdc1e345..737970b43ae 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -2235,6 +2235,11 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg,
 			flags |= R300_SURF_TILE_MICRO;
 	}
 
+	if (tiling_flags & RADEON_TILING_SWAP_16BIT)
+		flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
+	if (tiling_flags & RADEON_TILING_SWAP_32BIT)
+		flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
+
 	DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
 	WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
 	WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index 19e244a512b..944e4fa78db 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -45,71 +45,9 @@ struct radeon_fb_device {
 	struct radeon_device		*rdev;
 };
 
-static int radeon_fb_check_var(struct fb_var_screeninfo *var,
-			       struct fb_info *info)
-{
-	int ret;
-	ret = drm_fb_helper_check_var(var, info);
-	if (ret)
-		return ret;
-
-	/* big endian override for radeon endian workaround */
-#ifdef __BIG_ENDIAN
-	{
-		int depth;
-		switch (var->bits_per_pixel) {
-		case 16:
-			depth = (var->green.length == 6) ? 16 : 15;
-			break;
-		case 32:
-			depth = (var->transp.length > 0) ? 32 : 24;
-			break;
-		default:
-			depth = var->bits_per_pixel;
-			break;
-		}
-		switch (depth) {
-		case 8:
-			var->red.offset = 0;
-			var->green.offset = 0;
-			var->blue.offset = 0;
-			var->red.length = 8;
-			var->green.length = 8;
-			var->blue.length = 8;
-			var->transp.length = 0;
-			var->transp.offset = 0;
-			break;
-		case 24:
-			var->red.offset = 8;
-			var->green.offset = 16;
-			var->blue.offset = 24;
-			var->red.length = 8;
-			var->green.length = 8;
-			var->blue.length = 8;
-			var->transp.length = 0;
-			var->transp.offset = 0;
-			break;
-		case 32:
-			var->red.offset = 8;
-			var->green.offset = 16;
-			var->blue.offset = 24;
-			var->red.length = 8;
-			var->green.length = 8;
-			var->blue.length = 8;
-			var->transp.length = 8;
-			var->transp.offset = 0;
-			break;
-		default:
-			return -EINVAL;
-		}
-	}
-#endif
-	return 0;
-}
-
 static struct fb_ops radeonfb_ops = {
 	.owner = THIS_MODULE,
-	.fb_check_var = radeon_fb_check_var,
+	.fb_check_var = drm_fb_helper_check_var,
 	.fb_set_par = drm_fb_helper_set_par,
 	.fb_setcolreg = drm_fb_helper_setcolreg,
 	.fb_fillrect = cfb_fillrect,
@@ -206,6 +144,7 @@ int radeonfb_create(struct drm_device *dev,
 	void *fbptr = NULL;
 	unsigned long tmp;
 	bool fb_tiled = false; /* useful for testing */
+	u32 tiling_flags = 0;
 
 	mode_cmd.width = surface_width;
 	mode_cmd.height = surface_height;
@@ -230,7 +169,22 @@ int radeonfb_create(struct drm_device *dev,
 	robj = gobj->driver_private;
 
 	if (fb_tiled)
-		radeon_object_set_tiling_flags(robj, RADEON_TILING_MACRO|RADEON_TILING_SURFACE, mode_cmd.pitch);
+		tiling_flags = RADEON_TILING_MACRO;
+
+#ifdef __BIG_ENDIAN
+	switch (mode_cmd.bpp) {
+	case 32:
+		tiling_flags |= RADEON_TILING_SWAP_32BIT;
+		break;
+	case 16:
+		tiling_flags |= RADEON_TILING_SWAP_16BIT;
+	default:
+		break;
+	}
+#endif
+
+	if (tiling_flags)
+		radeon_object_set_tiling_flags(robj, tiling_flags | RADEON_TILING_SURFACE, mode_cmd.pitch);
 	mutex_lock(&rdev->ddev->struct_mutex);
 	fb = radeon_framebuffer_create(rdev->ddev, &mode_cmd, gobj);
 	if (fb == NULL) {
@@ -313,45 +267,6 @@ int radeonfb_create(struct drm_device *dev,
 	DRM_INFO("fb depth is %d\n", fb->depth);
 	DRM_INFO("   pitch is %d\n", fb->pitch);
 
-#ifdef __BIG_ENDIAN
-	/* fill var sets defaults for this stuff - override
-	   on big endian */
-	switch (fb->depth) {
-	case 8:
-		info->var.red.offset = 0;
-		info->var.green.offset = 0;
-		info->var.blue.offset = 0;
-		info->var.red.length = 8; /* 8bit DAC */
-		info->var.green.length = 8;
-		info->var.blue.length = 8;
-		info->var.transp.offset = 0;
-		info->var.transp.length = 0;
-		break;
-	case 24:
-		info->var.red.offset = 8;
-		info->var.green.offset = 16;
-		info->var.blue.offset = 24;
-		info->var.red.length = 8;
-		info->var.green.length = 8;
-		info->var.blue.length = 8;
-		info->var.transp.offset = 0;
-		info->var.transp.length = 0;
-		break;
-	case 32:
-		info->var.red.offset = 8;
-		info->var.green.offset = 16;
-		info->var.blue.offset = 24;
-		info->var.red.length = 8;
-		info->var.green.length = 8;
-		info->var.blue.length = 8;
-		info->var.transp.offset = 0;
-		info->var.transp.length = 8;
-		break;
-	default:
-		break;
-	}
-#endif
-
 	fb->fbdev = info;
 	rfbdev->rfb = rfb;
 	rfbdev->rdev = rdev;
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 1500d5bc7af..73af463b7a5 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -188,6 +188,7 @@ int radeon_object_kmap(struct radeon_object *robj, void **ptr)
 	if (ptr) {
 		*ptr = robj->kptr;
 	}
+	radeon_object_check_tiling(robj, 0, 0);
 	return 0;
 }
 
@@ -200,6 +201,7 @@ void radeon_object_kunmap(struct radeon_object *robj)
 	}
 	robj->kptr = NULL;
 	spin_unlock(&robj->tobj.lock);
+	radeon_object_check_tiling(robj, 0, 0);
 	ttm_bo_kunmap(&robj->kmap);
 }
 
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
index b67bbd75bd2..3b9932ab175 100644
--- a/include/drm/radeon_drm.h
+++ b/include/drm/radeon_drm.h
@@ -802,11 +802,12 @@ struct drm_radeon_gem_create {
 	uint32_t	flags;
 };
 
-#define RADEON_TILING_MACRO 0x1
-#define RADEON_TILING_MICRO 0x2
-#define RADEON_TILING_SWAP  0x4
-#define RADEON_TILING_SURFACE  0x8 /* this object requires a surface
-				    * when mapped - i.e. front buffer */
+#define RADEON_TILING_MACRO       0x1
+#define RADEON_TILING_MICRO       0x2
+#define RADEON_TILING_SWAP_16BIT  0x4
+#define RADEON_TILING_SWAP_32BIT  0x8
+#define RADEON_TILING_SURFACE     0x10 /* this object requires a surface
+					* when mapped - i.e. front buffer */
 
 struct drm_radeon_gem_set_tiling {
 	uint32_t	handle;
-- 
cgit v1.2.3


From 445282db9e815e7f5e82761c3c971dc9ea988d85 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Wed, 9 Sep 2009 17:40:54 +1000
Subject: drm/radeon/kms: add initial connector properties

This adds:
coherent mode: TMDS coherent mode for atom cards.
scaling mode: LVDS scaler mode
load detect: DAC load detection, DVI-I, VGA, TV
tmds pll: legacy TMDS pll selection
tv standard: TV standard selection.

for later: other TV ones? dvi subconnector selection using std prop

[contains fixes pointed out on dri-devel for atom bios mixups
 by Michel]

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/radeon_atombios.c        |  15 +-
 drivers/gpu/drm/radeon/radeon_combios.c         |  46 +++--
 drivers/gpu/drm/radeon/radeon_connectors.c      | 237 +++++++++++++++++++++---
 drivers/gpu/drm/radeon/radeon_display.c         |  81 ++++++++
 drivers/gpu/drm/radeon/radeon_encoders.c        |  10 +-
 drivers/gpu/drm/radeon/radeon_legacy_encoders.c |  29 ++-
 drivers/gpu/drm/radeon/radeon_mode.h            |  20 +-
 7 files changed, 376 insertions(+), 62 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index cb5efcaf2ba..74374212830 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -719,9 +719,8 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
 	return false;
 }
 
-struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct
-							      radeon_encoder
-							      *encoder)
+bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
+				   struct radeon_encoder_int_tmds *tmds)
 {
 	struct drm_device *dev = encoder->base.dev;
 	struct radeon_device *rdev = dev->dev_private;
@@ -732,7 +731,6 @@ struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct
 	uint8_t frev, crev;
 	uint16_t maxfreq;
 	int i;
-	struct radeon_encoder_int_tmds *tmds = NULL;
 
 	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
 			       &crev, &data_offset);
@@ -742,12 +740,6 @@ struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct
 				       data_offset);
 
 	if (tmds_info) {
-		tmds =
-		    kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
-
-		if (!tmds)
-			return NULL;
-
 		maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
 		for (i = 0; i < 4; i++) {
 			tmds->tmds_pll[i].freq =
@@ -773,8 +765,9 @@ struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct
 				break;
 			}
 		}
+		return true;
 	}
-	return tmds;
+	return false;
 }
 
 union lvds_info {
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index cb60f553233..748265a105b 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -998,48 +998,37 @@ static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
 	{{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},	/* CHIP_RS480 */
 };
 
-static struct radeon_encoder_int_tmds
-    *radeon_legacy_get_tmds_info_from_table(struct radeon_device *rdev)
+bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
+					    struct radeon_encoder_int_tmds *tmds)
 {
+	struct drm_device *dev = encoder->base.dev;
+	struct radeon_device *rdev = dev->dev_private;
 	int i;
-	struct radeon_encoder_int_tmds *tmds = NULL;
-
-	tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
-
-	if (!tmds)
-		return NULL;
 
 	for (i = 0; i < 4; i++) {
 		tmds->tmds_pll[i].value =
-		    default_tmds_pll[rdev->family][i].value;
+			default_tmds_pll[rdev->family][i].value;
 		tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
 	}
 
-	return tmds;
+	return true;
 }
 
-struct radeon_encoder_int_tmds *radeon_combios_get_tmds_info(struct
-							     radeon_encoder
-							     *encoder)
+bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
+					      struct radeon_encoder_int_tmds *tmds)
 {
 	struct drm_device *dev = encoder->base.dev;
 	struct radeon_device *rdev = dev->dev_private;
 	uint16_t tmds_info;
 	int i, n;
 	uint8_t ver;
-	struct radeon_encoder_int_tmds *tmds = NULL;
 
 	if (rdev->bios == NULL)
-		return radeon_legacy_get_tmds_info_from_table(rdev);
+		return false;
 
 	tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
 
 	if (tmds_info) {
-		tmds =
-		    kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
-
-		if (!tmds)
-			return NULL;
 
 		ver = RBIOS8(tmds_info);
 		DRM_INFO("DFP table revision: %d\n", ver);
@@ -1077,6 +1066,23 @@ struct radeon_encoder_int_tmds *radeon_combios_get_tmds_info(struct
 		}
 	} else
 		DRM_INFO("No TMDS info found in BIOS\n");
+	return true;
+}
+
+struct radeon_encoder_int_tmds *radeon_combios_get_tmds_info(struct radeon_encoder *encoder)
+{
+	struct radeon_encoder_int_tmds *tmds = NULL;
+	bool ret;
+
+	tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
+
+	if (!tmds)
+		return NULL;
+
+	ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
+	if (ret == false)
+		radeon_legacy_get_tmds_info_from_table(encoder, tmds);
+
 	return tmds;
 }
 
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 5ee81b6a879..af1d551f1a8 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -39,6 +39,15 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
 				       struct drm_encoder *encoder,
 				       bool connected);
 
+static void radeon_property_change_mode(struct drm_encoder *encoder)
+{
+	struct drm_crtc *crtc = encoder->crtc;
+
+	if (crtc && crtc->enabled) {
+		drm_crtc_helper_set_mode(crtc, &crtc->mode,
+					 crtc->x, crtc->y, crtc->fb);
+	}
+}
 static void
 radeon_connector_update_scratch_regs(struct drm_connector *connector, enum drm_connector_status status)
 {
@@ -78,6 +87,27 @@ radeon_connector_update_scratch_regs(struct drm_connector *connector, enum drm_c
 	}
 }
 
+struct drm_encoder *radeon_find_encoder(struct drm_connector *connector, int encoder_type)
+{
+	struct drm_mode_object *obj;
+	struct drm_encoder *encoder;
+	int i;
+
+	for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
+		if (connector->encoder_ids[i] == 0)
+			break;
+
+		obj = drm_mode_object_find(connector->dev, connector->encoder_ids[i], DRM_MODE_OBJECT_ENCODER);
+		if (!obj)
+			continue;
+
+		encoder = obj_to_encoder(obj);
+		if (encoder->encoder_type == encoder_type)
+			return encoder;
+	}
+	return NULL;
+}
+
 struct drm_encoder *radeon_best_single_encoder(struct drm_connector *connector)
 {
 	int enc_id = connector->encoder_ids[0];
@@ -95,7 +125,6 @@ struct drm_encoder *radeon_best_single_encoder(struct drm_connector *connector)
 	return NULL;
 }
 
-
 /*
  * radeon_connector_analog_encoder_conflict_solve
  * - search for other connectors sharing this encoder
@@ -224,6 +253,89 @@ static void radeon_add_common_modes(struct drm_encoder *encoder, struct drm_conn
 int radeon_connector_set_property(struct drm_connector *connector, struct drm_property *property,
 				  uint64_t val)
 {
+	struct drm_device *dev = connector->dev;
+	struct radeon_device *rdev = dev->dev_private;
+	struct drm_encoder *encoder;
+	struct radeon_encoder *radeon_encoder;
+
+	if (property == rdev->mode_info.coherent_mode_property) {
+		struct radeon_encoder_atom_dig *dig;
+
+		/* need to find digital encoder on connector */
+		encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
+		if (!encoder)
+			return 0;
+
+		radeon_encoder = to_radeon_encoder(encoder);
+
+		if (!radeon_encoder->enc_priv)
+			return 0;
+
+		dig = radeon_encoder->enc_priv;
+		dig->coherent_mode = val ? true : false;
+		radeon_property_change_mode(&radeon_encoder->base);
+	}
+
+	if (property == rdev->mode_info.tv_std_property) {
+		encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TVDAC);
+		if (!encoder) {
+			encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_DAC);
+		}
+
+		if (!encoder)
+			return 0;
+
+		radeon_encoder = to_radeon_encoder(encoder);
+		if (!radeon_encoder->enc_priv)
+			return 0;
+		if (rdev->is_atom_bios) {
+			struct radeon_encoder_atom_dac *dac_int;
+			dac_int = radeon_encoder->enc_priv;
+			dac_int->tv_std = val;
+		} else {
+			struct radeon_encoder_tv_dac *dac_int;
+			dac_int = radeon_encoder->enc_priv;
+			dac_int->tv_std = val;
+		}
+		radeon_property_change_mode(&radeon_encoder->base);
+	}
+
+	if (property == rdev->mode_info.load_detect_property) {
+		struct radeon_connector *radeon_connector =
+			to_radeon_connector(connector);
+
+		if (val == 0)
+			radeon_connector->dac_load_detect = false;
+		else
+			radeon_connector->dac_load_detect = true;
+	}
+
+	if (property == rdev->mode_info.tmds_pll_property) {
+		struct radeon_encoder_int_tmds *tmds = NULL;
+		bool ret = false;
+		/* need to find digital encoder on connector */
+		encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
+		if (!encoder)
+			return 0;
+
+		radeon_encoder = to_radeon_encoder(encoder);
+
+		tmds = radeon_encoder->enc_priv;
+		if (!tmds)
+			return 0;
+
+		if (val == 0) {
+			if (rdev->is_atom_bios)
+				ret = radeon_atombios_get_tmds_info(radeon_encoder, tmds);
+			else
+				ret = radeon_legacy_get_tmds_info_from_combios(radeon_encoder, tmds);
+		}
+		if (val == 1 || ret == false) {
+			radeon_legacy_get_tmds_info_from_table(radeon_encoder, tmds);
+		}
+		radeon_property_change_mode(&radeon_encoder->base);
+	}
+
 	return 0;
 }
 
@@ -320,6 +432,42 @@ static void radeon_connector_destroy(struct drm_connector *connector)
 	kfree(connector);
 }
 
+static int radeon_lvds_set_property(struct drm_connector *connector,
+				    struct drm_property *property,
+				    uint64_t value)
+{
+	struct drm_device *dev = connector->dev;
+	struct radeon_encoder *radeon_encoder;
+	enum radeon_rmx_type rmx_type;
+
+	DRM_DEBUG("\n");
+	if (property != dev->mode_config.scaling_mode_property)
+		return 0;
+
+	if (connector->encoder)
+		radeon_encoder = to_radeon_encoder(connector->encoder);
+	else {
+		struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
+		radeon_encoder = to_radeon_encoder(connector_funcs->best_encoder(connector));
+	}
+
+	switch (value) {
+	case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
+	case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
+	case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
+	default:
+	case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
+	}
+	if (radeon_encoder->rmx_type == rmx_type)
+		return 0;
+
+	radeon_encoder->rmx_type = rmx_type;
+
+	radeon_property_change_mode(&radeon_encoder->base);
+	return 0;
+}
+
+
 struct drm_connector_helper_funcs radeon_lvds_connector_helper_funcs = {
 	.get_modes = radeon_lvds_get_modes,
 	.mode_valid = radeon_lvds_mode_valid,
@@ -331,7 +479,7 @@ struct drm_connector_funcs radeon_lvds_connector_funcs = {
 	.detect = radeon_lvds_detect,
 	.fill_modes = drm_helper_probe_single_connector_modes,
 	.destroy = radeon_connector_destroy,
-	.set_property = radeon_connector_set_property,
+	.set_property = radeon_lvds_set_property,
 };
 
 static int radeon_vga_get_modes(struct drm_connector *connector)
@@ -368,8 +516,10 @@ static enum drm_connector_status radeon_vga_detect(struct drm_connector *connect
 	if (dret)
 		ret = connector_status_connected;
 	else {
-		encoder_funcs = encoder->helper_private;
-		ret = encoder_funcs->detect(encoder, connector);
+		if (radeon_connector->dac_load_detect) {
+			encoder_funcs = encoder->helper_private;
+			ret = encoder_funcs->detect(encoder, connector);
+		}
 	}
 
 	if (ret == connector_status_connected)
@@ -426,7 +576,11 @@ static enum drm_connector_status radeon_tv_detect(struct drm_connector *connecto
 {
 	struct drm_encoder *encoder;
 	struct drm_encoder_helper_funcs *encoder_funcs;
-	int ret;
+	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
+	enum drm_connector_status ret = connector_status_disconnected;
+
+	if (!radeon_connector->dac_load_detect)
+		return ret;
 
 	encoder = radeon_best_single_encoder(connector);
 	if (!encoder)
@@ -510,27 +664,29 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect
 		goto out;
 
 	/* find analog encoder */
-	for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
-		if (connector->encoder_ids[i] == 0)
-			break;
+	if (radeon_connector->dac_load_detect) {
+		for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
+			if (connector->encoder_ids[i] == 0)
+				break;
 
-		obj = drm_mode_object_find(connector->dev,
-					   connector->encoder_ids[i],
-					   DRM_MODE_OBJECT_ENCODER);
-		if (!obj)
-			continue;
+			obj = drm_mode_object_find(connector->dev,
+						   connector->encoder_ids[i],
+						   DRM_MODE_OBJECT_ENCODER);
+			if (!obj)
+				continue;
 
-		encoder = obj_to_encoder(obj);
+			encoder = obj_to_encoder(obj);
 
-		encoder_funcs = encoder->helper_private;
-		if (encoder_funcs->detect) {
-			if (ret != connector_status_connected) {
-				ret = encoder_funcs->detect(encoder, connector);
-				if (ret == connector_status_connected) {
-					radeon_connector->use_digital = false;
+			encoder_funcs = encoder->helper_private;
+			if (encoder_funcs->detect) {
+				if (ret != connector_status_connected) {
+					ret = encoder_funcs->detect(encoder, connector);
+					if (ret == connector_status_connected) {
+						radeon_connector->use_digital = false;
+					}
 				}
+				break;
 			}
-			break;
 		}
 	}
 
@@ -610,6 +766,7 @@ radeon_add_atom_connector(struct drm_device *dev,
 			  bool linkb,
 			  uint32_t igp_lane_info)
 {
+	struct radeon_device *rdev = dev->dev_private;
 	struct drm_connector *connector;
 	struct radeon_connector *radeon_connector;
 	struct radeon_connector_atom_dig *radeon_dig_connector;
@@ -645,6 +802,9 @@ radeon_add_atom_connector(struct drm_device *dev,
 			if (!radeon_connector->ddc_bus)
 				goto failed;
 		}
+		drm_connector_attach_property(&radeon_connector->base,
+					      rdev->mode_info.load_detect_property,
+					      1);
 		break;
 	case DRM_MODE_CONNECTOR_DVIA:
 		drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
@@ -654,6 +814,9 @@ radeon_add_atom_connector(struct drm_device *dev,
 			if (!radeon_connector->ddc_bus)
 				goto failed;
 		}
+		drm_connector_attach_property(&radeon_connector->base,
+					      rdev->mode_info.load_detect_property,
+					      1);
 		break;
 	case DRM_MODE_CONNECTOR_DVII:
 	case DRM_MODE_CONNECTOR_DVID:
@@ -671,6 +834,12 @@ radeon_add_atom_connector(struct drm_device *dev,
 				goto failed;
 		}
 		subpixel_order = SubPixelHorizontalRGB;
+		drm_connector_attach_property(&radeon_connector->base,
+					      rdev->mode_info.coherent_mode_property,
+					      1);
+		drm_connector_attach_property(&radeon_connector->base,
+					      rdev->mode_info.load_detect_property,
+					      1);
 		break;
 	case DRM_MODE_CONNECTOR_HDMIA:
 	case DRM_MODE_CONNECTOR_HDMIB:
@@ -687,6 +856,9 @@ radeon_add_atom_connector(struct drm_device *dev,
 			if (!radeon_connector->ddc_bus)
 				goto failed;
 		}
+		drm_connector_attach_property(&radeon_connector->base,
+					      rdev->mode_info.coherent_mode_property,
+					      1);
 		subpixel_order = SubPixelHorizontalRGB;
 		break;
 	case DRM_MODE_CONNECTOR_DisplayPort:
@@ -712,6 +884,9 @@ radeon_add_atom_connector(struct drm_device *dev,
 			drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type);
 			drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs);
 		}
+		drm_connector_attach_property(&radeon_connector->base,
+					      rdev->mode_info.load_detect_property,
+					      1);
 		break;
 	case DRM_MODE_CONNECTOR_LVDS:
 		radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
@@ -727,6 +902,10 @@ radeon_add_atom_connector(struct drm_device *dev,
 			if (!radeon_connector->ddc_bus)
 				goto failed;
 		}
+		drm_mode_create_scaling_mode_property(dev);
+		drm_connector_attach_property(&radeon_connector->base,
+					      dev->mode_config.scaling_mode_property,
+					      DRM_MODE_SCALE_FULLSCREEN);
 		subpixel_order = SubPixelHorizontalRGB;
 		break;
 	}
@@ -749,6 +928,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
 			    int connector_type,
 			    struct radeon_i2c_bus_rec *i2c_bus)
 {
+	struct radeon_device *rdev = dev->dev_private;
 	struct drm_connector *connector;
 	struct radeon_connector *radeon_connector;
 	uint32_t subpixel_order = SubPixelNone;
@@ -783,6 +963,9 @@ radeon_add_legacy_connector(struct drm_device *dev,
 			if (!radeon_connector->ddc_bus)
 				goto failed;
 		}
+		drm_connector_attach_property(&radeon_connector->base,
+					      rdev->mode_info.load_detect_property,
+					      1);
 		break;
 	case DRM_MODE_CONNECTOR_DVIA:
 		drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
@@ -792,6 +975,9 @@ radeon_add_legacy_connector(struct drm_device *dev,
 			if (!radeon_connector->ddc_bus)
 				goto failed;
 		}
+		drm_connector_attach_property(&radeon_connector->base,
+					      rdev->mode_info.load_detect_property,
+					      1);
 		break;
 	case DRM_MODE_CONNECTOR_DVII:
 	case DRM_MODE_CONNECTOR_DVID:
@@ -801,6 +987,9 @@ radeon_add_legacy_connector(struct drm_device *dev,
 			radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI");
 			if (!radeon_connector->ddc_bus)
 				goto failed;
+			drm_connector_attach_property(&radeon_connector->base,
+						      rdev->mode_info.load_detect_property,
+						      1);
 		}
 		subpixel_order = SubPixelHorizontalRGB;
 		break;
@@ -810,6 +999,9 @@ radeon_add_legacy_connector(struct drm_device *dev,
 		if (radeon_tv == 1) {
 			drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type);
 			drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs);
+			drm_connector_attach_property(&radeon_connector->base,
+						      rdev->mode_info.load_detect_property,
+						      1);
 		}
 		break;
 	case DRM_MODE_CONNECTOR_LVDS:
@@ -820,6 +1012,9 @@ radeon_add_legacy_connector(struct drm_device *dev,
 			if (!radeon_connector->ddc_bus)
 				goto failed;
 		}
+		drm_connector_attach_property(&radeon_connector->base,
+					      dev->mode_config.scaling_mode_property,
+					      DRM_MODE_SCALE_FULLSCREEN);
 		subpixel_order = SubPixelHorizontalRGB;
 		break;
 	}
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 22da85fe5ae..5d8141b1376 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -623,6 +623,83 @@ static const struct drm_mode_config_funcs radeon_mode_funcs = {
 	.fb_changed = radeonfb_probe,
 };
 
+struct drm_prop_enum_list {
+	int type;
+	char *name;
+};
+
+static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
+{	{ 0, "driver" },
+	{ 1, "bios" },
+};
+
+static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
+{	{ TV_STD_NTSC, "ntsc" },
+	{ TV_STD_PAL, "pal" },
+	{ TV_STD_PAL_M, "pal-m" },
+	{ TV_STD_PAL_60, "pal-60" },
+	{ TV_STD_NTSC_J, "ntsc-j" },
+	{ TV_STD_SCART_PAL, "scart-pal" },
+	{ TV_STD_PAL_CN, "pal-cn" },
+	{ TV_STD_SECAM, "secam" },
+};
+
+int radeon_modeset_create_props(struct radeon_device *rdev)
+{
+	int i, sz;
+
+	if (rdev->is_atom_bios) {
+		rdev->mode_info.coherent_mode_property =
+			drm_property_create(rdev->ddev,
+					    DRM_MODE_PROP_RANGE,
+					    "coherent", 2);
+		if (!rdev->mode_info.coherent_mode_property)
+			return -ENOMEM;
+
+		rdev->mode_info.coherent_mode_property->values[0] = 0;
+		rdev->mode_info.coherent_mode_property->values[0] = 1;
+	}
+
+	if (!ASIC_IS_AVIVO(rdev)) {
+		sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
+		rdev->mode_info.tmds_pll_property =
+			drm_property_create(rdev->ddev,
+					    DRM_MODE_PROP_ENUM,
+					    "tmds_pll", sz);
+		for (i = 0; i < sz; i++) {
+			drm_property_add_enum(rdev->mode_info.tmds_pll_property,
+					      i,
+					      radeon_tmds_pll_enum_list[i].type,
+					      radeon_tmds_pll_enum_list[i].name);
+		}
+	}
+
+	rdev->mode_info.load_detect_property =
+		drm_property_create(rdev->ddev,
+				    DRM_MODE_PROP_RANGE,
+				    "load detection", 2);
+	if (!rdev->mode_info.load_detect_property)
+		return -ENOMEM;
+	rdev->mode_info.load_detect_property->values[0] = 0;
+	rdev->mode_info.load_detect_property->values[0] = 1;
+
+	drm_mode_create_scaling_mode_property(rdev->ddev);
+
+	sz = ARRAY_SIZE(radeon_tv_std_enum_list);
+	rdev->mode_info.tv_std_property =
+		drm_property_create(rdev->ddev,
+				    DRM_MODE_PROP_ENUM,
+				    "tv standard", sz);
+	for (i = 0; i < sz; i++) {
+		drm_property_add_enum(rdev->mode_info.tv_std_property,
+				      i,
+				      radeon_tv_std_enum_list[i].type,
+				      radeon_tv_std_enum_list[i].name);
+	}
+
+	return 0;
+}
+
 int radeon_modeset_init(struct radeon_device *rdev)
 {
 	int num_crtc = 2, i;
@@ -643,6 +720,10 @@ int radeon_modeset_init(struct radeon_device *rdev)
 
 	rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
 
+	ret = radeon_modeset_create_props(rdev);
+	if (ret) {
+		return ret;
+	}
 	/* allocate crtcs - TODO single crtc */
 	for (i = 0; i < num_crtc; i++) {
 		radeon_crtc_init(rdev->ddev, i);
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index e274bb13866..621646752cd 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -241,9 +241,12 @@ atombios_dac_setup(struct drm_encoder *encoder, int action)
 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 	DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 	int index = 0, num = 0;
-	/* fixme - fill in enc_priv for atom dac */
+	struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 	enum radeon_tv_std tv_std = TV_STD_NTSC;
 
+	if (dac_info->tv_std)
+		tv_std = dac_info->tv_std;
+
 	memset(&args, 0, sizeof(args));
 
 	switch (radeon_encoder->encoder_id) {
@@ -296,9 +299,12 @@ atombios_tv_setup(struct drm_encoder *encoder, int action)
 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 	TV_ENCODER_CONTROL_PS_ALLOCATION args;
 	int index = 0;
-	/* fixme - fill in enc_priv for atom dac */
+	struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 	enum radeon_tv_std tv_std = TV_STD_NTSC;
 
+	if (dac_info->tv_std)
+		tv_std = dac_info->tv_std;
+
 	memset(&args, 0, sizeof(args));
 
 	index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index 0aaafcd2089..b1547f700d7 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -1271,6 +1271,30 @@ static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
 	.destroy = radeon_enc_destroy,
 };
 
+
+static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
+{
+	struct drm_device *dev = encoder->base.dev;
+	struct radeon_device *rdev = dev->dev_private;
+	struct radeon_encoder_int_tmds *tmds = NULL;
+	bool ret;
+
+	tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
+
+	if (!tmds)
+		return NULL;
+
+	if (rdev->is_atom_bios)
+		ret = radeon_atombios_get_tmds_info(encoder, tmds);
+	else
+		ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
+
+	if (ret == false)
+		radeon_legacy_get_tmds_info_from_table(encoder, tmds);
+
+	return tmds;
+}
+
 void
 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
 {
@@ -1317,10 +1341,7 @@ radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t
 	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 		drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
 		drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
-		if (rdev->is_atom_bios)
-			radeon_encoder->enc_priv = radeon_atombios_get_tmds_info(radeon_encoder);
-		else
-			radeon_encoder->enc_priv = radeon_combios_get_tmds_info(radeon_encoder);
+		radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
 		break;
 	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 		drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index dde13817dee..570a58729da 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -175,6 +175,15 @@ struct radeon_mode_info {
 	enum radeon_connector_table connector_table;
 	bool mode_config_initialized;
 	struct radeon_crtc *crtcs[2];
+	/* DVI-I properties */
+	struct drm_property *coherent_mode_property;
+	/* DAC enable load detect */
+	struct drm_property *load_detect_property;
+	/* TV standard load detect */
+	struct drm_property *tv_std_property;
+	/* legacy TMDS PLL detect */
+	struct drm_property *tmds_pll_property;
+
 };
 
 struct radeon_native_mode {
@@ -304,6 +313,7 @@ struct radeon_connector {
 	   and get modes due to analog/digital/tvencoder */
 	struct edid *edid;
 	void *con_priv;
+	bool dac_load_detect;
 };
 
 struct radeon_framebuffer {
@@ -364,16 +374,18 @@ extern bool radeon_atom_get_clock_info(struct drm_device *dev);
 extern bool radeon_combios_get_clock_info(struct drm_device *dev);
 extern struct radeon_encoder_atom_dig *
 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
-extern struct radeon_encoder_int_tmds *
-radeon_atombios_get_tmds_info(struct radeon_encoder *encoder);
+bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
+				   struct radeon_encoder_int_tmds *tmds);
+bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
+					   struct radeon_encoder_int_tmds *tmds);
+bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
+					    struct radeon_encoder_int_tmds *tmds);
 extern struct radeon_encoder_primary_dac *
 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
 extern struct radeon_encoder_tv_dac *
 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
 extern struct radeon_encoder_lvds *
 radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
-extern struct radeon_encoder_int_tmds *
-radeon_combios_get_tmds_info(struct radeon_encoder *encoder);
 extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
 extern struct radeon_encoder_tv_dac *
 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
-- 
cgit v1.2.3


From 5e6dde7ec2e72f49ff749204efc03a59478d7d34 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <daenzer@vmware.com>
Date: Thu, 17 Sep 2009 09:42:28 +0200
Subject: drm/radeon/kms: Move radeon_get_clock_info() call out of
 radeon_clocks_init().
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Someone on IRC reported problems after commit
95a8f1bf4f48b434c9f839ab5a0773f66b39d7c6 ('drm/radeon/kms: Move
radeon_clocks_init() call back after getting VRAM info.'). And indeed, at least
some ASIC vram_info hooks use the clock info obtained by
radeon_get_clock_info(). So, move that call out of radeon_clocks_init(), ahead
of the radeon_vram_info() call.

[airlied - fixup missing r600/rv770 calls]

Signed-off-by: Michel Dänzer <daenzer@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

drm/radeon/kms: fix get clock info calls for r600/rv770 init path.

These were missed when it got split out.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/r600.c          | 1 +
 drivers/gpu/drm/radeon/radeon_device.c | 4 ++--
 drivers/gpu/drm/radeon/rv770.c         | 1 +
 3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index af430d719e7..1e1cab5ef1e 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1537,6 +1537,7 @@ int r600_init(struct radeon_device *rdev)
 	r600_scratch_init(rdev);
 	/* Initialize surface registers */
 	radeon_surface_init(rdev);
+	radeon_get_clock_info(rdev->ddev);
 	r = radeon_clocks_init(rdev);
 	if (r)
 		return r;
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 0b5014c2ae7..8a40c616b53 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -386,7 +386,6 @@ int radeon_clocks_init(struct radeon_device *rdev)
 {
 	int r;
 
-	radeon_get_clock_info(rdev->ddev);
 	r = radeon_static_clocks_init(rdev->ddev);
 	if (r) {
 		return r;
@@ -617,7 +616,8 @@ int radeon_device_init(struct radeon_device *rdev,
 				radeon_combios_asic_init(rdev->ddev);
 			}
 		}
-		/* Get vram informations */
+		/* Get clock & vram information */
+		radeon_get_clock_info(rdev->ddev);
 		radeon_vram_info(rdev);
 		/* Initialize clocks */
 		r = radeon_clocks_init(rdev);
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index be2f86539eb..8bab6b4f05d 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -917,6 +917,7 @@ int rv770_init(struct radeon_device *rdev)
 	r600_scratch_init(rdev);
 	/* Initialize surface registers */
 	radeon_surface_init(rdev);
+	radeon_get_clock_info(rdev->ddev);
 	r = radeon_clocks_init(rdev);
 	if (r)
 		return r;
-- 
cgit v1.2.3


From 698443d9ec1a33eff65b27b9514e06998bf57eb3 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Fri, 18 Sep 2009 14:16:38 +1000
Subject: drm/radeon/kms: disable VGA rendering engine before taking over VRAM

Before we use any of VRAM, we need to disable the VGA rendering
engine, this render text mode into a graphical framebuffer
for scanout, however it does this on vblank, and can end up
overwriting the GART table and r600 shader objects.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/avivod.h | 9 +++++++++
 drivers/gpu/drm/radeon/r600.c   | 4 ++++
 drivers/gpu/drm/radeon/rs600.c  | 3 +++
 drivers/gpu/drm/radeon/rv770.c  | 4 ++++
 4 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/radeon/avivod.h b/drivers/gpu/drm/radeon/avivod.h
index d4e6e6e4a93..e2b92c445ba 100644
--- a/drivers/gpu/drm/radeon/avivod.h
+++ b/drivers/gpu/drm/radeon/avivod.h
@@ -57,4 +57,13 @@
 #define	VGA_RENDER_CONTROL				0x0300
 #define		VGA_VSTATUS_CNTL_MASK				0x00030000
 
+/* AVIVO disable VGA rendering */
+static inline void radeon_avivo_vga_render_disable(struct radeon_device *rdev)
+{
+	u32 vga_render;
+	vga_render = RREG32(VGA_RENDER_CONTROL);
+	vga_render &= ~VGA_VSTATUS_CNTL_MASK;
+	WREG32(VGA_RENDER_CONTROL, vga_render);
+}
+
 #endif
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 1e1cab5ef1e..aafdb8edc11 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -340,6 +340,10 @@ static void r600_mc_resume(struct radeon_device *rdev)
 	WREG32(D1VGA_CONTROL, d1vga_control);
 	WREG32(D2VGA_CONTROL, d2vga_control);
 	WREG32(VGA_RENDER_CONTROL, vga_render_control);
+
+	/* we need to own VRAM, so turn off the VGA renderer here
+	 * to stop it overwriting our objects */
+	radeon_avivo_vga_render_disable(rdev);
 }
 
 int r600_mc_init(struct radeon_device *rdev)
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 6af0331cae0..0e791e26def 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -28,6 +28,7 @@
 #include "drmP.h"
 #include "radeon_reg.h"
 #include "radeon.h"
+#include "avivod.h"
 
 #include "rs600_reg_safe.h"
 
@@ -197,6 +198,8 @@ void rs600_mc_disable_clients(struct radeon_device *rdev)
 		       "programming pipes. Bad things might happen.\n");
 	}
 
+	radeon_avivo_vga_render_disable(rdev);
+
 	tmp = RREG32(AVIVO_D1VGA_CONTROL);
 	WREG32(AVIVO_D1VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
 	tmp = RREG32(AVIVO_D2VGA_CONTROL);
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 8bab6b4f05d..47427623a84 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -229,6 +229,10 @@ static void rv770_mc_resume(struct radeon_device *rdev)
 	WREG32(D1VGA_CONTROL, d1vga_control);
 	WREG32(D2VGA_CONTROL, d2vga_control);
 	WREG32(VGA_RENDER_CONTROL, vga_render_control);
+
+	/* we need to own VRAM, so turn off the VGA renderer here
+	 * to stop it overwriting our objects */
+	radeon_avivo_vga_render_disable(rdev);
 }
 
 
-- 
cgit v1.2.3


From bc1a631e5104317cc8b4ef7d14adc597f2844003 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Tue, 15 Sep 2009 11:07:52 +1000
Subject: drm/radeon/r600: fix some issues with suspend/resume.

a) don't zero gart table on gart enable
b) move pinning shader object into resume path
c) unpin shader object on suspend
d) set cp ready to false after cp shutdown on suspend.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/r600.c          | 26 +++++++++++++++++++-------
 drivers/gpu/drm/radeon/r600_blit_kms.c | 11 ++---------
 2 files changed, 21 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index aafdb8edc11..9844783cd8d 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -141,8 +141,7 @@ int r600_pcie_gart_enable(struct radeon_device *rdev)
 	r = radeon_gart_table_vram_pin(rdev);
 	if (r)
 		return r;
-	for (i = 0; i < rdev->gart.num_gpu_pages; i++)
-		r600_gart_clear_page(rdev, i);
+
 	/* Setup L2 cache */
 	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 				ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
@@ -1477,6 +1476,14 @@ int r600_resume(struct radeon_device *rdev)
 	if (r)
 		return r;
 	r600_gpu_init(rdev);
+
+	r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
+			      &rdev->r600_blit.shader_gpu_addr);
+	if (r) {
+		DRM_ERROR("failed to pin blit object %d\n", r);
+		return r;
+	}
+
 	r = radeon_ring_init(rdev, rdev->cp.ring_size);
 	if (r)
 		return r;
@@ -1496,7 +1503,11 @@ int r600_suspend(struct radeon_device *rdev)
 {
 	/* FIXME: we should wait for ring to be empty */
 	r600_cp_stop(rdev);
+	rdev->cp.ready = false;
+
 	r600_pcie_gart_disable(rdev);
+	/* unpin shaders bo */
+	radeon_object_unpin(rdev->r600_blit.shader_obj);
 	return 0;
 }
 
@@ -1579,6 +1590,12 @@ int r600_init(struct radeon_device *rdev)
 		return r;
 
 	rdev->accel_working = true;
+	r = r600_blit_init(rdev);
+	if (r) {
+		DRM_ERROR("radeon: failled blitter (%d).\n", r);
+		return r;
+	}
+
 	r = r600_resume(rdev);
 	if (r) {
 		if (rdev->flags & RADEON_IS_AGP) {
@@ -1595,11 +1612,6 @@ int r600_init(struct radeon_device *rdev)
 			DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
 			rdev->accel_working = false;
 		}
-		r = r600_blit_init(rdev);
-		if (r) {
-			DRM_ERROR("radeon: failled blitter (%d).\n", r);
-			rdev->accel_working = false;
-		}
 		r = radeon_ib_test(rdev);
 		if (r) {
 			DRM_ERROR("radeon: failled testing IB (%d).\n", r);
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index 1287f4d3fb2..0a6f4681f46 100644
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -481,15 +481,8 @@ int r600_blit_init(struct radeon_device *rdev)
 		return r;
 	}
 
-	r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
-			     &rdev->r600_blit.shader_gpu_addr);
-	if (r) {
-		DRM_ERROR("failed to pin blit object %d\n", r);
-		return r;
-	}
-
-	DRM_DEBUG("r6xx blit allocated bo @ 0x%16llx %08x vs %08x ps %08x\n",
-		  rdev->r600_blit.shader_gpu_addr, obj_size,
+	DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n",
+		  obj_size,
 		  rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
 
 	r = radeon_object_kmap(rdev->r600_blit.shader_obj, &ptr);
-- 
cgit v1.2.3


From fc30b8efbe1b271eb64e0d4f6cb2a91bb57ee5f3 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Fri, 18 Sep 2009 15:19:37 +1000
Subject: drm/radeon/kms: move around new init path code to avoid posting at
 init

We really don't want to post the card at init, it takes a relatively
long time and isn't required, so split the resume path into
a startup path called by both init/resume and separate resume
entry point to do posting.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/r420.c  | 52 +++++++++++++++++++++++-------------------
 drivers/gpu/drm/radeon/r600.c  | 38 ++++++++++++++++++++++++++++--
 drivers/gpu/drm/radeon/rv770.c | 38 ++++++++++++++++++++++++++++--
 3 files changed, 101 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 2142a478197..9b38956e91c 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -157,31 +157,10 @@ static void r420_clock_resume(struct radeon_device *rdev)
 	WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
 }
 
-int r420_resume(struct radeon_device *rdev)
+static int r420_startup(struct radeon_device *rdev)
 {
 	int r;
 
-	/* Make sur GART are not working */
-	if (rdev->flags & RADEON_IS_PCIE)
-		rv370_pcie_gart_disable(rdev);
-	if (rdev->flags & RADEON_IS_PCI)
-		r100_pci_gart_disable(rdev);
-	/* Resume clock before doing reset */
-	r420_clock_resume(rdev);
-	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
-	if (radeon_gpu_reset(rdev)) {
-		dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
-			RREG32(R_000E40_RBBM_STATUS),
-			RREG32(R_0007C0_CP_STAT));
-	}
-	/* check if cards are posted or not */
-	if (rdev->is_atom_bios) {
-		atom_asic_init(rdev->mode_info.atom_context);
-	} else {
-		radeon_combios_asic_init(rdev->ddev);
-	}
-	/* Resume clock after posting */
-	r420_clock_resume(rdev);
 	r300_mc_program(rdev);
 	/* Initialize GART (initialize after TTM so we can allocate
 	 * memory through TTM but finalize after TTM) */
@@ -217,6 +196,33 @@ int r420_resume(struct radeon_device *rdev)
 	return 0;
 }
 
+int r420_resume(struct radeon_device *rdev)
+{
+	/* Make sur GART are not working */
+	if (rdev->flags & RADEON_IS_PCIE)
+		rv370_pcie_gart_disable(rdev);
+	if (rdev->flags & RADEON_IS_PCI)
+		r100_pci_gart_disable(rdev);
+	/* Resume clock before doing reset */
+	r420_clock_resume(rdev);
+	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
+	if (radeon_gpu_reset(rdev)) {
+		dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
+			RREG32(R_000E40_RBBM_STATUS),
+			RREG32(R_0007C0_CP_STAT));
+	}
+	/* check if cards are posted or not */
+	if (rdev->is_atom_bios) {
+		atom_asic_init(rdev->mode_info.atom_context);
+	} else {
+		radeon_combios_asic_init(rdev->ddev);
+	}
+	/* Resume clock after posting */
+	r420_clock_resume(rdev);
+
+	return r420_startup(rdev);
+}
+
 int r420_suspend(struct radeon_device *rdev)
 {
 	r100_cp_disable(rdev);
@@ -330,7 +336,7 @@ int r420_init(struct radeon_device *rdev)
 	}
 	r300_set_reg_safe(rdev);
 	rdev->accel_working = true;
-	r = r420_resume(rdev);
+	r = r420_startup(rdev);
 	if (r) {
 		/* Somethings want wront with the accel init stop accel */
 		dev_err(rdev->dev, "Disabling GPU acceleration\n");
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 9844783cd8d..5f42fad1919 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1466,7 +1466,7 @@ bool r600_card_posted(struct radeon_device *rdev)
 	return false;
 }
 
-int r600_resume(struct radeon_device *rdev)
+int r600_startup(struct radeon_device *rdev)
 {
 	int r;
 
@@ -1499,6 +1499,40 @@ int r600_resume(struct radeon_device *rdev)
 	return 0;
 }
 
+int r600_resume(struct radeon_device *rdev)
+{
+	int r;
+
+	if (radeon_gpu_reset(rdev)) {
+		/* FIXME: what do we want to do here ? */
+	}
+	/* post card */
+	if (rdev->is_atom_bios) {
+		atom_asic_init(rdev->mode_info.atom_context);
+	} else {
+		radeon_combios_asic_init(rdev->ddev);
+	}
+	/* Initialize clocks */
+	r = radeon_clocks_init(rdev);
+	if (r) {
+		return r;
+	}
+
+	r = r600_startup(rdev);
+	if (r) {
+		DRM_ERROR("r600 startup failed on resume\n");
+		return r;
+	}
+
+	r = radeon_ib_test(rdev);
+	if (r) {
+		DRM_ERROR("radeon: failled testing IB (%d).\n", r);
+		return r;
+	}
+	return r;
+}
+
+
 int r600_suspend(struct radeon_device *rdev)
 {
 	/* FIXME: we should wait for ring to be empty */
@@ -1596,7 +1630,7 @@ int r600_init(struct radeon_device *rdev)
 		return r;
 	}
 
-	r = r600_resume(rdev);
+	r = r600_startup(rdev);
 	if (r) {
 		if (rdev->flags & RADEON_IS_AGP) {
 			/* Retry with disabling AGP */
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 47427623a84..a6399662a84 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -851,7 +851,7 @@ int rv770_gpu_reset(struct radeon_device *rdev)
 	return 0;
 }
 
-int rv770_resume(struct radeon_device *rdev)
+static int rv770_startup(struct radeon_device *rdev)
 {
 	int r;
 
@@ -875,6 +875,40 @@ int rv770_resume(struct radeon_device *rdev)
 	return 0;
 }
 
+int rv770_resume(struct radeon_device *rdev)
+{
+	int r;
+
+	if (radeon_gpu_reset(rdev)) {
+		/* FIXME: what do we want to do here ? */
+	}
+	/* post card */
+	if (rdev->is_atom_bios) {
+		atom_asic_init(rdev->mode_info.atom_context);
+	} else {
+		radeon_combios_asic_init(rdev->ddev);
+	}
+	/* Initialize clocks */
+	r = radeon_clocks_init(rdev);
+	if (r) {
+		return r;
+	}
+
+	r = rv770_startup(rdev);
+	if (r) {
+		DRM_ERROR("r600 startup failed on resume\n");
+		return r;
+	}
+
+	r = radeon_ib_test(rdev);
+	if (r) {
+		DRM_ERROR("radeon: failled testing IB (%d).\n", r);
+		return r;
+	}
+	return r;
+
+}
+
 int rv770_suspend(struct radeon_device *rdev)
 {
 	/* FIXME: we should wait for ring to be empty */
@@ -959,7 +993,7 @@ int rv770_init(struct radeon_device *rdev)
 		return r;
 
 	rdev->accel_working = true;
-	r = rv770_resume(rdev);
+	r = rv770_startup(rdev);
 	if (r) {
 		if (rdev->flags & RADEON_IS_AGP) {
 			/* Retry with disabling AGP */
-- 
cgit v1.2.3


From 9052aa2458fc13788e468a010fa0ed9aa4020380 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Fri, 18 Sep 2009 18:33:07 +1000
Subject: drm/radeon/kms: rv770 blit init called too late.

re-align with r600 code, to init blit earlier.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/rv770.c | 19 ++++++++++++++-----
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index a6399662a84..576ae2f6c71 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -860,6 +860,14 @@ static int rv770_startup(struct radeon_device *rdev)
 	if (r)
 		return r;
 	rv770_gpu_init(rdev);
+
+	r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
+			      &rdev->r600_blit.shader_gpu_addr);
+	if (r) {
+		DRM_ERROR("failed to pin blit object %d\n", r);
+		return r;
+	}
+
 	r = radeon_ring_init(rdev, rdev->cp.ring_size);
 	if (r)
 		return r;
@@ -993,6 +1001,12 @@ int rv770_init(struct radeon_device *rdev)
 		return r;
 
 	rdev->accel_working = true;
+	r = r600_blit_init(rdev);
+	if (r) {
+		DRM_ERROR("radeon: failled blitter (%d).\n", r);
+		rdev->accel_working = false;
+	}
+
 	r = rv770_startup(rdev);
 	if (r) {
 		if (rdev->flags & RADEON_IS_AGP) {
@@ -1004,11 +1018,6 @@ int rv770_init(struct radeon_device *rdev)
 		rdev->accel_working = false;
 	}
 	if (rdev->accel_working) {
-		r = r600_blit_init(rdev);
-		if (r) {
-			DRM_ERROR("radeon: failled blitter (%d).\n", r);
-			rdev->accel_working = false;
-		}
 		r = radeon_ib_pool_init(rdev);
 		if (r) {
 			DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
-- 
cgit v1.2.3


From 4153e584ee02ee59388a89879795fd3653a6b6da Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Fri, 18 Sep 2009 18:41:24 +1000
Subject: drm/radeon/kms: more alignment for rv770.c with r600.c

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/rv770.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 576ae2f6c71..83723f8b94b 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -29,6 +29,7 @@
 #include <linux/platform_device.h>
 #include "drmP.h"
 #include "radeon.h"
+#include "radeon_drm.h"
 #include "rv770d.h"
 #include "avivod.h"
 #include "atom.h"
@@ -921,7 +922,11 @@ int rv770_suspend(struct radeon_device *rdev)
 {
 	/* FIXME: we should wait for ring to be empty */
 	r700_cp_stop(rdev);
+	rdev->cp.ready = false;
 	rv770_pcie_gart_disable(rdev);
+
+	/* unpin shaders bo */
+        radeon_object_unpin(rdev->r600_blit.shader_obj);
 	return 0;
 }
 
-- 
cgit v1.2.3


From fe62e1a45d8b11cf653cba79e244fc07bb9a84b0 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Mon, 21 Sep 2009 14:06:30 +1000
Subject: drm/radeon/kms: more fixes to rv770 suspend/resume path.

This resumes my
RV730PRO (4650)
RV770 (4850)
fine.

Still researching the RV4550 (RV710), resumes without X fine.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/radeon.h |  1 +
 drivers/gpu/drm/radeon/rv770.c  | 21 +++++++++++----------
 2 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index d7c4efd0892..8567f809a42 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1070,5 +1070,6 @@ extern void r600_scratch_init(struct radeon_device *rdev);
 extern int r600_blit_init(struct radeon_device *rdev);
 extern void r600_blit_fini(struct radeon_device *rdev);
 extern int r600_cp_init_microcode(struct radeon_device *rdev);
+extern int r600_gpu_reset(struct radeon_device *rdev);
 
 #endif
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 83723f8b94b..b574c73a510 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -56,8 +56,6 @@ int rv770_pcie_gart_enable(struct radeon_device *rdev)
 	r = radeon_gart_table_vram_pin(rdev);
 	if (r)
 		return r;
-	for (i = 0; i < rdev->gart.num_gpu_pages; i++)
-		r600_gart_clear_page(rdev, i);
 	/* Setup L2 cache */
 	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 				ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
@@ -681,11 +679,11 @@ static void rv770_gpu_init(struct radeon_device *rdev)
 	WREG32(SQ_CONFIG, sq_config);
 
 	WREG32(SQ_GPR_RESOURCE_MGMT_1,  (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
-						    NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
-						    NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
+					 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
+					 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
 
 	WREG32(SQ_GPR_RESOURCE_MGMT_2,  (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
-						    NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
+					 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
 
 	sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
 				   NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
@@ -717,14 +715,14 @@ static void rv770_gpu_init(struct radeon_device *rdev)
 	WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
 
 	WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
-						     FORCE_EOV_MAX_REZ_CNT(255)));
+					  FORCE_EOV_MAX_REZ_CNT(255)));
 
 	if (rdev->family == CHIP_RV710)
 		WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
-							   AUTO_INVLD_EN(ES_AND_GS_AUTO)));
+						AUTO_INVLD_EN(ES_AND_GS_AUTO)));
 	else
 		WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
-							   AUTO_INVLD_EN(ES_AND_GS_AUTO)));
+						AUTO_INVLD_EN(ES_AND_GS_AUTO)));
 
 	switch (rdev->family) {
 	case CHIP_RV770:
@@ -848,14 +846,15 @@ int rv770_mc_init(struct radeon_device *rdev)
 }
 int rv770_gpu_reset(struct radeon_device *rdev)
 {
-	/* FIXME: implement */
-	return 0;
+	/* FIXME: implement any rv770 specific bits */
+	return r600_gpu_reset(rdev);
 }
 
 static int rv770_startup(struct radeon_device *rdev)
 {
 	int r;
 
+	radeon_gpu_reset(rdev);
 	rv770_mc_resume(rdev);
 	r = rv770_pcie_gart_enable(rdev);
 	if (r)
@@ -1039,6 +1038,8 @@ int rv770_init(struct radeon_device *rdev)
 
 void rv770_fini(struct radeon_device *rdev)
 {
+	rv770_suspend(rdev);
+
 	r600_blit_fini(rdev);
 	radeon_ring_fini(rdev);
 	rv770_pcie_gart_fini(rdev);
-- 
cgit v1.2.3


From 18a4cd2e9147dd41234dade56edb62c6222832eb Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@linux.ie>
Date: Mon, 21 Sep 2009 14:15:10 +1000
Subject: drm/radeon/kms: r420 idle after programming GA_ENHANCE

https://bugs.freedesktop.org/show_bug.cgi?id=24041

The idle allows rs690 to startup properly.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/r420.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 9b38956e91c..49a2fdc57d2 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -64,6 +64,11 @@ void r420_pipes_init(struct radeon_device *rdev)
 
 	/* GA_ENHANCE workaround TCL deadlock issue */
 	WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3));
+	/* add idle wait as per freedesktop.org bug 24041 */
+	if (r100_gui_wait_for_idle(rdev)) {
+		printk(KERN_WARNING "Failed to wait GUI idle while "
+		       "programming pipes. Bad things might happen.\n");
+	}
 	/* get max number of pipes */
 	gb_pipe_select = RREG32(0x402C);
 	num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
-- 
cgit v1.2.3


From 5a6e9f9658c853fea8ebbf64cd36287f00a011a2 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Fri, 18 Sep 2009 11:30:30 -0400
Subject: drm/radeon/r600/kms: rv670 is not DCE3

RV670 was using the wrong modesetting code.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/radeon.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 8567f809a42..817af8ecff1 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -108,9 +108,9 @@ enum radeon_family {
 	CHIP_R600,
 	CHIP_RV610,
 	CHIP_RV630,
+	CHIP_RV670,
 	CHIP_RV620,
 	CHIP_RV635,
-	CHIP_RV670,
 	CHIP_RS780,
 	CHIP_RS880,
 	CHIP_RV770,
-- 
cgit v1.2.3


From aadd4e17452d3d5c2269cd2b000b7de7cfb6c79e Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Mon, 21 Sep 2009 14:48:45 +1000
Subject: drm/radeon: some r420s have a CP race with the DMA engine.

This patch makes sure the CP doesn't DMA do VRAM while 2D
is active by inserting a CP resync token.

todo: port to kms.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/radeon/radeon_cp.c  | 23 +++++++++++++++++++++++
 drivers/gpu/drm/radeon/radeon_drv.h |  3 +++
 2 files changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
index fa063d0cfb6..4f7afc79dd8 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -616,6 +616,18 @@ static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 
 	dev_priv->cp_running = 1;
 
+	/* on r420, any DMA from CP to system memory while 2D is active
+	 * can cause a hang.  workaround is to queue a CP RESYNC token
+	 */
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
+		BEGIN_RING(3);
+		OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1));
+		OUT_RING(5); /* scratch reg 5 */
+		OUT_RING(0xdeadbeef);
+		ADVANCE_RING();
+		COMMIT_RING();
+	}
+
 	BEGIN_RING(8);
 	/* isync can only be written through cp on r5xx write it here */
 	OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
@@ -653,8 +665,19 @@ static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
  */
 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 {
+	RING_LOCALS;
 	DRM_DEBUG("\n");
 
+	/* finish the pending CP_RESYNC token */
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
+		BEGIN_RING(2);
+		OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
+		OUT_RING(R300_RB3D_DC_FINISH);
+		ADVANCE_RING();
+		COMMIT_RING();
+		radeon_do_wait_for_idle(dev_priv);
+	}
+
 	RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 
 	dev_priv->cp_running = 0;
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index bc79ad6199b..cb0cfe4b308 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -1099,6 +1099,9 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
 #	define RADEON_CSQ_PRIBM_INDBM		(4 << 28)
 #	define RADEON_CSQ_PRIPIO_INDPIO		(15 << 28)
 
+#define R300_CP_RESYNC_ADDR		0x0778
+#define R300_CP_RESYNC_DATA		0x077c
+
 #define RADEON_AIC_CNTL			0x01d0
 #	define RADEON_PCIGART_TRANSLATE_EN	(1 << 0)
 #	define RS400_MSI_REARM	                (1 << 3)
-- 
cgit v1.2.3


From 28d520433b6375740990ab99d69b0d0067fd656b Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 21 Sep 2009 14:33:58 +1000
Subject: drm/vgaarb: add VGA arbitration support to the drm and kms.

VGA arb requires DRM support for non-kms drivers, to turn on/off
irqs when disabling the mem/io regions.

VGA arb requires KMS support for GPUs where we can turn off VGA
decoding. Currently we know how to do this for intel and radeon
kms drivers, which allows them to be removed from the arbiter.

This patch comes from Fedora rawhide kernel.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/drm_irq.c              | 27 +++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_dma.c        | 20 ++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h        |  1 +
 drivers/gpu/drm/i915/i915_reg.h        |  1 +
 drivers/gpu/drm/i915/intel_display.c   | 17 +++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h       |  1 +
 drivers/gpu/drm/radeon/r100.c          | 14 ++++++++++++++
 drivers/gpu/drm/radeon/r600.c          | 14 ++++++++++++++
 drivers/gpu/drm/radeon/r600d.h         |  1 +
 drivers/gpu/drm/radeon/radeon.h        |  2 ++
 drivers/gpu/drm/radeon/radeon_asic.h   | 12 ++++++++++++
 drivers/gpu/drm/radeon/radeon_device.c | 21 ++++++++++++++++++++-
 include/drm/drmP.h                     |  3 +++
 13 files changed, 133 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index f85aaf21e78..0a6f0b3bdc7 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -37,6 +37,7 @@
 
 #include <linux/interrupt.h>	/* For task queue support */
 
+#include <linux/vgaarb.h>
 /**
  * Get interrupt from bus id.
  *
@@ -171,6 +172,26 @@ err:
 }
 EXPORT_SYMBOL(drm_vblank_init);
 
+static void drm_irq_vgaarb_nokms(void *cookie, bool state)
+{
+	struct drm_device *dev = cookie;
+
+	if (dev->driver->vgaarb_irq) {
+		dev->driver->vgaarb_irq(dev, state);
+		return;
+	}
+
+	if (!dev->irq_enabled)
+		return;
+
+	if (state)
+		dev->driver->irq_uninstall(dev);
+	else {
+		dev->driver->irq_preinstall(dev);
+		dev->driver->irq_postinstall(dev);
+	}
+}
+
 /**
  * Install IRQ handler.
  *
@@ -231,6 +252,9 @@ int drm_irq_install(struct drm_device *dev)
 		return ret;
 	}
 
+	if (!drm_core_check_feature(dev, DRIVER_MODESET))
+		vga_client_register(dev->pdev, (void *)dev, drm_irq_vgaarb_nokms, NULL);
+
 	/* After installing handler */
 	ret = dev->driver->irq_postinstall(dev);
 	if (ret < 0) {
@@ -279,6 +303,9 @@ int drm_irq_uninstall(struct drm_device * dev)
 
 	DRM_DEBUG("irq=%d\n", dev->pdev->irq);
 
+	if (!drm_core_check_feature(dev, DRIVER_MODESET))
+		vga_client_register(dev->pdev, NULL, NULL, NULL);
+
 	dev->driver->irq_uninstall(dev);
 
 	free_irq(dev->pdev->irq, dev);
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 9909505d070..5a49a1867b3 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -33,6 +33,7 @@
 #include "intel_drv.h"
 #include "i915_drm.h"
 #include "i915_drv.h"
+#include <linux/vgaarb.h>
 
 /* Really want an OS-independent resettable timer.  Would like to have
  * this loop run for (eg) 3 sec, but have the timer reset every time
@@ -1012,6 +1013,19 @@ static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
 	return 0;
 }
 
+/* true = enable decode, false = disable decoder */
+static unsigned int i915_vga_set_decode(void *cookie, bool state)
+{
+	struct drm_device *dev = cookie;
+
+	intel_modeset_vga_set_state(dev, state);
+	if (state)
+		return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
+		       VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
+	else
+		return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
+}
+
 static int i915_load_modeset_init(struct drm_device *dev,
 				  unsigned long prealloc_size,
 				  unsigned long agp_size)
@@ -1057,6 +1071,11 @@ static int i915_load_modeset_init(struct drm_device *dev,
 	if (ret)
 		DRM_INFO("failed to find VBIOS tables\n");
 
+	/* if we have > 1 VGA cards, then disable the radeon VGA resources */
+	ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
+	if (ret)
+		goto destroy_ringbuffer;
+
 	ret = drm_irq_install(dev);
 	if (ret)
 		goto destroy_ringbuffer;
@@ -1324,6 +1343,7 @@ int i915_driver_unload(struct drm_device *dev)
 
 	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 		drm_irq_uninstall(dev);
+		vga_client_register(dev->pdev, NULL, NULL, NULL);
 	}
 
 	if (dev->pdev->msi_enabled)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 77ed060b429..a0632f8e76a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -766,6 +766,7 @@ static inline void opregion_enable_asle(struct drm_device *dev) { return; }
 /* modesetting */
 extern void intel_modeset_init(struct drm_device *dev);
 extern void intel_modeset_cleanup(struct drm_device *dev);
+extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
 
 /**
  * Lock test for when it's just for synchronization of ring access.
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e38cd21161c..3f796355346 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -30,6 +30,7 @@
  * fb aperture size and the amount of pre-reserved memory.
  */
 #define INTEL_GMCH_CTRL		0x52
+#define INTEL_GMCH_VGA_DISABLE  (1 << 1)
 #define INTEL_GMCH_ENABLED	0x4
 #define INTEL_GMCH_MEM_MASK	0x1
 #define INTEL_GMCH_MEM_64M	0x1
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 155719ff99d..0227b165290 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3917,3 +3917,20 @@ struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
 
 	return &intel_output->enc;
 }
+
+/*
+ * set vga decode state - true == enable VGA decode
+ */
+int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u16 gmch_ctrl;
+
+	pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
+	if (state)
+		gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
+	else
+		gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
+	pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
+	return 0;
+}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b9e47f1e1cc..3a0004f755d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -178,4 +178,5 @@ extern int intel_framebuffer_create(struct drm_device *dev,
 				    struct drm_mode_fb_cmd *mode_cmd,
 				    struct drm_framebuffer **fb,
 				    struct drm_gem_object *obj);
+
 #endif /* __INTEL_DRV_H__ */
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 737970b43ae..be51c5f7d0f 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1955,6 +1955,20 @@ void r100_vram_init_sizes(struct radeon_device *rdev)
 		rdev->mc.real_vram_size = rdev->mc.aper_size;
 }
 
+void r100_vga_set_state(struct radeon_device *rdev, bool state)
+{
+	uint32_t temp;
+
+	temp = RREG32(RADEON_CONFIG_CNTL);
+	if (state == false) {
+		temp &= ~(1<<8);
+		temp |= (1<<9);
+	} else {
+		temp &= ~(1<<9);
+	}
+	WREG32(RADEON_CONFIG_CNTL, temp);
+}
+
 void r100_vram_info(struct radeon_device *rdev)
 {
 	r100_vram_get_type(rdev);
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 5f42fad1919..eab31c1d6df 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1499,6 +1499,20 @@ int r600_startup(struct radeon_device *rdev)
 	return 0;
 }
 
+void r600_vga_set_state(struct radeon_device *rdev, bool state)
+{
+	uint32_t temp;
+
+	temp = RREG32(CONFIG_CNTL);
+	if (state == false) {
+		temp &= ~(1<<0);
+		temp |= (1<<1);
+	} else {
+		temp &= ~(1<<1);
+	}
+	WREG32(CONFIG_CNTL, temp);
+}
+
 int r600_resume(struct radeon_device *rdev)
 {
 	int r;
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 723295f5928..4a9028a85c9 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -78,6 +78,7 @@
 #define CB_COLOR0_MASK                                  0x28100
 
 #define	CONFIG_MEMSIZE					0x5428
+#define CONFIG_CNTL					0x5424
 #define	CP_STAT						0x8680
 #define	CP_COHER_BASE					0x85F8
 #define	CP_DEBUG					0xC1FC
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 817af8ecff1..c839b608970 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -596,6 +596,7 @@ struct radeon_asic {
 	int (*suspend)(struct radeon_device *rdev);
 	void (*errata)(struct radeon_device *rdev);
 	void (*vram_info)(struct radeon_device *rdev);
+	void (*vga_set_state)(struct radeon_device *rdev, bool state);
 	int (*gpu_reset)(struct radeon_device *rdev);
 	int (*mc_init)(struct radeon_device *rdev);
 	void (*mc_fini)(struct radeon_device *rdev);
@@ -954,6 +955,7 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
 #define radeon_errata(rdev) (rdev)->asic->errata((rdev))
 #define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
+#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
 #define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
 #define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 5f2a9e6f12c..8968f78fa1e 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -47,6 +47,7 @@ uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 void r100_errata(struct radeon_device *rdev);
 void r100_vram_info(struct radeon_device *rdev);
+void r100_vga_set_state(struct radeon_device *rdev, bool state);
 int r100_gpu_reset(struct radeon_device *rdev);
 int r100_mc_init(struct radeon_device *rdev);
 void r100_mc_fini(struct radeon_device *rdev);
@@ -89,6 +90,7 @@ static struct radeon_asic r100_asic = {
 	.init = &r100_init,
 	.errata = &r100_errata,
 	.vram_info = &r100_vram_info,
+	.vga_set_state = &r100_vga_set_state,
 	.gpu_reset = &r100_gpu_reset,
 	.mc_init = &r100_mc_init,
 	.mc_fini = &r100_mc_fini,
@@ -158,6 +160,7 @@ static struct radeon_asic r300_asic = {
 	.init = &r300_init,
 	.errata = &r300_errata,
 	.vram_info = &r300_vram_info,
+	.vga_set_state = &r100_vga_set_state,
 	.gpu_reset = &r300_gpu_reset,
 	.mc_init = &r300_mc_init,
 	.mc_fini = &r300_mc_fini,
@@ -208,6 +211,7 @@ static struct radeon_asic r420_asic = {
 	.resume = &r420_resume,
 	.errata = NULL,
 	.vram_info = NULL,
+	.vga_set_state = &r100_vga_set_state,
 	.gpu_reset = &r300_gpu_reset,
 	.mc_init = NULL,
 	.mc_fini = NULL,
@@ -262,6 +266,7 @@ static struct radeon_asic rs400_asic = {
 	.init = &r300_init,
 	.errata = &rs400_errata,
 	.vram_info = &rs400_vram_info,
+	.vga_set_state = &r100_vga_set_state,
 	.gpu_reset = &r300_gpu_reset,
 	.mc_init = &rs400_mc_init,
 	.mc_fini = &rs400_mc_fini,
@@ -323,6 +328,7 @@ static struct radeon_asic rs600_asic = {
 	.init = &rs600_init,
 	.errata = &rs600_errata,
 	.vram_info = &rs600_vram_info,
+	.vga_set_state = &r100_vga_set_state,
 	.gpu_reset = &r300_gpu_reset,
 	.mc_init = &rs600_mc_init,
 	.mc_fini = &rs600_mc_fini,
@@ -372,6 +378,7 @@ static struct radeon_asic rs690_asic = {
 	.init = &rs600_init,
 	.errata = &rs690_errata,
 	.vram_info = &rs690_vram_info,
+	.vga_set_state = &r100_vga_set_state,
 	.gpu_reset = &r300_gpu_reset,
 	.mc_init = &rs690_mc_init,
 	.mc_fini = &rs690_mc_fini,
@@ -428,6 +435,7 @@ static struct radeon_asic rv515_asic = {
 	.init = &rv515_init,
 	.errata = &rv515_errata,
 	.vram_info = &rv515_vram_info,
+	.vga_set_state = &r100_vga_set_state,
 	.gpu_reset = &rv515_gpu_reset,
 	.mc_init = &rv515_mc_init,
 	.mc_fini = &rv515_mc_fini,
@@ -477,6 +485,7 @@ static struct radeon_asic r520_asic = {
 	.init = &rv515_init,
 	.errata = &r520_errata,
 	.vram_info = &r520_vram_info,
+	.vga_set_state = &r100_vga_set_state,
 	.gpu_reset = &rv515_gpu_reset,
 	.mc_init = &r520_mc_init,
 	.mc_fini = &r520_mc_fini,
@@ -520,6 +529,7 @@ int r600_init(struct radeon_device *rdev);
 void r600_fini(struct radeon_device *rdev);
 int r600_suspend(struct radeon_device *rdev);
 int r600_resume(struct radeon_device *rdev);
+void r600_vga_set_state(struct radeon_device *rdev, bool state);
 int r600_wb_init(struct radeon_device *rdev);
 void r600_wb_fini(struct radeon_device *rdev);
 void r600_cp_commit(struct radeon_device *rdev);
@@ -556,6 +566,7 @@ static struct radeon_asic r600_asic = {
 	.resume = &r600_resume,
 	.cp_commit = &r600_cp_commit,
 	.vram_info = NULL,
+	.vga_set_state = &r600_vga_set_state,
 	.gpu_reset = &r600_gpu_reset,
 	.mc_init = NULL,
 	.mc_fini = NULL,
@@ -606,6 +617,7 @@ static struct radeon_asic rv770_asic = {
 	.cp_commit = &r600_cp_commit,
 	.vram_info = NULL,
 	.gpu_reset = &rv770_gpu_reset,
+	.vga_set_state = &r600_vga_set_state,
 	.mc_init = NULL,
 	.mc_fini = NULL,
 	.wb_init = &r600_wb_init,
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 8a40c616b53..daf5db78095 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -29,6 +29,7 @@
 #include <drm/drmP.h>
 #include <drm/drm_crtc_helper.h>
 #include <drm/radeon_drm.h>
+#include <linux/vgaarb.h>
 #include "radeon_reg.h"
 #include "radeon.h"
 #include "radeon_asic.h"
@@ -480,7 +481,18 @@ void radeon_combios_fini(struct radeon_device *rdev)
 {
 }
 
+/* if we get transitioned to only one device, tak VGA back */
+static unsigned int radeon_vga_set_decode(void *cookie, bool state)
+{
+	struct radeon_device *rdev = cookie;
 
+	radeon_vga_set_state(rdev, state);
+	if (state)
+		return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
+		       VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
+	else
+		return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
+}
 /*
  * Radeon device.
  */
@@ -578,6 +590,13 @@ int radeon_device_init(struct radeon_device *rdev,
 	if (r) {
 		return r;
 	}
+
+	/* if we have > 1 VGA cards, then disable the radeon VGA resources */
+	r = vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
+	if (r) {
+		return -EINVAL;
+	}
+
 	if (!rdev->new_init_path) {
 		/* Setup errata flags */
 		radeon_errata(rdev);
@@ -586,7 +605,6 @@ int radeon_device_init(struct radeon_device *rdev,
 		/* Initialize surface registers */
 		radeon_surface_init(rdev);
 
-		/* TODO: disable VGA need to use VGA request */
 		/* BIOS*/
 		if (!radeon_get_bios(rdev)) {
 			if (ASIC_IS_AVIVO(rdev))
@@ -697,6 +715,7 @@ void radeon_device_fini(struct radeon_device *rdev)
 		radeon_agp_fini(rdev);
 #endif
 		radeon_irq_kms_fini(rdev);
+		vga_client_register(rdev->pdev, NULL, NULL, NULL);
 		radeon_fence_driver_fini(rdev);
 		radeon_clocks_fini(rdev);
 		radeon_object_fini(rdev);
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index eeefb6369e1..c8e64bbadbc 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -810,6 +810,9 @@ struct drm_driver {
 	int (*gem_init_object) (struct drm_gem_object *obj);
 	void (*gem_free_object) (struct drm_gem_object *obj);
 
+	/* vga arb irq handler */
+	void (*vgaarb_irq)(struct drm_device *dev, bool state);
+
 	/* Driver private ops for this object */
 	struct vm_operations_struct *gem_vm_ops;
 
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