From d56ef9c8fd34ed29ffae27598a864b4a9a82521b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 27 Oct 2009 12:11:09 -0400 Subject: drm/radeon/kms/atom: Fix DVO support DVO in 12 bit mode (which seems to be the most common config) requires 2x ppll. Fixes fdo bug 21857. Signed-off-by: Alex Deucher Signed-off-by: Dave Airlie --- drivers/gpu/drm/radeon/atombios_crtc.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index e5a3c301b7a..8516e1b2329 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -483,8 +483,14 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&adjust_pll_args); adjusted_clock = le16_to_cpu(adjust_pll_args.usPixelClock) * 10; - } else - adjusted_clock = mode->clock; + } else { + /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ + if (ASIC_IS_AVIVO(rdev) && + (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) + adjusted_clock = mode->clock * 2; + else + adjusted_clock = mode->clock; + } if (radeon_crtc->crtc_id == 0) pll = &rdev->clock.p1pll; -- cgit v1.2.3