From f339f46b05cfe289024b15a0525c8b61f1426a88 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Tue, 19 May 2009 12:58:13 +0000 Subject: Blackfin: fix detection of cached L2 SRAM Make sure our bfin_addr_dcachable() function flags cached L2 SRAM properly else memory easily goes unflushed when working with DMA. Signed-off-by: Mike Frysinger --- arch/blackfin/include/asm/cacheflush.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h index d7726ab486f..94697f0f6f4 100644 --- a/arch/blackfin/include/asm/cacheflush.h +++ b/arch/blackfin/include/asm/cacheflush.h @@ -108,6 +108,11 @@ static inline int bfin_addr_dcachable(unsigned long addr) addr >= _ramend && addr < physical_mem_end) return 1; +#ifndef CONFIG_BFIN_L2_NOT_CACHED + if (addr >= L2_START && addr < L2_START + L2_LENGTH) + return 1; +#endif + return 0; } -- cgit v1.2.3