From 3ebb5a2b44b02bddd5fbf0f29d71f1df6146c2c3 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Wed, 31 Oct 2007 15:31:48 -0400 Subject: [ARM] add Feroceon support to compressed/head.S The cache replacement policy on the Feroceon core doesn't guarantee that reading through a linear chunk of memory flushes the entire cache. This is however what the default method for ARMv5TE cores does. Although the Feroceon is an ARMv5TE core, it implements the same cache handling instructions as the ARMv5TEJ cores, and must use it for proper cache flush. Signed-off-by: Nicolas Pitre Acked-by: Russell King --- arch/arm/boot/compressed/head.S | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 2073bf08052..3c2c8f2a1dc 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -623,6 +623,12 @@ proc_types: b __armv4_mmu_cache_off b __armv4_mmu_cache_flush + .word 0x56055310 @ Feroceon + .word 0xfffffff0 + b __armv4_mmu_cache_on + b __armv4_mmu_cache_off + b __armv5tej_mmu_cache_flush + @ These match on the architecture ID .word 0x00020000 @ ARMv4T -- cgit v1.2.3