From 41a9e680717e82c745b1ead979ea008e9134ea68 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 13 Dec 2007 09:31:34 +0100 Subject: [ARM] 4710/1: Fix coprocessor 14 usage for debug messages via ICEDCC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to ARM7TDMI Technical Reference Manual (ARM DDI 0210C) writing to the DCC data write register coproc dest registers are 1 and 0, not 0 and 1. ARM920T TRM (ARM DDI 0151C) agrees on that. Cc: Ben Dooks Signed-off-by: Uwe Kleine-König Signed-off-by: Russell King --- arch/arm/boot/compressed/head.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index b9b03eda70e..5cac46a19bb 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -31,7 +31,7 @@ .macro loadsp, rb .endm .macro writeb, ch, rb - mcr p14, 0, \ch, c0, c1, 0 + mcr p14, 0, \ch, c1, c0, 0 .endm #endif -- cgit v1.2.3