From 3f7e5815f4b774270e6506962de37af85aa9c830 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 18 Sep 2006 23:10:26 +0100 Subject: [ARM] 3817/1: iop3xx: split the iop3xx mach into iop32x and iop33x Split the iop3xx mach type into iop32x and iop33x -- split the config symbols, and move the code in the mach-iop3xx directory to the mach-iop32x and mach-iop33x directories. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-iop32x/irq.c | 97 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 arch/arm/mach-iop32x/irq.c (limited to 'arch/arm/mach-iop32x/irq.c') diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c new file mode 100644 index 00000000000..c5f633d2d63 --- /dev/null +++ b/arch/arm/mach-iop32x/irq.c @@ -0,0 +1,97 @@ +/* + * linux/arch/arm/mach-iop32x/irq.c + * + * Generic IOP32X IRQ handling functionality + * + * Author: Rory Bolt + * Copyright (C) 2002 Rory Bolt + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Added IOP3XX chipset and IQ80321 board masking code. + * + */ +#include +#include +#include + +#include +#include +#include + +#include + +static u32 iop321_mask /* = 0 */; + +static inline void intctl_write(u32 val) +{ + asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val)); +} + +static inline void intstr_write(u32 val) +{ + asm volatile("mcr p6,0,%0,c4,c0,0"::"r" (val)); +} + +static void +iop321_irq_mask (unsigned int irq) +{ + + iop321_mask &= ~(1 << (irq - IOP321_IRQ_OFS)); + + intctl_write(iop321_mask); +} + +static void +iop321_irq_unmask (unsigned int irq) +{ + iop321_mask |= (1 << (irq - IOP321_IRQ_OFS)); + + intctl_write(iop321_mask); +} + +struct irq_chip ext_chip = { + .name = "IOP", + .ack = iop321_irq_mask, + .mask = iop321_irq_mask, + .unmask = iop321_irq_unmask, +}; + +void __init iop321_init_irq(void) +{ + unsigned int i, tmp; + + /* Enable access to coprocessor 6 for dealing with IRQs. + * From RMK: + * Basically, the Intel documentation here is poor. It appears that + * you need to set the bit to be able to access the coprocessor from + * SVC mode. Whether that allows access from user space or not is + * unclear. + */ + asm volatile ( + "mrc p15, 0, %0, c15, c1, 0\n\t" + "orr %0, %0, %1\n\t" + "mcr p15, 0, %0, c15, c1, 0\n\t" + /* The action is delayed, so we have to do this: */ + "mrc p15, 0, %0, c15, c1, 0\n\t" + "mov %0, %0\n\t" + "sub pc, pc, #4" + : "=r" (tmp) : "i" (1 << 6) ); + + intctl_write(0); // disable all interrupts + intstr_write(0); // treat all as IRQ + if(machine_is_iq80321() || + machine_is_iq31244()) // all interrupts are inputs to chip + *IOP321_PCIIRSR = 0x0f; + + for(i = IOP321_IRQ_OFS; i < NR_IRQS; i++) + { + set_irq_chip(i, &ext_chip); + set_irq_handler(i, do_level_IRQ); + set_irq_flags(i, IRQF_VALID | IRQF_PROBE); + + } +} + -- cgit v1.2.3 From 7e9740b11529a0a69789fbe92d324f293e6266f6 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 18 Sep 2006 23:17:36 +0100 Subject: [ARM] 3821/1: iop3xx: switch iop32x/iop33x over to shared pci code Switch the iop32x and iop33x code over to the common PCI implementation, and remove the (nearly identical) iop32x and iop33x PCI implementations. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-iop32x/irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-iop32x/irq.c') diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index c5f633d2d63..76f2d561dbc 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c @@ -84,7 +84,7 @@ void __init iop321_init_irq(void) intstr_write(0); // treat all as IRQ if(machine_is_iq80321() || machine_is_iq31244()) // all interrupts are inputs to chip - *IOP321_PCIIRSR = 0x0f; + *IOP3XX_PCIIRSR = 0x0f; for(i = IOP321_IRQ_OFS; i < NR_IRQS; i++) { -- cgit v1.2.3 From 38ce73ebd74a9a1738b73619557f2397c59ba628 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 18 Sep 2006 23:21:38 +0100 Subject: [ARM] 3825/1: iop3xx: use cp6 enable/disable macros Add CP6 enable/disable sequences to the timekeeping code and the IRQ code. As a result, we can't depend on CP6 access being enabled when we enter get_irqnr_and_base anymore, so switch the latter over to using memory-mapped accesses for now. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-iop32x/irq.c | 23 +++++------------------ 1 file changed, 5 insertions(+), 18 deletions(-) (limited to 'arch/arm/mach-iop32x/irq.c') diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index 76f2d561dbc..cdd6943ce76 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c @@ -27,12 +27,16 @@ static u32 iop321_mask /* = 0 */; static inline void intctl_write(u32 val) { + iop3xx_cp6_enable(); asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val)); + iop3xx_cp6_disable(); } static inline void intstr_write(u32 val) { + iop3xx_cp6_enable(); asm volatile("mcr p6,0,%0,c4,c0,0"::"r" (val)); + iop3xx_cp6_disable(); } static void @@ -61,24 +65,7 @@ struct irq_chip ext_chip = { void __init iop321_init_irq(void) { - unsigned int i, tmp; - - /* Enable access to coprocessor 6 for dealing with IRQs. - * From RMK: - * Basically, the Intel documentation here is poor. It appears that - * you need to set the bit to be able to access the coprocessor from - * SVC mode. Whether that allows access from user space or not is - * unclear. - */ - asm volatile ( - "mrc p15, 0, %0, c15, c1, 0\n\t" - "orr %0, %0, %1\n\t" - "mcr p15, 0, %0, c15, c1, 0\n\t" - /* The action is delayed, so we have to do this: */ - "mrc p15, 0, %0, c15, c1, 0\n\t" - "mov %0, %0\n\t" - "sub pc, pc, #4" - : "=r" (tmp) : "i" (1 << 6) ); + unsigned int i; intctl_write(0); // disable all interrupts intstr_write(0); // treat all as IRQ -- cgit v1.2.3 From 610300e8f4f833904096ca1233ffd9dbd73fb11f Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 18 Sep 2006 23:22:24 +0100 Subject: [ARM] 3826/1: iop3xx: remove IOP3??_IRQ_OFS irq offset Get rid of the unused IOP3??_IRQ_OFS irq offset define, start IRQ numbering from zero. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-iop32x/irq.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/mach-iop32x/irq.c') diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index cdd6943ce76..ff049e02f5f 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c @@ -43,7 +43,7 @@ static void iop321_irq_mask (unsigned int irq) { - iop321_mask &= ~(1 << (irq - IOP321_IRQ_OFS)); + iop321_mask &= ~(1 << irq); intctl_write(iop321_mask); } @@ -51,7 +51,7 @@ iop321_irq_mask (unsigned int irq) static void iop321_irq_unmask (unsigned int irq) { - iop321_mask |= (1 << (irq - IOP321_IRQ_OFS)); + iop321_mask |= (1 << irq); intctl_write(iop321_mask); } @@ -73,7 +73,7 @@ void __init iop321_init_irq(void) machine_is_iq31244()) // all interrupts are inputs to chip *IOP3XX_PCIIRSR = 0x0f; - for(i = IOP321_IRQ_OFS; i < NR_IRQS; i++) + for(i = 0; i < NR_IRQS; i++) { set_irq_chip(i, &ext_chip); set_irq_handler(i, do_level_IRQ); -- cgit v1.2.3 From c852ac80440db9b0a47f48578e9c6303078abbc1 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 18 Sep 2006 23:26:25 +0100 Subject: [ARM] 3832/1: iop3xx: coding style cleanup Since the iop32x code isn't iop321-specific, and the iop33x code isn't iop331-specfic, do a s/iop321/iop32x/ and s/iop331/iop33x/, and tidy up the code to conform to the coding style guidelines somewhat better. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-iop32x/irq.c | 54 +++++++++++++++++++--------------------------- 1 file changed, 22 insertions(+), 32 deletions(-) (limited to 'arch/arm/mach-iop32x/irq.c') diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index ff049e02f5f..21294be5a36 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-iop32x/irq.c + * arch/arm/mach-iop32x/irq.c * * Generic IOP32X IRQ handling functionality * @@ -9,76 +9,66 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * - * Added IOP3XX chipset and IQ80321 board masking code. - * */ + #include #include #include - #include #include #include - #include -static u32 iop321_mask /* = 0 */; +static u32 iop32x_mask; static inline void intctl_write(u32 val) { iop3xx_cp6_enable(); - asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val)); + asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); iop3xx_cp6_disable(); } static inline void intstr_write(u32 val) { iop3xx_cp6_enable(); - asm volatile("mcr p6,0,%0,c4,c0,0"::"r" (val)); + asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val)); iop3xx_cp6_disable(); } static void -iop321_irq_mask (unsigned int irq) +iop32x_irq_mask(unsigned int irq) { - - iop321_mask &= ~(1 << irq); - - intctl_write(iop321_mask); + iop32x_mask &= ~(1 << irq); + intctl_write(iop32x_mask); } static void -iop321_irq_unmask (unsigned int irq) +iop32x_irq_unmask(unsigned int irq) { - iop321_mask |= (1 << irq); - - intctl_write(iop321_mask); + iop32x_mask |= 1 << irq; + intctl_write(iop32x_mask); } struct irq_chip ext_chip = { - .name = "IOP", - .ack = iop321_irq_mask, - .mask = iop321_irq_mask, - .unmask = iop321_irq_unmask, + .name = "IOP32x", + .ack = iop32x_irq_mask, + .mask = iop32x_irq_mask, + .unmask = iop32x_irq_unmask, }; -void __init iop321_init_irq(void) +void __init iop32x_init_irq(void) { - unsigned int i; + int i; - intctl_write(0); // disable all interrupts - intstr_write(0); // treat all as IRQ - if(machine_is_iq80321() || - machine_is_iq31244()) // all interrupts are inputs to chip + intctl_write(0); + intstr_write(0); + if (machine_is_iq80321() || + machine_is_iq31244()) *IOP3XX_PCIIRSR = 0x0f; - for(i = 0; i < NR_IRQS; i++) - { + for (i = 0; i < NR_IRQS; i++) { set_irq_chip(i, &ext_chip); set_irq_handler(i, do_level_IRQ); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); - } } - -- cgit v1.2.3 From e60d07b6cd38a7afb85f2cf51aebcb3359b63819 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 21 Sep 2006 02:42:12 +0100 Subject: [ARM] 3850/1: iop3xx: add thecus n2100 support Add support for the Thecus n2100 (80219-based.) Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-iop32x/irq.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-iop32x/irq.c') diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index 21294be5a36..17fb94e6e29 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c @@ -63,7 +63,8 @@ void __init iop32x_init_irq(void) intctl_write(0); intstr_write(0); if (machine_is_iq80321() || - machine_is_iq31244()) + machine_is_iq31244() || + machine_is_n2100()) *IOP3XX_PCIIRSR = 0x0f; for (i = 0; i < NR_IRQS; i++) { -- cgit v1.2.3 From 0c92e830bd39f3e6cf7b151dffecafbdc623496c Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Thu, 21 Sep 2006 02:46:03 +0100 Subject: [ARM] 3851/1: iop3xx: add io-data glantank support Add support for the IO-Data GLAN Tank, from Martin Michlmayr. Signed-off-by: Martin Michlmayr Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-iop32x/irq.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-iop32x/irq.c') diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index 17fb94e6e29..69d6302f40c 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c @@ -62,7 +62,8 @@ void __init iop32x_init_irq(void) intctl_write(0); intstr_write(0); - if (machine_is_iq80321() || + if (machine_is_glantank() || + machine_is_iq80321() || machine_is_iq31244() || machine_is_n2100()) *IOP3XX_PCIIRSR = 0x0f; -- cgit v1.2.3