From c852ac80440db9b0a47f48578e9c6303078abbc1 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 18 Sep 2006 23:26:25 +0100 Subject: [ARM] 3832/1: iop3xx: coding style cleanup Since the iop32x code isn't iop321-specific, and the iop33x code isn't iop331-specfic, do a s/iop321/iop32x/ and s/iop331/iop33x/, and tidy up the code to conform to the coding style guidelines somewhat better. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-iop32x/Kconfig | 9 +++---- arch/arm/mach-iop32x/iq31244.c | 22 ++++++++--------- arch/arm/mach-iop32x/iq80321.c | 14 +++++------ arch/arm/mach-iop32x/irq.c | 54 +++++++++++++++++------------------------- 4 files changed, 45 insertions(+), 54 deletions(-) (limited to 'arch/arm/mach-iop32x') diff --git a/arch/arm/mach-iop32x/Kconfig b/arch/arm/mach-iop32x/Kconfig index ff8a77a8866..d7abfaa525c 100644 --- a/arch/arm/mach-iop32x/Kconfig +++ b/arch/arm/mach-iop32x/Kconfig @@ -8,13 +8,14 @@ config ARCH_IQ80321 bool "Enable support for IQ80321" help Say Y here if you want to run your kernel on the Intel IQ80321 - evaluation kit for the IOP321 chipset. + evaluation kit for the IOP321 processor. config ARCH_IQ31244 - bool "Enable support for IQ31244" + bool "Enable support for EP80219/IQ31244" help - Say Y here if you want to run your kernel on the Intel IQ31244 - evaluation kit for the IOP321 chipset. + Say Y here if you want to run your kernel on the Intel EP80219 + evaluation kit for the Intel 80219 processor (a IOP321 variant) + or the IQ31244 evaluation kit for the IOP321 processor. endmenu diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c index 88b77d32b0a..be4aedfa0de 100644 --- a/arch/arm/mach-iop32x/iq31244.c +++ b/arch/arm/mach-iop32x/iq31244.c @@ -98,16 +98,16 @@ ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) if (slot == 0) { /* CFlash */ - irq = IRQ_IOP321_XINT1; + irq = IRQ_IOP32X_XINT1; } else if (slot == 1) { /* 82551 Pro 100 */ - irq = IRQ_IOP321_XINT0; + irq = IRQ_IOP32X_XINT0; } else if (slot == 2) { /* PCI-X Slot */ - irq = IRQ_IOP321_XINT3; + irq = IRQ_IOP32X_XINT3; } else if (slot == 3) { /* SATA */ - irq = IRQ_IOP321_XINT2; + irq = IRQ_IOP32X_XINT2; } else { printk(KERN_ERR "ep80219_pci_map_irq() called for unknown " "device PCI:%d:%d:%d\n", dev->bus->number, @@ -134,18 +134,18 @@ iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) if (slot == 0) { /* CFlash */ - irq = IRQ_IOP321_XINT1; + irq = IRQ_IOP32X_XINT1; } else if (slot == 1) { /* SATA */ - irq = IRQ_IOP321_XINT2; + irq = IRQ_IOP32X_XINT2; } else if (slot == 2) { /* PCI-X Slot */ - irq = IRQ_IOP321_XINT3; + irq = IRQ_IOP32X_XINT3; } else if (slot == 3) { /* 82546 GigE */ - irq = IRQ_IOP321_XINT0; + irq = IRQ_IOP32X_XINT0; } else { - printk(KERN_ERR "iq31244_pci_map_irq() called for unknown " + printk(KERN_ERR "iq31244_pci_map_irq called for unknown " "device PCI:%d:%d:%d\n", dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); irq = -1; @@ -206,7 +206,7 @@ static struct plat_serial8250_port iq31244_serial_port[] = { { .mapbase = IQ31244_UART, .membase = (char *)IQ31244_UART, - .irq = IRQ_IOP321_XINT1, + .irq = IRQ_IOP32X_XINT1, .flags = UPF_SKIP_TEST, .iotype = UPIO_MEM, .regshift = 0, @@ -287,7 +287,7 @@ MACHINE_START(IQ31244, "Intel IQ31244") .io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc, .boot_params = 0xa0000100, .map_io = iq31244_map_io, - .init_irq = iop321_init_irq, + .init_irq = iop32x_init_irq, .timer = &iq31244_timer, .init_machine = iq31244_init_machine, MACHINE_END diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c index 3c9b8627175..1f37b550188 100644 --- a/arch/arm/mach-iop32x/iq80321.c +++ b/arch/arm/mach-iop32x/iq80321.c @@ -78,19 +78,19 @@ iq80321_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) if ((slot == 2 || slot == 6) && pin == 1) { /* PCI-X Slot INTA */ - irq = IRQ_IOP321_XINT2; + irq = IRQ_IOP32X_XINT2; } else if ((slot == 2 || slot == 6) && pin == 2) { /* PCI-X Slot INTA */ - irq = IRQ_IOP321_XINT3; + irq = IRQ_IOP32X_XINT3; } else if ((slot == 2 || slot == 6) && pin == 3) { /* PCI-X Slot INTA */ - irq = IRQ_IOP321_XINT0; + irq = IRQ_IOP32X_XINT0; } else if ((slot == 2 || slot == 6) && pin == 4) { /* PCI-X Slot INTA */ - irq = IRQ_IOP321_XINT1; + irq = IRQ_IOP32X_XINT1; } else if (slot == 4 || slot == 8) { /* Gig-E */ - irq = IRQ_IOP321_XINT0; + irq = IRQ_IOP32X_XINT0; } else { printk(KERN_ERR "iq80321_pci_map_irq() called for unknown " "device PCI:%d:%d:%d\n", dev->bus->number, @@ -148,7 +148,7 @@ static struct plat_serial8250_port iq80321_serial_port[] = { { .mapbase = IQ80321_UART, .membase = (char *)IQ80321_UART, - .irq = IRQ_IOP321_XINT1, + .irq = IRQ_IOP32X_XINT1, .flags = UPF_SKIP_TEST, .iotype = UPIO_MEM, .regshift = 0, @@ -187,7 +187,7 @@ MACHINE_START(IQ80321, "Intel IQ80321") .io_pg_offst = ((IQ80321_UART) >> 18) & 0xfffc, .boot_params = 0xa0000100, .map_io = iq80321_map_io, - .init_irq = iop321_init_irq, + .init_irq = iop32x_init_irq, .timer = &iq80321_timer, .init_machine = iq80321_init_machine, MACHINE_END diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index ff049e02f5f..21294be5a36 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-iop32x/irq.c + * arch/arm/mach-iop32x/irq.c * * Generic IOP32X IRQ handling functionality * @@ -9,76 +9,66 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * - * Added IOP3XX chipset and IQ80321 board masking code. - * */ + #include #include #include - #include #include #include - #include -static u32 iop321_mask /* = 0 */; +static u32 iop32x_mask; static inline void intctl_write(u32 val) { iop3xx_cp6_enable(); - asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val)); + asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); iop3xx_cp6_disable(); } static inline void intstr_write(u32 val) { iop3xx_cp6_enable(); - asm volatile("mcr p6,0,%0,c4,c0,0"::"r" (val)); + asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val)); iop3xx_cp6_disable(); } static void -iop321_irq_mask (unsigned int irq) +iop32x_irq_mask(unsigned int irq) { - - iop321_mask &= ~(1 << irq); - - intctl_write(iop321_mask); + iop32x_mask &= ~(1 << irq); + intctl_write(iop32x_mask); } static void -iop321_irq_unmask (unsigned int irq) +iop32x_irq_unmask(unsigned int irq) { - iop321_mask |= (1 << irq); - - intctl_write(iop321_mask); + iop32x_mask |= 1 << irq; + intctl_write(iop32x_mask); } struct irq_chip ext_chip = { - .name = "IOP", - .ack = iop321_irq_mask, - .mask = iop321_irq_mask, - .unmask = iop321_irq_unmask, + .name = "IOP32x", + .ack = iop32x_irq_mask, + .mask = iop32x_irq_mask, + .unmask = iop32x_irq_unmask, }; -void __init iop321_init_irq(void) +void __init iop32x_init_irq(void) { - unsigned int i; + int i; - intctl_write(0); // disable all interrupts - intstr_write(0); // treat all as IRQ - if(machine_is_iq80321() || - machine_is_iq31244()) // all interrupts are inputs to chip + intctl_write(0); + intstr_write(0); + if (machine_is_iq80321() || + machine_is_iq31244()) *IOP3XX_PCIIRSR = 0x0f; - for(i = 0; i < NR_IRQS; i++) - { + for (i = 0; i < NR_IRQS; i++) { set_irq_chip(i, &ext_chip); set_irq_handler(i, do_level_IRQ); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); - } } - -- cgit v1.2.3