From 75f251e3d0803b028f3474fdc75be0994c377ab5 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 24 Jul 2009 19:44:01 -0600 Subject: OMAP2/3 SDRC: don't set SDRC_POWER.PWDENA on boot Stop setting SDRC_POWER.PWDENA on boot. There is a nasty erratum (34xx erratum 1.150) that can cause memory corruption if PWDENA is enabled. Based originally on a patch from Samu P. Onkalo . Tested on BeagleBoard rev C2. Signed-off-by: Paul Walmsley Cc: Samu P. Onkalo --- arch/arm/mach-omap2/sram34xx.S | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm/mach-omap2/sram34xx.S') diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index 3aef7448b2a..9c2d0465a83 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -58,7 +58,6 @@ /* SDRC_POWER bit settings */ #define SRFRONIDLEREQ_MASK 0x40 -#define PWDENA_MASK 0x4 /* CM_IDLEST1_CORE bit settings */ #define ST_SDRC_MASK 0x2 @@ -160,7 +159,6 @@ sdram_in_selfrefresh: ldr r12, [r11] @ read the contents of SDRC_POWER mov r9, r12 @ keep a copy of SDRC_POWER bits orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle - bic r12, r12, #PWDENA_MASK @ clear PWDENA str r12, [r11] @ write back to SDRC_POWER register ldr r12, [r11] @ posted-write barrier for SDRC idle_sdrc: -- cgit v1.2.3